US Patent No. 10,251,194

EFFICIENT SCHEDULING IN ASYNCHRONOUS CONTENTION-BASED SYSTEM


Patent No. 10,251,194
Issue Date April 02, 2019
Title Efficient Scheduling In Asynchronous Contention-based System
Inventorship Ioan-Virgil Dragomir, Bucharest (RO)
Alexandru Balmus, Neamt (RO)
Paul Marius Bivol, Bacau (RO)
Assignee NXP USA, Inc., Austin, TX (US)

Claim of US Patent No. 10,251,194

1. An operation scheduler adapted to schedule, in an asynchronous contention-based system, the execution of a standalone non-preemptable operations and of sequences of non-preemptable operations wherein after completion of a first operation of a sequence of the sequences of non-preemptable operations, the execution of a second operation of the sequence of the sequences of non-preemptable operations is suspended until a trigger message associated with the second operation is detected by the asynchronous contention-based system, the operation scheduler comprising:first and second first-in-first-out (FIFO) queues adapted to store asynchronous inputs in a first-in-first-out fashion, wherein the first FIFO queue is adapted to store trigger messages and operation requests, said operation requests comprising instructions associated with the execution of the standalone non-preemptable operations and instructions associated with the sequences of non-preemptable operations, and wherein the second FIFO queue is adapted to store instructions associated with the standalone non-preemptable operations;
a memory adapted to store instructions associated with the sequences of non-preemptable operations;
a message router coupled to the first and second FIFO queues and to the memory; and
an arbitration circuit coupled to the second FIFO queue and to the memory
wherein the message router is adapted to:
route a first instruction associated with a particular standalone non-preemptable operation to the second FIFO queue; and
store a second instruction associated with a first sequence of non-preemptable operations to the memory, wherein the first sequence of non-preemptable operations is suspended while a first trigger message associated with the second instruction has not been received by the first FIFO queue; and
wherein the arbitration circuit is further adapted to:
determine whether the first instruction was routed to the second FIFO queue before the first trigger message was received by the first FIFO queue;
schedule the execution of the first instruction when the first instruction was routed to the second FIFO queue before the first trigger message was received by the first FIFO queue; and
schedule the execution of the second instruction when the first instruction was not routed to the second FIFO queue before the first trigger message was received by the first FIFO queue.