US Patent No. 10,219,339


Patent No. 10,219,339
Issue Date February 26, 2019
Title Current Correction Techniques For Accurate High Current Short Channel Driver
Inventorship Bret Ross Howe, Irvine, CA (US)
Assignee IXYS, LLC, Milpitas, CA (US)

Claim of US Patent No. 10,219,339

1. An apparatus comprising:an output node;
a ground node;
a bias current node;
a replica node;
a summing node;
a current driver transistor;
a summing node reference current generator circuit, wherein the summing node reference current generator circuit generates a summing node reference current on the summing node;
voltage detector circuit, wherein during an operating mode the voltage detector circuit detects an output voltage on the output node and generates a replica voltage on the replica node;
an Output Model Current Mirror (OMCM) circuit, wherein the OMCM circuit receives the replica voltage generated by the voltage detector circuit and generates an output model current, and wherein the output model current is supplied onto the summing node;
a Corrected Current Mirror (CCM) circuit that generates a scaled corrected current, wherein the CCM circuit generates the scaled corrected current by scaling a corrected current, and wherein the corrected current is a difference between the summing node reference current and the output model current; and
a Corrected Current to Gate Voltage Converter (CCGVC) circuit, wherein the CCGVC circuit converts the scaled corrected current into a gate voltage that is supplied onto the gate of the current driver transistor.