US Patent No. 10,194,537

MINIMIZING PRINTED CIRCUIT BOARD WARPAGE


Patent No. 10,194,537
Issue Date January 29, 2019
Title Minimizing Printed Circuit Board Warpage
Inventorship Bruce J. Chamberlin, Vestal, NY (US)
Joseph Kuczynski, Rochester, MN (US)
Paula M. Nixa, Rochester, MN (US)
Assignee International Business Machines Corporation, Armonk, NY (US)

Claim of US Patent No. 10,194,537

1. A method of fabricating an asymmetric printed circuit board with reduced warpage, the method comprising:creating a stack of layers, wherein the stack of layers includes a top layer and a bottom layer;
determining a first area and a second area of the stack of layers;
determining a first target coefficient of thermal expansion for the first area and a second target coefficient of thermal expansion for the second area based, at least in part, on an amount of heat that is predicted to be produced by at least one circuit component;
identifying, in the stack of layers, a portion of the first area and a portion of the second area that include resin; and
generating the asymmetric printed circuit board, at least in part, by differentially applying at least one of (i) electromagnetic radiation and (ii) pressure to each of (a) the portion of the first area based on the first target coefficient of thermal expansion and (b) the portion of the second area based on the second target coefficient of thermal expansion, thereby increasing curing of resin included in the portion of the first area and the portion of the second area, wherein (i) a degree of curing in the first area is different than a degree of curing in the second area, and (ii) at least one of an amount of electromagnetic radiation and an amount of pressure applied to areas that include resin are based, at least in part, on at least one of a recommended set point for the resin, dwell time for the resin, ramp rate for the resin, and warpage predicted by computer modeling.