1. A system, comprising:a device adapted to connect to a bus;
wherein the device is adapted to implement a single logical slave as a bus participant in a first mode and at least two logical slaves as bus participants in a second mode;
wherein the first mode is a standard addressing mode, and the second mode is an expanded address mode;
wherein the device includes a reversing logic adapted to shift the device from the first mode to the second mode to switch the device from a standard address to an expanded address to implement the at least two logical slaves in a single addressing process, the at least two logical slaves being made available as bus participants immediately after the addressing;
wherein the at least two logical slaves are operable in the second mode in the expanded address mode in respective cycles by an address assigned by a standard addressing signal; and
wherein the at least two logical slaves have profiles that differ from each other.