US Patent No. 10,185,672


Patent No. 10,185,672
Issue Date January 22, 2019
Title Multiprocessor System With Improved Secondary Interconnection Network
Inventorship Carl S. Dobbs, Austin, TX (US)
Michael R. Trocino, Austin, TX (US)
Assignee Coherent Logix, Incorporated, Austin, TX (US)

Claim of US Patent No. 10,185,672

1. A multichip system, comprising:a first integrated circuit chip including:
a first plurality of processors;
a plurality of memories;
a first plurality of routers coupled together to form a first primary interconnection network;
a plurality of interface units coupled together to form a secondary interconnection network, wherein each interface unit is coupled to a respective processor of the first plurality of processors and a respective router of the first plurality of routers;
a bus controller coupled to at least a particular interface unit of the plurality of interface units;
wherein the first plurality of processors, the plurality of memories, and the first plurality of routers are coupled together in an interspersed fashion; and
a second integrated circuit chip coupled to the first integrated circuit chip via an inter-chip interconnect, wherein the second integrated circuit chip includes a second plurality of processors;
wherein a particular processor of the second plurality of processors is configured to send first data, via the inter-chip interconnect, to the bus controller; and
wherein the bus controller is configured to:
relay the first data to the particular interface unit; and
arbitrate requests for access to the particular interface unit from a plurality of circuit blocks.