US Patent No. 10,169,523

TIMING CONSTRAINTS FORMULATION FOR HIGHLY REPLICATED DESIGN MODULES


Patent No. 10,169,523
Issue Date January 01, 2019
Title Timing Constraints Formulation For Highly Replicated Design Modules
Inventorship Chithra Ravindranath, Bangalore (IN)
Sourav Saha, Kolkata (IN)
Rajashree Srinidhi, Bangalore (IN)
Assignee International Business Machines Corporation, Armonk, NY (US)

Claim of US Patent No. 10,169,523

1. A method for managing time constraints in a circuit, the method comprising:creating an initial placement design of blocks of macros in a circuit based on a weighted combination of a micro-architectural requirement, a critical path timing requirement, and a connection density requirement;
determining, by one or more processors, whether a first location-based criteria is met, wherein the first location-based criteria comprises a first predefined threshold;
in response to determining that the first location-based criteria is met, initiating, by one or more processors, a first checkpoint procedure, the first checkpoint procedure comprising a pin list filtering to generate a first shortened pin list;
performing an intermediate placement of blocks of macros in the circuit if the first predefined threshold is not met;
determining, by one or more processors, whether a second timing-based criteria is met, wherein the second timing-based criteria comprises a second predefined threshold;
in response to determining that the second timing-based criteria is met, initiating, by one or more processors, a second checkpoint procedure, the second checkpoint procedure comprising a pin list filtering to generate a second shortened pin list; and
performing design iterations, by one or more processors, using at least the first shortened pin list or the second shortened pin list instead of an unfiltered pin list to reach a final optimized stage.