US Patent No. 10,169,518


Patent No. 10,169,518
Issue Date January 01, 2019
Title Methods For Delaying Register Reset For Retimed Circuits
Inventorship Mahesh A. Iyer, Fremont, CA (US)
Assignee Intel Corporation, Santa Clara, CA (US)

Claim of US Patent No. 10,169,518

1. A method of operating an integrated circuit design tool implemented on computing equipment, comprising:receiving a circuit design that includes a plurality of registers that are resettable using a first reset sequence;
performing a first register move operation on the circuit design to move a first register in the plurality of registers across a first circuit element in the circuit design;
updating a first counter value associated with the first circuit element for a clock domain; and
generating a second reset sequence by delaying the first reset sequence based on the first counter value for the clock domain, wherein the second reset sequence is at least associated with resetting the moved first register to a reset state.