1. A method of performing timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence, the method comprising:generating a timing graph representation of the integrated circuit design, wherein the timing graph includes nodes interconnected by edges;
loading timing abstracts representing the nodes of the timing graph;
obtaining, using a processor, a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks, wherein each timing tag indicates a clock domain;
applying a design change;
determining, using the processor, one or more modified timing tags that are added or changed as a result of the design change;
processing the timing constraints associated with the modified timing tags as callbacks;
re-computing the timing result; and
providing the integrated circuit design to obtain a physical implementation based on the timing analysis.