US Patent No. 10,143,092

CIRCUIT SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME


Patent No. 10,143,092
Issue Date November 27, 2018
Title Circuit Substrate And Method For Manufacturing The Same
Inventorship Yukinobu Mikado, Ogaki (JP)
Mitsuhiro Tomikawa, Ogaki (JP)
Koji Asano, Ogaki (JP)
Kotaro Takagi, Ogaki (JP)
Assignee IBIDEN CO., LTD., Ogaki (JP)

Claim of US Patent No. 10,143,092

1. A circuit substrate, comprising:a core substrate comprising resin material and having a cavity formed such that the cavity is penetrating through the core substrate;
a metal block accommodated in the cavity of the core substrate and having a thickness greater than a thickness of the core substrate such that the metal block has a first surface and a second surface protruding from a first side and a second side of the core substrate respectively;
a first build-up layer laminated on the first side of the core substrate and comprising a plurality of insulating resin layers such that the first build-up layer is covering the first surface of the metal block in the cavity of the core substrate from the first side, and a first via conductor structure formed in an innermost portion of the first build-up layer such that the first via conductor structure is connected to the first surface of the metal block; and
a second build-up layer laminated on the second side of the core substrate on an opposite side with respect to the first side and comprising a plurality of insulating resin layers such that the second build-up layer is covering the second surface of the metal block in the cavity of the core substrate from the second side, and a second via conductor structure formed in an innermost portion of the second build-up layer such that the second via conductor structure is connected to the second surface of the metal block,
wherein the first build-up layer comprises an electronic component mounting structure formed on an outermost portion of the first build-up layer such that the electronic component mounting structure mounts an electronic component on the first build-up layer, the metal block is formed such that the first and second surfaces of the metal block comprise roughened surfaces in contact with respective insulating resin layers in the first and second build-up layers and that the roughened surface of the first surface has a surface roughness in a range of 1.0 ?m to 3.0 ?m in an arithmetic average roughness which is different from a surface roughness of the roughened surface of the second surface in a range of 0.1 ?m to 1.0 ?m in an arithmetic average roughness, and the first and second via conductor structures are formed such that the first via conductor structure comprises a plurality of via conductors which is greater in number than a plurality of via conductors forming the second via conductor structure.