19. A system comprising:a readout circuit, said readout circuit further comprising:
a front end comprising:
a current splitter configured between an input signal source and at least one integrator, said current splitter providing an output signal to said at least one integrator;
a plurality of bipolar transistors configured to control said current splitter scaling factors to minimize split ratio errors;
a range selection logic, a multiplexor and at least one voltage buffer which are configured to store an integration performed by said at least one integrator for a desired gain range in a capacitor storage array;
a sample switch opened at an end of an integration period and configured between a cascode transistor and an integrator capacitor;
a cascode transistor separating said sample switch and said at least one integrator; and
a back end configured to read out said capacitor storage array.