US Patent No. 10,015,885

PRINTED CIRCUIT BOARD, AND METHOD FOR MANUFACTURING SAME


Patent No. 10,015,885
Issue Date July 03, 2018
Title Printed Circuit Board, And Method For Manufacturing Same
Inventorship Won Suk Jung, Seoul (KR)
Yun Ho An, Seoul (KR)
Sang Myung Lee, Seoul (KR)
Joon Wook Han, Seoul (KR)
Assignee LG INNOTEK CO., LTD., Seoul (KR)

Claim of US Patent No. 10,015,885

1. A printed circuit board, comprising: a first element and a second element; a first base substrate including an embedding part in which the first element is embedded and a cavity into which the second element is mounted; a second base substrate bonded to one surface of the first base substrate and including a first via for the second element; an adhesive insulating layer formed between the first base substrate and the second base substrate, wherein the first base substrate includes: a dummy core layer on the adhesive insulating layer, and including the embedding part and a first part of the cavity, a first insulating layer on the dummy core layer to cover the embedding part and an upper part of the dummy core layer, and including a second part of the cavity, a first circuit layer on the first insulating layer; a second via for the first element, the second via for the first element passing through the first insulating layer to connect the first element and the first circuit layer, wherein the adhesive insulating layer includes a third part of the cavity, wherein the second base substrate includes: a second insulating layer below the adhesive insulating layer, a second circuit layer below the second insulating layer, and the first via for the second element, the first via for the second element passing through the second insulating layer to connect the second element and the second circuit layer, wherein a lower surface of the first element is exposed through a lower surface of the dummy core layer and is in direct physical contact with an upper surface of the adhesive insulating layer, wherein a lower surface of the second element is positioned at a lower level than the lower surface of the first element in the cavity, wherein an upper surface of the second element is positioned at a higher level than an upper surface of the first element in the cavity, wherein the first element is an image sensor or a photo sensor, and the second element is a controller chip, wherein the first element is embedded in the embedding part by the first insulating layer, wherein the second element is exposed to an outside by the cavity, wherein a terminal of the first element is disposed toward an upper surface of the first insulating layer, wherein a terminal of the second element is disposed toward an upper surface of the second insulating layer, wherein the first via is neither vertically nor horizontally overlapped with the second via, wherein the first via is vertically overlapped with the second element, wherein the second via is vertically overlapped with the first element, wherein a first solder resist layer is formed on the first insulating layer, wherein a second solder resist layer is formed below the second insulating layer, wherein the first solder resist layer does not include an opening to expose the second via, and wherein the second solder resist layer does not include an opening to expose the first via.