US Pat. No. 11,069,849

SHADOW MASK SIDEWALL TUNNEL JUNCTION FOR QUANTUM COMPUTING

INTERNATIONAL BUSINESS MA...


1. A tunnel junction device comprising a Josephson tunnel junction device, the tunnel junction device comprising:a first conducting layer having a height dimension greater than a width dimension;
an oxide layer formed on the first conducting layer; and
a second conducting layer formed on the oxide layer covering a top surface and a side portion of the first conducting layer, such that an angled portion of the second conducting layer is positioned on the top surface of the first conducting layer, the angled portion having a surface that is neither parallel nor perpendicular to the top surface, a third conducting layer interposed between the angled portion of the second conducting layer and the top surface of the first conducting layer.

US Pat. No. 11,069,848

METHODS FOR FABRICATION, MANUFACTURE AND PRODUCTION OF AN AUTONOMOUS ELECTRICAL POWER SOURCE

Face International Corpor...


1. A method for forming an electrical power source element, comprising:forming a first conductor of a first conductive material on a support surface, the first conductor having a first facing surface facing away from the support surface and a second surface opposite the first surface facing the support surface;
surface conditioning the first facing surface of the first conductor to have a comparatively low work function value measured in electron volts (eV);
providing a second conductor formed of a second conductive material, the second conductor having a first facing surface and a second surface opposite the first facing surface, the first facing surface of the second conductor having a work function value in a range of at least 1.0 eV greater than the work function value of the surface conditioned first facing surface of the first conductor; and
arranging the second conductor such that the first facing surface of the second conductor faces the first facing surface of the first conductor, the second conductor being arranged to form a gap between the first facing surface of the first conductor and the first facing surface of the second conductor, the gap being in a range of 200 angstroms or less in thickness, such that a resultant structure of the electrical power source element promotes electron migration between said first conductor and said second conductor through quantum tunneling effects, causing the electrical power source element to generate an electric potential between the first conductor and the second conductor at any temperature above absolute zero.

US Pat. No. 11,069,847

THERMOELECTRIC MODULE

Hyundai Motor Company, S...


1. A thermoelectric module, comprising:a plurality of first thermoelectric elements;
a plurality of second thermoelectric elements, each of the plurality of second thermoelectric elements alternating with each of the plurality of first thermoelectric elements to form at least three pairs of alternating first and second thermoelectric elements;
a plurality of upper electrodes including at least two first upper electrode plates each individually coupled to an upper surface of a first thermoelectric element of a first pair of alternating first and second thermoelectric elements and a first thermoelectric element of a second pair of alternating first and second thermoelectric elements; at least two second upper electrode plates each individually coupled to an upper surface of a second thermoelectric element of the first pair and a second thermoelectric element of the second pair; and a third upper electrode plate coupled to upper surfaces of a first thermoelectric element and a second thermoelectric element of a third pair of alternating first and second thermoelectric elements;
a plurality of lower electrodes including at least two first lower electrode plates each individually coupled to a lower surface of the first thermoelectric element of the first pair and the third pair; at least two second lower electrode plates each individually coupled to a lower surface of the second thermoelectric element of the second pair and the third pair; and a third lower electrode plate coupled to lower surfaces of the second thermoelectric element of the first pair and the first thermoelectric element of the second pair; and
a pivot unit including an upper pivot unit pivotally connecting one of the at least two first upper electrode plates to an adjacent one of the at least two second upper electrode plates, and a lower pivot unit pivotally connecting one of the at least two first lower electrode plates to an adjacent one of the at least two second lower electrode plates,
wherein the upper pivot unit and the lower pivot unit are disposed at upper portions of the plurality of first thermoelectric elements and the plurality of second thermoelectric elements and at lower portions of the plurality of first thermoelectric elements and the plurality of second thermoelectric elements, respectively, along a longitudinal direction of the thermoelectric module.

US Pat. No. 11,069,846

ULTRAVIOLET RAY EMITTING DEVICE HAVING MAXIMIZED ELECTRODE AREA FOR IMPROVED HEAT DISSIPATION

SEOUL VIOSYS CO., LTD., ...


1. A light emitting device comprising:a first body comprising a base and first to third conductive patterns disposed on the base, the first body having a plurality of element mounting regions;
a plurality of light emitting elements disposed in the plurality of element mounting regions of the first body, the plurality of element mounting regions including a first element mounting region and a second element mounting region;
a second body comprising a cavity and first through-holes disposed in the cavity; and
a cover disposed to cover the cavity of the second body,
wherein the first conductive pattern is electrically connected to at least two of the plurality of light emitting elements and has a first side, a second side shorter than the first side, a third side parallel to the first side and longer than the second side, and a fourth side parallel to the second side, the first, conductive pattern having an elongated shape, the at least two of the plurality of light emitting elements being connected to each other in series,
the at least two of the plurality of the light emitting elements include a first light emitting element that is disposed in the first element mounting region overlapping with the second conductive pattern and a second light emitting element that is disposed in the second element mounting region overlapping with the third conductive pattern,
the second conductive pattern and the third conductive pattern are disposed to surround the first conductive pattern such that the second conductive pattern extends along the first side and the second side of the first conductive pattern and the third conductive pattern extends along the third side and the fourth side of the first conductive pattern,
each of the second conductive pattern and the third conductive pattern comprises a pad electrode region,
the first to third conductive patterns occupy at least 80% of a surface area of an upper surface of the base and are separated from one another by a distance of 200 ?m to 2,400 ?m,
the second body is arranged over the first body such that the plurality of the light emitting elements are exposed by the first through holes, respectively,
uppermost ends of sidewalls of the first through holes are placed higher than uppermost ends of the plurality of the light emitting elements,
the cover is configured to contact with the uppermost ends of the sidewalls of the first through holes, and
a lower surface of the cover is spaced apart from upper surfaces of the plurality of the light emitting elements.

US Pat. No. 11,069,845

LIGHT EMITTING DEVICE

SAMSUNG ELECTRONICS CO., ...


1. A light emitting device, comprising:a substrate extending in a first direction and a second direction;
first through fourth light emitting structures spaced apart from each other in the first and second directions and arranged in a matrix form on the substrate;
a plurality of first interconnection layer structures connecting the first light emitting structure to the second light emitting structure, wherein the plurality of first interconnection layer structures are conductive structures horizontally separated from and discontinuous in relation to each other;
a second interconnection layer structure connecting the second light emitting structure to the third light emitting structure;
a plurality of third interconnection layer structures connecting the third light emitting structure to the fourth light emitting structure, wherein the plurality of third interconnection layer structures are conductive structures horizontally separated from and discontinuous in relation to each other,
wherein:the plurality of third interconnection layer structures are horizontally separated from and discontinuous in relation to the plurality of first interconnection layer structures,

the plurality of first interconnection layer structures each extend lengthwise in the second direction;the plurality of third interconnection layer structures each extend lengthwise in the second direction;
the second interconnection layer structure is a conductive structure horizontally separated from and discontinuous in relation to the plurality of first interconnection layer structures and the plurality of third interconnection layer structures and extending lengthwise in the first direction;
each of the first through fourth light emitting structures comprises a first conductive nitride semiconductor layer, an active layer above the first conductive nitride semiconductor layer, and a second conductive nitride semiconductor layer above the active layer;
each of the plurality of first interconnection layer structures electrically connects the first conductive nitride semiconductor layer of the first light emitting structure to the second conductive nitride semiconductor layer of the second light emitting structure;
the second interconnection layer structure electrically connects the first conductive nitride semiconductor layer of the second light emitting structure to the second conductive nitride semiconductor layer of the third light emitting structure; and
each of the plurality of third interconnection layer structures electrically connects the first conductive nitride semiconductor layer of the third light emitting structure to the second conductive nitride semiconductor layer of the fourth light emitting structure,

a first current diffusion layer structure connected to the second conductive nitride semiconductor layer of the first light emitting structure; and
a second current diffusion layer structure connected to the first conductive nitride semiconductor layer of the fourth light emitting structure, wherein layout shapes of the first current diffusion layer structure and the second current diffusion layer structure are T shapes,
wherein lengths of the first current diffusion layer structure and the second current diffusion layer structure in the second direction are greater than lengths of each of the plurality of first interconnection layer structures and the plurality of third interconnection layer structures in the second direction.

US Pat. No. 11,069,844

LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE

OSRAM OLED GMBH, Regensb...


1. A light-emitting device comprising:a light-emitting semiconductor chip having a light-outcoupling surface; and
an optical element arranged on the light-outcoupling surface,
wherein the light-emitting semiconductor chip is laterally surrounded by a frame element in a form-locking manner,
wherein the optical element is mounted on the frame element,
wherein the frame element projects beyond the light-outcoupling surface in a vertical direction such that a gas-filled gap is present at least in a partial region between the light-outcoupling surface and the optical element, and
wherein the frame element has a channel connecting the gap to an atmosphere surrounding the light-emitting device.

US Pat. No. 11,069,843

LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...


14. A light-emitting device comprising:a light-emitting element;
a first light-diffusion layer disposed laterally to the light-emitting element and constituting a first portion of lateral surfaces of the light-emitting device;
a second light-diffusion layer disposed above the light-emitting element and the first light-diffusion layer and constituting a second portion of the lateral surfaces of the light-emitting device;
a light-control portion disposed between the first light-diffusion layer and the second light-diffusion layer and configured to reflect a portion of light emitted from the light-emitting element; and
a first light-reflection layer disposed on the second light-diffusion layer; and
a second light-reflection layer under the light-emitting element.

US Pat. No. 11,069,842

METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND OPTOELECTRONIC SEMICONDUCTOR COMPONENT

OSRAM OLED GMBH, Regensb...


1. A method for manufacturing an optoelectronic semiconductor device, the method comprising:providing a semiconductor layer sequence having an active region for generating radiation and a plurality of emission regions;
forming a plurality of first contact points, each of the first contact points being electrically conductively connected to an emission region on the semiconductor layer sequence;
filling spacings between the first contact points with a molding compound;
removing a growth substrate of the semiconductor layer sequence; and
arranging the semiconductor layer sequence on a connection carrier comprising a control circuit and a plurality of connection surfaces,
wherein each of the first contact points is electrically conductively connected to a connection surface,
wherein the emission regions are independently controllable of one another by the control circuit,
wherein the molding compound serves as a temporary auxiliary carrier that mechanically stabilizes the semiconductor layer sequence during the removal of the growth substrate, and
wherein the growth substrate is removed prior to arranging the semiconductor layer sequence on the connection carrier.

US Pat. No. 11,069,841

MULTILAYER CERAMIC CONVERTER WITH STRATIFIED SCATTERING

OSRAM OPTO SEMICONDUCTORS...


1. A ceramic wavelength converter assembly having a layered structure, the ceramic wavelength converter assembly comprising:a phosphor layer;
an upper barrier layer; and
a lower barrier layer,
wherein the phosphor layer is at least partially located between the upper barrier layer and the lower barrier layer,
wherein the upper barrier layer and the lower barrier layer comprise a porous structure, and
wherein a diameter of pores of the porous structure of the upper barrier layer is bigger than a diameter of pores of the porous structure of the lower barrier layer.

US Pat. No. 11,069,839

OPTICAL COMPONENT PACKAGE AND DEVICE USING SAME

POINT ENGINEERING CO., LT...


1. A device using an optical component package, the device comprising:a main substrate including a plurality of metal bodies, and a vertical insulation part provided between the metal bodies;
a sub-substrate provided in a cavity of the main substrate, and electrically connected to each of the metal bodies with the vertical insulation part interposed therebetween;
an optical component mounted on the sub-substrate; and
a reservoir provided on the main substrate, accommodating a fluid, and including a light transmitting part provided at a position corresponding to the optical component,
wherein the main substrate includes a through hole horizontally passing through the metal bodies,
wherein the reservoir includes an input hole formed at one side thereof, and the input hole and the through-hole communicate with each other through a connection pipe.

US Pat. No. 11,069,838

LIGHT-EMITTING DEVICE WITH LIGHT-EMITTING ELEMENT MOUNTED ON SUPPORTING MEMBER AND DISPLAY APPARATUS

ROHM CO, LTD., Kyoto (JP...


1. A light-emitting device comprising:a light-emitting element having an element front surface and an element back surface spaced apart from each other in a first direction;
a supporting member on which the light-emitting element is mounted; and
a light-transmitting resin formed on the supporting member to cover the light-emitting element,
wherein the supporting member includes:a base having a base front surface and a base back surface opposite to the base front surface, and
a first wiring and a second wiring each disposed on the base and electrically connected to the light-emitting element,

wherein the light-emitting element is mounted on the support member with the element back surface facing the base front surface,
wherein the light-transmitting resin includes:
a lens portion; and
a base portion located between the lens portion and the supporting member in the first direction and surrounding the light-emitting element,
wherein a distance between the element back surface and the base back surface in the first direction is larger than a dimension of the base portion in the first direction.

US Pat. No. 11,069,837

SUB PIXEL LIGHT EMITTING DIODES FOR DIRECT VIEW DISPLAY AND METHODS OF MAKING THE SAME

GLO AB, Lund (SE)


1. A method of forming a light emitting diode (LED), comprising: forming a n-doped semiconductor material layer over a substrate; forming an active region including an optically active compound semiconductor layer stack configured to emit light on the n-doped semiconductor material layer; forming a p-doped semiconductor material layer on the active region; depositing a nickel layer directly on the p-doped semiconductor material layer; etching back the nickel layer to expose a nickel-doped surface region of the p-doped semiconductor layer; and forming a conductive layer on the exposed nickel-doped surface region.

US Pat. No. 11,069,836

METHODS FOR GROWING LIGHT EMITTING DEVICES UNDER ULTRA-VIOLET ILLUMINATION

LUMILEDS LLC, San Jose, ...


1. A method for forming a light emitting diode (LED), the method comprising:epitaxially growing a III-nitride n-type layer over a growth substrate;
epitaxially growing an active layer over the III-nitride n-type layer;
epitaxially growing a III-nitride p-type layer over the active layer in the presence of hydrogen and magnesium;
annealing at least the III-nitride p-type layer in situ to activate magnesium dopants in the III-nitride p-type layer;
ceasing the anneal;
epitaxially forming a first portion of a III-nitride tunnel junction n-type layer over the III-nitride p-type layer to form a tunnel junction light emitting diode;
illuminating a surface of the first portion of the III-nitride tunnel junction n-type layer with light having a photon energy higher than the III-nitride p-type layer's band gap energy during growth; and
epitaxially forming a remainder of the III-nitride tunnel junction n-type layer absent light illumination during growth.

US Pat. No. 11,069,835

OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME

OSRAM OLED GMBH, Regensb...


1. An optoelectronic semiconductor chip comprising:a plurality of fins; and
a current expansion layer for common contacting of at least some of the fins, each fin comprising:two side surfaces arranged opposite one another; and
an active region arranged on each of the side surfaces,

wherein the plurality of fins comprises inner fins and outer fins having an adjacent fin only on one side,
wherein the current expansion layer is in direct contact with the inner fins on their outside, and
wherein at least one of the plurality of fins has a length which is at least 50% of an edge length of the semiconductor chip.

US Pat. No. 11,069,834

OPTOELECTRONIC DEVICE HAVING A BORON NITRIDE ALLOY ELECTRON BLOCKING LAYER AND METHOD OF PRODUCTION

KING ABDULLAH UNIVERSITY ...


1. An optoelectronic device, comprising:a light emitting diode comprising a multiple quantum well layer, an electron blocking layer, a first doped contact layer and a second doped contact layer; and
a high electron mobility transistor comprising a two-dimensional electron gas channel and the electron blocking layer, wherein the two-dimensional electron gas channel of the high electron mobility transistor is comprised of a portion of a last quantum barrier layer of the multiple quantum well layer of the light emitting diode,
wherein the electron blocking layer is a boron nitride alloy electron blocking layer arranged in contact with the last quantum barrier layer on the two-dimensional electron gas channel to allow the portion of the last quantum barrier layer to function as the two-dimensional electron gas channel of the high electron mobility transistor.

US Pat. No. 11,069,833

RESONANT CAVITY STRAINED III-V PHOTODETECTOR AND LED ON SILICON SUBSTRATE

International Business Ma...


1. A method of an optoelectronic device comprising:forming a buffer layer on a type IV semiconductor containing substrate, the buffer layer having a detect density that is less than about 1000 defects/cm2;
forming a first reflector stack of III-V semiconductor material on the buffer layer, wherein the first reflector stack is comprised of at least one aluminum, gallium and arsenic containing layer;
forming an active layer on the first reflector stack, wherein a difference in lattice dimension between the active layer and the first reflector stack induces a strain in the active layer, wherein the active layer functions as an emission layer; and
forming a second reflector stack of III-V semiconductor material on the active layer, wherein the optoelectronic device emits light wavelengths greater than 800 nm.

US Pat. No. 11,069,832

RESONANT CAVITY STRAINED III-V PHOTODETECTOR AND LED ON SILICON SUBSTRATE

International Business Ma...


1. A light emitting diode comprising:a first reflector stack of III-V semiconductor material present on a germanium including buffer layer;
a light emission layer of III-V semiconductor material present on the first reflector stack of III-V semiconductor material, wherein a difference in lattice dimension between the light emission layer and the first reflector stack of III-V semiconductor material induces a strain in the light emission layer, and the light emission layer having a strain in the light emission layer is without a defect density less than 1,000 defects/cm2; and
a second reflector stack of III-V semiconductor material present on the light emission layer, wherein at least one of the first and second reflector stacks is comprised of an aluminum, gallium and arsenic containing layer, and the light emission layer is comprised of an indium, gallium and arsenic containing layer.

US Pat. No. 11,069,831

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...


1. A light emitting device comprising:a substrate;
a plurality of light sources arranged on the substrate, each of the light sources having a light emitting diode;
a partitioning member including a plurality of wall portions defining a plurality of sections respectively surrounding at least one of the light sources, the wall portions including top portions; and
a diffuser panel arranged above the light sources, the diffuser panel defining a plurality of grooves each having a V-shape cross sectional shape and respectively accommodating the top portions of the partitioning member, wherein
an inclination angle of the V-shape cross sectional shape of each of the grooves is greater than an apex angle of each of the top portions of the partitioning member in a cross-sectional view.

US Pat. No. 11,069,830

QUANTUM-CONFINED STARK EFFECT (QCSE) MODULATOR AND PHOTONICS STRUCTURE INCORPORATING THE QCSE MODULATOR

GLOBALFOUNDRIES U.S. Inc....


1. A modulator comprising:a first doped semiconductor region having a first type conductivity, wherein the first doped semiconductor region is at a bottom of a trench that extends through a dielectric layer to a semiconductor layer;
a multi-quantum well region in the trench on the first doped semiconductor region, wherein the trench has first sidewalls and the multi-quantum well region has second sidewalls adjacent to the first sidewalls, respectively, wherein a width of the multi-quantum well region narrows toward a top of the trench, wherein at least upper segments of the second sidewalls of the multi-quantum well region are physically separated from the first sidewalls of the trench by spaces that widen toward the top of the trench;
dielectric spacers filling the spaces between the first sidewalls of the trench and the second sidewalls of the multi-quantum well region, wherein widths of the dielectric spacers increase toward the top of the trench; and
a second doped semiconductor region on the multi-quantum well region, wherein the second doped semiconductor region has a second type conductivity that is different from the first type conductivity.

US Pat. No. 11,069,829

LIGHT-EMITTING ELEMENT, METHOD OF MANUFACTURING THE SAME AND DISPLAY DEVICE COMPRISING LIGHT-EMITTING ELEMENT

Samsung Display Co., Ltd....


1. A method of manufacturing a light-emitting element comprising:positioning a substrate;
forming a first separation layer, which comprises a first sacrificial layer, an etching control layer on the first sacrificial layer, and a second sacrificial layer on the etching control layer, on the substrate;
forming at least one first light-emitting element on the first separation layer; and
separating the first light-emitting element from the substrate,
wherein the forming at least one first light-emitting element comprises forming a first light-emitting laminate on the first separating layer;
performing a first etching process after forming a first light-emitting laminate; and
performing a second etching process after the first etching process, the second etching process comprising forming an insulating film on the vertically etched first light-emitting laminate and vertically etching a part of the insulating film.

US Pat. No. 11,069,827

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...


1. A semiconductor device comprising:a substrate having a mounting surface and an attachment surface facing away from each other;
a light-receiving element mounted on the mounting surface of the substrate, the light-receiving element having a light-receiving region that detects light;
a light-emitting element mounted on the mounting surface of the substrate and spaced apart from the light-receiving element in a first direction perpendicular to a thickness direction of the substrate;
a light-transmitting member covering the light-receiving element and the light-emitting element, the light-transmitting member having a convex lens from which light is emitted; and
a light-shielding member that covers the light-transmitting member and has a first opening exposing the lens,
wherein the lens has a first lens surface and a second lens surface that are next to each other in the first direction, the first lens surface being located between an imaginary plane perpendicular to the first direction and the light-receiving element, the second lens surface being located on a side of the imaginary plane opposite the first lens surface,
wherein a curvature radius of the first lens surface is smaller than a curvature radius of the second lens surface,
wherein an inner wall of the first opening includes a first portion facing the first lens surface and a second portion facing the second lens surface, and
wherein an inclination angle of the first portion relative to the first direction is larger than an inclination angle of the second portion relative to the first direction.

US Pat. No. 11,069,826

PHOTOSENSITIVE DEVICE WITH ELECTRIC SHUTTER

EMBERION OY, Espoo (FI)


1. A photosensitive device which can be configured to provide an electrical response when illuminated by electromagnetic radiation incident on the device, comprising:at least one substantially horizontal, electrically conducting gate electrode which defines a first region on a substrate surface, and is configured to receive a gate voltage,
a substantially horizontal layer of ambipolar two-dimensional material which overlies or underlies the at least one gate electrode across the first region,
an insulating layer between the at least one gate electrode and the layer of ambipolar two-dimensional material across the first region, and
a substantially horizontal layer of photoactive semiconducting material which is in contact with and forms a junction with the layer of ambipolar two-dimensional material across the first region,
wherein the electrical response of the photosensitive device is measured from the ambipolar two-dimensional material,
wherein the doping concentration of the ambipolar two-dimensional material and the doping concentration of the photoactive semiconducting layer generate a non-screening gate voltage interval where an interface voltage at the junction between the photoactive semiconducting layer and the ambipolar two-dimensional material can be changed by applying to the gate electrode a gate voltage which falls within the non-screening gate voltage interval, and
the doping concentration of the ambipolar two-dimensional material and the doping concentration of the photoactive semiconducting layer generate in the non-screening gate voltage interval a flat-band gate voltage at which the interface voltage is zero, a depletion gate voltage range where the interface voltage is nonzero, and a charge-neutrality gate voltage at which the ambipolar two-dimensional material is at its charge-neutrality point, and
wherein the depletion gate voltage range and the charge-neutrality gate voltage lie on the same side of the flat-band gate voltage on a gate voltage axis.

US Pat. No. 11,069,824

OPTICAL SENSOR DEVICE AND METHOD OF MANUFACTURING THE SAME

ABLIC INC., Chiba (JP)


1. An optical sensor device, comprising:a base portion;
an optical semiconductor element placed on the base portion;
a lid portion stacked onto the base portion, the lid portion sealing the optical semiconductor element in a hollow portion;
a first metallization layer formed on a surface of the lid portion opposing the base portion;
a second metallization layer formed on a surface of the base portion is opposing the lid portion; and
a metal bonding layer bonding the first metallization layer to the second metallization layer,
the first metallization layer having a plurality of first notch portions.

US Pat. No. 11,069,823

PHOTOELECTRIC CONVERSION DEVICE, PHOTOELECTRIC CONVERSION SYSTEM, AND MOVABLE OBJECT COMPRISING A COMPARISON UNIT TO COMPARE THE COUNT VALUE OF PULSE WITH A PREDETERMINED THRESHOLD VALUE

CANON KABUSHIKI KAISHA, ...


1. A photoelectric conversion device comprising:a plurality of pixels arranged in a plurality of rows and a plurality of columns; and
a plurality of output lines to which signals from the plurality of pixels are output,
wherein each of the plurality of pixels includes a light receiving unit that outputs a pulse in response to incidence of a photon and a signal generation unit that, based on output from the light receiving unit, generates a pixel signal output to corresponding output line,
wherein the signal generation unit includes a count unit that generates a count signal indicating a count value of pulses output from the light receiving unit and a comparison unit that compares the count value indicated by the count signal with a predetermined threshold value, and
wherein the signal generation unit outputs a signal in accordance with a result of comparison performed by the comparison unit.

US Pat. No. 11,069,822

TRANSITION METAL CHALCOGENIDE VAN DER WAALS FILMS, METHODS OF MAKING SAME, AND APPARATUSES AND DEVICES COMPRISING SAME

CORNELL UNIVERSITY, Itha...


1. A method of forming a VDW film comprising one or more TMD monolayers, and having a heterostructure comprised of at least two atomically thin monolayer TMD building blocks, wherein the VDW film has no detectible carbon and less than one bubble defect and/or wrinkle defect per 2 micron×2 micron area, wherein an interlayer between two adjacent TMD monolayers is a clean, bubble-free and wrinkle-free interface comprising a constant distance, the method comprising:providing a formation substrate having one or more transition metal dichalcogenide (TMD) monolayers disposed on the formation substrate;
dry peeling at least one of the TMD monolayer from the formation substrate;
transferring the TMD monolayer to a substrate under vacuum to form a Van der Waals (VDW) film;
optionally, repeating the providing, dry peeling, and transferring to form a VDW film comprising a plurality of TMD monolayers on the substrate.

US Pat. No. 11,069,821

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Manufacturi...


1. A semiconductor device, comprising:a semiconductor substrate comprising a first region and a second region that are mutually exclusive from one another;
a first oxide layer on the first region;
a nitride barrier layer on the first oxide layer;
a second oxide layer on the second region; and
a separation structure positioned between the first oxide layer and the second oxide layer, wherein a first side of the separation structure directly contacts the first oxide layer, is opposite a second side of the separation structure, and directly contacts at least one more layer than the second side of the separation structure does, wherein the second side of the separation structure directly contacts the second oxide layer, wherein the second oxide layer includes no nitrogen and directly contacts no nitride layer, wherein a first section of the first side of the separation structure directly contacts the nitride barrier layer, wherein a second section of the first side of the separation structure directly contacts the first oxide layer, wherein a third section of the first side of the separation structure directly contacts the semiconductor substrate, and wherein the second section of the first side of the separation structure is positioned between the first section of the first side of the separation structure and the third section of the first side of the separation structure.

US Pat. No. 11,069,820

FINFET DEVICES HAVING ACTIVE PATTERNS AND GATE SPACERS ON FIELD INSULATING LAYERS

Samsung Electronics Co., ...


1. A semiconductor device, comprising:an active pattern including a lower active pattern and an upper active pattern on the lower active pattern, protruding from a substrate and extending in a first direction, and the upper active pattern spaced apart from the lower active pattern in a second direction different from the first direction and extending in the first direction;
a field insulating layer covering at least a part of the active pattern on the substrate;
a gate structure on the field insulating layer and the active pattern, the gate structure extending in a third direction different from the first direction and the second direction; and
a gate spacer on a side wall of the gate structure,
wherein the field insulating layer includes a first region overlapping with the gate spacer and a second region overlapping with the gate structure, and
wherein the field insulating layer in the first region contains nitrogen element and the field insulating layer in the second region does not contain nitrogen element.

US Pat. No. 11,069,819

FIELD-EFFECT TRANSISTORS WITH CHANNEL REGIONS THAT INCLUDE A TWO-DIMENSIONAL MATERIAL ON A MANDREL

GLOBALFOUNDRIES U.S. INC....


17. A method of forming a field-effect transistor, the method comprising:forming a first channel layer including a channel region;
forming a first dielectric mandrel that includes a first side surface and a second side surface;
forming a second dielectric mandrel that includes a side surface and that is arranged over the first dielectric mandrel;
forming a gate electrode that has a section wrapped about the first side surface and the second side surface of the first dielectric mandrel; and
forming a second channel layer including a channel region positioned in part between the side surface of the second dielectric mandrel and the section of the gate electrode,
wherein the channel region of the first channel layer is positioned in part between the first side surface of the first dielectric mandrel and the section of the gate electrode, and the first channel layer and the second channel layer are comprised of a two-dimensional material.

US Pat. No. 11,069,818

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...


1. A semiconductor device comprising:a first wire pattern disposed on a substrate and extending in a first direction;
a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly;
a first transistor including the first wire pattern and the first gate electrode;
a second wire pattern disposed on the substrate and extending in the first direction;
a second gate electrode surrounding the second wire pattern and extending in the second direction;
a second transistor including the second wire pattern and the second gate electrode,
one or more third wire patterns disposed above the first wire pattern in a third direction perpendicular to the first and second directions and extending in the first direction; and
one or more fourth wire patterns disposed above the second wire pattern in the third direction and extending in the first direction,
wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction,
wherein the first gate electrode surrounds each of the third wire patterns,
wherein the second gate electrode surrounds each of the fourth wire patterns, and
wherein a total number of wire patterns overlapping with the first wire pattern in the third direction including the third wire patterns is different from a total number of wire patterns overlapping with the second wire pattern in the third direction including the fourth wire patterns.

US Pat. No. 11,069,816

SEMICONDUCTOR DEVICE AND DISPLAY DEVICE

Semiconductor Energy Labo...


1. A semiconductor device comprising:a first semiconductor layer;
a second semiconductor layer;
a third semiconductor layer;
a first insulating layer;
a second insulating layer;
a third insulating layer;
a fourth insulating layer;
a first conductive layer; and
a pair of second conductive layers,
wherein the first conductive layer is positioned over the second semiconductor layer,
wherein the second semiconductor layer is positioned over the first semiconductor layer,
wherein the second conductive layers are on and in contact with the second semiconductor layer,
wherein the second insulating layer is provided so as to be in contact with and cover top surfaces and side surfaces of the second conductive layers,
wherein the second insulating layer includes, in a region between the pair of second conductive layers, a first opening overlapping with the second semiconductor layer,
wherein the third semiconductor layer is provided in contact with a top surface of the second insulating layer, a side surface of the first opening, and the second semiconductor layer,
wherein the first insulating layer is positioned between the first conductive layer and the third semiconductor layer,
wherein the third insulating layer is positioned between the first insulating layer and the first conductive layer,
wherein the fourth insulating layer is provided so as to be in contact with and surround the first conductive layer,
wherein the fourth insulating layer is in contact with the third insulating layer, the first insulating layer, and the third semiconductor layer, and
wherein the third semiconductor layer includes a portion in contact with a side surface of the second semiconductor layer and a portion in contact with part of the first semiconductor layer.

US Pat. No. 11,069,815

RADIATION HARDENED THIN-FILM TRANSISTORS

Auburn University, Aubur...


5. A radiation-hardened thin-film transistor, comprising:a dielectric layer; and
an annealed layer comprising zinc oxide or zinc tin oxide and positioned adjacent to the dielectric layer, wherein an annealing temperature of the layer is selected based on a dose of radiation expected to irradiate the thin-film transistor, and wherein the annealed layer has a thickness and threshold displacement energies after it has been annealed such that when the dose irradiates the thin-film transistor, a change in performance of the thin-film transistor when a voltage is applied is less than a performance threshold.

US Pat. No. 11,069,814

TRANSISTOR HAVING VERTICAL STRUCTURE AND ELECTRIC DEVICE

LG DISPLAY CO., LTD., Se...


19. A transistor having a vertical structure, comprising:a gate electrode disposed on a substrate;
a first insulating film disposed on the gate electrode;
an active layer disposed on the first insulating film, the active layer including:a first portion of the active layer overlapping with an upper surface of the gate electrode,
a second portion of the active layer extending from the first portion, being disposed along a side surface of the gate electrode and including a channel area, and
a third portion of the active layer extending from the second portion, the third portion of the active layer being disposed on a portion of the first insulating film that does not overlap with the gate electrode;

a second insulating film disposed on the active layer;
a first electrode disposed on the second insulating film, the first electrode being electrically connected to the first portion of the active layer;
a second electrode disposed on the second insulating film, the second electrode being electrically connected to the third portion of the active layer; and
an insulation pattern disposed between the active layer and the second insulating film,
wherein the insulation pattern overlaps the channel area of the active layer.

US Pat. No. 11,069,813

LOCALIZED HEATING IN LASER ANNEALING PROCESS

Taiwan Semiconductor Manu...


1. A method of forming a semiconductor device, comprising:forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures;
forming conductive plugs in the source/drain contact openings;
depositing a light blocking layer over the conductive plugs and the at least one dielectric layer;
etching the light blocking layer to expose the conductive plugs;
directing a laser irradiation to the conductive plugs and the light blocking layer, the laser irradiation configured to activate dopants in the source/drain contact regions; and
removing the light blocking layer.

US Pat. No. 11,069,812

FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...


1. A method of forming a semiconductor device, the method comprising:forming a fin protruding above a substrate;
forming a liner over the fin;
performing a surface treatment process to convert an upper layer of the liner distal to the fin into a conversion layer, the conversion layer comprising an oxide or a nitride of the liner;
forming isolation regions on opposing sides of the fin after the surface treatment process;
forming a gate dielectric over the conversion layer after forming the isolation regions; and
forming a gate electrode over the fin and over the gate dielectric.

US Pat. No. 11,069,811

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...


1. A method for forming a semiconductor device structure, comprising:forming a gate stack over a substrate;
forming a first mask layer covering the gate stack;
forming a contact alongside the gate stack and the first mask layer;
recessing the contact, wherein the contact is recessed to expose a sidewall of the first mask layer;
etching the first mask layer, wherein etching the first mask layer comprises laterally etching the first mask layer from the sidewall of the first mask layer; and
forming a second mask layer covering the contact and a portion of the first mask layer.

US Pat. No. 11,069,810

SEMICONDUCTOR DEVICE HAVING A SHAPED EPITAXIAL REGION

Taiwan Semiconductor Manu...


1. A semiconductor device comprising:a fin extending from a substrate;
a source/drain region in the fin, the source/drain region comprising:a bulk section comprising a first semiconductor material and a first dopant, a first interface of the bulk section and the fin having a first concentration of the first dopant;
a shaping section on the bulk section, the shaping section comprising the first semiconductor material and the first dopant, a second interface of the shaping section and the bulk section having a second concentration of the first dopant, the second concentration being greater than the first concentration; and
a finishing section on the shaping section, the finishing section comprising the first semiconductor material and the first dopant, a third interface of the finishing section and the shaping section having a third concentration of the first dopant, the third concentration being greater than the second concentration.


US Pat. No. 11,069,809

SOI FINFET FINS WITH RECESSED FINS AND EPITAXY IN SOURCE DRAIN REGION

GLOBALFOUNDRIES U.S. INC....


1. A semiconductor device comprising:a fin structure extended above a substrate structure, the fin structure including a channel region of a first height above the substrate structure, and a recessed fin portion having a top surface, a first horizontal width, and a second height above the substrate structure that is less than the first height;
an epitaxially-grown semiconductor material, having a bottom surface with a second horizontal width greater than the first horizontal width of the recessed fin structure, and extending laterally out from the recessed fin portion to form at least one of a source region and a drain region of the semiconductor device, wherein the bottom surface of the epitaxially-grown semiconductor material contacts and overlies the recessed fin portion; and
an additional semiconductor material having a different material composition from the epitaxially-grown semiconductor material, and disposed over the epitaxially-grown semiconductor material and in physical contact with both the bottom surface of the epitaxially-grown semiconductor material and at least one sidewall of the recessed fin portion, wherein the additional semiconductor material encloses both the epitaxially-grown semiconductor material and the recessed fin portion, and wherein the additional semiconductor material that encloses the epitaxially-grown semiconductor material and the recessed fin portion has a single material composition.

US Pat. No. 11,069,808

NEGATIVE CAPACITANCE FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

Institute of Microelectro...


1. A negative capacitance field effect transistor, comprising:a substrate structure, comprising a MOS (metal-oxide-semiconductor field effect transistor) region;
a gate insulating dielectric structure, covering the MOS region; and
a metal gate stack layer, covering the gate insulating dielectric structure;
wherein the gate insulating dielectric structure comprises an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure;
wherein a ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1?x?0.9; and
wherein a material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1.

US Pat. No. 11,069,807

FERROELECTRIC STRUCTURE FOR SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...


1. A method of forming a semiconductor device, comprising:forming a substrate;
forming first and second spacers on the substrate;
depositing an interface layer, wherein a first portion of the interface layer is deposited on the substrate and a second portion of the interface layer is deposited on the first and second spacers;
depositing an amorphous dielectric layer on the interface layer, wherein first and second portions of the amorphous dielectric layer are deposited on the first and second portions of the interface layer, respectively;
performing a plasma treatment on the amorphous dielectric layer, wherein the plasma treatment converts the first portion of the amorphous dielectric layer into a crystalline dielectric layer; and
forming a gate electrode on the crystalline dielectric layer and the second portion of the amorphous dielectric layer.

US Pat. No. 11,069,806

INTEGRATED CIRCUIT INCLUDING A LOW-NOISE AMPLIFYING CIRCUIT WITH ASYMMETRICAL SOURCE AND DRAIN REGIONS AND A LOGIC CIRCUIT WITH SYMMETRICAL SOURCE AND DRAIN REGIONS

RichWave Technology Corp....


1. An integrated circuit comprising a low-noise amplifying circuit and a logic circuit formed on a substrate, wherein:the low-noise amplifying circuit comprises at least one first transistor, and the first transistor comprises:a first well region;
a first gate formed on the first well region and coupled to a signal input terminal; and
a first source region and a first drain region respectively formed in the first well region on both sides of the first gate, wherein the first source region is coupled to a reference voltage terminal, and a sheet resistance of the first source region is lower than a sheet resistance of the first drain region; and

the logic circuit comprises at least one second transistor, and the second transistor comprises:a second well region;
a second gate formed on the second well region; and
a second source region and a second drain region respectively formed in the second well region on both sides of the second gate, wherein a sheet resistance of the second source region and a sheet resistance of the second drain region are equal.


US Pat. No. 11,069,805

EMBEDDED JFETS FOR HIGH VOLTAGE APPLICATIONS

Taiwan Semiconductor Manu...


16. A device comprising:a Junction Field-Effect Transistor (JFET) comprising:a high-voltage n-type well region (HVNW) region;
a drain region in the HVNW region;
an insulation region extending into the HVNW region;
a p-well region comprising a plurality of strip portions separated from each other, wherein first ends of the plurality of strip portions contact a sidewall of the HVNW region;
a first heavily doped n-type region and a second heavily doped n-type region extending into the HVNW region, wherein the first heavily doped n-type region and the second heavily doped n-type region are separated from each other by the plurality of strip portions of the p-well region; and
a heavily doped p-type region over and contacting the p-well region.


US Pat. No. 11,069,804

INTEGRATION OF HVLDMOS WITH SHARED ISOLATION REGION

Alpha and Omega Semicondu...


1. A power device, comprising:a) a semiconductor substrate composition having a substrate layer of a first conductivity type;
b) two or more lateral double diffused metal oxide semiconductor (LDMOS) devices formed in the substrate layer and integrated into an isolation region of a high voltage well, wherein each LDMOS is isolated from a power device substrate area by an isolator structure formed from the substrate layer and wherein each LDMOS includes:a deep well region of a second conductivity type opposite the first conductivity type formed in the substrate layer,
a source region, a body region and a drain contact pickup region formed in the deep well region, wherein the body region is of the first conductivity type, the source region is of the second conductivity type and the drain contact pickup region is of the second conductivity type;
a body pickup region formed in the body region and laterally adjacent to the source region, wherein the body pickup region is of the first conductivity type but more heavily doped than the body region,
an insulated gate layer formed on top an active channel region, the active channel being located in the body region between the source region and a junction between the body region and the deep well region,
an insulation layer formed on top of the substrate composition between the body region and the drain contact pickup region;
a RESURF region of the first conductivity type located directly underneath the insulation layer;

c) a continuous field plate formed at least partially on the insulation layer over each of the two or more LDMOS devices and in conductive contact with the power device substrate area, wherein the continuous field plate is continuous over each of the two or more LDMOS devices; and
d) a plurality of conductive electrically floating rings formed on top the insulation layer, wherein the plurality of conductive electrically floating rings are continuous over the isolator structure and the power device substrate area.

US Pat. No. 11,069,803

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR

KABUSHIKI KAISHA TOSHIBA,...


1. A semiconductor device comprising:a silicon carbide layer having a first plane parallel to a first direction and a second direction perpendicular to the first direction and a second plane facing the first plane, the silicon carbide layer having
a first trench being located on a side of the first plane and extending in the first direction,
a first silicon carbide region of n-type,
a second silicon carbide region of p-type being located between the first silicon carbide region and the first plane,
a third silicon carbide region of n-type being located between the second silicon carbide region and the first plane, and
a fourth silicon carbide region of p-type being located between the first silicon carbide region and the first plane, at least a portion of the fourth silicon carbide region being located in the second silicon carbide region, the fourth silicon carbide region having a higher p-type impurity concentration than a p-type impurity concentration of the second silicon carbide region;
a gate electrode being located in the first trench;
a gate insulating layer being located between the gate electrode and the silicon carbide layer;
a first electrode being located on a side of the first plane of the silicon carbide layer; and
a second electrode being located on a side of the second plane of the silicon carbide layer,
wherein a first position and a second position exist in the at least portion of the fourth silicon carbide region, a first distance from the first plane to the first position is smaller than a second distance from the first plane to the second position, and a third distance from the gate insulating layer to the first position is smaller than a fourth distance from the gate insulating layer to the second position.

US Pat. No. 11,069,802

FIELD EFFECT TRANSISTOR INCLUDING GRADUALLY VARYING COMPOSITION CHANNEL

Samsung Electronics Co., ...


1. A field effect transistor (FET) comprising:a drain region;
a drift region on the drain region;
a channel region on the drift region, the channel region having a gradually varying composition along a vertical direction such that an intensity of a polarization in the channel region gradually varies;
a source region on the channel region;
a gate, the gate penetrating the channel region and the source region in the vertical direction; and
a gate oxide surrounding the gate.

US Pat. No. 11,069,801

SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Sony Semiconductor Soluti...


12. A method of manufacturing a semiconductor device, the method comprising:providing an element region and an element separating region on a substrate, the element separating region being provided at least on both sides of the element region;
providing a gate insulating film at least on the element region of the substrate at least from one side to another side of the element separating region;
providing a predetermined mask on the gate insulating film;
forming a film containing an impurity on the gate insulating film and the mask, and performing heat treatment to diffuse the impurity in the gate insulating film that is not covered by the mask;
removing the mask;
providing a gate electrode on the gate insulating film; and
providing a source region and a drain region with the gate electrode interposed therebetween in the element region.

US Pat. No. 11,069,800

SINGLE ELECTRON TRANSISTOR WITH GAP TUNNEL BARRIERS

International Business Ma...


1. A semiconductor device, comprising:a vertical single electron transistor (SET) comprising:an island region over a top surface of a substrate;
a bottom source/drain region on the top surface of the substrate and under the island region, and a top source/drain region over the top surface of the substrate and over the island region;
wherein the top source/drain region is at a different height in a direction perpendicular to the top surface of the substrate than a height of the bottom source/drain region;
a first gap between the bottom source/drain region and the island region;
a second gap between the top source/drain region and the island region; and
a gate structure on a side of the island region;
wherein the first and second gaps are selected from the group consisting of air, a vacuum, nitrogen, hydrogen, oxygen, carbon dioxide, helium, argon, neon, and krypton.


US Pat. No. 11,069,799

AMORPHOUS METAL HOT ELECTRON TRANSISTOR

Amorphyx, Incorporated, ...


1. A device, comprising:a substrate;
an amorphous metal layer on the substrate;
a tunneling dielectric layer on the amorphous metal layer;
a barrier layer on the tunneling dielectric layer;
a first electrode and a second electrode on the tunneling dielectric layer, each overlapping the amorphous metal layer;
a second dielectric layer on the first electrode and the second electrode; and
a third electrode on the second dielectric layer, the third electrode overlapping the second electrode and the amorphous metal layer.

US Pat. No. 11,069,798

BALLISTIC TRANSPORT DEVICE AND CORRESPONDING COMPONENT

STMicroelectronics S.r.l....


1. A device, comprising:a particle propagation channel including:a particle inflow portion,
a particle outflow portion, and
a particle flow deflection portion between the particle inflow portion and the particle outflow portion, the particle propagation channel being configured to facilitate ballistic transport of particles from the particle inflow portion to the particle outflow portion, the particle flow deflection portion including a first protrusion that protrudes outwardly with respect to the particle inflow portion;

a first particle deflector arranged outside of an outer surface of a wall of the first protrusion of the particle flow deflection portion, the first particle deflector being activatable to deflect particles propagating in the particle flow deflection portion toward an inner surface of the wall of the first protrusion and prevent the particles from reaching the particle outflow portion; and
a particle source at the particle inflow portion of the particle propagation channel, and a particle sink at the particle outflow portion of the particle propagation channel, wherein the particle source and the particle sink are configured to cause a current path of the particles through the device.

US Pat. No. 11,069,797

RUGGEDIZED SYMMETRICALLY BIDIRECTIONAL BIPOLAR POWER TRANSISTOR

IDEAL POWER INC., Austin...


1. A semiconductor device, comprising, on BOTH surfaces of a first-conductivity-type semiconductor die:a second-conductivity-type emitter/collector region, laterally surrounded by a first insulated trench; and
a first-conductivity-type base contact region, laterally separated from the emitter/collector region by the first insulated trench, and making ohmic contact to the bulk of the semiconductor die;
wherein an interior of the emitter/collector region includes, at locations at a distance from sides of the surrounding first insulated trench and separated from the first insulated trench and not at locations adjacent to and not contacting the first insulated trench, and at a distance from and not overlapping or contacting a vertical plane of the sides of the surrounding first insulated trench, breakdown initiation regions where an additional implanted population of second-conductivity-type dopant atoms creates embedded enriched regions of second-conductivity-type dopant, compared to the adjacent region of second-conductivity-type dopant of the second-conductivity-type emitter/collector region, said enriched regions exhibiting a reduced breakdown voltage;
whereby breakdown, under overvoltage conditions, begins near the initiation regions, and thereby minimizes hot carrier injection into the first insulated trench.

US Pat. No. 11,069,796

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...


1. A method for manufacturing a semiconductor device, comprising:forming a semiconductor layer comprising a metal oxide;
forming a gate insulating layer comprising an oxide over the semiconductor layer;
forming a metal oxide layer over the gate insulating layer;
performing heat treatment after forming the metal oxide layer;
removing the metal oxide layer after the heat treatment;
forming a gate electrode overlapping with part of the semiconductor layer over the gate insulating layer after removing the metal oxide layer; and
supplying a first element through the gate insulating layer to a region of the semiconductor layer not overlapping with the gate electrode,
wherein the first element is phosphorus, boron, magnesium, aluminum, or silicon.

US Pat. No. 11,069,795

TRANSISTORS WITH CHANNEL AND SUB-CHANNEL REGIONS WITH DISTINCT COMPOSITIONS AND DIMENSIONS

Intel Corporation, Santa...


1. An integrated circuit (IC) including at least one transistor, the IC comprising:a gate structure including a gate electrode and a gate dielectric, the gate electrode including metal material; and
a fin proximate the gate electrode, the gate dielectric between the gate electrode and the fin, the fin having an upper region that includes germanium and a lower region that includes germanium, the lower region having opposing sidewalls adjacent to and in contact with regions of insulator material, and the upper region having opposing sidewalls directly adjacent to and in contact with the gate dielectric, the lower region opposing sidewalls each having a first chemical composition and the upper region opposing sidewalls each having a second chemical composition different from the first chemical composition, the first chemical composition including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, or sulfur;
wherein a first width between the lower region opposing sidewalls at a first location is at least 1 nanometer (nm) wider than a second width between the upper region opposing sidewalls at a second location, the first location being within 10 nm of the second location.

US Pat. No. 11,069,794

TRENCH POWER TRANSISTOR AND METHOD OF PRODUCING THE SAME

Leadpower-semi Co., LTD.,...


1. A trench power transistor comprising:a semiconductor body having a first surface and a second surface opposite to each other, and including at least one active region, said active region includinga trench electrode structure having an electrode trench that is recessed from said first surface, and that has a bottom wall, a lower surrounding wall extending upwardly from said bottom wall, and an upper surrounding wall extending upwardly from said lower surrounding wall to said first surface, said electrode trench having a lower trench portion that is defined by said bottom wall and said lower surrounding wall, and an upper trench portion that is defined by said upper surrounding wall, said trench electrode structure including an insulating layer that is disposed over said bottom wall and said upper and lower surrounding walls, a shield electrode that is disposed in said lower trench portion and that is enclosed by said insulating layer, and a gate electrode that is disposed in said upper trench portion, and that is surrounded by said insulating layer to be separated from said shield electrode,
a well formed adjacent to said electrode trench of said trench electrode structure, and extending downwardly from said first surface, and
a source formed in said well,

wherein said semiconductor body further includes a trench edge termination structure surrounding said active region and having a termination trench that is recessed from said first surface and that has a bottom wall, a lower surrounding wall extending upwardly from said bottom wall of said termination trench, and an upper surrounding wall extending upwardly from said lower surrounding wall of said termination trench to said first surface, said termination trench having a lower trench portion that is defined by said bottom wall and said lower surrounding wall of said termination trench, and an upper trench portion that is defined by said upper surrounding wall of said termination trench, said trench edge termination structure including an insulator layer that is disposed over said bottom wall and said upper and lower surrounding walls of said termination trench, an electrically conductive member that is disposed at least in said lower trench portion of said termination trench, and that is surrounded by said insulator layer, and a nitride layer that is disposed in said upper trench portion of said termination trench, and that is surrounded by said insulator layer to be separated from said electrically conductive member.

US Pat. No. 11,069,793

REDUCING PARASITIC CAPACITANCE FOR GATE-ALL-AROUND DEVICE BY FORMING EXTRA INNER SPACERS

TAIWAN SEMICONDUCTOR MANU...


1. A semiconductor device, comprising:a plurality of nanostructures, the nanostructures each containing a semiconductive material;
a plurality of first spacers circumferentially wrapping around the nanostructures in 360 degrees in a cross-sectional view;
a plurality of second spacers circumferentially wrapping around the first spacers in 360 degrees in the cross-sectional view;
a plurality of third spacers disposed between the second spacers vertically in the cross-sectional view; and
a gate structure that surrounds the second spacers and the third spacers in the cross-sectional view.

US Pat. No. 11,069,791

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES

TAIWAN SEMICONDUCTOR MANU...


1. A method of manufacturing a semiconductor device, comprising:forming a plurality of fin structures over a semiconductor substrate, the plurality of fin structures extending along a first direction and arranged in a second direction crossing the first direction;
forming a plurality of sacrificial gate structures extending in the second direction over the fin structures;
forming an interlayer dielectric layer over the plurality of fin structures between adjacent sacrificial gate structures;
cutting the sacrificial gate structures into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction; and
forming gate separation plugs by filling the gate end spaces with two or more dielectric materials,
wherein the two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

US Pat. No. 11,069,790

QUANTUM TUNNELING MATTER-WAVE TRANSISTOR SYSTEM

ColdQuanta, Inc., Boulde...


1. A quantum tunneling matter-wave transistor process comprising:causing a source well of a matter-wave transistor to be populated with matter-wave particles, the matterwave transistor including a source well, a source-gate barrier, a gate well, a gate-drain barrier, and a drain well; and
changing the source-to-drain matterwave current tunneling through the source-gate barrier and the gate-drain barrier by changing resonant tunneling conditions of the gate well.

US Pat. No. 11,069,789

VARIED SILICON RICHNESS SILICON NITRIDE FORMATION

MONTEREY RESEARCH, LLC, ...


1. A method of fabricating a three-dimensional device, comprising:forming a stack, including multiple sacrificial nitride and inter-cell dielectric layers arranged in an alternating arrangement, overlaying a substrate;
etching at least one opening in the stack;
forming a blocking dielectric layer overlying an inner surface of the at least one opening;
depositing a first silicon nitride layer having a first silicon richness value abutting the blocking dielectric layer;
pre-determining an initial silicon richness value;
depositing a second silicon nitride layer having the initial silicon richness value, abutting the first silicon nitride layer;
adjusting the initial silicon richness value to a first updated silicon richness value; and
depositing a third silicon nitride layer having the first updated silicon richness value.

US Pat. No. 11,069,788

SEMICONDUCTOR DEVICE

TOYODA GOSEI CO., LTD., ...


1. A semiconductor device comprising:a GaN base layer having a first surface and a second surface;
a Group III nitride semiconductor layer on the first surface of the GaN base layer; and
an electrode on the second surface of the GaN base layer, wherein
the first surface is a +c plane;
the second surface is a surface opposite to the first surface; and
the electrode has a first Ti layer, an Al-containing layer, a second Ti layer, a TiN layer, a third Ti layer, a Ni layer, and an Ag-containing layer sequentially from the second surface.

US Pat. No. 11,069,787

GAN-BASED MICROWAVE POWER DEVICE WITH LARGE GATE WIDTH AND MANUFACTURING METHOD THEREOF

SOUTH CHINA UNIVERSITY OF...


1. A GaN-based microwave power device with a large gate width, wherein the device comprises:an AlGaN/GaN hetero unction epitaxial layer; a first dielectric layer overlying the AlGaN/GaN heterojunction epitaxial layer; a strip-like source electrode; a drain electrode distributed in a shape of a fishbone, wherein the drain electrode comprises a first drain electrode located at a fish ridge of the fishbone and a plurality of second drain electrodes located at fish bones of the fishbone, and all of the second drain electrodes are connected together by the first drain electrode in a middle;
a plurality of annular gate electrodes, wherein the gate electrodes are disposed on two sides of the first drain electrode in a symmetrical manner, and the gate electrodes disposed on one side of the first drain electrode are arranged along an extending direction of the first drain electrode;
a second dielectric layer; and an interconnect metal electrode pad, wherein the second dielectric layer separates the gate electrodes and a portion of the interconnect metal electrode pad which connects the source electrode, and the second dielectric layer separates the drain electrode and the portion of the interconnect metal electrode pad, wherein the first dielectric layer overlying the AlGaN/GaN heterojunction epitaxial layer is one of SiN, SiO2, SON, Ga2O3, Al2O3, AlN, and HfO2, or is a multilayer structure which is combined by two or more of them, and the first dielectric layer has a thickness of 10 nm to 50 nm.

US Pat. No. 11,069,785

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Taiwan Semiconductor Manu...


1. A semiconductor device, comprising:a metal-semiconductor compound film over a semiconductor substrate, wherein the metal-semiconductor compound film comprising a semiconductor and a first metal; and
a cover layer enclosing a first portion of a surface of the metal-semiconductor compound film, wherein the cover layer comprises at least one of an oxide of the first metal, a nitride of the first metal, an oxynitride of the first metal, or a carbide of the first metal.

US Pat. No. 11,069,784

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...


1. A method, comprising:recessing a first portion of a source/drain contact to form a recess disposed within a first dielectric layer of a finFET device, the source/drain contact being formed from a first metal material;
depositing a second metal material to form a metal riser in the recess and in physical contact with the source/drain contact, the second metal material being different from the first metal material and an interface between the metal riser and the source/drain contact having a first width being smaller than a width of the source/drain contact;
depositing a second dielectric layer over the metal riser;
etching an opening through the second dielectric layer and exposing the metal riser through the second dielectric layer;
depositing a third metal material in the opening through the second dielectric layer and in physical contact with the metal riser to form a source/drain contact via, an interface between the source/drain contact via and the metal riser having a second width that is smaller than the first width;
before depositing the second dielectric layer, recessing a second portion of the source/drain contact of the finFET device; and
depositing an etch stop layer in a recess of the second portion of the source/drain contact and in physical contact with the source/drain contact.

US Pat. No. 11,069,783

SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND PACKAGED SEMICONDUCTOR DEVICE

NUVOTON TECHNOLOGY CORPOR...


1. A semiconductor device, comprising:a semiconductor substrate that includes silicon and a first conductivity-type impurity;
a low-concentration impurity layer that is in contact with a front surface of the semiconductor substrate, and includes a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate;
a backside electrode that is in contact with a back surface of the semiconductor substrate, and includes a metal material;
a first vertical metal-oxide semiconductor (MOS) transistor that is located in a first region in the low-concentration impurity layer; and
a second vertical MOS transistor that is located in a second region adjacent to the first region in the low-concentration impurity layer in a plan view of the semiconductor substrate,
wherein the first vertical MOS transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer,
the second vertical MOS transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer,
the semiconductor substrate serves as a common drain region of a first drain region of the first vertical MOS transistor and a second drain region of the second vertical MOS transistor,
a thickness of the backside electrode ranges from 25 ?m to 35 ?m, inclusive, and
a ratio of the thickness of the backside electrode to a thickness of a semiconductor layer including the semiconductor substrate and the low-concentration impurity layer is 0.32 or more.

US Pat. No. 11,069,782

SEMICONDUCTOR DEVICE COMPRISING A GRADUALLY INCREASING FIELD DIELECTRIC LAYER AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Infineon Technologies AG


1. A semiconductor device, comprising:a transistor in a semiconductor body having a main surface, the transistor comprising:a source region;
a drain region;
a body region;
a drift zone;
a gate electrode at the body region, the body region and the drift zone being disposed along a first direction between the source region and the drain region, and the first direction being parallel to the main surface;
a field plate disposed in each of a plurality of field plate trenches, each of the plurality of field plate trenches having a respective longitudinal axis extending along the first direction in the drift zone; and
a field dielectric layer between the field plate and the drift zone, a first thickness of the field dielectric layer at a bottom of each of the plurality of field plate trenches gradually increases along the first direction, the first thickness being measured along a second direction, the second direction being perpendicular to the main surface and corresponding to a depth direction of the plurality of field plate trenches.


US Pat. No. 11,069,781

CRYSTALLINE SEMICONDUCTOR FILM, PLATE-LIKE BODY AND SEMICONDUCTOR DEVICE

FLOSFIA INC., Kyoto (JP)...


1. A semiconductor device comprising:a crystalline semiconductor film that comprises a corundum structured oxide semiconductor as a major component, the corundum structured oxide semiconductor that comprises an oxide comprising gallium and/or indium, and a thickness of the crystalline semiconductor film that is 1 ?m or more;
a Schottky electrode, the Schottky electrode that is arranged on the crystalline semiconductor film; and
wherein the semiconductor device further has a diode structure.

US Pat. No. 11,069,780

COATING LIQUID FOR FORMING OXIDE, METHOD FOR PRODUCING OXIDE FILM, AND METHOD FOR PRODUCING FIELD-EFFECT TRANSISTOR

Ricoh Company, Ltd., Tok...


1. A coating liquid for forming an oxide, the coating liquid comprising:A element, which is at least one alkaline earth metal; and
B element, which is at least one selected from the group consisting of gallium (Ga), scandium (Sc), yttrium (Y), and lanthanoid,
wherein when a total concentration of the A element is denoted by CA mg/L and a total concentration of the B element is denoted by CB mg/L, a total of concentrations of sodium (Na) and potassium (K) in the coating liquid is (CA+CB)/103 mg/L or less but not zero and a total of concentrations of chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), and copper (Cu) in the coating liquid is (CA+CB)/103 mg/L or less but not zero.

US Pat. No. 11,069,779

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

FUJI ELECTRIC CO., LTD., ...


1. A silicon carbide semiconductor device comprising:a first semiconductor layer of silicon carbide;
a device structure provided on top of the first semiconductor layer;
a second semiconductor layer of silicon carbide having a higher impurity concentration than the first semiconductor layer, provided below the first semiconductor layer, the second semiconductor layer implementing an ohmic-contact;
a silicide layer, formed by a silicidation reaction between a metallic layer and only the second semiconductor layer, having a thickness of 20 nm or less, provided below the second semiconductor layer; and
a metallic electrode film provided below the silicide layer;
wherein
a thickness of a carbon-containing region in which carbon-atoms are amorphously disposed inside the silicide layer is 10 nm or less and greater than zero nm, and is less than the thickness of the silicide layer.

US Pat. No. 11,069,778

SILICON CARBIDE COMPONENTS AND METHODS FOR PRODUCING SILICON CARBIDE COMPONENTS

Infineon Technologies AG,...


1. A method for producing a silicon carbide component, the method comprising:forming a silicon carbide layer on an initial wafer;
forming a doping region of the silicon carbide component to be produced in the silicon carbide layer;
forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer, the electrically conductive contact structure electrically contacting the doping region;
splitting at least one from the silicon carbide layer and the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off; and
forming a passivation layer on the surface of the silicon carbide layer before the splitting, wherein the electrically conductive contact structure is disposed within an opening in the passivation layer.

US Pat. No. 11,069,777

MANUFACTURING METHOD OF SELF-ALIGNED DMOS BODY PICKUP

Monolithic Power Systems,...


1. A manufacturing process of a DMOS device in a drift region of a first doping type in a semiconductor substrate, comprising:forming a polysilicon layer above the drift region;
forming a block layer above the polysilicon layer;
etching both the block layer and the polysilicon layer, through a window of a first masking layer to expose a window to the drift region;
implanting dopants of a second doping type through the window to the drift region to form a body region;
forming blocking spacers to wrap side walls of the polysilicon layer in a window of the polysilicon layer which is formed after etching;
implanting dopants of the second doping type into the body region under a window shaped by the blocking spacers to form a body pickup region;
etching away the blocking spacers;
performing a masking step to form gates;
forming ONO spacers to wrap side walls of the gates; and
performing a masking step to form source regions and drain pickup regions.

US Pat. No. 11,069,776

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...


1. A semiconductor device, comprising: a first active pattern that extends in a first direction on a first active region of a substrate;a first source/drain pattern in a recess of an upper portion of the first active pattern;
a gate electrode that runs across a first channel pattern of the upper portion of the first active pattern, wherein the gate electrode extends in a second direction different from the first direction and is provided on a top surface and at least one sidewall of the first channel pattern; and
an active contact electrically connected to the first source/drain pattern,
wherein, the recess, when viewed in a cross-section of the first active pattern taken along the first direction, includes:a first inner sidewall that extends, at a first angle with respect to a bottom surface of the substrate, from a top surface of the first active pattern toward the first channel pattern; and
a second inner sidewall that extends, at a second angle with respect to the bottom surface of the substrate different from the first angle, from the first inner sidewall toward a bottom of the recess,

the first source/drain pattern includes a first layer in a lower portion of the recess and a second layer on the first layer,
the first layer covers the second inner sidewall,
the second layer covers at least a portion of the first inner sidewall, the at least a portion of the first inner sidewall being exposed by the first layer,
the first layer has a side part on the second inner sidewall and a central part on the bottom of the recess, a height of the side part being higher than a height of the central part,
the first layer and the second layer include silicon-germanium (SiGe),
a concentration of germanium (Ge) in the first layer is in a range from 10 at % to 45 at %, and
a concentration of germanium (Ge) in the second layer is in a range from 50 at % to 70 at %,
wherein each of the first angle and the second angle is measured counterclockwise with respect to the bottom surface of the substrate and is an acute angle, and
wherein a maximum width of the recess is between the bottom of the recess and a boundary between the first inner sidewall and the second inner sidewall.

US Pat. No. 11,069,775

SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FORMATION IN STACKED-CHANNEL FETS

International Business Ma...


1. A method for forming a field effect transistor, comprising:for a stack of alternating layers of channel material and sacrificial material, with a layer of sacrificial material forming a top layer of the stack:selectively etching the sacrificial material to form recesses in the sacrificial material layers;
forming spacers in the recesses in direct contact with a dummy gate disposed over the stack, with at least one pair of spacers being formed in recesses above an uppermost layer of channel material extending above the top layer;
removing the dummy gate and the sacrificial material to expose the layers of channel material; and
forming a gate stack over and around the layers of channel material.


US Pat. No. 11,069,774

SHALLOW TRENCH ISOLATION STRUCTURE AND SEMICONDUCTOR DEVICE WITH THE SAME

Fujian Jinhua Integrated ...


1. A shallow trench isolation structure, comprising:a substrate;
at least one trench in the substrate;
a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench;
a first groove between the second dielectric layer and the substrate, wherein a topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and a topmost surface of the substrate; and
a fourth dielectric layer, located at a surface of an inner wall of the first groove; and
a fifth layer at the first groove, wherein the fifth layer is located in a groove formed by an inner wall of the fourth dielectric layer;
wherein a topmost surface of the fifth layer is lower than the topmost surface of the substrate.

US Pat. No. 11,069,772

TECHNIQUES FOR FABRICATING PLANAR CHARGE BALANCED (CB) METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) DEVICES

GENERAL ELECTRIC COMPANY,...


1. A charge balanced (CB) planar metal-oxide-semiconductor (MOS) device, comprising:a charge balanced (CB) layer defined within a first epitaxial (epi) layer and comprising a first conductivity type, wherein the CB layer includes a plurality of charge balanced (CB) regions of a second conductivity type;
a device layer defined in a second epi layer disposed on the CB layer, wherein the second epi layer comprises the first conductivity type and wherein the device layer includes a plurality of non-linear device cells that each comprise:a first base region of the second conductivity type disposed at an upper surface of the second epi layer;
a source region of the first conductivity type disposed at the upper surface of the second epi layer adjacent to the first base region;
a second base region of the first conductivity type disposed in the second epi layer adjacent to the source region;
a shield region of the second conductivity type disposed below the source region; and
a junction field-effect transistor (JFET) region of the first conductivity type disposed at the upper surface of the second epi layer adjacent to a channel region or the second base region;

a source contact disposed directly on the source region and the first base region in the second epi layer; and
a charge balanced (CB) bus region of the second conductivity type that extends between at least one of the plurality of CB regions of the CB layer and the shield region and electrically couples the at least one of the plurality of CB regions of the CB layer to the source contact via the shield region of at least one of the plurality of non-linear device cells.

US Pat. No. 11,069,771

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...


1. A semiconductor device comprising:a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side;
a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer;
a trench source structure including a source trench formed deeper than the gate trench and formed across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0;
a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench;
a source region of the first conductivity type formed in a surface layer portion of the body region; and
a drain electrode connected to the second main surface of the semiconductor layer;
wherein an aspect ratio of the trench source structure is greater than an aspect ratio of the trench gate structure.

US Pat. No. 11,069,770

CARRIER INJECTION CONTROL FAST RECOVERY DIODE STRUCTURES

IPOWER SEMICONDUCTOR, Gi...


1. A semiconductor device, comprising:a first conductivity type semiconductor substrate;
a drift region formed on top of the first conductivity type semiconductor substrate to support blocking of high voltage, the drift region being of a first conductivity type, the drift region comprising:a medium level doped buffer region on top,
a lightly doped middle region, and
a medium level doped field stop region or carrier storage region;

a shield region of a second conductivity type, the shield region comprising a deep junction encircling the medium level doped buffer region of the drift region; and
a second conductivity type shallow junction anode region in electrical contact with an anode electrode of the second conductivity type.

US Pat. No. 11,069,769

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...


1. A semiconductor device comprising:an N?-type drift layer;
a P-type well layer formed in a surface layer portion of an upper surface side of the N?-type drift layer;
an N-type emitter layer formed in a surface layer portion of the P-type well layer;
a gate electrode formed on an upper surface side of a semiconductor layer in which the N?-type drift layer, the P-type well layer, and the N-type emitter layer are formed;
an N-type buffer layer formed on a lower surface side of the N?-type drift layer;
a P-type collector layer formed on a lower surface side of the N-type buffer layer; and
an N++-type layer formed within the N-type buffer layer such that the P-type collector layer underlies an entirety of the N++-type layer, wherein
the N++-type layer has a maximum impurity concentration higher than a maximum impurity concentration of the N-type buffer layer and higher than a maximum impurity concentration of the P-type collector layer.

US Pat. No. 11,069,768

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...


1. A semiconductor device, comprising:a landing pad on a substrate;
a lower electrode on the landing pad and connected to the landing pad, the lower electrode including:an outer portion, the outer portion including first and second regions, and
an inner portion inside the outer portion;

a dielectric film on the lower electrode to extend along the first region of the outer portion; and
an upper electrode on the dielectric film,
wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion.

US Pat. No. 11,069,767

DISPLAY DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME

Samsung Electronics Co., ...


1. A display driving circuit comprising:a source driver configured to apply source data to a display panel;
a power supply circuitry configured to receive an external voltage from an external device and to generate a first voltage; and
a processing circuitry configured to receive the first voltage, to determine whether to change the external voltage, and to output a voltage change signal to the external device when the processing circuitry determines to change the external voltage.

US Pat. No. 11,069,766

DISPLAY PANEL WITH IRREGULAR SHAPE AND DISPLAY DEVICE

SHANGHAI TIANMA AM-OLED C...


1. A display panel with irregular shapes, comprising:a plurality of first constant-potential lines; and
a plurality of data lines with different lengths arranged in a display area of the display panel;
wherein the plurality of data lines is arranged at a different layer from the plurality of first constant-potential lines;
wherein the plurality of data lines each is intersected with at least one of the plurality of first constant-potential lines, wherein the intersecting lines have an overlapped area in a direction vertical to the display panel;
wherein the display area is divided into a plurality of display subareas in an extending direction of the first constant-potential lines;
wherein at least one of the plurality of the data lines is arranged in each of the display subareas; and
wherein for different display subareas, a shorter line in the plurality of the data lines in the display subareas corresponds to a larger total overlapped area of one of the plurality of data lines and one of the plurality of first constant-potential lines.

US Pat. No. 11,069,765

DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...


1. A manufacturing method of a display panel, comprising:forming a flexible substrate on a display area and a welding area of a glass substrate, wherein the glass substrate comprises the display area, the welding area, and an edge area;
forming a switch array layer on the flexible substrate and the edge area of the glass substrate, and patterning the switch array layer, such that the switch array layer corresponding to the display area serves as a switching element, and the switch array layer corresponding to the welding area serves as a metal wire, and a portion of the switch array layer on the edge area is removed, wherein the switch array layer comprises an active layer; and
forming an organic light-emitting display layer on the switch array layer, a portion of the flexible substrate that is not covered by the switch array layer, and the edge area of the glass substrate, and removing a portion of the organic light-emitting display layer on the metal wire and the edge area such that the edge area of the glass substrate is free from any thin film layers;
in steps of forming the switch array layer on the flexible substrate and the edge area of the glass substrate, and patterning the switch array layer, such that the switch array layer corresponding to the display area serves as the switching element, and the switch array layer corresponding to the welding area serves as the metal wire, and the portion of the switch array layer on the edge area is removed, comprising:
forming the active layer on the flexible substrate and the edge area of the glass substrate; and
patterning the active layer, such that the active layer corresponding to the display area forms a channel pattern, and a portion of the active layer on the edge area is removed;
wherein the switch array layer further comprises a first metal layer, and after a step of patterning the active layer, such that the active layer corresponding to the display area forms the channel pattern, and the portion of the active layer on the edge area is removed, the method further comprises:
forming a first insulating layer on the channel pattern, another portion of the flexible substrate that is not covered by the channel pattern, and the edge area of the glass substrate;
forming the first metal layer on the first insulating layer; and
patterning the first metal layer, such that the first metal layer corresponding to the display area serves as a gate, and a portion of the first metal layer on the edge area is removed.

US Pat. No. 11,069,764

DISPLAY PANEL AND DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...


1. A display panel, comprising a display region and a frame region disposed on both sides of the display region, wherein the frame region comprises a substrate and a base layer, a voltage signal trace, a planar layer, a lead-out trace, and a packaging layer that are sequentially disposed on the substrate, and the packaging layer extends to an outer side of the planar layer and is connected to the substrate;wherein the display region comprises the substrate and a driving circuit unit, the planar layer, and an anode that are sequentially disposed on the substrate, and the lead-out trace extends outward from a side of the anode and overlaps the voltage signal trace;
wherein a length of an overlapping portion between the lead-out trace and the voltage signal trace is greater than a length of an orthographic projection of the overlapping portion on the substrate;
wherein the base layer is provided with a plurality of trenches, and the voltage signal trace is formed on the base layer and the voltage signal trace is configured as a concave-convex structure;
wherein the display region further comprises a pixel defining layer, a cathode, and the packaging layer that are disposed on the anode; and
wherein the packaging layer corresponding to the display region comprises a first inorganic layer, an organic layer, and a second inorganic layer that are disposed on the cathode.

US Pat. No. 11,069,763

DISPLAY APPARATUS

Samsung Display Co., Ltd....


1. A display apparatus comprising:a display panel comprising a base substrate and a first pad electrode on a first pad portion of the base substrate;
a flexible substrate connected to the first pad portion, the flexible substrate comprising:a first film layer; and
a first wiring layer on the first film layer and comprising a first wiring, the first wiring comprising a first_first wiring and a first_second wiring, the first_first wiring and the first_second wiring extending in a same direction and along a same line, the first_first wiring and the first_second wiring being spaced from each other by a gap therebetween, the gap being at an edge of the base substrate in a plan view; and
a driving chip electrically connected to the flexible substrate.


US Pat. No. 11,069,762

DISPLAY DEVICE

Samsung Display Co., Ltd....


1. A display device comprising:a display panel including a display area for displaying an image and a non-display area, the non-display area including a bending region,
wherein the display panel in the bending region includes:
a plurality of connection wires,
a pattern including a plurality of electrodes, and
a protection layer positioned between the plurality of connection wires and the pattern,
wherein each electrode is insulated and is not configured to transmit electric signals, and
wherein the pattern is electrically isolated from the plurality of connection wires.

US Pat. No. 11,069,761

DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....


1. A display panel comprising:a substrate comprising a first area, a second area, and a third area located between the first area and the second area;
a display layer comprising a pixel circuit located in the second area and a display element electrically connected to the pixel circuit, the display element comprising a pixel electrode, a counter electrode, and an intermediate layer located between the pixel electrode and the counter electrode and comprising an emission layer and at least one organic layer;
a first metal layer located in the third area;
an organic insulating layer located on the first metal layer and comprising at least one contact portion; and
a second metal layer located on the organic insulating layer and contacting the first metal layer through the at least one contact portion,
wherein the second metal layer has a first hole, and the organic insulating layer has a second hole or a first recess corresponding to the first hole, and
a residual layer located in the second hole or the first recess and including a part of the at least one organic layer overlaps the first metal layer.

US Pat. No. 11,069,760

DISPLAY DEVICE WITH THROUGH HOLE DEFINED IN ELECTRONIC ELEMENT SETUP REGION CORRESPONDING TO ELECTRONIC ELEMENTS

WUHAN CHINA STAR OPTOELEC...


1. A display device, comprising a display panel and electronic elements, wherein the display panel comprises:a substrate;
a driving circuit layer disposed on the substrate;
a light-shielding layer disposed between the substrate and the driving circuit layer;
a planarization layer disposed on the driving circuit layer;
a pixel electrode layer disposed on the planarization layer;
a pixel definition layer disposed on the pixel electrode layer and defining a light-emitting region;
a light-emitting material layer disposed in the light-emitting region defined by the pixel definition layer; and
a common electrode layer disposed on the light-emitting material layer;
wherein in at least one of the driving circuit layer, the planarization layer, the pixel definition layer, or the common electrode layer, a through hole is defined in an electronic element setup region disposed corresponding to the electronic elements, and the through hole comprises a first-via hole, a second via-hole, a third via-hole, a fourth via-hole, and a fifth via hole, wherein the first via-hole is defined in the electronic element setup region and in the common electrode layer, the second via-hole is defined in the electronic element setup region and in the pixel definition layer, the third via-hole is defined in the electronic element setup region and in the planarization layer, the fourth via-hole is defined in the electronic element setup region and in the driving circuit layer, and the fifth via-hole is defined in the electronic element setup region and in the light-shielding layer; projections of the first via-hole, the second via-hole, the third via-hole, the fourth via-hole, and fifth via-hole projected on the substrate overlap each other; and a reflection component is disposed at a sidewall of the fifth via-hole to reflect a light from the electronic elements.

US Pat. No. 11,069,759

ORGANIC LIGHT-EMITTING DISPLAY DEVICE

Samsung Display Co., Ltd....


1. An organic light-emitting display device, comprising: a substrate;a pixel in a display area of the organic light-emitting display device, the pixel being implemented by an organic light-emitting diode on the substrate;
a first inclination structure surrounding the pixel in a plan view;
a second inclination structure at least partially surrounding the first inclination structure in a plan view, and being spaced apart from the first inclination structure in a direction away from the pixel; and
a planarization layer covering the first inclination structure and the second inclination structure and having a refractive index that is greater than a refractive index of the first inclination structure and is greater than a refractive index of the second inclination structure,
wherein a height of the first inclination structure is greater than a height of the second inclination structure, and
wherein the first and second inclination structures are in the display area between the organic light-emitting diode and an adjacent organic light-emitting diode in a plan view.

US Pat. No. 11,069,758

ORGANIC LIGHT-EMITTING DIODE DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING ORGANIC LIGHT-EMITTING DIODE DISPLAY SUBSTRATE AND DISPLAY DEVICE

HEFEI XINSHENG OPTOELECTR...


1. An OLED display substrate, comprising:an anode;
wherein the anode comprises a second transparent conductive pattern, and the second transparent conductive pattern, as a whole, correspond to a plurality of pixel opening regions;
the anode comprises a metal layer, and the metal layer comprises a first portions and a pixel definition layer transition patterns arranged alternately;
the anode further comprises a third transparent conductive pattern, the first portion and the third transparent conductive pattern are arranged in the corresponding pixel opening region;
a projection of the pixel defining layer transition pattern on the second transparent conductive pattern and a projection of the pixel opening region on the second transparent conductive pattern do not overlap;
the OLEO display substrate further comprises a pixel defining layer that is acquired by oxidizing the pixel defining layer transition pattern.

US Pat. No. 11,069,757

ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL AND METHOD FOR MAKING SAME

Interface Technology (Che...


1. An organic light emitting diode (OLED) display panel, comprising:a substrate;
a plurality of light emitting units on the substrate;
wherein each of the plurality of light emitting units comprises a light emitting element on the substrate and an electrochromic element on the substrate;
the electrochromic element comprises a first cathode, a first anode, and an electrochromic layer between the first cathode and the first anode;
the light emitting element comprises a second cathode, a second anode, and a light emitting material between the second cathode and the second anode; and
a portion of the second anode is shared with the first cathode;
wherein the first anode comprises a first metallic oxide layer on a surface of the substrate and a first metal layer between the first metallic oxide layer and the electrochromic layer;
the second anode comprises a second metallic oxide layer on the surface of the substrate, a metallic oxide layer between the light emitting material and the electrochromic layer and a second metal layer between the second metallic oxide layer and the metallic oxide layer;
the metallic oxide layer is shared with the first cathode.

US Pat. No. 11,069,756

DISPLAY PANEL, DISPLAY DEVICE AND METHOD FOR DRIVING DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...


1. A display panel, comprising a control unit layer, an organic light emitting device structure and a liquid crystal display device structure, wherein the control unit layer is electrically coupled to the organic light emitting device structure and the liquid crystal display device structure, respectively, and an electrode of the organic light emitting device structure and an electrode of the liquid crystal display device structure are at least partially shared,wherein the organic light emitting device structure at least comprises an anode, a cathode and a light emitting layer between the anode and the cathode, and the liquid crystal display device structure at least comprises a pixel electrode, a common electrode, a liquid crystal layer and a color filter layer; and the cathode of the organic light emitting device structure also serves as the pixel electrode or the common electrode of the liquid crystal display device structure,
wherein the anode, the light emitting layer, and the cathode of the organic light emitting device structure are disposed sequentially in a vertical direction, the cathode serves as the pixel electrode, and the liquid crystal layer, the common electrode and the color filter layer of the liquid crystal display device structure are disposed sequentially at a side of the cathode distal to the light emitting layer along a direction pointing away from the cathode, and
wherein the pixel electrode is made of a reflective conductive material.

US Pat. No. 11,069,755

FLEXIBLE DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING ELECTROCHROMIC PART

Samsung Display Co., Ltd....


1. A display panel comprising:a flexible electrochromic substrate comprising a first flexible substrate layer, a second flexible substrate layer opposing to the first flexible substrate layer, an electrochromic part disposed between the first and second flexible substrate layers and configured to discolor in response to a driving signal, a first barrier layer disposed on the first flexible substrate layer, and a second barrier layer disposed under the second flexible substrate layer;
a transistor layer disposed on the flexible electrochromic substrate, the transistor layer comprising a plurality of transistors; and
an organic light emitting diode layer disposed on the flexible electrochromic substrate on which the transistor layer is disposed, the organic light emitting diode layer comprising a plurality of organic light emitting diodes connected to the plurality of transistors,
wherein the second flexible substrate layer is disposed between the transistor layer and the second barrier layer,
wherein the electrochromic part comprises a first electrode, a second electrode, and an electrochromic layer, the electrochromic layer is disposed between the first electrode and the second electrode and overlaps the first electrode and the second electrode,
wherein the electrochromic part is directly disposed between the first barrier layer and the second barrier layer in an area where the electrochromic part overlaps the first barrier layer and the second barrier layer,
wherein the first barrier layer is in direct contact with the second barrier layer in an area where the electrochromic part does not overlap the first barrier layer and the second barrier layer, such that the electrochromic part is sealed by the first barrier layer and the second barrier layer,
wherein a first pad part is disposed on the first barrier layer in an outer area other than an area where the first barrier layer is in direct contact with the second barrier layer, the second barrier layer being not disposed in the outer area, and
wherein a second pad part is disposed in the area where the first barrier layer is in direct contact with the second barrier layer.

US Pat. No. 11,069,754

DISPLAY DEVICE

TIANMA MICROELECTRONICS C...


1. A display device comprising:a display panel including an active region including a display region where a user image is displayed and a measurement region including pixels with a same structure as pixels in the display region where an image to measure a property of the display panel is displayed;
a transparent front panel disposed on a front side of the display panel;
a bonding layer provided between the display panel and the front panel to avoid a first space and cover the display region, and bonding the display panel and the front panel together; and
a component placed in the first space, the component including a detector configured to detect a luminance factor of light emitted by the measurement region of the first space and flexible print circuits with the detector mounted thereon, the flexible print circuits extending from the first space to an outside of an interspace between the display panel and the front panel,
wherein the bonding layer includes a first outer side end face and a second outer side end face in addition to a face bonded with the display panel and a face bonded with the front panel, and
wherein the first space is formed inside of a first virtual face extending in parallel to the first outer side end face from an edge of the first outer side end face and a second virtual face extending in parallel to the second outer side end face from an edge of the second outer side end face.

US Pat. No. 11,069,753

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...


1. A display apparatus comprising:a light-source substrate portion which generates light; and
a color control portion to which the generated light from the light-source substrate portion is incident and at which color of the generated light is adjusted to define a color-converted light having a color different from that of the generated light,
wherein the color control portion comprises:an exit surface through which the color-converted light exits the color control portion;
a substrate comprising a plurality of concave portions defined therein, each of the concave portions comprising:a first portion and a second portion in order in a direction from the light-source substrate portion to the exit surface of the color control portion,
a width of the first portion and the second portion taken in a direction along the light-source substrate portion, and
in the direction from the light-source substrate portion to the exit surface of the color control portion;the width of the first portion increasing, and
the width of the second portion substantially constant; and


a plurality of color conversion members respectively in the plurality of concave portions, the color conversion members each comprising a color-converting material which converts the color of the generated light to the color of the color-converted light,
wherein each of the concave portions is concaved toward the light-source substrate portion.


US Pat. No. 11,069,752

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....


1. A display device comprising:a display area;
a color filter area disposed over the display area; and
a touch area disposed between the display area and the color filter area,
wherein the display area includes:a substrate on which a transistor is disposed;
an insulating layer disposed over the substrate and the transistor;
a first electrode connected with the transistor and disposed over the insulating layer;
a second electrode disposed over the first electrode;
a partition wall disposed between the insulating layer and the second electrode;
an emission layer disposed in an opening formed by the partition wall, and
a spacer disposed on the partition wall, and

wherein
the partition wall includes a first region overlapping the spacer and a second region not overlapping the spacer,
the color filter area includes:a first light blocking member disposed at a region overlapping the first region of the partition wall, the first light blocking member including at least two color filters stacked on each other; anda second light blocking membered disposed at a region overlapping the second region of the partition wall, and


the first light blocking member and the second light blocking member include different materials.

US Pat. No. 11,069,751

DISPLAY DEVICE

SAMSUNG ELECTRONICS CO., ...


1. A method of forming a display device, the method comprisingforming a light source comprisingdisposing an organic light emitting layer on a first electrode, the organic light emitting layer emitting a first light, the first electrode having a light reflectance for the first light of greater than or equal to about 60%
disposing a second electrode on the organic light emitting layer to form the light source, the second electrode having a light transmittance in a visible wavelength region of greater than or equal to about 70%,
wherein the light source has a first absorption peak in a wavelength region of about 650 nanometers to about 750 nanometers or a second absorption peak in a wavelength region of about 550 nanometers to about 600 nanometers at a viewing angle of about 55 degrees to about 85 degrees; and

disposing a color filter layer above the light source to form the display device, the color filter layer comprising a quantum dot configured to convert the first light into a second light.

US Pat. No. 11,069,750

FLEXIBLE COLOR FILTER, FLEXIBLE ORGANIC LIGHT EMITTING DISPLAY DEVICE COMPRISING SAME, AND MANUFACTURING METHOD THEREFOR

Dongwoo Fine-Chem Co., Lt...


1. A flexible color filter having a structure comprising:a base material film;
an adhesive layer formed on the base material film;
a separation layer formed on the adhesive layer;
a black matrix layer formed on the separation layer; and
a pixel layer formed between different portions of the black matrix layer,
wherein the separation layer is formed of a composition of A/C/D and A/B/D,
wherein the A is Acrylic series copolymer, the B is Acrylic series monomer, the C is Melamine series curing agent and the D is Propylene glycol mono methyl ether acetate.

US Pat. No. 11,069,748

ORGANIC ELECTROLUMINESCENCE DEVICE AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...


1. An organic electroluminescence device comprising:a plurality of pixels respectively configured to emit a predetermined light color from among a plurality of different light colors, each of the pixels respectively including a first electrode having light reflectivity, a second electrode, and an organic layer therebetween, the organic layer including an organic electroluminescence layer; and
a light shielding portion located on a light emission side of the organic layer, and including first apertures for the respective pixels,
the light shielding portion having a different angular shape for respective pixels based on the different light colors of the pixels.

US Pat. No. 11,069,747

DISPLAY DEVICE AND ELECTRONIC DEVICE HAVING MULTIPLE OVERLAPPING DISPLAY PANELS

Semiconductor Energy Labo...


1. A display device comprising:a first flexible display panel;
a second flexible display panel;
a resin layer; and
a protective substrate,
wherein the first flexible display panel comprises a first region configured to display an image, a second region having light-transmitting property, and a third region provided with a first flexible printed circuit (FPC),
wherein the second flexible display panel comprises a fourth region configured to display an image, a fifth region having light-transmitting property, and a sixth region provided with a second FPC,
wherein the first region is positioned between the second region and the third region,
wherein the fourth region is positioned between the fifth region and the sixth region,
wherein the first region overlaps with the fifth region,
wherein the fifth region is located between the first region and the protective substrate,
wherein the resin layer has a region in contact with the first region, the second region, the fourth region, and the fifth region,
wherein the protective substrate has a region that overlaps the first region and the fourth region with the resin layer in-between, and
wherein the third region has a curved region.

US Pat. No. 11,069,746

ELECTRONIC DEVICE

SK hynix Inc., Icheon (K...


1. An electronic device comprising a semiconductor memory,wherein the semiconductor memory includes:
first column lines extending in a first direction;
first row lines extending in a second direction intersecting the first direction;
first memory cells located between the first row lines and the first column lines;
second column lines electrically connected to the first column lines, the second column lines extending in the first direction;
second row lines extending in the second direction; and
second memory cells located between the second row lines and the second column lines,
wherein the first column lines and the second column lines overlap with each other in a third direction intersecting the first direction and the second direction,
wherein a first second column line belongs to a region in which current paths on the second row lines are shorter than current paths on the second row lines in a region a second second column line belongs to, and
wherein an overlapping ratio of the first second column line with a first first column line is smaller than an overlapping ratio of the second second column line with a second first column line.

US Pat. No. 11,069,745

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...


1. A memory device comprising:a substrate;
a CMOS circuit configured to perform operations to a memory element;
a memory array disposed above the CMOS circuit; and
a electrically connecting portion between the CMOS circuit and the memory array,
wherein the memory array comprises:a plurality of first wirings provided above the substrate, and extending horizontally;
a plurality of second wirings extending horizontally;
a plurality of third wirings extending vertically;
at least one memory element integrally formed between a third wiring of the plurality of third wirings and its crossing second wiring; and
at least one selector which selectively electrically couples the third wiring to one of the plurality of first wirings.


US Pat. No. 11,069,744

STEEP-SWITCH VERTICAL FIELD EFFECT TRANSISTOR

INTERNATIONAL BUSINESS MA...


1. A method for forming a semiconductor device, the method comprising:forming a semiconductor fin vertically extending from a bottom source or drain region of a substrate;
recessing a portion of the bottom source or drain region;
forming a bottom metallization layer on the recessed portion of the bottom source or drain region; and
forming a bi-stable resistive system on the bottom metallization layer.

US Pat. No. 11,069,743

NON-VOLATILE MEMORY ELEMENTS WITH A MULTI-LEVEL CELL CONFIGURATION

GLOBALFOUNDRIES SINGAPORE...


1. A structure comprising:a first non-volatile memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode;
a second non-volatile memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode;
a bit line strap coupled to the first electrode of the first non-volatile memory element and the first electrode of the second non-volatile memory element;
a first bit line coupled by the bit line strap to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element; and
a second bit line coupled to the second electrode of the first non-volatile memory element.

US Pat. No. 11,069,742

CROSSBAR ARRAY CIRCUIT WITH PARALLEL GROUNDING LINES

TetraMem Inc., Newark, C...


1. An apparatus comprising:a word line;
a bit line;
a first selector line;
a grounding line;
a first transistor comprising:a first source terminal;
a first drain terminal;
a first gate terminal; and
a first body terminal; and

an RRAM device connected in series with the first transistor, wherein the grounding line is connected to the first body terminal and is grounded, and the grounding line is parallel to the bit line, wherein the first selector line is connected to the first gate terminal.

US Pat. No. 11,069,740

IMAGE SENSOR GRID AND METHOD OF MANUFACTURING SAME

TAIWAN SEMICONDUCTOR MANU...


18. A method for forming a semiconductor device comprising:forming sensing regions over a frontside of a substrate;
forming an insulating layer over a backside of the substrate;
patterning a light reflective grid over the insulating layer, the light reflective grid defining first areas and second areas, each of the first areas at least partially overlapping with corresponding sensing regions on the frontside of the substrate, each of the second areas not overlapping with corresponding sensing regions on the frontside of the substrate;
forming an etch-stop layer over the insulating layer and the light reflective grid;
forming a filter layer over the etch-stop layer;
removing the filter layer from over the first areas while leaving portions of the filter layer over the second areas and at least a portion of the light reflective grid; and
forming optical layers over the backside.

US Pat. No. 11,069,739

IMAGING DEVICE AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...


1. An imaging device comprising:a pixel region including a first photoelectric converter;
an outside-pixel region including a second photoelectric converter coupled to a predetermined electric potential; and
a circuit substrate having one surface on which the first photoelectric converter and the second photoelectric converter are provided, the circuit substrate including a peripheral circuit electrically coupled to the first photoelectric converter.

US Pat. No. 11,069,738

INFRARED DETECTOR AND INFRARED SENSOR INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...


1. An infrared detector comprising:a substrate;
a first electrode, disposed on the substrate; and
an infrared-absorbing layer disposed on the first electrode, comprising a plurality of quantum dots configured to absorb infrared light having a width of wavelength band of about 50 nm or less within which a responsivity of the infrared light absorbed by the plurality of quantum dots is about 0.4 or more and generate a current corresponding to absorbed infrared light; and
a second electrode disposed on the infrared-absorbing layer,
wherein the first electrode, the infrared-absorbing layer, and the second electrode are sequentially arranged from the substrate, and the current generated in the infrared-absorbing flows in a direction perpendicular to the substrate.

US Pat. No. 11,069,737

SHALLOW TRENCH TEXTURED REGIONS AND ASSOCIATED METHODS

SiOnyx, LLC, Beverly, MA...


1. A photosensitive imager device capable of detecting visible and infrared electromagnetic radiation, comprising:a semiconductor layer having a light incident side and an opposed side, said semiconductor layer having multiple doped regions forming at least one junction,
a textured region comprising a plurality of surface features configured to interact with incident electromagnetic radiation so as to increase the quantum efficiency of the device, wherein the surface features are arranged according to a pattern,
a support substrate coupled to said semiconductor layer, and
a first bonding layer disposed between the semiconductor layer and the support substrate.

US Pat. No. 11,069,736

VIA SUPPORT STRUCTURE UNDER PAD AREAS FOR BSI BONDABILITY IMPROVEMENT

Taiwan Semiconductor Manu...


1. An integrated chip, comprising:a first interconnect wire disposed within a dielectric structure on a substrate;
a bond pad having a lower surface contacting the first interconnect wire;
a via layer vertically between the first interconnect wire and a second interconnect wire within the dielectric structure; and
wherein the via layer comprises:a plurality of support vias having a first size; and
a plurality of additional vias having a second size that is smaller than the first size, the plurality of support vias extending from directly under the lower surface of the bond pad to laterally past outermost edges of the lower surface of the bond pad.


US Pat. No. 11,069,735

SEMICONDUCTOR DEVICE AND IMAGING DEVICE

SONY CORPORATION, Tokyo ...


1. A light detecting device, comprising:a first substrate including a plurality of pixels in a pixel array and a first wiring layer, wherein the first wiring layer includes a first electrode and a second electrode; and
a second substrate including a signal processing region and a second wiring layer,
wherein the plurality of pixels outputs a plurality of pixel signals to the signal processing region,
wherein the second wiring layer includes a third electrode and a fourth electrode,
wherein the first electrode is bonded to the third electrode,
wherein the first electrode and the third electrode are electrically connected to each other,
wherein the first electrode is electrically connected to the first substrate,
wherein the third electrode is electrically connected to the second substrate,
wherein the second electrode and the fourth electrode are disposed outside of the pixel array,
wherein the second electrode is bonded to the fourth electrode,
wherein the second electrode and the fourth electrode are electrically connected to a potential that is different from the plurality of pixel signals,
wherein the second electrode and the fourth electrode each includes a plurality of cascading portions provided around perimeters of respective first and second wiring layers, and
wherein one of the cascading portions of each of the plurality of cascading portions provided around perimeters of the respective first and second wiring layers borders end portions of the respective first and second wiring layers.

US Pat. No. 11,069,734

IMAGE SENSOR DEVICE

INVENSAS CORPORATION, Sa...


1. A method, comprising:obtaining an image sensor wafer having a first dielectric layer with a first surface;
obtaining a reconstituted wafer having a processor die and a second dielectric layer with a second surface;
wherein the reconstituted wafer comprises the processor die, a controller die and a memory die structurally coupled to one another with a molding material to provide the reconstituted wafer; and
bonding the reconstituted wafer and the image sensor wafer to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer.

US Pat. No. 11,069,733

IMAGE SENSOR HAVING IMPROVED FULL WELL CAPACITY AND RELATED METHOD OF FORMATION

Taiwan Semiconductor Manu...


1. A method for forming an image sensor, the method comprising:forming a trench in a semiconductor substrate, wherein the trench extends into the semiconductor substrate from a back-side of the semiconductor substrate, and wherein forming the trench comprises:forming an initial trench in the semiconductor substrate, wherein the initial trench has a first depth; and
forming an extended trench in the semiconductor substrate by extending the initial trench to a second depth that is greater than the first depth;

forming an epitaxial layer that lines the trench, wherein the epitaxial layer comprises a dopant having a first doping type;
driving the dopant into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer; and
forming a dielectric layer over the back-side of the semiconductor substrate, wherein the dielectric layer fills the trench to form a back-side deep trench isolation (BDTI) structure.

US Pat. No. 11,069,732

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Canon Kabushiki Kaisha, ...


1. A semiconductor device comprising:a semiconductor layer that has a front surface on which a transistor is arranged and a back surface opposite to the front surface, wherein a virtual plane that includes the front surface and extends along the front surface is set as a first plane, a virtual plane that includes the back surface and extends along the back surface is set as a second plane, and a virtual plane that is positioned at an equal distance from the first plane and the second plane is set as a third plane;
a trench penetrating through the third plane and extending from the second plane, arranged in the semiconductor layer, and having a bottommost end;
a hollow part arranged in the trench; and
a solid material arranged in the trench and surrounding the hollow part between the first plane and the second plane in a direction crossing the first plane and the second plane,
wherein a center of the hollow part equidistant from a topmost end of the hollow part and a bottommost end of the hollow part in the direction crossing the first plane and the second plane is positioned between the first plane and the third plane,
wherein a distance between the center of the hollow part and the first plane is greater than a half of a length of the hollow part in the direction, and
wherein the solid material includes a layer that extends from the second plane to the bottommost end of the trench.

US Pat. No. 11,069,731

APPARATUS FOR REDUCING OPTICAL CROSS-TALK IN IMAGE SENSORS

TAIWAN SEMICONDUCTOR MANU...


1. A device comprising:a semiconductor substrate;
a plurality of color filters disposed above the semiconductor substrate;
a plurality of micro-lenses disposed above the plurality of color filters; and
a structure that is configured to block light radiation that is traveling towards a region between adjacent micro-lenses of the plurality of micro-lenses, wherein the structure and the plurality of color filters are at a same level at respective top most surfaces thereof.

US Pat. No. 11,069,730

SOLID-STATE IMAGING APPARATUS, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE

Sony Semiconductor Soluti...


1. A solid-state imaging apparatus comprising a plurality of pixels arranged in a pixel region, whereineach of the pixels has:
a first optical filter layer disposed on a photoelectric conversion unit;
a second optical filter layer disposed on the first optical filter layer;
a separation wall separating at least a part of the first optical filter layer for each of the pixels without separating the photoelectric conversion units and without separating the second optical filter layer from each other for each of the pixels,
wherein the separation wall comprises a metal core with a height smaller than a height of an oxide film provided within the separation wall; and
either the first optical filter layer or the second optical filter layer in at least one of the pixels is formed by an infrared cut filter, while another is formed by a color filter.

US Pat. No. 11,069,729

PHOTOELECTRIC CONVERSION DEVICE, AND EQUIPMENT

CANON KABUSHIKI KAISHA, ...


1. A photoelectric conversion device, comprising:a photoelectric conversion substrate having a plurality of photoelectric conversion portions and a microlens array arranged on the plurality of photoelectric conversion portions;
a light-transmitting plate covering the microlens array; and
a film arranged between the microlens array and the light-transmitting plate,
wherein the film has:
a refractive index within a range from 1.05 to 1.15,
an average transmittance of light in a wavelength region within a range from 400 nm to 700 nm of 98.5% or higher, and
a film thickness within a range from 500 nm to 5000 nm,
wherein the film contains a plurality of hollow particles and pores between the hollow particles, and
wherein a ratio of a total volume of the pores between the hollow particles relative to a unit volume of the film is within a range from 30.0% to 80.0%.

US Pat. No. 11,069,728

LOW NOISE VERTICAL GATE DEVICE STRUCTURE

Taiwan Semiconductor Manu...


1. An image sensor comprising:a photodetector disposed in a semiconductor substrate;
a floating diffusion node disposed in the semiconductor substrate and above the photodetector; and
a transfer gate electrode overlying the photodetector, wherein the transfer gate electrode has a top conductive body overlying a top surface of the semiconductor substrate and a bottom conductive body extending from the top conductive body to below the floating diffusion node, wherein a portion of the top conductive body directly overlies the floating diffusion node, wherein a first sidewall of the top conductive body is a substantially straight line and comprises an inner segment extending between opposing outer segments, wherein the inner segment directly overlies the bottom conductive body and the opposing outer segments directly overlie the floating diffusion node.

US Pat. No. 11,069,727

IMAGING ELEMENT HAVING TRANSFER GATE STRUCTURE COMPRISING A TRENCH

SONY CORPORATION, Tokyo ...


1. An imaging element, comprising:within a pixel:a semiconductor substrate;
a photoelectric conversion unit in the semiconductor substrate, wherein the photoelectric conversion unit is configured to generate a charge;
a first charge storage unit configured to store the charge generated by the photoelectric conversion unit;
a first transfer gate unit on an opposite surface of the semiconductor substrate, whereinthe opposite surface of the semiconductor substrate is on an opposite side of a light incident surface of the semiconductor substrate,
the first transfer gate unit is configured to transfer the charge from the photoelectric conversion unit to the first charge storage unit, and
the first transfer gate unit includes:a first electrode embedded in a first trench, wherein the first trench is in the semiconductor substrate from the opposite surface of the semiconductor substrate, and
a second electrode that surrounds at least a portion of a periphery of the first electrode; and


a light shielding film on the light incident surface of the semiconductor substrate, whereinthe light shielding film covers an entire bottom surface of the second electrode, and
the entire bottom surface of the second electrode faces the light incident surface of the semiconductor substrate.



US Pat. No. 11,069,726

METHOD OF MANUFACTURING DISPLAY DEVICE

Samsung Display Co., Ltd....


1. A method of manufacturing a display device, the method comprising:providing a substrate;
forming a first electrode, forming a second electrode spaced from the first electrode and in a same plane as the first electrode, forming a first alignment line connected to the first electrode and comprising a same material as the first electrode, and forming a second alignment line connected to the second electrode and comprising a same material as the second electrode on the substrate;
self-aligning a plurality of light emitting elements by providing a solution containing the plurality of light emitting elements on the substrate having thereon the first and second electrodes and the first and second alignment lines, and supplying voltages to the first alignment line and the second alignment line;
removing the first alignment line and the second alignment line from the substrate on which the plurality of light emitting elements are self-aligned;
forming a first contact electrode electrically connecting one end of each light emitting element of the plurality of light emitting elements to the first electrode; and
forming a second contact electrode electrically connecting an other end of each light emitting element to the second electrode.

US Pat. No. 11,069,725

DISPLAY SUBSTRATE AND METHOD OF PREPARING THE SAME, AND DISPLAY DEVICE

HEFEI XINSHENG OPTOELECTR...


1. A method of preparing a display substrate, comprising:providing a substrate;
forming a switching thin film transistor precursor and a driving thin film transistor precursor on the substrate respectively, each of the switching thin film transistor precursor and the driving thin film transistor precursor comprising a semiconductor layer, a gate insulating material layer and a gate metallic layer which are stacked sequentially above the substrate;
forming a photoresist layer above the switching thin film transistor precursor and the driving thin film transistor precursor, and forming an etching mask from the photoresist layer, a first portion of the etching mask at the switching thin film transistor precursor and a second portion of the etching mask at the driving thin film transistor precursor having different shapes; and
forming a switching thin film transistor and a driving thin film transistor, by performing an etching processing on the switching thin film transistor precursor and the driving thin film transistor precursor with the etching mask,
wherein performing the etching processing on the switching thin film transistor precursor and the driving thin film transistor precursor comprises:forming a gate of the switching thin film transistor and a gate of the driving thin film transistor by performing a wet etching on the gate metallic layer with the etching mask;
forming a gate insulating layer of the switching thin film transistor and a gate insulating layer of the driving thin film transistor by performing a dry etching on the gate insulating material layer merely with the etching mask; and
forming an active layer and connecting lines of the switching thin film transistor, and an active layer and connecting lines of the driving thin film transistor, by transforming a portion of the semiconductor layer in a region outside a channel region into a conductor, and

wherein the etching mask is formed by a half-tone mask exposure technology, and wherein:a thickness of the first portion of the etching mask at the switching thin film transistor precursor is larger than a thickness of the second portion of the etching mask at the driving thin film transistor precursor; and
a slope angle of the first portion of the etching mask at the switching thin film transistor precursor is larger than a slope angle of the second portion of the etching mask at the driving thin film transistor precursor.


US Pat. No. 11,069,724

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE USING THE SAME

Wuhan China Star Optoelec...


1. A method for manufacturing a display device, comprisingproviding an array substrate comprising a polysilicon layer and insulating layer being disposed in a stacked manner;
introducing a first mixed gas to deposit an amorphous silicon layer;
introducing a second mixed gas to deposit the insulating layer on the amorphous silicon layer, wherein the insulating layer covers the amorphous silicon layer, the second mixed gas is a mixed gas of SiH4 and NH3;
dehydrogenating the amorphous silicon layer; and
performing an excimer laser annealing process on the dehydrogenated amorphous silicon layer to transform the amorphous silicon layer into the polysilicon layer while the insulating layer is covering the amorphous silicon layer;
wherein, an amorphous silicon layer and an insulating layer covering the amorphous silicon layer are formed during performing one same process of chemical vapor deposition (CVD), the polysilicon layer has a first side face and a second side face, the insulating layer has a third side face and a fourth side face, the first side face is flushed with the third side face, and the second side face is flushed with the fourth side face.

US Pat. No. 11,069,723

METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, AND DISPLAY APPARATUS

Chengdu CEC Panda Display...


1. A method for manufacturing a thin film transistor, comprising:forming a gate layer on a substrate;
forming a gate insulating layer on the gate layer;
forming an active layer on the gate insulating layer;
forming a source/drain layer on the active layer; and
performing a plasma bombardment treatment on a surface of the active layer on which the source/drain layer is formed, and controlling the plasma bombardment treatment to be performed at a gas flow rate of 4K sccm to 70K sccm, at a pressure of 600 mTorr to 1200 mTorr, at a power of 4 KW to 12 KW for a treatment time of 10 s to 60 s.

US Pat. No. 11,069,722

ACTIVE MATRIX SUBSTRATE AND METHOD OF MANUFACTURING SAME

SHARP KABUSHIKI KAISHA, ...


1. An active matrix substrate having a displaying region including a plurality of pixels and a non-displaying region located around the displaying region, the active matrix substrate comprising:a substrate;
a plurality of first TFTs supported by the substrate and provided in the non-displaying region;
a peripheral circuit including the plurality of first TFTs; and
a plurality of second TFTs supported by the substrate and provided in the displaying region and/or the non-displaying region; wherein
each of the plurality of first TFTs includes:a first gate electrode provided on the substrate;
a first gate insulating layer covering the first gate electrode;
a first oxide semiconductor layer opposed to the first gate electrode via the first gate insulating layer, the first oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on opposite sides of the channel region;
a first source electrode connected to the source contact region of the first oxide semiconductor layer; and
a first drain electrode connected to the drain contact region of the first oxide semiconductor layer;

each of the plurality of first TFTs includes a bottom contact structure such that the first source electrode and the first drain electrode are in contact with a lower face of the first oxide semiconductor layer;
a first region of the first gate insulating layer that overlaps the channel region has a thickness which is smaller than a thickness of a second region of the first gate insulating layer that overlaps the source contact region and the drain contact region;
each of the plurality of second TFTs includes:a second gate electrode provided on the substrate;
a second gate insulating layer covering the second gate electrode;
a second oxide semiconductor layer opposed to the second gate electrode via the second gate insulating layer, the second oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on opposite sides of the channel region of the second oxide semiconductor layer;
a second source electrode connected to the source contact region of the second oxide semiconductor layer; and
a second drain electrode connected to the drain contact region of the second oxide semiconductor layer;

each of the plurality of second TFTs has a top contact structure such that the second source electrode and the second drain electrode are in contact with an upper face of the second oxide semiconductor layer; and
a third oxide semiconductor layer which covers the channel region of the second oxide semiconductor layer is provided the third oxide semiconductor layer is in a same layer as the first oxide semiconductor layer.

US Pat. No. 11,069,721

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...


1. A display device, comprising:a substrate having an active area, a non-active area around the active area, and a pad portion at one side of the non-active area;
a plurality of printed circuit films in the pad portion, each of the printed circuit films having a drive Integrated circuit (IC), the printed circuit films being spaced a first distance apart from an edge of the substrate in a first direction and being spaced apart from each other at regular intervals in a second direction that intersects the first direction;
a first-layer line and a second-layer line within the first distance between the printed circuit films and the edge of the substrate so that the first-layer line and the second-layer line are respectively adjacent to the printed circuit films each in the first direction; and
a plurality of dummy patterns on a same layer as the second-layer line in a region between two adjacent ones of the printed circuit films, the plurality of dummy patterns having island shapes, respectively.

US Pat. No. 11,069,720

DISPLAY PANEL AND DISPLAY DEVICE

SHANGHAI TIANMA AM-OLED C...


1. A display panel, comprising: a display area and a non-display area adjacent to the display area, wherein the display area includes: a first display area and a second display area;the first display area and the second display area comprise a plurality of pixels arranged in an array, a plurality of data lines extending in a column direction and arranged in a row direction, and a plurality of fixed potential signal lines extending in the column direction and arranged in the row direction, with the row direction being perpendicular to the column direction; the data lines and the fixed potential signal lines are arranged in a same layer, and a quantity of pixels in each column of pixels in the first display area is less than that of pixels in any column of pixels in the second display area; and
the first display area further comprises compensation lines, wherein the compensation line and the fixed potential signal lines are electrically connected and arranged in different layers, the compensation lines and the data lines are insulated from each other, and there is an overlapping area between each of the compensation lines and each of the data lines in a direction perpendicular to the display panel;
wherein the first display area comprises at least a first column of pixels and a second column of pixels with different quantity of pixels, and a quantity of pixels in the first column of pixels is less than a quantity of pixels in the second column of pixels;
there is a first overlapping area between a data line and a compensation line corresponding to the first column of pixels, and there is a second overlapping area between a data line and a compensation line corresponding to the second column of pixels; and
the first overlapping area is larger than the second overlapping area.

US Pat. No. 11,069,719

ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, DISPLAY DEVICE

BEIJING BOE DISPLAY TECHN...


1. An array substrate, comprising:a base substrate;
a plurality of signal lines disposed at a side of the base substrate; and
an organic layer disposed at a side of the plurality of signal lines facing away from the base substrate, wherein
the organic layer includes at least one auxiliary portion and a reference portion surrounding the at least one auxiliary portion, and a thickness of each auxiliary portion is less than a thickness of the reference portion;
the thickness of each auxiliary portion is less than or equal to one third of the thickness of the reference portion, and the thickness of each auxiliary portion is less than or equal to a value in a range of 0.8 ?m to 1.2 ?m; and
the at least one auxiliary portion includes a plurality of auxiliary portions, and thicknesses of the plurality of auxiliary portions are the same.

US Pat. No. 11,069,718

DISPLAY DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...


1. A display device comprising:a pixel comprising:a capacitor;
a first transistor;
a second transistor; and
a light-emitting element,

wherein the first transistor comprises a first gate electrode, a second gate electrode and an oxide semiconductor layer over the first gate electrode and under the second gate electrode,
wherein the second transistor comprises a first gate electrode, a second gate electrode and an oxide semiconductor layer over the first gate electrode and under the second gate electrode,
wherein the first gate electrode of the first transistor is not connected to the second gate electrode of the first transistor in a pixel region,
wherein the first gate electrode of the first transistor is electrically connected to a scan line,
wherein the second gate electrode of the second transistor is electrically connected to the first gate electrode of the second transistor, and
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the light-emitting element.

US Pat. No. 11,069,717

METAL OXIDE AND FIELD-EFFECT TRANSISTOR

Semiconductor Energy Labo...


1. A semiconductor device comprising:a transistor comprising a channel formation region; and
a light-emitting element electrically connected to the transistor,
wherein the channel formation region comprises a first nano-size region comprising indium, gallium, and zinc and a second nano-size region comprising indium, gallium, and zinc,
wherein the number of gallium atoms in the first nano-size region is larger than the number of gallium atoms in the second nano-size region, and
wherein the first nano-size region and the second nano-size region have different crystal structures.

US Pat. No. 11,069,715

MEMORY STRUCTURE

Powerchip Semiconductor M...


8. A memory structure, comprising:a silicon-on-insulator substrate, comprising a silicon base, and a first dielectric layer and a silicon layer sequentially disposed on the silicon base;
a first transistor and a second transistor, disposed on the silicon layer;
an isolation structure, disposed in the silicon layer between the first transistor and the second transistor;
a capacitor, disposed between the first transistor and the second transistor, and comprising:a body portion;
a first extension portion, extending from the body portion to a source/drain region of the first transistor and connected to the source/drain region of the first transistor;
a second extension portion, extending from the body portion to a source/drain region of the second transistor and connected to the source/drain region of the second transistor;
a third extension portion, extending from the body portion, penetrating through the isolation structure, and extending into the first dielectric layer, and comprising a first part and a second part, wherein the second part is located in the first dielectric layer, and a projection area of the second part on the silicon base is greater than a projection area of the first part on the silicon base; and
a liner layer, disposed between the first extension portion and the third extension portion, between the second extension portion and the third extension portion, between the isolation structure and the third extension portion, and between the first dielectric layer and the third extension portion,
wherein each of the body portion, the first extension portion, the second extension portion and the third extension portion is composed of a lower electrode, an upper electrode and an insulating layer between the lower electrode and the upper electrode.


US Pat. No. 11,069,714

BOUNDARY SCHEME FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FORMING AN INTEGRATED CIRCUIT

TAIWAN SEMICONDUCTOR MANU...


1. An integrated circuit comprising:a substrate comprising a first region and a second region;
a first isolation structure disposed in the substrate and separating the first region from the second region, wherein the first isolation structure has a first top surface and a second top surface lower than the first top surface;
a first device disposed in the first region;
a second device disposed in the second region; and
a semiconductor dummy structure disposed on the first isolation structure, wherein the semiconductor dummy structure covers a portion of the first top surface, a portion of the second top surface and a boundary between the first top surface and the second top surface.

US Pat. No. 11,069,713

SEMICONDUCTOR MEMORY ELEMENT, OTHER ELEMENTS, AND THEIR PRODUCTION METHODS

NATIONAL INSTITUTE OF ADV...


1. A semiconductor memory element, comprising:a semiconductor substrate having a source region and a drain region;
a buffer insulator formed on the semiconductor substrate;
a stacked ferroelectric formed on the buffer insulator;
a stacked conductor formed on the stacked ferroelectric; and
a partition wall surrounding a side surface of the stacked ferroelectric,
wherein a cross-sectional area of the stacked ferroelectric parallel with the semiconductor substrate is narrowest at a bottom surface of the stacked ferroelectric, a length (L) between the source region and the drain region being equal to or smaller than 100 nm,
a distance (H) between the stacked conductor and the bottom surface of the stacked ferroelectric is equal to or greater than double the length (L),
the semiconductor memory element has an intensity of the memory function that becomes stronger as L decreases in a range of L?(2×k×d) and that disappears when L>(2×k×d),
where d: a controlled film thickness of the stacked ferroelectric which is measured on a flat surface, and
k: a ratio of ferroelectric film-forming speed on an inner wall surface and a horizontal surface of a groove defined by the partition wall, where 0

US Pat. No. 11,069,712

THREE-DIMENSIONAL MEMORY DEVICE

Yangtze Memory Technologi...


1. A three-dimensional (3D) memory device, comprising:a substrate;
an alternating conductive/dielectric stack disposed on the substrate, the alternating conductive/dielectric stack comprising a plurality of dielectric layers and a plurality of conductive layers alternately stacked in a vertical direction perpendicular to a surface of the substrate;
an epitaxial layer disposed between the substrate and the alternating conductive/dielectric stack in the vertical direction; and
a vertical structure penetrating the alternating conductive/dielectric stack in the vertical direction for being partly disposed in the epitaxial layer, wherein the epitaxial layer comprises a protruding part disposed between the vertical structure and a bottom dielectric layer of the alternating conductive/dielectric stack in a horizontal direction orthogonal to the vertical direction, wherein the epitaxial layer is a doped well region comprising the protruding part and disposed on the substrate.

US Pat. No. 11,069,711

3-DIMENSIONAL NOR MEMORY ARRAY WITH VERY FINE PITCH: DEVICE AND METHOD

SUNRISE MEMORY CORPORATIO...


1. A process for forming a memory structure, comprising:forming first and second multi-layer semiconductor structures above a planar surface of a semiconductor substrate separated from each other by a trench with a depth along a first direction substantially perpendicular to the planar surface, the trench having a predetermined width along a second direction substantially parallel the planar surface;
forming in the trench a first group of conductors extending along the first direction, each conductor comprising a first conductive material and each conductor being isolated from each adjacent multi-layer semiconductor structure by a first charge-trapping material, wherein the conductors within each trench are separated from each other by a predetermined distance; and
forming a second group of conductors extending along the first direction, each conductor in the second group of conductors being provided between two adjacent ones of the first group of conductors, each conductor of the second group of conductors comprising a second conductive material and each conductor in the second group of conductors being isolated from its adjacent multi-layer semiconductor structure by a second charge-trapping material;
wherein each conductor in the first or the second group of conductors and a portion of the first or second charge-trapping material between that conductor one of the multi-layer semiconductor structure form a gate electrode and a storage layer for a thin-film storage transistor.

US Pat. No. 11,069,710

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...


1. A semiconductor memory device comprising:a substrate;
a memory cell array provided on the substrate, the memory cell array including a plurality of memory cells;
a transistor provided on the substrate, the memory cell array and the transistor being arranged along the substrate, the transistor including a gate electrode and a gate insulating layer, the gate electrode being provided above the substrate, the gate insulating layer being provided between the gate electrode and the substrate;
a first insulating layer provided on the substrate, the first insulating layer including first and second parts arranged along a surface of the substrate, the first and second parts being spaced from one another, the first and second parts of the first insulating layer and the transistor being arranged along the substrate, the transistor being provided between the memory cell array and the first part of the first insulating layer, the first part of the first insulating layer being provided between the transistor and the second part of the first insulating layer,
a second insulating layer provided on the first insulating layer, the second insulating layer being in contact with the substrate at the space between the first and second parts of the first insulating layer.

US Pat. No. 11,069,709

VERTICAL MEMORY DEVICES

Samsung Electronics Co., ...


1. A vertical memory device, comprising:a substrate, an upper portion of the substrate including an impurity region doped with impurities;
a gate electrode structure on the substrate, the gate electrode structure including gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, the gate electrode structure including at least one first gate electrode serving as a selection line, and a plurality of second gate electrodes serving as word lines, respectively, over the at least one first gate electrode; and
a channel extending through the gate electrode structure in the vertical direction to contact the impurity region of the substrate, the channel including a first portion and a second portion sequentially stacked,the first portion having a slanted sidewall with respect to the upper surface of the substrate, a width of an upper surface of the first portion being greater than a width of a lower surface thereof, and
a width of an upper surface of the second portion being less than the width of the upper surface of the first portion,

wherein the upper surface of the first portion of the channel is higher than an upper surface of the at least one first gate electrode, and
wherein a lower surface of a lowermost one of the plurality of second gate electrodes is higher than the upper surface of the first portion of the channel.

US Pat. No. 11,069,708

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

MACRONIX INTERNATIONAL CO...


1. A method for manufacturing a memory device, comprising:forming a hole in an oxide-nitride stack;
forming a vertical channel structure and a charge trapping structure in an inner wall of the hole;
forming a first opening and a second opening partially overlapping the hole and penetrating the vertical channel structure, wherein the vertical channel structure is divided into two arc channel parts by the first opening and the second opening;
forming a drain pillar structure and a source pillar structure in the first opening and the second opening respectively; and
forming a gate structure surrounding the drain pillar structure, the source pillar structure and the vertical channel structure.

US Pat. No. 11,069,707

VARIABLE DIE SIZE MEMORY DEVICE AND METHODS OF MANUFACTURING THE SAME

SANDISK TECHNOLOGIES LLC,...


1. A semiconductor die comprising:a plurality of alternating stacks of insulating layers and electrically conductive layers that are laterally separated from each other by first backside trenches that laterally extend along a first horizontal direction;
an array of memory stack structures vertically extending through each of the plurality of alternating stacks;
an inner edge seal structure that continuously laterally surrounds the plurality of alternating stacks;
an outer edge seal structure that continuously laterally surrounds the inner edge seal structure; and
additional alternating stacks of insulating layers and electrically conductive layers located between the inner edge seal structure and the outer edge seal structure.

US Pat. No. 11,069,706

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES

SAMSUNG ELECTRONICS CO., ...


1. A three-dimensional (3D) semiconductor memory device, comprising:a substrate including a cell array region and a connection region;
a stack structure disposed on the substrate and comprising a plurality of electrodes and first insulating layers disposed between the electrodes, the stack structure having a stair structure on the connection region;
a vertical channel structure penetrating the stack structure on the cell array region; and
a vertical dummy structure penetrating at least a portion of the stair structure on the connection region,
wherein the stack structure further comprises: a second insulating layer selectively disposed on the cell array region and not disposed on the connection region,
wherein a maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer,
wherein the vertical channel structure includes a portion of abrupt diameter change at a level of a top surface of the second insulating layer,
wherein the portion of abrupt diameter change has: a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer, and
wherein an upper portion of the portion of abrupt diameter change has a first diameter, and a lower portion of the portion of abrupt diameter change has a second diameter that is greater than the first diameter.

US Pat. No. 11,069,705

THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

Yangtze Memory Technologi...


1. A three-dimensional (3D) memory device, comprising:a channel structure region including a plurality of channel structures;
a first staircase structure in a first staircase region including a number X1 of division block structures arranged along a first direction on a first side of the channel structure region; and
a second staircase structure in a second staircase region including the number X1 of division block structures arranged along the first direction on a second side of the channel structure region;
a top select gate staircase structure including a number X2 of steps arranged along a second direction in the channel structure region;
wherein a first vertical offset defines a boundary between adjacent division block structures, and each division block structure includes a number X3 of staircases arranged along the second direction that is different from the first direction, each staircase including a plurality of steps arranged along the first direction, and the first vertical offset between adjacent division block structures equals to 2X2X3 times a thickness of one step.

US Pat. No. 11,069,704

3D NOR MEMORY HAVING VERTICAL GATE STRUCTURES

MACRONIX INTERNATIONAL CO...


1. A memory device, comprising:a plurality of stacks of bit lines alternating with insulating strips over an insulating layer on a substrate, wherein the stacks of bit lines are separated by trenches having a first width;
a plurality of vertical gate structures disposed between the stacks;
vertical channel structures and memory elements disposed between outside surfaces of the vertical gate structures and sidewalls of insulating strips in the stacks of bit lines, the vertical channel structures providing channels between adjacent bit lines in the stacks; and
insulating structures separating the vertical gate structures, the vertical channel structures, and the memory elements in the trenches, wherein the insulating structures have a second width greater than the first width.

US Pat. No. 11,069,703

THREE-DIMENSIONAL DEVICE WITH BONDED STRUCTURES INCLUDING A SUPPORT DIE AND METHODS OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...


10. A bonded assembly comprising:a first semiconductor die comprising a first substrate including a first distal planar surface and a first proximal planar surface, first semiconductor devices located on, or over, the first proximal planar surface of the first substrate, first interconnect-level dielectric layers including first metal interconnect structures that are electrically connected to the first semiconductor devices, and first die-to-die bonding pads located at a surface portion of the first interconnect-level dielectric layers and electrically connected to the first metal interconnect structures; and
a second semiconductor die comprising a second substrate including a second distal planar surface and a second proximal planar surface, second semiconductor devices located on, or over, the second proximal planar surface of the second substrate, second interconnect-level dielectric layers including second metal interconnect structures that are electrically connected to the second semiconductor devices, and second die-to-die bonding pads located at a surface portion of the second interconnect-level dielectric layers and electrically connected to the second metal interconnect structures, wherein the second die-to-die bonding pads are bonded to the first die-to-die bonding pads to provide die-to-die bonding between the first semiconductor die and the second semiconductor die;
a first external bonding pad located on, or over, the second distal planar surface of the second substrate;
a first laterally-insulated external connection via structure vertically extending at least from the second distal planar surface of the second substrate, through the second substrate, the second interconnect-level dielectric layers, a horizontal plane including an interface between the first semiconductor die and the second semiconductor die, and a subset of layers within the first interconnect-level dielectric layers, and to one of the first metal interconnect structures and contacting the first external bonding pad;
a second external bonding pad located on, or over, the second distal planar surface of the second substrate; and
a second laterally-insulated external connection via structure contacting the second external bonding pad and vertically extending at least from the second distal planar surface of the second substrate, through the second substrate, the second interconnect-level dielectric layers, the horizontal plane including the interface between the first semiconductor die and the second semiconductor die, and another subset of layers within the first interconnect-level dielectric layers, and to an additional one of the first metal interconnect structures that is located at a different vertical distance from the interface between the first semiconductor die and the second semiconductor die than the one of the first metal interconnect structures is from the interface between the first semiconductor die and the second semiconductor die.

US Pat. No. 11,069,702

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TOSHIBA MEMORY CORPORATIO...


1. A semiconductor device comprising:a stack comprising a plurality of conductive layers stacked and separated from each other in a first direction;
an insulating layer provided above the stack;
a columnar portion extending through the plurality of conductive layers and the insulating layer in the first direction;
wherein the columnar portion includes a core layer extending through at least one of the conductive layers in the first direction, a first semiconductor layer located between the core layer and the plurality of conductive layers, a memory layer located between the first semiconductor layer and the plurality of conductive layers, and a second semiconductor layer that is located above the core layer and contacts the first semiconductor layer, and
wherein the second semiconductor layer includes a first region containing phosphorous, and a second region that contains carbon and phosphorous, and
the second region includes a first sub-region provided between the core layer and the first region of the second semiconductor layer in the first direction and a second sub-region provided between the insulating layer and the first region of the second semiconductor layer.

US Pat. No. 11,069,701

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR

TOSHIBA MEMORY CORPORATIO...


1. A semiconductor memory device comprising:a first conductive layer;
a plurality of second conductive layers that extend in a first direction and are stacked above the first conductive layer in a second direction;
a third conductive layer between the first conductive layer and the plurality of second conductive layers;
a memory pillar that extends inside the plurality of second conductive layers in the second direction;
a first insulating layer that extends in the first direction, and isolates the plurality of second conductive layers in a third direction orthogonal to the first direction and the second direction; and
a plurality of second insulating layers spaced from an end of the first insulating layer and aligned along the third direction, each of the second insulating layers extending in the third direction,
wherein the plurality of second insulating layers are spaced from an extension line of the first insulating layer that extends in the first direction,
wherein the first conductive layer includes a region that overlaps in the second direction an intersection region in which the extension line of the first insulating layer intersects an extension line in which the plurality of second insulating layers are aligned, and
wherein the third conductive layer does not overlap the intersection region in the second direction.

US Pat. No. 11,069,700

SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...


1. A semiconductor storage device comprising:a first stacked body that comprises a plurality of first electrode layers stacked in a first direction;
a second stacked body, disposed above the first stacked body, that comprises a plurality of second electrode layers stacked in the first direction;
a first pillar, extending in the first direction through the first stacked body, that comprises a first semiconductor layer;
a second pillar, extending in the first direction through the second stacked body, that comprises a second semiconductor layer, the second semiconductor layer electrically connected to the first semiconductor layer;
a first charge storage layer provided between the plurality of first electrode layers and first semiconductor layer;
a second charge storage layer provided between the plurality of second electrode layers and second semiconductor layer;
a first division film, extending in the first direction through the first stacked body, that divides the first stacked body in a second direction crossing the first direction;
a second division film, extending in the first direction through the second stacked body, that divides the second stacked body in the second direction; and
a plurality of first films, extending in the first direction through the second stacked body and separated from each other in a third direction crossing the first direction and the second direction, that are disposed above the first division film, a material of each of the plurality of first films identical to a material of the first division film.

US Pat. No. 11,069,699

NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FORMING SAME

Cypress Semiconductor Cor...


1. A method of forming a non-planar non-volatile memory (NVM) string, comprising:forming alternating dielectric layers and gate layers over a substrate and forming an opening through the alternating dielectric and gate layers;
forming a first stack of layers including a charge trapping layer on an inner surface of the opening;
forming a channel layer adjacent to the first stack of layers within the opening and extending from a source in the substrate to a drain overlying the substrate, wherein:
the channel layer connects serially a plurality of core cells between a source select gate and a drain select gate, wherein at least one of the source and drain select gates is a stacked select gate; and
at least one gate layer forms at least a portion of an internal wordline of one of the plurality of core cells and is separated from the channel layer by the first stack of layers.

US Pat. No. 11,069,697

3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES

Monolithic 3D Inc., Klam...


1. A 3D memory device, the device comprising:a plurality of memory cells,wherein each of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain and a channel;

a plurality of bit-line pillars,wherein each of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
wherein said bit-line pillars are vertically oriented,
wherein said channel is horizontally oriented, and
wherein said channel comprises a circular shape or an ellipsoidal shape.


US Pat. No. 11,069,696

DEVICE STRUCTURE FOR A 3-DIMENSIONAL NOR MEMORY ARRAY AND METHODS FOR IMPROVED ERASE OPERATIONS APPLIED THERETO

SUNRISE MEMORY CORPORATIO...


1. A thin-film storage transistor in a memory string, comprising:first and second semiconductor layers of a first conductivity, serving as a drain terminal and a source terminal of the thin-film storage transistor, respectively;
a third semiconductor layer of a second conductivity adjacent the first and second semiconductor layers, serving as a channel region of the thin-film storage transistor;
a conductor serving as a gate terminal of the thin-film storage transistor;
a charge-trapping region between the conductor and third semiconductor layer;
a fourth semiconductor layer of the second conductivity provided in close proximity to the third semiconductor layer and having a dopant concentration substantially equal to or great than the dopant concentration of the third semiconductor layer and
a diffusion barrier layer that prevents dopant diffusion between the third and fourth semiconductor layer.

US Pat. No. 11,069,695

FLOATING GATE TEST STRUCTURE FOR EMBEDDED MEMORY DEVICE

Taiwan Semiconductor Manu...


1. An integrated circuit (IC) comprising:a memory region and a logic region integrated in a substrate;
a plurality of logic devices disposed in the logic region, wherein a logic device of the plurality of logic devices comprises a logic gate electrode separated from the substrate by a logic gate dielectric;
a plurality of memory cell structures disposed in a memory cell region of the memory region, wherein a memory cell structure of the plurality of memory cell structures comprises a pair of control gates respectively separated from the substrate by a pair of floating gates and a pair of select gate electrodes disposed on opposite sides of the pair of control gates; and
a plurality of memory test structures disposed in a memory test region at a periphery of the memory region surrounding the plurality of memory cell structures, wherein a memory test structure of the plurality of memory test structures comprises a pair of dummy control gates respectively separated from the substrate by a pair of dummy floating gates and a pair of dummy select gate electrodes disposed on opposite sides of the pair of dummy control gates;
wherein the memory test structure further comprises a pair of conductive floating gate test contact vias respectively extending through the pair of dummy control gates and reaching on the dummy floating gates.

US Pat. No. 11,069,694

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Semiconductor Manufacturi...


1. A method for forming a semiconductor structure, comprising:providing a substrate comprising:
a unit memory area, and
a plurality of discrete first gate laminated structures that are formed on the substrate of the unit memory area;
forming a unit dielectric layer on a portion of the substrate exposed from a first gate laminated structure of the plurality of discrete first gate laminated structures, where a portion of a side wall of the first gate laminated structure is exposed from the unit dielectric layer, and the first gate laminated structure and the unit dielectric layer enclose a unit groove;
forming an isolation spacer layer on a side wall of the unit groove, where a bottom of the isolation spacer layer is in contact with the unit dielectric layer, and a top of the isolation spacer layer is lower than a top of the first gate laminated structure;
forming a metal layer conformally covering the isolation spacer layer, the first gate laminated structure, and the unit dielectric layer; and
annealing the metal layer to form a metal silicide layer.

US Pat. No. 11,069,693

METHOD FOR IMPROVING CONTROL GATE UNIFORMITY DURING MANUFACTURE OF PROCESSORS WITH EMBEDDED FLASH MEMORY

Taiwan Semiconductor Manu...


1. A method, comprising:forming a recessed region in a semiconductor substrate;
forming gate materials for a plurality of floating gates and control gates of a memory array in layers over the recessed region;
forming a protective layer over the gate materials in the recessed region;
planarizing the protective layer by:depositing a sacrificial layer over the protective layer;
planarizing the sacrificial layer; and
after planarizing the sacrificial layer, etching the planarized surface of the sacrificial layer at an even rate across the recessed region, to a depth sufficient to leave a planarized surface on the protective layer:,

forming an etch mask layer over the planarized protective layer; and
forming a plurality of gate stacks in the recessed region by etching the gate materials.

US Pat. No. 11,069,692

FINFET SRAM CELLS WITH DIELECTRIC FINS

TAIWAN SEMICONDUCTOR MANU...


1. An integrated circuit (IC), comprising:a first static random access memory (SRAM) cell oriented lengthwise along a first direction and widthwise along a second direction generally perpendicular to the first direction, wherein the first SRAM cell is disposed over a substrate, and wherein the first SRAM cell includes:first, second, third, and fourth dielectric fins disposed in this order along the first direction and oriented lengthwise along the second direction, wherein the first and the fourth dielectric fins define two edges of the first SRAM cell, and wherein bottom portions of the first, second, third, and fourth dielectric fins are disposed in isolation features over the substrate;
a first p-type semiconductor fin disposed between the first and the second dielectric fins;
a second p-type semiconductor fin disposed between the third and the fourth dielectric fins;
a first n-type semiconductor fin and a second n-type semiconductor fin disposed between the second and the third dielectric fins,
wherein the first and the second p-type semiconductor fins and the first and the second n-type semiconductor fins are oriented lengthwise along the second direction, and
wherein the isolation features separate each of the first and the second p-type semiconductor fins and the first and the second n-type semiconductor fins from each of the first, second, third, and fourth dielectric fins; and
gate structures oriented lengthwise along the first direction and spaced from each other along the second direction, wherein the gate structures engage one or more of the first, the second, the third, and the fourth dielectric fin, the first and the second n-type semiconductor fins, and the first and the second p-type semiconductor fins.


US Pat. No. 11,069,691

MEMORY CELL ARRAY WITH LARGE GATE WIDTHS

GLOBALFOUNDRIES U.S. Inc....


1. An integrated circuit with a memory cell array, comprising:a plurality of conductive lines exhibiting a serpentine shape;
a plurality of semiconductor lines extending in a first direction; and
a plurality of transistor devices, wherein gates of said transistor devices are formed in portions of said conductive lines and channels of said transistor devices are formed in said semiconductor lines;
wherein at least one portion of at least one of said conductive lines runs across a first one of said semiconductor lines in a second direction inclined to a direction perpendicular to said first direction at a first inclination angle of more than 5° as measured clockwise from said direction perpendicular to said first direction, and said at least one of said conductive lines run across a second one of said semiconductor lines in a third direction at a second inclination angle of more than 5° as measured counterclockwise from said direction perpendicular to said first direction,
wherein said first inclination angle is between 10° and 40° as measured clockwise from said direction perpendicular to said first direction and said second inclination angle is between 10° and 40° as measured counterclockwise from said direction perpendicular to said first direction, and
wherein a portion of said at least one of said conductive lines that overlaps a third one of said semiconductor lines is perpendicular to said first direction, wherein a width of said first one of said semiconductor lines in said direction perpendicular to said first direction is different from a width of said third one of said semiconductor lines in said direction perpendicular to said first direction.

US Pat. No. 11,069,690

DRAM AND FLASH STRUCTURE AND METHOD OF FABRICATING THE SAME

UNITED MICROELECTRONICS C...


1. A method of fabricating a DRAM and a flash, comprising:providing a substrate comprising a first region and a second region, wherein the first region is for disposing a DRAM, and the second region is for disposing a flash;
forming a plurality of trenches in the first region and the second region to define a first active region in the first region and a second active region in the second region;
forming a silicon oxide/silicon nitride/silicon oxide composite layer filling in the trenches to form a plurality of shallow trench isolations;
forming a first buried gate crossing the first active region and a second buried gate crossing the second active region, wherein the second buried gate only consists of a control gate and a gate dielectric layer, the gate dielectric layer is formed by a single material;
forming a capacitor plug contacting the first active region and disposed at one side of the first buried gate; and
forming a capacitor electrically connecting the capacitor plug.

US Pat. No. 11,069,689

MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

UNITED MICROELECTRONICS C...


1. A manufacturing method of a semiconductor memory device, comprising:providing a semiconductor substrate, wherein a memory cell region and a peripheral region are defined on the semiconductor substrate;
forming a contact hole on the memory cell region, wherein the contact hole exposes a part of the semiconductor substrate;
forming a dielectric layer on the semiconductor substrate;
forming a first trench on the memory cell region, wherein the first trench penetrates the dielectric layer;
forming a second trench on the peripheral region, wherein the second trench penetrates the dielectric layer;
forming a metal conductive layer, wherein the first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench; and
forming a contact structure in the contact hole, wherein the contact structure is located between the bit line metal structure and the semiconductor substrate.

US Pat. No. 11,069,688

VERTICAL TRANSISTOR WITH EDRAM

International Business Ma...


1. A method comprising:providing a substrate with a first doped layer thereon;
forming a trench through the substrate and the first doped layer;
filling the trench with a first polysilicon material;
after filling the trench with the first polysilicon material, i) growing a second polysilicon material over the first polysilicon material and ii) epitaxially growing a second doped layer over the first doped layer, wherein the grown second polysilicon material and the epitaxially grown second doped layer form a basis for a strap merging the second doped layer and the second polysilicon material; and
performing a planarization process on an excess portion of the grown second polysilicon material that grows over the second doped layer.

US Pat. No. 11,069,687

INTEGRATED ASSEMBLIES HAVING SHIELD LINES BETWEEN DIGIT LINES, AND METHODS OF FORMING INTEGRATED ASSEMBLIES

Micron Technology, Inc., ...


1. An integrated assembly, comprising:digit lines extending along a first direction; the digit lines being spaced from one another by intervening regions; each of the digit lines having a first width along a cross-section orthogonal to the first direction; each of the intervening regions also having the first width along the cross-section; each of the digit lines having a top surface at a first height;
vertically-extending pillars over the digit lines; each of the vertically-extending pillars comprising a transistor channel region and an upper source/drain region; lower source/drain regions being under the channel regions and being coupled with the digit lines; the transistor channel regions extending vertically between the lower source/drain regions and the upper source/drain regions; each of the vertically-extending pillars having the first width along the cross-section; the intervening regions extending upwardly to between the vertically-extending pillars and comprising the first width from top surfaces of the upper source/drain regions to bottom surfaces of the digit lines;
storage elements coupled with the upper source/drain regions;
wordlines extending along a second direction which crosses the first direction; the wordlines including gate regions adjacent the channel regions; and
shield lines within the intervening regions and extending along the first direction; each of the shield lines having a top surface at a second height which is greater than or equal to the first height.

US Pat. No. 11,069,686

TECHNIQUES FOR ENHANCING VERTICAL GATE-ALL-AROUND FET PERFORMANCE

International Business Ma...


1. A vertical field effect transistor (VFET) device, comprising:at least one fin patterned in a substrate;
bottom source and drains at a base of the at least one fin;
bottom spacers on the bottom source and drains;
a gate along sidewalls of the at least one fin;
an oxide layer formed along the sidewalls of a top portion of the at least one fin;
a charged layer disposed over the at least one fin in direct contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the at least one fin forming a dipole;
top spacers above the gate; and
top source and drains above the top spacers.

US Pat. No. 11,069,685

SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...


1. A semiconductor device comprising:a substrate including a first region and a second region, and having a silicon-on-insulator (SOI) structure;
a first gate on the first region of the substrate;
a second gate on the second region of the substrate;
a first source/drain on the first region of the substrate;
a second source/drain on the second region of the substrate;
a plurality of first insulating spacers on sidewalls of the first gate;
a plurality of second insulating spacers on sidewalls of the second gate; and
a plurality of air spacers between the plurality of first insulating spacers and the first source/drain,
wherein no air spacer is between the plurality of second insulating spacers and the second source/drain.

US Pat. No. 11,069,684

STACKED FIELD EFFECT TRANSISTORS WITH REDUCED COUPLING EFFECT

International Business Ma...


1. A method for forming a semiconductor structure, comprising:forming a first set of nanosheet layers and a second set of nanosheet layers on a substrate, wherein each of the first set of nanosheet layers and the second set of nanosheet layers comprises alternating silicon layers and silicon-germanium layers, and wherein the first set of nanosheet layers and the second set of nanosheet layers are separated by a first sacrificial isolation layer;
forming a bottom source/drain region on the substrate and in contact with the first set of nanosheet layers;
forming a second sacrificial isolation layer on at least the bottom source/drain region;
forming a top source/drain region on at least a portion of the second sacrificial isolation layer;
depositing an interlevel dielectric layer on the top source/drain region and the second sacrificial isolation layer;
forming one or more trenches in the interlevel dielectric layer and exposing a top surface of the second sacrificial isolation layer; and
removing the second sacrificial isolation layer to form an air gap positioned between the bottom source/drain region and the top source/drain region.

US Pat. No. 11,069,683

SELF RESTORING LOGIC STRUCTURES

ICs LLC, McCall, ID (US)...


1. A Self Restoring Logic (SRL) latch formed of three NMOS and PMOS structures having a first latch with a first NMOS structure adjacent a first PMOS structure to form a first logic section, a second latch with a second NMOS structure adjacent a second PMOS structure to form a second logic section wherein the first and second NMOS structures are adjacent one another, and a third latch with a third NMOS structure adjacent a third PMOS structure to form a third logic section wherein the second and third PMOS structures are adjacent one another, wherein the latch is adapted to have alternating logic with a state assignment of 010 and 101, further wherein outputs of the first and third logic sections are the same and an output of the second logic section is the logical complement of the outputs of the first and third logic sections.

US Pat. No. 11,069,682

MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS

STMICROELECTRONICS, INC.,...


1. A device, comprising:a substrate;
a plurality of fins over the substrate, the plurality of fins including a first fin and a second fin, the first fin including a first sidewall surface and a second sidewall surface opposite to the first sidewall surface, the second fin including a third sidewall surface and a fourth sidewall surface opposite to the third sidewall surface, the second sidewall surface of the first fin facing the third sidewall surface of the second fin;
a gate over the plurality of fins;
a plurality of epitaxial source and drain structures positioned between the plurality of fins, ones of the plurality of epitaxy source and drain structures contacting the third sidewall surface and the second sidewall surface; and
an epitaxial growth barrier layer over the first sidewall surface of the first fin and on an upper portion only of the second sidewall of the first fin.

US Pat. No. 11,069,681

INTEGRATED CIRCUIT DEVICE

Samsung Electronics Co., ...


1. An integrated circuit device comprising:a fin-type active region extending lengthwise in a first direction;
a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region; and
a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction,
wherein the plurality of nanosheets comprises a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets, and
wherein the source/drain region comprises a source/drain main region and a first source/drain protruding region protruding from the source/drain main region, wherein the first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet to overlap portions of the plurality of nanosheets in the second direction,
wherein the source/drain region comprises a first semiconductor layer doped with a first dopant of a first conductivity type,
wherein the first nanosheet comprises a second semiconductor layer doped with a second dopant of the first conductivity type, and
wherein nanosheets other than the first nanosheet, from among the plurality of nanosheets, comprise an undoped third semiconductor layer.

US Pat. No. 11,069,680

FINFET-BASED INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE

International Business Ma...


1. An integrated circuit comprising:a first set of fins protruding upward from a substrate;
a second set of fins protruding upward from the substrate, discrete from the first set of fins;
a gate passing above the first set of fins and the second set of fins; and
a dielectric plug surrounded by the gate on two sides where the gate passes between the first set of fins and the second set of fins,
wherein the gate protrudes in a first portion and a second portion on opposite sides of the dielectric plug, and the first portion is closer to the substrate than is the second portion.

US Pat. No. 11,069,679

REDUCING GATE RESISTANCE IN STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

International Business Ma...


1. A method for forming a stacked semiconductor device structure, the method comprising at least:forming, on a substrate, a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length;
forming an insulating layer on the first VTFET; and
forming a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length,
wherein the insulating layer insulates a first semiconductor fin of the first VTFET from a second semiconductor fin of the second VTFET.

US Pat. No. 11,069,678

LOGIC GATE CELL STRUCTURE

Qorvo US, Inc., Greensbo...


1. A logic gate cell structure comprising:a substrate;
a channel layer disposed over the substrate;
a field-effect transistor (FET) contact layer disposed over the channel layer and divided by an isolation region into a first portion within a single contact region and a second portion within a combined contact region, wherein a gate contact is disposed within the isolation region over the channel layer, and the channel layer and the FET contact layer form part of a FET device;
a first etch stop layer disposed over the second portion of the FET contact layer within the combined contact region, wherein the first etch stop layer has a dopant atom concentration that is in the range from 4×1018 cm?3 to 5×1018 cm?3;
a sub-collector layer disposed within the combined contact region and directly onto the first etch stop layer to provide a shorted current path between the gate contact and a combined collector/source contact disposed over the sub-collector layer;
a collector layer disposed over the sub-collector layer, wherein the collector layer has the same type of doping as the first etch stop layer;
a base layer disposed over the collector layer; and
an emitter layer disposed over the base layer, wherein the sub-collector, the collector layer, the base layer, and the emitter layer form part of a bipolar junction transistor.

US Pat. No. 11,069,676

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

NANYA TECHNOLOGY CORPORAT...


1. A semiconductor device, comprising:a first gate structure comprising a first gate bottom insulating layer inwardly positioned, a first gate top insulating layer positioned on the first gate bottom insulating layer, a first gate top conductive layer positioned on the first gate top insulating layer, and a first gate filler layer positioned on the first gate top conductive layer; and
a capacitor structure comprising a capacitor bottom insulating layer inwardly positioned, a capacitor bottom conductive layer positioned on the capacitor bottom insulating layer, a capacitor top insulating layer positioned on the capacitor bottom conductive layer, a capacitor top conductive layer positioned on the capacitor top insulating layer, and a capacitor filler layer positioned on the capacitor top conductive layer;
wherein the first gate bottom insulating layer is formed of a same material as the capacitor bottom insulating layer.

US Pat. No. 11,069,675

ESD PROTECTION DEVICE WITH BIDIRECTIONAL DIODE STRING-TRIGGERING SCR STRUCTURE

JIANGNAN UNIVERSITY, Wux...


1. An ESD protection device for bidirectional diode string triggering SCR structure, comprising:a diode string formed by a well splitting technique,
a bidirectional SCR structure; and
a metal wire,
wherein the bidirectional SCR structure and the diode string comprise a P substrate, a deep N well, a first P well, a first N well, a second P well, a second N well, a first P+ implantation region, a first N+ implantation region, a second P+ implantation region, a second N+ implantation region, a third P+ implantation region, a third N+ implantation region, a fourth P+ implantation region and a fourth N+ implantation region, wherein the deep N well is arranged on the P substrate, and the first P well, the first N well, the second P well and the second N well are successively arranged from left to right on a surface region of the deep N well; the left edge of the first P well is connected with the left edge of the deep N well; the right side of the first P well is connected with the left side of the first N well; the right side of the first N well is connected with the left side of the second P well; the right edge of the second P well is connected with the left side of the second N well; the right edge of the second N well is connected with the right edge of the deep N well; the first P+ implantation region and the first N+ implantation region are successively arranged from left to right on the surface region of the first P well; the second P+ implantation region and the second N+ implantation region are successively arranged from left to right on the surface region of the first N well; the third P+ implantation region and the third N+ implantation region are successively arranged from left to right on the surface region of the second P well; the fourth P+ implantation region and the fourth N+ implantation region are successively arranged from left to right on the surface region of the second N well,
wherein, in the second N well region, a mask preparing plate is used to insert a plurality of P wells at intervals; the circumference of each P well is isolated by the N well; different quantities of diodes are prepared to form a diode string which assists a departure path to effectively suppress the Darlington effect; the surface region of each P well is respectively provided with a pair of P+ implantation region and N+ implantation region; trigger voltage is controlled by increasing or decreasing the number of diodes formed by well splitting,
wherein the metal wire is used to connect the implantation region, and lead out two electrodes from the metal wire respectively as the forward conduction and reverse conduction of the ESD protection device, to ensure that a diode formed by well splitting assists a trigger path in conducting, thereby reducing the trigger voltage and turn-on time of the ESD protection device,
wherein when the ESD protection device is a bidirectional three-diode triggering SCR structure, in the second N well region, along the Z-axis direction of the ESD protection device, the third P well, the third N well, the fourth P well, the fourth N well, the fifth P well, the fifth N well and the sixth N well are successively inserted on the right side; the fifth P+ implantation region, the fifth N+ implantation region, the sixth P+ implantation region, the sixth N+ implantation region, the seventh P+ implantation region and the seventh N+ implantation region are respectively inserted into the P well,
wherein the lower side of the second N well is connected with the lower side of the deep N well; the upper side of the second N well is connected with the lower side of the third P well; the upper side of the third P well is connected with the lower side of the third N well; the upper side of the third N well is connected with the lower side of the fourth P well; the upper side of the fourth P well is connected with the lower side of the fourth N well; the upper side of the fourth N well is connected with the lower side of the fifth P well; the upper side of the fifth P well is connected with the lower side of the fifth N well; the upper side of the fifth N well is connected with the upper side of the deep N well; the fifth P+ implantation region and the fifth N+ implantation region are successively arranged from bottom to top on the surface region of the third P well; the sixth P+ implantation region and the sixth N+ implantation region are successively arranged from bottom to top on the surface region of the fourth P well; the seventh P+ implantation region and the seventh N+ implantation region are successively arranged from bottom to top on the surface region of the fifth P well,
wherein the first N+ implantation region is connected with first metal; the second P+ implantation region is connected with second metal; the second N+ implantation region is connected with third metal; the third N+ implantation region is connected with fourth metal; the fourth P+ implantation region is connected with fifth metal; the fourth N+ implantation region is connected with sixth metal; the first P+ implantation region is connected with seventh metal; the third P+ implantation region is connected with eighth metal; the fifth P+ implantation region is connected with ninth metal; the fifth N+ implantation region is connected with tenth metal; the sixth P+ implantation region is connected with eleventh metal; the sixth N+ implantation region is connected with twelfth metal; the seventh P+ implantation region is connected with thirteenth metal; the seventh N+ implantation region is connected with fourteenth metal,
wherein the third metal, the sixth metal and the ninth metal are connected with the seventeenth metal; the seventh metal, the eighth metal and the fourteenth metal are connected with the twentieth metal; the tenth metal and the eleventh metal are connected with the eighteenth metal; the twelfth metal and the thirteenth metal are connected with the nineteenth metal,
wherein the first metal and the second metal are connected with the fifteenth metal, and a first electrode is led out from the fifteenth metal, and used as a metal anode of the ESD protection device—conducted forward or a metal cathode—conducted reversely,
wherein the fourth metal and the fifth metal are connected with the sixteenth metal; a second electrode is led out from the sixteenth metal, and used as a metal cathode of the ESD protection device—conducted forward or a metal anode—conducted reversely,
wherein when the first electrode is used as the metal anode of the ESD protection device and the second electrode is used as the metal cathode of the ESD protection device, the first N+ implantation region and the first P well, the first N well and the second P well, the second N well and the fourth P+ implantation region respectively form reverse bias PN junctions,
wherein the reverse bias PN junction formed by the first N well and the second P well is an avalanche breakdown junction of the SCR, and the diode formed by the well splitting assists the trigger path in conducting, thereby reducing the trigger voltage and turn-on time of the ESD protection device,
wherein when the first electrode is used as the metal cathode of the ESD protection device and the second electrode is used as the metal anode of the ESD protection device, the third N+ implantation region and the second P well, the first N well and the second P+ implantation region, the first N well and the first P+ well respectively form reverse bias PN junctions, and
wherein the reverse bias PN junction formed by the first N well and the first P well is an avalanche breakdown junction of the SCR, and the diode formed by the well splitting assists the trigger path in conducting, thereby reducing the trigger voltage and turn-on time of the ESD protection device.

US Pat. No. 11,069,674

SEMICONDUCTOR DEVICE

INFINEON TECHNOLOGIES AG,...


1. A semiconductor device comprising:“n” pairs of pn-junction structures, with n is an integer?2, wherein the i-th pair, with i?{1, . . . , n}, comprises two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected,
wherein the pn-junction structure of the i-th type comprises an i-th junction grading coefficient mi,
wherein at least a first pair of the n pairs of pn-junction structures comprises a first junction grading coefficient with m1?0.48 and a second pair of the n pairs of pn-junction structures comprises a second junction grading coefficient m2?0.52, and
wherein the junction grading coefficients m1, m2 of the first and second pair of the n pairs of pn-junction structures result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.

US Pat. No. 11,069,673

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...


1. A package comprising:at least one semiconductor die encapsulated by a molding compound;
a redistribution layer, disposed on the molding compound and over a front-side of the at least one semiconductor die and electrically connected with the at least one semiconductor die; and
a backside film, disposed on the molding compound and over a backside of the at least one semiconductor die, wherein the backside film that is located on the at least one semiconductor die includes trenches, and bottoms of the trenches are free of a conductor.

US Pat. No. 11,069,672

LAMINATED ELEMENT MANUFACTURING METHOD

HAMAMATSU PHOTONICS K.K.,...


1. A laminated element manufacturing method comprising:a first forming step of preparing a first wafer as a semiconductor wafer including a semiconductor substrate having a front surface and a back surface, and a circuit layer including a plurality of functional elements two-dimensionally arranged along the front surface, and forming a first gettering region for each of the functional elements by irradiating the semiconductor substrate of the first wafer with a laser light so as to correspond to each of the functional elements;
a first grinding step of grinding the semiconductor substrate of the first wafer and removing a portion of the first gettering region, after the first forming step;
a bonding step of preparing a second wafer as the semiconductor wafer and bonding the circuit layer of the second wafer to the semiconductor substrate of the first wafer such that each of the functional elements of the first wafer correspond to each of the functional elements of the second wafer, after the first grinding step;
a second forming step of forming a second gettering region for each of the functional elements by irradiating the semiconductor substrate of the second wafer with a laser light so as to correspond to each of the functional elements, after the bonding step; and
a second grinding step of grinding the semiconductor substrate of the second wafer and removing a portion of the second gettering region, after the second forming step.

US Pat. No. 11,069,671

SEMICONDUCTOR PACKAGE AND METHOD

Taiwan Semiconductor Manu...


1. A method comprising:aligning a first package component with a second package component, the first package component having a first region and a second region, the first region comprising a first conductive connector, the second region comprising a second conductive connector;
performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region, wherein performing the first laser shot comprises:directing a laser beam at the first portion of the top surface of the first package component until the first conductive connector reflows; and
after the first conductive connector reflows, turning off the laser beam until the first conductive connector solidifies; and

after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.

US Pat. No. 11,069,670

CAMERA ASSEMBLY AND PACKAGING METHOD THEREOF, LENS MODULE, AND ELECTRONIC DEVICE

Ningbo Semiconductor Inte...


1. A method for packaging a camera assembly, comprising:providing a photosensitive chip;
mounting an optical filter on the photosensitive chip;
temporarily bonding the photosensitive chip and functional components on a carrier substrate, wherein the photosensitive chip has soldering pads facing away from the carrier substrate and the functional components have soldering pads facing toward the carrier substrate;
forming an encapsulation layer covering the carrier substrate, the photosensitive chip, and the functional components, and exposing the optical filter;
after the encapsulation layer is formed, removing the carrier substrate; and
after the carrier substrate is removed, forming a redistribution layer structure on a side of the encapsulation layer facing away from the optical filter to electrically connect the soldering pads of the photosensitive chip with the soldering pads of the functional components,
wherein after bonding the photosensitive chip and the functional components on the carrier substrate, forming a stress buffering layer on sidewall of the optical filter between the sidewall of the optical filter and the soldering pads of the photosensitive chip, wherein:
the stress buffering layer is formed on the sidewall of the optical filter before the optical filter is mounted on the photosensitive chip; or
the stress buffering layer is formed on the sidewall of the optical filter after the photosensitive chip is temporarily bonded on the carrier substrate and before the encapsulation layer is formed.

US Pat. No. 11,069,669

MICRO LED DISPLAY PANEL AND METHOD FOR MAKING SAME

HON HAI PRECISION INDUSTR...


1. A micro LED display panel, comprising:a blue LED layer, the blue LED layer comprising a plurality of blue micro LEDs spaced apart from each other, each of the plurality of blue micro LEDs defining a blue sub-pixel;
a green LED layer, the green LED layer comprising a plurality of green micro LEDs spaced apart from each other, each of the plurality of green micro LEDs defining a green sub-pixel; and
a red LED layer, the red LED layer comprising a plurality of red micro LEDs spaced apart from each other, each of the plurality of red micro LEDs defining a red sub-pixel;
wherein the blue LED layer, the green LED layer, and the red LED layer are stacked one by one along a depth direction of the micro LED display panel; and
each of the plurality of blue micro LEDs, each of the plurality of green micro LEDs, and each of the plurality of red micro LEDs are staggered from each other;
wherein the blue LED layer comprises a first transparent conductive layer, a first light emitting layer, and a first electrode layer stacked one by one along the depth direction; the first light emitting layer is provided between the first transparent conductive layer and the first electrode layer; the first light emitting layer comprises an N-type doped inorganic light emitting layer, an active layer, and a P-type doped inorganic light emitting layer stacked one by one along the depth direction; the active layer is provided between the P-type doped inorganic light emitting layer and the N-type doped inorganic light emitting layer; the N-type doped inorganic light emitting layer comprises a plurality of N-type doped units spaced apart from each other; the first electrode layer comprises a plurality of electrodes spaced apart from each other; each of the plurality of N-type doped units is coupled to the first transparent conductive layer; the P-type doped inorganic light emitting layer is coupled to each of the plurality of electrodes; a projection of each of the plurality of N-type doped units on the first electrode layer overlaps with one of the plurality of electrodes; a portion of the blue LED layer corresponding to one of the plurality of N-type doped units defines one blue sub-pixel.

US Pat. No. 11,069,668

ELECTRONIC DEVICE FOR REDUCING A BORDER EDGE OF THE NON-DISPLAY AREAS

INNOLUX CORPORATION, Mia...


1. An electronic device, comprising:a display area;
a non-display area adjacent to the display area;
a plurality of first signal lines, and each of the plurality of first signal lines comprising:
a first section extending in a first direction; and
a second section extending in a second direction different from the first direction; wherein from a top view of the electronic device, the second section crosses the first section;
a plurality of second signal lines extending in the second direction and sequentially arranged in the first direction;
wherein the plurality of first signal lines are scan lines and the plurality of second signal lines are data lines, or the plurality of first signal lines are data lines and the plurality of second signal lines are scan lines; and
wherein each of the second sections of the plurality of first signal lines is disposed between any two of the plurality of second signal lines, and all of the second sections of the plurality of first signal lines are disposed between part of the plurality of second signal lines.

US Pat. No. 11,069,667

WAFER LEVEL PROXIMITY SENSOR

STMICROELECTRONICS PTE LT...


16. A wafer level proximity micro-sensor module, comprising:a back-grinded silicon substrate having a first surface opposite a second surface;
a light sensor at the first surface of the back-grinded silicon substrate, the light sensor including a surface substantially co-planar with the first surface of the back-grinded silicon substrate;
a first contact pad at the first surface of the silicon substrate;
a light emitter coupled to the first contact pad;
a cap coupled to the first surface of the silicon substrate, the cap including a third surface opposite to the first surface of the silicon substrate, a first opening aligned with the light emitter and a second opening aligned with the light sensor, the first opening having a width proximate the light emitter that is greater than a width of the light emitter; and
a first transparent portion fills the first opening and covers the light emitter, a second transparent portion fills the second opening and covers the light sensor, the first transparent portion has a fourth surface, the second transparent portion has a fifth surface, and the fourth surface and the fifth surface are substantially flush with the third surface of cap, the first transparent portion is in direct physical contact with a surface of the first contact pad, and the second transparent portion is in direct physical contact with the light sensor;
wherein the back-grinded substrate and the cap are singulated to yield the wafer level proximity micro-sensor module, and a thickness of the wafer level proximity micro-sensor module extends between the second surface of the back-grinded silicon substrate and the third surface of the cap, the thickness is in the range of 0.4 and 0.6 millimeters.

US Pat. No. 11,069,666

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...


1. A semiconductor package, comprising:a frame having a through-hole;
a first semiconductor chip disposed in the through-hole of the frame, and having an active surface on which a connection pad is disposed, an inactive surface opposing the active surface, and a side surface connecting the active and inactive surfaces;
a first encapsulant covering at least a portion of each of the inactive surface and the side surface of the first semiconductor chip;
a connection structure having a first surface having disposed thereon the active surface of the first semiconductor chip and a first surface of the frame, and including an insulating layer, a redistribution layer disposed on the insulating layer, and at least one via extending from the redistribution layer through the insulating layer to directly contact and electrically connect to the connection pad of the first semiconductor chip;
a first passive component disposed on a second surface of the connection structure opposing the first surface of the connection structure, the first passive component being electrically connected to the redistribution layer;
a second passive component disposed on the first surface of the connection structure and electrically connected to the redistribution layer; and
a plurality of metal pads protruding from a second surface of the frame opposing the first surface of the frame, each metal pad having a respective electrical connection metal thereon,
wherein the connection structure has a first thickness, measured between the first and second surfaces thereof, in a first region having the first semiconductor chip thereon, and a second thickness, measured between the first and second surfaces thereof, different from the first thickness, in a second region having the second passive component thereon, the second passive component including at least one of a Multilayer Ceramic Capacitor (MLCC), a capacitor, an inductor, or a bead,
wherein the frame has an additional through-hole spaced apart from the through-hole in which the first semiconductor chip is disposed,
the second passive component is disposed in the additional through-hole of the frame, the second passive component having a thickness smaller than a thickness of the first semiconductor chip, and
the connection structure has the first thickness throughout a region facing the through-hole of the frame, and has the second thickness higher than the first thickness throughout a region facing the additional through-hole of the frame.

US Pat. No. 11,069,664

MICRO-LED MODULE AND METHOD FOR FABRICATING THE SAME

LUMENS CO., LTD., Yongin...


1. A micro-LED module comprising:a micro-LED comprising:a plurality of LED cells arrayed in a matrix, each of the plurality of LED cells comprising an n-type semiconductor layer, an active layer, and a p-type semiconductor layer;
a plurality of p-type electrode pads on the p-type semiconductor layers of the plurality of LED cells; and
an n-type electrode pad formed in an exposed area of the n-type semiconductor layer, the exposed area being formed along a peripheral edge of the micro-LED;

an active matrix substrate comprising:a plurality of individual electrode pads corresponding to the plurality of p-type electrode pads of the micro-LED;
a common electrode pad corresponding to the n-type electrode pad of the micro-LED;
a plurality of first pillars corresponding to the plurality of individual electrode pads; and
a second pillar corresponding to the common electrode pad;

a plurality of first solder bonding portions bonding each of the plurality of first pillars of the active matrix substrate to the corresponding p-type electrode pad of the micro-LED; and
a second solder bonding portion bonding the second pillar of the active matrix substrate to the n-type electrode pad of the micro-LED,
wherein a maximum cross-sectional diameter of each of the plurality of first solder bonding portions is larger than a diameter of the corresponding first pillar, and a minimum cross-sectional diameter of each of the plurality of first solder bonding portions is larger than 80% and smaller than 100% of the diameter of the corresponding first pillar.

US Pat. No. 11,069,663

METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT, AND OPTOELECTRONIC SEMICONDUCTOR COMPONENT

OSRAM OLED GmbH, Regensb...


1. A method of producing an optoelectronic semiconductor component comprising:A) providing at least three source substrates, wherein each of the source substrates is equipped with a specific type of radiation-emitting semiconductor chips,
B) providing a target substrate having a mounting plane configured to mount the semiconductor chips thereto,
C) forming platforms on the target substrate, and
D) transferring at least some of the semiconductor chips with a wafer-to-wafer process from the source substrates onto the target substrate so that the semiconductor chips transferred to the target substrate maintain their relative position with respect to one another, within the types of semiconductor chips, wherein
on the target substrate the semiconductor chips of each type of semiconductor chips have a specific height above the mounting plane due to the platforms so that the semiconductor chips of different types of semiconductor chips have different heights,
only after the transfer of the semiconductor chips of a first to a penultimate type of semiconductor chips and before the semiconductor chips of the respective next type of semiconductor chips are transferred, one of each type of platform is produced, and
at least the semiconductor chips of one of the types of semiconductor chips are detached from the respective source substrate by a laser lift-off method so that a laser radiation is irradiated through the associated source substrate.

US Pat. No. 11,069,662

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...


1. A semiconductor package, comprising:a first chip package, comprising:a plurality of first semiconductor dies, electrically connected to each other; and
a first insulating encapsulant, encapsulating the plurality of first semiconductor dies;

a second semiconductor die and a third semiconductor die, electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die;
a second insulating encapsulant, encapsulating the second semiconductor die and the third semiconductor die; and
through vias, penetrating the second insulating encapsulant and arranged aside of the second semiconductor die and the third semiconductor die, wherein the through vias are overlapped with the second semiconductor die and the third semiconductor die along a direction perpendicular to a stacking direction of the first chip package and the second semiconductor die.