US Pat. No. 11,031,562

METAL COMPLEXES

Merck Patent GmbH, Darms...

1. A monometallic compound comprising a hexadentate tripodal ligand wherein three bidentate sub-ligands which are optionally the same or different coordinate to a metal and the three bidentate sub-ligands are joined to one another via a bridge of formula (1):
wherein
the dotted bonds denote the bonds of the bridge of formula (1) to the three bidentate sub-ligands;
X1 is, identically or differently in each instance, CR or N;
X2 is, identically or differently in each instance, —CR??CR?—, —CR??N—, —C(?O)—O—, —C(?O)—NR?—, —C(?O)—S—, —C(?S)—O—, —C(?S)—NR?— or —C(?S)—S—;
X3 is, identically or differently in each instance, X2 or a —CR?CR— group;
R and R?
is, identically or differently in each instance, H, D, F, Cl, Br, I, N(R1)2, CN, NO2, OR1, SR1, COOH, C(?O)N(R1)2, Si(R1)3, B(OR1)2, C(?O)R1, P(?O)(R1)2, S(?O)R1, S(?O)2R1, OSO2R1, a straight-chain alkyl group having 1 to 20 carbon atoms or an alkenyl or alkynyl group having 2 to 20 carbon atoms or a branched or cyclic alkyl group having 3 to 20 carbon atoms, wherein the alkyl, alkenyl, and alkynyl groups in each instance are optionally substituted by one or more radicals R1, and wherein one or more nonadjacent CH2 groups are optionally replaced by R1C?CR1, C?C, Si(R1)2, C?O, NR1, O, S, or CONR1, an aromatic or heteroaromatic ring system having 5 to 40 aromatic ring atoms and in each instance is optionally substituted by one or more radicals R1; and wherein, when X2 is —CR??CR?—, two radicals R? together optionally define an aliphatic or heteroaliphatic ring system; and wherein, X3 is —CR?CR—, two radicals R together optionally define an aliphatic, heteroaliphatic, aromatic, or heteroaromatic ring system;
R? is, identically or differently in each instance, H, D, a straight-chain alkyl group having 1 to 20 carbon atoms or a branched or cyclic alkyl group having 3 to 20 carbon atoms, wherein the alkyl group in each instance is optionally substituted by one or more radicals R1 and wherein one or more nonadjacent CH2 groups are optionally replaced by Si(R1)2, or an aromatic or heteroaromatic ring system having 5 to 40 aromatic ring atoms and in each instance is optionally substituted by one or more radicals R1;
R1 is, identically or differently in each instance, H, D, F, Cl, Br, I, N(R2)2, CN, NO2, OR2, SR2, Si(R2)3, B(OR2)2, C(?O)R2, P(?O)(R2)2, S(?O)R2, S(?O)2R2, OSO2R2, a straight-chain alkyl group having 1 to 20 carbon atoms or an alkenyl or alkynyl group having 2 to 20 carbon atoms or a branched or cyclic alkyl group having 3 to 20 carbon atoms, wherein the alkyl, alkenyl, and alkynyl groups in each instance are optionally substituted by one or more radicals R2, wherein one or more nonadjacent CH2 groups are optionally replaced by R2C?CR2, C?C, Si(R2)2, C?O, NR2, O, S, or CONR2, an aromatic or heteroaromatic ring system having 5 to 40 aromatic ring atoms and in each instance is optionally substituted by one or more radicals R2; and wherein two or more radicals R1 together optionally define an aliphatic, heteroaliphatic, aromatic or heteroaromatic ring system;
R2 is, identically or differently in each instance, H, D, F, or an aliphatic, aromatic, and/or heteroaromatic organic radical having 1 to 20 carbon atoms, wherein one or more hydrogen atoms are optionally replaced by F; and
wherein the three bidentate ligands, in addition to the bridge of formula (1), are also optionally ring-closed by a further bridge so as to form a cryptate,
wherein the metal is Ir(III) and two of the bidentate sub-ligands each coordinate to the iridium via one carbon atom and one nitrogen atom or via two carbon atoms and the third bidentate sub-ligand coordinates to the iridium via one carbon atom and one nitrogen atom or via two carbon atoms or via two nitrogen atoms or via one nitrogen atom and one oxygen atom or via two oxygen atoms.

US Pat. No. 11,031,561

ORGANIC ELECTRON TRANSPORT MATERIAL AND ORGANIC ELECTROLUMINESCENT ELEMENT USING SAME

Dyden Corporation, Fukuo...

1. An organic electron transport material, which includes a compound represented by the following Formula (1):
where, in Formula (1),
R1 represents an atomic group which has either or both of one or more aryl groups and one or more heteroaryl groups,
R1 includes, when R1 does not have a heteroaryl group, interatomic bonds comprising carbon-carbon bonds that constitute two or less benzene rings, the interatomic bonds being obtained by tracing in Formula (1) from one P to another P such that interatomic bonds between the one P and the other P is shortest,
R1 includes, when R1 has a heteroaryl group, interatomic bonds comprising bonds that constitute a six-ring heterocycle, the interatomic bonds being obtained by tracing in Formula (1) from one P to another P such that interatomic bonds between the one P and the other P is shortest,
R2 to R17 each independently represent an atom or an atomic group selected from the group consisting of a hydrogen atom, a halogen atom, a cyano group, a C1-C12 linear or branched alkyl group, a linear or branched fluoroalkyl group, an aryl group, a substituted aryl group, a heteroaryl group, and a substituted heteroaryl group:
where, in Formula (1),
X represents an atom or an atomic group represented by any one of the following Formulae (2) to (7):

where, in Formula (2),
R21 and R22 each independently represent an atom or an atomic group selected from the group consisting of a hydrogen atom, a C1-C12 linear or branched alkyl group, a linear or branched fluoroalkyl group, an aryl group, a substituted aryl group, a heteroaryl group, and a substituted heteroaryl group,
where, in Formula (3),
R31 represents an atom or an atomic group selected from the group consisting of a hydrogen atom, a C1-C12 linear or branched alkyl group, a linear or branched fluoroalkyl group, an aryl group, a substituted aryl group, a heteroaryl group, and a substituted heteroaryl group.

US Pat. No. 11,031,560

COMPOUND AND ORGANIC ELECTRONIC ELEMENT COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A compound represented by the following Chemical Formula 1, 2, or 3:
wherein, in Chemical Formula 1, 2, or 3,
one or two of R1 to R8 is -(L)m-(Ar)n, and the rest are hydrogen,
L is a direct bond or a phenylene group,
m is an integer of 1 to 3,
when m is an integer of 2 or greater, a plurality of Ls are the same as or different from each other,
Ar is a phenyl group substituted with at least one selected from the group consisting of a C1 to C20 alkyl group and a C6 to C20 aryl group; a substituted or unsubstituted multicyclic aryl group selected from naphthalene or fluorene; a substituted or unsubstituted heterocyclic group selected from carbazole, triazine, pyrimidine, pyridine, dibenzofuran, dibenzothiophene, benzimidazole, benzothiazole, or benzoxazole; a substituted or unsubstituted aryl amine group; or a substituted or unsubstituted phosphoryl group,
n is 1 or 2, and when n is 2, a plurality of Ars are the same as or different from each other,
R9 and R10 are hydrogen,
R11 and R12 are the same as or different from each other, and each independently hydrogen; deuterium; a halogen group; a nitro group; a cyano group; an ester group; a carbonyl group; a substituted or unsubstituted alkyl group; a substituted or unsubstituted cycloalkyl group; a substituted or unsubstituted alkoxy group; a substituted or unsubstituted alkenyl group; a substituted or unsubstituted aryl group; or a substituted or unsubstituted heterocyclic group, and
p and q are each an integer of 0 to 4.

US Pat. No. 11,031,559

PHENOXASILINE BASED COMPOUNDS FOR ELECTRONIC APPLICATION

UDC Ireland Limited, Dub...

1. A compound of the formula (I)
in which
R1, R2, R3, R4, R5, R6 and R7
are each independently hydrogen, C1-C20-alkyl, C3-C20-cycloalkyl, heterocycloalkyl having 3 to 20 ring atoms, C6-C30-aryl, heteroaryl having 5 to 30 ring atoms or a substituent with donor or acceptor action selected from the group consisting of C1-C20-alkoxy, C6-C30-aryloxy, C1-C20-alkylthio, C6-C30-arylthio, SiR10R11R12, halogen radicals, halogenated C1-C20-alkyl radicals, carbonyl (—CO(R10)), carbonylthio (—C?O(SR10)), carbonyloxy (—C?O(OR10)), oxycarbonyl (—OC?O(R10)), thiocarbonyl (—SC?O(R10)), amino (—NR10R11), OH, pseudohalogen radicals, amido (—C?O(NR10R11)), —NR10C?O(R11), phosphonate (—P(O) (OR10)2), phosphate (—OP(O)(OR10)2), phosphine (—PR10R11), phosphine oxide (—P(O)R102), sulfate (—OS(O)2OR10), sulfoxide (—S(O)R10), sulfonate (—S(O)2OR10), sulfonyl (—S(O)2R10), sulfonamide (—S(O)2NR10R11), NO2, boronic esters (—OB(OR10)2), imino (—C?NR10), borane radicals, stannane radicals, hydrazine radicals, hydrazone radicals, oxime radicals, nitroso groups, diazo groups, vinyl groups, sulfoximines, alanes, germanes, boroxines and borazines;
or two adjacent R1, R2, R3, R4, R5, R6 or R7 radicals, in each case together with the carbon atoms to which they are bonded, form a ring having a total of 3 to 12 atoms, where the ring is saturated or mono- or polyunsaturated and, as well as carbon atoms, has or does not have one or more heteroatoms selected from N, O and P, where the ring is unsubstituted or mono- or polysubstituted and/or is fused to further 3- to 12-membered rings;
R8 and R9
are each independently C1-C20-alkyl, C3-C20-cycloalkyl, heterocycloalkyl having 3 to 20 ring atoms, C6-C30-aryl or heteroaryl having 5 to 30 ring atoms;
R10, R11, R12
are each independently C1-C20-alkyl, C3-C20-cycloalkyl, heterocycloalkyl having 3 to 20 ring atoms, C6-C30-aryl, heteroaryl having 5 to 30 ring atoms, —O—Si(C1-C20-alkyl)3, —O—Si(C6-C30-aryl)3, C1-C20-alkoxy or C6-C30-aryloxy;
or two adjacent R10 and R11, R10 and R12 or R11 and R12 radicals, together with the atom to which they are bonded, form a ring having a total of 3 to 12 atoms, where the ring is saturated or mono- or polyunsaturated and, as well as the atom to which the R10, R11 or R12 radicals are bonded, have exclusively carbon atoms or one or more further heteroatoms selected from N, O and P, where the ring is unsubstituted or mono- or polysubstituted and/or is fused to further 3- to 12-membered rings;
with the proviso that for —NR10C?O(R11), the two adjacent R10 and R11 radicals, together with the atom to which they are bonded, form a ring having a total of 3 to 12 atoms, where the ring is saturated or mono- or polyunsaturated and, as well as the atom to which the R10 or R11 radicals are bonded, have exclusively carbon atoms or one or more further heteroatoms selected from N, O and P, where the ring is unsubstituted and/or is fused to further unsubstituted 3- to 12-membered rings;
Y is C3-C20-alkyl, C3-C20-cycloalkyl, heterocycloalkyl having 3 to 20 ring atoms, C6-C30-aryl, heteroaryl having 5 to 30 ring atoms or a substituent with donor or acceptor action selected from the group consisting of C1-C20-alkoxy, C6-C30-aryloxy, C1-C20-alkylthio, C6-C30-arylthio, SiR10R11R12, halogen radicals, halogenated C1-C20-alkyl radicals, carbonyl(—CO(R10)), carbonylthio (—C?O(SR10)), carbonyloxy (—C?O(OR10)), oxycarbonyl (—OC?O(R10)), thiocarbonyl (—SC?O(R10)), amino (—NR10R11), OH, pseudohalogen radicals, amido (—C?O (NR10R11)), —NR10C?O(R11), phosphonate (—P(O)(OR10)2), phosphate (—OP(O)(OR10)2), phosphine (—PR10R11), phosphine oxide (—P(O)R102), sulfate (—OS(O)2OR10), sulfoxide (—S(O)R10), sulfonate (—S(O)2OR10), sulfonyl (—S(O)2R10), sulfonamide (—S(O)2NR10R11), NO2, boronic esters (—OB(OR10)2), imino (—C?NR10), borane radicals, stannane radicals, hydrazine radicals, hydrazone radicals, oxime radicals, nitroso groups, diazo groups, vinyl groups, sulfoximines, alanes, germanes, boroxines and borazines; or SiR10R11R12.

US Pat. No. 11,031,558

P-TYPE SEMICONDUCTOR FILM CONTAINING HETEROFULLERENE, AND ELECTRONIC DEVICE

PANASONIC INTELLECTUAL PR...

1. A p-type semiconductor film comprisinga fullerene C601,
wherein the fullerene C60 includes carbon atoms, a single boron atom, and a single nitrogen atom, and
the single boron atom is a substitution of a carbon atom at position 1 in the fullerene C60,
the single nitrogen atom is a substitution of another carbon atom at position 60 in the fullerene C60.

US Pat. No. 11,031,557

CONJUGATED POLYMERS BASED ON TERTHIOPHENE AND THEIR APPLICATIONS

RAYNERGY TEK INC., Hsinc...

1. A conjugated polymer containing 5 or more repeating units of Formula (II):
wherein Ar1 and Ar2 are aromatic units that are not thiophene, wherein a * bond is a bond to an additional unit of Formula (II) and there are three thiophene units between each Ar1 unit and Ar2 unit in the conjugated polymer, Ar1 and Ar2 are different from each other and independently selected from:

M5, M6, M7, M8, M9, M10, M11, M12 are H atom; and
R1 and R2 are independently selected from branched alkyl groups with 6-40 C atoms, in which one of more non-adjacent C atoms are optionally replaced by —O—, —S—, —C(O)—, —C(O—)—O—, —O—C(O)—, —O—C(O)—O—, —CR0=CR00- or—C?C— and in which one or more H atoms are optionally replaced by F, Cl, Br, I or CN, or denote aryl, heteroaryl, aryloxy, heteroaryloxy, arylcarbonyl, heteroarylcarbonyl, arylcarbonyloxy, heteroarylcarbonyloxy, aryloxycarbonyl or heteroaryloxycarbonyl having 4 to 30 ring atoms that is unsubstituted or substituted by one or more non-aromatic groups.

US Pat. No. 11,031,556

SYSTEMS AND METHODS FOR PHASE CHANGE MATERIAL BASED THERMAL ASSESSMENT

Taiwan Semiconductor Manu...

1. A method, comprising:growing a phase change material on a platform configured for a semiconductor workpiece process;
setting the phase change material to an amorphous state;
performing the semiconductor workpiece process within a semiconductor processing chamber, wherein the semiconductor workpiece process comprises at least one of: rapid thermal processing (RTP), physical vapor deposition (PVD) and dynamic surface annealing (DSA);
measuring resistance across two points along the phase change material; and
setting the phase change material to the amorphous state while performing the semiconductor workpiece process.

US Pat. No. 11,031,555

POWER HANDLING IMPROVEMENTS FOR PHASE-CHANGE MATERIAL (PCM) RADIO FREQUENCY (RF) SWITCH CIRCUITS

Newport Fab, LLC, Newpor...

1. A circuit comprising:a plurality of stacked phase-change material (PCM) radio frequency (RF) switches;
a PCM RF switch in said plurality of stacked PCM RF switches including:
a PCM;
a heating element transverse to said PCM;
first and second heating element contacts, wherein said first heating element contact is electrically coupled to an RF ground when said PCM RF switch is in an OFF state.

US Pat. No. 11,031,554

METHOD FOR MANUFACTURING A PASS-THROUGH DEVICE

1. A method for producing a via through a base layer of a microelectronic device, the method comprising:a formation of a hole in a first face of the base layer and a filling of the hole with at least one first filling material thereby forming an element which conducts electricity,
the method comprising an at least partial removal of the at least one first filling material over a depth, directed along a thickness dimension of the hole from the first face of the base layer, the depth being less than the thickness dimension of the hole so as to produce a hollow portion, and
the method comprising a second at least partial filling of the hollow portion with at least one second filling material, the second filling thereby forming at least one electrically conductive layer immediately above the element which conducts electricity,
wherein the second filling comprises a formation of at least one layer of the at least one second filling material in the hollow portion, then a formation of a clearance in said at least one layer to define a stack of a residual portion of the at least one layer circumscribed by the clearance.

US Pat. No. 11,031,553

METHOD, SYSTEM, AND DEVICE FOR PHASE CHANGE MEMORY SWITCH WALL CELL WITH APPROXIMATELY HORIZONTAL ELECTRODE CONTACT CROSS REFERENCES

OVONYX MEMORY TECHNOLOGY,...

1. A system, comprising:a first dielectric layer;
a second dielectric layer;
a memory array comprising one or more storage components that are formed over a selector layer and that at least partially enclose the first dielectric layer and the second dielectric layer; and
a processor configured to initiate a memory access command to access the memory array.

US Pat. No. 11,031,552

PCM RF SWITCH WITH PCM CONTACTS HAVING SLOT LOWER PORTIONS

Newport Fab, LLC, Newpor...

1. A method for fabricating contacts in an RF switch comprising a phase-change material (PCM) and a heating element approximately underlying an active segment of said PCM, the method comprising:forming a contact uniformity support layer over said PCM;
patterning said PCM and said contact uniformity support layer;
forming a contact dielectric over said contact uniformity support layer;
forming slot lower portions of PCM contacts extending through said contact dielectric and through said contact uniformity support layer, and connected to passive segments of said PCM;
forming wide upper portions of said PCM contacts over said contact dielectric and over said slot lower portions of said PCM contacts;
wherein said contact dielectric separates said wide upper portion of said PCM contacts from said heating element so as to reduce a parasitic capacitance of said RF switch.

US Pat. No. 11,031,551

LIGHT-ACTIVATED SWITCHING RESISTOR, AN OPTICAL SENSOR INCORPORATING A LIGHT-ACTIVATED SWITCHING RESISTOR, AND METHODS OF USING SUCH DEVICES

UCL BUSINESS LTD, London...

1. A switching resistor comprising a dielectric layer disposed between a first electrode layer, the first electrode layer comprising a p-type semiconductor or an n-type semiconductor, and a second electrode layer, wherein the dielectric layer is an oxide of silicon,the switching resistor having a high resistance state and a low resistance state; the switching resistor being responsive to a voltage bias, applied between the first electrode layer and the second electrode layer, exceeding a threshold to switch from the high resistance state to the low resistance state, wherein the first electrode layer comprises a substrate configured to absorb photo-illumination to generate free carriers, and wherein said switching resistor is sensitive to photo-illumination to reduce said threshold.

US Pat. No. 11,031,550

PHASE-CHANGE MEMORY CELL HAVING A COMPACT STRUCTURE

STMicroelectronics (Croll...

1. A process for fabricating a memory cell, the process comprising:covering a semiconductor substrate with a first insulating layer;
covering the first insulating layer with an active layer of a semiconductor material;
forming a first control gate and first and second conduction regions of a first selection transistor;
covering, with a second insulating layer, a lateral flank of the first control gate on the same side as the first conduction region;
forming a first trench through the active layer in the first conduction region, reaching the first insulating layer;
depositing a first layer in the first trench, covering a first lateral flank of the active layer in the trench; and
depositing a second layer in contact with the first layer, wherein the second layer is a variable-resistance material, extends longitudinally in a plane parallel to the surface of the substrate and makes contact with an upper portion of the first layer, the first layer including a first resistor configured to heat the second layer in order to make the second layer change phase between a non-conductive amorphous phase and a conductive crystalline phase.

US Pat. No. 11,031,549

MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) DEVICE

SAMSUNG ELECTRONICS CO., ...

1. An MRAM device comprising:a lower electrode layer on a substrate;
an MTJ structure on the lower electrode layer, the MTJ structure including:
a fixed layer structure;
a tunnel barrier structure on the fixed layer structure;
a free layer on the tunnel barrier structure; and
an upper oxide layer on the free layer; and
an upper electrode layer on the MTJ structure,
wherein the tunnel barrier structure has first and second tunnel barrier layers sequentially stacked, the first and second tunnel barrier layers including a first metal oxide and a second metal oxide, respectively, and the second tunnel barrier layer having a metal content less than a metal content of the first tunnel barrier layer, and
wherein the upper oxide layer includes a third metal oxide.

US Pat. No. 11,031,548

REDUCE INTERMIXING ON MTJ SIDEWALL BY OXIDATION

Headway Technologies, Inc...

1. A method for magnetic tunnel junction (MTJ) fabrication comprising:depositing a MTJ film stack on a bottom electrode on a substrate;
first etching said MTJ film stack to form a MTJ device wherein conductive re-deposition forms on sidewalls of said MTJ device;
thereafter first oxidizing said conductive re-deposition;
thereafter second etching said MTJ device to remove oxidized said re-deposition; and
thereafter second oxidizing any remaining conductive re-deposition on said sidewalls of said MTJ device.

US Pat. No. 11,031,547

REDUCTION OF CAPPING LAYER RESISTANCE AREA PRODUCT FOR MAGNETIC DEVICE APPLICATIONS

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a capped ferromagnetic layer having a perpendicular-to-plane magnetic anisotropy, comprising:providing a ferromagnetic layer having an upper surface;
applying a first plasma treatment to the upper surface of the ferromagnetic layer to smooth the surface and provide a barrier to oxygen diffusion;
forming an oxide layer, as a cap, on the plasma-treated upper surface of the ferromagnetic layer to promote a perpendicular-to-plane magnetic anisotropy in the ferromagnetic layer; and
annealing the capped ferromagnetic layer to provide an enhanced anisotropy field (Hk) and coercivity field (Hc), wherein a region between an upper surface of the oxide layer and the plasma-treated upper surface of the ferromagnetic layer is characterized by an oxygen concentration profile that approaches approximately zero at the plasma-treated upper surface of the ferromagnetic layer after the annealing of the capped ferromagnetic layer.

US Pat. No. 11,031,546

METHOD OF INTEGRATION OF A MAGNETORESISTIVE STRUCTURE

Everspin Technologies, In...

1. A method of manufacturing an interconnect to a magnetoresistive structure, the method comprising:forming at least one via on a first surface of a first dielectric layer, the at least one via including sidewalls;
depositing a first electrically conductive material in the at least one via to form a first layer of the first electrically conductive material on at least a portion of the sidewalls of the at least one via;
after forming the first layer, depositing a second electrically conductive material to at least partially fill the at least one via and form a layer of the second electrically conductive material above a first surface of the first dielectric layer;
polishing an exposed surface of the layer of the second electrically conductive material, wherein at least a portion of the layer of the second electrically conductive material above the first surface remains after the polishing, and a top surface of the first dielectric layer is covered by the second electrically conductive material; and
forming a magnetoresistive structure above the layer of the second electrically conductive material after the polishing;
wherein (a) the step of depositing the second electrically conductive material fills the at least one via and covers an opening of the at least one via on the first surface, and the exposed surface of the layer of the second electrically conductive material includes a depression at a location corresponding to the location of the opening, and (b) the step of polishing the exposed surface of the layer of the second electrically conductive material removes the depression.

US Pat. No. 11,031,545

HIGH STABILITY FREE LAYER FOR PERPENDICULAR SPIN TORQUE TRANSFER MEMORY

Intel Corporation, Santa...

1. An apparatus for magnetoresitive memory, the apparatus comprising:a fixed layer;
a free layer, the free layer being a single layer consisting of an alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio;
a tunneling barrier between the fixed layer and the free layer, the free layer directly on the tunneling barrier; and
a cap layer directly on the free layer.

US Pat. No. 11,031,544

MEMORY DEVICE WITH SUPERPARAMAGNETIC LAYER

Taiwan Semiconductor Manu...

1. A compound free layer for a memory device, comprising:a ferromagnetic free layer;
a non-magnetic barrier layer overlying the ferromagnetic free layer, the non-magnetic barrier layer meeting the ferromagnetic free layer at an interface extending in parallel with an in-plane direction; and
a first superparamagnetic free layer overlying the non-magnetic barrier layer, the first superparamagnetic free layer having a magnetization component that is superparamagnetic in the in-plane direction, wherein the first superparamagnetic free layer comprises a plurality of superparamagnetic nano-particles.

US Pat. No. 11,031,543

VIA LANDING ENHANCEMENT FOR MEMORY DEVICE

Taiwan Semiconductor Manu...

1. A method for manufacturing a memory cell, the method comprising:forming a multi-layer stack comprising a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, a top electrode layer over the resistance switching dielectric layer, and a hard mask layer over the top electrode layer;
performing a first series of etch to pattern the hard mask layer, the top electrode layer and the resistance switching dielectric layer to form a hard mask, a top electrode and a resistance switching dielectric;
forming a first dielectric spacer layer over the bottom electrode layer, extending alongside the resistance switching dielectric, the top electrode, and the hard mask, and further extending over the hard mask; and
forming a second dielectric spacer layer having a bottom surface over the bottom electrode layer and a sidewall surface contacting the first dielectric spacer layer;
wherein the first dielectric spacer layer is deposited at a first temperature and the second dielectric spacer layer is deposited at a second temperature higher than that of the first temperature.

US Pat. No. 11,031,542

CONTACT VIA WITH PILLAR OF ALTERNATING LAYERS

INTERNATIONAL BUSINESS MA...

1. A back end of line (BEOL) metallization structure comprising:a vertical via structure intermediate and in electrical contact with an overlying pillar device and an underlying conductor, wherein the vertical via structure comprises an insulator material on sidewalls thereof, wherein the vertical via structure has a width dimension less than the width dimensions of the overlying pillar device and the underlying conductor, and wherein the pillar device comprises layers of a metal and layers of a metal oxide formed in an alternating fashion.

US Pat. No. 11,031,541

SPIN-ORBIT TORQUE TYPE MAGNETIZATION ROTATING ELEMENT, SPIN-ORBIT TORQUE TYPE MAGNETORESISTANCE EFFECT ELEMENT, AND MAGNETIC MEMORY

TDK CORPORATION, Tokyo (...

1. A spin-orbit torque type magnetization rotating element, comprising:a spin-orbit torque wiring extending in a first direction; and
a first ferromagnetic layer laminated on one surface of the spin-orbit torque wiring such that a first side of the first ferromagnetic layer faces the one surface of the spin-orbit torque wiring, wherein:
the spin-orbit torque wiring includes a first wiring and a second wiring in an order from the first side of the first ferromagnetic layer; and
the first wiring is made of a metal and the second wiring is made of a semiconductor.

US Pat. No. 11,031,540

SUBSTITUTED ALUMINUM NITRIDE FOR IMPROVED ACOUSTIC WAVE FILTERS

SKYWORKS SOLUTIONS, INC.,...

1. A piezoelectric material comprising:AlN doped with cations of one or more elements selected from the group consisting of:
a) one of Sb, or Nb;
b) Cr in combination with one or more of B, Sc, Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, or Yb;
c) one of Nb and Ta in combination with one of Li, Ca, Ni, or Co; or
d) one or more of Co, Sb, Ta, Nb, Si, or Ge in combination with one or more of Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, or Yb;
the cations at least partially substituting for Al in a crystal structure of the piezoelectric material.

US Pat. No. 11,031,539

PIEZOELECTRIC VIBRATOR AND SENSOR

PIEZO STUDIO INC., Miyag...

1. A piezoelectric vibrator comprising at least one vibrating piece made of a Ca3Ta(Ga1-xAlx)3Si2O14 single crystal (0

US Pat. No. 11,031,538

LIQUID EJECTION APPARATUS

BROTHER KOGYO KABUSHIKI K...

1. A head, comprising:an actuator comprising a plurality of first contacts,
wherein two protrusions and a recess are formed on and in each of the plurality of first contacts, the two protrusions being arranged in a first direction parallel with a placement surface of each of the plurality of first contacts, the recess being interposed between the two protrusions, and
wherein the plurality of first contacts are arranged at an interval of less than or equal to 21 ?m.

US Pat. No. 11,031,537

SYSTEMS, METHODS AND APPARATUS FOR ACTIVE COMPENSATION OF QUANTUM PROCESSOR ELEMENTS

D-WAVE SYSTEMS INC., Bur...

1. A circuit comprising:an input current path;
an output current path;
a primary compound Josephson junction structure comprising:
a closed loop connected to the input current path at a first node and the output current path at a second node, the closed loop comprising two primary electrically parallel current paths between the first node and the second node, each primary electrically parallel current path formed of a material that is superconducting below a critical temperature, wherein current flow from the input current path is restricted to the two primary electrically parallel current paths until reaching the output current path; and
at least two Josephson junction structures, each of which interrupts a respective one of the two primary electrically parallel current paths between the first node and the second node;
wherein the Josephson junction structure in a first one of the two primary electrically parallel current paths includes a first secondary compound Josephson junction structure nested within the primary compound Josephson junction structure, the first secondary compound Josephson junction structure comprising two secondary electrically parallel current paths that are each formed of a material that is superconducting below a critical temperature, and at least two Josephson junctions, each of which interrupts a respective one of the two secondary electrically parallel current paths;
a first programming interface that is positioned to couple a control signal to the primary compound Josephson junction structure; and
a second programming interface that is positioned to couple a control signal to the first secondary compound Josephson junction structure, the second programming interface operable to tune a characteristic of the first secondary compound Josephson junction structure to match a characteristic of the Josephson junction structure in a second one of the two primary electrically parallel current paths.

US Pat. No. 11,031,536

VEHICLE BATTERY THERMOELECTRIC DEVICE WITH INTEGRATED COLD PLATE ASSEMBLY AND METHOD OF ASSEMBLING SAME

Gentherm Incorporated, N...

1. A cooling system for thermally conditioning a component, the cooling system comprising:a battery;
a heat spreader supporting the battery;
multiple thermoelectric devices operatively secured to the heat spreader, wherein each of the multiple thermoelectric devices include pellets consisting of p-n materials, the pellets are directly secured to and between pads by a first solder having a first melting point, wherein one pad secured directly to one side of the pellets is secured to a cold side substrate by the first solder, and another pad secured to another side of the pellets is secured directly to a hot side substrate by the first solder;
a cold side plate is secured to the cold side substrate, the heat spreader operatively thermally engaging the thermoelectric device via the cold side plate, the cold side plate is secured to the heat spreader by a second solder having a second melting point that is less than the first melting point;
a hot side plate is secured to the hot side substrate;
a cold plate assembly operatively thermally engaging the thermoelectric devices via the hot side plate;
a thermal foil securing the cold plate assembly to the hot side plate; and
a DC/DC converter arranged in operative thermal engagement with the cold plate assembly.

US Pat. No. 11,031,535

THERMOELECTRIC POWER GENERATION SYSTEM

YANMAR POWER TECHNOLOGY C...

1. A thermoelectric power generation system comprising: a plurality of thermoelectric power generation devices, wherein: each of the thermoelectric power generation devices comprises:a heating unit having a heat medium passage configured for flow of a heat medium flows, medium, a cooling unit having a cooling liquid passage in which configured for flow of a cooling liquid,
a thermoelectric element having the heating unit on one side thereof and the cooling unit on another side thereof, the thermoelectric element configured to generate power by utilizing a temperature difference between a condensation temperature of the heat medium that undergoes latent heat transfer in the heat medium passage and a temperature of the cooling liquid, and
a heat transfer pipe in fluid communication with the heat medium passage to form a circulation path associated with the heat medium, and
each heat transfer pipe of the plurality of thermoelectric power generation devices is arranged in a single flow path configured for flow of a high temperature fluid,
each heat medium passage of the plurality of thermoelectric power generation devices is in fluid communication each other heat medium passage of the plurality of thermoelectric power generation devices, and
each circulation path of the plurality of thermoelectric power generation devices is configured to include an amount of heat medium based on a position of a corresponding heat transfer pipe, the amount of heat medium based on a first position of the corresponding heat transfer pipe less than an amount of heat medium based on a second position of the corresponding heat transfer pipe, the corresponding heat transfer pipe configured to receive more heat in the first position than the second position.

US Pat. No. 11,031,534

RADIATION-EMITTING SEMICONDUCTOR CHIP

OSRAM OLED GMBH, Regensb...

1. A radiation-emitting semiconductor chip comprising:a carrier comprising:
a first main surface and a second main surface opposite to the first main surface;
an n-doped layer and a p-doped layer forming a pn-junction; and
a vertical region starting from the first main surface and running parallel to side faces of the carrier, wherein the vertical region is n-doped, p-doped or electrically insulating, and wherein the vertical region extends within a boundary region of the carrier and completely encloses a central volume region of the carrier;
an epitaxial semiconductor layer sequence having an active zone configured to generate electromagnetic radiation during operation, the epitaxial semiconductor layer sequence being located at the first main surface of the carrier; and
two electrical contacts disposed on a front side of the radiation-emitting semiconductor chip.

US Pat. No. 11,031,533

LIGHT-EMITTING DEVICE, LIGHT-EMITTING MODULE, AND BACKLIGHT MODULE

DARWIN PRECISIONS CORPORA...

1. A light-emitting device comprising:a second lens having a light-emitting surface, a bottom surface, a plurality of side surfaces, and an accommodation hole, wherein the bottom surface is corresponded to the light-emitting surface, and the side surfaces connect the light-emitting surface and the bottom surface, and the accommodation hole passes through the second lens;
a light-emitting unit, wherein the accommodation hole accommodates the light-emitting unit, and the light-emitting unit has a light-emitting chip, an encapsulation covering the light-emitting chip, and a first shading layer disposed on the encapsulation; and
a second shading layer disposed on the first shading layer and the light-emitting surface, the second shading layer having an opening corresponding to a position of the first shading layer, and the opening of the second shading layer corresponding to part of the first shading layer.

US Pat. No. 11,031,532

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a base having a mounting surface with a conductor wiring;
at least one LED package, each of the at least one LED package comprising:
a light emitting element mounted on the mounting surface of the base and electrically connected to the conductor wiring, the light emitting element having a light axis direction substantially perpendicular to the mounting surface, the light emitting element having a lower surface facing the base, an upper surface opposite to the lower surface, and a side surface connecting the lower surface and the upper surface;
a wavelength converter provided on the upper surface of the light emitting element; and
a reflection member provided directly on the side surface of the light emitting element to cover the side surface and the lower surface of the light emitting element; and
at least one light transmissive sealing member, each of the at least one light transmissive sealing member including a light diffusion material and covering the wavelength converter and the reflection member of each of the at least one LED package, each of the at least one light transmissive sealing member having a projection shape with a substantially circular bottom surface facing the base and with a height in the light axis direction of the light emitting element.

US Pat. No. 11,031,531

OPTOELECTRONIC COMPONENT AND METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT

OSRAM OLED GmbH, Regensb...

1. An optoelectronic component comprising a housing comprising a first cavity bounded by a first wall, wherein a circumferentially extending first step is formed at an inner side of the first wall, the first step circumferentially extends around the first cavity obliquely with respect to a bottom of the first cavity, a first optoelectronic semiconductor chip is arranged at the bottom of the first cavity, the first optoelectronic semiconductor chip is embedded into a first potting material arranged in the first cavity and extending from the bottom of the first cavity as far as the first step, a first potting surface of the first potting material is formed at the first step, and the first potting surface of the first potting material is likewise formed obliquely in a manner corresponding to an angle of inclination of the first step formed obliquely with respect to the bottom of the first cavity.

US Pat. No. 11,031,530

LIGHT EMITTING DEVICE WITH NANOSTRUCTURED PHOSPHOR

Lumileds LLC, San Jose, ...

1. A structure comprising:a semiconductor light emitting device; and
a wavelength converting region comprising:
a nanostructured wavelength converting material configured to absorb pump light and emit converted light, the nanostructured wavelength converting material comprising particles having at least one dimension that is no more than 100 nm in length; and
a transparent matrix in which the nanostructured wavelength converting material is disposed,
a spacing between the wavelength converting region and the semiconductor light emitting device is greater than 0 nm and no more than 10 mm; and
a phosphor, the phosphor disposed between the nanostructured wavelength converting material and the semiconductor light emitting device, the phosphor not in direct contact with the nanostructured wavelength converting material and not in direct contact with the semiconductor light emitting device.

US Pat. No. 11,031,529

WAVELENGTH CONVERTING MATERIAL FOR A LIGHT EMITTING DEVICE

Lumileds LLC, San Jose, ...

1. A wavelength converting material, comprising:a ceramic material comprising:
a (Ba1-xSrx)2-zSi5-yO4yN8-4y:Euz wavelength converting material in a first crystalline phase where 0.5?x?0.9; 0?y?1; and 0.001?z?0.02; and
a M3Si3O3N4 material in a second crystalline phase where M is Ba, Sr, Eu, or combinations thereof; the second crystalline phase different from the first crystalline phase and comprising no more than 5 weight % of a total amount of crystalline phases in the ceramic material.

US Pat. No. 11,031,528

DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF

Innolux Corporation, Mia...

1. An apparatus, comprising:a substrate;
a metal layer disposed on the substrate, wherein a first distance is between an upper surface of the metal layer and the substrate in a direction perpendicular to the substrate; and
a light-emitting diode disposed on the metal layer, wherein the light-emitting diode comprises a light-emitting diode body and an electrode, the electrode is bonded to the metal layer, the light-emitting diode body has a first surface and a second surface opposite to the first surface, the first surface faces the substrate, and in the direction, a second distance is between the first surface and the second surface, wherein a ratio of the second distance to the first distance is greater than or equal to 0.25 and less than or equal to 6.

US Pat. No. 11,031,527

REFLECTIVE LAYERS FOR LIGHT-EMITTING DIODES

CreeLED, Inc., Durham, N...

1. A light-emitting diode (LED) chip comprising:an active LED structure comprising an active layer between an n-type layer and a p-type layer;
a first reflective layer adjacent the active LED structure and comprising a plurality of dielectric layers that forms an aperiodic Bragg reflector;
a second reflective layer on the first reflective layer;
a barrier layer on the second reflective layer;
a passivation layer on the barrier layer; and
a metal-containing interlayer embedded within the passivation layer, wherein the metal-containing interlayer is electrically isolated from the active LED structure.

US Pat. No. 11,031,526

SEMINCONDUCTOR CHIP HAVING INTERNAL TERRACE-LIKE STEPS AND METHOD FOR PRODUCING A SEMICONDUCTOR CHIP

OSRAM OLED GmbH, Regensb...

1. A semiconductor chip comprising:a semiconductor body comprising a first semiconductor layer, a second semiconductor layer, and an active layer located therebetween;
a current expansion layer disposed in a vertical direction between a contact structure and the semiconductor body; and
the contact structure;
wherein the semiconductor body has a plurality of internal steps formed in a terrace structure; and
wherein the contact structure comprises a plurality of conductor tracks, wherein regarding their lateral orientations, the conductor tracks are arranged with regard to the lateral orientations of the internal steps in such a way that a current expansion along the internal steps is favored over a current expansion transverse to the internal steps.

US Pat. No. 11,031,525

MICRO LIGHT EMITTING DIODE CHIP AND DISPLAY PANEL HAVING A BACKPLANE AND A PLURALITY OF SUB-PIXELS REGIONS

PlayNitride Inc., Hsinch...

1. A display panel comprises:a backplane, having a plurality of sub-pixel regions and a plurality of pads; and
a plurality of micro light emitting diode chips located in the sub-pixel regions, wherein each of the micro light emitting diode chips has a plurality of light-emitting regions and comprises:
a semiconductor epitaxial structure, comprising a plurality of first-type doped semiconductor layers disposed at interval, a plurality of second-type doped semiconductor layers disposed at interval and a plurality of light-emitting layers disposed in the light-emitting regions at interval, wherein the plurality of light-emitting layers are located between the plurality of first-type doped semiconductor layers and the plurality of second-type doped semiconductor layers, respectively, and the plurality of light-emitting layers are electrically contacted to the plurality of first-type doped semiconductor layers, respectively;
a first electrode, electrically connected and directly contacted to the first-type doped semiconductor layers, and overlapped with the second-type doped semiconductor layers and the light-emitting layers; and
a plurality of second electrodes, disposed at interval and electrically connected to the second-type doped semiconductor layers,
wherein the micro light emitting diode chips are electrically connected to the backplane through the pads and the backplane controls the micro light emitting diode chips to emit light in the corresponding sub-pixel regions,
wherein areas of the light-emitting layers are different from each other and the light-emitting layers are independently controlled,
wherein a type of carriers provided by the first electrode is a first type carrier and the other type of carriers provided by the second electrodes is a second type carrier, the first electrode and one of the second electrodes provide the first type carrier and the second type carrier to one of the light-emitting layers, and the first electrode and another one of the second electrodes provide the first type carrier and the second type carrier to another one of the light-emitting layers,
wherein the first electrode is electrically connected to one of the pads of the backplane for providing the first type carrier, and at least one of the second electrodes is electrically connected to another one of the pads of the backplane for providing the second type carrier.

US Pat. No. 11,031,524

OPTOELECTRONIC COMPONENT HAVING A LAYER WITH LATERAL OFFSET INCLINED SIDE SURFACES

OSRAM OLED GMBH, Regensb...

1. An optoelectronic component comprising:a layer structure, comprising an active zone for generating an electromagnetic radiation, wherein the active zone comprises a plurality of layers of the layer structure, wherein the active zone is arranged in a first plane perpendicular to a layer stacking direction of the plurality of layers, wherein a surface of the layer structure has a recess formed therein, wherein the recess adjoins side face of the component and extends from the side face into the layer structure, wherein the side face is arranged in a second plane and extends from a topmost surface of the layer structure, past the recess with the recess forming an edge of the side face, to a bottom surface of the layer structure, wherein the second plane is substantially perpendicular to the first plane, wherein the recess comprises a bottom recess face and a first side recess face, wherein the first side recess face is arranged substantially perpendicularly to the side face, wherein the first side recess face is arranged in a manner inclined at an angle different from 90° with respect to the plane of the active zone, wherein the bottom recess face is arranged in a region of the first plane of the active zone, wherein the recess further comprises a second side recess face, and wherein the second side recess face is arranged opposite with respect to the first side recess face, wherein the first and second side recess faces are arranged at different angles with respect to the plane of the active zone.

US Pat. No. 11,031,523

MANUFACTURING METHOD OF MICRO LED DISPLAY MODULE

SYNDIANT INC., Dallas, T...

1. A manufacturing method of micro light emitting diode (LED) display module, the manufacturing method comprising the following steps:initially, preparing a LED wafer and a driver circuit wafer, wherein a portion of the LED wafer is defined as a LED block, a chip size portion of the driver circuit wafer is defined as a driver chip block, wherein the LED block has a first semiconductor layer, a light emitting layer and a second semiconductor layer, the light emitting layer is disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer connects with a substrate, and the first semiconductor layer is a N-type semiconductor layer and the second semiconductor layer is a P-type semiconductor layer;
next, disposing a light transmissive conductive layer on the second semiconductor layer;
next, removing the substrate;
next, etching the LED block to form a plurality of trenches arranged crisscrossingly, wherein the trenches define a plurality of micro LED pixels arranged in an array, each of the trenches at least penetrates through the first semiconductor layer and the light emitting layer, and the second semiconductor layer is not penetrated through by each of the trenches, wherein the light transmissive conductive layer has a common electrode corresponds to the micro LED pixels;
next, bonding the LED block and the driver chip block to each other, wherein the first semiconductor layer is electrically connected to a plurality of pixel electrodes of the driver chip block, and each of the micro LED pixels corresponding to one of the pixel electrodes; and
next, disposing a color layer on the light transmissive conductive layer, wherein the color layer is a red, green and blue color layer.

US Pat. No. 11,031,522

OPTICAL SEMICONDUCTOR ELEMENT COMPRISING N-TYPE ALGAN GRADED LAYER

STANLEY ELECTRIC CO., LTD...

1. An optical semiconductor element comprising:an AlN single crystal growth substrate;
an n-type semiconductor layer composed of AlGaN layers, one of the AlGaN layers being grown on the AlN single crystal growth substrate and being pseudomorphic with the AlN single crystal growth substrate, Al compositions of the AlGaN layers being reduced with an increase in distance from the AlN single crystal growth substrate;
an active layer which is grown on the n-type semiconductor layer; and
a p-type semiconductor layer which is grown on the active layer;
wherein a surface of the AlN single crystal growth substrate on an opposite side thereof from the n-type semiconductor layer is an outermost surface of the optical semiconductor element; and
wherein the n-type semiconductor layer includes:
a first composition gradient layer which is grown on the AlN single crystal growth substrate to have a composition of Alx1Ga1-x1N (0.7?x1?1) such that the Al composition x1 of the first composition gradient layer is within a range of 0.95 to 1 at a side thereof adjacent to an interface with the AlN single crystal growth substrate, and such that the Al composition x1 is gradually reduced at a first rate in a range of 0.5 to 2/?m from the side adjacent to the interface with the AlN single crystal growth substrate toward the active layer; and
a second composition gradient layer which is grown on the first composition gradient layer such that the second composition gradient layer has a same Al composition at an interface between the first and second composition gradient layers as the Al composition x1 of the first composition gradient layer at the interface between the first and second composition gradient layers and such that the Al composition of the second composition gradient layer is gradually reduced at a second rate that is smaller than the first rate from the first composition gradient layer toward the active layer.

US Pat. No. 11,031,521

FLEXIBLE TRANSPARENT THIN FILM

New Asia Group Holdings L...

1. A transparent conductive film comprising:at least one transparent substrate; anda conductive network being integrated into said at least one transparent substrate and having an aspect ratio of at least 1.5 with a protrusion exposed out of said at least one transparent substrate for contacting with an external structure,wherein said conductive network has a rough surface,
wherein said substrate is selected from polymer resin or vanish,
wherein said conductive network is patterned to have an irregular polygon shape, and
said irregular polygon shape is introduced to a periodic polygon pattern in order to suppress optical interference.

US Pat. No. 11,031,520

ADVANCED HYDROGEN PASSIVATION THAT MITIGATES HYDROGEN-INDUCED RECOMBINATION (HIR) AND SURFACE PASSIVATION DETERIORATION IN PV DEVICES

NEWSOUTH INNOVATIONS PTY ...

1. A method for processing a silicon-based photovoltaic device having doped silicon regions that are doped with a hydrogen concentration of at least 1e16 atoms/cm3, the method comprising the steps of:(a) providing the photovoltaic device, wherein the photovoltaic device includes hydrogen;
(b) thermally treating at least a portion of the photovoltaic device by heating the photovoltaic device in an environment with a temperature above 600° C., such that hydrogen migrates towards at least one of the doped regions so that a concentration of hydrogen within the at least one of the doped regions increases to above a minimum concentration of hydrogen at which hydrogen causes degradation to the electrical characteristics of that region;
(c) applying an electric field across at least a portion of the photovoltaic device in a manner such that, charged hydrogen atoms are driven away, by the electric field, from the at least one of the doped silicon regions;
wherein:
step (b) is conducted such that hydrogen atoms distribute within the at least one of the doped silicon regions;
step (c) comprises applying a forward biasing electric field across the photovoltaic device to promote drifting of charged hydrogen atoms away from regions with high atomic hydrogen concentration; and
step (c) is conducted such that hydrogen migrates out of the at least one of the doped silicon regions.

US Pat. No. 11,031,519

LIGHT RECEIVING UNIT

AZUR SPACE Solar Power Gm...

1. A light receiving unit comprising:a first energy source, the first energy source comprising a first and a second sub source formed as a current source or a voltage source, the first energy source only having a first electric terminal contact and a second electric terminal contact, the first terminal contact being formed on an upper face of the first sub source and the second terminal contact being formed on a lower face of the second sub source;
at least one first semiconductor diode provided in the first sub source; and
at least one second semiconductor diode provided in the second sub source,
wherein the first semiconductor diode has an absorption edge adapted to a first wavelength of light and the second semiconductor diode has an absorption edge adapted to a second wavelength of light so that the first sub source generates an electric voltage upon being irradiated with the first wavelength of light and the second sub source generates an electric voltage upon being irradiated with the second wavelength of light,
wherein the first wavelength of light differs from the second wavelength of light by a differential wavelength,
wherein the first semiconductor diode is connected in series with the second semiconductor diode so that a polarization of the first semiconductor diode is opposite to a polarization of the second semiconductor diode, such that the voltage generated by the first semiconductor diode and the second semiconductor diode at least partly compensate for each other, and
wherein a current distribution layer is arranged between the first sub source and the second sub voltage source.

US Pat. No. 11,031,518

PHOTOVOLTAIC MODULE COMPRISING A CONCENTRATION OPTIC WITH SUBWAVELENGTH PATTERNS AND SOLAR GENERATOR FOR SATELLITE COMPRISING SAID MODULE

THALES, Courbevoie (FR)

1. A photovoltaic module comprising:at least one photovoltaic cell; and
at least one concentration optic device configured to be illuminated by a light flux emitting at at least one illumination wavelength belonging to a band of wavelengths defined by a minimum wavelength and a maximum wavelength, said band of wavelengths being of solar radiation on an order of 380 nm to 1600 nm,
wherein said at least one concentration optic device is a monolithic component having a first surface and a second surface, said at least one concentration optic device comprising at least one diffractive structure on said first surface and a focusing structure on said first surface, each surface operating in transmission, said at least one diffractive structure having one level subwavelength patterns with at least one dimension less than or equal to an average illumination wavelength divided by a refractive index of said at least one concentration optic device, said subwavelength patterns being separated by subwavelength distances between centers of adjacent subwavelength patterns,
wherein said one level subwavelength patterns codes a variation of effective index in the plane of said first surface, and said subwavelength distances are periodic, and
wherein the focusing structure comprises a second diffractive structure comprising subwavelength patterns.

US Pat. No. 11,031,517

METHOD OF MANUFACTURING LIGHT TRANSMISSION TYPE COMPOUND THIN FILM, COMPOUND THIN FILM MANUFACTURED THEREFROM, AND SOLAR CELL INCLUDING THE SAME

Korea Institute of Scienc...

1. A method of manufacturing a compound thin film, comprising:configuring an electrodeposition circuit by connecting an electrolytic solution, which is manufactured by mixing a predetermined precursor with a solvent, and an electrochemical cell, which includes a working electrode in a form of an electrode at which a specific pattern is patterned on a predetermined substrate, to a voltage application device or a current application device; and
applying a reduction voltage or current to the working electrode using the voltage application device or the current application device, and selectively electrodepositing a thin film in some region of the electrode along a shape of the electrode at which the specific pattern is patterned;
wherein the specific pattern is a pattern formed by a plurality of hollows having different light transmittance areas.

US Pat. No. 11,031,516

PHOTOELECTRIC CONVERSION ELEMENT, PHOTOELECTRIC CONVERSION MODULE, AND SOLAR PHOTOVOLTAIC POWER GENERATION SYSTEM

SHARP KABUSHIKI KAISHA, ...

1. A photoelectric conversion element comprising:a semiconductor substrate;
a first non-crystalline semiconductor layer having a first conductive type;
a second non-crystalline semiconductor layer having a second conductive type opposite to the first conductive type;
a first electrode which is in contact with the first non-crystalline semiconductor layer; and
a second electrode which is in contact with the second non-crystalline semiconductor layer,
wherein the first electrode includes a first transparent conductive layer formed on the first non-crystalline semiconductor layer and a first metal layer formed on the first transparent conductive layer,
wherein the first metal layer includes a plurality of metal crystal grains,
wherein an average crystal grain size of the plurality of metal crystal grains in an in-surface direction of the first metal layer is greater than 1.5 times a thickness of the first metal layer,
wherein the plurality of metal crystal grains includes metal crystal grains oriented in a <110> direction, metal crystal grains oriented in a <100> direction, and metal crystal grains oriented in a <111> direction,
wherein each of the <100> direction, the <110> direction, and the <111> direction is within 10 degrees with respect to a thickness direction of the semiconductor substrate, and
wherein an area of the plurality of metal crystal grains oriented in the <111> direction is greater than an area of the plurality of metal crystal grains oriented in the <100> direction and an area of the plurality of metal crystal grains oriented in the <110> direction.

US Pat. No. 11,031,515

SEPARATION REGION BETWEEN DIFFUSION REGIONS IN A CONTINUOUS LAYER OF A SOLAR CELL

SunPower Corporation, Sa...

1. A solar cell comprising:a silicon substrate having a front side that faces towards the sun during normal operation and a back side opposite the front side;
a dielectric layer disposed over the back side of the silicon substrate;
a polysilicon layer disposed over the dielectric layer;
a P-type diffusion region disposed in the polysilicon layer;
an N-type diffusion region disposed in the polysilicon layer;
a separation region disposed in the polysilicon layer and between the P-type diffusion region and the N-type diffusion-region, the separation region having higher resistivity than either the P-type diffusion region or the N-type diffusion region;
a first metal finger disposed over the back side of the silicon substrate and electrically connected to the P-type diffusion region; and
a second metal finger disposed over the back side of the silicon substrate and electrically connected to the N-type diffusion region.

US Pat. No. 11,031,514

SOLAR CELL WITH SELECTIVELY DOPED CONDUCTIVE OXIDE LAYER AND METHOD OF MAKING THE SAME

1. A solar cell comprisinga first substrate having a first surface and a second surface;
a first conductive layer over at least a portion of the second surface, the first conductive layer comprising zinc stannate doped with a dopant having a non-uniform profile, wherein the first conductive layer comprises a first portion having a dopant, a second portion over the first portion having an amount of dopant, the amount of dopant being less than an amount of dopant in the first portion, a third portion over the second portion having more dopant than the amount of dopant in the second portion and less dopant than the first portion; a fourth portion having less dopant than the first, second, and third portion; and a fifth portion having less dopant than the first and third portions and more dopant than the second and fourth portions;
a semiconductor layer over the first conductive layer; and
a second conductive layer over at least a portion of the semiconductor layer.

US Pat. No. 11,031,513

INTEGRATED SILICON CARBIDE ULTRAVIOLET SENSORS AND METHODS

1. An ultraviolet sensitive engine probe apparatus for use in an engine using an engine block head, the engine including a combustion chamber securing combustion events generating ultraviolet light, the apparatus comprising:a silicon carbide photo transistor converting the ultraviolet light to a light voltage;
a probe casing surrounding the silicon carbide photo transistor, the probe casing mounted adjacent to the combustion chamber, the probe casing including threads fitting in the engine block head,
the probe casing including a quartz window mounted in the probe casing, the silicon carbide photo transistor positioned to receive ultraviolet light from the quartz window allowing ultraviolet light outside the probe casing to reach the light penetration zone.

US Pat. No. 11,031,512

SOLAR CELL, MULTIJUNCTION SOLAR CELL, SOLAR CELL MODULE, AND SOLAR POWER GENERATION SYSTEM

KABUSHIKI KAISHA TOSHIBA,...

1. A solar cell comprising:a substrate having a light transmitting property;
a first electrode including a plurality of metal portions and having a light transmitting property;
a light absorbing layer disposed on the first electrode and absorbing light; and
a second electrode disposed on the light absorbing layer and having a light transmitting property,
wherein the plurality of metal portions is in direct contact with the light absorbing layer,
at least one part of the plurality of metal portions is separated,
each of the plurality of metal portions has a dot shape,
the plurality of metal portions is not in direct contact with each other,
the plurality of metal portions consist of metal,
a thickness of the plurality of metal portions is 50 nm or more, and wherein the first electrode consists essentially of one or more semiconductor films and the plurality of metal portions, and side surfaces of the plurality of metal portions are each in direct contact with the light absorbing layer and the one or more semiconductor films.

US Pat. No. 11,031,511

CONTROL CIRCUIT AND METHOD OF OPERATING A CONTROL CIRCUIT

1. A circuit, comprising:an avalanche diode;
an active module configured to enable the avalanche diode and apply a first reverse bias voltage to the avalanche diode, the first reverse bias voltage being equal to or greater than a breakdown voltage of the avalanche diode, the active module including a first control signal generator configured to generate a first control signal and, a first switch configured to be controlled by the first control signal to connect and disconnect the avalanche diode to a first voltage input; and
a passive module configured to disable the avalanche diode and apply a second reverse bias voltage to the avalanche diode, the second reverse bias voltage being less than the breakdown voltage, the passive module including a clamp diode coupled to a second voltage input, the first switch, and the avalanche diode.

US Pat. No. 11,031,510

IMPACT IONIZATION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:disposing a gate electrode layer over a substrate;
disposing a dielectric layer over the gate electrode layer;
disposing and patterning a photo-resist layer over the dielectric layer to cover at least a middle portion of the dielectric layer;
forming a charge-trapping layer inside a portion of the dielectric layer not covered by the photo-resist layer;
disposing a two-dimensional (2D) material layer over the charge-trapping layer and a remaining portion of the dielectric layer after removing the patterned photo-resist layer; and
forming source and drain contacts over the 2D material layer,
wherein the charge-trapping layer comprises a first portion extending under the source contact in the dielectric layer that does not extend from under the source contact to under the drain contact and does not extend under the drain contact.

US Pat. No. 11,031,509

MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

MACRONIX INTERNATIONAL CO...

1. A memory device, comprising:a substrate comprising a first region and a second region, wherein the second region is adjacent to the first region;
a stack structure located in the first region and disposed on the substrate, wherein the stack structure comprises a gate dielectric layer and a floating gate, and the tunnel dielectric layer is located between the floating gate and the substrate;
an isolation structure located in the first region and disposed in the substrate and at two sides of the stack structure;
an inter-gate dielectric layer located in the first region and covering the stack structure and the isolation structure;
a control gate located in the first region and covering the inter-gate dielectric layer;
a first insulation structure located in the second region and disposed in the substrate, wherein a top surface of the first insulation structure is lower than a top surface of the substrate, and a side surface of a portion of the substrate is exposed;
a first gate dielectric layer located in the second region and disposed only on the top and the side surfaces of the substrate and terminating on the top surface of the first insulation structure; and
a first gate located in the second region and covering the first gate dielectric layer.

US Pat. No. 11,031,508

SEMICONDUCTOR DEVICE WITH TREATED INTERFACIAL LAYER ON SILICON GERMANIUM

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a source region and a drain region over a substrate;
a silicon germanium (SiGe) channel region laterally between the source region and the drain region;
an interfacial layer forming an interface with the SiGe channel region;
a high-k dielectric layer over the interfacial layer;
a gate electrode over the high-k dielectric layer; and
a high-k passivation layer between the interfacial layer and the high-k dielectric layer and having a high-k silicate, wherein a concentration of the high-k silicate in the high-k passivation layer decreases as a distance from the interfacial layer increases.

US Pat. No. 11,031,507

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

Comptek Solutions Oy, Tu...

1. A method of fabricating a semiconductor device comprising a plurality of layers, the method comprising:obtaining a substrate layer;
arranging at least one III-V compound semiconductor layer on the substrate layer;
arranging a first corresponding crystalline terminating oxide layer on the at least one III-V compound semiconductor layer;
arranging a first electrical insulating layer on the first corresponding crystalline terminating oxide layer;
cutting away, cleaving or etching the substrate layer;
arranging a second corresponding crystalline terminating oxide layer on the at least one III-V compound semiconductor layer; and
arranging a second electrical insulating layer on the second corresponding crystalline terminating oxide layer, wherein
arranging the corresponding crystalline terminating oxide layers is carried out by heating an external surface of the semiconductor layer in vacuum conditions with a chamber background pressure in range of 1×10?11 to 1×10?7 mBar and at a temperature of at least 200° C. and up to 550° C., by exposing the external surface to a dosage of oxygen atoms at the selected temperature by having an oxygen gas with partial pressure of less than 1×10?7 to 1×10?2 mBar in a vacuum chamber;
arranging the electrical insulating layers is carried out by atomic layer deposition;
and wherein a surface symmetry of the crystalline terminating oxide layers is
(2×3) or (1×1) when the III-V compound semiconductor layer is InP,
c(4×2) and (3×1) or (3×1) or (3×3) when the III-V compound semiconductor layer is InAs,
c(4×2), (4×3), (3×1) and (3×2) or (3×1) or (3×3) when the III-V compound semiconductor layer is InGaAs,
(3?3×3?3?R30°) when the III-V compound semiconductor layer is GaN,
(1×1) when the III-V compound semiconductor layer is AlGaN or InGaP,
(1×2) when the III-V compound semiconductor layer is InSb or InGaSb.

US Pat. No. 11,031,506

SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR USING OXIDE SEMICONDUCTOR

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first oxide;
a second oxide, a first layer, and a second layer over the first oxide;
an insulator over the second oxide;
a first conductor over the insulator;
a second conductor over the first layer; and
a third conductor over the second layer,
wherein each of the first layer and the second layer comprises a region with a thickness greater than or equal to 0.5 nm and less than or equal to 3 nm,
wherein each of the second conductor and the third conductor comprises a conductive material capable of extracting hydrogen,
wherein a part of the first layer is sandwiched between a first side surface of the second oxide and the second conductor, and
wherein a part of the second layer is sandwiched between a second side surface of the second oxide and the third conductor.

US Pat. No. 11,031,505

TRANSISTOR AND ITS MANUFACTURING PROCESS

X-FAB FRANCE, Corbeil Es...

1. A transistor carried by at least one substrate comprising at least one active layer based on at least one semiconductor material, the transistor comprising:a) at least one source area and at least one drain area;
b) at least one electrical contact area;
c) at least one conduction channel:
i) located between the source area and the drain area;
ii) extending from said source area to said drain area in a transverse dimension j1 and extending in a longitudinal dimension Jc;
d) at least one gate completely overlying said conduction channel, wherein said gate comprises:
(1) a longitudinal portion extending longitudinally from at least each of the source and drain areas, above the conduction channel, and at least to the electrical contact area;
(2) a transverse portion located between the electrical contact area and each of the source and drain areas and extending transversely on either side of a portion of the active layer on a transverse dimension I4, and the transverse portion comprising:
(a) at least a first portion extending transversely beyond a first side of said portion of the active layer on a first extension dimension I2, the first portion being shaped to be disposed between a portion of the electrical contact area and a first area taken from the source area or the drain area so as to avoid any electrical connection between the electrical contact area and said first area;
(b) at least a second portion extending transversely beyond a second side of said portion of the active layer, opposite said first side, on a second extension dimension I3;
and in that: I2>I3 with I3?0,
and in that the electrical contact area is located at a distance from the source area and the drain area so as to avoid any electrical connection between the electrical contact area and a second area being the other area taken among the source area or the drain area, the second area being which is disposed opposite the electrical contact area,
and wherein an insulating trench is interposed between the electrical contact area and said second area being the other area taken among the source area or the drain area, the insulating trench extending to the substrate.

US Pat. No. 11,031,504

GATE ALL AROUND VACUUM CHANNEL TRANSISTOR

STMICROELECTRONICS, INC.,...

1. A device, comprising:a substrate;
a first semiconductor pillar structure oriented in a first direction, the first semiconductor structure having a first tapered end pointing away from the substrate;
a second semiconductor pillar structure oriented in the first direction and spaced apart from the first semiconductor pillar structure, the second semiconductor structure having a second tapered end pointing toward the substrate;
a gap region between the first semiconductor pillar structure and the second semiconductor pillar structure; and
a gate structure adjacent to the gap region in a second direction transverse to the first direction.

US Pat. No. 11,031,503

NON-PLANAR GATE THIN FILM TRANSISTOR

Intel Corporation, Santa...

1. An integrated circuit, comprising:a plurality of layers formed on a substrate, the plurality of layers including a first conductor material layer comprising a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first conductor material layer, and a second conductor material layer formed on the ILD, the second conductor material layer comprising a second one of the source or drain;
a semiconductive layer formed on a sidewall of the plurality of layers, including on a sidewall of the first conductor material layer, a sidewall of the ILD, and a sidewall of the second conductor material layer;
a gate dielectric layer formed on the semiconductive layer; and
a gate formed in contact with the gate dielectric layer;
wherein the semiconductive layer fully wraps around a portion of the gate that is located in a hole, the semiconductive layer including a cylindrical interior surface and a cylindrical exterior surface, wherein the first conductor material layer, the second conductor material layer, and the gate are made of a same metal material.

US Pat. No. 11,031,502

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A semiconductor device, comprising:an active region extending in a first direction on a substrate;
a plurality of channel layers on the active region and spaced apart from each other vertically;
a gate structure intersecting the active region and the plurality of channel layers, the gate structure extending in a second direction on the substrate and surrounding the plurality of channel layers; and
a source/drain region on the active region at at least one side of the gate structure, the source/drain region being in contact with the plurality of channel layers, the source/drain region including:
first epitaxial layers having a first composition and including first layers on side surfaces of the plurality of channel layers taken in the first direction and a second layer on the active region at a lower end of the source/drain region; and
a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being interposed between the first epitaxial layers in the first direction and being interposed between the first epitaxial layers in a third direction, wherein the third direction is a vertical direction perpendicular to the first direction and the second direction.

US Pat. No. 11,031,501

ISOLATION STRUCTURE HAVING DIFFERENT DISTANCES TO ADJACENT FINFET DEVICES

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first fin structure that extends in a first direction in a top view;
a second fin structure that extends in the first direction in the top view;
a first gate structure disposed over the first fin structure in a cross-sectional side view, wherein the first gate structure extends in a second direction different from the first direction in the top view;
a second gate structure disposed over the second fin structure in the cross-sectional side view, wherein the second gate structure extends in the second direction in the top view; and
a dielectric structure disposed between the first gate structure and the second gate structure in the cross-sectional side view and the top view, wherein the dielectric structure at least partially contains air and extends in the first direction in the top view, and wherein the dielectric structure is disposed closer to the first fin structure than to the second fin structure in the cross-sectional side view and in the top view.

US Pat. No. 11,031,500

GATE RESISTANCE IMPROVEMENT AND METHOD THEREOF

Taiwan Semiconductor Manu...

1. A method, comprising:providing a substrate, the substrate comprising a gate structure with a work-function metal (WFM) layer and a barrier metal layer substantially level with the WFM layer;
removing a top portion of the WFM layer to form a lower portion of the WFM layer with a first top surface lower than a second top surface of the barrier metal layer;
forming a self-assembled monolayer (SAM) over the first top surface of the lower portion of the WFM layer; and
depositing a filler gate metal layer over the SAM.

US Pat. No. 11,031,499

GERMANIUM TRANSISTOR STRUCTURE WITH UNDERLAP TIP TO REDUCE GATE INDUCED BARRIER LOWERING/SHORT CHANNEL EFFECT WHILE MINIMIZING IMPACT ON DRIVE CURRENT

Intel Corporation, Santa...

1. An apparatus comprising:a transistor device comprising a channel material disposed above a substrate, the channel material having an upper portion comprising a channel between a source and a drain, and the channel material having a lower portion extending beneath the source and the drain, a gate stack disposed on the channel, the gate stack comprising a gate dielectric and a gate electrode, wherein the channel comprises a length dimension between the source and the drain that is greater than a length dimension of the gate electrode such that there is an underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain, wherein the underlap is passivated with a passivation layer, and wherein the passivation layer is not vertically beneath the gate electrode.

US Pat. No. 11,031,498

SEMICONDUCTOR STRUCTURE WITH IMPROVED SOURCE DRAIN EPITAXY

TAIWAN SEMICONDUCTOR MAN...

1. A semiconductor structure, comprising:a substrate;
first fins extending from the substrate, the first fins having a first fin pitch;
second fins extending from the substrate, the second fins having a second fin pitch that is smaller than the first fin pitch;
first gate structures over the substrate and engaging the first fins;
second gate structures over the substrate and engaging the second fins;
first epitaxial semiconductor features adjacent the first gate structures; and
second epitaxial semiconductor features adjacent the second gate structures,
wherein the first epitaxial semiconductor features are partially embedded in the first fins at a first depth, wherein the second epitaxial semiconductor features are partially embedded in the second fins at a second depth that is smaller than the first depth.

US Pat. No. 11,031,497

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Silergy Semiconductor Tec...

1. A semiconductor device, comprising:a) a high-voltage side device and a low-voltage side device;
b) a substrate having a first doping type and being shared by both the high-voltage side device located at a first side of the substrate, and the low-voltage side device located at a second side of the substrate;
c) a gate oxide layer located on the surface of the substrate and being shared by both the high-voltage side device and the low-voltage side device;
d) a first well region located in the substrate of the first side and having a second doping type, wherein the first doping type is opposite to the second doping type;
e) a buried layer having the second doping type and being located in the first side of the substrate, wherein the buried layer is in contact with the first well region to form a first region that is surrounded by the buried layer and the first well region; and
f) a source region and a drain region located in the first region, wherein the source region and the drain region have the second doping type.

US Pat. No. 11,031,496

MOSFET AND MANUFACTURING METHOD THEREOF

MOSEL VITELIC INC., Hsin...

1. A MOSFET, comprising:a substrate;
a trench formed on the substrate;
a bottom oxide formed on the trench;
a shield poly formed on the trench, wherein a part of the bottom oxide is separated by the shield poly;
two gate polys formed on the bottom oxide; and
an inter-poly oxide formed between the two gate polys,
wherein the shield poly the two gate polys have completely on overlap in a horizontal direction and a vertical direction.

US Pat. No. 11,031,495

APPARATUS AND METHOD FOR POWER MOS TRANSISTOR

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first region of a first conductivity;
a second region of the first conductivity above the first region;
a third region of a second conductivity above the second region;
a source region of the first conductivity in the third region;
a first dielectric layer in the second region, the second region extending along opposing sidewalls of the first dielectric layer;
a gate electrode above the first dielectric layer and in the second region;
a gate dielectric layer interposed between the gate electrode and the second region, wherein the gate dielectric layer is interposed between the gate electrode and the first dielectric layer;
a drain region of the first conductivity in the second region and on an opposite side of the gate electrode from the source region; and
a conductive element in the second region, wherein the conductive element is electrically coupled to the gate electrode.

US Pat. No. 11,031,494

SILICON CARBIDE SEMICONDUCTOR DEVICE HAVING A GATE ELECTRODE FORMED IN A TRENCH STRUCTURE

Infineon Technologies AG,...

1. A semiconductor device, comprising:a trench structure extending from a first surface into a semiconductor body composed of silicon carbide, the trench structure comprising an electrode and a gate electrode, the gate electrode being positioned between the electrode and the first surface;
a shielding region formed in the semiconductor body, the shielding region adjoining the electrode and forming a first pn junction with a drift structure; and
a Schottky contact formed between the drift structure and a first contact structure,
wherein the shielding region contacts the electrode at a bottom of the trench structure.

US Pat. No. 11,031,493

DOPING AND TRAP PROFILE ENGINEERING IN GAN BUFFER TO MAXIMIZE ALGAN/GAN HEMT EPI STACK BREAKDOWN VOLTAGE

1. A transistor with improved breakdown voltage, said transistor having an AlGaN barrier layer and a GaN buffer layer, wherein compensation C-doping is performed in said GaN buffer layer for controlling acceptor trap concentration in said GaN buffer layer, and thereafter an intentional n-type doping is performed in said GaN buffer layer for controlling donor trap concentration in said GaN buffer layer,wherein the intentional n-type doping comprises Si-doping, and wherein the Si-doping is optimized based on dynamic ON resistance.

US Pat. No. 11,031,492

SEMICONDUCTOR STRUCTURE COMPRISING III-N MATERIAL

Exagan, Grenoble (FR)

1. A semiconductor structure including III-N materials, comprising:a support substrate;
a main layer made of III-N material, the main layer having a first section disposed on the support substrate and a second section disposed over the first section;
an interlayer made of III-N material disposed between the first section and the second section for compressing the second section of the main layer, wherein the interlayer comprises:
a lower layer disposed on the first section of the main layer; and
an upper layer disposed on and in contact with the lower layer formed by a superlattice, wherein the lower layer consists essentially of a homogeneous layer or a superlattice which is different from the superlattice constituting the upper layer, having a dislocation density greater than that of the upper layer and a lattice parameter smaller than a lattice parameter of the material forming the upper layer, the superlattice constituting the upper layer and, where appropriate, the superlattice constituting the lower layer being formed by a repetition of a pattern comprising at least two layers of different types; and wherein each layer making up the pattern has a thickness of between 0.5 nm and 50 nm, the interlayer has a thickness of between 200 nm and 1000 nm, and the upper layer comprises a p-type dopant of carbon, iron or magnesium in a concentration of between 5×1018 and 5x1019 at/cm3 to make the layer resistive.

US Pat. No. 11,031,491

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a first semiconductor layer of a first conductivity type including first and second main surfaces;
a second semiconductor layer of a second conductivity type disposed on the first main surface of the first semiconductor layer;
a third semiconductor layer of the first conductivity type selectively disposed in a surface of the second semiconductor layer;
a first main electrode on a side of the first main surface disposed on the second semiconductor layer and the third semiconductor layer;
a first gate channel region formed in a region in the second semiconductor layer, between the first semiconductor layer and the third semiconductor layer;
a first control electrode isolated from the first gate channel region by a first gate insulating film;
a fourth semiconductor layer of the second conductivity type disposed in the second main surface of the first semiconductor layer;
a fifth semiconductor layer of the first conductivity type selectively disposed in a surface of the fourth semiconductor layer;
a second mam electrode on a side of the second main surface disposed on the fourth semiconductor layer and the fifth semiconductor layer;
a second gate channel region of the first conductivity type provided between the first semiconductor layer and the fifth semiconductor layer; and
a second control electrode isolated from the second gate channel region by a second gate insulating film.

US Pat. No. 11,031,490

FABRICATION OF FIELD EFFECT TRANSISTORS WITH FERROELECTRIC MATERIALS

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a semiconductor device, comprising:removing a dummy gate stack to form a first trench between gate spacers, wherein the first trench exposes a semiconductor layer;
forming a sacrificial layer along sidewalls of the gate spacers in the first trench, wherein the semiconductor layer is exposed in the first trench between portions of the sacrificial layer;
forming a first hafnium-containing gate dielectric layer along the semiconductor layer but not along the sacrificial layer in the first trench;
removing the sacrificial layer to form a second trench within the first trench, wherein a first sidewall of the second trench is defined by one of the gate spacers and a second sidewall of the second trench is defined by the first hafnium-containing gate dielectric layer;
forming a second hafnium-containing gate dielectric layer over the first hafnium-containing gate dielectric layer and along the sidewalls of the gate spacers to fill the second trench;
annealing the first and the second hafnium-containing gate dielectric layers, wherein the annealing includes simultaneously applying an electric field; and
forming a gate electrode over the annealed first and second hafnium-containing gate dielectric layers.

US Pat. No. 11,031,489

SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:an active fin disposed on a substrate;
a gate structure;
a pair of gate spacers disposed on sidewalls of the gate structure, wherein the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers; and
a hard mask layer disposed between the gate structure and the first portion of the active fin.

US Pat. No. 11,031,488

SEMICONDUCTOR DEVICE STRUCTURE WITH BARRIER LAYER AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device structure, comprising:a transistor over a substrate;
a dielectric structure over the substrate and covering the transistor; and
a contact structure passing through the dielectric structure and electrically connected to the transistor, wherein the contact structure comprises a contact layer, a first barrier layer, and a second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, a first lower portion of the first barrier layer is in direct contact with the dielectric structure, and a thickness of the first lower portion increases toward the substrate.

US Pat. No. 11,031,487

CONTACT OVER ACTIVE GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a fin comprising silicon, the fin having a top and sidewalls;
a gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin;
a gate electrode over the gate dielectric layer, over the top of the fin and laterally adjacent the sidewalls of the fin, the gate electrode having a first side and a second side opposite the first side, and having an insulating cap having a top surface;
a dielectric spacer adjacent the first side of the gate electrode;
a semiconductor source or drain region adjacent the dielectric spacer;
a trench contact structure over the semiconductor source or drain region adjacent the dielectric spacer, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating cap of the gate electrode, and the insulating cap of the trench contact structure extending laterally into a recess in the dielectric spacer and overhanging the conductive structure of the trench contact structure.

US Pat. No. 11,031,486

SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, the method comprising:depositing a first dielectric material in an opening over a substrate;
depositing a first conductive material over the first dielectric material, the first conductive material comprising a first metal;
depositing a second conductive material over the first conductive material, the second conductive material being different from the first conductive material;
depositing a blocking material over the second conductive material;
depositing a first nucleation layer over the blocking material;
depositing a second nucleation layer over the first nucleation layer, wherein the first nucleation layer has an oxygen concentration greater than zero but less than 0.1% atomic adjacent to a boundary between the first nucleation layer and the second nucleation layer; and
exposing the first nucleation layer to oxygen prior to depositing the second nucleation layer.

US Pat. No. 11,031,485

TRANSISTOR WITH AIRGAP SPACER

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a gate structure on a substrate;
forming a sacrificial region between the gate structure and a contact spacer;
recessing the gate structure and the contact spacer to enlarge the sacrificial region; and
depositing a dielectric material in the enlarged sacrificial region to form an airgap between a remaining portion of the contact spacer and the gate structure,
wherein forming the sacrificial region comprises:
forming a sacrificial layer against a gate spacer of the gate structure;
forming the contact spacer against a sidewall of the sacrificial layer; and
removing the sacrificial layer to define a void in the sacrificial region between the contact spacer and the gate spacer, and
wherein removing the sacrificial layer comprises:
forming a sacrificial base portion of the sacrificial layer on a base portion of the gate spacer;
forming the contact spacer on the sacrificial base portion;
removing the sacrificial base portion while preserving the contact spacer and the base portion of the gate spacer to form a divot between the contact spacer, the base portion and a remaining portion of the sacrificial layer;
filling the divot with a hardmask material to form a divot plug; and
etching away the sacrificial layer while preserving the contact spacer, the base portion and the divot plug to define the void.

US Pat. No. 11,031,484

SILICIDED GATE STRUCTURES

GLOBALFOUNDRIES U.S. INC....

1. A structure comprising:a substrate;
a gate structure comprising a silicided gate region; and
source and drain regions adjacent to the gate structure and comprising source/drain (S/D) silicided regions having a differential thickness compared to the silicided gate region, wherein the source and drain regions comprise an epitaxial stack which comprises a main layer directly on the substrate and a stop layer over the main layer.

US Pat. No. 11,031,483

FORMING SEMICONDUCTOR DEVICES IN SILICON CARBIDE

Infineon Technologies AG,...

1. A method, comprising:providing a first layer of silicon carbide supported by a silicon carbide substrate;
providing a second layer of epitaxial silicon carbide on the first layer;
forming a plurality of semiconductor devices in the second layer; and
separating the substrate from the second layer at the first layer,
wherein the first layer comprises a plurality of voids,
wherein providing the first layer comprises using an epitaxial growth process
wherein a trench-fill process is used to define the plurality of voids,
wherein the epitaxial growth process is a step-controlled epitaxial growth process which uses an off-orientation direction with respect to a crystallographic face of the substrate,
wherein trenches of the trench-fill process enclose an angle of at least 1° with the off-orientation direction.

US Pat. No. 11,031,482

GATE ELECTRODE HAVING A CAPPING LAYER

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a semiconductor layer comprising silicon, the semiconductor layer comprising silicon on an insulator structure;
a gate stack over the semiconductor layer comprising silicon, the gate stack comprising:
a higk-k gate dielectric layer, the high-k gate dielectric layer comprising hafnium and oxygen, and the high-k gate dielectric layer further comprising silicon distributed within the hafnium and oxygen, wherein the high-k gate dielectric layer is directly on the semiconductor layer comprising silicon;
a first layer on the high-k gate dielectric layer, the first layer comprising titanium and nitrogen; and
a second layer on the first layer, the second layer comprising silicon; and
a first source or drain region at a first side of the gate stack; and
a second source or drain region at a second side of the gate stack, the second side opposite the first side.

US Pat. No. 11,031,481

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

18. A semiconductor device, comprising:fin structures disposed over a substrate;
an isolation insulating layer, from which an upper portion of each of the fin structures protrude, and in which a lower portion of each of the fin structures is embedded;
a gate structure disposed over the upper portion of each of the fin structures; and
sidewall spacers disposed on opposing side surfaces of the gate structure, wherein:
each of the sidewall spacers includes a lower portion and an upper portion disposed on the lower layer, and
the lower portion includes an air gap.

US Pat. No. 11,031,480

SEMICONDUCTOR DEVICE, COMPRISING AN INSULATED GATE FIELD EFFECT TRANSISTOR CONNECTED IN SERIES WITH A FIELD EFFECT TRANSISTOR

K. EKLUND INNOVATION, Up...

1. A semiconductor device, comprising:a substrate of a first conductivity type that is a base for the semiconductor device;
an insulated gate field effect transistor (IGFET) over the substrate, the IGFET being isolated with deep poly trenches of the first conductivity type (DPPTs) on both sides thereof;
a high voltage field effect transistor (JFET) over the substrate and connected in series with the IGFET, the JFET comprising a plurality of parallel conductive layers, the JFET being isolated with a deep poly trench of a second conductivity type (DNPT) on a source side of the JFET in relation to the JFET source,
a first conductive layer of the second conductivity type of the parallel conductive layers stretches over the substrate,
on top of the first conductive layer of the second conductivity type are disposed a plurality of second conductive layers of the parallel conductive layers with channels formed by a plurality of doped epitaxial layers of the second conductivity type with a plurality of gate layers of the first conductivity type on both sides thereof, the plurality of second conductive layers and the channels being disposed on top of the first conductive layer; and
another isolated region comprising logics and analogue control functions isolated with deep poly trenches of the first conductivity type (DPPTs) on both sides thereof.

US Pat. No. 11,031,479

SEMICONDUCTOR DEVICE WITH DIFFERENT GATE TRENCHES

Infineon Technologies Aus...

1. A transistor device, comprising:a first trench and a second trench arranged in a comb-like structure, first sections of the first and second trenches corresponding to teeth of the comb-like structure and second sections of the first and second trenches corresponding to opposing shafts of the comb-like structure,
wherein the arrangement of the first trench and the second trench forms a pattern of interdigitated fingers,
wherein transistor cells of the transistor device are disposed between single fingers of the first and second trenches,
wherein a semiconductor mesa separates the first trench and the second trench from each other,
wherein a gate electrode in the first trench or a gate electrode in the second trench is electrically connected to a source potential instead of a gate potential to decrease a gate charge of the transistor device.

US Pat. No. 11,031,478

SEMICONDUCTOR DEVICE HAVING BODY CONTACTS WITH DIELECTRIC SPACERS AND CORRESPONDING METHODS OF MANUFACTURE

Infineon Technologies Aus...

1. A semiconductor device, comprising:a trench extending into a first main surface of a semiconductor substrate;
a gate electrode and a gate dielectric in the trench, the gate dielectric separating the gate electrode from the semiconductor substrate;
a source region having a first conductivity type formed in the semiconductor substrate at the first surface and adjacent the trench;
a body region having a second conductivity type opposite the first conductivity type and formed in the semiconductor substrate below the source region and adjacent the trench, the body region adjoining the source region;
a drift region having the first conductivity type formed in the semiconductor substrate below the body region and adjacent the trench, the drift region adjoining the body region;
a contact opening in the semiconductor substrate which extends into the body region;
an electrically insulative spacer on sidewalls of the semiconductor substrate formed by the contact opening;
an electrically conductive material in the contact opening and adjoining the electrically insulative spacer on the sidewalls of the semiconductor substrate formed by the contact opening; and
a body contact region of the second conductivity type formed on a section of the body region adjacent the contact opening,
wherein the source region adjoins a side surface of the body contact region of the second conductivity type facing the trench and extends onto a front surface of the body contact region of the second conductivity type,
wherein the body contact region is in ohmic contact with the electrically conductive material at the front surface of the body contact region,
wherein the semiconductor substrate is free of device channels along the sidewalls formed by the contact opening.

US Pat. No. 11,031,477

METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE

UNITED MICROELECTRONICS C...

1. A method for fabricating a semiconductor device, comprising:providing a substrate;
forming a first dummy gate and a second dummy gate on the substrate with a gap between the first and second dummy gates, wherein the first dummy gate has a first sidewall, and the second dummy gate has a second sidewall directly facing the first sidewall, and wherein a first sidewall spacer is disposed on the first sidewall, and a second sidewall spacer is disposed on the second sidewall;
depositing a contact etch stop layer on the first and second dummy gates and on the first and second sidewall spacers;
subjecting the contact etch stop layer to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer; and
depositing an inter-layer dielectric layer on the contact etch stop layer and into the gap.

US Pat. No. 11,031,476

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

XIA TAI XIN SEMICONDUCTOR...

1. A method for fabricating a semiconductor device, the method comprising:recessing at least one trench inward from a surface of a semiconductor substrate;
forming a silicon oxide layer on an inner wall of the at least one trench;
forming a titanium nitride layer on the surface of the semiconductor substrate and the silicon oxide layer;
forming a spin-on hard mask on the titanium nitride layer, wherein the spin-on hard mask comprises a first portion above the surface of the semiconductor substrate and a second portion filled in the at least one trench;
performing an etch back process to remove the first portion and a part of the second portion to expose a portion of the titanium nitride layer;
removing the exposed titanium nitride layer, wherein a remaining portion of the titanium nitride layer is encircled by a remaining part of the second portion and the silicon oxide layer;
performing an ashing process to remove the remaining part of the second portion to expose the remaining portion of titanium nitride layer;
filling a metal layer in the at least one trench to a first predefined height by a selective deposition process, wherein the metal layer is surrounded by the remaining portion of the titanium nitride layer; and
filling a first silicon nitride layer in the at least one trench to a second predefined height,
wherein the first silicon nitride layer contacts the metal layer and is surrounded by the silicon oxide layer, and the metal layer includes a material selected from ruthenium and cobalt.

US Pat. No. 11,031,475

SELF-STANDING GAN SUBSTRATE, GAN CRYSTAL, METHOD FOR PRODUCING GAN SINGLE CRYSTAL, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Mitsubishi Chemical Corpo...

1. A self-standing GaN substrate with an angle between the normal of the principal surface and an in-axis of 0 degrees or more and 20 degrees or less,wherein:
the size of the projected image in a c-axis direction when the principal surface is vertically projected on an M-plane is 10 mm or more; and
when a region excluding a portion at a distance of 2 mm or less from a substrate end surface, of the principal surface, is assumed to be an effective region, a stacking fault density obtained by dividing a total length of stacking faults existing in the effective region by an area of the effective region is less than 15 cm?1.

US Pat. No. 11,031,474

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a substrate;
a first semiconductor layer provided above the substrate, the first semiconductor layer including a first region;
a second semiconductor layer provided away from the first semiconductor layer in a first direction, the second semiconductor layer including a second region;
a third region provided between the first region and the second region;
an electrode provided above the third region;
a fourth region provided between the first region and the third region, the fourth region including carbon;
a fifth region provided between the second region and the third region, the fifth region including carbon;
a sixth region including boron and provided between the third region and the fourth region;
a seventh region including phosphorus and provided between the third region and the fourth region; and
an insulating film provided on a side surface of the electrode;
wherein
a carbon concentration in the first region and a carbon concentration in the second region are lower than a carbon concentration in the fourth region and a carbon concentration in the fifth region, and
at least one of the first semiconductor layer or the second semiconductor layer is provided with a part that is in contact with a side surface in the first direction of the insulating film.

US Pat. No. 11,031,473

SILICON CARBIDE SUPERJUNCTION POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ABB POWER GRIDS SWITZERLA...

1. A superjunction power semiconductor device comprising:a semiconductor wafer having a first main side surface and a second main side surface, the semiconductor wafer including:
a first semiconductor layer having a first conductivity type;
a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface, the first semiconductor regions having a second conductivity type, which is different from the first conductivity type, wherein the first semiconductor layer is a layer of hexagonal silicon carbide, and wherein the first semiconductor regions are regions of 3C polytype cubic silicon carbide; and
a second semiconductor region of hexagonal silicon carbide separating the first semiconductor layer from the first semiconductor regions, wherein the second semiconductor region is of the second conductivity type.

US Pat. No. 11,031,472

SYSTEMS AND METHODS FOR INTEGRATED DIODE FIELD-EFFECT TRANSISTOR SEMICONDUCTOR DEVICES

GENERAL ELECTRIC COMPANY,...

1. A silicon carbide (SiC) semiconductor device comprising:a charge balance (CB) layer defined in a first epitaxial (epi) layer having a first conductivity type, wherein the CB layer includes a plurality of CB regions having a second conductivity type;
a device epi layer having the first conductivity type disposed on the CB layer, wherein the device epi layer comprises a plurality of regions having the second conductivity type;
an ohmic contact disposed directly on the device epi layer, wherein a field-effect transistor (FET) of the SiC semiconductor device comprises the ohmic contact; and
a rectifying contact disposed directly on the device epi layer, wherein a diode of the SiC semiconductor device comprises the rectifying contact, wherein the diode and the FET are integrated in parallel in the SiC semiconductor device.

US Pat. No. 11,031,471

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate;
a first conductivity-type drift region formed in the semiconductor substrate;
a second conductivity-type base region formed between an upper surface of the semiconductor substrate and the drift region in the semiconductor substrate;
and
a dummy trench portion formed to penetrate the base region from the upper surface of the semiconductor substrate in the semiconductor substrate;
wherein the dummy trench portion includes a dummy conductive portion and an insulating film between an inner wall of the dummy trench portion and the dummy conductive portion, the insulating film including:
a trench thin-film portion of a predetermined film thickness, and
a trench thick-film portion of a greater thickness than the predetermined film thickness.

US Pat. No. 11,031,470

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate;
a channel structure protruding above the substrate, wherein the channel structure comprises alternately stacked first portions and second portions having widths greater than widths of the first portions, and the first portions and the second portions are made of the same semiconductor material, wherein the channel structure has a bottommost end lower than a topmost surface of the substrate; and
a metal gate structure wrapping around the channel structure.

US Pat. No. 11,031,469

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING THE SAME

INSTITUTE OF MICROELECTRO...

1. A semiconductor device, comprising:a substrate;
a first source/drain region, a channel region and a second source/drain region stacked on the substrate in sequence and contiguous to each other, and a gate stack formed surrounding a periphery of the channel region;
wherein spacers are respectively provided between the gate stack and the first source/drain region and between the gate stack and the second source/drain region in a form of surrounding the periphery of the channel region, and outer surfaces of the spacers are substantially coplanar with outer surfaces of the first source/drain region and/or the second source/drain region.

US Pat. No. 11,031,468

GERMANIUM NITRIDE LAYERS ON SEMICONDUCTOR STRUCTURES, AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A device comprising:a semiconductor substrate;
a germanium nanowire on the semiconductor substrate, the germanium nanowire comprising a channel; and
a germanium nitride layer surrounding a circumference of the channel, the germanium nitride layer having a thickness that is more than a monolayer.

US Pat. No. 11,031,467

FIELD EFFECT TRANSISTOR BASED ON VERTICALLY INTEGRATED GATE-ALL-ROUND MULTIPLE NANOWIRE CHANNELS

Korea Advanced Institute ...

1. A method of manufacturing a transistor based on vertically integrated gate-all-around multiple nanowire channels, the method comprising:forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated;
forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels;
forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels are exposed; and
forming a gate dielectric layer on the interlayer dielectric layer to fill the hole,
wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole comprises:
depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels that are exposed though the hole
wherein a source, a drain, and a channel region of the transistor are doped with same type of dopant.

US Pat. No. 11,031,466

METHOD OF FORMING OXYGEN INSERTED SI-LAYERS IN POWER SEMICONDUCTOR DEVICES

Infineon Technologies Aus...

1. A method of manufacturing a semiconductor device, the method comprising:forming one or more device epitaxial layers over a main surface of a doped Si base substrate;
forming a diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers; and
forming a gate above the diffusion barrier structure.

US Pat. No. 11,031,465

SEMICONDUCTOR DEVICE INCORPORATING EPITAXIAL LAYER FIELD STOP ZONE

Alpha and Omega Semicondu...

1. An insulated gate bipolar transistor (IGBT), comprising:a heavily doped semiconductor layer;
an epitaxial layer of a first conductivity type formed on the semiconductor layer, the epitaxial layer including a first portion of the first conductivity type adjacent to the semiconductor layer forming a field stop zone, and the epitaxial layer further including a second portion of the first conductivity type forming a base region, the field stop zone having a first side adjacent to the semiconductor layer and a second side adjacent to the base region, the base region having a first side adjacent to the field stop zone and a second side opposite the first side, the field stop zone and the base region being formed using a same dopant of the first conductivity type and with different doping concentrations;
a device region formed in the second side of the base region, the device region comprising a PN junction; and
a gate dielectric layer and a conductive gate formed in or on the epitaxial layer at the second side of the base region,
wherein the epitaxial layer is formed to have a doping profile of the first conductivity type having a first doping level as a background doping level and having multiple flat top regions with step increase in doping levels from the first doping level, the multiple flat top regions being spaced apart within the field stop zone, wherein the multiple flat top regions include a first flat top region near the first side of the field stop zone and a last flat top region near the second side of the field stop zone, and the thickness of each of the multiple flat top regions increases from the first flat top region to the last flat top region.

US Pat. No. 11,031,464

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a semiconductor substrate of a first conductivity type, having a front surface and a rear surface opposite to the front surface;
a first semiconductor layer of the first conductivity type, provided on the front surface of the semiconductor substrate, the first semiconductor layer having an impurity concentration lower than an impurity concentration of the semiconductor substrate, and having a first side and a second side opposite to the first side and facing toward the front surface of the semiconductor substrate;
a first base region of a second conductivity type, selectively provided in a surface layer at the first side of the first semiconductor layer;
second base regions of the second conductivity type, each selectively provided within the first semiconductor layer;
a second semiconductor layer of the second conductivity type, provided on the first semiconductor layer at the first side thereof;
a first semiconductor region of the first conductivity type, selectively provided in a surface layer of the second semiconductor layer;
a plurality of trenches each penetrating the first semiconductor region and the second semiconductor layer, and reaching the first semiconductor layer;
a plurality of gate electrodes, each gate electrodes being provided in a corresponding one of the trenches, via a gate insulating film;
an interlayer insulating film provided on each of the gate electrodes;
a first electrode in contact with the second semiconductor layer and the first semiconductor region; and
a second electrode provided at a rear surface opposite to the front surface of the semiconductor substrate, wherein
the first base region is provided between adjacent two of the trenches, and each of the second base regions is provided at a bottom of a corresponding one of the trenches,
the first base region includes a lower region having a thickness equal to a thickness of one of the second base regions, and an upper region provided on the lower region, the lower region being disposed closer to the front surface of the semiconductor substrate than is the upper region, in a thickness direction and
the first base region has a plurality of peaks of impurity concentration that are local maximum values in the thickness direction, and among the plurality of peaks, a peak that is nearest an interface between the upper region and the lower region is located at a position furthest from any other peak among the plurality of peaks in the thickness direction.

US Pat. No. 11,031,463

SILICON CARBIDE SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A silicon carbide semiconductor device, comprising:a first load electrode;
a normally-on junction field effect transistor comprising a channel region electrically connected to the first load electrode; and
an insulated gate field effect transistor electrically connected in series with the normally-on junction field effect transistor, the insulated gate field effect transistor comprising a source region and a body region, the source region being electrically connected to the channel region of the normally-on junction field effect transistor, the body region being electrically connected to the first load electrode.

US Pat. No. 11,031,462

SEMICONDUCTOR STRUCTURE WITH IMPROVED GUARD RING STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure, comprising:a semiconductor wafer having a topside and a backside, wherein the semiconductor wafer comprising:
a first semiconductor well of a first conductive type;
a second semiconductor well of a second conductive type different from the first conductive type, wherein the first semiconductor well is disposed within the second semiconductor well and exposed to the topside;
a semiconductor device formed within the first semiconductor well;
a plurality of first semiconductor doped regions of the first conductive type, wherein the first semiconductor doped regions are disposed within the first semiconductor well to surround the semiconductor device;
a plurality of first through silicon vias (TSVs), wherein each first TSV extends into a corresponding one of the first semiconductor doped regions from the backside through the first and second semiconductor wells and is filled with a conductive material, and each first TSV is connected to a DC voltage or a ground potential from the backside; and
a plurality of conductive bumps, wherein each conductive bump is disposed on the backside and connected to a corresponding one of the first TSVs, and each conductive bump is connected to a DC voltage or a ground potential.

US Pat. No. 11,031,461

MANUFACTURE OF ROBUST, HIGH-PERFORMANCE DEVICES

GeneSiC Semiconductor Inc...

1. A device comprising: the device comprising SiC (Silicon Carbide), the device comprising a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) channel, a junction gate field-effect transistor region, a first conductivity type well region or a second conductivity type well region, and a first conductivity type shield region or a second conductivity type shield region, wherein the first conductivity type shield region or the second conductivity type shield region is outside the junction gate field-effect transistor region, and wherein a doping concentration in the first conductivity type well region or the second conductivity type well region within the MOSFET channel is non-uniform.

US Pat. No. 11,031,460

INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. An integrated circuit device comprising:a substrate;
a conductive region on the substrate;
a lower electrode structure on the conductive region, the lower electrode structure including a main electrode part and a bridge electrode part, the main electrode part including an outer sidewall and a lower surface;
a dielectric layer contacting the outer sidewall of the main electrode part and contacting the bridge electrode part; and
an upper electrode above the lower electrode structure,
wherein the main electrode part is spaced apart from the conductive region and includes a first metal,
the bridge electrode part contacts the conductive region at a surface recessed from a top surface of the conductive region, contacts the lower surface of the main electrode part, and includes a second metal different from the first metal, and
the dielectric layer is between the upper electrode and the lower electrode structure.

US Pat. No. 11,031,459

SEMICONDUCTOR DEVICE INCLUDING A CAPACITOR AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a semiconductor substrate;
a wiring layer provided on or above the semiconductor substrate, the wiring layer having a first metal layer and a second metal layer in contact with a lower face and a side face of the first metal layer;
a capacitor lower electrode provided on or above the semiconductor substrate, the capacitor lower electrode being the same material as the second metal layer;
a capacitor insulating film provided on the capacitor lower electrode; and
a capacitor upper electrode provided on the capacitor insulating film,
wherein a distance from the semiconductor substrate to an upper face of the capacitor lower electrode is equal to or less than a distance from the semiconductor substrate to an upper face of the wiring layer, and
a distance from the semiconductor substrate to a lower face of the capacitor lower electrode is greater than a distance from the semiconductor substrate to a lower face of the wiring layer.

US Pat. No. 11,031,458

METAL-INSULATOR-METAL (MIM) CAPACITOR STRUCTURE AND METHOD FOR FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A metal-insulator-metal (MIM) capacitor structure, comprising:a substrate, wherein the substrate comprises a capacitor region and a non-capacitor region;
a first electrode layer formed over the substrate;
a first spacer formed on a sidewall of the first electrode layer;
a first dielectric layer formed on the first spacers, wherein the first dielectric layer has a top portion and a bottom portion lower than the top portion, the top portion is in direct contact with a top surface of the first electrode layer, and the bottom portion is in direct contact with an outer sidewall of the first spacer;
a second electrode layer formed on the first dielectric layer, wherein the second electrode layer extends from the capacitor region to the non-capacitor region, and the second electrode layer extends beyond the outer sidewall of the first spacer; and
a second spacer and a third spacer formed on opposite sidewalls of the second electrode layer, wherein a top surface of the second spacer is higher than a top surface of the third spacer.

US Pat. No. 11,031,457

LOW RESISTANCE HIGH CAPACITANCE DENSITY MIM CAPACITOR

INTERNATIONAL BUSINESS MA...

9. A semiconductor device comprising:one or more bottom plate contacts including a barrier metal liner with a high electrical conductivity formed over a substrate;
a bottom capacitor plate formed directly on a top surface and a sidewall of each of the one or more bottom plate contacts, wherein a sidewall of the bottom capacitor plate is in direct contact with an entirety of a sidewall of one bottom plate contact of the one or more bottom plate contacts;
a capacitor dielectric layer formed directly on a surface of the bottom capacitor plate, a first portion of the capacitor dielectric layer extending in a direction parallel to the substrate and remaining above a highest portion of the one or more bottom plate contacts forming an offset region;
a top capacitor plate formed directly on a surface of the capacitor dielectric layer, a first portion of the top capacitor plate extending above the offset region; and
a top plate contact formed directly on the first portion of the top capacitor plate so as not to overlay a portion of the bottom capacitor plate in the offset region, wherein the one bottom plate contact of the one or more bottom plate contacts has a top surface in direct contract with the bottom capacitor plate and a bottom surface in direct contact with the substrate, the one bottom plate contact having an entirely of another sidewall in direct contact with dielectric material, the another sidewall and the sidewall of the one bottom plate contact being opposite one another.

US Pat. No. 11,031,456

ROLLED-UP ELECTROMAGNETIC COMPONENT FOR ON-CHIP APPLICATIONS AND METHOD OF MAKING A ROLLED-UP ELECTROMAGNETIC COMPONENT

The Board of Trustees of ...

1. A rolled-up electromagnetic component for on-chip applications, the rolled-up electromagnetic component comprising:a multilayer sheet in a rolled configuration comprising at least one turn about a longitudinal axis, the multilayer sheet comprising a conductive pattern layer on a strain-relieved layer;
a core defined by a first turn of the rolled configuration; and
a soft magnetic material disposed within the core,
wherein a magnetic layer comprising the soft magnetic material is disposed on the conductive pattern layer.

US Pat. No. 11,031,455

OLED TILED DISPLAY AND A RELATED TILING METHOD

WUHAN CHINA STAR OPTOELEC...

1. An organic light emitting diode (OLED) tiled display, comprising a front lighting display unit and a back lighting display unit that emit lights toward each other; whereinthe front lighting display unit comprises a first substrate and a first organic light emitting device;
the back lighting display unit comprises a second substrate and a second organic light emitting device;
the first substrate comprises a first main section whose front side has the first light emitting device configured and a first extended section laterally extended from the main section;
the second substrate comprises a second main section whose back side has the second organic light emitting device configured and a second extended section laterally extended from the second main section;
the first and second organic light emitting devices laterally neighbor on each other;
the first organic light emitting device is vertically aligned with the second extended section of the second substrate; and
the second organic light emitting device is vertically aligned with the first extended section of the first substrate;
wherein both the first and second organic light emitting devices have wiring sections at their lateral sides; the wiring sections are perpendicular to the first substrate; and the wiring section of the first organic light emitting device has a projection towards the second organic light emitting device at least partially overlapped with the wiring section of the second organic light emitting device.

US Pat. No. 11,031,454

ELECTRONIC COMPONENT, ELECTRIC DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. An electronic device comprising:a display panel including a base substrate, a plurality of pixels disposed on the base substrate, a first insulation layer disposed on the base substrate, and a plurality of panel pads, at least a portion of the plurality of panel pads being partially exposed by the first insulation layer, the plurality of panel pads being spaced apart in a first direction from the pixels, and each of the plurality of panel pads being arranged along a second direction crossing the first direction;
a circuit board including a flexible substrate and a plurality of output pads which are disposed on the flexible substrate and connected to the plurality of panel pads; and
a first pad spaced apart in the second direction from the plurality of output pads in a plan view, and electrically insulated from the plurality of panel pads,
wherein the first pad comprises a same material as the output pads.

US Pat. No. 11,031,453

FLEXIBLE DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus, comprising:a panel including a display area that displays images and a fan-out portion in which a plurality of wirings connected to the display area are located; and
a driving chip connected to the fan-out portion and connected to the display area via the plurality of wirings, wherein:
the plurality of wirings arranged in the fan-out portion include first wirings at a first layer on the panel and second wirings at a second layer that is different from the first layer,
the first wirings and the second wirings are in an overlapping relationship above and below each other, and
the first wirings and the second wirings are electrically separate from each other.

US Pat. No. 11,031,452

DISPLAY PANEL

Samsung Display Co., Ltd....

1. A display panel comprising:a first substrate having a display area and a peripheral area outside the display area;
a plurality of pixels at the display area;
a plurality of first output wires and a plurality of second output wires connected to the plurality of pixels, at least one pixel of the plurality of pixels being connected to one of the first output wires and connected to one of the second output wires;
a first driver at a first peripheral area of the peripheral area at a first side of the display area, the first driver being connected to the plurality of first output wires and not connected to the plurality of second output wires; and
a second driver at a second side opposing the first side with respect to the display area in the peripheral area, the second driver being spaced apart from the first driver along a first direction,
wherein the second driver has a first sub-driver connected to the plurality of first output wires and a second sub-driver connected to the plurality of second output wires,
wherein the first substrate comprises a notch portion having a curved edge,
wherein the display area comprises a first display portion and a second display portion that are spaced apart from each other with the notch portion interposed between the first display portion and the second display portion, and
wherein at least one of the plurality of first output wires comprises:
a first main line at the first display portion;
a second main line at the second display portion; and
a first connecting line that is connected to the first main line and the second main line and is at the peripheral area between the first display portion and the second display portion.

US Pat. No. 11,031,451

ORGANIC EL DISPLAY DEVICE

Japan Display Inc., Mina...

1. An organic EL display device, comprising:a substrate;
a plurality of pixels disposed on the substrate,
a first inorganic insulating layer that covers the plurality of pixels;
a conductive layer that is disposed on a side of the first inorganic insulating layer opposite to the plurality of pixels and covers the plurality of pixels; and
a second inorganic insulating layer that is disposed on a side of the conductive layer opposite to the first inorganic insulating layer and covers the plurality of pixels, wherein
a display area including the plurality of pixels is positioned on the substrate,
the first inorganic insulating layer, the conductive layer, and the second inorganic insulating layer cover the display area,
a part of the first inorganic insulating layer is positioned on outside of the display area,
a part of the second inorganic insulating layer is positioned on the outside, and
an edge of the first inorganic insulating layer overlaps an edge of the second inorganic insulating layer in a plan view on the outside.

US Pat. No. 11,031,450

LIGHT EMITTING DISPLAY APPARATUS FOR IMPROVING LIGHT EXTRACTION EFFICIENCY

LG DISPLAY CO., LTD., Se...

1. A light emitting display apparatus, comprising:a substrate including a first area and a second area;
an insulating layer on the substrate and having an uneven surface;
a first bank on the insulating layer in the second area, and formed of a black material;
a first electrode on the insulating layer in the first area, the first electrode covering at least a part of a side surface of the first bank and including a reflective layer and a transparent conductive layer on the reflective laver;
a light emitting layer on the first electrode;
a second electrode on the light emitting layer; and
a planarization layer between the reflective layer and the transparent conductive layer,
wherein the reflective layer is disposed along the uneven surface of the insulating layer.

US Pat. No. 11,031,449

LIGHT-EMITTING DEVICE HAVING FLUORESCENT AND PHOSPHORESCENT MATERIALS

Semiconductor Energy Labo...

1. A light-emitting device comprising:a substrate having light-transmitting property with respect to visible light;
a first insulating layer over the substrate;
a second insulating layer over the first insulating layer;
a third insulating layer over the second insulating layer;
a light-emitting element over the substrate; and
a metal substrate over the light-emitting element,
wherein the light-emitting element comprises a first light-emitting layer and a second light-emitting layer over the first light-emitting layer,
wherein the first light-emitting layer comprises a fluorescent material,
wherein the second light-emitting layer comprises a phosphorescent material,
wherein oxygen content in the first insulating layer is larger than nitrogen content in the first insulating layer,
wherein nitrogen content in the second insulating layer is larger than oxygen content in the second insulating layer, and
wherein oxygen content in the third insulating layer is larger than nitrogen content in the third insulating layer.

US Pat. No. 11,031,448

ORGANIC LIGHT EMITTING DIODE (OLED) DISPLAY PANEL AND THE MANUFACTURING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. An organic light emitting diode (OLED) display panel, comprising:a thin film transistor (TFT) array substrate;
a flat layer arranged on the TFT array substrate, the flat layer comprising a first flat layer and a second flat layer, the second flat layer being arranged on the first flat layer, and a viscosity of the first flat layer being less than a viscosity of the second flat layer; and
an OLED display layer arranged on the flat layer,
wherein the second flat layer is made of a material that is denser than the first flat layer and the denser material of the second flat layer is disposed atop the first flat layer for blocking upward migration of gaseous impurities from the first flat layer into the OLED display layer.

US Pat. No. 11,031,447

FLEXIBLE DISPLAY

LG DISPLAY CO., LTD., Se...

1. A flexible display comprising:a flexible substrate;
a thin film transistor array positioned on the flexible substrate, and the thin film transistor array including a thin film transistor, an organic light emitting diode, inorganic layers, and organic layers; and
an encapsulation layer positioned on the thin film transistor array,
wherein at least one of the inorganic layers is extended to be exposed at an outermost end of the flexible substrate,
wherein the organic layers include a bank layer surrounding the organic light emitting diode,
wherein the bank layer is positioned on the at least one of the inorganic layers and is extended to be exposed at the outermost end of the flexible substrate,
wherein the encapsulation layer is positioned at a predetermined distance inwardly from the outermost end of the flexible substrate,
wherein the bank layer is positioned as an uppermost layer at the outermost end of the flexible substrate, and
wherein a total height of the organic layers and the inorganic layers located at the display area is greater than a total height of the organic layers and the inorganic layers positioned at the outermost end of the flexible substrate located at the non-display area.

US Pat. No. 11,031,446

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. An electronic device comprising:a substrate; and
a pad area on the substrate,
wherein the pad area comprises:
a first pad part comprising a first pad terminal;
a second pad part on a side of the first pad part in a first direction and comprising a second pad terminal; and
a third pad part on another side of the first pad part in the first direction and comprising a third pad terminal,
wherein each of the first pad terminal, the second pad terminal and the third pad terminal comprises a first long side, a second long side facing the first long side, and at least one bridge extending from the first long side to the second long side,
wherein the first long side of the first pad terminal extends in a second direction intersecting the first direction, an angle formed by the first long side of the second pad terminal and the second direction and an angle formed by the first long side of the third pad terminal and the second direction have different mathematical signs such that the first long side of the second pad terminal angles away from the second direction in a third direction different from a fourth direction in which the first long side of the third pad terminal angles away from the second direction, and
wherein a first angle formed by an extending direction of the bridge of the first pad terminal and the first direction is greater than a second angle formed by the extending direction of the bridge of the second pad terminal and the first direction and a third angle formed by the extending direction of the bridge of the third pad terminal and the first direction.

US Pat. No. 11,031,445

ARRAY SUBSTRATE AND DISPLAY DEVICE WITH BACKSIDE CAMERA

WUHAN CHINA STAR OPTOELEC...

1. An array substrate, comprising a base substrate, a thin film transistor layer, a planarization layer, and a pixel definition layer prepared on the base substrate in turn, the pixel definition layer being used to define pixel opening areas;the base substrate disposing a camera area in a display area, and the camera area including a first blind hole and a wiring area around the first blind hole;
the first blind hole being used to expose a camera disposed on a back of the base substrate, and the wiring area disposing signal lines and second blind holes;
wherein, the second blind holes are arranged to avoid the signal lines for increasing a light transmittance of the wiring area.

US Pat. No. 11,031,444

DISPLAY PANEL COMPRISING A CONTAINER PORTION EXTENDS ALONG A LENGTH OF A ROW OF SUBPIXEL REGIONS HAVING GROOVES CONNECT TO SUBPIXEL REGIONS OF A SAME COLOR AND A METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

11. The display panel of claim 1, wherein each of the one or more gaps comprises a width substantially equal to a width of each subpixel region along a direction of rows of subpixel regions.

US Pat. No. 11,031,443

ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY DEVICE INCLUDING SENSOR DISPOSED IN GROOVE OF BASE SUBSTRATE

WUHAN CHINA STAR OPTOELEC...

1. An organic light-emitting diode (OLED) display device, comprising a display panel and an image capturing assembly disposed in the display panel, whereinthe display panel comprises a base substrate and a display layer disposed on the base substrate;
the display layer comprises a thin film transistor (TFT) layer disposed on the base substrate and an OLED functional layer disposed on the TFT layer;
the display panel is divided into a display area, an image capturing area located in the display area, and a peripheral area located outside the display area;
the image capturing assembly comprises a sensor, a signal module electrically connected to the sensor and disposed on a side of an upper end of the sensor, and a lens disposed above the sensor;
a groove configured to accommodate the sensor is disposed at a surface of the base substrate close to the display layer and corresponding to the image capturing area;
the sensor is disposed in the groove of the base substrate, and a height of the sensor is greater than a depth of the groove, and the upper end of the sensor and the signal module are located in the TFT layer;
an opening corresponding to the image capturing area is provided through the display layer configured to receive the lens;
the lens is disposed in the opening; and
the TFT layer comprises a first metal layer and a plurality of inorganic layers, and an image capturing signal transmission line electrically connected to the signal module is disposed in the first metal layer.

US Pat. No. 11,031,442

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device comprising:a display panel divided into a light emitting unit, in which an organic light emitting diode is disposed, and a light transmitting unit which selectively transmits light; and
a driving circuit configured to drive the display panel,
wherein the display panel comprises:
a first substrate where the organic light emitting diode is disposed in the light emitting unit and a first electrode is disposed in the light transmitting unit;
a second substrate facing the first substrate and where a second electrode is disposed in the light transmitting unit;
a liquid crystal layer interposed between the first electrode and the second electrode, and
adjusting a transmittance of the liquid crystal layer according to a difference between a voltage applied to the first electrode and a voltage applied to the second electrode;
a low-potential voltage line disposed on the first substrate;
at least one insulating layer disposed on the low-potential voltage line; and
an auxiliary electrode disposed on the at least one insulating layer contacting the low-potential voltage line through an auxiliary connector passing through the at least one insulating layer,
wherein the auxiliary electrode is in contact with the first electrode and a cathode of the organic light emitting diode.

US Pat. No. 11,031,441

ELECTRO-OPTICAL DEVICE, MANUFACTURING METHOD OF ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS

SEIKO EPSON CORPORATION, ...

1. An electro-optical device comprising:a first substrate;
a second substrate;
a color filter disposed in a layer between the first substrate and the second substrate;
an adhesive disposed in a layer between the color filter and the second substrate;
a first overcoat layer disposed in a layer between the adhesive and the color filter; and
a second overcoat layer that is disposed in the layer between the adhesive and the color filter and that is disposed along the first overcoat layer.

US Pat. No. 11,031,440

LIGHT CONVERSION SUBSTRATE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A light conversion substrate comprising:a first substrate which comprises a first region, a second region, and a third region;
a first light conversion pattern disposed on the first region and including first wavelength conversion particles;
a first color filter disposed between the first substrate and the first light conversion pattern, the first color filter overlapping the first light conversion pattern and including a first colorant;
a second light conversion pattern disposed on the second region and is spaced apart from the first light conversion pattern, the second light conversion pattern including second wavelength conversion particles;
a second color filter disposed between the first substrate and the second light conversion pattern, the second color filter overlapping the second light conversion pattern and including a second colorant which is different from the first colorant; and
a first scattering pattern disposed on the third region and is configured to fill a space between the first light conversion pattern and the second light conversion pattern, the first scattering pattern including first scattering particles,
wherein the first scattering pattern overlaps a portion of the first light conversion pattern and a portion of the second light conversion pattern in a direction of a thickness of the first substrate,
wherein the first light conversion pattern and the second light conversion pattern comprise the same scattering particles as the first scattering pattern, and
wherein the first scattering pattern overlaps the first color filter and the second color filter.

US Pat. No. 11,031,439

LIGHT-EMITTING DEVICE AND DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a transistor having a single crystal semiconductor layer:
a first light-emitting element comprising:
a first electrode that is reflective;
a first conductive layer over the first electrode;
a first light-emitting layer over the first conductive layer;
a second light-emitting layer over the first light-emitting layer; and
a second electrode over the second light-emitting layer;
a second light-emitting element comprising:
a third electrode that is reflective;
a second conductive layer over the third electrode;
the first light-emitting layer over the second conductive layer;
the second light-emitting layer over the first light-emitting layer; and
the second electrode over the second light-emitting layer;
a first color filter overlapping with the first light-emitting element and having a first central wavelength of a first wavelength range in which the first color filter has a transmittance of 50% or higher in a visible wavelength range;
a second color filter overlapping with the second light-emitting element and having a second central wavelength of a second wavelength range in which the second color filter has a transmittance of 50% or higher in the visible light range; and
a filler between the first light-emitting element and the first color filter,
wherein:
the single crystal semiconductor layer comprises silicon or silicon carbine,
the first electrode and the third electrode comprise one of aluminum, gold, platinum, silver, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, and palladium,
the second electrode comprises one of indium oxide, indium tin oxide, an indium oxide-zinc oxide alloy, zinc oxide, zinc oxide with gallium added, and graphene, and
the filler comprises one of an inert gas, an organic resin, and a sealant.

US Pat. No. 11,031,438

PIXEL FOR AN ORGANIC LIGHT-EMITTING DIODE MICROSCREEN

1. A pixel for an organic light-emitting diode microscreen, comprising, successively:a substrate;
a reflector that is reflective in the visible spectrum and is formed on the substrate;
a spacing layer that is formed on the reflector;
a first electrode that is transparent in the visible spectrum and is formed on the spacing layer;
a stack of organic light-emitting layers that is configured to emit a white light and is formed on the first electrode;
a second electrode that is semitransparent in the visible spectrum and is formed on the stack, the second electrode and the reflector forming an optical resonator; wherein
the spacing layer has first, second and third portions, the thicknesses of which are adjusted such that the optical resonator allows, respectively, the transmission of red, green and blue light from the white light emitted by the stack so as to define, respectively, red, green and blue sub-pixels;
the first, second and third portions of the spacing layer each includes lateral edges extending from the first electrode toward the reflector that are covered with a material that is reflective in the visible spectrum; and
the material covering the lateral edges has an uppermost surface located beneath and not in contact with the stack.

US Pat. No. 11,031,437

DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE

Hefei Xinsheng Optoelectr...

1. A display substrate, comprising a plurality of pixels, wherein,each of the plurality of pixels includes a plurality of sub-pixels that emit light of different colors, each of the plurality of sub-pixels includes a light emitting element, and the light emitting element includes an anode, a cathode, and a light emitting layer provided between the anode and the cathode,
the plurality of sub-pixels of each of the plurality of pixels includes a red-light sub-pixel, a green-light sub-pixel, and a blue-light sub-pixel, a light emitting layer of a light emitting element of the red-light sub-pixel emits red light, a light emitting layer of a light emitting element of the green-light sub-pixel emits green light, and a light emitting layer of a light emitting element of the blue-light sub-pixel emits blue light,
each of the red-light sub-pixel, the green-light sub-pixel, and the blue-light sub-pixel further includes a color filter,
a color filter of the red-light sub-pixel covers a portion of a light emitting region of the light emitting element of the red-light sub-pixel, and a color of the color filter of the red-light sub-pixel is the same as a color of the red light emitted by the light emitting layer of the red-light sub-pixel,
a color filter of the green-light sub-pixel covers a portion of a light emitting region of the light emitting element of the green-light sub-pixel, and a color of the color filter of the green-light sub-pixel is the same as a color of the green light emitted by the light emitting layer of the green-light sub-pixel,
a color filter of the blue-light sub-pixel covers a portion of a light emitting region of the light emitting element of the blue-light sub-pixel, and a color of the color filter of the blue-light sub-pixel is the same as a color of the blue light emitted by the light emitting layer of the green-light sub-pixel,
a coverage rate of the color filter of the green-light sub-pixel is less than a coverage rate of the color filter of the blue-light sub-pixel, and
wherein a position where the color filter of the green-light sub-pixel is provided corresponds to a center portion of the light emitting region of the light emitting element of the green-light sub-pixel.

US Pat. No. 11,031,436

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device, comprising:a substrate including a display area and a non-display area;
a pixel area in the display area, the pixel area divided into a plurality of first pixel columns including first pixels and second pixels, and a plurality of second pixel columns including third pixels, the third pixels being of a same third color only, and the first and second pixels being of first and/or second colors that are different from the third color;
first data lines respectively coupled to the first pixel columns; and
second data lines respectively coupled to the second pixel columns,
wherein a swing width of a data voltage sent by a data drive unit corresponding to the first and/or second colors is greater than a swing width of a data voltage sent by the data drive unit corresponding to the third color, and
wherein each of the first data lines has a first line structure or first contact structure having a first resistance that is less than a second resistance of a second line structure or second contact structure of each of the second data lines, such that an overall resistance between the data drive unit and each of the first pixel columns is less than an overall resistance between the data drive unit and each of the second pixel columns.

US Pat. No. 11,031,435

MEMORY DEVICE CONTAINING OVONIC THRESHOLD SWITCH MATERIAL THERMAL ISOLATION AND METHOD OF MAKING THE SAME

WESTERN DIGITAL TECHNOLOG...

1. A memory device, comprising:a plurality of memory cells;
an isolation material portion located between the plurality of memory cells, wherein the isolation material portion comprises at least one ovonic threshold switch material portion;
first electrically conductive lines laterally extending along a first horizontal direction and located over a substrate;
a two-dimensional array of memory pillar structures located on the first electrically conductive lines, wherein each memory pillar structure of the two-dimensional array of memory pillar structures comprises a memory cell of the plurality of memory cells; and
second electrically conductive lines laterally extending along a second horizontal direction and contacting top surfaces of a respective subset of the two-dimensional array of memory pillar structures;
wherein:
the isolation material portion further comprises a dielectric material layer in addition to the least one ovonic threshold switch material portion;
the isolation material portion surrounds the two-dimensional array of memory pillar structures;
a segment of the dielectric material layer and a segment of the at least one ovonic threshold switch material portion are located between each laterally-neighboring pair of memory pillar structures;
the at least one ovonic threshold switch material portion comprises a compound of at least one Group 14 elements and at least one Group 16 element; and
the at least one ovonic threshold switch material portion comprises an ovonic threshold switch material layer that contacts sidewalls of each memory pillar structure of the two-dimensional array of memory structures.

US Pat. No. 11,031,434

SELF ALIGNED GRIDS IN BSI IMAGE SENSOR

Taiwan Semiconductor Manu...

1. A device comprising:a substrate having a plurality of photodiodes formed therein;
a trench isolation grid having trench isolation grid segments embedded in the substrate, wherein a trench isolation grid segment laterally surrounds a photodiode; and
a conductive grid having conductive grid segments formed over the trench isolation grid, wherein the conductive grid comprises a conductive barrier layer and a metallic layer, wherein a conductive grid segment is aligned with and in direct contact with the trench isolation grid segment at an interface between the conductive grid segment and the trench isolation grid segment, and wherein a cross section of the conductive grid segment at the interface is identical to a cross section of the trench isolation grid segment at the interface.

US Pat. No. 11,031,433

BACK-SIDE ILLUMINATED IMAGE SENSOR

STMicroelectronics (Croll...

1. An image sensor, comprising:a semiconductor layer having a first surface and a second surface opposite the first surface, the semiconductor layer being a substantially uniform silicon layer;
a first insulation layer extending from the first surface of the semiconductor layer through the second surface of the semiconductor layer;
a second insulation layer spaced laterally apart from the first insulation layer, the second insulation layer extending from the first surface of the semiconductor layer through the second surface of the semiconductor layer; and
a region of conductive or semiconductor material between the first insulation layer and the second insulation layer, the region of conductive or semiconductor material being substantially coplanar with both the first and second surfaces of the semiconductor layer,
wherein the first and second insulation layers protrude outwardly beyond the second surface of the semiconductor layer, and the region of conductive or semiconductor material is substantially coplanar with the second surface of the semiconductor layer.

US Pat. No. 11,031,432

VERTICAL MICROBOLOMETER CONTACT SYSTEMS AND METHODS

FLIR Systems, Inc., Wils...

1. A method of forming an infrared imaging device, the method comprising:providing a device having a bolometer bridge structure and a contact structure, wherein the bolometer bridge structure is formed on a sacrificial layer, and wherein the contact structure extends through the sacrificial layer;
depositing an additional sacrificial layer over the sacrificial layer;
forming openings in the additional sacrificial layer;
forming a leg structure having at least a first portion that runs between the bolometer bridge structure and the contact structure, wherein the forming of the leg structure comprises forming portions of a first layer on sidewalls of the openings, and wherein the leg structure comprises the portions of the first layer; and
removing the sacrificial layer and the additional sacrificial layer to suspend the bolometer bridge structure and the leg structure above a substrate of the infrared imaging device, wherein the first portion of the leg structure has a first dimension that extends in a first direction that is substantially perpendicular to a plane defined by a surface of the substrate, wherein the first portion of the leg structure has a second dimension that extends in a second direction that is substantially parallel to the plane, wherein the portions of the first layer have a first dimension that extends in the first direction and a second dimension that extends in the second direction, and wherein the first dimension of the portions of the first layer is greater than the second dimension of the portions of the first layer.

US Pat. No. 11,031,431

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS

SONY SEMICONDUCTOR SOLUTI...

1. A method of manufacturing a semiconductor device, comprising:preparing a plurality of substrates, wherein
each of the plurality of substrates includes a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, and
the semiconductor substrate includes a circuit with a specific function; and
stacking the plurality of substrates, wherein
the plurality of substrates includes a plurality of bonding surfaces between at least two substrates of the plurality of substrates,
the plurality of bonding surfaces includes an electrode junction structure in which a plurality of electrodes on the plurality of bonding surfaces are joined in direct contact with each other,
the electrode junction structure is a structure for electrical connection between the two substrates, and
the plurality of electrodes and a via for connection of the plurality of electrodes to a wiring line in the multi-layered wiring layer includes:
forming a through hole that extends from one surface of a first substrate of the plurality of substrates to the wiring line,
forming a porous film including a porous material on at least a partial region of a sidewall of the through hole, and
filling the through hole having the porous film formed therein with an electrically-conductive material constituting the plurality of electrodes and the via.

US Pat. No. 11,031,430

IMAGE SENSOR WITH DUMMY LINES FOR MINIMIZING FIXED PATTERN NOISE (FPN) AND ELECTRONIC APPARATUS INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. An image sensor, comprising:a plurality of pixels, each pixel of the plurality of pixels including a photodiode, which is coupled to a transfer transistor, which is coupled to a reset transistor, which is coupled to a source-follower transistor, which is coupled to a selection transistor;
a plurality of first interconnection lines connected to a gate of the transfer transistor, a gate of the reset transistor, and a gate of the selection transistor, the plurality of first interconnection lines extending in a first direction; and
a plurality of second interconnection lines connected to a source region of the selection transistor, the plurality of second interconnection lines extending in a second direction that intersects the first direction,
wherein the plurality of second interconnection lines includes dummy lines on a peripheral area that is outside of a pixel area in which the pixels are located.

US Pat. No. 11,031,429

SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE PICKUP ELEMENT, IMAGE PICKUP DEVICE, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An image pickup device, comprising:a solid-state image pickup element that captures an image; and
a mounting substrate on which the solid-state image pickup element is mounted,
wherein the solid-state image pickup element is mounted on the mounting substrate with a connection portion having a configuration that does not use a solder ball,
wherein part of the mounting substrate is a transparent substrate,
wherein in a light receiving direction of the image pickup device, a bottom surface of the transparent substrate is adhered to an entire top light receiving surface of the solid-state image pickup element and
wherein the connection portion is provided outside a region where the bottom surface of the transparent substrate adheres to the entire top light receiving surface of the solid-state image pickup element.

US Pat. No. 11,031,428

IMAGE SENSOR

SAMSUNG ELECTRONICS CO., ...

1. An image sensor comprising:a semiconductor substrate including a plurality of photoelectric conversion regions; and
a plurality of isolation layers penetrating at least a portion of the semiconductor substrate,
wherein the plurality of isolation layers includes a first isolation layer, a second isolation layer, and a third isolation layer,
each of the first isolation layer, the second isolation layer, and the third isolation layer has a virtual line passing through a center of a bottom surface thereof and a center of a top surface thereof,
the virtual line of the first isolation layer is inclined in a first direction,
the virtual line of the second isolation layer is inclined in a second direction opposite to the first direction, and
the virtual line of the third isolation layer is substantially normal to a top surface of the semiconductor substrate.

US Pat. No. 11,031,427

SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

SONY CORPORATION, Tokyo ...

1. An imaging device comprising:a semiconductor substrate having a first side and a second side opposite to the first side;
a plurality of photoelectric conversion portions disposed in the semiconductor substrate;
a trench disposed between adjacent photoelectric conversion portions of the plurality of photoelectric conversion portions;
a wiring layer disposed adjacent to the second side of the semiconductor substrate;
a first material disposed in the trench;
a silicon oxide layer disposed above the first material and the first side of the semiconductor substrate, wherein a first part of a surface of the silicon oxide layer that faces the first material is coplanar with a second part of the surface of the silicon oxide layer that faces the first side of the substrate; and
a light-shielding portion disposed above the silicon oxide layer,
wherein the first material includes silicon oxide.

US Pat. No. 11,031,426

IMAGE SENSOR HAVING GRID ISOLATION STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. An image sensor, comprising:a substrate having a light-sensitive element therein;
a grid isolation structure above the substrate and including a reflective layer, a first dielectric layer above the reflective layer, and a second dielectric layer above the first dielectric layer, wherein a dielectric constant of the first dielectric layer is greater than a dielectric constant of the second dielectric layer, and a bottom of the first dielectric layer is above a top of the reflective layer; and
a color filter above the light-sensitive element and surrounded by the grid isolation structure.

US Pat. No. 11,031,425

IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. An image sensor comprising:a substrate including a pixel region and a pad region and including a first surface and a second surface opposite to the first surface;
a first conductive pad on the second surface of the substrate in the pad region;
a micro lens layer on the second surface of the substrate in the pixel region; and
a first protective pattern covering the pad region and exposing the first conductive pad,
wherein the first protective pattern and the micro lens layer include the same material,
wherein the first protective pattern overlaps both edges of the first conductive pad, and
wherein the first protective pattern and the micro lens layer are separated by a separation region.

US Pat. No. 11,031,424

IMAGE SENSOR WITH SELECTIVE LIGHT-SHIELDING FOR REFERENCE PIXELS

SAMSUNG ELECTRONICS CO., ...

1. An image sensor comprising:a substrate having a first surface and a second surface opposite to the first surface;
a first photoelectric conversion region and a second photoelectric conversion region in the substrate;
a first layer including a first opening and a second opening, the first layer being disposed to cover the second surface;
a second layer including a third opening and a fourth opening, the second layer being disposed on the first layer;
a planarization layer disposed on the second layer; and
a first lens corresponding to the first photoelectric conversion region and a second lens corresponding to the second photoelectric conversion region,
wherein the first opening is vertically aligned with the third opening and the second opening is vertically aligned with the fourth opening,
wherein the first opening is vertically aligned with a central portion of the first photoelectric conversion region, and
wherein the third opening is at least as wide as the first opening in a first direction.

US Pat. No. 11,031,423

IMAGING ELEMENT AND CAMERA SYSTEM

SONY CORPORATION, Tokyo ...

1. An imaging element comprising:a substrate;
a first layer including a red color filter, a green color filter, and a blue color filter;
a plurality of photoelectric conversion sections arrayed on the substrate, the plurality of photoelectric conversion sections configured to receive light incident through dielectric multilayer films, the photoelectric conversion sections including:
a red light photoelectric conversion section corresponding to the red color filter,
a green light photoelectric conversion section corresponding to the green color filter,
a blue light photoelectric conversion section corresponding to the blue color filter, and
a white light photoelectric conversion section;
a planarization layer;
a near-infrared absorption filter; and
a light-shielding layer including an opening, wherein the light-shielding layer separates neighboring photoelectric conversion sections, wherein at least a part of the near-infrared absorption filter is embedded into the opening of the light-shielding layer.

US Pat. No. 11,031,422

SOLID-STATE IMAGING ELEMENT AND IMAGING DEVICE

SONY SEMICONDUCTOR SOLUTI...

1. A solid-state imaging element, comprising:an optical sensor chip that includes a first substrate and a wiring layer, wherein
the wiring layer is on a specific surface of the first substrate, and
the specific surface of the first substrate is opposite to a light receiving surface of the first substrate;
a second substrate bonded to the wiring layer, wherein the wiring layer is between the first substrate and the second substrate;
a protective layer on the light receiving surface of the first substrate, wherein
the protective layer has a first thickness, and
the protective layer comprises a first material; and
a rewiring layer on a first surface of the second substrate, wherein
the first surface of the second substrate is opposite to a second surface of the second substrate,
the second surface of the second substrate faces the wiring layer,
the solid-state imaging element is a wafer-level chip size package,
the rewiring layer has a second thickness,
the rewiring layer comprises a second material different from the first material,
a connection terminal of the rewiring layer is a copper flat pad that excludes a solder ball,
an alloy layer of tin and copper is absent on a front surface of the copper flat pad, and
the first thickness of the protective layer and the second thickness of the rewiring layer are such that a thermal expansion coefficient of the protective layer is balanced with a thermal expansion coefficient of the rewiring layer.

US Pat. No. 11,031,421

SOLID-STATE IMAGING ELEMENT AND IMAGING APPARATUS

Sony Semiconductor Soluti...

1. A solid-state imaging element comprising:a first electric charge accumulating section and a second electric charge accumulating section arranged in a predetermined direction;
a plurality of first photoelectric conversion elements;
a first transfer section configured to transfer electric charge from the plurality of first photoelectric conversion elements to the first electric charge accumulating section and cause the first electric charge accumulating section to accumulate the electric charge;
a plurality of second photoelectric conversion elements;
a second transfer section configured to transfer electric charge from the plurality of second photoelectric conversion elements to the second electric charge accumulating section and cause the second electric charge accumulating section to accumulate the electric charge;
a first transistor configured to output a signal corresponding to an amount of the electric charge accumulated in each of the first electric charge accumulating section and the second electric charge accumulating section;
a second transistor arranged with the first transistor in the predetermined direction and connected in parallel to the first transistor, wherein
each of the first electric charge accumulating section and the second electric charge accumulating section is configured to generate a voltage corresponding to the amount of the accumulated electric charge, and
each of the first transistor and the second transistor is configured to amplify the voltage and output the voltage as the signal;
a third transistor and a fourth transistor arranged in the predetermined direction, wherein
the third transistor is configured to open and close a path between the first transistor and a predetermined signal line according to a predetermined selection signal, and
the fourth transistor is configured to open and close a path between the third transistor and the predetermined signal line according to the predetermined selection signal; and
a reset transistor and a dummy transistor arranged in the predetermined direction, wherein
the reset transistor is configured to initialize the first electric charge accumulating section and the second electric charge accumulating section.

US Pat. No. 11,031,420

IMAGE PICKUP DEVICE AND ELECTRONIC APPARATUS

SONY CORPORATION, Tokyo ...

1. An image pickup device, comprising:a first structural body, wherein the first structural body includes a pixel array unit having a plurality of pixels that photoelectrically convert incident light into an electric charge; and
a second structural body, wherein the second structural body is fixed to a side of the first structural body that is opposite a light incident side of the first structural body,
the second structural body including an input unit having an input circuit unit that inputs a signal from an outside of the device, an output unit having an output circuit unit that outputs a pixel signal from at least one of the pixels included in the plurality of pixels, and a signal processing circuit, wherein the output unit and the input unit are arranged adjacent the pixel array unit of the first structural body,
wherein a first through-via penetrates a semiconductor substrate constituting a part of the second structural body and connects a signal output external terminal to the output circuit unit,
wherein a second through-via penetrates the semiconductor substrate constituting a part of the second structural body and connects a signal input external terminal to the input circuit unit,
wherein the signal output external terminal is electrically connected to the first through-via by a first rewiring line,
wherein the signal input external terminal is electrically connected to the second through-via by a second rewiring line, and
wherein a third rewiring line that is electrically independent from at least the first rewiring line and the second rewiring line is disposed in a layer in which the first rewiring line and the second rewiring line are disposed.

US Pat. No. 11,031,419

ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

ORDOS YUANSHENG OPTOELECT...

1. An array substrate, comprising a base substrate, wherein the array substrate comprises a plurality of pixel units,wherein, in each of the plurality of pixel units, the array substrate comprises a thin film transistor and a storage capacitor disposed above the base substrate,
wherein the storage capacitor comprises a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate,
wherein the array substrate further comprises a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor;
wherein the thin film transistor comprises the active layer, a gate insulating layer, a gate electrode layer, an interlayer dielectric layer and a source-drain metal layer stacked sequentially on a side of the base substrate, and the active layer is adjacent to the base substrate; and
wherein the gate electrode layer and the metal layer are formed by using one and the same mask, the interlayer dielectric layer serves as the intermediate layer of the storage capacitor, and the metal layer is electrically connected to the active layer through a via hole provided in the gate insulating layer.

US Pat. No. 11,031,418

INTEGRATED CIRCUIT STRUCTURE AND METHOD WITH HYBRID ORIENTATION FOR FINFET

TAIWAN SEMICONDUCTOR MANU...

17. A semiconductor structure, comprising:a semiconductor substrate having a first region and a second region;
a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, and being isolated from the semiconductor substrate by a dielectric feature, wherein the first fin active region has a <100> crystalline direction along the first direction;
a second fin active region of a second semiconductor material disposed on the semiconductor substrate within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction, the second semiconductor material being different from the first semiconductor material in composition;
a shallow trench isolation (STI) feature formed in the semiconductor substrate, wherein the STI feature has a sidewall directly contacting a sidewall of the dielectric feature, wherein the STI feature has a top surface being coplanar with the top surface of the dielectric feature and the STI feature has a bottom surface being below a bottom surface of the dielectric feature; and
a silicon layer underlying the second fin active region, wherein the silicon layer includes a top surface being coplanar with a top surface of the dielectric feature, wherein
each of the first fin active region and the second fin active region is in a crystalline structure with a top surface on a (100) crystal plane;
the semiconductor substrate is a silicon substrate having a top surface on a (100) crystal plane; and
the semiconductor substrate has a crystalline orientation <110> along the first direction.

US Pat. No. 11,031,417

METHODS USED IN FORMING AN ARRAY OF ELEVATIONALLY-EXTENDING TRANSISTORS

Micron Technology, Inc., ...

1. A method used in forming an array of elevationally-extending transistors, comprising:forming vertically-alternating tiers of different composition first and second materials, the first material being insulative and the second material being conductive;
forming elevationally-extending dummy-structure openings into the vertically-alternating tiers;
forming elevationally-extending channel openings into the vertically-alternating tiers;
forming horizontally-elongated trenches extending elevationally into the vertically-alternating tiers;
simultaneously forming multiple different composition of the same solid materials into each of the dummy structure openings, the channel openings, and the trenches;
elevationally recessing the solid materials in the dummy-structure openings and in the trenches to form elevational recesses; and
filling such recesses with insulating material.

US Pat. No. 11,031,416

SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STORAGE DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device comprising:a first stacked body in which a plurality of conductive layers are stacked via a first insulating layer, the first stacked body having a first stepped portion in which end portions of the plurality of conductive layers are formed in a step shape in an upper layer and a second stepped portion in which end portions of the plurality of conductive layers are formed in a step shape in a lower layer;
a second stacked body in which a plurality of second insulating layers are stacked via a third insulating layer of an identical type as the first insulating layer, the second stacked body having a third stepped portion in which end portions of the plurality of second insulating layers in identical levels as the conductive layers forming the first stepped portion are formed in a step shape;
a plurality of pillars which extend in a stacking direction of the first stacked body in the first stacked body and forms a plurality of memory cells at intersections with the plurality of conductive layers;
a first columnar portion which is arranged in the first stepped portion and penetrates the first stacked body; and
a second columnar portion which is arranged in the second stepped portion and penetrates the first stacked body,
wherein the first stepped portion and the third stepped portion oppose each other, and the second stepped portion and the third stepped portion overlap each other at least partially in a top view.

US Pat. No. 11,031,415

SEMICONDUCTOR STORAGE DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device, comprising:a plurality of first conductive layers stacked in a first direction;
a second conductive layer disposed in the first direction with respect to the plurality of first conductive layers;
a plurality of first division films that respectively divide the plurality of first conductive layers and the second conductive layer in a second direction intersecting the first direction, and that respectively extend through the plurality of first conductive layers and the second conductive layer in the first direction and a third direction intersecting the first direction and the second direction, the second conductive layer including a first region disposed between two first films among the plurality of first division films:
a plurality of second division films that respectively divide the first region of the second conductive layer, in the second direction, and that respectively extend through the second conductive layer in the first direction and the third direction, the first region including a second region and a third region, the second region disposed between one first film of the two first films and a second film, the second film being the nearest among the plurality of second division films to the one first film, the third region disposed between the second film and a third film, the third film being the second nearest among the plurality of second division films to the one first film;
a first pillar-shaped portion including a first semiconductor layer, the first semiconductor layer extending m the first direction through the plurality of first conductive layers and the third region of the second conductive layer;
a second pillar-shaped portion including a second semiconductor layer, the second semiconductor layer extending in the first direction through the plurality of first conductive layers and the second region of the second conductive layer;
a first charge storage layer disposed between the first semiconductor layer and the plurality of first conductive layers;
a second charge storage layer disposed between the second semiconductor layer and the plurality of first conductive layers; and
a peripheral circuit configured to apply a first initial write voltage to a first layer among the plurality of first conductive layers when the peripheral circuit supplies a select potential to the third region of the second conductive layer, and configured to apply a second initial write voltage to the first layer when the peripheral circuit supply the select potential to the second region of the second conductive layer,
wherein the first initial write voltage is different from the second initial write voltage.

US Pat. No. 11,031,414

INTEGRATED ASSEMBLIES HAVING VERTICALLY-SPACED CHANNEL MATERIAL SEGMENTS, AND METHODS OF FORMING INTEGRATED ASSEMBLIES

Micron Technology, Inc., ...

1. An integrated structure, comprising:a vertical stack of alternating insulative levels and conductive levels;
the conductive levels having primary regions of a first vertical thickness, and having terminal projections of a second vertical thickness which is greater than the first vertical thickness;
charge-blocking material arranged in vertically-stacked first segments; the first segments being along the conductive levels, and being adjacent the terminal projections; the first segments being vertically spaced from one another by first gaps;
charge-storage material arranged in vertically-stacked second segments; the second segments being along the conductive levels, and being adjacent the first segments; the second segments being vertically spaced from one another by second gaps;
gate-dielectric material adjacent the charge-storage material;
channel material adjacent the gate-dielectric material; and
wherein each of the first and the second segments has a vertical length, at least one of the vertical lengths is greater than the second vertical thickness.

US Pat. No. 11,031,413

THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

Yangtze Memory Technologi...

1. A method for forming a three-dimensional (3D) NAND memory device, comprising:forming a plurality of hybrid shallow trench isolation structures in a substrate, comprising:
forming at least one row of shallow trenches extending in the horizontal direction in the substrate,
forming the plurality of hybrid shallow trench isolation structures in the at least one row of shallow trenches,
forming a dielectric sublayer in the at least one row of shallow trenches,
removing an upper portion of the dielectric sublayer, and
forming a conductive sublayer on the remaining portion of the dielectric sublayer and in the at least one row of shallow trenches;
forming an alternating dielectric stack on the substrate, the alternating dielectric stack including a plurality of dielectric layer pairs each comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer;
forming a plurality of channel structures in the alternating dielectric stack;
forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction to divide the plurality of channel structures and to expose a row of hybrid shallow trench isolation structures;
replacing the second dielectric layers in the alternating dielectric stack with a plurality of gate structures through the slit;
forming a spacer wall to fill the slit; and
forming a plurality of array common source contacts each in electric contact with a corresponding hybrid shallow trench isolation structure of the plurality of hybrid shallow trench isolation structures, comprising:
forming a plurality of via holes each vertically penetrating the substrate and the dielectric sublayer of a corresponding hybrid shallow trench isolation structure of the plurality of hybrid shallow trench isolation structures, and
forming the plurality of array common source contacts in the plurality of via holes respectively,
each array common source contact being in electrical contact with the conductive sublayer of the corresponding shallow trench isolation structure.

US Pat. No. 11,031,412

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device including a non-volatile memory (NVM) cell, wherein:the NVM cell includes a semiconductor wire disposed over an isolation insulating layer disposed on a substrate, the semiconductor wire including a select gate portion and a control gate portion,
the NVM cell includes a select transistor formed at the select gate portion and a control transistor formed at the control gate portion,
the select transistor includes a first gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the first gate dielectric layer, and
the control transistor includes a second gate dielectric layer disposed around the control gate portion, a third gate dielectric layer disposed on the second gate dielectric layer and a control gate electrode disposed on the third gate dielectric layer.

US Pat. No. 11,031,411

VERTICAL NON-VOLATILE MEMORY DEVICE WITH HIGH ASPECT RATIO

Samsung Electronics Co., ...

10. A non-volatile memory device comprising:a substrate;
a lower insulating layer disposed on the substrate;
a multilayer structure of layers comprising gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, the multilayer structure having an opening extending vertically from the lower insulating layer, the opening including a first open portion and a second open portion,
wherein the first open portion extends through at least one of the layers of the multilayer structure from the lower insulating layer, and the second open portion is located on the first open portion and extends vertically upwardly from the first open portion in the multilayer structure, and the opening has a first width at the first open portion and a second width at the second open portion, the second width being less than the first width;
a gate dielectric extending along an inner surface and a lower surface defining a side and a bottom of the opening, respectively; and
a channel structure disposed on the gate dielectric within the opening as extending along the inner surface and the lower surface defining the side and the bottom of the opening, the channel structure extending through the lower insulating layer and electrically connected to the substrate,
wherein the channel structure includes a first channel layer on the gate dielectric and a second channel layer electrically connected to the substrate on the first channel layer,
wherein a distance from a bottom surface of the gate dielectric to an upper surface of the substrate is smaller than a distance between an upper surface of the second channel layer and an upper surface of the lower insulating layer in the first open portion, and
wherein a lower surface of the gate dielectric contacts an upper surface of the lower insulating layer in the bottom of the opening.

US Pat. No. 11,031,410

NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

Samsung Electronics Co., ...

1. A nonvolatile memory device comprising:a mold structure which includes a first insulating pattern, a first gate electrode and a second insulating pattern sequentially stacked on a substrate;
a semiconductor pattern which penetrates the mold structure, is connected to the substrate, and extends in a first direction;
a first charge storage film extending in the first direction between the first insulating pattern and the second insulating pattern and between the first gate electrode and the semiconductor pattern; and
a blocking insulation film between the first gate electrode and the first charge storage film,
wherein a first length at which the first charge storage film extends in the first direction is longer than a second length at which the blocking insulation film extends in the first direction, and
wherein the first charge storage film includes a protrusion extending, in the first direction, into one of the first insulating pattern and the second insulating pattern.

US Pat. No. 11,031,409

CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY

Taiwan Semiconductor Manu...

1. An integrated circuit (IC), comprising:a semiconductor substrate including a logic region and a memory region;
a dielectric isolation structure disposed between the logic region and the memory region;
a memory cell structure disposed on the memory region and a logic device structure disposed on the logic region; and
a cell boundary structure disposed on the dielectric isolation structure and comprising a boundary sidewall spacer facing the logic region;
wherein the boundary sidewall spacer and an upper portion of the dielectric isolation structure collectively define a boundary sidewall facing the logic region, wherein the boundary sidewall is continuously slanted, and
wherein the boundary sidewall spacer comprises a sidewall different than the boundary sidewall that directly contacts the dielectric isolation structure.

US Pat. No. 11,031,408

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device, comprising:a semiconductor substrate, and
a nonvolatile memory cell disposed on the semiconductor substrate, wherein:
the nonvolatile memory cell comprises a field-effect transistor for data writing, and a field-effect transistor for data readout that is adjacent to the field-effect transistor for data writing,
each of the field-effect transistor for data writing and the field-effect transistor for data readout includes a gate insulating film formed on the semiconductor substrate, a floating gate formed on the gate insulating film, and diffusion layers configuring a source region and a drain region on respective sides of the floating gate viewed in a thickness direction of the semiconductor substrate, and
a thickness of the gate insulating film of the field-effect transistor for data readout, and a thickness of the gate insulating film of the field-effect transistor for data writing, are different.

US Pat. No. 11,031,407

ANTI-FUSE DEVICE, CIRCUIT, METHODS, AND LAYOUT

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit (IC) device comprising:an active area comprising first through fourth source-drain (S/D) structures;
an anti-fuse transistor device comprising a dielectric layer between a first gate structure and the active area;
a first selection transistor comprising a second gate structure overlying the active area; and
a second selection transistor comprising a third gate structure overlying the active area,
wherein
the first gate structure is between the second gate structure and the third gate structure,
the second gate structure overlies the first S/D structure and the second S/D structure,
the first gate structure overlies the second S/D structure and the third S/D structure, and
the third gate structure overlies the third S/D structure and the fourth S/D structure.

US Pat. No. 11,031,406

SEMICONDUCTOR DEVICES HAVING SILICON/GERMANIUM ACTIVE REGIONS WITH DIFFERENT GERMANIUM CONCENTRATIONS

GLOBALFOUNDRIES U.S. INC....

1. A semiconductor device, comprising:a first transistor element comprising a first channel region, said first channel region comprising a first crystalline silicon/germanium (Si/Ge) material mixture having a first germanium concentration;
a second transistor element comprising a second channel region, said second channel region comprising a second crystalline Si/Ge material mixture having a second germanium concentration that is higher than said first germanium concentration; and
a third transistor element comprising a third channel region, wherein said third channel region comprises a third crystalline semiconductor material having a lower germanium concentration than said first and second germanium concentrations.

US Pat. No. 11,031,405

PERIPHERAL LOGIC CIRCUITS UNDER DRAM MEMORY ARRAYS

Micron Technology, Inc., ...

1. A method, comprising:forming at least, one peripheral circuit; and
forming a DRAM memory array over the at least one peripheral circuit, the at least one peripheral circuit configured to control an operation of the DRAM memory array, wherein forming the DRAM memory array includes:
forming an access transistor over the at least one peripheral circuit;
forming a digit line over the access transistor and coupled to the access transistor and the at least one peripheral circuit;
forming a wordline over the access transistor and coupled to the access transistor and the at least one peripheral circuit; and
forming a capacitor structure over the digit line and the wordline and coupled to the access transistor;
wherein forming the at least one peripheral circuit includes forming a first level of conductive line under the access transistor and coupled to the access transistor, and forming a second level of conductive line under the access transistor and between the access transistor and the first level of conductive line, the second level of conductive line coupled to the first level of conductive line, and wherein the peripheral circuit comprises sense amplifiers and sub-word line drivers; and
staggering the sense amplifiers and the sub-word line drivers by an approximately half-core length, the core length being a characteristic dimension of at least, one side of the DRAM memory array.

US Pat. No. 11,031,404

DYNAMIC MEMORY STRUCTURE WITH A SHARED COUNTER ELECTRODE

Etron Technology, Inc., ...

1. A DRAM structure, comprising:a capacitor set with a first capacitor and a second capacitor; and
a first transistor electrically coupled to the capacitor set, wherein the capacitor set further comprises a counter electrode shared by the first and the second capacitors, and the counter electrode is perpendicular to an extension direction of an active region of the first transistor, wherein the DRAM structure further comprises a second transistor electrically coupled to the capacitor set and the capacitor set is formed in a concave of a semiconductor substrate, the capacitor set further comprises:
an isolating layer positioned around side-walls of the concave;
a first and a second electrodes abutting against the isolating layer;
an insulator configured between the first and the second electrodes, wherein the counter electrode is surrounded by the insulator; and
two collar connectors positioned on a top of the isolating layer around the side-walls of the concave.

US Pat. No. 11,031,403

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor, a second transistor, a first capacitor, a second capacitor, and a wiring;
wherein the first transistor comprises:
an oxide semiconductor over a first insulator;
a second insulator over the oxide semiconductor;
a first conductor over the second insulator;
a third insulator over the first conductor;
a fourth insulator in contact with the second insulator, the first conductor, and the third insulator; and
a fifth insulator in contact with the fourth insulator,
wherein the second transistor comprises:
the semiconductor oxide over the first insulator;
a sixth insulator over the oxide semiconductor;
a second conductor over the sixth insulator;
a seventh insulator over the second conductor;
an eighth insulator in contact with the sixth insulator, the second conductor, and the seventh insulator; and
a ninth insulator in contact with the eighth insulator,
wherein the first capacitor comprises:
the oxide semiconductor;
a tenth insulator in contact with one side surface of the oxide semiconductor in a channel length direction and part of a top surface of the oxide semiconductor; and
a third conductor over and in contact with the tenth insulator,
wherein the second capacitor comprises:
the oxide semiconductor;
an eleventh insulator in contact with the other side surface of the oxide semiconductor in the channel length direction and part of the top surface of the oxide semiconductor; and
a fourth conductor over and in contact with the eleventh insulator,
wherein the oxide semiconductor comprises:
a channel formation region of the first transistor overlapping with the second insulator;
a channel formation region of the second transistor overlapping with the sixth insulator; and
a region between the channel formation region of the first transistor and the channel formation region of the second transistor, and
wherein the wiring is in contact with the fifth insulator and the ninth insulator and electrically connected to the region.

US Pat. No. 11,031,402

CAPACITORLESS DRAM CELL

International Business Ma...

1. A capacitorless DRAM cell, the cell comprising:a heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, wherein the channel layers and the barrier layers are alternatingly stacked in a first direction;
a gate structure adjoining the heterostructure in the first direction, wherein the gate structure comprises a gate insulator layer adjoining the barrier layer;
a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction; and
a source structure adjoining the heterostructure in a direction opposite the second direction.

US Pat. No. 11,031,401

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. A semiconductor memory array comprising a plurality of semiconductor memory cells, wherein each of said semiconductor memory cells comprises:a memory transistor comprising:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first insulating region located above said floating body region;
second insulating regions adjacent to said floating body region;
a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions;
wherein said floating body region is configured to be bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, and a depletion region formed as a result of an application of a back bias to said buried layer region; and
an access device comprising a body region, wherein said access device is connected in series to said memory transistor, and wherein said body region is configured to be isolated from said floating body region by said depletion region;
 wherein said buried layer region is located underneath at least two of said memory cells.

US Pat. No. 11,031,400

INTEGRATED MEMORY COMPRISING SECONDARY ACCESS DEVICES BETWEEN DIGIT LINES AND PRIMARY ACCESS DEVICES

Micron Technology, Inc., ...

1. An integrated assembly, comprising:a primary access transistor having a first source/drain region and a second source/drain region which are coupled to one another when the primary access transistor is in an ON mode, and which are not coupled to one another when the primary access transistor is in an OFF mode;
a charge-storage device coupled with the first source/drain region; and
a digit line coupled with the second source/drain region through a secondary access device; the secondary access device having an ON mode and an OFF mode; the digit line being coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

US Pat. No. 11,031,399

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

SONY CORPORATION, Tokyo ...

1. A first semiconductor device, comprising:a compound semiconductor substrate; and
a second semiconductor device and a field effect transistor on the compound semiconductor substrate, wherein
the second semiconductor device is a p-type field effect transistor, and
the second semiconductor device comprises:
a buffer layer, wherein the buffer layer comprises a first semiconductor configured to produce a piezoelectric polarization; and
a first semiconductor layer of Gallium Aluminum Indium Phosphide (GaAlInP) stacked between the buffer layer and the compound semiconductor substrate.

US Pat. No. 11,031,398

STRUCTURE AND METHOD FOR SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

17. A semiconductor device, comprising:a substrate;
an isolation structure over the substrate;
two first fins in a P-type region of the semiconductor device;
two second fins in an N-type region of the semiconductor device, wherein the two first fins and the two second fins extend from the substrate and through the isolation structure, the two first fins are disposed side-by-side, the two second fins are disposed side-by-side, and each of the two first fins and the two second fins has a channel region and two source/drain (S/D) regions sandwiching the respective channel region;
first and second gate stacks over the isolation structure, the first gate stack engaging the channel regions of the two first fins, the second gate stack engaging the channel regions of the two second fins;
a dielectric layer disposed over the isolation structure and adjacent to the S/D regions of the two first fins and the two second fins;
four first S/D features over the S/D regions of the two first fins; and
four second S/D features over the S/D regions of the two second fins,
wherein:
each of the four first S/D features and the four second S/D features includes a lower portion and an upper portion over the lower portion;
the lower portions of the four first S/D features and the four second S/D features are surrounded at least partially by the dielectric layer;
each of the lower portions of the four first S/D features and the four second S/D features has a cross-sectional profile that is wider at its bottom than at its top;
the upper portions of the four second S/D features merge into two merged second S/D features with one on each side of the second gate stack; and
each of the two merged second S/D features has a curvy top surface.

US Pat. No. 11,031,397

MULTI-GATE DEVICE INTEGRATION WITH SEPARATED FIN-LIKE FIELD EFFECT TRANSISTOR CELLS AND GATE-ALL-AROUND TRANSISTOR CELLS

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit comprising:a first cell including first gate-all-around (GAA) transistors located in a first region of the integrated circuit;
a second cell including second GAA transistors located in the first region of the integrated circuit, wherein the second cell is disposed directly adjacent to the first cell, the first GAA transistors have first channel semiconductor layers having a first width, and the second GAA transistors have second channel semiconductor layers have a second width that is different than the first width; and
a third cell including fin-like field effect transistors (FinFETs) located in a second region of the integrated circuit, wherein the second region of the integrated circuit does not share an interface with the first region of the integrated circuit and a distance between the second region of the integrated circuit and the first region of the integrated circuit is equal to at least four times a first gate pitch of the first GAA transistors or a second gate pitch of the second GAA transistors.

US Pat. No. 11,031,396

SPACER FOR DUAL EPI CMOS DEVICES

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor comprising:patterning a first transistor comprising two or more first gate stacks on a first source-drain area and a second transistor comprising two or more second gate stacks on a second source-drain area, the first source-drain area and the second source drain area each comprising a horizontal surface, the horizontal surface being on an upper surface of the first and second source-drain areas, respectively, and wherein the upper surface is level with the bottom surface of the gate stack;
depositing a wet-etch resistant spacer material on the first and second transistors;
removing the spacer from a first transistor fin region and a second transistor fin region with anisotropic spacer reactive ion etch;
depositing a first nitride liner on the first and second transistors;
depositing a dielectric layer on the first nitride layer;
planarizing the dielectric layer;
selectively removing the dielectric layer from between the spacer material in the first transistor fin region and the second transistor fin region;
depositing a second nitride liner on the first and second transistors and selectively removing the second nitride liner from the first source-drain area;
growing a first epitaxial layer on the first source-drain area by an epitaxial growth process such that the epitaxial layer extends the length of the first source-drain area and covers the horizontal surface of the first source drain area except areas covered by the gate stack and the dielectric spacers;
depositing a third nitride liner on the first and second transistors and selectively removing the third nitride liner from the second source-drain area; and
growing a second epitaxial layer on the second source-drain area by an epitaxial growth process such that the epitaxial layer extends the length of the second source-drain area and covers the horizontal surface of the second source drain area except areas covered by the gate stack and the dielectric spacers,
wherein removing the spacer from the first transistor fin region and the second transistor fin region is performed after selectively removing the dielectric layer from between the spacer material in the first transistor fin region and the second transistor fin region.

US Pat. No. 11,031,395

METHOD OF FORMING HIGH PERFORMANCE MOSFETS HAVING VARYING CHANNEL STRUCTURES

Taiwan Semiconductor Manu...

1. A method comprising:disposing a first and a second vertical structure over a substrate, wherein the first and second vertical structures are separated by a first isolation layer and each of the first and the second vertical structures have different widths and a top portion, above the first isolation layer, comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers;
disposing a sacrificial gate structure over the top portion of the first and second vertical structures and over a portion of the first isolation layer;
depositing a second isolation layer over the first and second vertical structures and the first isolation layer so that the second isolation layer surrounds a sidewall of the sacrificial gate structure;
etching the sacrificial gate structure to expose each multilayer nano-sheet stack of the first and second vertical structures;
removing the first nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended second nano-sheet layers;
forming a metal gate structure to surround the suspended second nano-sheet layers, the metal gate structure comprising a metal gate electrode;
after forming the metal gate structure, etching the metal gate electrode to expose one or more upper nano-sheet layers of the second nano-sheet layers; and
after etching the metal gate electrode, removing the one or more upper nano-sheet layers, wherein the metal gate electrode is a gate electrode of a transistor.

US Pat. No. 11,031,394

3D SEMICONDUCTOR DEVICE AND STRUCTURE

MONOLITHIC 3D INC., Klam...

1. A 3D semiconductor device, the device comprising:a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprising second transistors, and
wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections; and
a plurality of connection paths,
wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors,
wherein said second level is bonded to said first level,
wherein said bonded comprises oxide to oxide bond regions,
wherein said bonded comprises metal to metal bond regions,
wherein said second level comprises at least one memory array,
wherein said first level comprises a first die area,
wherein said first level comprises a first clock tree,
wherein said second level comprises a second clock tree,
wherein at least one of said connection paths comprises connecting between said first clock tree and said second clock tree, and
wherein said third layer comprises crystalline silicon.

US Pat. No. 11,031,393

III-V FINS BY ASPECT RATIO TRAPPING AND SELF-ALIGNED ETCH TO REMOVE ROUGH EPITAXY SURFACE

International Business Ma...

1. A method of reducing roughness in a fin structure comprising:forming a dielectric material layer on a planar top surface of a substrate;
forming a trench in the dielectric material layer to expose a portion of the planar top surface of the substrate;
forming a semiconductor material having a fin geometry in the trench with a first width of less than 50 nm, wherein a second portion of the semiconductor material contacting dielectric sidewalls of the trench has a greater roughness than a first portion of the semiconductor material that is not in contact with the dielectric sidewalls;
forming a spacer component abutting the dielectric sidewalls of the trench that are atop the second portion of the semiconductor material having the greater roughness;
forming a masking structure over the first portion of the semiconductor material; and
removing the spacer component and the second portion of the semiconductor material using the masking structure as an etch mask to provide the fin structure having a second width of less than 20 nm.

US Pat. No. 11,031,392

INTEGRATED CIRCUIT DEVICE HAVING A WORK FUNCTION CONTROL LAYER WITH A STEP PORTION LOCATED ON AN ELEMENT ISOLATION LAYER

SAMSUNG ELECTRONICS CO., ...

16. An integrated circuit device comprising:a buried insulation layer on a substrate;
a first active area, a second active area and an element isolation layer on the buried insulation layer, wherein the first active area and the second active area are arranged spaced apart from each other by the element isolation layer;
a plurality of first semiconductor patterns on the first active area, the plurality of first semiconductor patterns being spaced apart from a top surface of the first active area and each of the plurality of first semiconductor patterns having a channel area;
a plurality of second semiconductor patterns on the second active area, the plurality of second semiconductor patterns being apart from a top surface of the second active area and each of the plurality of second semiconductor patterns having a channel area;
a first work function control layer including a first portion surrounding each of the plurality of first semiconductor patterns and a second portion extending from the first portion onto the element isolation layer, the second portion of the first work function control layer including a first step portion which is on the element isolation layer and has a first thickness, and a second step portion; and
a second work function control layer including a third portion surrounding each of the plurality of second semiconductor patterns, a fourth portion extending from the third portion onto the element isolation layer, the fourth portion of the second work function control layer having a second thickness being greater than the first thickness,
wherein the first step portion of the first work function control layer is disposed between the second step portion of the first work function control layer and the first active area, and
wherein the second step portion of the first work function control layer is connected to the second work function control layer.

US Pat. No. 11,031,391

METHOD FOR MANUFACTURING A FINFET DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:etching a semiconductor substrate to form semiconductor fins;
depositing a dielectric material into a trench between the semiconductor fins;
etching the semiconductor fins such that top ends of the semiconductor fins are lower than a top surface of the dielectric material;
after etching the semiconductor fins, epitaxially growing epitaxial fins on the semiconductor fins, respectively;
performing a chemical mechanical polish (CMP) process on the epitaxial fins;
after performing the CMP process, cleaning the epitaxial fins using a non-contact-type cleaning device;
after cleaning the epitaxial fins using the non-contact-type cleaning device, etching the dielectric material such that the top surface of the dielectric material is lower than top ends of the epitaxial fins; and
forming a gate structure across the epitaxial fins.

US Pat. No. 11,031,390

BIDIRECTIONAL SWITCH HAVING BACK TO BACK FIELD EFFECT TRANSISTORS

Alpha and Omega Semicondu...

1. A method for forming a bi-directional semiconductor switching device, comprising:forming first and second vertical field effect transistors (FETs) in tandem from a semiconductor substrate, wherein a source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side, wherein gates for both the first and second FETs are disposed in tandem in a common set of trenches formed in a drift region of the semiconductor substrate that is sandwiched between the source for the first FET and the source for the second FET, wherein the drift region forms a common drain for both the first FET and the second FET wherein the drift region is of a same conductivity type as the source for the first FET and the source for the second FET but at a lower carrier concentration than that of the source for the first FET and the source for the second FET.

US Pat. No. 11,031,389

SEMICONDUCTOR STRUCTURES OVER ACTIVE REGION AND METHODS OF FORMING THE STRUCTURES

GLOBALFOUNDRIES U.S. INC....

1. A semiconductor device comprising:an active region and a shallow trench isolation layer disposed above a substrate;
a plurality of source or drain regions disposed in the active region;
a plurality of gate stacks having a first and second gate stacks, wherein each gate stack is disposed in between the source or drain regions;
a plurality of trench contact structures having a first and second trench contact structures, wherein each trench contact structure is disposed on a corresponding source or drain region;
gate spacers with top surfaces, wherein the gate spacers are adjacent to the trench contact structures;
a gate cut region having a plurality of gate isolation structures disposed on the shallow trench isolation layer, wherein the first trench contact structure is also disposed on the shallow trench isolation and in between the gate isolation structures;
a gate cap dielectric layer disposed on the first or the second gate stack;
a trench cap dielectric layer disposed on a top surface of the first or the second trench contact structure and the top surfaces of the gate spacers, wherein the trench cap dielectric layer has a top surface that is coplanar with a top surface of the gate cap dielectric layer; and
a dielectric fill layer disposed on the gate isolation structures and adjacent to the trench cap dielectric layer.

US Pat. No. 11,031,388

SEMICONDUCTOR STRUCTURE AND DRIVING CHIP

Silergy Semiconductor Tec...

1. A semiconductor structure, comprising:a) a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first and second regions;
b) an isolation structure located in the isolation region, wherein the isolation structure comprises a first isolation ring having a first doping type, and a second isolation ring having a second doping type, wherein the first isolation ring is configured to absorb first carriers flowing from the first region to the second region, the second isolation ring is configured to absorb second carriers flowing from the second region to the first region, the first isolation ring comprises a first portion adjacent to the first region, and a second portion adjacent to the second region, and the second isolation ring is located between the first and second portions of the first isolation ring; and
c) a lateral blocking component formed between the first isolation ring and the second isolation ring in the isolation structure, wherein the lateral blocking component comprises a trench configured to block a lateral flow of the first and second carriers, in order to increase a flow path of the first and second carriers in the semiconductor substrate.