US Pat. No. 10,971,761

INTERFACIAL LAYERS FOR SOLID-STATE BATTERIES AND METHODS OF MAKING SAME

UNIVERSITY OF MARYLAND, C...

1. An interfacial layer and solid-state electrolyte (SSE) combination comprising:an interfacial layer that is an inorganic interfacial layer;
an anode material; and
a sintered solid-state electrolyte (SSE) material comprising pores,
wherein the inorganic interfacial layer is a metal oxide selected from Al2O3, TiO2, V2O5, Y2O3, and combinations thereof or a lithiated metal oxide selected from Al2O3, TiO2, V2O5, Y2O3, and combinations thereof, and has a thickness of 1 nm to 100 nm, and is in contact with at least a portion of the SSE material and the anode material within the pores, and the interfacial layer increases contact between the SSE material and the anode material.

US Pat. No. 10,971,760

HYBRID SOLID-STATE CELL WITH A SEALED ANODE STRUCTURE

KERACEL, INC., San Jose,...

1. A monolithic ceramic electrochemical cell comprising:a first electrochemical sub cell housing comprising a first anode receptive space, a cathode receptive space, a first separator between the first anode receptive space and the cathode receptive space; and
a second electrochemical sub cell housing comprising a second anode receptive space, the cathode receptive space, and a second separator between the second anode receptive space and the cathode receptive space, the cathode receptive space being the cathode receptive space for the first electrochemical sub-cell housing and the second electrochemical sub-cell housing,
wherein the cathode receptive space is bounded on one side by a first cathode current collector and on the other side by a second cathode current collector.

US Pat. No. 10,971,759

DEVICE FOR BATTERY FORMATION

JIANGSU CONTEMPORARY AMPE...

1. A device for battery formation, comprising a base plate, a press plate, a positioning block and a connecting assembly;the press plate being connected with the base plate, the positioning block and the connecting assembly each being provided as plurality in number, and the plurality of the connecting assemblies corresponding to the plurality of positioning blocks;
the positioning block having a main portion and a protruding portion, the main portion being provided between the base plate and the press plate, and the protruding portion extending from a surface of the main portion away from the press plate;
the base plate being provided with a plurality of positioning holes, and the protruding portion of each positioning block being inserted into the positioning hole;
each connecting assembly being provided to the main portion of a corresponding positioning block and used for being connected to a battery.

US Pat. No. 10,971,758

ELECTROLYTE ADDITIVE AND LITHIUM SECONDARY BATTERY COMPRISING THE SAME

1. An electrolyte additive comprising:a salt of an anion with K+ or Na+, the anion being derived from a nitrogen atom-containing compound, and
a lithium-containing compound for forming a coating film,
wherein the anion derived from a nitrogen atom-containing compound is at least one selected from the group consisting of amide-based anion, imide-based anion, nitrile-based anion, nitrite anion, and nitrate anion,
wherein the amide-based anion is represented by Chemical Formula 1 below:

in Chemical Formula 1, R1 and R2 are each fluoro or C1-C4 fluoroalkyls, or R1 and R2 may be linked to each other to form a ring having a C1-C4 fluoroalkylene group,
wherein the lithium-containing compound for forming a coating film is at least one selected from the group consisting of LiPO2F2, LiBOB, LiTFSI, LiFSI, and LiDFOB,
wherein a weight ratio of the salt of the anion derived from the nitrogen atom-containing compound with K+ or Na+ and the lithium-containing compound for forming a coating film is 1:0.5 to 1:4.

US Pat. No. 10,971,757

LITHIUM-ION BATTERY AND ITS ELECTROLYTE

Contemporary Amperex Tech...

1. A Lithium ion battery electrolyte comprising an organic solvent, a lithium salt, and an additive, wherein the said additive comprises a cyclic fluoro carbonate (A), a cyclic phosphazene (B), a cyclic sulfate (C) and a lithium fluoro oxalate borate (D),wherein the cyclic fluoro carbonate (A) iswherein the cyclic phosphazene (B) iswherein the cyclic sulfate (C) iswherein the lithium fluoro oxalato borate (D) isand wherein the cyclic fluoro carbonate is present in an amount of 15 to 25%, based on the total weight of the electrolyte.

US Pat. No. 10,971,756

POLYMER ELECTROLYTE, POLYMER, ELECTROCHEMICAL DEVICE, AND METHOD OF PREPARING THE POLYMER

SAMSUNG ELECTRONICS CO., ...

1. A polymer electrolyte comprising:a copolymer represented by Formula 1; and
a lithium salt:

wherein, in Formula 1,
each R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, and R14, are the same or different, and are each independently a hydrogen atom; a halogen atom; a linear or branched C1-C10 alkyl group that is unsubstituted or substituted with halogen; a C6-C10 cycloalkyl group that is substituted or unsubstituted with halogen; a C2-C10 alkenyl group that is substituted or unsubstituted with halogen; a C2-C10 alkynyl group that is substituted or unsubstituted with halogen; a C6-C10 aryl group that is substituted or unsubstituted with halogen; or a C2-C10 heteroaryl group that is substituted or unsubstituted with halogen,
each R15 is the same or different, and is a linear or branched C1-C10 alkyl group that is unsubstituted or substituted with halogen; a C6-C10 cycloalkyl group that is substituted or unsubstituted with halogen; a C2-C10 alkenyl group that is substituted or unsubstituted with halogen; a C2-C10 alkynyl group that is substituted or unsubstituted with halogen; a C6-C10 aryl group that is substituted or unsubstituted with halogen; or a C2-C10 heteroaryl group that is substituted or unsubstituted with halogen,
each R16 is the same or different, and is a covalent bond; a C1-C10 linear or branched alkylene group that is substituted or unsubstituted with halogen; -(—Ra—O—)k—, wherein k is an integer of 2 to 100, and Ra is a C2-C10 alkylene group that is substituted or unsubstituted with halogen; a C6-C10 cycloalkylene group that is substituted or unsubstituted with halogen; a C6-C10 arylene group that is substituted or unsubstituted with halogen; a C2-C10 heteroarylene group that is substituted or unsubstituted with halogen; or a divalent linking group comprising one or more of the foregoing groups,
each R17 is the same or different, and is a halogen atom; a linear or branched C1-C10 alkyl group that is unsubstituted or substituted with halogen; a C6-C10 cycloalkyl group that is substituted or unsubstituted with halogen; a C2-C10 alkenyl group that is substituted or unsubstituted with halogen; a C2-C10 alkynyl group that is substituted or unsubstituted with halogen; a C6-C10 aryl group that is substituted or unsubstituted with halogen; or a C2-C10 heteroaryl group that is substituted or unsubstituted with halogen,
L1 is a covalent bond or —Rb—C(?O)—O—, and L2 is a covalent bond or —C(?O)—Rc—, wherein Rb and Rc are each independently a linear or branched C1-C20 alkylene group,
n1 is an integer of 2 to 100, and
x, y, and z are each mole fractions in repeating units, wherein 0

US Pat. No. 10,971,755

SECONDARY BATTERY-USE ELECTROLYTIC SOLUTION, SECONDARY BATTERY, BATTERY PACK, ELECTRIC VEHICLE, ELECTRIC POWER STORAGE SYSTEM, ELECTRIC POWER TOOL, AND ELECTRONIC APPARATUS

Murata Manufacturing Co.,...

1. A secondary battery comprising:a cathode;
an anode; and
a nonaqueous electrolytic solution,
the nonaqueous electrolytic solution including
a first compound represented by a formula (1),
a second compound represented by one or both of a compound represented by a formula (2) and a compound represented by a formula (3), and
a third compound represented by one or more of a compound represented by a formula (4), a compound represented by a formula (5), a compound represented by a formula (6), a compound represented by a formula (7), and a compound represented by a formula (9), and
a content of the first compound represented by the formula (1) in the nonaqueous electrolytic solution being within a range of 2.5 mol/dm3 to 6 mol/dm3 both inclusive,
M+[(Z1Y1)(Z2Y2)N]?  (1)
where M is a metal element, each of Z1 and Z2 is one of a fluorine group (—F), a monovalent hydrocarbon group, and a monovalent fluorinated hydrocarbon group, one or both of Z1 and Z2 are one of the fluorine group and the monovalent fluorinated hydrocarbon group, each of Y1 and Y2 is one of a sulfonyl group (—S(?O)2—) and a carbonyl group (—C(?O)—),
R1-CN  (2)
where R1 is a monovalent hydrocarbon group,
R2-X—CN  (3)
where R2 is a monovalent hydrocarbon group, and X is a group in which one or more ether bonds (—O—) and one or more divalent hydrocarbon groups are bound in any order,

where each of R3 and R4 is one of a hydrogen group (—H) and a monovalent hydrocarbon group, each of R5 to R8 is one of a hydrogen group, a monovalent saturated hydrocarbon group, and a monovalent unsaturated hydrocarbon group, one or more of R5 to R8 are the monovalent unsaturated hydrocarbon group, R9 is a group represented by >CR10R11, and each of R10 and R11 is one of a hydrogen group and a monovalent hydrocarbon group,

where each of R12 to R15 is one of a hydrogen group, a halogen group, a monovalent hydrocarbon group, and a monovalent halogenated hydrocarbon group, one or more of R12 to R15 are one of the halogen group and the monovalent halogenated hydrocarbon group, and
R22-(CN)n  (9)
where R22 is an n-valent hydrocarbon group, and n is an integer of 2 or more.

US Pat. No. 10,971,754

METHOD FOR MANUFACTURING NEGATIVE ACTIVE MATERIAL, AND NEGATIVE ACTIVE MATERIAL AND LITHIUM SECONDARY BATTERY USING SAME

LG CHEM, LTD., Seoul (KR...

1. A method for preparing a negative electrode active material comprising:(a) preparing a coating composition comprising a precursor of metal-phosphorus-oxynitride;
(b) forming a precursor layer on a negative electrode active material with the coating composition of (a) using a solution process; and
(c) forming a metal-phosphorus-oxynitride protective layer on the negative electrode active material by heat treating the negative electrode active material having the precursor layer formed thereon.

US Pat. No. 10,971,753

NEGATIVE ELECTRODE FOR LITHIUM METAL BATTERY, METHOD OF PREPARING NEGATIVE ELECTRODE, AND LITHIUM METAL BATTERY INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A negative electrode for a lithium metal battery, the negative electrode comprising:a lithium metal layer comprising lithium metal or a lithium metal alloy; and
a protective layer on at least a portion of the lithium metal layer,
wherein the protective layer comprises a plurality of composite particles having a particle size of greater than about 1 micrometer to about 100 micrometers,
wherein the plurality of composite particles comprises
an organic particle comprising a polymer comprising polystyrene, a copolymer comprising a styrene repeating unit, a copolymer comprising a divinylbenzene repeating unit, or a combination thereof; and
a coating layer disposed on a surface of the organic particle, the coating layer comprising an ion conductive material,
wherein the ion conductive material comprises polyethylene glycol, polypropylene glycol, poly(ethylene glycol-co-propylene glycol-co-ethylene glycol), poly(propylene glycol-co-ethylene glycol-co-propylene glycol), polysiloxane, poly(oxyethylene)methacrylate, poly(ethylene glycol)diacrylate, poly(propylene glycol)diacrylate, poly(ethylene glycol)dimethacrylate, poly(propylene glycol)dimethacrylate, poly(ethylene glycol)urethane diacrylate, poly(ethylene glycol)urethane dimethacrylate, polyester diacrylate, polyester dimethacrylate, poly(ethylene glycol) urethane triacrylate, poly(ethylene glycol) urethane trimethacrylate, a polymer derived from trimethylolpropane triacrylate and trimethylolpropane trimethacrylate, poly(ethylene oxide) grafted poly(methyl methacrylate), poly(propylene oxide) grafted poly(methyl methacrylate), poly(butylene oxide) grafted poly(methyl methacrylate), polysiloxane grafted poly(methyl methacrylate), poly(ethylene glycol) grafted poly(methyl methacrylate), poly(propylene glycol) grafted poly(methyl methacrylate), or a combination thereof.

US Pat. No. 10,971,751

ELECTRODE ASSEMBLY

LG Chem, Ltd.

1. An electrode assembly, comprising:a cell stack part having (a) a structure in which one kind of radical unit is repeatedly disposed such that one of the one kind of radical unit is in direct contact with another one of the one kind of radical unit, the one kind of radical unit having a same number of electrodes and separators which are alternately disposed and integrally combined, or (b) a structure in which at least two kinds of radical units are disposed in a predetermined order such that one of the at least two kinds of radical units is in direct contact with another of the at least two kinds of radical units, the at least two kinds of radical units each having a same number of electrodes and separators which are alternately disposed and integrally combined;
a first fixing part and a second fixing part, each extending from a top surface of the cell stack part to a bottom surface of the cell stack part around an upper side edge of the cell stack part from which a first electrode terminal is extended for fixing the cell stack part;
a third fixing part and a fourth fixing part, each extending from the top surface of the cell stack part to the bottom surface of the cell stack part around an lower side edge of the cell stack part from which a second electrode terminal is extended for fixing the cells stack part; and
a fifth fixing part and a sixth fixing part that wrap the cell stack part by at least one full lap in a direction perpendicular to the first to fourth fixing parts,
wherein each of the first to sixth fixing parts is directly attached to an outermost separator of the cell stack part or an outermost cathode current collector of the cell stack part, the outermost separator abutting at most one electrode,
wherein all of the first to sixth parts are made of a same material,
wherein the one kind of radical unit of (a) has a four-layered structure in which a first electrode, a first separator, a second electrode and a second separator are sequentially stacked together or a repeating structure in which the four-layered structure is repeatedly stacked,
wherein each of the at least two kinds of radical units of (b) are stacked by ones in the predetermined order to form the four-layered structure or the repeating structure in which the four-layered structure is repeatedly stacked, and
wherein the first separator and the second separator comprise a coating layer having adhesive strength on one side or both sides of the first separator and the second separator.

US Pat. No. 10,971,750

MULTI-CELL TAB CUTTING APPARATUS AND METHOD THEREFOR

SK INNOVATION CO., LTD., ...

1. A multi-cell tab cutting apparatus for a plurality of stacked cells, which have a plurality of tabs formed at one side, the apparatus comprising:a base frame;
a cell fixer configured to fix cell bodies of the plurality of stacked cells so that the plurality of tabs are spaced at predetermined intervals;
at least one cell tab fixer having a plurality of fixing recesses formed at the predetermined intervals so that the plurality of tabs of the plurality of cells are inserted and fixed, respectively,
at least one cutter configured to cut the fixed plurality of the tabs while maintaining the predetermined intervals of the plurality of the tabs, and
the at least one cutter includes a cutting member having a plurality of cutting recesses, each tab of the plurality of tabs is disposed within a corresponding cutting recess and the tabs are simultaneously cut during driving of the cutting member.

US Pat. No. 10,971,749

METHOD OF AND APPARATUS FOR PRODUCING MEMBRANE ELECTRODE ASSEMBLY

HONDA MOTOR CO., LTD., T...

1. A method of producing a membrane electrode assembly including a solid polymer electrolyte membrane, a porous first electrode and a porous second electrode, the first electrode and the second electrode being joined to respective both sides of the solid polymer electrolyte membrane, the first electrode and the second electrode each including a gas diffusion layer and an electrode catalyst layer,the method comprising:
a first joining step of attracting by suction and heating the solid polymer electrolyte membrane stacked on the first electrode, through the first electrode placed on a suction/heating surface of a suction/heating plate having a suction unit and a heating unit, and then joining the first electrode to one surface of the solid polymer electrolyte membrane to thereby form a joint body; and
a second joining step of pressing and heating a stack body including the solid polymer electrolyte membrane of the joint body and the second electrode stacked together, in a stacking direction between the suction/heating surface and a heating plate, to thereby join the second electrode to another surface of the solid polymer electrolyte membrane.

US Pat. No. 10,971,748

IMPLEMENTATION OF FEEDFORWARD AND FEEDBACK CONTROL IN STATE MEDIATOR

1. A system for controlling airflow through a fuel cell circuit, comprising:a source of a gas;
a fuel cell stack having a plurality of fuel cells configured to receive the gas and generate electricity via a reaction using the gas;
a compressor located between the source of the gas and the fuel cell stack and configured to compress the gas;
an intercooler located between the source of the gas and the fuel cell stack and configured to adjust a temperature of the gas;
a valve having a valve position that affects a pressure of the gas in the fuel cell circuit and a valve area corresponding to a cross-sectional area of the valve through which the gas may flow;
a non-transitory memory programmed to store a map or function that correlates the valve area to the valve position; and
an electronic control unit (ECU) coupled to the valve and configured to:
determine or receive a desired pressure of the gas at the fuel cell stack,
determine a desired mass flow rate of the gas through the valve that will result in the pressure of the gas at the fuel cell stack reaching the desired pressure,
calculate a desired valve area to achieve the desired mass flow rate based on the desired mass flow rate,
compare the desired valve area to the map or function to determine a desired valve position that provides the desired valve area, and
control the valve to have the desired valve position.

US Pat. No. 10,971,747

FUEL CELL SYSTEM AND FUEL CELL CONTROL PROGRAM

TOKYO GAS CO., LTD., Tok...

1. A fuel cell system comprising:a first fuel cell that generates electric power using a hydrogen-containing fuel gas;
a second fuel cell that generates electric power using off-gas exhausted from the first fuel cell and containing hydrogen that has not reacted in the first fuel cell;
a first control device that controls the electric power output from the first fuel cell by adjusting a current or a voltage being output from the first fuel cell;
a second control device that controls the electric power output from the second fuel cell by adjusting a current or a voltage being output from the second fuel cell; and
an output control device that controls at least one of the first control device or the second control device such that a total electric power being generated by the first fuel cell and the second fuel cell approaches an electric power demand.

US Pat. No. 10,971,746

FUEL CELL SYSTEM FOR MODULATING OFFSET OF HYDROGEN PRESSURE SENSOR AND METHOD FOR MODULATING OFFSET OF HYDROGEN PRESSURE SENSOR

Hyundai Motor Company, S...

1. A fuel cell system for modulating an offset of a hydrogen pressure sensor, comprising:a stack including a plurality of cells, wherein each of the plurality of cells include a first electrode to which hydrogen is supplied and a second electrode to which oxygen is supplied;
the hydrogen pressure sensor configured to sense a pressure of the hydrogen supplied to the stack; and
a controller configured to:
determine whether an offset is generated in the hydrogen pressure sensor based on a first ratio of an average output voltage of the plurality of cells to a maximum value of output voltages of the plurality of cells; and
modulate the offset of the hydrogen pressure sensor when the offset is generated in the hydrogen pressure sensor.

US Pat. No. 10,971,745

CELL REVERSAL DIAGNOSTICS FOR A FUEL CELL STACK

GM Global Technology Oper...

8. A fuel cell system comprising:a fuel cell stack having a plurality of fuel cells; and
a controller having a processor in communication with the plurality of fuel cells and programmed with instructions for diagnosing a cell reversal event, wherein execution of the instructions causes the controller to:
detect the cell reversal event of one of the plurality of fuel cells;
integrate, over time, a current density of the fuel cell having the detected cell reversal event in response to detecting the cell reversal event, thereby determining an accumulated charge density; and
execute a control action with respect to the fuel cell stack when the accumulated charge density exceeds a first calibrated charge density threshold, including recording a diagnostic code, via the controller, that is indicative of severity of the cell reversal event, and continuing operation of the fuel cell stack at a reduced power capability when the accumulated charge density exceeds the first calibrated charge density threshold and is less than a second charge density threshold, and shutting off the fuel cell stack when the accumulated charge density exceeds the second charge density threshold.

US Pat. No. 10,971,744

METHOD FOR INSPECTING CURRENT LEAK OF FUEL CELL

HONDA MOTOR CO., LTD., T...

1. A method for inspecting a current leak of a fuel cell, which is provided with an anode electrode,a cathode electrode, and
an electrolyte membrane sandwiched between the anode electrode and the cathode electrode, the method comprising:
a first process in which a first voltage, which is a limit voltage of the electrolyte membrane, is applied to the fuel cell to be inspected;
a second process in which a second voltage, which is lower than the first voltage, is applied to the fuel cell after the first process;
a third process in which a third voltage, which is lower than the second voltage, is applied to the fuel cell after the second process; and
a determination process in which a value of a current flowing through the fuel cell in the third process is detected, and whether the detected current value is lower than a prescribed current value is determined.

US Pat. No. 10,971,743

SYSTEM AND METHOD FOR CONTROLLING PERFORMANCE OF FUEL CELL STACK

Hyundai Motor Company, S...

1. A controller for controlling a performance of a fuel cell stack, the controller comprising:a processor configured to execute one or more processes;
a memory configured to store the one or more processes executable by the processor, the one or more processes including:
waiting for a period of time to lapse;
once the period of time has lapsed, determining an output performance of the fuel cell stack by comparing the difference between an initial voltage and a voltage after the period of time has lapsed with the difference between the initial voltage and a preset minimum voltage;
determining whether the output performance is decreasing;
in response to the output performance decreasing, determining based on the comparison why the performance is decreasing;
executing processes to increase the performance of the fuel cell stack;
operating the fuel cell stack at an increased pressure by increasing a hydrogen pressure and an amount of air inside the fuel cell stack in accordance with the determining result;
a first re-determining step of re-performing the determining step after operating the fuel cell stack at an increased pressure for an additional period of time;
controlling the purge by increasing a purge amount of hydrogen and shortening a purge cycle of hydrogen when the difference between an initial voltage and a voltage after the period of time has lapsed is greater than the difference between the initial voltage and a preset minimum voltage in the first re-determining step;
a second re-determining step of re-performing the determining step after the purge control step; and
introducing air to a hydrogen recirculation line of the fuel cell stack when the difference between an initial voltage and a voltage after the additional period of time has lapsed is greater than the difference between the initial voltage and a preset minimum voltage in the second re-determining step,
wherein carbon monoxide in the fuel cell stack is converted into carbon dioxide by the step of introducing air to the hydrogen recirculation line.

US Pat. No. 10,971,742

FUEL CELL STATE DETERMINATION METHOD AND FUEL CELL STATE DETERMINATION APPARATUS

NISSAN MOTOR CO., LTD., ...

1. A fuel cell state determination method for determining an internal state of a fuel cell supplied with an anode gas and a cathode gas to generate electricity, comprising:detecting a decrease of a reaction resistance value of a cathode caused by hydrogen evolution reaction generated in the cathode as the fuel cell has an oxygen deficiency state;
determining the oxygen deficiency state on the basis of detection of the decrease of the reaction resistance value,
wherein the reaction resistance value of the cathode is calculated on the basis of one or more internal impedances of the fuel cell acquired on the basis of one or more frequencies belonging to a predetermined frequency band, and
the predetermined frequency band is a specific frequency band in which a difference between the reaction resistance value of the cathode during occurrence of the hydrogen evolution reaction and the reaction resistance value of the cathode during non-occurrence of the hydrogen evolution reaction becomes equal to or larger than a predetermined value; and
when the oxygen deficiency state has been determined, adjusting oxygen gas flow.

US Pat. No. 10,971,741

FUEL CELL SYSTEM

PANASONIC INTELLECTUAL PR...

1. A fuel cell system comprising:a fuel cell configured to generate power by using a fuel gas and an oxidant gas;
a fuel gas supply path configured to supply the fuel gas to an anode entrance of the fuel cell;
a recycling path configured to return anode off-gas which is discharged from an anode exit of the fuel cell to an entrance of the fuel cell;
an anode off-gas discharge path that branches from the recycling path and is configured to discharge the anode off-gas to an outside;
a first valve that is provided in the anode off-gas discharge path;
a pressurizer that is provided in the recycling path and configured to pressurize the anode off-gas which flows through the recycling path to thereby flow the anode off-gas into the fuel gas supply path; and
a controller programmed to control that controls the pressurizer to act in at least one of a timing in execution of a purge action in which the fuel gas is supplied from the fuel gas supply path and the anode off-gas is discharged to the outside in a state where the first valve is opened and a timing in prescribed time after the purge action and programmed to assess abnormality, while the control is executed, based on a pressure of the anode off-gas that flows through the recycling path or the anode off-gas discharge path, or an action amount of the pressurizer.

US Pat. No. 10,971,740

HUMIDIFIER, PLATE, DEVICE, AND MOTOR VEHICLE

Audi AG, Ingoistadt (DE)...

1. A plate made of water-permeable material, the plate comprising:webs on a flat side extending in a flow direction and delimiting a humidification channel, a distance between the webs decreasing monotonically in the flow direction; wherein a plurality of the webs delimit the humidification channel and at least one further mutually parallel humidification channel, widths of the webs monotonically increasing in the flow direction, so that cross-sectional areas of the humidification channel and the at least one further humidification channel decrease in the flow direction.

US Pat. No. 10,971,739

COMMON FLOW FIELD TYPE FUEL CELL SEPARATOR, FUEL CELL SEPARATOR ASSEMBLY, AND FUEL CELL STACK

Sejong IND. CO., LTD, Ul...

2. The fuel cell separator assembly as set forth in claim 1, wherein the sub-gasket extends around the edge of the fuel cell separator to surround the main gasket.

US Pat. No. 10,971,738

METHOD OF MANUFACTURING ELECTROLYTE MEMBRANE WITH HIGH-DURABILITY FOR FUEL CELL

Hyundai Motor Company, S...

1. A method for manufacturing an electrolyte membrane for fuel cells, the method comprising steps of:preparing a substrate;
applying a first ionomer solution onto the substrate;
inserting a porous support into the first ionomer solution to impregnate the first ionomer solution in the porous support;
allowing the first ionomer solution-impregnated porous support to stand;
applying a second ionomer solution to the first ionomer solution-impregnated porous support; and
drying the porous support,
wherein, after the porous supported is inserted into the first ionomer solution, the first ionomer solution-impregnated porous support is allowed to stand at a pressure of 0.1 to 1 atm, and
wherein the step of applying a second ionomer solution includes applying, after allowing the first ionomer solution-impregnated porous support to stand, the second ionomer solution onto the first ionomer solution-impregnated porous support, without an additional drying process.

US Pat. No. 10,971,737

FUEL CELL STACK, FUEL CELL STACK DUMMY CELL, METHOD OF PRODUCING DUMMY CELL

HONDA MOTOR CO., LTD., T...

1. A fuel cell stack comprising:a stack body comprising a plurality of power generation cells stacked together in a stacking direction, the power generation cells each including a membrane electrode assembly, a resin frame member provided around the membrane electrode assembly, and separators sandwiching the membrane electrode assembly, the membrane electrode assembly including an electrolyte membrane and electrodes provided on both sides of the electrolyte membrane, the electrodes each having a gas diffusion layer of electrically conductive porous body;
a dummy cell provided at least at one end of the stack body in the stacking direction;
wherein the dummy cell includes a dummy assembly corresponding to the membrane electrode assembly, a dummy resin frame member provided around the dummy assembly, and dummy separators sandwiching the dummy assembly;
the dummy assembly is formed by stacking together three electrically conductive porous bodies each having a different surface size; and
the three electrically conductive porous bodies are stacked to form a stepped surface at an outer marginal portion of the dummy assembly, and the dummy resin frame member is joined to the stepped surface.

US Pat. No. 10,971,736

ELECTRODE SEPARATOR STRUCTURE AND FUEL CELL APPLIED WITH THE SAME

INDUSTRIAL TECHNOLOGY RES...

1. An electrode separator structure, comprising:a conductive gas-resistant plate, having a receiving space and at least a set of an inlet port and an outlet port, wherein at least the set of the inlet port and the outlet port have passages respectively communicating the receiving space; and
a conductive porous structure, disposed in the receiving space and communicating with at least the set of the inlet port and the outlet port to form reaction gas flow paths, wherein the conductive porous structure comprises a plurality of holes laminated as at least two porous layers, and the at least two porous layers are laminated in a staggered arrangement along a direction vertical to an extending plane of the conductive porous structure such that a gas is allowed to flow along the direction vertical to the extending plane of the conductive porous structure by the staggered arrangement between the holes of different porous layers.

US Pat. No. 10,971,735

ELECTROCHEMICAL CELL AND ELECTROCHEMICAL APPARATUS

KABUSHIKI KAISHA TOSHIBA,...

1. An electrochemical cell, comprising:a solid electrolyte layer having a first face and a second face, the solid electrolyte layer having insulating property and allowing ions to move therethrough;
a first electrode being one of an anode and a cathode, the first electrode being provided on the first face, the first electrode provided with an inside channel, the first electrode including a third face, a fourth face, and an inner wall face, the channel through which gas passes, the third face into which a first open end of the channel opens, the fourth face into which a second open end of the channel opens, the inner wall face that defines the channel; and
a second electrode being the other of the anode and the cathode, the second electrode being provided on the second face, wherein
the channel includes a plurality of unit passages that have the same shape or similar shapes and communicate with one another,
the first electrode includes a plurality of unit walls that are connected to one another in three directions perpendicular to one another, include at least part of the inner wall face, and form the plurality of unit passages,
the plurality of unit passages communicate with one another in the three directions by connecting the plurality of unit walls to one another in the three directions,
the plurality of unit walls have a same shape or similar shapes and form a three-dimensional periodic minimal surface that can be connected infinitely in the three directions,
the plurality of unit walls have a gyroid shape, and
the inner wall face includes a plurality of protrusions that protrudes to inside of the channel.

US Pat. No. 10,971,734

PLANAR STRUCTURAL BODY CONTAINING FIBROUS CARBON NANOHORN AGGREGATE

NEC CORPORATION, Tokyo (...

1. A planar structural body, comprising a mixture of a fibrous carbon nanohorn aggregate and a globular aggregate of carbon nanohorn, wherein the fibrous carbon nanohorn aggregate comprises a plurality of single-walled carbon nanohorns aggregated in a fibrous state, wherein the globular aggregate of carbon nanohorn comprises at least one of seed-shaped, bud-shaped, dahlia-shaped, petal dahlia-shaped, and petal-shaped globular carbon nanohorn aggregates.

US Pat. No. 10,971,733

RAPID SULFUR MELT DIFFUSION INTO CARBON HOST FOR MAKING ELECTRODES

Drexel University, Phila...

1. A free-standing electrically conductive porous structure, consisting essentially of:an electrically conductive porous substrate with a layer of sulfur on a surface of the electrically conductive porous substrate, wherein the sulfur layer includes an additive to reduce the viscosity of melted sulfur for diffusing the melted sulfur into the substrate;
wherein at least a portion of the layer of sulfur is in pores of the substrate and located on a surface of the pores of the substrate,
the free-standing electrically conductive porous structure contains at least 50 wt.% of sulfur and less than 10 wt.% of graphene, both based on a total weight of the electrically conductive porous structure,
the additive to reduce the viscosity of melted sulfur for diffusing the sulfur into the substrate comprises an element selected from the group consisting of selenium, tellurium, bromine and iodine,
the sulfur layer contains less than 30 wt.% of a combination of the additive to reduce the viscosity of melted sulfur for diffusing the sulfur into the substrate and one or more optional additives selected from a conductive additive and an additive that prevent or reduces active material dissolution or loss into an electrolyte during device operation, and
when the porous structure is configured as a cathode for a battery, the battery including the cathode has a C rate of at least 0.2 C at a discharge capacity of from about 400 mAh g?1 to about 1675 mAh g?1 with a cycling stability of at least 100 cycles.

US Pat. No. 10,971,732

LITHIUM NEGATIVE ELECTRODE HAVING METAL FOAM AND LITHIUM SECONDARY BATTERY USING THE SAME

1. A negative electrode for a lithium secondary battery, the negative electrode comprising:a negative electrode current collector made of a metal foam having a plurality of pores; and
a lithium thin film attached to a rear surface of the negative electrode current collector,
wherein the metal foam includes: a first metal foam region having a plurality of first pores and in contact with the lithium thin film; and a second metal foam region having a plurality of second pores and being able to be in contact with a separator, the second metal foam region having a size larger than that of the first metal foam region, and
wherein the first pores are filled with a negative electrode material, and the second pores remains empty and provide a space into which a lithium agglomerate is capable of being accommodated when a lithium secondary battery is charged or discharged.

US Pat. No. 10,971,731

ELECTRODE CURRENT COLLECTOR INCLUDING ALUMINUM OXIDE LAYER HAVING ALUMINUM-FLUORIDE BOND, ALL SOLID STATE BATTERY, AND METHOD FOR PRODUCING

TOYOTA JIDOSHA KABUSHIKI ...

1. An electrode current collector to be used in an all solid state battery, the electrode current collector comprising in the following layer order:a current collecting layer, an aluminum oxide layer, and a coating layer containing a conductive material, a resin, and an inorganic filler; and
an Al—F bond is present in the aluminum oxide layer, wherein F elements are present inside the coating layer, and the F element has a strength whose maximum value in the aluminum oxide layer is 2 times or more of an average value of the strength of the F elements inside the coating layer.

US Pat. No. 10,971,730

ELECTRODES, COMPOSITIONS, AND DEVICES HAVING HIGH STRUCTURE CARBON BLACKS

Cabot Corporation, Bosto...

1. Carbon black particles having (a) a Brunauer-Emmett-Teller (BET) surface area ranging from 70 to 120 m2/g; (b) an oil absorption number (OAN) ranging from 180 to 310 mL/100 g; (c) a surface energy less than or equal to 15 mJ/m2; and (d) either an La crystallite size less than or equal to 29 ?, or a primary particle size less than or equal to 24 nm.

US Pat. No. 10,971,729

HIGH PERFORMANCE ELECTRODES

CORNELL UNIVERSITY, Itha...

1. A process for manufacturing an electrode directly on a conductive substrate, the electrode comprises a film comprising (a) a plurality of nanostructured inclusions comprising an active material and (b) a first graphenic component comprising a first graphenic web, wherein the nanostructured inclusions are wrapped within the first graphenic web; the process comprising:a. producing an electrostatically charged plume comprising a plurality of nanoscale particles and/or droplets from a fluid stock by:
i. providing the fluid stock to a first inlet of a first conduit of an electrospray nozzle, the first conduit being enclosed along the length of the conduit by a wall having an interior surface and an exterior surface, the first conduit having a first outlet, and the fluid stock comprising a nanostructured inclusion comprising an active material, a graphene oxide, and water, the graphene oxide containing a sulfur atom or sulfur containing compound;
ii. providing a pressurized gas to a second inlet of a second conduit of the nozzle, thereby providing high velocity gas at a second outlet of the second conduit, the high velocity gas having a velocity of about 5 m/s or more, the second conduit being enclosed along the length of the conduit by a second wall having an interior surface, the second conduit having a second inlet and a second outlet, the second conduit having a second diameter, and the first conduit being positioned inside the second conduit, the exterior surface of the first wall and the interior surface of the second wall being separated by a conduit gap; and
iii. providing a voltage to the nozzle, the voltage providing an electric field; and
b. collecting a deposition on the substrate, the deposition comprising (a) a nanostructured inclusion comprising an active material and (b) a second graphenic component, the first and second graphenic components being the same or different.

US Pat. No. 10,971,728

AQUEOUS LITHIUM ION SECONDARY BATTERY, METHOD FOR PRODUCING ANODE ACTIVE MATERIAL COMPOSITE, AND METHOD FOR PRODUCING AQUEOUS LITHIUM ION SECONDARY BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A method for producing an aqueous lithium ion secondary battery, the method comprising:producing an anode active material composite by: mixing a carbon-based anode active material and polytetrafluoroethylene to obtain a mixture; and heating the mixture at a temperature of no less than a glass transition temperature and lower than a vaporization temperature of the polytetrafluoroethylene to obtain a composite of the carbon-based anode active material and the polytetrafluoroethylene as the anode active material composite;
producing an anode comprising the anode active material composite;
producing a cathode;
producing an aqueous electrolyte solution;
storing the anode, the cathode, and the aqueous electrolyte solution in a battery case; and
after said storing of the anode, the cathode, and the aqueous electrolyte solution in the battery case, to configure the battery, performing charge and discharge at potentials higher than that at which the aqueous electrolyte solution decomposes to generate hydrogen and at which an electrolyte contained in the aqueous electrolyte solution decomposes to form a SEI.

US Pat. No. 10,971,727

SOLVATED GRAPHENE FRAMEWORKS AS HIGH-PERFORMANCE ANODES FOR LITHIUM-ION BATTERIES

THE REGENTS OF THE UNIVER...

1. A lithium-ion battery comprising:an anode comprising a solvated graphene framework film of interconnected graphene sheets, wherein the solvated graphene framework forms a 3-dimensional hierarchical network of pores formed between stacked and interconnected graphene sheets, and wherein the basal planes of the graphene sheets comprise nanopores;
a cathode; and
an electrolyte disposed between the anode and the cathode and including lithium ions,
wherein the solvated graphene framework of the anode is infiltrated by the electrolyte, and wherein the solvated graphene framework film has a specific surface area of 600 m2 g?1 or more.

US Pat. No. 10,971,726

LITHIUM ION SECONDARY BATTERY AND METHOD FOR MANUFACTURING LITHIUM ION SECONDARY BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A lithium ion secondary battery comprising a positive electrode, a negative electrode, and a separator, whereinthe positive electrode at least includes a positive electrode composite layer containing a positive electrode active material,
the negative electrode at least includes a negative electrode composite material layer containing a negative electrode active material,
a whole of the positive electrode composite layer and a portion of the negative electrode composite material layer face each other with the separator being interposed between the positive electrode composite layer and the negative electrode composite material layer,
the negative electrode composite material layer includes at least one first region and a second region,
the first region is a region that does not face the positive electrode composite layer and that extends from a position facing one end portion of the positive electrode composite layer to a point separated from the position by more than or equal to 0.1 mm and less than or equal to 10 mm,
the second region is a region other than the first region, wherein the second region faces the positive electrode composite layer,
the first region includes, as the negative electrode active material, silicon oxide doped with lithium, and
the second region includes, as the negative electrode active material, silicon oxide that is not doped with lithium.

US Pat. No. 10,971,725

LITHIUM METAL SECONDARY BATTERY CONTAINING ELASTIC POLYMER FOAM AS AN ANODE-PROTECTING LAYER

Global Graphene Group, In...

1. A lithium metal secondary battery comprising a cathode, an anode, an electrolyte-separator assembly disposed between said cathode and said anode, wherein said anode comprises:a) an anode active material layer containing a layer of lithium or lithium alloy, in a form of a foil, coating, or multiple particles aggregated together, as an anode active material, wherein said anode active material layer is optionally supported by an anode current collector; and
b) an anode-protecting layer in physical contact with said anode active material layer and in ionic contact with said electrolyte-separator assembly, wherein said anode-protecting layer has a thickness from 10 nm to 500 ?m and comprises an elastic polymer foam having a fully recoverable compressive elastic strain from 2% to 500% and pores having a pore volume fraction from 5% to 95% based on the polymer foam volume and wherein said pores contain interconnected pores, wherein the anode-protecting layer reduces or eliminates reactions between the lithium metal and the electrolyte;
wherein said battery does not include lithium-sulfur battery or lithium-selenium battery.

US Pat. No. 10,971,724

METHOD OF PRODUCING ELECTROCHEMICALLY STABLE ANODE PARTICULATES FOR LITHIUM SECONDARY BATTERIES

Global Graphene Group, In...

1. A method of producing a powder mass of multiple particulates for an anode of a lithium battery, the method comprising:a) dispersing an electrically conducting material, multiple porous primary particles of an anode active material, an optional electron-conducting material, and a sacrificial material in a liquid medium to form a precursor mixture or a multi-component suspension or slurry;
b) forming the precursor mixture into droplets and drying the droplets into multiple particulates wherein at least one of the particulates comprises particles of the carbonaceous or graphitic material, multiple porous primary particles of the anode active material, the optional electron-conducting material, and the sacrificial material; and
c) removing the sacrificial material or thermally converting the sacrificial material into a carbon material that is bonded to at least one of the porous primary particles of the anode active material to obtain multiple particulates;wherein at least a particulate comprises a core and a thin encapsulating layer encapsulating said core, wherein said core comprises a plurality of porous primary particles of said anode active material having a pore volume Vpp and a solid volume Va, an electron-conducting material as a non-porous matrix, binder or filler material occupying from 0% to 50% by weight of said particulate weight, and additional pores having a pore volume Vp between primary particles and the encapsulating layer, wherein said core does not contain a carbon foam or porous carbon matrix, and said thin encapsulating layer comprises an electrically conducting material and has a thickness from 1 nm to 10 ?m, an electric conductivity from 10?6 S/cm to 20,000 S/cm and a lithium ion conductivity from 10?8 S/cm to 5×10?2 S/cm and wherein the particulate has a volume ratio Vp/Va from 0.1/1.0 to 10/1.0 or a total pore-to-solid ratio (Vp+Vpp)/Va from 0.3/1.0 to 20/1.0, and said plurality of primary particles are themselves porous having a free space in a form of surface pores and/or internal pores to expand into without straining said thin encapsulating layer when said battery is charged.

US Pat. No. 10,971,723

PROCESS FOR ALKALI METAL-SELENIUM SECONDARY BATTERY CONTAINING A CATHODE OF ENCAPSULATED SELENIUM PARTICLES

Global Graphene Group, In...

1. A method of manufacturing a rechargeable alkali metal-selenium cell, said method comprising:(a) providing a cathode and an optional cathode current collector to support said cathode;
(b) providing an alkali metal anode and an optional anode current collector to support said anode; and
(c) combining the anode and the cathode and adding an electrolyte in contact with the anode and the cathode to form said alkali metal-selenium cell;
wherein said cathode contains multiple particulates of a selenium-containing material selected from selenium, a selenium-carbon hybrid, selenium-graphite hybrid, selenium-graphene hybrid, conducting polymer-selenium hybrid, a metal selenide, a Se alloy or mixture with Sn, Sb, Bi, S, or Te, a selenium compound, or a combination thereof and wherein at least one of said particulates comprises one or a plurality of said selenium-containing material particles being embraced or encapsulated by a thin layer of an elastomer having a recoverable tensile strain from 5% to 1000% when measured without an additive or reinforcement being present in said elastomer, a lithium ion conductivity no less than 10?7 S/cm at room temperature, and a thickness from 0.5 nm to 10 ?m.

US Pat. No. 10,971,722

METHOD OF MANUFACTURING CONDUCTING ELASTOMER COMPOSITE-ENCAPSULATED PARTICLES OF ANODE ACTIVE MATERIALS FOR LITHIUM BATTERIES

Global Graphene Group, In...

1. A method of producing a powder mass of an anode active material for a lithium battery, the method comprising: (a) mixing graphene sheets and a sulfonated elastomer or its precursor in a liquid medium or solvent to form a suspension; (b) dispersing a plurality of particles of an anode active material in the suspension to form a slurry; and (c) dispensing the slurry and removing the solvent and/or polymerizing or curing the precursor to form the powder mass, wherein the powder mass comprises multiple particulates of the anode active material, wherein at least one of the particulates is composed of one or a plurality of the anode active material particles which are encapsulated by a thin layer of a sulfonated elastomer/graphene composite having from 0.01% to 50% by weight of graphene sheets dispersed in said sulfonated elastomer matrix material based on the total weight of the graphene/elastomer composite, and wherein the encapsulating thin layer of sulfonated elastomer/graphene composite has a thickness from 1 nm to 10 ?m, a fully recoverable tensile strain from 2% to 500%, a lithium ion conductivity from 10?7 S/cm to 5×10?2 S/cm and an electrical conductivity from 10?7 S/cm to 100 S/cm when measured at room temperature, wherein said step of mixing the graphene sheets and the sulfonated elastomer or its precursor includes a procedure of chemically bonding the sulfonated elastomer or its precursor to the graphene sheets.

US Pat. No. 10,971,721

LITHIUM BATTERY ANODE MATERIAL AND METHOD OF MANUFACTURING THE SAME

AUO Crystal Corporation, ...

1. A lithium battery anode material, comprising:a graphite material; and
a composite material mixed with the graphite material to form a plurality of spherical structures, wherein the composite material comprises:
a silicon material, wherein a plurality of crystals are grown on a surface of the silicon material, and the crystals comprises silicon carbide;
an agglomerate comprising metal silicide; and
a plurality of protrusions distributed on a surface of the agglomerate, wherein the protrusions comprise silicon and metal.

US Pat. No. 10,971,720

POSITIVE ELECTRODE ACTIVE MATERIAL, LITHIUM ION SECONDARY BATTERY, AND METHOD OF PRODUCING POSITIVE ELECTRODE ACTIVE MATERIAL

Toyota Jidosha Kabushiki ...

1. A positive electrode active material comprising:secondary particles, wherein the secondary particles include a plurality of primary particles, the primary particles are a lithium-containing composite metal oxide, inside the secondary particles, an electron conducting oxide is disposed at substantially an entire grain boundary between the primary particles inside the secondary particle, and the electron conducting oxide has a perovskite structure and is represented by Formula (I): ACox1Mx2O3, wherein in the formula, A is at least one of La and Sr, M is at least one of Mn and Ni, and x1 and x2 satisfy 0

US Pat. No. 10,971,719

METHOD FOR MANUFACTURING A BATTERY ELECTRODE WITH DISCONTINUOUS INK COATING

1. Method of manufacturing at least one electrode for a battery with a discontinuous ink coating, said electrode comprising a metal foil coated with a plurality of ink zones at a spacing from each other along a longitudinal direction of the electrode on at least one of its two opposite surfaces, the method comprising the following steps:make ink zones on a first longitudinal segment of a metallic support wider than the foil of the electrode to be manufactured, and make at least one additional ink zone on at least one second longitudinal segment of the support offset from the first segment along a lateral direction of the support, the assembly composed of the ink zones of the first segment being laterally spaced from the assembly formed by each additional ink zone of at least one second segment directly consecutive to it along the lateral direction, the ink zones and each additional ink zone jointly forming a support coating on one of the two opposite faces of the support, such that at least one additional ink zone of a second segment laterally faces each recessed zone located between two directly consecutive ink zones of the first segment and wherein a non-zero spacing in the lateral direction is formed between the ink zones and each additional ink zone;
calendering of the metallic support provided with its coating, by movement between the calendering rolls along a longitudinal direction of the support orthogonal to its lateral direction, the calendering roll located on the side of the support coating being permanently in contact with this coating during calendering; and
separation of the segments so as to obtain the electrode through the first segment, and at least one other electrode through at least one of the second segments.

US Pat. No. 10,971,717

POSITIVE ELECTRODE ACTIVE MATERIAL, POSITIVE ELECTRODE, AND LITHIUM ION SECONDARY BATTERY

TDK CORPORATION, Tokyo (...

1. A positive electrode active material comprising:a lithium complex oxide expressed by chemical formula (1);
a highly thermal conductive compound; and
graphene or multilayer graphene,
the chemical formula (1) being
LixM1yM21-yO2  (1)where M1 is at least one metal selected from Ni, Co, and Mn, M2 is at least one metal selected from the group consisting of Al, Fe, Ti, Mg, Cu, Ga, Zn, Sn, B, V, Ca, and Sr, and x and y are numbers such that 0.05?x?1.2 and 0.3?y?1,wherein the highly thermal conductive compound is at least one selected from the group consisting of AN, BN, Si3N4, ZrN, VN, Cr2N, SiC, ZrC, Mo2C, Cr3C2, TiB2, ZrB2, VB2, and NbB2,
wherein the lithium complex oxide is coated with a coating layer, and
the coating layer includes the highly thermal conductive compound.

US Pat. No. 10,971,716

ELECTRODE UNIT AND METHOD FOR MANUFACTURING THE SAME

LG Chem, Ltd.

1. A method for manufacturing an electrode unit comprising a positive electrode, a negative electrode, and a separator, the method comprising:a selection step of selecting a positive electrode collector provided in a positive electrode and a negative electrode collector provided in a negative electrode, the positive electrode collector comprising aluminum and the negative electrode collector comprising copper;
a coating step of applying an active material to each of the positive and negative electrode collectors selected in the selection step; and
a bonding step of applying heat to bond the positive electrode, the separator, and the negative electrode to each other,
wherein, in the selection step, a stress applied to the inside of each of the positive electrode collector and the negative electrode collector due to cooling of the electrode unit after the electrode unit is manufactured is calculated to reflect the calculated results, thereby selecting the positive electrode collector and the negative electrode collector,
wherein, in the selection step, the positive electrode collector and the negative electrode collector are selected so that a ratio of a thickness of the positive electrode collector to a thickness of the negative electrode collector is 1.8:1 to 3.1:1, and
wherein, in the selection step, the stress applied to the inside of each of the positive electrode collector and the negative electrode collector is calculated according to the following two equations:

wherein A is an average of Aal and Acu.

US Pat. No. 10,971,715

SEALED BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A sealed battery comprising:an electrode assembly including a positive-electrode current collecting portion and a negative-electrode current collecting portion;
a battery case enclosing the electrode assembly;
a positive electrode terminal attached to the battery case;
a first conductive path connecting the positive-electrode current collecting portion and the positive electrode terminal;
a negative electrode terminal attached to the battery case;
a second conductive path connecting the negative-electrode current collecting portion and the negative electrode terminal;
a partition disposed in the battery case and dividing an interior space of the battery case into a first space enclosing the electrode assembly and a second space being independent from the first space, wherein the partition comprises a partition wall defining the second space, wherein the partition is a separate structure from the electrode assembly;
a first electrolyte solution enclosed in the first space;
a second electrolyte solution enclosed in the second space and containing an addition agent generating a gas when a predetermined voltage is applied to the second electrolyte solution; and
a current interrupt mechanism including the partition wall defining the second space, the partition wall including a current path portion serving as a current path of the sealed battery, the current interrupt mechanism interrupting the current path in response to an internal pressure of the second space that is higher than a predetermined pressure; wherein:
one of the first conductive path and the second conductive path passes through the current path of the current interrupt mechanism, and is in contact with the second electrolyte solution enclosed in the second space; and
the other one of the conductive paths includes a current application line that is wired to the second electrolyte solution of the second space.

US Pat. No. 10,971,714

BATTERY PACK AND A PRE-ASSEMBLED ELECTRICAL CONNECTION UNIT FOR THE BATTERY PACK

GM Global Technology Oper...

1. A pre-assembled electrical connection unit for a battery pack, the unit comprising:a bus bar defining a hole;
a cage defining a cavity;
a fastener disposed in the cavity and the cage surrounds the fastener;
wherein the cage is secured to the bus bar, and the fastener is in an initial position which positions the fastener in the hole of the bus bar and the cavity of the cage;
wherein the fastener is movable from the initial position to a final position relative to the cage which positions the fastener deeper in the hole of the bus bar; and
wherein the cage includes a first flange and a second flange that each protrude outwardly into the cavity in an orientation different from each other.

US Pat. No. 10,971,713

ELECTRIC STORAGE DEVICE AND SPACER

GS YUASA INTERNATIONAL LT...

1. An electric storage device, comprising:an electrode assembly including a positive electrode plate and a negative electrode plate that are insulated from each other;
a pair of current collectors, each of which includes a connecting portion and is connected to a corresponding one of the positive electrode plate and the negative electrode plate at the connecting portion;
a case that houses the electrode assembly and the pair of current collectors, the electrode assembly being supported by the pair of current collectors in the case;
a cover plate which covers a top surface of the case, the cover plate extending above an upper surface of the electrode assembly; and
a distance retaining member that retains a distance between portions more distal than respective connecting portions of the pair of current collectors,
wherein each connecting portion includes an outer face that faces an inner surface of the case and an inner face that faces the electrode assembly,
wherein the distance retaining member comprises a spacer that connects the pair of current collectors in the case while supporting inner faces of the current collectors,
wherein the spacer includes:
a first coupler including a first support face that faces the inner surface of the case and abuts the inner face of the current collector of one of the pair of current collectors, and a second support face that faces the electrode assembly and abuts an outer face of the current collector of said one of the pair of current collectors;
a second coupler including a third support face that faces the inner surface of the case and abuts the inner face of the current collector of an other of the pair of current collectors, and a fourth support face that faces the electrode assembly and abuts an outer face of the current collector of the other one of the pair of current collectors; and
a bridge portion connecting the first coupler with the second coupler, a bottom surface of the bridge portion extending below a bottom surface of the electrode assembly,
wherein the first support face protrudes from the distance retaining member in a perpendicular direction to a longitudinal direction of an extension of the electrode assembly,
wherein the spacer is electrically insulating, and
wherein the first support face continuously extends from the bottom surface of the bridge portion.

US Pat. No. 10,971,712

SEPARATOR INCLUDING THERMOPLASTIC RESIN AND METAL HYDROXIDE PARTICLES, NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY, AND METHOD OF MANUFACTURING SEPARATOR

TOYOTA JIDOSHA KABUSHIKI ...

1. A separator for a non-aqueous electrolyte secondary battery comprising:at least a porous film,
the porous film containing a resin composition, and
the resin composition containing a first thermoplastic resin and metal hydroxide particles,
wherein the metal hydroxide particles are at least one type selected from the group consisting of nickel hydroxide particles and zinc hydroxide particles,
the first thermoplastic resin is a polyolefin resin, and
a content of the metal hydroxide particles is not smaller than 1 part by volume and not greater than 60 parts by volume with respect to 100 parts by volume of the thermoplastic resin.

US Pat. No. 10,971,711

SEPARATOR AND NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A separator for a battery, comprising:a porous film and a columnar filler, wherein
the porous film is made of resin,
the columnar filler is made of insulating ceramic,
the columnar filler is filled in the porous film,
an axial direction of the columnar filler is in line with a thickness direction of the porous film,
the separator has a piercing stretch of 180% or more, and
in a radial cross section of the columnar filler, a ratio of a maximum radial diameter of the columnar filler to a minimum radial diameter of the columnar filler is 1 or more to 2 or less.

US Pat. No. 10,971,710

ALL-SOLID BATTERY AND METHOD OF MANUFACTURING THE SAME

Hyundai Motor Company, S...

1. A method of manufacturing an all-solid battery, comprising steps of:forming a cathode layer;
forming an anode layer;
forming an electrolyte layer between the cathode layer and the anode layer; and
forming an insulation layer using a baroplastic polymer which comprises a mixture of at least two at an edge portion of the battery,
wherein the step of forming the insulation layer comprises:
forming a coating layer through coating of the edge portion of the battery with the baroplastic polymer; and
shaping the baroplastic polymer through pressing of the coating layer,
wherein the coating layer includes a composite comprising the baroplastic polymer in combination with at least one selected from among a cathode material, an anode material, or an all-solid electrolyte.

US Pat. No. 10,971,709

BATTERY ELECTRODE PLATE REINFORCEMENT MAT HAVING IMPROVED WETTABILITY CHARACTERISTICS AND METHODS OF USE THEREFOR

Johns Manville, Denver, ...

1. A method of manufacturing a nonwoven fiber mat for reinforcing a plate or electrode of a lead-acid battery, the method comprising:providing a plurality of glass fibers;
applying a binder mixture to the plurality of glass fibers to couple the plurality of glass fibers together to form the nonwoven fiber mat so as to exhibit a loss on ignition (LOI) of up to about 20%, the binder mixture comprising an acid resistant binder that bonds the plurality of glass fibers and a poly acrylic acid based binder that increases the wettability of the nonwoven fiber mat such that the nonwoven fiber mat has or exhibits an average water wick height of at least 0.5 cm after exposure to water for 10 minutes conducted according to method IS08787; and
exposing the nonwoven fiber mat to an acid solution to dissolve at least some of the poly acrylic acid based binder, wherein a portion of the nonwoven fiber mat is lost due to dissolving of the at least some of the poly acrylic acid based binder.

US Pat. No. 10,971,708

RELEASE LAYER FOR PREPARATION OF ION CONDUCTING MEMBRANES

International Business Ma...

1. A method comprising:applying to a substrate a solution comprising a polymeric compound, thereby forming a release layer on the substrate, wherein the release layer is not an adhesive material;
applying ion-conducting elements on the release layer;
applying a matrix polymer on the release layer, wherein the matrix polymer surrounds at least some of the ion-conducting elements; and
removing the release layer to separate the matrix polymer from the substrate, such that the ion-conducting elements remain embedded in a carrier layer of the matrix polymer and form an ion-conducting membrane.

US Pat. No. 10,971,707

LAMINATED ALL-SOLID-STATE BATTERY INCLUDING A FILLER

TOYOTA JIDOSHA KABUSHIKI ...

1. A laminated all-solid-state battery, comprising:a casing composed of a laminated film;
an all-solid-state battery laminate housed in the casing, having a plurality of all-solid-state unit cells, wherein each all-solid-state unit cell is obtained by laminating a negative electrode current collector layer having a negative electrode current collector tab, a negative electrode active material layer, a solid electrolyte layer, a positive electrode active material layer and a positive electrode current collector layer having a positive electrode current collector tab in this order,
wherein the all-solid-state battery laminate includes edges in a planar direction, wherein the edges in the planar direction encompass: the negative electrode current collector tabs and the positive electrode current collector tabs, and edges of the negative electrode current collector layers, the negative electrode active material layers, the solid electrolyte layers, the positive electrode active material layers and the positive electrode current collector layers,
an injectable filler housed in the casing;
wherein the injectable filler is configured to reach the edges in the planar direction so as to be located between the edges in the planar direction of the all-solid-state battery laminate and the laminated film and the injectable filler is configured to inhibit deformation of the edges in the planar direction; and
wherein the all-solid-state battery laminate contacts the laminated film in a direction of lamination, and
wherein a viscosity, after curing, of the injectable filler is 100,000 cps-300,000 cps at a temperature of 25° C. during use of the all-solid-state battery.

US Pat. No. 10,971,706

ELECTRODE ASSEMBLY

NINGDE AMPEREX TECHNOLOGY...

1. An electrode assembly, comprising:a cell; and
a protective layer;
wherein the cell comprises a cell body and an electrode tab protruding from the cell body;
wherein in a height direction of the cell, at least one end of the protective layer extends beyond an anode electrode, and the extended dimension is no more than 3 mm; and
wherein the protective layer comprises a first binding sub-layer and an isolation sub-layer which are laminated, and the protective layer is bound to the cell through the first binding sub-layer.

US Pat. No. 10,971,705

POUCH FOR SECONDARY BATTERY AND DIE FOR FORMING THE SAME

LG Chem, Ltd.

1. A pouch for a secondary battery, comprising:a lower accommodation part accommodating an electrode assembly therein;
an upper accommodation part covering an opening of the lower accommodation part; and
a bridge part connecting the lower accommodation part to the upper accommodation part,
wherein, when the lower accommodation part and the upper accommodation part are unfolded, the bridge part has a U-shape cross section, and a height of the bridge part, which is measured from a bottom surface of the lower accommodation part, is lower than a height of the lower accommodation part, which is measured from the bottom surface of the lower accommodation part,
wherein a height (h1) corresponding to a length measured from the bottom of the accommodation part to the bridge part is 0.1 mm to 1.5 mm, and a depth (h2) of the bridge part is from 0.03 mm to 0.1 mm.

US Pat. No. 10,971,704

DISPLAY PANEL AND DISPLAY DEVICE

HKC CORPORATION LIMITED, ...

1. A display panel, comprising:a substrate;
active switches disposed on the substrate; and
an active layer disposed on the active switches;
wherein a light-obstructing layer is disposed between the substrate and the active layer, the light-obstructing layer is provided with a light-permeable region, orthogonal projection areas of the light-permeable region and the active layer on the substrate correspond to each other, and the light-permeable region defines pixels of the display panel; a buffer layer and a passivation layer are disposed on and cover the substrate, an interlayer dielectric layer is disposed between the buffer layer and the passivation layer, a planarization layer is disposed between the passivation layer and the active layer, the active layer comprises a light-emitting device, and the light-obstructing layer corrects light rays of the light-emitting device; the light-emitting device is a color organic light-emitting diode; the light-obstructing layer is also disposed between orthogonal projections of a source and a drain of the active switch on the substrate, and the light-obstructing layer is disposed on the substrate and filled into a spacing gap between the orthogonal projections of the source and the drain on the substrate,
wherein a transparent anode is disposed between the active layer and the planarization layer and an upper surface of the active layer is provided with a metal cathode.

US Pat. No. 10,971,703

LIGHT-EMITTING DEVICE HAVING INTERMEDIATE LAYER LOCATED OVER INTERCONNECT

PIONEER CORPORATION, Tok...

1. A light-emitting device comprising:a light-transmitting substrate;
a light-transmitting interconnect positioned over the substrate;
an insulating layer positioned over the substrate and the interconnect; and
an intermediate layer positioned in at least a portion of a region of a lateral side of the interconnect which overlaps the insulating laver,
wherein a refractive index of the intermediate layer is between a refractive index of the interconnect and a refractive index of the insulating layer.

US Pat. No. 10,971,702

DISPLAY DEVICE HAVING A LOW REFRACTIVE INDEX LAYER AND A HIGH REFRACTIVE INDEX LAYER

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate;
a first electrode disposed on the substrate;
a pixel definition layer disposed on the substrate;
a second electrode disposed on the first electrode and the pixel definition layer;
an organic emission layer disposed between the first electrode and the second electrode;
a planarization layer disposed on the second electrode;
a low refractive index layer disposed on the planarization layer and overlapping the pixel definition layer; and
a high refractive index layer disposed on the planarization layer and overlapping the second electrode,
wherein the high refractive index layer has a higher refractive index than that of the low refractive index layer,
wherein the low refractive index layer has a tapered shape, and
wherein a taper angle ? of the low refractive index layer satisfies a following equation:

wherein n1 is a refractive index of the low refractive index layer, n2 is a refractive index of the high refractive index layer, and asind (x) represents an angle in degrees.

US Pat. No. 10,971,701

TRANSPARENT DISPLAY DEVICES AND METHODS OF MANUFACTURING TRANSPARENT DISPLAY DEVICES

Samsung Display Co., Ltd....

1. A method of manufacturing a transparent organic light emitting display device, comprising:forming a semiconductor device on a transparent base substrate;
forming an insulation layer on the transparent base substrate to cover the semiconductor device;
forming a display structure on the insulation layer, the display structure being electrically connected to the semiconductor device;
forming an encapsulation layer covering the display structure; and
forming a protection layer including an adhesion film containing a blue dye and a protection film containing a blue dye on the encapsulation layer,
wherein the blue dye is distributed in both of the adhesion film and the protection film to overlap the entire transparent base substrate, and
wherein the transparent base substrate is a colored polymer substrate having a yellow color.

US Pat. No. 10,971,700

ORGANIC LIGHT EMITTING DIODE DISPLAY

LG DISPLAY CO., LTD., Se...

1. An organic light emitting diode display comprising:a substrate including a thin film transistor region in which a thin film transistor and an organic light emitting diode connected to the thin film transistor are disposed, and an auxiliary electrode region in which an auxiliary electrode is disposed;
a passivation layer disposed on the auxiliary electrode and exposing at least a portion of the auxiliary electrode;
a dummy pattern disposed on the passivation layer, the dummy pattern including a protrusion protruding more than the passivation layer in an area overlapping with the auxiliary electrode;
a cathode included in the organic light emitting diode, divided by the protrusion, and exposing at least a portion of the auxiliary electrode, an end of the cathode being in direct contact with the auxiliary electrode;
a cover layer disposed on the cathode, and having continuity to cover the protrusion and the auxiliary electrode; and
a protective layer interposed between the cathode and the cover layer,
wherein the cover layer contacts a side of the passivation layer in a location under the protrusion of the dummy pattern, and
wherein the cover layer is an electrical insulator.

US Pat. No. 10,971,699

DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A display panel comprising:a first substrate and a second substrate, each including a display area and a peripheral area in a plan view; and
a sealing portion disposed between the first substrate and the second substrate,
wherein
an edge of the display panel comprises a straight-lined edge and a shaped edge in the plan view,
the shaped edge comprises a curved portion in the plan view,
an edge surface of the first substrate at the straight-lined edge, an edge surface of the second substrate at the straight-lined edge and an edge surface of the sealing portion at the straight-lined edge collectively define a continuous first surface,
an edge surface of the first substrate at the shaped edge, an edge surface of the second substrate at the shaped edge and an edge surface of the sealing portion at the shaped edge collectively define a continuous second surface, and
a shape of the first surface and a shape of the second surface are different from each other,
wherein the second surface comprises:
one flat surface defined by at least a part of the edge surface of the first substrate at the shaped edge, at least a part of the edge surface of the second substrate at the shaped edge and an entire part of the edge surface of the sealing portion at the shaped edge;
a first inclined surface disposed between a first main surface of the first substrate and the flat surface; and
a second inclined surface disposed between a second main surface of the second substrate and the flat surface,
wherein each of the first inclined surface and the second inclined surface is substantially flat,
wherein the first surface comprises:
one curved surface defined by at least a part of the edge surface of the first substrate at the straight-lined edge, at least a part of the edge surface of the second substrate at the straight-lined edge, and an entire part of the edge surface of the sealing portion at the straight-lined edge;
a third inclined surface disposed between the first main surface of the first substrate and the curved surface; and
a fourth inclined surface disposed between the second main surface of the second substrate and the curved surface,
wherein each of the third inclined surface and the fourth inclined surface is substantially flat.

US Pat. No. 10,971,698

OLED DISPLAY PANEL AND MANUFACTURING METHOD FOR THE SAME

WUHAN CHINA STAR OPTOELEC...

1. A manufacturing method for an OLED display panel comprising steps of:step 1: providing a packaging cover plate, wherein the packaging cover plate includes a main body, and a first light-shielding film and a second light-shielding film which are disposed on the main body; the main body is provided with one or multiple sealant coating region; the sealant coating region includes a sealant thick region, and a first sealant thin region and a second sealant thin region which are located at two sides of the sealant thick region; the first light-shielding film and the second light-shielding film are correspondingly disposed at two sides of the sealant thick region;
defining an edge of each of the first sealant thin region, the second sealant thin region, the first light-shielding film and a second light-shielding film which is closed to the sealant thick region as an inner edge, and defining an edge of each of the first sealant thin region, the second sealant thin region, the first light-shielding film and the second light-shielding film which is away from the sealant thick region as an outer edge;
wherein an inner edge of the first light-shielding film and an inner edge of the first sealant thin region are aligned; an outer edge of the first light-shielding film exceeds an outer edge of the first sealant thin region; an inner edge of the second light-shielding film and an inner edge of the second sealant region are aligned; an outer edge of the second light-shielding film exceeds an outer edge of the second sealant thin region;
the first light-shielding film includes a first semi-transparent region that is completely overlapped with the first sealant thin region and a first light-blocking region that is disposed outside the first semi-transparent region; the transmittance of the first semi-transparent region is gradually decreased along direction from the inner edge to the outer edge of the first light-shielding film;
the second light-shielding film includes a second semi-transparent region that is completely overlapped with the second sealant thin region and a second light-blocking region that is disposed inside the second semi-transparent region; the transmittance of the second semi-transparent region is gradually decreased along a direction from the inner edge to the outer edge of the second light-shielding film;
step 2: coating a sealant at the one or the multiple sealant coating regions on the packaging cover plate, and baking and curing the sealant; and
step 3: providing an OLED substrate, aligning the packaging cover plate with the OLED substrate; using a laser beam to scan the sealant from a side of the packaging cover plate so as to cure the sealant in order to obtain an OLED display panel;
wherein the first and second sealant thin regions are spaced from each other by the sealant thick region such that the inner edges of the first light-shielding film and the second light-shielding film that are respectively aligned with the inner edges of the first light-shielding film and the second light-shielding film are spaced from each other to expose a part of the main body of the packaging cover plate that corresponds to the sealant thick region, and wherein the sealant is coated such that a first portion of the sealant is coated on the sealant thick region to be directly deposited on a surface of the main body of the packaging cover plate, and a second portion of the sealant is coated on the first and second light-shielding films and is separated from the surface of the main body of the packaging cover plate.

US Pat. No. 10,971,697

LIGHT-EMITTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:a first organic insulating layer over a first substrate;
a conductive layer over the first organic insulating layer;
an anode over the first organic insulating layer;
a second organic insulating layer over the conductive layer and the anode;
a layer containing a light-emitting material over the second organic insulating layer;
a cathode over the layer containing a light-emitting material;
a second substrate over the cathode; and
a layer configured to keep a gap between the first substrate and the second substrate,
wherein the cathode overlaps a first region of the conductive layer with the second organic insulating layer therebetween,
wherein the layer configured to keep a gap between the first substrate and the second substrate overlaps the conductive layer with the second organic insulating layer therebetween, and
wherein the conductive layer comprises a plurality of openings in a second region which is not overlapped by the cathode.

US Pat. No. 10,971,696

DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A flexible display panel comprising:a substrate having an active area that display an image and a non-active area that does not display the image;
a pixel unit on a first surface of the substrate in the active area of the substrate, the pixel unit comprising a light emitting element;
an encapsulation layer on the first surface of the substrate, the encapsulation layer covering the pixel unit and disposed in both the active area the non-active area of the substrate;
a support member on a second surface of the substrate that is opposite the first surface of the substrate, the support member overlapping an edge of the encapsulation layer in the non-active area without extending to the active area of the substrate;
a printed circuit board configured to generate a plurality of data signals supplied to the flexible display panel; and
a back cover configured to overlap a rear surface of the flexible display panel, the back cover comprising:
a first portion that includes a plurality of openings, the first portion overlapping the flexible display panel without overlapping the printed circuit board; and
a second portion that lacks the plurality of openings, the second portion overlapping the printed circuit board without overlapping the first portion.

US Pat. No. 10,971,695

MULTILAYER REFLECTION ELECTRODE FILM, MULTILAYER REFLECTION ELECTRODE PATTERN, AND METHOD OF FORMING MULTILAYER REFLECTION ELECTRODE PATTERN

MITSUBISHI MATERIALS CORP...

1. A multilayer reflection electrode film comprising:a Ag film that is formed of Ag or an Ag alloy; and
a transparent conductive oxide film that is disposed on the Ag film,
wherein the transparent conductive oxide film is formed of an oxide that includes Zn and Ga and further includes one element or two or more elements selected from the group consisting of Sn, Y, and Ti, and
wherein the transparent conductive oxide film further includes Y.

US Pat. No. 10,971,694

ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An organic light emitting diode display device, comprising:a first electrode;
a first stack on the first electrode, the first stack configured to emit a first blue colored light;
a first charge generating layer on the first stack;
a second stack on the first charge generating layer, the second stack configured to emit a red colored light and a yellow-green colored light; and
a second electrode on the second stack,
wherein the second stack comprises:
a red-yellow-green emitting material layer including a yellow-green host, a yellow-green dopant and a red dopant; and
a yellow-green emitting material layer including the yellow-green host and the yellow-green dopant.

US Pat. No. 10,971,693

LIGHT EMITTING DEVICES, METHODS FOR PREPARING THE SAME, AND DISPLAY DEVICES

1. A light emitting device comprising: a cathode layer, a quantum dot light emitting layer, a hole injection layer and an anode layer,wherein the cathode layer, the quantum dot light emitting layer, the hole injection layer, and the anode layer are laminated, and
wherein the hole injection layer comprises a heterojunction interface comprising a complex metal oxide film, the complex metal oxide film comprising at least two metal oxides, the two metal oxides characterized by partial oxidation, the heterojunction interface being characterized by an improved injection capability.

US Pat. No. 10,971,692

QUANTUM DOT LIGHT-EMITTING LAYER, QUANTUM DOT LIGHT-EMITTING DEVICE AND PREPARING METHODS THEREFOR

BOE TECHNOLOGY GROUP CO.,...

1. A preparing method for a quantum dot light-emitting layer, comprising:placing a first halide AX and a second halide BX2 in a solvent;
stirring and dispersing a reaction system formed by the first halide AX, the second halide BX2 and the solvent at a set temperature for a set time period; and
cooling the reaction system at a cooling rate of 0.1° C./24 h-1° C./24 h to generate an A4BX6 single crystal thin film containing ABX3 quantum dots, and using the A4BX6 single crystal thin film containing ABX3 quantum dots as the quantum dot light-emitting layer; and
wherein A comprises one of Cs+, CH3NH3+ and HC(NH2)2+;
B comprises one of Pb2+ and Sn2+; and
X comprises one of Cl—, Br— and I—.

US Pat. No. 10,971,691

DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a plurality of light emitting elements disposed on a substrate, each of the plurality of light emitting elements including:
a first electrode disposed on the substrate,
a first semiconductor layer, an active layer and a second semiconductor layer sequentially disposed on the first electrode, the first semiconductor layer contacting a top surface of the first electrode, and
a second electrode contacting a side surface of the second semiconductor layer;
an insulating pattern disposed between the light emitting elements, the insulating pattern comprising an insulating material in direct contact with at least side surfaces of the plurality of light emitting elements and covering the at least side surfaces of the plurality of light emitting elements;
a color conversion array including a plurality of sub-color conversion parts corresponding to the respective light emitting elements, the plurality of sub-color conversion parts each converting the light into light of a specific color for each of the plurality of light emitting elements and emitting the converted light; and
a driver disposed on the substrate and electrically connected to the light emitting element,
wherein the plurality of sub-color conversion parts include first to third sub-color conversion parts that convert the light provided from corresponding light emitting elements into lights of first to third colors and emitting the converted lights, and
wherein each of the plurality of light emitting elements is electrically insulated from an adjacent light emitting element.

US Pat. No. 10,971,690

SOLAR CELLS, STRUCTURES INCLUDING ORGANOMETALLIC HALIDE PEROVSKITE MONOCRYSTALLINE FILMS, AND METHODS OF PREPARATION THEREOF

KING ABDULLAH UNIVERSITY ...

5. A device, comprising:a substrate, wherein the substrate includes one or more of indium tin oxide (ITO)-coated glass, fluoride coated tin oxide (FTO), silicon, and metal coated silicon;
an organometallic halide perovskite monocrystalline film having a (001) orientation grown on the substrate by cavitation-triggered asymmetric crystallization, wherein the organometallic halide perovskite monocrystalline includes methylammonium lead bromide (MAPbBr3); and
a metal layer disposed on the organometallic halide perovskite monocrystalline film, wherein the metal layer includes one or more of Au, Ag, and Cu.

US Pat. No. 10,971,689

TRIPHENYLENE-BASED MATERIALS FOR ORGANIC ELECTROLUMINESCENT DEVICES

Merck Patent GmbH, Darms...

1. A neutral compound of the formula (2),
where the following applies to the symbols and indices used:
Z is on each occurrence, identically or differently, CR? or N, with the proviso that a maximum of two groups Z per ring stand for N;
R is selected on each occurrence, identically or differently, from the group consisting of N(Ar1)2, C(?O)Ar1, P(?O)(Ar1)2 and an aromatic or heteroaromatic ring system having 5 to 60 aromatic ring atoms, which may in each case be substituted by one or more radicals R1;
Ar1 is on each occurrence, identically or differently, an aromatic or heteroaromatic ring system having 5 to 60 aromatic ring atoms, which is optionally substituted by one or more non-aromatic radicals R3; two radicals Ar1 here which are bonded to the same N atom or P atom may also be bridged to one another by a single bond or a bridge selected from N(R4), C(R4)2, O or S;
R1 is hydrogen;
R? is selected on each occurrence, identically or differently, from the group consisting of H or where two or more adjacent substituents R? which are bonded to the same benzene ring may optionally form a monocyclic or polycyclic, aliphatic, aromatic or heteroaromatic ring system;
R3 is selected on each occurrence, identically or differently, from the group consisting of H, D, F, Cl, Br, I, CN, NO2, N(R4)2, C(?O)Ar1, C(?O)R4, P(?O)(Ar1)2, a straight-chain alkyl, alkoxy or thioalkyl group having 1 to 40 C atoms or a branched or cyclic alkyl, alkoxy or thioalkyl group having 3 to 40 C atoms or an alkenyl or alkynyl group having 2 to 40 C atoms, where the alkyl, alkoxy, thioalkyl, alkenyl or alkynyl group is optionally substituted by one or more radicals R4, where one or more non-adjacent CH2 groups is optionally replaced by R4C?CR4, C?C, Si(R4)2, C?O, C?NR4, P(?O)(R4), SO, SO2, NR4, O, S or CONR4 and where one or more H atoms is optionally replaced by D, F, Cl, Br, I, CN or NO2, an aromatic or heteroaromatic ring system having 5 to 60 aromatic ring atoms, which may in each case be substituted by one or more radicals R4, an aryloxy or heteroaryloxy group having 5 to 60 aromatic ring atoms, which is optionally substituted by one or more radicals R4, or a combination of these systems, where two or more adjacent substituents R3 may optionally form a monocyclic or polycyclic, aliphatic, aromatic or heteroaromatic ring system, which is optionally substituted by one or more radicals R4;
R4 is selected from the group consisting of H, D, F, CN, an aliphatic hydrocarbon radical having 1 to 20 C atoms, an aromatic or heteroaromatic ring system having 5 to 30 aromatic ring atoms, in which one or more H atoms is optionally replaced by D, F, Cl, Br, I, CN or an alkyl group having 1 to 5 C atoms, where two or more adjacent substituents R4 may form a mono- or polycyclic, aliphatic, aromatic or heteroaromatic ring system with one another;
with the proviso that the following compounds are excluded from the invention:

US Pat. No. 10,971,688

ORGANIC MOLECULES FOR USE IN ORGANIC OPTOELECTRONIC DEVICES

CYNORA GMBH, Bruchsal (D...

1. An organic molecule comprising a compound represented by a structure of Formula Va-Vh:
wherein
in each occurrence Rc is independently selected from the group consisting of Me, iPr, tBu, CN, CF3, Ph, which can be respectively substituted with one or more radicals selected from Me, iPr, tBu, CN, CF3 or Ph, pyridinyl, which can be respectively substituted with one or more radicals selected from Me, iPr, tBu, CN, CF3 or Ph, pyrimidinyl, which can be respectively substituted with one or more radicals selected from Me, iPr, tBu, CN, CF3 or Ph, carbazolyl, which can be respectively substituted with one or more radicals selected from Me, iPr, tBu, CN, CF3 or Ph, triazinyl, which can be respectively substituted with one or more radicals selected from Me, iPr, tBu, CN, CF3 or Ph, and N(Ph)2.

US Pat. No. 10,971,687

ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES

UNIVERSAL DISPLAY CORPORA...

1. A compound selected from the group consisting of
wherein
at least one of RG, or at least one of RJ, of Formula II includes a structure of Formula III, wherein the structure of Formula II forms a direct bond to Formula III through a carbon of one of X21 to X24, a carbon of one of X25 to X28, or RN, or optionally, the structure of Formula II is linked to Formula III through a carbon of one of X21 to X24, a carbon of one of X25 to X28, or RN, by an aromatic linker;

Ar is selected from aryl or heteroaryl, each of which is optionally substituted;
X1 to X24 are independently selected from C or N;
L1 and L2 is selected from a direct bond or an aromatic linker;
Y1, Y2, and Y3 are independently selected from CRY or N, and at least one of Y1, Y2, or Y3 is N;
RA, RB, RC, RD, RE, RF, RG, RH, RI, and RJ represent mono to the maximum allowable substitution, or no substitution;
wherein each RY, RA, RB, RC, RD, RE, RF, RG, RH, RI, and RJ are independently hydrogen or a substituent selected from the group consisting of deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carbonyl, carboxylic acids, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof; or optionally, any two adjacent substituents of RE, RF, RG, RH, RI, and RJ join to form a fused ring; and wherein RB and RE do not comprise carbazole; and
RN is a direct bond or is independently selected from the group consisting of hydrogen, deuterium, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, and combinations thereof;
wherein the compounds of Formula I do not include compounds of the formulae

US Pat. No. 10,971,686

ORGANIC SEMICONDUCTOR ELEMENT, POLYMER, ORGANIC SEMICONDUCTOR COMPOSITION, AND ORGANIC SEMICONDUCTOR FILM

FUJIFILM Corporation, To...

1. An organic semiconductor element comprising:an organic semiconductor film that includes a polymer having a repeating unit represented by the following Formula (4) or (5),

in Formula (4) or (5),
RC3 to RC10 each independently represent a hydrogen atom, a halogen atom, an alkyl group, an alkenyl group, an alkynyl group, an aromatic hydrocarbon group, or an aromatic heterocyclic group,
XZ's each independently represent a chalcogen atom,
WZ's each independently represent a nitrogen atom or CRW,
RW represents a hydrogen atom or a substituent,
A11 and A13 each independently represent an aromatic hydrocarbon group, an aromatic heterocyclic group other than aromatic heterocyclic groups represented by the following Formulae (A-1) to (A-12), a vinylene group, or an ethynylene group,
A12 represents an aromatic heterocyclic group represented by any one of the following Formulae (A-1) to (A-12),
m11 and m13 each independently represent an integer of 0 to 4, and
m12 represents an integer of 1 to 4,

in Formulae (A-1) to (A-12),
XA's each independently represent an oxygen atom, a sulfur atom, a selenium atom, or NRX,
RN and RX each independently represent an alkyl group which may have at least one of —O—, —S—, or —NRA3— in a carbon chain or a group represented by the following Formula (1-1),
YA's each independently represent an oxygen atom or a sulfur atom,
ZA's each independently represent CRA2 or a nitrogen atom,
WA's each independently represent C(RA2)2, NRA1, a nitrogen atom, CRA2, an oxygen atom, a sulfur atom, or a selenium atom,
RA1's each independently represent an alkyl group which may have at least one of —O—, —S—, or —NRA3— in a carbon chain, a group represented by the following Formula (1-1), or a single bond,
RA2's each independently represent a hydrogen atom, a halogen atom, an alkyl group which may have at least one of —O—, —S—, or —NRA3— in a carbon chain, or a single bond,
RA3's each independently represent a hydrogen atom or a substituent, and
* represents a binding site to another group forming the repeating unit, and
*-La-Ar?Lb)l  (1-1)
in Formula (1-1),
La represents an alkylene group having 1 to 20 carbon atoms which may have at least one of —O—, —S—, or —NR1S— in a carbon chain,
Ar represents an aromatic heterocyclic group or an aromatic hydrocarbon group having 6 to 18 carbon atoms,
Lb represents an alkyl group having 1 to 100 carbon atoms which may have at least one of —O—, —S—, or —NR2S— in a carbon chain,
R1S and R2S each independently represent a hydrogen atom or a substituent,
l represents an integer of 1 to 5, and
* represents a binding site to a ring-constituting nitrogen atom in Formula (A-1) or (A-2), a nitrogen atom in NRX of XA, or a nitrogen atom in NRA1 of WA.

US Pat. No. 10,971,685

SELECTIVE DEVICE, MEMORY CELL, AND STORAGE UNIT

SONY CORPORATION, Tokyo ...

1. A selective device, comprising:a first electrode;
a second electrode that faces the first electrode;
a switch device that includes a switch layer, wherein
the switch layer is between the first electrode and the second electrode, and
the switch layer is in direct contact with the first electrode; and
a non-linear resistive device that comprises a non-linear resistive layer, wherein
the non-linear resistive layer comprises at least one of boron (B), silicon (Si), or carbon (C),
the non-linear resistive layer and the switch layer are directly stacked between the first electrode and the second electrode,
the non-linear resistive device further comprises a junction field-effect transistor,
a gate electrode of the junction field-effect transistor is independently of the second electrode, and
the second electrode corresponds to a drain electrode and a source electrode of the junction field-effect transistor.

US Pat. No. 10,971,684

INTERCALATED METAL/DIELECTRIC STRUCTURE FOR NONVOLATILE MEMORY DEVICES

Taiwan Semiconductor Manu...

1. An integrated chip including a memory device, the memory device comprising:a bottom electrode disposed over a semiconductor substrate;
an upper electrode disposed over the bottom electrode; and
an intercalated metal/dielectric structure sandwiched between the bottom electrode and the upper electrode, the intercalated metal/dielectric structure comprising a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer;
wherein the upper dielectric layer has a first width, the first metal layer has a second width greater than the first width, and the lower dielectric layer has a third width that is greater than the second width, such that the intercalated metal/dielectric structure has outermost sidewalls that are slanted continuously from the upper dielectric layer to the lower dielectric layer.

US Pat. No. 10,971,683

METHODS FOR FORMING NARROW VERTICAL PILLARS AND INTEGRATED CIRCUIT DEVICES HAVING THE SAME

Micron Technology, Inc., ...

1. A method comprising:forming a bottom electrode;
forming an upper electrode; and
forming a conductive wire extending between the bottom electrode and the upper electrode, the conductive wire disposed within an insulating region that is laterally elongated and the conductive wire extending across the width of the insulating region, wherein the insulating region is formed between a dielectric material extending laterally across the length of the insulating region, and the dielectric material is in direct physical contact with the bottom electrode and the upper electrode.

US Pat. No. 10,971,682

METHOD FOR FABRICATING MEMORY DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:depositing a resistance switching element layer over a bottom electrode layer;
depositing a top electrode layer over the resistance switching element layer;
etching the top electrode layer, the resistance switching element layer, and the bottom electrode layer to form a memory stack;
depositing a first spacer layer over the memory stack;
etching the first spacer layer to form a first spacer extending along a sidewall of the memory stack;
depositing a second spacer layer over the memory stack and the first spacer;
etching the second spacer layer to form a second spacer extending along a sidewall of the first spacer; and
depositing an etch stop layer over and in contact with a top of the second spacer such that a bottom of the etch stop layer is higher than a top of the first spacer, wherein the etch stop layer is spaced apart from the first spacer by a portion of the second spacer.

US Pat. No. 10,971,681

METHOD FOR MANUFACTURING A DATA RECORDING SYSTEM UTILIZING HETEROGENEOUS MAGNETIC TUNNEL JUNCTION TYPES IN A SINGLE CHIP

SPIN MEMORY, INC., Fremo...

1. A method for manufacturing a magnetic memory array comprising:depositing a first magnetic element material using first shadow-mask that is configured to allow deposition in a first area;
depositing a second magnetic element material using a second shadow-mask that is configured to allow deposition in a second area; and
forming a mask over the first and second magnetic element material, the mask being configured to define a plurality of magnetic element pillars in the first and second areas, and performing a material removal process to remove portions of the first and second magnetic element material not protected by the mask.

US Pat. No. 10,971,680

MULTI TERMINAL DEVICE STACK FORMATION METHODS

Spin Memory, Inc., Fremo...

1. A multi terminal fabrication process comprising:performing an initial pillar layer formation process to create layers of a multi terminal stack;
forming a first device in the layers of the multi terminal stack;
forming a second device in the layers of the multi terminal stack; and
constructing a set of terminals comprising: a first terminal coupled to the first device, a second terminal coupled to the second device, and a third terminal coupled to the first device, wherein the third terminal is a side terminal and a portion of an insulator on a sidewall of the first device or second device operates as a mask in the terminal formation process formation of the third terminal, wherein at least two terminals in the set of terminals are independent.

US Pat. No. 10,971,679

MAGNETORESISTIVE EFFECT ELEMENT

TDK CORPORATION, Tokyo (...

1. A magnetoresistive effect element comprising:a first ferromagnetic layer;
a second ferromagnetic layer; and
a nonmagnetic spacer layer provided between the first ferromagnetic layer and the second ferromagnetic layer,
wherein the nonmagnetic spacer layer comprises an Ag alloy represented by General Formula (1),
Ag?X1-?  (1)
where X indicates one element selected from the group consisting of Cu, Ga, Ge, As, Y, La, Sin, Yb, and Pt, and 0 wherein at least one of the first ferromagnetic layer and the second ferromagnetic layer comprises a Heusler alloy represented by General Formula (2),
Co2L?M?  (2)
where L is at least one or more elements of Mn and Fe, M indicates one or more elements selected from the group consisting of Si, Al, Ga, and Ge, 0.7

US Pat. No. 10,971,678

SEMICONDUCTOR DEVICE

ABLIC INC., Chiba (JP)

1. A semiconductor device, comprising:a semiconductor substrate having a first conductivity; and
a first vertical Hall element and a second vertical Hall element which are formed on the semiconductor substrate,
each of the first vertical Hall element and the second vertical Hall element comprising:
a semiconductor layer having a second conductivity formed on the semiconductor substrate;
a first drive current supply electrode, a Hall voltage output electrode, and a second drive current supply electrode each of which is formed of an impurity region having the second conductivity and having an impurity concentration higher than an impurity concentration of the semiconductor layer, and is sequentially arranged along a straight line on a surface of the semiconductor layer; and
a first electrode isolation diffusion layer having the first conductivity formed between the first drive current supply electrode and the Hall voltage output electrode, and a second electrode isolation diffusion layer having the first conductivity formed between the Hall voltage output electrode and the second drive current supply electrode,
the straight line on the first vertical Hall element and the straight line on the second vertical Hall element being parallel,
the Hall voltage output electrode having a first depth,
each of the first drive current supply electrode and the second drive current supply electrode having a second depth which is deeper than the first depth and a depth of each of the first electrode isolation diffusion layer and the second electrode isolation diffusion layer.

US Pat. No. 10,971,677

ELECTRICALLY CONTROLLED NANOMAGNET AND SPIN ORBIT TORQUE MAGNETIC RANDOM ACCESS MEMORY INCLUDING THE SAME

ACADEMIA SINICA, Taipei ...

1. An electrically controlled nanomagnet, comprising:a first spin-Hall material layer comprising a first spin-Hall material;
a second spin-Hall material layer comprising a second spin-Hall material; and
a first magnetic layer disposed between the first spin-Hall material layer and the second spin-Hall material layer,
wherein the first spin-Hall material and the second spin-Hall material are substantially mirror image to each other.

US Pat. No. 10,971,676

MAGNETORESISTIVE RANDOM ACCESS MEMORY HAVING A RING OF MAGNETIC TUNNELING JUNCTION REGION SURROUNDING AN ARRAY REGION

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate having an array region defined thereon;
a ring of magnetic tunneling junction (MTJ) region surrounding the array region, wherein the ring of MTJ region comprises a first MTJ; and
metal interconnect patterns overlapping part of the ring of MTJ region, wherein each of the metal interconnect patterns comprises a first metal interconnection connected to the first MTJ directly.

US Pat. No. 10,971,675

DUAL FUNCTION MAGNETIC TUNNEL JUNCTION PILLAR ENCAPSULATION

International Business Ma...

1. A method of forming a diffusion barrier on a pillar including a magnetic tunnel junction, comprising:obtaining a pillar having sidewalls and including a magnetic tunnel junction and metallic residue on the sidewalls;
selectively depositing a manganese layer on the sidewalls of the pillar and over the metallic residue;
forming an oxidized diffusion barrier layer on the sidewalls of the pillar from the manganese layer, and
causing oxidation of the metallic residue using oxygen within the oxidized diffusion barrier layer.

US Pat. No. 10,971,674

METHOD FOR PRODUCING COMPOSITE WAFER HAVING OXIDE SINGLE-CRYSTAL FILM

SHIN-ETSU CHEMICAL CO., L...

1. A method of producing a composite wafer having an oxide single-crystal film on a support wafer, the method comprising steps of:implanting hydrogen atom ions or hydrogen molecule ions into an oxide single-crystal wafer through a surface thereof, which wafer is a lithium tantalate or lithium niobate wafer, to form an ion-implanted layer inside the oxide single-crystal wafer;
subjecting at least one of the surface of the oxide single-crystal wafer and a surface of a support wafer to be laminated with the oxide single-crystal wafer to surface activation treatment;
after the surface activation treatment, bonding the surface of the oxide single-crystal wafer to the surface of the support wafer to obtain a laminate;
heat-treating the laminate at a temperature of 90° C. or higher at which cracking is not caused; and
applying a mechanical impact to the ion-implanted layer of the heat-treated laminate to split the laminate along the ion-implanted layer to obtain an oxide single-crystal film transferred onto the support wafer,
wherein an implantation dose of the hydrogen atom ions is from 5.0×1016 atom/cm2 to 2.75×1017 atom/cm2 and an implantation dose of the hydrogen molecule ions is from 2.5×1016 atoms/cm2 to 1.37×1017 atoms/cm2,
the support wafer is selected from the group consisting of a sapphire wafer, a silicon wafer, a silicon wafer with an oxide film and a glass wafer, and
the temperature in the step of heat-treating is from 90 to 225° C. in a case where the support wafer is the sapphire wafer, from 90° C. to 200° C. in a case where the support wafer is the silicon wafer or a silicon wafer with an oxide film, and from 90 to 110° C. in a case where the support wafer is the glass wafer.

US Pat. No. 10,971,673

PIEZOELECTRIC ELEMENT, PIEZOELECTRIC DEVICE, ULTRASONIC PROBE AND ELECTRONIC APPARATUS

Seiko Epson Corporation, ...

1. A piezoelectric element comprising:a first electrode layer;
a piezoelectric layer stacked on the first electrode layer;
a second electrode layer stacked on the piezoelectric layer, the second electrode layer having a first layer and a second layer, the second layer being stacked on the first layer, the first layer including first metal, the a second layer including second metal;
a third electrode layer stacked on a part of the second electrode layer, the third electrode layer including third metal; and
an insulating layer on the second electrode layer and covering at least a part of the piezoelectric layer that is not provided with the second electrode layer, the insulating layer having an aperture exposing apart of the second electrode layer,
wherein the second layer of the second electrode layer is exposed in the aperture, and
a difference in standard redox potential between the second metal and the third metal is smaller than a difference in standard redox potential between the first metal and the third metal.

US Pat. No. 10,971,672

QUANTUM DEVICE WITH MODULAR QUANTUM BUILDING BLOCKS

INTERNATIONAL BUSINESS MA...

1. A device, comprising:a plurality of substrates, each of the plurality of substrates having a plurality of qubit pockets, wherein at least one qubit pocket of the plurality of qubit pockets is provided with a qubit of a plurality of qubits in the respective plurality of qubit pockets;
a plurality of connectors directly connected between at least two of the plurality of substrates and positioned around an edge of the at least two of the plurality of substrates, the plurality of connectors comprising respective connecting elements, wherein each of the respective connecting elements directly connects the at least two of the plurality of substrates; and
a plurality of transmission lines formed on the substrate and connected to at least one connector of the plurality of connectors and to at least one qubit pocket of the plurality of qubit pockets, and wherein the plurality of substrates are separate from one another rendering the device a modular quantum device in which the qubit is separately replaceable from other ones of the plurality of qubits without replacement of the entire device.

US Pat. No. 10,971,671

THERMOELECTRIC CONVERSION MODULE AND VEHICLE INCLUDING THE SAME

Hyundai Motor Company, S...

1. A thermoelectric conversion module comprising:a plurality of n type thermoelectric conversion materials and a plurality of p type thermoelectric conversion materials that are disposed alternately; and
a plurality of electrodes configured to connect the plurality of thermoelectric conversion materials disposed alternately at low temperature side end portions and a central portion of the plurality of thermoelectric conversion materials alternately, and
wherein the plurality of electrodes includes:
a first electrode configured to penetrate a central portion of an n type thermoelectric conversion material and a central portion of a p type thermoelectric conversion material that are adjacent to each other to form a radial thermal gradient in the plurality of thermoelectric conversion materials by transferring heat obtained from a heat source to the plurality of thermoelectric conversion materials, and
wherein the first electrode is further configured to protrude towards a pipe, through which a heat transfer fluid flows, with respect to high temperature side end portions of the plurality of thermoelectric conversion materials such that the first electrode is inserted into a through-hole formed at the pipe to obtain the heat while directly contacting with the heat transfer fluid and to transfer the obtained heat to the plurality of thermoelectric conversion materials.

US Pat. No. 10,971,670

THERMOELECTRIC CONVERSION DEVICE

NIPPON THERMOSTAT CO., LT...

1. A thermoelectric conversion device comprising:a plurality of first electrodes;
a plurality of thermoelectric conversion elements, each having one end electrically connected to each of the first electrodes;
a plurality of second electrodes, to which another end of each of the thermoelectric conversion elements is electrically connected;
a hot-side heat exchanger connected to the first electrodes; and
a cold-side heat exchanger connected to the second electrodes via a plate-shaped insulator to which the second electrodes are not fixed, the cold-side heat exchanger consisting of two metal plates placed parallel to and facing each other with a space therebetween,
wherein a plurality of springs is disposed in an interior of the cold-side heat exchanger at portions connected to the second electrodes, such that one spring is disposed so as to bias one thermoelectric conversion element,
the cold-side heat exchanger is provided with a transfer portion capable of transmitting to one thermoelectric conversion element a biasing force of one spring at a portion connected to the first electrode or the second electrode,
the transfer portion being a metal foil having a thickness thinner than a thickness of either one of the plates of the cold-side heat exchanger,
a side of the thermoelectric conversion elements nearest the cold-side heat exchanger forming a free end in contact with only the transfer portion, and
each spring of the plurality of springs has a Z-shaped cross-section formed by cutting and raising a single metal plate at a plurality of positions corresponding to the thermoelectric conversion elements,
each spring of the plurality of springs having an inclined portion extending upward at an angle to the single metal plate and a pressing portion continuous with the inclined portion and extending parallel to the single metal plate.

US Pat. No. 10,971,669

EXB DRIFT THERMOELECTRIC ENERGY GENERATION DEVICE

1. A thermoelectric energy generator utilizing the ExB drift effect, said thermoelectric generator comprising:a) layers comprising a semiconductor material at a semiconductor temperature, said layers having a layer thickness and said layer having a multiplicity of at least one;
b) a thermal contact for transferring heat from a heat source to said layers;
c) no thermal contact to any heat sink;
d) electrical carriers in said semiconductor, comprising electrons and holes, said electrons having an electron concentration and said holes having a hole concentration, said electron concentration and said hole concentration in combination being called carrier concentration;
e) said semiconductor material being in a depletion mode, a maximum carrier concentration being defined as a value of said carrier concentration below which said semiconductor material remains in said depletion mode;
f) said electrons having electron properties;
g) said holes having hole properties generally different from said electron properties;
h) a magnetic field along a magnetic axis essentially parallel to said layers;
i) an electric field along an electric axis essentially perpendicular to said layers;
j) said magnetic field and said electric field in combination producing said ExB drift of said electrical carriers;
k) said electrons carried by said ExB drift, traveling along cycloid orbits with an electron drift speed and in an electron drift direction in accordance with their said electron properties, said electron drift direction not generally aligned with said electric field, said electrons producing an electron negative current;
l) said holes carried by said ExB drift, traveling along cycloid orbits with a hole drift speed and in a hole drift direction distinct from said electron drift speed and said electron drift direction respectively, said hole drift direction not generally aligned with said electric field, in accordance with their said hole properties, said hole producing a hole positive current;
m) said electron negative current and said hole positive current, not being equal to each other in magnitude and direction, and not cancelling each other out, and producing a net output current;
n) electrodes in contact with said layers, said electrodes capturing said net output current, and not generating said electric field, said net output current being accompanied by an output voltage;
o) said carriers contributing a largest current being called overriding carriers, their said largest current, overriding current, their said properties, overriding properties, and furthermore, said carriers contributing a smallest current being called overridden carriers, their said smallest current, overridden current, their said properties, overridden properties;
p) said electrodes having a polarity determined by said ExB drift and said properties of said overriding carriers.

US Pat. No. 10,971,668

LIGHT-EMITTING DEVICE PACKAGE INCLUDING A LEAD FRAME

SAMSUNG ELECTRONICS CO., ...

1. A light-emitting device package, comprising:a lead frame comprising:
a first metallic lead comprising:
a first inner metallic lead portion; and
a first outer metallic lead portion; and
a second metallic lead comprising:
a second inner metallic lead portion;
a second outer metallic lead portion, the first metallic lead and the second metallic lead being spaced apart from each other in a first direction,
a light-emitting device chip disposed in a flip-chip structure on a part of the first inner metallic lead portion and a part of the second inner metallic lead portion; and
a molding structure comprising:
an outer barrier portion surrounding the first and second inner metallic lead portions of the lead frame, the first and second outer metallic lead portions protruding from the outer barrier portion; and
an electrode separating portion disposed between the first metallic lead and the second metallic lead and filling space between the first and second metallic leads, the electrode separating portion extending in a second direction intersecting the first direction,
wherein each of the first and second metallic leads comprises at least two inner slots formed to extend in the first direction, the at least two inner slots of the first metallic lead penetrating through an upper surface to a lower surface of the first metallic lead, the at least two inner slots of the second metallic lead penetrating through an upper surface to a lower surface of the second metallic lead, and
wherein the molding structure further comprises inner slot molding portions integrally connected to the electrode separating portion and filling the at least two inner slots of each of the first metallic lead and the second metallic lead.

US Pat. No. 10,971,667

LIGHT EMITTING DEVICE AND FABRICATING METHOD THEREOF

Samsung Display Co., Ltd....

1. A light emitting device comprising:a substrate;
a first conductive line on the substrate;
a second conductive line on the substrate and spaced apart from the first conductive line;
a metal member between the first conductive line and the second conductive line, the metal member having an opening; and
a light emitting element having a first end portion and a second end portion, the first end portion being in the opening, the second end portion protruding outside of the opening.

US Pat. No. 10,971,666

METHOD FOR MANUFACTURING AN OPTICAL MODULE AND OPTICAL MODULE

MITSUMI ELECTRIC CO., LTD...

10. An optical module, comprising:a board having a plurality of electrodes on its surface;
a light emitting device mounted on the plurality of electrodes of the board in a facedown manner;
a first light transmissive resin mixed with a light wavelength conversion material and sealing the surface of the board including the light emitting device;
a second light transmissive resin covering a top surface of the first light transmissive resin;
a light reflective resin containing a light reflective material provided to cover an outer peripheral lateral surface along the outer peripheral lateral surface of a stack constituted of the board, the light emitting device, the first light transmissive resin and the second light transmissive resin; and
a layer made of an inorganic film between the outer peripheral lateral surface of the stack and the light reflective resin.

US Pat. No. 10,971,665

PHOTON EXTRACTION FROM NITRIDE ULTRAVIOLET LIGHT-EMITTING DEVICES

CRYSTAL IS, INC., Green ...

1. An illumination device comprising:a ultraviolet (UV) light-emitting semiconductor die;
a rigid lens for extracting light from the light-emitting semiconductor die, the rigid lens having a mounting surface and a transmission surface opposite the mounting surface; and
a layer of encapsulant disposed between the light-emitting semiconductor die and the mounting surface of the rigid lens, whereby the light-emitting semiconductor die is attached to the rigid lens by the layer of encapsulant,
wherein (i) a thickness of the encapsulant is less than approximately 10 ?m, and (ii) at least a portion of the rigid lens between the mounting surface and the transmission surface has a straight vertical sidewall.

US Pat. No. 10,971,664

DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate;
a bank layer on the substrate, wherein the bank layer defines an opening;
a light-emitting diode in the opening defined by the bank layer;
a pixel separating layer between a plurality of the light-emitting diodes, wherein the pixel separating layer is disposed on the bank layer and does not overlap the opening when viewed from a plan view in a thickness direction of the substrate; and
a light dispersion layer arranged on the light-emitting diode to cover the bank layer and the pixel separating layer,
wherein the light dispersion layer comprises micro-particles such that the light dispersion layer scatters light emitted from the light-emitting diode.

US Pat. No. 10,971,663

SEMICONDUCTOR LIGHT EMITTING DEVICE

STANLEY ELECTRIC CO., LTD...

1. A semiconductor light emitting device comprising:a mount substrate;
a light emitting element mounted on a surface of the mount substrate;
a wavelength conversion layer for converting light emitted from the light emitting element to light having a predetermined wavelength;
a light reflection member provided on the same surface of the mount substrate as the light emitting element, the light reflection member surrounding the light emitting element and the wavelength conversion layer; and
a thin film provided on an outermost surface from which the light wavelength-converted by the wavelength conversion layer exits, the thin film having a coarse surface,
wherein:
the light emitting element comprises a light emitting layer, and light emitting surfaces of the light emitting element comprise an upper surface and side surfaces of the light emitting layer,
the wavelength conversion layer has a plate shape,
an upper surface of the wavelength conversion layer is a coarse surface,
the thin film is directly formed on the coarse surface which is the upper surface of the wavelength conversion layer,
the thin film has a shape that follows concavities and convexities of the coarse surface which is the upper surface of the wavelength conversion layer,
an upper surface of the thin film is a coarse surface having concavities and convexities,
the wavelength conversion layer is a plate made of an inorganic material which is one of (i) a mixture of or a sintered body of ceramic and a fluorescent material, (ii) a mixture of glass and a fluorescent material, (iii) ceramic on which a fluorescent material film is disposed, (iv) glass on which a fluorescent material film is formed, (v) fluorescent material dispersion glass, and (vi) a fluorescent material ceramic plate,
the light reflection member is made from a material that includes a mixture of a resin material and a light reflection filler, the material being curable by heating or irradiation with ultraviolet rays,
the thin film and the wavelength conversion layer are made of materials such that a contact angle of the thin film with respect to an uncured material of the light reflection member is larger than a contact angle of the wavelength conversion layer with respect to the uncured material of the light reflection member,
the light reflection member directly contacts side surfaces of the light emitting element and directly contacts side surfaces of the wavelength conversion layer, and
the light reflection member does not cover an upper surface of the thin film.

US Pat. No. 10,971,662

LIGHT EMITTING DIODE PACKAGE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A light-emitting diode (LED) package comprising:a light-emitting structure including a first conductivity type layer, a second conductivity type layer, and an active layer between the first and second conductivity type layers;
a transmissive material layer on the light-emitting structure, the transmissive material layer contacting a top surface of the light-emitting structure;
a support structure covering at least a portion of a side surface of the transmissive material layer, a side surface of the light-emitting structure, and at least a portion of a bottom surface of the light-emitting structure, the side surface of the transmissive material layer being parallel to and non-contiguous with the side surface of the light-emitting structure; and
an electrode connected to the bottom surface of the light emitting structure, the electrode including a first electrode and a second electrode, the first electrode connected to the first conductivity type layer through an opening in the second conductivity type layer and active layer, the second electrode connected to the second conductivity type layer,
wherein the support structure comprises:
a first material from a bottom surface of the support structure to a first level, and the first material covering the side surface of the light-emitting structure; and
a second material from the first level to a top surface of the support structure, the second material different from the first material, and the second material covering at least a portion of a side surface of the transmissive material layer;
a light reflection efficiency of the first material is greater than that of the second material.

US Pat. No. 10,971,661

LIGHT-EMITTING DEVICE WITH LIGHT SCATTER TUNING TO CONTROL COLOR SHIFT

LUMILEDS LLC, San Jose, ...

1. A light-emitting device configured to produce a white light comprising:a light emitting semiconductor structure configured to emit blue light;
a wavelength converting structure disposed in a path of the light emitted by the light emitting semiconductor structure and comprising a green phosphor material, a broad red phosphor material, and a narrow red phosphor material; and
a light scattering structure arranged with respect to the wavelength converting structure to scatter light back toward the wavelength converting structure; the light scattering structure configured to scatter more light as the temperature of the light scattering structure increases;
in operation with the light scattering structure at 25° C., the white light output of the light-emitting device has a correlated color temperature of less than 2500K and with the light scattering structure at 85° C., the white light output of the light-emitting device has a correlated color temperature of greater than 2700K.

US Pat. No. 10,971,660

WHITE LED LIGHT SOURCE AND METHOD OF MAKING SAME

Eyesafe Inc., Eden Prair...

1. An LED light source comprising:an LED,wherein the LED light source emits white light;a first encapsulant comprising a light-absorbing component that absorbs light from about 415 to about 455 nm,wherein the light-absorbing component comprises a dye, an organic pigment, or an inorganic pigment; anda second encapsulant comprising a phosphor.

US Pat. No. 10,971,659

WHITE LIGHT EMITTING DEVICE COMPRISING MULTIPLE PHOTOLUMINESCENCE MATERIALS

Bridgelux, Inc., Fremont...

1. A white light emitting device comprising:first and second LEDs operable to generate excitation light having a dominant wavelength in a range from 440 nm to 480 nm and mounted on a substrate;
a first photoluminescence material which generates light having a peak emission wavelength in a range from 500 nm to 590 nm; and
a second photoluminescence material which generates light having a peak emission wavelength in a range from 600 nm to 650 nm,
wherein the first LED is covered by the first photoluminescence material, and the second LED is covered by the first and second photoluminescence materials; and wherein the second photoluminescence material is directly in contact with the second LED.

US Pat. No. 10,971,658

INFRARED EMITTING DEVICE

Lumileds LLC, San Jose, ...

1. A device comprising:a light source emitting a first light; and
a wavelength converting structure disposed in a path of the first light emitted by the light source, the wavelength converting structure comprising:
a first phosphor; and
a second phosphor;
the second phosphor absorbing the first light and emitting a second light, which second light is visible light, the first phosphor absorbing the first light and emitting a third light, the first phosphor absorbing the second light and emitting a fourth light, the third light and the fourth light have different peak wavelengths in the infrared emission range.

US Pat. No. 10,971,657

LIGHT EMITTING MODULE AND METHOD OF MANUFACTURING THE SAME

NICHIA CORPORATION, Anan...

1. A light emitting module comprising:a plurality of light emitting elements each having a primary light emitting surface and a lateral surface;
a plurality of wavelength conversion members arranged respectively on the primary light emitting surfaces of the plurality of light emitting elements; and
a lightguide plate having a first primary surface and a second primary surface and arranged continuously on the plurality of wavelength conversion members so that the second primary surface faces the plurality of wavelength conversion members, wherein the lightguide plate includes a plurality of recessed portions located on the second primary surface, and a lateral surface of at least one of the plurality of wavelength conversion members is partially in contact with an inner lateral surface of at least one of plurality of the recessed portions.

US Pat. No. 10,971,656

RESIN MOLDING, SURFACE MOUNTED LIGHT EMITTING APPARATUS AND METHODS FOR MANUFACTURING THE SAME

NICHIA CORPORATION, Anan...

1. A light emitting apparatus comprising:a light emitting device comprising a first electrode and a second electrode, wherein the light emitting device emits light with a wavelength that is equal to or greater than 420 nm and equal to or smaller than 490 nm; and
a first resin molding which integrally molds
a first lead, on which the light emitting device is mounted, a metal plating being provided on the first lead, the first lead being electrically connected to the first electrode of the light emitting device by a wire or an electrically conductive die bonding member, and
a second lead, which is electrically connected to the second electrode of the light emitting device, a metal plating being provided on the second lead,
wherein a resin forming the first resin molding is a thermosetting resin including at least triglycidyl isocyanurate and an acid anhydride,
wherein the first resin molding includes a titanium oxide pigment so that the first resin molding is reflective to thereby reflect light emitted by the light emitting device,
wherein the light emitting apparatus further comprises a second resin that covers the light emitting device,
wherein the second resin is formed by at least one kind selected from the group consisting of epoxy resin, modified epoxy resin, silicone resin, and modified silicone resin, and
wherein a thickness of at least one of the first lead and the second lead is substantially the same as a thickness of a portion of the first resin molding that is located between the first lead and the second lead.

US Pat. No. 10,971,655

SEMICONDUCTOR DEVICE

LG INNOTEK CO., LTD., Se...

1. A semiconductor device comprising:a substrate;
a first semiconductor layer disposed on the substrate;
a second semiconductor layer disposed on the first semiconductor layer;
a third semiconductor layer disposed on the second semiconductor layer; and
a reflective layer disposed on the third semiconductor layer,
wherein:
a part between the first and second semiconductor layers, a part between the third and second semiconductor layers, and the second semiconductor layer comprise a depletion region; and
a conductivity type of the first semiconductor layer and a conductivity type of the third semiconductor layer are different from each other, and the second semiconductor layer comprises an intrinsic semiconductor layer.

US Pat. No. 10,971,654

DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME

LG ELECTRONICS INC., Seo...

1. A display device, comprising:a semiconductor light emitting device; and
a substrate having a receiving groove in which the semiconductor light emitting device is accommodated;
wherein the semiconductor light emitting device comprises:
a first conductive semiconductor layer;
a second conductive semiconductor layer disposed on an upper portion of the first conductive semiconductor layer;
a first conductive electrode disposed on the first conductive semiconductor layer; and
a second conductive electrode disposed on the second conductive semiconductor layer, and spaced apart from the first conductive electrode along a horizontal direction of the semiconductor light emitting device,
wherein the first conductive semiconductor layer has a symmetrical shape with respect to at least one direction of the semiconductor light emitting device so that the first conductive electrode and the second conductive electrode are arranged at preset positions when the semiconductor light emitting device is accommodated into the receiving groove, and
wherein a shape of the receiving groove matches the symmetrical shape of the first conductive semiconductor layer to control an assembly direction of the semiconductor light emitting device.

US Pat. No. 10,971,653

RADIATION-EMITTING SEMICONDUCTOR BODY AND METHOD OF PRODUCING A SEMICONDUCTOR LAYER SEQUENCE

OSRAM OLED GmbH, Regensb...

1. A radiation-emitting semiconductor body comprising a semiconductor layer sequence comprising an active region that generates radiation, an n-conducting semiconductor layer and a p-conducting semiconductor layer, wherein the active region is arranged between the n-conducting semiconductor layer and the p-conducting semiconductor layer and the p-conducting semiconductor layer comprises a first doping region with a first dopant and a second doping region with a second dopant different from the first dopant, and the p-conducting semiconductor layer comprises a further doping region doped with the first dopant and has a thickness of at most 2 nm.

US Pat. No. 10,971,652

SEMICONDUCTOR DEVICE COMPRISING ELECTRON BLOCKING LAYERS

EPISTAR CORPORATION, Hsi...

1. A semiconductor device, comprising:a first semiconductor structure;
a second semiconductor structure on the first semiconductor structure;
an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region comprises multiple alternating well layers and barrier layers, wherein each of the barrier layers has a band gap, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface;
an electron blocking region between the second semiconductor structure and the active region, wherein the electron blocking region comprises a first electron blocking layer having a band gap greater than the band gap of one of the barrier layers;
a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; and
a second electron blocking layer between the first aluminum-containing layer and the active region, wherein the second electron blocking layer has a band gap greater than the band gap of one of the barrier layers,
wherein the first electron blocking layer comprises InaAlbGa1-a-bN, the second electron blocking layer comprises IncAldGa1-c-dN, the first aluminum-containing layer comprises IneAlfGa(1-e-f)N, and 0?a

US Pat. No. 10,971,651

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE INCLUDING SAME

LG INNOTEK CO., LTD., Se...

1. A semiconductor device comprising:a first conductive semiconductor layer;
a second conductive semiconductor layer;
an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer;
a first electrode electrically connected to the first conductive semiconductor layer; and
a second electrode electrically connected to the second conductive semiconductor layer,
wherein the first conductive semiconductor layer includes a first sub semiconductor layer,
a third sub semiconductor layer, and
a second sub semiconductor layer disposed between the first sub semiconductor layer and the third sub semiconductor layer,
each of an average value of a proportion of aluminum in the first sub semiconductor layer and an average value of a proportion of aluminum in the third sub semiconductor layer is greater than an average value of a proportion of aluminum in the active layer,
an average value of a proportion of aluminum in the second sub semiconductor layer is less than each of the average value of the proportion of aluminum in the first sub semiconductor layer and the average value of the proportion of aluminum in the third sub semiconductor layer,
the second conductive semiconductor layer includes a current injection layer in which a proportion of aluminum decreases in a direction away from the active layer,
the first electrode is disposed on the second sub semiconductor layer,
the second electrode is disposed on the current injection layer, and
a ratio of the average value of the proportion of aluminum in the second sub semiconductor layer to an average value of the proportion of aluminum in the current injection layer ranges from 1:0.12 to 1:1.6.

US Pat. No. 10,971,650

LIGHT EMITTING DEVICE

Lextar Electronics Corpor...

1. A light emitting device, comprising:a stacked structure comprising:
a p-type semiconductor layer;
an n-type semiconductor layer on the p-type semiconductor layer;
a light emitting layer sandwiched between the p-type semiconductor layer and the n-type semiconductor layer;
an n-type electrode on the n-type semiconductor layer;
an n-type contact layer sandwiched between the n-type semiconductor layer and the n-type electrode;
a p-type electrode on the p-type semiconductor layer;
an n-type contact pad on the n-type electrode;
a p-type contact pad on the p-type electrode; and
a semiconductor reflector between the light emitting layer and the n-type contact layer, the semiconductor reflector including multiple periods, each period comprising at least a first layer and at least a second layer, a refractive index of the first layer being different from a refractive index of the second layer; and
a first insulating layer covering at least side surfaces of the stacked structure.

US Pat. No. 10,971,649

SEMICONDUCTOR DEVICE AND LIGHT EMITTING DEVICE PACKAGE COMPRISING SAME

LG INNOTEK CO., LTD., Se...

1. A semiconductor device comprising:a first semiconductor layer;
a second semiconductor layer disposed on the first semiconductor layer and comprising first V-pits;
an active layer disposed on the second semiconductor layer and comprising second V-pits disposed on the first V-pits;
a third semiconductor layer disposed on the active layer and comprising third V-pits disposed on the second V-pits;
a fourth semiconductor layer disposed on the third semiconductor layer and comprising fourth V-pits disposed on the third V-pits;
a fifth semiconductor layer disposed on the fourth semiconductor layer and comprising fifth V-pits disposed on the fourth V-pits;
a sixth semiconductor layer disposed on the fifth semiconductor layer;
wherein the first and second semiconductor layers are an n-type semiconductor layer doped with an n-type dopant,
wherein the third and sixth semiconductor layers are a p-type semiconductor layer doped with a p-type dopant,
wherein the third semiconductor layer includes a bandgap wider than a bandgap of the active layer,
wherein the fourth semiconductor layer includes a bandgap lower than the bandgap of the third semiconductor layer,
wherein the fifth semiconductor layer includes a bandgap wider than the bandgaps of the third and fourth semiconductor layers,
wherein the active layer includes a first region disposed on the first V-pits, and a second region disposed outside the first region and the first V-pits,
wherein the second region of the active layer is disposed to be higher than the first region of the active layer,
wherein the third semiconductor layer includes a first region disposed on the second V-pits, and a second region disposed outside the first region on the third semiconductor layer and the second V-pits,
wherein the second region of the third semiconductor layer is disposed to be higher than the first region of the third semiconductor layer,
wherein a thickness of the first region of the third semiconductor layer is less than a thickness of the second region of the third semiconductor layer,
wherein the thickness of the first region of the third semiconductor layer is 1 nm to 50 nm,
wherein the third semiconductor layer and the fifth semiconductor layer comprise an aluminum composition,
wherein the sixth semiconductor layer has a bandgap equal to the bandgap of the fourth semiconductor layer,
wherein the active layer includes a first width which is a width of the second V-pits which is parallel to an upper portion of the active layer in a horizontal direction,
wherein the fifth semiconductor layer includes a second width which is a width of the fifth V-pits which is parallel to an upper portion of the fifth semiconductor layer in the horizontal direction,
wherein the second width is greater than the first width,
wherein the first width is 200 nm to 300 nm, and the second width is 300 nm to 400 nm,
wherein a width of each of the first to fifth V-pits is gradually increased in the direction from a top surface of the first semiconductor layer to a top surface of the sixth semiconductor layer,
wherein a lower vertex of each of the first to fifth V-pits is disposed between a bottom surface of the second semiconductor layer and a top surface of the second semiconductor layer.

US Pat. No. 10,971,648

ULTRAVIOLET LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING ELEMENT PACKAGE

LG INNOTEK CO., LTD., Se...

1. An ultraviolet light-emitting device comprising:a support member;
a light-emitting structure on the support member, the light-emitting structure having a second conductive type semiconductor layer and a first conductive type semiconductor layer, an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer, and a plurality of recesses that penetrate the second conductive type semiconductor layer and the active layer and expose a part of a region of the first conductive type semiconductor layer;
a first electrode disposed between the support member and the light-emitting structure and is electrically connected to the second conductive type semiconductor layer,
a second electrode disposed under the first electrode and is electrically connected to the exposed region of the first conductive type semiconductor layer,
wherein the first conductive type semiconductor layer includes a first conductive type second semiconductor layer disposed on the active layer, a first conductive type first semiconductor layer disposed on the first conductive type second semiconductor layer, and an etching-blocking layer disposed between the first conductive type first semiconductor layer and the first conductive type second semiconductor layer,
wherein the first conductive type first semiconductor layer includes a light extraction pattern,
wherein an electron spreading layer is disposed between the etching-blocking layer and the first conductive type second semiconductor layer,
wherein the electron spreading layer includes a first conductive AlGaN based fourth semiconductor layer, an undoped AlN layer, a first conductive AlGaN based fifth semiconductor layer, and an undoped AlGaN based semiconductor layer,
wherein the first conductive AlGaN based fourth semiconductor layer is disposed between the etching-blocking layer and an undoped AlN layer,
wherein the undoped AlN layer is disposed between the first conductive AlGaN based fourth semiconductor layer and a first conductive AlGaN based fifth semiconductor layer,
wherein the first conductive AlGaN based fifth semiconductor layer is disposed between the undoped AlN layer and an undoped AlGaN based semiconductor layer,
wherein the undoped AlGaN based semiconductor layer is disposed between the first conductive AIGaN based fifth semiconductor layer and the first conductive type second semiconductor layer,
wherein the undoped AlN layer has larger bandgap energy than that of the first conductive type AlGaN-based fourth semiconductor layer, the first conductive AlGaN based fifth semiconductor layer and the undoped AlGaN based semiconductor layer,
wherein a bandgap energy of the first conductive AIGaN based fifth semiconductor layer gradually decreases toward the undoped AlGaN-based semiconductor layer from the undoped AlN layer,
wherein a thickness of the undoped AlN layer is thinner than a thickness of the undoped AlGaN-based semiconductor layer,
wherein the thickness of the undoped AlGaN-based semiconductor layer is thinner than a thickness of the first conductive AIGaN based fifth semiconductor layer,
wherein the second electrode includes a contact portion disposed in each of the plurality of recesses and directly makes contact with the first conductive type second semiconductor layer,
wherein the etching-blocking layer and the electron spreading layer are spaced apart from the contact portion of the second electrode by distance in a vertical direction.

US Pat. No. 10,971,647

SOLAR CELL VIA THIN FILM SOLDER BOND

AmberWave, Inc., Salem, ...

1. A method of forming a solar cell device, comprising:forming a porous layer in a monocrystalline donor substrate;
forming an epitaxial semiconductor layer on the porous layer;
forming a base region layer on the epitaxial semiconductor layer;
forming an emitter region layer on the base region layer to provide a junction for a solar cell structure;
bonding a carrier substrate to the solar cell structure through a bonding layer;
removing the monocrystalline donor substrate by cleaving the porous layer;
forming a grid of metal contacts on the epitaxial semiconductor layer;
removing exposed portions of the epitaxial semiconductor layer, wherein remaining portions of the epitaxial semiconductor layer remain between the grid of metal contacts and the junction for the solar cell structure;
texturing an exposed surface of the base region layer of the solar cell structure to provide a textured surface of the base region layer, wherein said texturing the exposed surface of the base region layer is after forming said junction of the solar cell structure, the junction of the solar cell structure for receiving light; and
forming a passivation layer on at least the textured surface of the base region layer, wherein the passivation layer is in direct contact with the textured surface of the base region layer, wherein the epitaxial semiconductor layer is a base contact region having a higher dopant concentration than the base region.

US Pat. No. 10,971,646

CHEMICAL VAPOR DEPOSITION EQUIPMENT FOR SOLAR CELL AND DEPOSITION METHOD THEREOF

LG ELECTRONICS INC., Seo...

1. A chemical vapor deposition (CVD) equipment for depositing a doped polycrystalline silicon layer for a solar cell, the CVD equipment comprising:a chamber having an inner space extending in a horizontal direction;
a boat carrying a plurality of silicon wafers and arranged in the horizontal direction in the inner space of the chamber, the plurality of silicon wafers disposed vertically in the inner space of the chamber;
at least one first pipe extending in the horizontal direction and disposed to face first side edges of the plurality of silicon wafers;
at least one second pipe extending in the horizontal direction and disposed to face second side edges of the plurality of silicon wafers opposite the first side edges of the plurality of wafers;
a door installed at a front side of the chamber along the horizontal direction and through which the boat is able to enter and exit the chamber;
a vent installed at a rear side of the chamber along the horizontal direction and through which a gas is able to escape; and
a plurality of shower nozzles each connected to one of the at least one first pipe and at least one second pipe and configured to inject a mixed gas composed of a silicon deposition gas and an impurity gas toward the first and second side edges of the plurality of wafers,
wherein each of the plurality of shower nozzles has a plurality of holes to inject the mixed gas,
wherein the at least one first pipe and the at least one second pipe are respectively arranged to inject the mixed gas into a plurality of different silicon wafer groups, and
wherein the door and the vent face each other in the horizontal direction.

US Pat. No. 10,971,645

CONTROLLING DETECTION TIME IN PHOTODETECTORS

Waymo LLC, Mountain View...

1. A method comprising:providing a device comprising:
a light source comprising a laser;
a substrate; and
a photodetector coupled to the substrate,
wherein the photodetector is arranged to detect a light signal emitted from the light source upon the light signal being reflected from one or more objects in an external environment and irradiating a top surface of the device;
emitting the light signal from the light source; and
mitigating dark current arising from minority carriers photoexcited in the substrate based on the light signal emitted from the light source.

US Pat. No. 10,971,644

PHOTODETECTION DEVICE, PHOTODETECTION SYSTEM, AND MOVING BODY

CANON KABUSHIKI KAISHA, ...

1. A photodetection device comprisinga first semiconductor substrate including a first surface and a second surface opposite of the first surface; and
a pixel including an avalanche diode disposed on the first semiconductor substrate,
wherein the avalanche diode includes:
a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type disposed at a first depth from the first surface of the first semiconductor substrate, a polarity of the second conductivity type being different from a polarity of the first conductivity type, and the first semiconductor region configured to form part of the first surface of the first semiconductor substrate;
a third semiconductor region of the first conductivity type and a fourth semiconductor region of the second conductivity type disposed at a second depth from the first surface of the first semiconductor substrate, the second depth being deeper than the first depth, the fourth semiconductor region being in contact with the third semiconductor region, the third semiconductor region having a concentration of an impurity of the first conductivity type lower than a concentration of an impurity of the first conductivity type of the first semiconductor region, and the fourth semiconductor region having a concentration of an impurity of the second conductivity type lower than a concentration of an impurity of the second conductivity type of the second semiconductor region; and
a fifth semiconductor region of the first conductivity type disposed at a third depth from the first surface of the first semiconductor substrate, the third depth being deeper than the second depth, and the fifth semiconductor region having a concentration of the impurity of the first conductivity type lower than the concentration of an impurity of the first conductivity type of the third semiconductor region, and
wherein, in a plan view,
the first semiconductor region overlaps at least a part of the third semiconductor region, the second semiconductor region overlaps at least a part of the fourth semiconductor region, and the third semiconductor region and the fourth semiconductor region overlap the fifth semiconductor region.

US Pat. No. 10,971,643

IMPLEMENTATION OF AN OPTIMIZED AVALANCHE PHOTODIODE (APD)/SINGLE PHOTON AVALANCHE DIODE (SPAD) STRUCTURE

AVAGO TECHNOLOGIES INTERN...

1. A photodetector, comprising:a plurality of single-photon avalanche diodes or avalanche photodiodes, at least one of the plurality of single-photon avalanche diodes or avalanche photodiodes comprising an un-depleted anode and cathode region which are separated by one or more conductive trenches that extend completely between the anode region and cathode region, wherein the one or more conductive trenches define an active volume of the at least one single-photon avalanche diode or avalanche photodiode and are configured to reflect light back into the active volume of the at least one single-photon avalanche diode or avalanche photodiode, wherein the one or more conductive trenches comprise:
a polysilicon material;
a conductive material deposited within a polysilicon material; and
an outer trench doping that is positioned between the polysilicon material of the one or more conductive trenches and the active volume of the at least one single-photon avalanche diode or avalanche photodiode, and wherein the outer trench doping comprises a same type of doping as one of the anode region and the cathode region, wherein the one or more conductive trenches is in direct contact with the active volume of the at least one single-photon avalanche diode or avalanche photodiode.

US Pat. No. 10,971,642

OPTO-ELECTRONIC UNIT COMPOSED OF AN OPTO-PHOTONIC PLATFORM

SEGTON ADVANCED TECHNOLOG...

1. An opto-electronic unit to be used as a photovoltaic solar sensor, comprising:an opto-photonic platform adapted to be exposed to solar radiation and comprising at least one photonic converter and at least one photonic diffraction grating incorporated therein comprising a plurality of diffractive structures, wherein the opto-photonic platform is configured to specifically output radiation wavelengths of spectral sub-bands of the visible range having predetermined widths,
wherein the plurality of diffractive structures are slanted relative to a normal of a main plane of the photonic diffraction grating so that respective surfaces of the plurality of diffractive structures are oriented toward the main plane of the photonic diffraction grating,
wherein at least one of the plurality of diffractive structures has at least one selected from the group consisting of a different height, a different thickness, a different slant angle, a different position, a different spacing, and a different pitch than at least one other of the plurality of diffractive structures,
wherein the plurality of diffractive structures comprise slanted ribs or slanted fringes having height dimensions within a range of from 0.3 to 3 nanometers, and spacings between two adjacent ribs or fringes are within a range of from 100 to 600 nanometers,
a light-to-electricity conversion unit operatively associated with said opto-photonic platform comprising a plurality of light-to-electricity converters each having an exposure surface upon which said specifically outputted spectral sub-bands of the visible range, outputted from said opto-photonic platform, are respectively received as incident light flux so as to produce electricity.

US Pat. No. 10,971,641

FLEXIBLE OPTOELECTRONIC DEVICES

FLEXENBLE LIMITED, Cambr...

10. A method of producing a device according claim 1, the method comprising: applying the one or more driver chips to the first sheet component; bonding the second sheet component to the first sheet component so as to overlie the one or more driver chips; and filling a space between the first and second sheet components and around the one or more driver chips with a material.

US Pat. No. 10,971,640

SELF-ASSEMBLY PATTERNING FOR FABRICATING THIN-FILM DEVICES

FLISOM AG, Niederhasli (...

1. A photovoltaic device, comprising:at least one absorber layer disposed over a surface of a substrate; and
a plurality of cavities at a surface of the at least one absorber layer, wherein the surface of the at least one absorber layer comprises an amount of cesium (Cs) and/or rubidium (Rb), and wherein a first line of regularly spaced cavities is adjacent and parallel to at least a second line of regularly spaced cavities within at least one region of the at least one absorber layer.

US Pat. No. 10,971,639

METHOD OF MOUNTING AN ELECTRICAL COMPONENT ON A BASE PART

SICK AG, Waldkirch (DE)

1. A method of mounting an electrical component on a base part, said base part having an inclined support surface in which method a first wedge surface of a wedge element is arranged on the support surface and a lateral force is exerted on the wedge element so that the first wedge surface moves on the support surface until a second wedge surface of the wedge element remote from the support surface reaches a desired position,wherein the electrical component is arranged on the second wedge surface,
and wherein a first fastening element fixes the wedge element to the base part in the desired position, with means for exerting the lateral force on the wedge element being removed after fixing the wedge element to the base part so that the lateral force is no longer exerted after assembly.

US Pat. No. 10,971,638

LASER TECHNIQUES FOR FOIL-BASED METALLIZATION OF SOLAR CELLS

SunPower Corporation, Sa...

1. A method of fabricating a solar cell, the method comprising:forming a semiconductor region in or above a substrate;
forming a metal layer over the semiconductor region;
applying a laser over a first region of the metal layer to form a first metal weld, wherein applying a laser over the first region comprises applying the laser at a first scanning speed;
subsequent to applying the laser over the first region, applying the laser over a second region of the metal layer wherein applying the laser over the second region comprises applying a laser at a second scanning speed;
subsequent to applying the laser over the second region, applying the laser over a third region of the metal layer to form a second metal weld, wherein applying the laser over the third region comprises applying the laser at a third scanning speed; and
subsequent to applying the laser over the third region, applying the laser over a fourth region of the metal layer, wherein applying the laser over the fourth region comprises applying the laser at a fourth scanning speed, wherein the second scanning speed is greater than the first and third scanning speeds, and wherein the fourth scanning speed is greater than the first and third scanning speeds.

US Pat. No. 10,971,637

AIRSHIP WITH A RADIO FREQUENCY TRANSPARENT PHOTOVOLTAIC CELL

Raytheon Company, Waltha...

1. An airship, comprising:one or more radio frequency antennas disposed in an interior of the airship; and
one or more radio frequency transparent photovoltaic cells disposed on an outer surface of the airship, wherein
each of the one or more radio frequency transparent photovoltaic cells includes a back contact layer having first and second apertures to provide for passing of radio frequency radiation generated by the one or more radio frequency antennas, wherein
the first aperture is formed only in the back contact layer and is configured to pass signals of a first radio frequency band, and the second aperture is formed only in the back contact layer and is configured to pass signals of a second radio frequency band, wherein the first radio frequency band is different from the second radio frequency band, and wherein
the first aperture and the second aperture are of different size.

US Pat. No. 10,971,636

PHOTOELECTRIC DETECTION STRUCTURE, MANUFACTURING METHOD THEREFOR, AND PHOTOELECTRIC DETECTOR

BOE TECHNOLOGY GROUP CO.,...

1. A photoelectric detection structure, comprising:a base substrate;
an electrode strip on the base substrate;
a semiconductor layer on a side of the base substrate facing the electrode strip;
an insulating layer between the electrode strip and the semiconductor layer, the insulating layer being an integral film layer covering the electrode strip,
wherein the insulating layer comprises a thickness increasing portion, which is located on at least one edge of the electrode strip,
the electrode strip comprises a plurality of first sub-electrode strips and a plurality of second sub-electrode strips extending in a first direction and alternately arranged in a second direction, the plurality of first sub-electrode strips and the plurality of second sub-electrode strips are configured to apply different voltages to form a potential difference between adjacent ones of the plurality of first sub-electrode strips and the plurality of second sub-electrode strips, and the first direction and the second direction cross each other,
the thickness increasing portion is located on an edge of at least one of the plurality of first sub-electrode strips and the plurality of second sub-electrode strips facing the other.

US Pat. No. 10,971,634

OXIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING OXIDE SEMICONDUCTOR DEVICE

MITSUBISHI ELECTRIC CORPO...

1. An oxide semiconductor device comprising:an n-type gallium oxide epitaxial layer formed on an upper surface of an n-type gallium oxide substrate;
a p-type oxide semiconductor layer formed from an upper surface of the gallium oxide epitaxial layer to at least an inside of the gallium oxide epitaxial layer, the p-type oxide semiconductor layer being an oxide that is a different material from a material for the gallium oxide epitaxial layer;
a dielectric layer formed to cover at least part of a side surface of the oxide semiconductor layer and made of a material having a lower dielectric constant than the material for the oxide semiconductor layer;
an anode electrode formed on the upper surface of the gallium oxide epitaxial layer and forming a Schottky junction with the gallium oxide epitaxial layer; and
a cathode electrode formed on a lower surface of the gallium oxide substrate and forming an ohmic junction with the gallium oxide substrate,
wherein a hetero pn junction is formed between a lower surface of the oxide semiconductor layer and the gallium oxide substrate or between a lower surface of the oxide semiconductor layer and the gallium oxide epitaxial layer.

US Pat. No. 10,971,633

STRUCTURE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE

STMICROELECTRONICS (ROUSS...

1. A method of making a semiconductor device, the method comprising:simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, the semiconductor layer having a first conductivity type;
etching through first openings of a mask layer to form first implantation surfaces on the semiconductor layer and to form a plurality of projecting regions comprising conductive material of the conductive layer over the semiconductor layer; and
using the plurality of projecting regions as a part of a first implantation mask, performing a first implantation of dopants having a second conductivity type into the semiconductor layer, to form a sequence of PN junctions forming diodes in the semiconductor layer, the diodes vertically extending from an upper surface of the semiconductor layer to the insulating layer.

US Pat. No. 10,971,632

HIGH VOLTAGE DIODE ON SOI SUBSTRATE WITH TRENCH-MODIFIED CURRENT PATH

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device, comprising:a Silicon on Insulator (SOI) substrate;
a diode formed on the SOI substrate, the diode including a cathode region and an anode region; and
at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region, the at least one breakdown voltage trench being non-conductive and including an insulating material.

US Pat. No. 10,971,631

THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME, DISPLAY SUBSTRATE AND METHOD OF FABRICATING THE SAME, DISPLAY DEVICE

HEFEI XINSHENG OPTOELECTR...

1. A method of fabricating a display substrate, comprising:forming an active layer of a thin film transistor (TFT) on a substrate, the active layer being formed to comprise a first active layer and a second active layer, a carrier mobility of the first active layer being greater than a carrier mobility of the second active layer;
forming, by one patterning process, a data line and a source electrode and a drain electrode of the TFT on the substrate, the second active layer being closer to the source electrode and the drain electrode than the first active layer, an orthographic projection of the source electrode on the substrate and an orthographic projection of the drain electrode on the substrate at least partially overlapping with an orthographic projection of the second active layer on the substrate, respectively, and the first active layer being formed to be separated from the source electrode and the drain electrode;
forming an insulating layer on the substrate on which the data line, the source electrode, and the drain electrode have been formed, and forming, by a patterning process, a first via hole in the insulating layer to expose the data line, and a second via hole in the insulating layer to expose the source electrode; and
forming, by a patterning process, a connection electrode on the substrate on which the insulating layer has been formed, the connection electrode being electrically coupled to the data line and the source electrode through the first via hole and the second via hole.

US Pat. No. 10,971,630

SEMICONDUCTOR STRUCTURE HAVING BOTH GATE-ALL-AROUND DEVICES AND PLANAR DEVICES

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:receiving a semiconductor substrate having a first device region and a second device region separate from the first device region;
forming a mask covering the second device region;
while the mask covers the second device region, performing:
recessing the semiconductor substrate in the first device region; and
after the recessing, epitaxially growing multiple silicon and silicon germanium layers alternately stacked in the first device region;
patterning the silicon and silicon germanium layers in the first device region to define first active regions for gate-all-around (GAA) nanowire transistors and second active regions for GAA nanosheet transistors; and
patterning the semiconductor substrate in the second device region to define third active regions for planar devices, wherein a first width of the first active regions is smaller than a second width of the second active regions, and the second width is smaller than a third width of the third active regions.

US Pat. No. 10,971,629

SELF-ALIGNED UNSYMMETRICAL GATE (SAUG) FINFET AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor structure, the method comprising:forming a fin extending from a substrate, the fin having isolation regions along opposing sides of the fin;
forming a source region and a drain region in the fin;
forming a programming gate structure on a first sidewall of the fin;
forming a switching gate structure on a second sidewall of the fin opposite the programming gate structure, wherein the programming gate structure and the switching gate structure are along a portion of the fin interposed between the source region and the drain region;
forming a first contact to the programming gate structure, wherein the first contact contacts the programming gate structure at a point not lower than an upper surface of the fin; and
forming a second contact to the switching gate structure, wherein the second contact contacts the switching gate structure at a point lower than the upper surface of the fin.

US Pat. No. 10,971,628

FINFET DEVICE WITH T-SHAPED FIN

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device structure, comprising:an isolation feature over a substrate;
a fin structure protruding from the substrate and partially surrounded by the isolation feature, comprising:
a first portion above the isolation feature and having a first width;
a second portion extending from a top of the first portion and having a second width greater than the first width, so that the fin structure above the isolation feature has a T-shaped profile; and
a third portion extending from a bottom of the first portion; and
a gate structure covering the fin structure, and having a bottom surface that is in contact with a top surface of the third portion of the fin structure.

US Pat. No. 10,971,627

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD

TAIWAN SEMICONDUCTOR MANU...

1. A method for semiconductor manufacturing, comprising:forming mandrel structures on a semiconductor layer with a recess that is surrounded by the mandrel structures;
forming, in the recess, a gate structure that includes
a dielectric structure on a surface of the semiconductor layer, wherein forming the gate structure further comprises depositing a dielectric layer with a first portion on a bottom surface of the recess and a second portion lining sidewalls of the mandrel structures to form a dielectric recess that is surrounded by the dielectric layer,
a metal structure on the dielectric structure, and
an insulator structure on the metal structure;
removing the mandrel structures, wherein removing the mandrel structures further comprises etching the mandrel structures to remove the mandrel structures and the second portion of the dielectric layer that lines the sidewalls of the mandrel structures;
forming a spacer structure that spaces between the gate structure and a source/drain structure, wherein forming the spacer structure further comprises depositing a spacer layer that fills in a space that is underneath the insulator structure and was previously occupied by the second. portion of the dielectric layer, the second portion of the dielectric layer being removed by the etching of the mandrel structures; and
forming the source/drain structure adjacent to the spacer structure.

US Pat. No. 10,971,626

INTERFACE CHARGE REDUCTION FOR SIGE SURFACE

International Business Ma...

1. A field effect transistor (FET) device, comprising:a substrate;
an epitaxial silicon germanium (SiGe) channel material disposed on the substrate;
a thin continuous silicon (Si) layer formed on a surface of the SiGe channel material, wherein the thin continuous Si layer is less than 5 monolayers thick, wherein the SiGe channel material comprises planar surfaces and faceted surfaces, wherein the Si layer has a thickness T1 over the planar surfaces and a thickness T2 over the faceted surfaces, and wherein T1>T2; and
a gate stack disposed on the SiGe channel material, wherein the gate stack comprises a gate dielectric disposed on the SiGe channel material over the thin continuous Si layer and a gate conductor on the gate dielectric, and wherein the thin continuous Si layer passivates an interface between the SiGe channel material and the gate dielectric.

US Pat. No. 10,971,625

EPITAXIAL STRUCTURES OF A SEMICONDUCTOR DEVICE HAVING A WIDE GATE PITCH

GLOBALFOUNDRIES U.S. INC....

1. A semiconductor device comprising:an array of active regions, gate stacks and substantially uniform epitaxial structures, the gate stacks including a first gate stack and a second gate stack over an active region, the second gate stack being adjacent to the first gate stack;
an active pillar between the first gate stack and the second gate stack, wherein the active pillar comprises a doped conductive region;
two substantially uniform epitaxial structures between the first and second gate stacks and are separated by the active pillar, wherein each of the substantially uniform epitaxial structures has a width substantially equal to a minimum gate-to-gate spacing of the semiconductor device; and
a contact structure over the active pillar that is positioned equidistant from the first gate stack and the second gate stack.

US Pat. No. 10,971,624

HIGH-VOLTAGE TRANSISTOR DEVICES WITH TWO-STEP FIELD PLATE STRUCTURES

Macronix International Co...

16. A high voltage transistor device comprising:a source region in a well of a first dopant type in a semiconductor substrate;
a doping drift region of a second dopant type in the semiconductor substrate;
a drain region of the second dopant type in the doping drift region;
a gate electrode disposed via a gate dielectric layer over the semiconductor substrate between the source region and the drain region;
a first film region laterally extending from over the gate electrode to over a first portion of the doping drift region between the gate electrode and the drain region, the first portion of the doping drift region being adjacent to the gate electrode and away from the drain region, wherein the first film region comprises at least a part of a first film disposed on a top surface of the first portion of the doping drift region;
a second film region laterally extending over a second portion of the doping drift region, wherein the second portion of the doping drift region laterally abuts the first portion of the doping drift region at a first end and is adjacent to the drain region at a second end, wherein the second film region comprises a second film that includes a conductive layer laterally separated from the drain region;
a field plate laterally extending from over the first film region to over the second film region; and
a metal line layer coupling the field plate to one of the source region and the gate electrode,
wherein the first film is formed over the second film and under the field plate, and
wherein a first thickness is defined vertically from the top surface of the first portion of the drift region to a bottom surface of the field plate, the first thickness comprising a thickness of the first film, wherein a second thickness is defined vertically from a top surface of the second portion of the doping drift region to the bottom surface of the field plate, the second thickness comprising at least a thickness of the second film, and wherein the second thickness is larger than the first thickness.

US Pat. No. 10,971,623

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor device comprising:a semiconductor body including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, the semiconductor body having a front surface and a back surface opposite to the front surface, the first semiconductor layer and the second semiconductor layer being alternately arranged in a first direction along the front surface of the semiconductor body;
a first electrode partially contacting the front surface of the semiconductor body;
a second electrode provided on the back surface of the semiconductor body, the semiconductor body being provided between the first electrode and the second electrode; and
a control electrode provided between the semiconductor body and the first electrode,
the semiconductor body further including a third semiconductor layer of the second conductivity type and a fourth semiconductor layer of the first conductivity type, the third semiconductor layer being provided between the second semiconductor layer and the first electrode, the fourth semiconductor layer being selectively provided between the third semiconductor layer and the first electrode,
the first semiconductor layer including a first portion, a second portion, and a third portion arranged in a second direction from the second electrode to the first electrode, the second portion of the first semiconductor layer being provided between the first portion and third portions of the first semiconductor layer,
the second portion of the first semiconductor layer including first conductivity type impurities with a concentration lower than a concentration of first conductivity type impurities in the first portion of the first semiconductor layer and a concentration of first conductivity type impurities in the third portion of the first semiconductor layer, the second portion of the first semiconductor layer having a second width in the second direction smaller than a first width in the second direction of the first portion of the first semiconductor layer and a third width in the second direction of the third portion of the first semiconductor layer,
the second semiconductor layer including a first portion, a second portion and a third portion arranged in the second direction, the second portion of the second semiconductor layer being provided between the first portion and third portions of the second semiconductor layer,
the second portion of the second semiconductor layer including second conductivity type impurities with a concentration lower than a concentration of second conductivity type impurities in the first portion of the second semiconductor layer and a concentration of a second conductivity type impurities in the third portion of the second semiconductor layer, the second portion of the second semiconductor layer having a second width in the second direction smaller than a first width in the second direction of the first portion of the second semiconductor layer and a third width in the second direction of the third portion of the second semiconductor layer,
the second portion of the first semiconductor layer being provided at a level in the second direction same as a level in the second direction of the second portion of the second semiconductor layer.

US Pat. No. 10,971,622

TRANSISTOR STRUCTURES

Avago Technologies Intern...

1. A transistor structure, comprising:a substrate;
a fin structure on the substrate and including an undoped portion, a first doped portion, and a second doped portion, the second doped portion being separated from the first doped portion by the undoped portion;
an electrode on the fin structure between the first doped portion and the second doped portion;
an insulating layer on the fin structure;
a first trench in the insulating layer at a first side of the fin structure and between the electrode and the second doped portion, the first trench including a first conductive material; and
a second trench in the insulating layer at a second side of the fin structure and between the electrode and the second doped portion, the second side being opposite the first side, the second trench including a second conductive material.

US Pat. No. 10,971,621

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a semiconductor body including a first semiconductor layer of a first conductivity type;
a first electrode provided on a front surface of the semiconductor body;
a first control electrode placed inside a first trench, the first trench being provided on the front surface side of the semiconductor body, the first control electrode being electrically insulated from the semiconductor body by a first insulating film;
a second control electrode placed inside a second trench adjacent to the first trench on the front surface side of the semiconductor body, the second control electrode being electrically insulated from the semiconductor body by a second insulating film; and
a second electrode provided on the front surface of the semiconductor body with a third insulating film interposed, the second electrode being electrically connected to the first control electrode and the second control electrode,
the second electrode being placed to be spaced from the first electrode,
the first control electrode and the second control electrode each including a first portion, a second portion, and a third portion, the first portion being positioned between the semiconductor body and the first electrode, the second portion being positioned between the semiconductor body and the second electrode, the third portion being linked to the first portion and the second portion,
the semiconductor body further including a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a fourth semiconductor layer of the second conductivity type, the second to fourth semiconductor layers being provided between the first control electrode and the second control electrode,
the second semiconductor layer being provided on the first semiconductor layer and extending along the first portions, the third portions, and the second portions of the first control electrode and the second control electrode,
the third semiconductor layer being selectively provided between the second semiconductor layer and the first electrode,
the fourth semiconductor layer being provided selectively on the second semiconductor layer, the fourth semiconductor layer extending along the third portions and the second portions of the first control electrode and the second control electrode along an extension direction of the first control electrode and the second control electrode, the fourth semiconductor layer including second conductivity-type impurities with a higher concentration than a concentration of second conductivity-type impurities in the second semiconductor layer.

US Pat. No. 10,971,620

METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT

1. A method, comprising:partly removing a supporting layer arranged between a first semiconductor layer and a second semiconductor layer using an etching process, so as to form at least one undercut between the first semiconductor layer and the second semiconductor layer;
filling the at least one undercut with a first material having a higher thermal conductivity than the supporting layer such that the at least one undercut is completely filled with the first material or such that the undercut is filled with the first material except for a cavity between the first material and a corner location of the undercut wherein the supporting layer intersects the second semiconductor layer; and
forming a sensor device in or on the second semiconductor layer.

US Pat. No. 10,971,619

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

DENSO CORPORATION, Kariy...

1. A semiconductor device comprising:a semiconductor layer;
a source electrode disposed above one main surface of the semiconductor layer;
a drain electrode disposed below another main surface of the semiconductor layer; and
an insulation gate section, wherein
the semiconductor layer comprises:
a drift region of a first conductivity type;
a JFET region of the first conductivity type disposed above the drift region;
a body region of a second conductivity type disposed above the drift region and adjoining the JFET region; and
a source region of the first conductivity type separated from the JFET region by the body region,
the insulation gate section is opposed to a portion of the body region that separates the JFET region and the source region,
an empty space is provided within the semiconductor layer, and
the drift region, the JFET region and the body region are exposed to the empty space.

US Pat. No. 10,971,618

GENERATING MILLED STRUCTURAL ELEMENTS WITH A FLAT UPPER SURFACE

Applied Materials Israel ...

1. A method for generating milled structural elements, the method comprises:milling each structural element of an array of structural elements that are spaced apart from each other by gaps to provide the milled structural elements, wherein each milled structural element of the array has a flat upper surface; wherein prior to the milling, the each structural element has a flat upper surface of a certain width, wherein the certain width is of a nanometric scale;
wherein the milling comprises scanning a defocused ion beam of the certain width along a longitudinal axis of the each structural element; and
wherein a current intensity of the defocused ion beam decreases with a distance from a middle of the defocused ion beam.

US Pat. No. 10,971,617

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

INNOSCIENCE (ZHUHAI) TECH...

1. A semiconductor device, comprising:a substrate;
a barrier layer, disposed on the substrate;
a first channel layer, disposed on the barrier layer;
a first gate conductor, disposed on the first channel layer;
a first doped semiconductor layer, disposed between the first gate conductor and the first channel layer;
wherein a forbidden band width of the barrier layer is greater than a forbidden band width of the first channel layer;
a first source conductor;
a first ohmic contact, located between the first source conductor and the first channel layer;
wherein the first ohmic contact comprises a p-type category-III-V layer;
a first drain conductor;
a second ohmic contact, located between the first drain conductor and the first channel layer;
wherein the second ohmic contact comprises a p-type category-III-V layer;
a second channel layer, disposed between the substrate and the barrier layer;
a second gate conductor, located on the barrier layer;
a second doped semiconductor layer, disposed between the second gate conductor and the barrier layer;
wherein a forbidden band width of the barrier layer is greater than a forbidden band width of the second channel layer;
a second source conductor, disposed on the barrier layer; and
a second drain conductor, disposed on the barrier layer,
wherein the second drain conductor is electrically connected to the first drain conductor.

US Pat. No. 10,971,616

APPARATUS AND CIRCUITS WITH DUAL THRESHOLD VOLTAGE TRANSISTORS AND METHODS OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:a substrate;
an active layer that is formed over the substrate and comprises a first active portion having a first thickness and a second active portion having a second thickness;
a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and
a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness.

US Pat. No. 10,971,615

HIGH POWER PERFORMANCE GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR WITH LEDGES AND FIELD PLATES

QUALCOMM Incorporated, S...

1. A high electron mobility transistor (HEMT) comprising:a substrate;
a buffer layer disposed above the substrate;
a gallium nitride (GaN) layer disposed above the buffer layer;
an aluminum gallium nitride (AlGaN) layer disposed above the GaN layer;
a source electrode, a gate electrode, and a drain electrode disposed above the AlGaN layer;
one or more n-doped protuberances disposed above on the AlGaN layer and disposed between at least one of:
the gate electrode and the drain electrode; or
the source electrode and the gate electrode, wherein each of the one or more n-doped protuberances is separated from the gate electrode, the drain electrode, and the source electrode; anda metal plate disposed above the one or more n-doped protuberances and separate from the gate electrode, wherein the one or more n-doped protuberances comprise two or more n-doped protuberances having one or more trenches therebetween, and wherein the metal plate comprises one or more protrusions extending into the one or more trenches between the two or more n-doped protuberances.

US Pat. No. 10,971,614

HIGH ELECTRON MOBILITY TRANSISTOR WITH REVERSE ARRANGEMENT OF CHANNEL LAYER AND BARRIER LAYER

SUMITOMO ELECTRIC DEVICE ...

1. A high electron mobility transistor (HEMT), comprising:a substrate;
a barrier layer provided on the substrate, the barrier layer being made of at least one of aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), and indium aluminum gallium nitride (InAlGaN), and having an N-polar surface in a side opposite to the substrate;
a channel layer provided on the barrier layer, the channel layer being made of nitride semiconductor material and having bandgap energy smaller than bandgap energy of the barrier layer and an N-polar surface in a side opposite to the barrier layer;
a layer provided on the channel layer;
a gate electrode provided on the layer,
a source electrode and a drain electrode provided on the channel layer; and
a buffer layer made of gallium nitride (GaN) located between the substrate and the barrier layer,
wherein the layer is excluded from an area between the source electrode and the channel layer, and an area between the drain electrode and the channel layer.

US Pat. No. 10,971,613

SEMICONDUCTOR DEVICES WITH DOPED REGIONS FUNCTIONING AS ENHANCED RESISTIVITY REGIONS OR DIFFUSION BARRIERS, AND METHODS OF FABRICATION THEREFOR

NXP USA, Inc., Austin, T...

1. A method of fabricating a high electron mobility transistor (HEMT), the method comprising the steps of:forming one or more first doped regions at the upper surface of a base semiconductor substrate, wherein the one or more first doped regions include one or more ion species, and each of the one or more first doped regions has a first lower boundary that is located above the lower surface of the base semiconductor substrate, and an upper boundary that coincides with the upper surface of the base semiconductor substrate; and
forming the HEMT over the upper surface of the base semiconductor substrate from a plurality of epitaxially-grown semiconductor layers, wherein the first doped region does not extend into the plurality of epitaxially-grown semiconductor layers, and wherein forming the HEMT includes
disposing a nucleation layer over the one or more first doped regions,
disposing a first semiconductor layer over the nucleation layer, and
disposing a second semiconductor layer over the first semiconductor layer,
wherein a channel is present within the second semiconductor layer and proximate to an upper surface of the second semiconductor layer.

US Pat. No. 10,971,612

HIGH ELECTRON MOBILITY TRANSISTORS AND POWER AMPLIFIERS INCLUDING SAID TRANSISTORS HAVING IMPROVED PERFORMANCE AND RELIABILITY

Cree, Inc., Durham, NC (...

1. A GaN-based high electron mobility transistor (HEMT) device configured to operate for greater than 1000 hours in a high-temperature-reverse-bias (HTRB) operation at 84 V drain bias, wherein the GaN-based HEMT device comprises:a channel layer and a barrier layer sequentially stacked on a substrate;
a source contact comprising a first ohmic portion on the barrier layer, wherein the source contact is shared between a first unit cell transistor and a second unit cell transistor; and
a via extending in the channel layer, the barrier layer, and the substrate to the first ohmic portion of the source contact, wherein the via is between the first unit cell transistor and the second unit cell transistor.

US Pat. No. 10,971,611

PARTICLE DETECTORS

Honeywell International I...

1. A light source for use in a particle detection system, the light source including:a first light emitter for emitting a first beam of light;
a second light emitter for emitting a second beam of light; and
an optical system including a transmission zone through which the first beam of light and the second beam of light are transmitted from the first light emitter and the second light emitter, respectively,
wherein the optical system is arranged such that obstruction of the transmission zone results in a substantially equivalent obstruction of both the first beam of light and the second beam of light;
wherein the optical system includes beam shaping optics adapted to modify a beam shape of either or both of the first beam of light and the second beam of light; and
wherein the beam shaping optics provide the first beam of light and the second beam of light transmitted from the first light emitter and the second light emitter, respectively, with a beam divergence of approximately 10 degrees.

US Pat. No. 10,971,610

HIGH ELECTRON MOBILITY TRANSISTOR

UNITED MICROELECTRONICS C...

1. A high electron mobility transistor (HEMT), comprising:a substrate;
a buffer layer over the substrate;
a GaN layer over the buffer layer;
a first AlGaN layer over the GaN layer;
a first AlN layer over the first AlGaN layer;
a gate recess over the first AlN layer; and
a p-type GaN layer over the first AlN layer.

US Pat. No. 10,971,609

BACK END OF LINE NANOWIRE POWER SWITCH TRANSISTORS

Taiwan Semiconductor Manu...

1. A method for forming an integrated circuit (IC) structure, the method comprising:forming a first layer of metal lines of a first back end of line (BEOL) interconnect structure, wherein the BEOL interconnect structure is formed on a front end of line (FEOL) device layer having a plurality of active devices;
forming a semiconductor nanowire structure on a first metal line of the first layer of metal lines of the first BEOL interconnect structure;
forming a first dielectric layer wrapped around the semiconductor nanowire structure;
forming a metal layer on the first dielectric layer and in direct contact with a second metal line of the first layer of metal lines of the first BEOL interconnect structure, wherein the first and second metal lines are electrically isolated from each other; and
forming a second layer of metal lines of a second BEOL interconnect structure on the semiconductor nanowire structure.

US Pat. No. 10,971,608

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a first surface, and a second surface that is a surface opposite to the first surface and provided with an opening of a trench, the semiconductor substrate including
a drift layer of a first conductivity type,
a carrier storage layer of the first conductivity type, the carrier storage layer being provided on a second surface side of the drift layer facing the second surface and having an impurity concentration higher than an impurity concentration of the drift layer,
a base layer of a second conductivity type, the base layer being provided on the second surface side of the carrier storage layer and reaching the second surface, and
an impurity layer of the first conductivity type selectively provided on the second surface side of the base layer, the trench penetrating the impurity layer, the base layer, and the carrier storage layer to reach the drift layer;
an internal insulating film covering an inner surface of the trench; and
a trench electrode provided in the trench to face the drift layer, the carrier storage layer, the base layer, and the impurity layer via the internal insulating film,
wherein the internal insulating film has a first thickness at a portion facing the base layer, has a second thickness at a portion facing the drift layer, and has the first thickness and the second thickness at a portion facing the carrier storage layer, the second thickness being thicker than the first thickness, and
a width of the trench is tapered from a larger width to a smaller width along at least a portion of the trench that extends from the carrier storage layer through the second surface side of the drift layer into the drift layer in a direction toward a deepest part of the trench electrode, such that the width of the trench at a depth of the deepest part of the trench electrode is smaller than a width of the opening of the trench on the second surface.

US Pat. No. 10,971,607

METHODS OF FORMING NAND CELL UNITS

Micron Technology, Inc., ...

12. A method of forming a NAND cell unit, comprising:forming a select gate comprising gate material and electrically insulative material only partially covering the gate material and leaving an opening;
forming a conductive liner in the opening and against at least one of the gate material and the electrically insulative material; and
forming a string gate spaced from the select gate.

US Pat. No. 10,971,606

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device comprising:forming a shallow trench isolation (STI) structure surrounding a pair of semiconductor fins;
forming a dummy gate layer over the STI structure and the semiconductor fins;
etching a first portion of the dummy gate layer to form a trench through the dummy gate layer until the STI structure is exposed, wherein the trench extends between the semiconductor fins along a lengthwise direction of the semiconductor fins;
forming an insulating structure in the trench through the dummy gate layer;
after forming the insulating structure extending through the dummy gate layer, patterning the dummy gate layer to form a pair of dummy gate structures each of which is across a respective one of the semiconductor fins; and
replacing the dummy gate structures with a pair of metal gate structures.

US Pat. No. 10,971,605

DUMMY DIELECTRIC FIN DESIGN FOR PARASITIC CAPACITANCE REDUCTION

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first device fin;
a second device fin;
a first source/drain component epitaxially grown over the first device fin;
a second source/drain component epitaxially grown over the second device fin;
a first dummy fin structure disposed between the first device fin and the second device fin; and
a gate structure that partially wraps around the first device fin, the second device fin, and the first dummy fin structure;
wherein:
a first portion of the first dummy fin structure is comprised of a first type of dielectric material and is disposed between the first source/drain component and the second source/drain component and outside the gate structure;
a second portion of the first dummy fin structure is disposed underneath the gate structure and is comprised of the first type of dielectric material and a second type of dielectric material disposed over the first type of dielectric material, the second type of dielectric material having a greater dielectric constant than the first type of dielectric material; and
the first portion of the first dummy fin structure and the second portion of the first dummy fin structure have different physical characteristics.

US Pat. No. 10,971,604

GATE ALL AROUND FIN FIELD EFFECT TRANSISTOR

International Business Ma...

1. A method for forming a semiconductor device, comprising:forming a dummy gate over a semiconductor fin;
forming gate spacers on sidewalls of the dummy gate;
forming a second dielectric layer on sidewalls of a channel region of a semiconductor fin and over the gate spacers, wherein the semiconductor fin is surrounded at a fin base by a first dielectric layer;
recessing the first dielectric layer to expose a portion of a sidewall of the channel region of the semiconductor fin, between the recessed first dielectric layer and the second dielectric layer;
etching away the exposed portion of the sidewall to separate the semiconductor fin from an underlying surface in the channel region; and
forming a gate stack in the channel region that completely encircles the semiconductor fin.

US Pat. No. 10,971,603

WAVY CHANNEL FLEXIBLE THIN-FILM-TRANSISTOR ON A FLEXIBLE SUBSTRATE AND METHOD OF PRODUCING SUCH A THIN-FILM-TRANSISTOR

KING ABDULLAH UNIVERSITY ...

1. A method for producing a thin-film-transistor, comprising:forming a flexible substrate on a rigid substrate;
forming a plurality of fins and trenches in a structural layer arranged on the flexible substrate;
forming a wavy gate layer, channel layer, source contact layer, and drain contact layer on each of the plurality of fins and each of a plurality of trenches of the structural layer; and
removing the plurality of fins and trenches having the wavy gate, channel, source contact, and drain contact layers from the rigid substrate.

US Pat. No. 10,971,602

HIGH-K METAL GATE PROCESS AND DEVICE

Taiwan Semiconductor Manu...

1. A device structure comprising:a high-k gate dielectric layer over a semiconductor fin;
a barrier layer over the high-k gate dielectric layer;
a metal silicate layer over the barrier layer;
a work function metal layer over the metal silicate layer; and
a metal fill layer over the work function metal layer.

US Pat. No. 10,971,601

REPLACEMENT METAL GATE STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A structure, comprising:a plurality of gate structures composed of a gate dielectric with a bottom surface which directly contacts a semiconductor layer, spacers and a bottom surface of chamfered spacers over a top surface of the spacers, the chamfered spacers comprising a chamfered side; and
a contact between the gate structures,
wherein the bottom surface of the gate dielectric is at a same level as a bottom surface of the spacers,
the contact comprises a conductive material in direct contact with sides of the spacers and in direct contact with the chamfered side of the chamfered spacers,
a contact cap with a bottom surface in direct contact with a top surface of a metal material of the gate structure,
the chamfered spacers in direct contact with the metal material, and
an oxide material with a bottom surface in direct contact with a top surface of the contact cap and sides of the conductive material.

US Pat. No. 10,971,600

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

Intel Corporation, Santa...

1. A transistor comprising:a gate comprising a gate dielectric over a first portion of a semiconductor fin and a gate electrode over the gate dielectric;
a blocking material on a second portion of the semiconductor fin adjacent the first portion, the blocking material comprising silicon, carbon, and nitrogen;
an interlayer dielectric material on a third portion of the semiconductor fin adjacent to the second portion; and
a gate sidewall spacer on the blocking material and adjacent the gate, wherein the blocking material and the gate sidewall spacer are adjacent to the interlayer dielectric material and between the gate and the interlayer dielectric material.

US Pat. No. 10,971,599

POWER SEMICONDUCTOR DEVICE WITH SELF-ALIGNED SOURCE REGION

Infineon Technologies AG,...

1. A method of forming a power semiconductor device, the method comprising:providing a semiconductor body having a semiconductor body surface;
forming an auxiliary layer above the semiconductor body surface, the auxiliary layer being coupled to the semiconductor body and having an auxiliary layer surface;
forming a plurality of trenches extending from the auxiliary layer surface along a vertical direction through the auxiliary layer into the semiconductor body, wherein two trench sidewalls facing each other of two adjacent ones of the trenches laterally confine a mesa region of the semiconductor body along a first lateral direction, wherein both adjacent trenches comprise a respective trench section protruding out of the semiconductor body surface against the vertical direction by a protrusion distance of at least 50 nm;
filling the trenches with at least one trench filler material;
planarizing the at least one trench filler material to expose the auxiliary layer;
removing the auxiliary layer at least partially while maintaining the protruding trench sections comprising the at least one trench filler material; and
subjecting the mesa region to an implantation processing step for forming a semiconductor zone in the mesa region, wherein the implantation is tilted with respect to the vertical direction by an angle of at least 10°, and wherein the protruding trench sections of the adjacent trenches serve at least partially as a mask during the tilted implantation.

US Pat. No. 10,971,598

METHOD OF FORMING HETEROJUNCTION BIPOLAR TRANSISTOR (HBT)

Keysight Technologies, In...

20. A method of forming a heterojunction bipolar transistor (HBT) structure, comprising:providing an HBT epitaxial layer structure formed over a first substrate wafer;
inverting the HBT epitaxial layer structure and the first substrate wafer, and attaching the HBT epitaxial layer structure to a second substrate wafer via glue layers;
removing the first substrate wafer;
forming a first subcollector metal layer over the HBT epitaxial layer structure;
inverting the first subcollector metal layer and the HBT epitaxial layer structure, and thermal compression bonding the first subcollector metal layer to a second subcollector metal layer on a third substrate wafer; and
removing the second substrate wafer by wet etching, using the first and second subcollector metal layers as an etch stop.

US Pat. No. 10,971,597

SELF-ALIGNED BASE AND EMITTER FOR A BIPOLAR JUNCTION TRANSISTOR

GLOBALFOUNDRIES U.S. INC....

1. A device structure for a bipolar junction transistor, the device structure comprising:a trench isolation region surrounding an active region;
a collector in the active region;
a base layer including a first portion and a second portion that are located over the active region, the base layer having a top surface;
an emitter positioned on the first portion of the base layer, the emitter having a sidewall;
an extrinsic base layer on the second portion of the base layer, the extrinsic base layer having a thickness, the extrinsic base layer having a side surface adjacent to the emitter, and the side surface of the extrinsic base layer spaced from the sidewall of the emitter by a gap; and
a spacer in the gap between the sidewall of the emitter and the side surface of the extrinsic base layer,
wherein the side surface is inclined over a first portion of the thickness relative to the top surface of the base layer in a first direction away from the emitter and is in contact with the spacer over a second portion of the thickness.

US Pat. No. 10,971,596

SEMICONDUCTOR DEVICE WITH REDUCED FLICKER NOISE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a source region and a drain region disposed in a semiconductor substrate, wherein the source region is laterally spaced from the drain region;
a gate stack disposed over the semiconductor substrate and disposed between the source region and the drain region;
a cap layer disposed over the gate stack, wherein a first lower surface of the cap layer contacts a first upper surface of the gate stack;
sidewall spacers disposed along sides of the gate stack and the cap layer;
a resist protective oxide (RPO) layer disposed over the cap layer, wherein the RPO layer extends along sides of the sidewall spacers to the semiconductor substrate; and
a contact etch stop layer (CESL) disposed over the RPO layer, the source region, and the drain region.

US Pat. No. 10,971,595

MOFSET AND METHOD OF FABRICATING SAME

Nexchip Seminconductor Co...

1. A metal-oxide-semiconductor field-effect transistor (MOSFET), comprising:a substrate;
a shallow trench isolation (STI) region formed in the substrate;
an active area, formed in the substrate and delimited by the STI region, the active area comprising a source region, a drain region and a channel region located between the source and drain regions; and
a gate formed over the channel region, the gate comprising a first polysilicon layer and a second polysilicon layer, the first polysilicon layer being a layer of lightly-doped polysilicon, the first polysilicon layer covering a channel edge between the channel region and the STI region such that the first polysilicon layer covers a first portion of the channel region and a part of the STI region without completely covering the channel region, the second polysilicon layer being a layer of doped polysilicon that covers the first polysilicon layer and a second portion of the channel region not covered by the first polysilicon layer, the lightly-doped polysilicon being implanted with ions of a same conductivity type as ions implanted in the second polysilicon layer and in the source and drain regions, and the lightly-doped polysilicon being implanted with the ions of a concentration lower than that of the ions implanted in the second polysilicon layer.

US Pat. No. 10,971,594

SEMICONDUCTOR DEVICE HAVING MODIFIED PROFILE METAL GATE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a semiconductor substrate having a top surface; and
a gate structure disposed over the semiconductor substrate, wherein the gate structure includes:
a first layer of a substantially U-shaped configuration and extending to a first height above the top surface;
a second layer having a substantially U-shaped configuration and extending to a second height above the top surface;
a third layer having a substantially U-shaped configuration and extending to a third height above the top surface, wherein the first height, the second height and third height are different; and
a fill layer disposed over the first, second and third layers wherein a top surface of the fill layer is disposed at a fourth height from the top surface of the semiconductor substrate, wherein the fourth height is greater than the first, second and third heights, wherein the second height is greater than the first height.

US Pat. No. 10,971,593

OXYGEN RESERVOIR FOR LOW THRESHOLD VOLTAGE P-TYPE MOSFET

International Business Ma...

11. A p-type FinFET comprising:a channel;
a source electrically connected to a source side of the channel;
a drain electrically connected to a drain side of the channel;
a gate stack comprising a high k dielectric material disposed on the channel and a work function metal (WFM) disposed on the high k dielectric material;
an oxygen reservoir disposed on the gate stack, the oxygen reservoir made of a reservoir material, the reservoir material containing oxygen; and
a low resistivity metal layer contact electrically connected to the work function metal (WFM) as well as being physically disposed above a top of the oxygen reservoir.

US Pat. No. 10,971,592

SEMICONDUCTOR DEVICE WITH GATE ELECTRODE HAVING SIDE SURFACES DOPED WITH CARBON

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a semiconductor substrate;
a gate insulating film on the semiconductor substrate; and
a gate electrode on the gate insulating film, wherein
the gate electrode includes
a first layer containing polycrystalline silicon,
a second layer between the first layer and the gate insulating film and containing polycrystalline silicon and carbon,
a third layer on an upper surface of the first layer and containing polycrystalline silicon and carbon,
a fourth layer on a first side surface of the first layer and containing polycrystalline silicon and carbon, and
a fifth layer on a second side surface of the first layer and containing polycrystalline silicon and carbon.

US Pat. No. 10,971,591

POWER SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

4. A power semiconductor device comprising:a semiconductor substrate having a first main surface and a second main surface disposed opposite the first main surface;
a plurality of cell regions disposed on the first main surface;
a first main electrode disposed over the plurality of cell regions; and
a second main electrode disposed above the second main surface,
wherein the plurality of cell regions each include
a semiconductor layer connected to the first main electrode,
a control electrode, and
an interlayer insulating film covering the control electrode, and electrically insulating the control electrode from the first main electrode, a step being formed between the semiconductor layer and the interlayer insulating film,
the first main electrode includes
a first metal film disposed over the plurality of cell regions, the first metal film being made of metal having an Al concentration greater than or equal to 95 wt %,
an intermediate film disposed on the first metal film, the intermediate film containing primary-constituent phases each of which is formed of a metal compound of at least one kind of element selected from a group consisting of a group 4A element, a group 5A element, and a group 6A element on a long-form periodic table, and at least one kind of element selected from a group consisting of C and N, the intermediate film containing a secondary-constituent phase that is formed of an iron group element and joins the primary-constituent phases to each other, and
a second metal film disposed on the intermediate film, the second metal film being made of metal having an Al concentration greater than or equal to 95 wt %, and
the intermediate film has a higher degree of hardness than the second metal film and is a plane-shaped mesh film, such that the first metal film and the second metal film are in contact with each other via openings in the plane-shaped mesh film.

US Pat. No. 10,971,590

TRANSISTOR LAYOUT TO REDUCE KINK EFFECT

Taiwan Semiconductor Manu...

1. An integrated chip, comprising:a substrate having interior surfaces that define a trench within an upper surface of the substrate;
one or more dielectric materials disposed within the trench;
a source region disposed within the substrate;
a drain region disposed within the substrate and separated from the source region along a first direction; and
a gate structure over the upper surface of the substrate between the source region and the drain region, wherein the upper surface of the substrate has a first width directly below the gate structure that is larger than a second width of the upper surface of the substrate within the source region or the drain region, the first width and the second width measured along a second direction that is perpendicular to the first direction.

US Pat. No. 10,971,589

LOW-K FEATURE FORMATION PROCESSES AND STRUCTURES FORMED THEREBY

Taiwan Semiconductor Manu...

1. A method comprising:forming a low-k layer using an Atomic Layer Deposition (ALD) process, the ALD process comprising:
for a cycle, flowing a silicon-carbon source precursor having a chemical structure comprising at least one carbon atom bonded between two silicon atoms and wherein each chemical bond of the two silicon atoms that are not bonded to the at least one carbon atom is bonded to a halogen element; and
for the cycle, flowing an oxygen source precursor; and
repeating the cycle at least one time, wherein a flow rate of the silicon-carbon source precursor is modified from a first cycle to a second cycle.

US Pat. No. 10,971,588

SEMICONDUCTOR DEVICE INCLUDING FINFET WITH SELF-ALIGN CONTACT

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first fin structure extending in a first direction and having a source/drain region;
a second fin structure extending in the first direction and having a source/drain region;
an isolation insulating layer, from which upper portions of the first and second fin structures protrude;
an interlayer dielectric layer disposed over the isolation insulating layer;
a first source/drain contact layer disposed on the source/drain region of the first fin structure, a part of the first source/drain contact layer being disposed over the isolation insulating layer; and
a separation insulating layer disposed adjacent to the first source/drain contact layer, wherein:
the separation insulating layer is disposed between the first fin structure and the second fin structure,
an end of the first source/drain contact layer is in contact with a first face of the separation insulating layer,
no source/drain contact layer contacting a second face of the separation insulating layer opposite to the first face is disposed on the source/drain region of the second fin structure, and
the separation insulating layer is made of an insulating material different from the isolation insulating layer and the interlayer dielectric layer.

US Pat. No. 10,971,587

GAN LATERAL VERTICAL JFET WITH REGROWN CHANNEL AND DIELECTRIC GATE

Gangfeng Ye, Fremont, CA...

1. A method comprising:growing as-grown epitaxial layers on top of a N+ GaN substrate, wherein the growing as-grown epitaxial layers comprising growing an N-type GaN drift layer over the N+ GaN substrate layer, and growing a P-type block layer over the N-type GaN drift layer;
re-growing a lateral channel layer over the P-type block layer;
forming a contact gap by selective area regrowth during the regrowing the lateral channel layer or etching through the lateral channel after the regrowing;
implanting N+ in the lateral channel layer to form an implanted N+ source region; and
depositing source metal in the contact gap and over a part of the lateral channel layer such that the source metal is attached to the P-type block layer and the implanted N+ source region.

US Pat. No. 10,971,586

DOUBLE HEIGHT CELL REGIONS, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHOD OF GENERATING A LAYOUT DIAGRAM CORRESPONDING TO THE SAME

TAIWAN SEMICONDUCTOR MANU...

11. A semiconductor device comprising:fins extending substantially parallel to a first direction; and
gate structures formed over corresponding ones of the fins and extending substantially parallel to a second direction which is substantially perpendicular to the first direction, the gate structures being configured to include:
dummy gate structures; and
active gate structures; and
wherein:
the fins and the gate structures are organized into cell regions; and
a boundary, relative to the first direction, between first and second one of the cell regions is defined by a consecutive sequence of a first active gate structure, a first dummy gate structure and a second active gate structure; and
the fins are configured to include:
dummy fins;
first active fins having a first conductivity type; and
second active fins having a second conductivity type; and
the fins and the gate structures are located in corresponding ones of the cell regions; and
each cell region, relative to the second direction, includes:
a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region;
a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and
a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.

US Pat. No. 10,971,585

GATE SPACER AND INNER SPACER FORMATION FOR NANOSHEET TRANSISTORS HAVING RELATIVELY SMALL SPACE BETWEEN ADJACENT GATES

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a semiconductor device, the method comprising:performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate;
wherein the fabrication operations include:
forming a gate spacer along a gate region of the nanosheet FET device;
forming channel nanosheets to a desired final channel nanosheet width dimension (Wf) for each of the channel nanosheets;
forming an inner spacer between the channel nanosheets;
wherein the gate spacer and the inner spacer comprise the same type of spacer material;
wherein forming the gate spacer and the inner spacer comprises, subsequent to forming the channel nanosheets to the desired Wf, conformally depositing a layer of the spacer material having a first thickness dimension to extend along a sidewall of the gate region, sidewalls of the channel nanosheets, and within a space between the channel nanosheets;
wherein forming the gate spacer and the inner spacer further comprises performing an etch operation that removes a portion of the layer of spacer material that extends along sidewalls of the channel nanosheets; and
separately from forming the gate spacer and the inner spacer by performing the etch operation that removes the portion of the layer of spacer material that extends along sidewalls of the channel nanosheets, trimming a portion of the layer of the spacer material that is along the sidewall of the gate region such that the portion of the spacer layer that is along the sidewall of the gate region comprises a second thickness dimension that is less than the first thickness dimension;
wherein the gate spacer comprises the portion of the layer of the spacer material that comprises the second thickness dimension and is along the sidewall of the gate region;
wherein the inner spacer comprises a portion of the layer of the spacer material that is within the space between the channel nanosheets.

US Pat. No. 10,971,584

LOW CONTACT RESISTANCE NANOWIRE FETS

INTERNATIONAL BUSINESS MA...

1. A method for forming a nanowire transistor, the method comprising:depositing a fill material such that the fill material contacts ends of recessed first nanowires of a stack of nanowires between second nanowires of the stack of nanowires extending beyond the recessed first nanowires;
transforming, by annealing the fill material, portions of the fill material into inner spacers at ends of the recessed first nanowires, the inner spacers being self-aligned with gate spacers formed on sides of a dummy gate disposed over and around the stack of nanowires;
after forming the inner spacers, removing remaining portions of the fill material;
growing source and drain regions from surfaces of the second nanowires beyond a width defined by outer surfaces of the gate spacers such that the second nanowires extend into the source and drain regions outside of the width defined by outer surfaces of the gate spacers; and
forming a gate between the gate spacers, including replacing the dummy gate and the recessed first nanowires with a gate conductor such that the second nanowires extend through the gate conductor.