US Pat. No. 10,892,266

NONVOLATILE MEMORY STRUCTURE AND ARRAY

eMemory Technology Inc., ...

1. A nonvolatile memory structure, comprising:a substrate comprising an oxide defined (OD) region and an erase region;
a select transistor disposed on the OD region; and
a floating-gate transistor disposed on the OD region between the select transistor and the erase region, wherein the floating-gate transistor comprises a floating gate having an extended portion capacitively coupled to the erase region, and the extended portion has an extending direction parallel to a first direction, wherein
the OD region has at least one addition region protruding in a second direction and partially overlapped with the floating gate, wherein the second direction is vertical to the first direction, and
an area of the at least one addition region is A1, an overlap area between the floating gate and the addition region is A2, and a ratio of A2 to A1 is 0.5 or more.

US Pat. No. 10,892,265

WORD LINE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

MACRONIX INTERNATIONAL CO...

1. A word line structure, comprising:a stack structure disposed on a substrate; and
a metal silicide structure disposed on the stack structure, wherein the metal silicide structure comprises a first metal element, a second metal element, and a silicon element, the first metal element is different from the second metal element, concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate, and a concentration of the silicon element does not gradually increase or decrease along the direction from the top surface of the metal silicide structure to the substrate.

US Pat. No. 10,892,264

MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL

Micron Technology, Inc., ...

1. An apparatus comprising:a memory cell including:
a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure; and
a second transistor including a second channel region electrically coupled to the charge storage structure;
a first data line electrically coupled to the first channel region;
a second data line electrically coupled to the first channel region;
a third data line electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line, each of the first, second, and third data lines including a length extending in a first direction;
a first access line located on a first level of the apparatus and separated from the first channel by a first dielectric; and
a second access line located on a second level of the apparatus and separated from the second channel by a second dielectric, the charge storage structure located on a level of the apparatus between the first and second levels, and each of the first and second access lines including length extending in a second direction.

US Pat. No. 10,892,263

METHODS OF FABRICATING SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A method of fabricating a semiconductor device, the method comprising:forming a gate structure on a core-peri region of a substrate, wherein the substrate further comprises a cell region, and the gate structure comprises a conductive film and a gate stack insulation film that comprises a side portion contacting a sidewall of the conductive film and a top portion extending on an upper surface of the conductive film;
forming a gate spacer on a sidewall of the gate structure;
forming a first impurity region adjacent the gate spacer in the core-peri region of the substrate by performing a first ion implantation process;
removing the gate spacer;
forming a second impurity region in the core-peri region of the substrate between the gate structure and the first impurity region by performing a second ion implantation process;
forming a stress film on the gate structure, an upper surface of the first impurity region, and an upper surface of the second impurity region, wherein the stress film contacts the side portion and the top portion of the gate stack insulation film; and
forming a recrystallization region by crystallizing the first impurity region and the second impurity region by performing an annealing process.

US Pat. No. 10,892,262

SEMICONDUCTOR DEVICE HAVING JUNCTIONLESS VERTICAL GATE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

SK hynix Inc., Icheon (K...

1. A semiconductor device comprising:an active pillar extending upward from a top surface of a substrate and including:
a first source/drain region provided at a first level,
a channel region provided at a second level higher than the first level, and
a second source/drain region provided at a third level higher than the second level;
a bit line coupled to the first source/drain region and buried within the substrate; and
a gate electrode coupled to the channel region,
wherein the first and the second source/drain regions and the channel region have the same polarities,
wherein the bit line is disposed over a liner insulation layer formed along inner sidewalls of a recess formed in the substrate, and
wherein a top surface of the bit line and a top surface of the liner insulation layer are level with the top surface of the substrate.

US Pat. No. 10,892,261

METAL RESISTOR AND SELF-ALIGNED GATE EDGE (SAGE) ARCHITECTURE HAVING A METAL RESISTOR

Intel Corporation, Santa...

1. A semiconductor structure, comprising:a plurality of semiconductor fins protruding through a trench isolation region above a substrate;
a first gate structure over a first of the plurality of semiconductor fins;
a second gate structure over a second of the plurality of semiconductor fins;
a gate edge isolation structure laterally between and in contact with the first gate structure and the second gate structure, the gate edge isolation structure on the trench isolation region and extending above an uppermost surface of the first gate structure and the second gate structure; and
a metal layer on the gate edge isolation structure and electrically isolated from the first gate structure and the second gate structure.

US Pat. No. 10,892,260

CAPACITOR

HIMAX TECHNOLOGIES LIMITE...

1. A capacitor comprising:a first transistor having a first terminal used to couple to a first terminal of the capacitor;
a second transistor having a first terminal used to couple to a second terminal of the capacitor; and
a control circuit coupled between the first transistor and the second transistor, wherein the control circuit comprises:
a first switch having a first terminal used to couple to a first voltage, wherein a second terminal of the first switch is coupled to a control terminal of the first transistor, and when the first switch is turned on, the first voltage turns off the first transistor;
a second switch having a first terminal used to couple to a second voltage, wherein a second terminal of the second switch is coupled to a control terminal of the second transistor, and when the second switch is turned on, the second voltage turns off the second transistor;
a third switch having a first terminal used to couple to the second voltage, wherein a second terminal of the third switch is coupled to the control terminal of the first transistor; and
a fourth switch having a first terminal used to couple to the first voltage, wherein a second terminal of the fourth switch is coupled to the control terminal of the second transistor,
wherein in a power saving mode, the control circuit turns off the first transistor and the second transistor; and
wherein in a normal mode, the control circuit turns on the first transistor and the second transistor, a second terminal of the second transistor is coupled to the control terminal of the first transistor through the control circuit, and the control terminal of the second transistor is coupled to a second terminal of the first transistor through the control circuit.

US Pat. No. 10,892,259

APPARATUS CONTAINING CIRCUIT-PROTECTION DEVICES

Micron Technology, Inc., ...

1. An apparatus, comprising:an array of memory cells comprising a plurality of strings of series-connected memory cells;
a plurality of data lines, each data line of the plurality of data lines selectively connected to a respective set of strings of series-connected memory cells of the plurality of strings of series-connected memory cells;
peripheral circuitry for access of the array of memory cells;
a first transistor comprising a control gate, a first source/drain connected to a first contact for connection to the peripheral circuitry, and a second source/drain connected to a second contact for connection to a particular data line of the plurality of data lines; and
a second transistor comprising a control gate, a first source/drain connected to the second contact, and a second source/drain connected to a third contact for connection to a common source selectively connected to each string of series-connected memory cells of the respective set of strings of series-connected memory cells for the particular data line.

US Pat. No. 10,892,258

ESD-ROBUST STACKED DRIVER

NXP B.V., Eindhoven (NL)...

1. A driver circuit with electrostatic discharge (ESD) protection comprising:a power supply conductor;
a conductive pad;
an output driver transistor formed in a substrate or well region and electrically coupled between a circuit element and the conductive pad, the output driver transistor comprising a first MOSFET gate electrode coupled to receive a control signal, a source node coupled to the circuit element, and a drain node coupled to the conductive pad;
an ESD bypass transistor formed in the substrate or well region and electrically coupled in series with the output driver transistor between the power supply conductor and the source node of the output driver transistor, the ESD bypass transistor comprising a second MOSFET gate electrode and a source node coupled directly or indirectly to the power supply conductor and a drain node coupled to the source node of the output driver transistor; and
one or more conductive interconnect layers for connecting the ESD bypass transistor in parallel with the circuit element so that the ESD bypass transistor is in an off-state during normal operation and is activated to form a parasitic bipolar junction transistor with the output driver transistor to conduct ESD current between the power supply conductor and the conductive pad during ESD events.

US Pat. No. 10,892,257

FOLDABLE DISPLAY DEVICE

InnoLux Corporation, Mia...

1. A foldable display device including a first display region, a second display region, and a foldable display region connecting the first display region and the second display region, the foldable display device comprising:a flexible substrate;
a plurality of first light emitting units disposed on the flexible substrate in the first display region;
a plurality of second light emitting units disposed on the flexible substrate in the foldable display region;
a first protector protecting at least one of the first light emitting units; and
a second protector protecting at least one of the second light emitting units;
wherein a ratio of a thickness of the first protector to a thickness of the flexible substrate in the first display region is defined as a first ratio, a ratio of a thickness of the second protector to a thickness of the flexible substrate in the foldable display region is defined as a second ratio, and the second ratio is greater than the first ratio, and the thickness of the second protector is greater than the thickness of the first protector.

US Pat. No. 10,892,256

LIGHT EMITTING DISPLAY SYSTEM HAVING IMPROVED FIRE PERFORMANCE

Nanolumens Acquisition, I...

1. A light emitting display component having improved fire performance comprising:a) a plurality of light emitting elements fixed on a substrate in a predetermined pattern collectively creating a viewing plane for the viewing of visual media;
b) a mask component having a plurality of apertures disposed to match said predetermined pattern of light emitting elements, the mask component attached to said substrate, each of said light emitting elements visible through a corresponding aperture in said mask component, said mask component comprising a halogen free material;
c) said substrate further characterized in that it comprises a printed circuit board of less than 1.6 mm thickness, the printed circuit board comprising:
d) a woven fiberglass portion comprising at least 57% by weight of the printed circuit board;
e) a resin portion comprising less than about 43% by weight of the printed circuit board, said resin portion being a halogen free material;
f) each light emitting element comprising:
i) a plurality of light emitting devices disposed in a cavity of a rigid outer housing, the rigid housing comprising a halogen free polymer;
ii) an optical encapsulant disposed within said rigid outer housing, said optical encapsulant encapsulating said plurality of light emitting devices, the optical encapsulant having a halogen free formula.

US Pat. No. 10,892,255

METHOD OF MANUFACTURING LIGHT EMITTING MODULE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light emitting module includinga substrate,
a light emitting element having an electrode formation surface comprising a positive and negative pair of element electrodes, and a light emitting surface on a side opposite to the electrode formation surface,
a pair of wiring electrodes respectively connected to the element electrodes, and
a light reflective resin layer, wherein
the method of manufacturing the light emitting module comprising:
placing the light emitting element on a support member, in a state with the electrode formation surface facing upward, and the light emitting surface facing downward;
forming a coating layer on the support member, surrounding the light emitting element;
forming the wiring electrodes extending respectively from the element electrodes over the coating layer;
forming the light reflective resin layer on the wiring electrodes and the coating layer;
joining the substrate on top of the light reflective resin layer,
removing the support member; and
removing the coating layer.

US Pat. No. 10,892,254

DEFECT-TOLERANT LAYOUT AND PACKAGING FOR GAN POWER DEVICES

5. A method for making a gallium nitride (GaN) power switching device, comprising:preparing at least one die comprising a plurality of sub-devices, wherein each sub-device is a switching device;
distinguishing functional sub-devices from any defective sub-devices in the at least one die according to an identifying mark on defective sub-devices; and
packaging the at least one die by selectively connecting together in parallel only functional sub-devices in the at least one die;
wherein the at least one die is rectangular and the plurality of sub-devices are each diamond-shaped, and each three of the diamond-shaped sub-devices are in a high-density hexagonal arrangement;
wherein the selectively connecting together in parallel only functional sub-devices in the at least one die provides the GaN power switching device.

US Pat. No. 10,892,253

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device manufacturing method comprising:bonding a rear surface of a chip having electrodes on both sides thereof to a front surface of a substrate;
providing, to an entirety of the front surface of the substrate to which the chip is bonded, a first plating protective film having an opening at a position which is on the front surface of the chip and corresponds to an electrode at which plating is to be formed, after the bonding;
plating the electrode of the chip after the providing while the first plating protective film covers the entirety of the front surface other than the opening; and
removing, in a single process step without any intervening process, all of the first plating protective film from the entirety of the front surface of the substrate, after the plating, wherein
in the providing, a second plating protective film is pasted onto a rear surface of the substrate, and a peripheral portion of a face of the first plating protective film is adhered face-to-face to a peripheral portion of a face of the second plating protective film along an edge portion of the substrate.

US Pat. No. 10,892,252

FACE-TO-FACE MOUNTED IC DIES WITH ORTHOGONAL TOP INTERCONNECT LAYERS

XCELSIS CORPORATION, San...

1. A method of fabricating a three-dimensional (3D) circuit, the method comprising:selecting (i) a first integrated circuit (IC) die comprising a first semiconductor substrate and a first set of interconnect layers defined on top of the first semiconductor substrate, and (ii) a second IC die comprising a second semiconductor substrate and a second set of interconnect layers defined on top of the second semiconductor substrate, said first and second sets of interconnect layers having similar sets of alternating preferred wiring directions;
rotating the second IC die by 90 degrees; and
face-to-face mounting the first and second IC dies so that an outermost interconnect layer of the first IC die has a preferred wiring direction that is orthogonal to the preferred wiring direction of an outermost interconnect layer of the second IC die.

US Pat. No. 10,892,251

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a wiring board;
a controller chip provided on the wiring board, the controller chip sealed by a first resin layer;
a nonvolatile memory chip provided on the first resin layer, the nonvolatile memory chip and the first resin layer sealed by a second resin layer;
a second bonding wire, sealed by the first resin layer, that connects a pad for electric power supply wiring of the controller chip to the wiring board; and
a first bonding wire, sealed by the first resin layer, that connects a pad for signal wiring of the controller chip to the wiring board, wherein a palladium (Pd) content of the first bonding wire is greater than a Pd content of the second bonding wire.

US Pat. No. 10,892,250

STACKED PACKAGE STRUCTURE WITH ENCAPSULATION AND REDISTRIBUTION LAYER AND FABRICATING METHOD THEREOF

Powertech Technology Inc....

1. A stacked package structure, comprising:a metal casing having a lateral portion and a plurality of longitudinal portions extending from an inner surface of the lateral portion;
a stacked chipset having:
an active surface having a plurality of metal pads; and
a rear surface opposite to the active surface and adhered to the inner surface of the lateral portion of the metal casing;
an encapsulation encapsulating the stacked chipset and all outsides of the longitudinal portions of the metal casing, wherein a plurality of surfaces of the plurality of metal pads, each surface of a plurality free ends of the longitudinal portions and an outer surface of the encapsulation are coplanar to constitute a coplanar surface; and
a redistribution layer directly formed on the coplanar surface constituted by the surfaces of the plurality of metal pads, each surface of the free ends of the longitudinal portions and the outer surface of the encapsulation, wherein the redistribution layer electrically connecting to the plurality of metal pads of the stacked chipset.

US Pat. No. 10,892,249

CARRIER AND INTEGRATED MEMORY

International Business Ma...

1. A method of integrated circuit (IC) carrier fabrication comprising:joining a memory, a heat spreader, and a IC chip carrier with a dielectric material such that the heat spreader contacts a sidewall of the memory and such that a contact surface of the memory and an IC chip facing surface of the dielectric material are coplanar with a IC chip facing surface of the carrier; and
forming a vertical interconnect access (VIA) within the heat spreader and within the dielectric material from the IC chip facing surface of the dielectric material to a system facing surface of the dielectric material.

US Pat. No. 10,892,248

MULTI-STACKED DIE PACKAGE WITH FLEXIBLE INTERCONNECT

Intel Corporation, Santa...

1. An apparatus comprising:a first die having at least one bond pad;
a first flexible layer comprising an anisotropic conductive material, wherein the first flexible layer is adjacent to the at least one bond pad such that it makes an electrical contact with the at least one bond pad;
a second flexible layer comprising a conductive metal, wherein the second layer is adjacent to the first flexible layer;
a second die having at least one bond pad;
a fourth flexible layer comprising an anisotropic conductive material, wherein the fourth flexible layer is adjacent to the at least one bond pad of the second die such that it makes an electrical contact with the at least one bond pad of the second die; and
a fifth flexible layer comprising a conductive metal, wherein the fifth flexible layer is adjacent to the fourth layer.

US Pat. No. 10,892,247

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

Infineon Technologies AG,...

1. A method of soldering a conductor to an aluminum metallization, the method comprising:substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer;
removing metal oxides from the substitute metal oxide layer or substitute metal alloy oxide layer by applying a flux material to the substitute metal oxide layer or to the substitute metal alloy oxide layer to generate a reduced substitute metal layer or substitute metal alloy layer; and
soldering the conductor to the aluminum metallization via the reduced substitute metal layer or reduced substitute metal alloy layer using a solder material.

US Pat. No. 10,892,246

STRUCTURES AND METHODS FOR LOW TEMPERATURE BONDING USING NANOPARTICLES

Invensas Corporation, Sa...

6. An assembly, comprising:a first component including a substrate having a first surface and a plurality of first conductive elements exposed at the first surface, each first conductive element having a top surface generally facing in a first direction, the top surface of each first conductive element exposed in a recess extending below the first surface; and
a second component including a substrate having a major surface and a plurality of second conductive elements exposed at the major surface, each second conductive element having a top surface generally facing in a second direction opposite the first direction, the top surface of each second conductive element exposed in a recess extending below the major surface,
the first conductive elements being joined with the second conductive elements, such that the top surfaces of the first conductive elements at least partially confront the top surfaces of the second conductive elements,
each first conductive element being electrically interconnected with a corresponding one of the second conductive elements by a bond region including impurities that show structural evidence of the use of conductive nanoparticles having long dimensions smaller than 100 nanometers in a joining process, each bond region penetrating at least partially into the first conductive element and the second conductive element,
wherein at least one of the substrates of the first component and the second component has a metal element extending in a respective plane in first and second transverse directions within the respective substrate, the metal element configured to provide electromagnetic shielding to reduce signal noise of signals traveling between the first and second conductive elements.

US Pat. No. 10,892,245

SEMICONDUCTOR SWITCHING DEVICE

ABB Power Grids Switzerla...

1. A semiconductor switching device comprising:a semiconductor element having a cathode side and an anode side opposite to the cathode side; and
a housing, wherein the housing comprises:
a cathode pole piece arranged on the semiconductor element on the cathode side;
an anode pole piece is arranged on the semiconductor element on the anode side, wherein the cathode pole piece and the anode pole piece laterally project beyond the semiconductor element; and
a spring system laterally surrounding the semiconductor element for clamping the semiconductor element between the cathode pole piece and anode pole piece, wherein the spring system comprises a ring-shaped washer laterally surrounding the semiconductor element, the washer having a first side and second side opposite to the first side;
wherein the washer is made of a material that keeps its shape reproducibly under deformation at least up to a spring deflection;
wherein the washer is deflectable between the cathode pole piece and the anode pole piece by a first deflection element that comprises a plurality of first protruding elements that contact the washer in a first contact area of the washer on the first side, and by a second deflection element that comprises a plurality of second protruding elements that contact the washer in a second contact area of the washer on the second side;
wherein the first protruding elements are spaced from each other and wherein the second protruding elements are spaced from each other and offset from the first protruding elements so that the first contact area is laterally displaced to the second contact area and the first contact area and the second contact area are arranged lateral to each other in a plane parallel to the cathode side; and
wherein the first deflection element and the second deflection element are adapted to deflect the washer during clamping by a strain distance that is less or equal to the spring deflection, wherein the strain distance is sufficiently large that in a clamped condition an electrical contact is achievable between the cathode pole piece, the semiconductor element and the anode pole piece.

US Pat. No. 10,892,244

APPARATUS AND METHOD FOR SECURING SUBSTRATES WITH VARYING COEFFICIENTS OF THERMAL EXPANSION

Cerebras Systems Inc., L...

1. An integrated circuit board assembly comprising:a printed circuit board (PCB) comprising a first plurality of conducting pads arranged on a first surface of the PCB;
an integrated circuit wafer comprising a second plurality of conducting pads arranged on a second surface of the integrated circuit wafer; and
a compliant connector directly connected to the first surface and the second surface and connecting the first plurality of conducting pads to the second plurality of conducting pads, the compliant connector loaded with a mechanical stress that dynamically changes based on a thermal expansion mismatch between the PCB and integrated circuit wafer, wherein the compliant connector forms an arcuate electrical pathway of varying radii between one or more of the first plurality and one or more of the second plurality of conducting pads.

US Pat. No. 10,892,243

ANISOTROPIC ELECTRICALLY CONDUCTIVE FILM AND CONNECTION STRUCTURE

DEXERIALS CORPORATION, T...

1. An anisotropic electrically conductive film comprising:an electrically insulating adhesive layer; and
electrically conductive particles disposed in the electrically insulating adhesive layer, wherein:
the electrically conductive particles are arranged such that first axes, along which the electrically conductive particles are arranged at a predetermined particle pitch, are arranged side by side at a predetermined axis pitch,
the electrically conductive particles are substantially spherical,
directions of all sides of a triangle formed by an electrically conductive particle P0, an electrically conductive particle P1, and an electrically conductive particle P2 are oblique to a film width direction of the anisotropic electrically conductive film, the electrically conductive particle P0 being any one of the electrically conductive particles at any one of the first axes, the electrically conductive particle P1 being at the one of the first axes and adjacent to the electrically conductive particle P0, the electrically conductive particle P2 being at another one of the first axes that is adjacent to the one of the first axes, and the electrically conductive particle P2 being spaced from the electrically conductive particle P0 by a minimum spacing, and
the number density of the electrically conductive particles ranges from 40 to 100000 per mm2.

US Pat. No. 10,892,241

SUBSTRATE DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING SUBSTRATE DEVICE

SONY CORPORATION, Tokyo ...

1. A substrate device, comprising:a substrate;
an electrical connection unit on the substrate;
a metal post on the electrical connection unit; and
a metal film formed in one body from a tip surface of the metal post to at least part of a side surface of the metal post, wherein
a wettability of the metal film to a solder material is lower than a wettability of the metal post to the solder material.

US Pat. No. 10,892,240

SEMICONDUCTOR FABRICATION APPARATUS AND SEMICONDUCTOR FABRICATION METHOD

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor fabrication method comprising:adjusting a pitch of at least part of a plurality of transfer pins of a transfer plate, the plurality of transfer pins transferring a flux onto a plurality of lands on a semiconductor substrate; and
contacting the plurality of transfer pins after the pitch is adjusted, with the corresponding one of the lands to transfer fluxes attached to tips of the plurality of transfer pins onto the respective plurality of lands,
wherein adjusting the pitch heats at least one of the transfer plate and a holder movable with the transfer plate.

US Pat. No. 10,892,239

BOND PAD RELIABILITY OF SEMICONDUCTOR DEVICES

GLOBALFOUNDRIES Singapore...

1. A bond pad structure comprising:a dielectric layer;
at least one bond pad in the dielectric layer, having a bond pad top surface;
a passivation layer having an interface with a first portion of the bond pad top surface;
an opening in the passivation layer over the bond pad, wherein the opening has sidewalls;
a low-k barrier layer covering the sidewalls of the opening and a second portion of the bond pad top surface; and
protective structures over the low-k barrier layer at the sidewalls of the opening.

US Pat. No. 10,892,238

CIRCUIT STRUCTURE AND CHIP PACKAGE

Global Unichip Corporatio...

1. A circuit structure, comprising:a first signal line, comprising a first line segment, a first ball grid array pad, and a first through hole disposed between the first line segment and the first ball grid array pad;
a second signal line, comprising a second line segment, a second ball grid array pad, and a second through hole disposed between the second line segment and the second ball grid array pad, wherein in a top view direction:
a line connecting the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance;
a line connecting the center of the first through hole and the center of the second through hole has a second distance; and
the first distance is less than the second distance;
a third signal line, forming a first differential pair with the first signal line; and
a fourth signal line, forming a second differential pair with the second signal line.

US Pat. No. 10,892,237

METHODS OF FABRICATING HIGH VOLTAGE SEMICONDUCTOR DEVICES HAVING IMPROVED ELECTRIC FIELD SUPPRESSION

General Electric Company,...

1. A method of fabricating a semiconductor device, comprising:providing a wafer comprising a plurality of semiconductor devices;
disposing an electric field (E-field) suppression layer on the wafer, wherein the E-field suppression layer comprises openings that are aligned with conductive pads of each of the plurality of semiconductor devices; and
functionally testing each of the plurality of semiconductor devices on the wafer over a full range of operating parameters.

US Pat. No. 10,892,236

INTEGRATED CIRCUIT HAVING A PERIPHERY OF INPUT/OUTPUT CELLS

QUALCOMM Incorporated, S...

1. An integrated circuit, comprising:a core region in an interior of the integrated circuit;
a guard ring proximate to the core region;
a first plurality of I/O cells arranged along a perimeter of the integrated circuit, each of the first plurality of I/O cells comprising an external circuit portion and a high voltage I/O circuit located proximate to the perimeter of the integrated circuit; and
a second plurality of I/O cells arranged between the first plurality of I/O cells and the guard ring, each of the second plurality of I/O cells comprising an external circuit portion and a high voltage I/O circuit located proximate to the guard ring.

US Pat. No. 10,892,235

DIE SEAL RING AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A die seal ring, comprising: a substrate; a dielectric layer disposed on the substrate; conductive layers stacked on the substrate and located in the dielectric layer, wherein each of the conductive layers comprises: a first conductive portion; and a second conductive portion disposed on the first conductive portion, wherein a width of the first conductive portion is smaller than a width of the second conductive portion, wherein a first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer, and a second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer; and a first strengthening layer disposed between the first air gap and the dielectric layer and between the second air gap and the dielectric layer, wherein the first air gap is located between the first strengthening layer and the first conductive portion, the second air gap is located between the first strengthening layer and the second conductive portion, and a portion of the first strengthening layer is directly below a bottom surface of the first conductive portion, wherein a material of the first strengthening layer comprises aluminum nitride, titanium nitride, or tantalum nitride.

US Pat. No. 10,892,234

METHOD FOR DETECTING A DIFFERENTIAL FAULT ANALYSIS ATTACK AND A THINNING OF THE SUBSTRATE IN AN INTEGRATED CIRCUIT, AND ASSOCIATED INTEGRATED CIRCUIT

STMicroelectronics (Rouss...

1. A method for detecting an attack on an integrated circuit, where the integrated circuit includes:a first semiconductor well within a semiconductor substrate having a rear face, the first semiconductor well comprising circuit components; and
a second semiconductor well within said semiconductor substrate, the second semiconductor well insulated from the first semiconductor well and from a rest of the semiconductor substrate;
wherein the second semiconductor well includes a PN junction;
the method comprising:
detecting of a thinning of the semiconductor substrate via the rear face by a detection of an absence of a current flowing in the second semiconductor well in response to an applied bias, and
detecting a Differential Fault Analysis (DFA) attack initiated by application of a laser radiation to the semiconductor substrate, where there is no detection of the thinning of the semiconductor substrate, by a detection of a photocurrent flowing in the second semiconductor well, wherein said photocurrent is generated by said PN junction in response to said laser radiation and in the absence of the applied bias.

US Pat. No. 10,892,233

MITIGATING MOISTURE-DRIVEN DEGRADATION OF FEATURES DESIGNED TO PREVENT STRUCTURAL FAILURE OF SEMICONDUCTOR WAFERS

International Business Ma...

1. An apparatus comprising:a semiconductor die having an edge;
an inboard crack stop, formed in the die, that extends parallel to the die edge;
an outboard crack stop, formed in the die, that extends parallel to the die edge between the inboard crack stop and the die edge;
a moisture barrier, embedded in the die, inboard of the inboard crack stop;
a groove, formed in an upper surface of the die, that extends parallel to the crack stop between the outboard crack stop and the die edge; and
a first moisture barrier material that fills the entire depth of the groove.

US Pat. No. 10,892,232

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device comprising:a semiconductor substrate comprising a first face, and a second face on an opposite side to the first face;
a semiconductor element provided on the first face of the semiconductor substrate;
a polycrystalline or non-crystalline first material layer provided at least on an outer edge of the first face of the semiconductor substrate; and
a second material layer provided on the second face of the semiconductor substrate, the second material layer transmitting laser light.

US Pat. No. 10,892,231

ELECTRONICS PACKAGE INCLUDING INTEGRATED ELECTROMAGNETIC INTERFERENCE SHIELD AND METHOD OF MANUFACTURING THEREOF

General Electric Company,...

1. An electronics package comprising:a substrate comprising a first surface and a second surface opposite the first surface;
an electrical component coupled to the first surface of the substrate via a component attach material, the electrical component having a front surface, a back surface opposite the front surface, and a plurality of side walls extending between the front and back surfaces;
a first insulating material coupled to the first surface and extending along at least a portion of one side wall of the plurality of side walls from the front surface toward the back surface, wherein the first insulating material comprises an exterior surface; and
a conductive material formed on the exterior surface and encapsulating the electrical component, the first insulating material, and at least a portion of the first surface.

US Pat. No. 10,892,230

MAGNETIC SHIELDING MATERIAL WITH INSULATOR-COATED FERROMAGNETIC PARTICLES

Taiwan Semiconductor Manu...

1. A device, comprising:a semiconductor die;
a magnetic shield, including:
a mixture covering a first portion of the semiconductor die and having:
a plurality of first ferromagnetic particles;
an insulating coating encapsulating each of the plurality of first ferromagnetic particles; and
a matrix containing the first ferromagnetic particles; and
a magnetic epoxy covering a second portion of the semiconductor die and having a plurality of second ferromagnetic particles in electrical contact with each other.

US Pat. No. 10,892,229

MEDIA SHIELD WITH EMI CAPABILITY FOR PRESSURE SENSOR

NXP USA, INC., Austin, T...

1. A packaged semiconductor device comprising:a package body having a recess in which a pressure sensor is located;
a polymeric gel within the recess that vertically and laterally surrounds the pressure sensor; and
a media shield comprising at least one metal layer on a top surface of the polymeric gel, wherein the media shield and the polymeric gel are sufficiently flexible to transmit pressure to the pressure sensor.

US Pat. No. 10,892,228

METHOD OF MANUFACTURING CONDUCTIVE FEATURE AND METHOD OF MANUFACTURING PACKAGE

Taiwan Semiconductor Manu...

1. A method of manufacturing a conductive feature, comprising:forming a seed layer;
forming a conductive pattern over the seed layer, wherein the seed layer and the conductive pattern comprise a same material;
performing a dry etch process to partially remove the seed layer exposed by the conductive pattern, to form a seed layer pattern; and
performing a plasma treatment process on the seed layer pattern and the conductive pattern thereon, wherein performing the dry etch process and performing the plasma treatment process are in-situ processes.

US Pat. No. 10,892,227

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A fan-out semiconductor package comprising:a first connection member having a through hole penetrating through an entirety of the first connection member;
a semiconductor chip disposed in the through hole, and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface;
a reinforcing layer including an insulating resin and a plurality of cores made of glass fiber, glass cloth, or glass fabric, and disposed on the first connection member and the inactive surface of the semiconductor chip, at least a portion of the plurality of cores is embedded in the insulating resin;
an encapsulant including a first portion encapsulating at least a portion of the first connection member and disposed between the first connection member and the reinforcing layer, a second portion encapsulating at least a portion of the inactive surface of the semiconductor chip and disposed between the inactive surface of the semiconductor chip and the reinforcing layer, and a third portion continuously extending from the first and second portions of the encapsulant, disposed at least in the through hole, and separating the first connection member and the semiconductor chip from each other, wherein a modulus of elasticity of the encapsulant is less than that of the reinforcing layer;
a second connection member disposed on the first connection member and the active surface of the semiconductor chip;
an opening passing through the encapsulant and the reinforcing layer; and
an external connection terminal filling at least a portion of the opening,
wherein the first connection member and the second connection member comprise redistribution layers electrically connected to the connection pad of the semiconductor chip, respectively, a redistribution layer of the first connection member comprises a pad having at least a portion exposed by the opening to be connected to the external connection terminal,
a wall surface of the opening passing through the encapsulant and the reinforcing layer has surface roughness greater than surface roughness of an exposed surface of the pad,
a wall of the opening extending through the reinforcing layer is common with a wall of the opening extending through the encapsulant,
the wall of the opening has a plurality of first voids recessed from the wall surface of the opening, each of the plurality of first voids corresponds to each of the plurality of cores,
the external connection terminal extends from the wall surface of the opening into each of the plurality of first voids, and
sidewalls of each of the plurality of first voids extending from the wall surface of the opening are composed of the insulating resin of the reinforcing layer, and an end surface of each of the plurality of first voids connecting the sidewalls thereof is composed of one of the plurality of cores.

US Pat. No. 10,892,226

POWER SEMICONDUCTOR MODULE

LSIS CO., LTD., Anyang-s...

1. A power semiconductor module, comprising:a first plate;
a second plate configured to comprise first and second device receiving portions thereinside, and coupled to one side of the first plate;
first and second power semiconductor devices arranged in the first and second device receiving portions;
first and second input bus bars coupled to an outside of the second plate;
a third plate configured to comprise third and fourth device receiving portions thereinside, and coupled to the other side of the first plate;
third and fourth power semiconductor devices arranged in the third and fourth device receiving portions; and
third and fourth input bus bars coupled to an outside of the third plate, and
wherein the first plate and the second plate are sealed to shield the first and second device receiving portions from the outside,
wherein the first plate and the third plate are sealed to shield the third and fourth device receiving portions from the outside,
wherein the second plate includes a first partition wall placed between the first and the second device receiving portion, and a bottom surface of the first partition wall of the second plate is in contact with the one side of the first plate, and
wherein the third plate includes a second partition wall place between the third and fourth device receiving portions, and a bottom surface of the second partition wall of the third plate is in contact with the other side of the first plate.

US Pat. No. 10,892,225

DIE INTERCONNECT STRUCTURES AND METHODS

Intel Corporation, Santa...

1. A system comprising:a substrate including first routing therein at a first routing density;
an interconnect structure embedded, at least partially, in the substrate, the interconnect structure including second routing therein at a second routing density, the first routing density less than the second routing density;
a first die electrically connected to the first routing; and
a second die electrically connected to the first routing and electrically connected to the first die through the second routing;
the interconnect structure comprising:
alternating metal and dielectric layers including a first metal layer, second metal layer, and a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane and vias within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field, the third metal layer includes alternating ground and signal traces outside the footprint of the bump field such that the signal trace to ground trace ratio in the third metal layer and outside the footprint of the bump field is one to one.

US Pat. No. 10,892,224

APPARATUSES COMPRISING PROTECTIVE MATERIAL ALONG SURFACES OF TUNGSTEN-CONTAINING STRUCTURES

Micron Technology, Inc., ...

1. An apparatus comprising:a series of tungsten-containing lines extending across a supporting base; the tungsten-containing lines being spaced apart from one another;
each of the tungsten-containing lines comprising, along a cross-section, a bottom surface facing the supporting base and being in direct physical contact with a conductive structure, an opposing top surface consisting essentially of tungsten, and a pair of sidewall surfaces consisting essentially of tungsten extending downwardly from the top surface, the conductive structure and the tungsten-containing line being of an identical width; and
protective material along the top surfaces and the sidewall surfaces of the tungsten-containing lines; the protective material comprising titanium nitride; the titanium nitride of the protective material having a surface consisting essentially of titanium nitride directly against the top and sidewall surfaces that consist essentially of tungsten.

US Pat. No. 10,892,223

ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by a partial body portion;
a trench isolation layer between the plurality of semiconductor bodies and adjacent to lower portions of the plurality of semiconductor bodies, but not adjacent to upper portions of the plurality of semiconductor bodies, wherein the trench isolation layer is over the partial body portion;
one or more gate electrode stacks on top surfaces and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies and on portions of the trench isolation layer; and
a back end of line (BEOL) metallization layer above the one or more gate electrode stacks, the BEOL metallization layer comprising a plurality of alternating first and second conductive line types along a same direction, wherein a total composition of the first conductive line type is different from a total composition of the second conductive line type.

US Pat. No. 10,892,222

ANTI-FUSE FOR AN INTEGRATED CIRCUIT (IC) PRODUCT AND METHOD OF MAKING SUCH AN ANTI-FUSE FOR AN IC PRODUCT

GLOBALFOUNDRIES Inc., Gr...

1. An integrated circuit product, comprising:a first conductive line positioned at a first level within the integrated circuit product;
a first conductive structure positioned at a second level within the integrated circuit product, wherein the second level is lower than the first level;
a second conductive structure that is conductively coupled to the first conductive line, wherein at least a portion of the second conductive structure is positioned at a level that is above the first level and wherein nearest surfaces of the first conductive structure and the second conductive structure are laterally offset from one another by a lateral distance; and
insulating material positioned between the nearest surfaces of the first conductive structure and the second conductive structure.

US Pat. No. 10,892,221

TRANSFORMER FOR A CIRCUIT IN MMIC TECHNOLOGY

THALES, Courbevoie (FR) ...

1. A transformer for a circuit in MMIC technology, of the type including a primary track and a secondary track that are coupled to one another by mutual inductance, the primary and secondary tracks being superimposed on top of each other in two different parallel planes, while being arranged so as to follow a same contour, the plane of the primary track corresponding to the main conductive layer of the circuit, deposited on a substrate, and the secondary track being supported, plumb with the primary track, by supporting means, wherein the supporting means comprises at least one wall,the wall bearing directly on the substrate of the circuit and on a lower surface of the secondary track,
a length of the wall being greater than a width of the wall,
the wall having a shared height making it possible to arrange a predetermined interval between an upper surface of the primary track and the lower surface of the secondary track, and
the wall comprising a lower part made from a first metal of the main conductive layer of the circuit, an upper part made from a second metal of the secondary track, and, between the lower part and the upper part, an insulating layer, the transformer function being performed by electromagnetic coupling between the primary track and the assembly formed by the secondary track and the upper part of the wall.

US Pat. No. 10,892,220

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device in which a plurality of interconnect layers are stacked, comprising:a power switch implemented by a primitive unit lattice under the interconnect layers, the power switch being configured to shut down power supply in a divided functional block region;
a lowermost interconnect layer in which a power supply interconnect, a ground interconnect and a virtual power supply interconnect are formed, each of the power supply interconnect, the ground interconnect and the virtual power supply interconnect having an access point to the power switch;
an intermediate interconnect layer located in a layer above the lowermost interconnect layer;
an uppermost interconnect layer in which a power supply interconnect, a ground interconnect and a virtual power supply interconnect are formed in an arrangement direction which is perpendicular to an arrangement direction of the power supply interconnect, the ground interconnect and the virtual power supply interconnect of the lowermost interconnect layer;
an interconnect layer located in a layer above the intermediate interconnect layer, and located immediately under the uppermost interconnect layer; and
a power supply via, a ground via and a virtual power supply via, which are stacked vias, and are juxtaposed in the arrangement direction of the power supply interconnect, the ground interconnect and the virtual power supply interconnect of the lowermost interconnect layer, and which penetrate from the interconnect layer immediately under the uppermost interconnect layer to the lowermost interconnect layer.

US Pat. No. 10,892,219

MOLDED EMBEDDED BRIDGE FOR ENHANCED EMIB APPLICATIONS

Intel Corporation, Santa...

1. An embedded multi-die interconnect bridge (EMIB) substrate comprising:an organic substrate; and
a bridge embedded in the organic substrate, the bridge including a plurality of routing layers embedded within the bridge, each routing layer having a plurality of traces, each of the plurality of routing layers being made of a material, the material for each of the plurality of routing layers being the same, each of the plurality of routing layers having a different silica filler content and a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer due to the different silica filler content.

US Pat. No. 10,892,218

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device, comprising:a first power supply terminal and a second power supply terminal which are arranged so as to be adjacent in a predetermined one direction in a plan view; and
a circuit element which is electrically connected between the first power supply terminal and the second power supply terminal; wherein,
the first power supply terminal includes a first internal wiring connection portion and a first external wiring connection portion which are flat plate-shaped and arranged so as to face each other, with an interval kept, in a vertical direction along a plan view direction and a first coupling portion which couples an edge portion of the first internal wiring connection portion and that of the first external wiring connection portion on the side of the second power supply terminal,
the second power supply terminal includes a second internal wiring connection portion and a second external wiring connection portion and a second coupling portion which couples the second internal wiring connection portion and the second external wiring connection portion and is disposed adjacent to the first coupling portion, and
the first coupling portion and the second coupling portion are opposed to each other, and at least a part of the first connecting part and at least a part of the second connecting part extend in the vertical direction.

US Pat. No. 10,892,217

WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate, comprising:a plurality of first wiring portions;
an insulation layer covering the first wiring portions;
a plurality of openings, each of the openings extending through the insulation layer in a thickness-wise direction to partially expose an upper surface of one of the first wiring portions, wherein the openings differ from each other in capacity; and
a plurality of second wiring portions, each of the second wiring portions including a via wiring and a columnar connection terminal, wherein each of the openings is filled with the via wiring of one of the second wiring portions, and the columnar connection terminal is arranged on an upper surface of the insulation layer and electrically connected to the via wiring of a corresponding one of the second wiring portions, wherein
the via wiring includes an electrolytic plated layer and an electroless plating structure including N layers where N represents an integer greater than or equal to zero, the electroless plating structure being arranged between the electrolytic plated layer and the upper surface of a corresponding one of the first wiring portions exposed in a bottom of a corresponding one of the openings,
the via wiring is formed so that the electroless plating structure has a thickness that increases as a capacity of the corresponding opening filled with the via wiring is increased,
the plurality of openings include a first opening and a second opening having a smaller capacity than the first opening,
the via wiring with which the first opening is filled is a first via wiring, the first via wiring including:
a first base plated layer provided as the electroless plating structure including N layers (N=1), wherein the first base plated layer covers an entire upper surface of the corresponding first wiring portion exposed in the bottom of the first opening;
a first seed layer that continuously covers an entire upper surface of the first base plated layer and an entire wall surface of the first opening; and
a first electrolytic plated layer arranged on the first seed layer to fill the first opening, and
the via wiring with which the second opening is filled is a second via wiring not including the electroless plating structure, the second via wiring including:
a second seed layer that continuously covers an entire upper surface of the corresponding first wiring portion exposed in the bottom of the second opening and an entire wall surface of the second opening; and
a second electrolytic plated layer arranged on the second seed layer to fill the second opening.

US Pat. No. 10,892,216

WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate comprising:a first insulation layer including a concave portion formed in a lower surface of the first insulation layer;
a first wiring layer formed in the concave portion;
a protective insulation layer having an opening configured to expose a part of the first wiring layer and stacked on the lower surface of the first insulation layer; and
an adhesion layer interposed between the first wiring layer and the protective insulation layer and having higher adhesiveness with the protective insulation layer than the first wiring layer,
wherein the first wiring layer is formed on an upper surface of the protective insulation layer with the adhesion layer being interposed therebetween, and comprises a pad portion formed in the concave portion and a protrusion protruding from a portion of a lower surface of the pad portion into the opening,
wherein the adhesion layer is formed to cover the lower surface of the pad portion and a side surface of the protrusion and to expose a lower end face of the protrusion,
wherein a lower surface of the protective insulation layer is an exposed outside surface of the wiring substrate, and
wherein the adhesion layer is formed to cover a first portion of a side surface of the protective insulation layer that defines the opening, and to expose a second portion of the side surface of the protective insulation layer that defines the opening.

US Pat. No. 10,892,215

METAL ON BOTH SIDES WITH POWER DISTRIBUTED THROUGH THE SILICON

Intel Corporation, Santa...

1. An apparatus comprising:a silicon substrate having a first side and a second side, the second side opposite the first side;
a transistor device on the first side of the silicon substrate;
a supply line on the second side of the silicon substrate; and
a device contact coupled to the transistor device, the device contact coupled to the supply line by a through silicon via (TSV) extending through the silicon substrate, wherein the device contact is directly on the TSV.

US Pat. No. 10,892,214

SEMICONDUCTOR CHIP COMPRISING A MULTIPLICITY OF EXTERNAL CONTACTS, CHIP ARRANGEMENT AND METHOD FOR CHECKING AN ALIGNMENT OF A POSITION OF A SEMICONDUCTOR CHIP

Infineon Technologies AG,...

1. A semiconductor chip, comprising:a mounting surface comprising a plurality of first conductive contacts and at least one second conductive contact,
wherein each of the first contacts in the plurality is arranged at one of first grid positions defined by a regularly spaced apart array such that centroids of immediately adjacent ones of the first contacts are separated from one another in a first direction by a first distance,
wherein each of the first contacts in the plurality have an identical first lateral extent,
wherein the at least one second conductive contact overlaps with a second grid position defined by the regularly spaced apart array, and
wherein a centroid of the at least one second conductive contact is separated in the first direction from the centroid of the immediately adjacent one of the first contacts by a second distance that is different from the first distance.

US Pat. No. 10,892,213

WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A wiring structure, comprising:an upper conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
a lower conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
an adhesion layer interposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together; and
at least one via extending through at least a portion of the upper conductive structure and the adhesion layer, and electrically connected to the circuit layer of the lower conductive structure,
wherein a line width/line space (L/S) of the circuit layer of the lower conductive structure is greater than a line width/line space (L/S) of the circuit layer of the upper conductive structure, wherein each of the at least one dielectric layer of the upper conductive structure defines a through hole having an inner surface, the adhesion layer defines a through hole having an inner surface, and the inner surface of the through hole of the adhesion layer and the inner surfaces of the through holes of the at least one dielectric layer are coplanar with each other, and a material of the adhesion layer is transparent.

US Pat. No. 10,892,212

FLAT NO-LEAD PACKAGE WITH SURFACE MOUNTED STRUCTURE

STMICROELECTRONICS, INC.,...

1. A device, comprising:a substrate having a first plurality and a second plurality of exposed metal leads and a pad on a surface thereof;
a semiconductor circuit die mounted on the pad and electrically coupled to the first plurality of exposed metal leads on the substrate;
a surface mounted structure mounted on and electrically coupled to the first surface of the substrate, the surface mounted structure including an electrical element coupled between a first end portion and a second end portion, the first end portion coupled to a first exposed metal lead of the second plurality of metal leads, and the second end portion coupled to a second exposed metal lead of the second plurality of metal leads to electrically connect the surface mounted structure to the first surface of the substrate, and the first end portion including a recessed member positioned about a coupling edge where the first end portion is coupled to the first exposed metal lead; and
a coupling medium between the first end portion and the first exposed metal lead, the coupling medium being positioned at least partially within the recessed member.

US Pat. No. 10,892,211

SIDE-SOLDERABLE LEADLESS PACKAGE

Semtech Corporation, Cam...

1. A method of making a semiconductor device, comprising:forming a leadframe by chemically half-etching a bottom surface of a sheet of conductive material, wherein the half-etching of the bottom surface forms a trench into the leadframe with a first side surface of a first contact and a second side surface of a second contact of the leadframe exposed within the trench, and wherein a portion of the bottom surface of the sheet of conductive material between the first contact and second contact is masked during half-etching of the bottom surface to form a support structure within the trench;
plating a solder wettable layer over the first side surface of the first contact; and
singulating the leadframe into a plurality of units, wherein the trench extends for an entire length or width of one of the plurality of units.

US Pat. No. 10,892,210

PACKAGE STRUCTURES

DELTA ELECTRONICS, INC., ...

1. A package structure, comprising:a leadframe comprising a plurality of connection portions, each of the connection portions having a first side and a second side;
a device comprising a substrate having an outermost edge, an active layer disposed on the substrate and aplurality of electrodes disposed on the active layer, wherein the electrodes of the device are connected to the first sides of the connection portions of the leadframe, wherein the leadframe is located underneath the device;a conductive unit comprising conductive metal having a first side and a second side located above the device, wherein the first side of the conductive unit extends and terminates at the outermost edge of the substrate connects to the substrate of the device, and the conductive unit directly connects to the first side of at least one of the connection portions of the leadframe;
an encapsulation material covering the device and the leadframe, wherein the second side of the conductive unit and the second side of at least one of the connection portions of the leadframe are exposed from the encapsulation material; and
a redistribution layer comprising an insulation layer and a metal layer, wherein the insulation layer is disposed on the active layer of the device, and the metal layer is connected with the electrodes of the device and the connection portions of the leadframe.

US Pat. No. 10,892,209

SEMICONDUCTOR DEVICE WITH METAL DIE ATTACH TO SUBSTRATE WITH MULTI-SIZE CAVITY

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device, comprising:a metal substrate including a through-hole aperture having a multi-size cavity having a larger area top cavity portion above a smaller area bottom cavity portion that defines a first ring around the bottom cavity portion;
a semiconductor die having a top side with bond pads thereon and a back side with a metal (BSM) layer thereon is mounted top side up with the BSM layer on the first ring; and
a metal die attach layer directly contacting at least a portion of the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

US Pat. No. 10,892,208

HEAT DISSIPATION APPARATUS AND METHOD FOR POWER SEMICONDUCTOR DEVICES

BEIJING E. MOTOR ADVANCE ...

1. An improved power semiconductor heat dissipation apparatus, said apparatus comprising:a liquid heat exchange manifold featuring:
an influent through which coolant fluid may flows into said manifold;
an effluent through which coolant fluid may flow out of said manifold;
a heat exchange surface positioned within said manifold between the influent and effluent such that the coolant fluid must flow past said heat exchange surface to flow from said influent to said effluent;
a first plenum defined by the space within said manifold between the influent and the heat exchange surface;
a second plenum defined by the space within said manifold between the heat exchange surface and the effluent;
at least one power semiconductor mounted externally to said manifold in thermal communication with said heat exchange surface; and
wherein said influent provides cooling fluid ingress to said first plenum and said effluent provides cooling fluid egress from said second plenum and said heat exchange surface extends between said first plenum and said second plenum such that cooling liquid must flow past said heat exchange surface to flow from said first plenum to said second plenum;
at least one flow balancer located inside and along the length of either the first or second plenum specifically shaped to manipulate the hydrodynamic pressure of the cooling fluid along the length of said heat exchange surface bordering said first plenum or second plenum to optimize coolant fluid flow distribution from the first plenum to the second plenum past said heat exchange surface.

US Pat. No. 10,892,207

POWER MODULE

Robert Bosch GmbH, Stutt...

1. A power module (1) comprising at least three layers that are stacked one above the other, the power module comprising:at least one cooling body (10) having an upper face (11),
at least one intermediate layer (20) that is applied to the upper face (11) of the cooling body (10) and extends in a planar manner, wherein the intermediate layer is non-conductive, provides an adhesive bond and comprises a first face (21) that is facing the upper face (11) of the cooling body (10) and a second face (22) that is remote from the first face (21),
at least one metal layer (30) that is arranged on the second face (22) of the intermediate layer (20) and is sub-divided into conductor track sections (31), the conductor track sections (31) being spaced apart from each other, wherein the metal layer comprises a contact face (32) that faces the second face (22) of the intermediate layer (20),
wherein the power module (1) furthermore comprises at least one electric and/or electronic power component (40) that is applied to at least one conductor track section (31) of the metal layer (30) and is in electrical contact with the at least one conductor track section (31) of the metal layer (30),
characterized in that the metal layer (30) that is sub-divided into the conductor track sections (31) is produced from at least one metal sheet, which is sub-divided into conductor track sections (31), independently from the production of the intermediate layer (20) and independently from the production of the cooling body (10),
wherein the first face of the intermediate layer (20) is laminated to the upper face (11) of the cooling body (10),
wherein the second face (22) of the intermediate layer (20) is laminated to the contact face (32) of the metal layer (30), and
wherein the intermediate layer (20) is configured as a laminating film that is embodied from a synthetic material.

US Pat. No. 10,892,206

METHODS OF FORMING POWER ELECTRONIC ASSEMBLIES USING METAL INVERSE OPAL STRUCTURES AND ENCAPSULATED-POLYMER SPHERES

18. A method for bonding a semiconductor device to a substrate using metal inverse opals, the method comprising:depositing the substrate onto a first major surface of an opal structure, the opal structure defining a plurality of voids between the first major surface and a second major surface of the opal structure;
receiving a plurality of polymer spheres within at least one of the plurality of voids of the opal structure;
electrodepositing metal within the plurality of voids of the opal structure to bond the substrate to the opal structure;
dissolving the opal structure to provide a metal inverse opal structure secured along the substrate, the metal inverse opal structure defining a plurality of spheres; and
dissolving the plurality of polymer spheres from within the metal inverse opal structure to expose an encapsulated material positioned within the plurality of polymer spheres; and
depositing the semiconductor device onto the metal inverse opal structure to bond the substrate to the semiconductor device.

US Pat. No. 10,892,205

PACKAGE STRUCTURE AND POWER MODULE USING SAME

1. A package structure, comprising:a first insulation layer;
a first redistribution structure located in the first insulation layer and exposed from a bottom surface of the first insulation layer, wherein the first redistribution structure comprises at least one first redistribution layer;
a second redistribution structure, wherein a part of the second redistribution structure is disposed on a part of a top surface of the first insulation layer, and the other part of the second redistribution structure is located in the first insulation layer, wherein the second redistribution structure comprises at least one second redistribution layer;
at least one electronic component embedded within the first insulation layer, disposed on the first redistribution structure, and comprising plural conducting terminals, wherein at least one of the conducting terminals is connected with the second redistribution structure;
a second insulation layer disposed on the other part of the top surface of the first insulating layer and the second redistribution structure;
a first heat spreader disposed on the second insulation layer;
a heat dissipation substrate disposed on the bottom surface of the first insulation layer;
a second heat spreader disposed on the heat dissipation substrate; and
plural thermal conduction structures embedded within the first insulation layer, wherein at least one of the plural thermal conduction structures is connected with at least one of the first redistribution structure and the second redistribution structure, and the plural thermal conduction structures are respectively exposed from the opposite sides of the first insulation layer to form plural pins.

US Pat. No. 10,892,204

ELECTROMAGNETIC WAVE ABSORBING HEAT CONDUCTIVE SHEET, METHOD FOR PRODUCING ELECTROMAGNETIC WAVE ABSORBING HEAT CONDUCTIVE SHEET, AND SEMICONDUCTOR DEVICE

Dexerials Corporation, T...

1. An electromagnetic wave absorbing heat conductive sheet, comprising:a polymer matrix component;
a magnetic metal powder; and
fibrous heat conductive fillers,
wherein 90% or more of the fibrous heat conductive fillers are oriented in one direction,
an angle of an orientation direction of the oriented fillers relative to an extending direction of a sheet surface is in the range of more than 60° to 90°,
and
the electromagnetic wave absorbing heat conductive sheet satisfies condition of (a), (b) or (c):
(a) a heat conductivity in thickness direction of 5 W/(m·K) or more and a transmission absorption rate of the electromagnetic wave at 1 GHz of 3.6% or more,
(b) a heat conductivity in thickness direction of 5 W/(m·K) or more and a transmission absorption rate of the electromagnetic wave at 3 GHz of 30% or more,
(c) a heat conductivity in thickness direction of 5 W/(m·K) or more and a transmission absorption rate of the electromagnetic wave at 6 GHz of 70% or more.

US Pat. No. 10,892,203

POWER SEMICONDUCTOR MODULE

MITSUBISHI ELECTRIC CORPO...

1. A power semiconductor module, comprising:a metal base plate;
an insulating substrate arranged on the metal base plate and provided with an electrode;
a semiconductor element arranged on the insulating substrate;
a case arranged on the metal base plate so as to surround the insulating substrate and the semiconductor element; and
a potting material filled into a space defined by the metal base plate and the case so as to seal the insulating substrate and the semiconductor element,
the potting material including:
a silicone gel; and
a conductivity-imparting agent added to the silicone gel and including a silicon atom and an ionic group,
wherein an amount of leakage current generated at a comb-electrode boundary of an evaluation structure sealed with the potting material which is used within the power semiconductor module is 1.5×10?8 A or less and 4.2×10?10 A or more,
wherein the evaluation structure has a silicon nitride substrate, a first comb-electrode formed on the silicon nitride substrate, and a second comb-electrode formed on the silicon nitride substrate so as to oppose to the first comb-electrode,
wherein the first comb-electrode has a plurality of first linear electrodes, a number of the plurality of first linear electrodes is 10, and each of the plurality of first linear electrodes has a length of 18 mm,
wherein the second comb-electrode has a plurality of second linear electrodes, a number of the plurality of second linear electrodes is 9, and each of the plurality of second linear electrodes has a length of 18 mm,
wherein the plurality of first linear electrodes and the plurality of second linear electrodes are arranged alternately at an interval of 1 mm, and
wherein the amount of leakage current is measured after 300 seconds from application of a DC voltage of 1 kV between the first comb-electrode and the second comb-electrode.

US Pat. No. 10,892,202

EXTERNAL GETTERING METHOD AND DEVICE

Micron Technology, Inc., ...

1. A semiconductor wafer comprising:a substrate having a device section for forming semiconductor devices and a backside section;
a first gettering material directly interfacing with said backside section, said first gettering material for forming a denude zone at said device section; and
an external gettering element separate from said first gettering material and directly interfacing with said backside section, said external gettering element comprising (i) a second gettering material for forming said denude zone at said device section and (ii) an adhesive material,
wherein said second gettering material is integrated with said adhesive material.

US Pat. No. 10,892,201

ELECTRONIC DEVICE COMPRISING A SUPPORT SUBSTRATE AND AN ENCAPSULATING COVER FOR AN ELECTRONIC COMPONENT

STMicroelectronics (Greno...

1. A method, comprising:forming annular metal local layers on a face of a support substrate, the annular metal local layers surrounding locations for receiving and mounting an electronic component;
forming a plurality of notches in the annular metal local layers to define a plurality of spaced-apart teeth;
mounting a plurality of encapsulating covers to the support substrate, each encapsulating cover mounted above a corresponding one of the locations with an end edge of a peripheral wall of each encapsulating cover attached to the annular metal local layer; and
then cutting, between and at a distance from adjacent ones of the encapsulating covers, along the annular metal local layers and through the support substrate and the teeth of said annular local metal layers to obtain a plurality of individual electronic devices.

US Pat. No. 10,892,200

SEMICONDUCTOR APPARATUS AND ELECTRIC POWER CONVERSION APPARATUS

Mitsubishi Electric Corpo...

1. A semiconductor apparatus comprising:a base plate;
an adhesive agent provided on an upper face of the base plate; and
a casing having a lower face and an inclined face both positioned entirely above an uppermost portion of the upper face of the base plate and an inclined face continuous to the lower face and positioned closer to a center of the base plate than the lower face and positioned directly above the upper face of the base plate, and fixed to the base plate through the adhesive agent adhering to the lower face and the inclined face, wherein
of the adhesive agent, a portion that is in contact with the inclined face is thicker than all other portions of the adhesive agent that are in contact with the upper face of the base plate.

US Pat. No. 10,892,199

SEMICONDUCTOR PACKAGE STRUCTURE, PRODUCT AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a substrate;
a semiconductor sensor disposed on the substrate;
a lid covering the semiconductor sensor and defining a through hole; and
an air-permeable film covering the through hole of the lid and having a first surface, wherein the first surface is hydrophilic.

US Pat. No. 10,892,198

SYSTEMS AND METHODS FOR IMPROVED PERFORMANCE IN SEMICONDUCTOR PROCESSING

Applied Materials, Inc., ...

1. An etching method comprising:flowing a hydrogen-containing precursor into a semiconductor processing chamber;
flowing a fluorine-containing precursor into a remote plasma region of the semiconductor processing chamber;
forming a plasma of the fluorine-containing precursor in the remote plasma region;
etching a pre-determined amount of a silicon-containing material from a substrate in a processing region of the semiconductor processing chamber;
measuring a radical density within the remote plasma region during the etching; and
halting the flow of the hydrogen-containing precursor into the semiconductor processing chamber when the radical density measured over time correlates to a produced amount of etchant to remove the pre-determined amount of the silicon-containing material.

US Pat. No. 10,892,197

EDGE SEAL CONFIGURATIONS FOR A LOWER ELECTRODE ASSEMBLY

LAM RESEARCH CORPORATION,...

1. A lower electrode assembly configured to support a semiconductor substrate in a plasma processing chamber, the lower electrode assembly comprising:a base plate, an upper plate above the base plate, and a mounting groove surrounding a bond layer located between the base plate and the upper plate;
an edge seal comprising a compressible ring mounted in the mounting groove such that the compressible ring is axially compressed between the upper plate and the base plate; and
at least one gas passage in fluid communication with an annular space between the compressible ring and an inner wall of the mounting groove, wherein the at least one gas passage extends from a gas source through the base plate to the annular space to pressurize the annular space and includes a plurality of outlets in fluid communication with the annular space.

US Pat. No. 10,892,196

MAGNETIC PROPERTY MEASURING SYSTEM, A METHOD FOR MEASURING MAGNETIC PROPERTIES, AND A METHOD FOR MANUFACTURING A MAGNETIC MEMORY DEVICE USING THE SAME

Samsung Electronics Co., ...

1. A magnetic property measuring system comprising:a stage configured to hold a sample; and
a magnetic structure disposed over the stage,
wherein the stage comprises:
a body part;
a magnetic part adjacent the body part; and
a plurality of holes defined in the body part,
wherein the magnetic part of the stage and the magnetic structure are configured to apply a magnetic field, which is perpendicular to one surface of the sample, to the sample, and
wherein the stage is configured to move horizontally in an x-direction and a y-direction which are parallel to the one surface of the sample.

US Pat. No. 10,892,195

METHOD AND STRUCTURE FOR FORMING A VERTICAL FIELD-EFFECT TRANSISTOR USING A REPLACEMENT METAL GATE PROCESS

International Business Ma...

1. A vertical transistor device, comprising:a first plurality of fins in a first device region on a substrate;
a second plurality of fins in a second device region on the substrate;
a first type gate metal layer in the first device region and a second type gate metal layer in the second device region; and
a barrier layer between the first and second device regions;
wherein the barrier layer is disposed between the first type gate metal layer in the first device region and the second type gate metal layer in the second device region;
wherein part of the first type gate metal layer and part the second type gate metal layer contact the barrier layer;
wherein a bottom surface of the barrier layer is coplanar with a bottom surface of the first type gate metal layer and with a bottom surface of the second type gate metal layer; and
wherein the first device region is an n-type transistor region and the second device region is a p-type transistor region.

US Pat. No. 10,892,194

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a fin-shaped structure on a substrate;
a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, wherein the SDB structure comprises silicon oxycarbonitride (SiOCN); and
a gate structure on the SDB structure, wherein the gate structure comprises a metal gate and the metal gate comprises a n-type work function metal layer or a p-type work function metal layer.

US Pat. No. 10,892,193

CONTROLLING ACTIVE FIN HEIGHT OF FINFET DEVICE

International Business Ma...

1. A semiconductor device, comprising:a vertical semiconductor fin disposed on a semiconductor substrate, the vertical semiconductor fin comprising a first fin portion having a first width, and a second fin portion having a second width, wherein the second width is less than the first width, and wherein the first fin portion and the second fin portion are separated by a step transition in vertical sidewalls of the vertical semiconductor fin;
an isolation layer disposed on the semiconductor substrate, wherein the isolation layer covers the first fin portion, and wherein the second fin portion extends above an upper surface of the isolation layer; and
a fin field-effect transistor device comprising the second fin portion of the vertical semiconductor fin, and a gate structure which overlaps a portion of the second fin portion of the vertical semiconductor fin in a gate region of the fin field-effect transistor device;
wherein in the gate region, the upper surface of the isolation layer is coplanar with the step transition between the first and second fin portions of the vertical semiconductor fin such that the isolation layer prevents the gate structure from overlapping sidewalls of the first fin portion of the vertical semiconductor fin; and
wherein outside the gate region, the upper surface of the isolation layer is not coplanar with the step transition.

US Pat. No. 10,892,192

NON-PLANAR I/O AND LOGIC SEMICONDUCTOR DEVICES HAVING DIFFERENT WORKFUNCTION ON COMMON SUBSTRATE

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a first N-type fin-FET device having a first fin, the first fin having a first sidewall at a first end of the fin and a second sidewall at a second end of the fin, the first sidewall opposite the second sidewall, and the first N-type fin-FET device comprising a first gate electrode over the first end of the first fin and adjacent to the first sidewall of the first fin, a second gate electrode over the second end of the first fin and adjacent to the second sidewall of the first fin, and a third gate electrode over the first fin and between the first and second gate electrodes, wherein the first, second and third gate electrodes have a first workfunction; and
a second N-type fin-FET device having a second fin, the second N-type fin-FET device comprising a fourth gate electrode over the second fin, wherein the fourth gate electrode has a second workfunction different than the first workfunction.

US Pat. No. 10,892,191

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A method of manufacturing a semiconductor device, comprising:irradiating a division region of a semiconductor wafer with laser to form a plurality of modified portions arranged in a direction along a top surface of the semiconductor wafer and along the division region in the semiconductor wafer, the plurality of modified portions being at a first interval in a first part of the division region and at a second interval smaller than the first interval in a second part of the division region; and
splitting the semiconductor wafer into a plurality of semiconductor chips using a cleavage generated from the plurality of modified portions in the semiconductor wafer,
wherein, in a sub region of the division region that corresponds to one of the plurality of semiconductor chips, modified portions at the second interval are formed at edge areas of the one of the plurality of semiconductor chips in the direction, and not formed at an intermediate area between the edge areas, and modified portions at the first interval are formed at the intermediate area and not formed at the edge areas.

US Pat. No. 10,892,190

MANUFACTURING PROCESS OF ELEMENT CHIP

PANASONIC INTELLECTUAL PR...

1. A manufacturing process of an element chip, comprising:a first step for preparing a substrate having first and second sides opposed to each other, and including a plurality of dicing regions and element regions defined by the dicing regions;
a second step for attaching a holding sheet held on a frame to the second side of the substrate with a die attach film in between;
a third step for forming a protective film covering the substrate;
a fourth step for forming a plurality of grooves in the protective film to expose the substrate along the dicing regions;
a fifth step for plasma-etching the substrate exposed along the dicing regions within a first plasma atmosphere to form a plurality of element chips from the substrate, and to expose the die attach film;
a sixth step for plasma-etching the die attach film exposed along the dicing regions within a second plasma atmosphere, to separate the die attach film into pieces corresponding to the element chips; and
a seventh step for picking up each of the element chips along with the separated die attach film away from the holding sheet,
wherein the die attach film in the second step has an area greater than that of the substrate,
wherein the protective film formed in the third step includes a first covering portion covering the first side of the substrate and a second covering portion covering at least a portion of the die attach film that extends beyond an outer edge of the substrate, and
wherein in the fifth step, the substrate is plasma-etched, with the at least the portion of the die attach film covered with the protective film.

US Pat. No. 10,892,189

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION

LAPIS SEMICONDUCTOR CO., ...

1. A method for manufacturing a semiconductor device, comprising:providing a semiconductor substrate having an obverse surface and a reverse surface opposite to the obverse surface;
forming a shallow-trench-isolation region of an insulating film on the obverse surface;
forming, in the shallow-trench-isolation region, a plurality of island-shaped dummy portions and a second dummy portion which is surrounded with the island-shaped dummy portions and has a distance across being larger than a distance across each of the island-shaped dummy portions, wherein each of the island-shaped dummy portions and the second dummy portion has a top face coplanar with a top face of the shallow-trench-isolation region and comprises a same material as the semiconductor substrate;
forming a plurality of active elements on the obverse surface to define an element-absence area provided adjacent to the active elements on the obverse surface, the element-absence area being free of any of the active elements;
forming an interlayer insulating film on and over the active elements and the element-absence area;
forming an electrode pad so as to be buried inside the interlayer insulating film and electrically connected to one or more of the active elements; and
forming a Through Silicon VIA hole penetrating within an outer edge of the second dummy portion from the reverse surface of the semiconductor substrate to the obverse surface to form a Through Silicon VIA electrode to be electrically connected to the electrode pad;
wherein the second dummy portion is formed to be a ring-shaped dummy portion surrounding the Through Silicon VIA hole on the obverse surface so that an inner diameter of the ring-shaped dummy portion is larger than an outer diameter of the Through Silicon VIA hole and the ring-shaped dummy portion is separated by a shallow trench isolation region from the Through Silicon VIA hole.

US Pat. No. 10,892,188

SELF-ALIGNED TRENCH MOSFET CONTACTS HAVING WIDTHS LESS THAN MINIMUM LITHOGRAPHY LIMITS

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device, comprising:a silicon substrate comprising a surface;
a gate electrode formed in a gate trench extending into the substrate from the surface;
a channel region adjacent to the gate electrode comprising a non-uniform channel dopant profile;
a source region adjacent to the gate electrode between the surface and the channel region, comprising a non-uniform source dopant profile;
an insulator layer formed above the substrate; and
a source contact extending through the insulator layer, wherein the source contact comprises a width that is less than a minimum lithography limit for a processing capability.

US Pat. No. 10,892,187

METHOD FOR CREATING A FULLY SELF-ALIGNED VIA

Micromaterials LLC, Wilm...

1. A method to provide a via, comprising:providing a substrate comprising a first insulating layer having a plurality of parallel recessed first conductive lines extending in a first direction, the recessed first conductive lines having a top surface recessed below a top surface of the first insulating layer;
forming first pillars on the recessed first conductive lines, the first pillars extending orthogonal to the top surface of the first insulating layer;
depositing a second insulating layer around the first pillars and on the top surface of the first insulating layer;
selectively removing at least one of the first pillars to form at least one opening in the second insulating layer, leaving at least one first pillar on the recessed first conductive lines;
depositing a second conductive material in the at least one opening to form a first via and second conductive lines, the first via connecting the recessed first conductive lines to the second conductive lines; removing the at least one first pillar left on the recessed first conductive lines to form at least one bridging opening in the second insulating layer;
forming at least one bridging pillar on the recessed first conductive lines through the at least one bridging opening, the at least one bridging pillar extending orthogonal to a top surface of the second insulating layer;
depositing a third insulating layer around the at least one bridging pillar and on a portion of the second insulating layer;
removing the at least one bridging pillar to form at least one bridging opening in the second insulating layer and third insulating layer; and
depositing a third conductive material in the at least one bridging opening to form a bridging via and third conductive lines, the bridging via connecting the recessed first conductive lines to the third conductive lines.

US Pat. No. 10,892,186

INTEGRATION OF ALD COPPER WITH HIGH TEMPERATURE PVD COPPER DEPOSITION FOR BEOL INTERCONNECT

Applied Materials, Inc., ...

1. A method of gapfilling, the method comprising:forming a copper gapfill seed layer by atomic layer deposition (ALD) on a substrate surface having a feature thereon, the atomic layer deposition occurring at a first temperature; and
filling the feature with copper by physical vapor deposition (PVD) at a second temperature greater than the first temperature to form a seam-free gapfill film,
wherein forming the copper gapfill seed layer comprises depositing a copper nitride film and converting the copper nitride film to a copper film by thermal decomposition prior to filling the feature with copper by PVD or at the same time as filling the feature with copper by PVD.

US Pat. No. 10,892,185

SEMICONDUCTOR DEVICE INCLUDING A BLOCKING PATTERN IN AN INTERCONNECTION LINE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a first interconnection line having a first end and extending in a first direction;
a first blocking pattern at the first end of the first interconnection line and adjacent to the first interconnection line in the first direction;
a second interconnection line spaced apart from the first interconnection line in a second direction crossing the first direction and extending in the first direction, the second interconnection line having a second end; and
a second blocking pattern at the second end of the second interconnection line and adjacent to the second interconnection line in the first direction,
wherein a width of the first blocking pattern in the first direction is different from a width of the second blocking pattern in the first direction.

US Pat. No. 10,892,184

PHOTOBUCKET FLOOR COLORS WITH SELECTIVE GRAFTING

Intel Corporation, Santa...

1. A method of fabricating an interconnect structure for an integrated circuit, the method comprising:forming a grating structure above an inter-layer dielectric (ILD) layer formed above a substrate, the grating structure comprising a plurality of dielectric spacers separated by alternating first trenches and second trenches;
grafting a resist-inhibitor layer in the first trenches but not in the second trenches; forming photoresist in the first trenches and in the second trenches;
exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations; etching the set of via locations into the ILD layer; and
subsequent to etching the set of via locations into the ILD layer, forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.

US Pat. No. 10,892,183

METHODS FOR REMOVING METAL OXIDES

Micromaterials LLC, Wilm...

13. A method comprising:providing a substrate in a reaction chamber, the substrate having a substrate surface with at least one feature formed therein, the at least one feature extending a distance from the substrate surface into the substrate and having a sidewall and bottom, the at least one feature having an aspect ratio greater than or equal to about 10:1, the at least one feature having a tungsten film therein and a tungsten oxide film on the tungsten film, wherein the tungsten film is partially oxidized to form the tungsten oxide film on the tungsten film;
exposing the substrate to an aqueous hydroxide solution to remove the tungsten film and the tungsten oxide film from the feature without affecting the substrate surface adjacent to the feature, the aqueous hydroxide solution comprising one or more of NaOH and KOH and having a hydroxide concentration of less than or equal to about 0.1 M; and
rinsing the substrate with a solution comprising water and isopropyl alcohol,
wherein no plasma is used and wherein the reaction chamber is not purged.

US Pat. No. 10,892,182

RELATING TO SEMICONDUCTOR DEVICES

X-FAB SARAWAK SDN. BHD., ...

1. A method of fabricating a semiconductor device with Shallow Trench Isolation (STI), said method comprising performing the following steps in the following order:providing a substrate comprising first and second gate regions separated by a trench formed in said substrate, wherein said trench is filled with an STI material;
depositing a sacrificial polysilicon layer covering and in direct contact with the STI material;
growing a thick oxide layer directly on said substrate in said first and second gate regions,
whilst growing said thick oxide layer, oxidizing said sacrificial polysilicon layer to form an oxidized sacrificial polysilicon layer;
removing said thick oxide layer from said first gate region to expose said substrate in said first region while leaving said thick oxide layer in said second gate region, wherein said step of removing said thick oxide layer also comprises removing said oxidized sacrificial polysilicon layer so as to at least partly expose said STI material.

US Pat. No. 10,892,181

SEMICONDUCTOR DEVICE WITH MITIGATED LOCAL LAYOUT EFFECTS

International Business Ma...

1. An integrated chip, comprising:a semiconductor fin comprising a first active region and a second active region that are electrically separated by an oxide region, which comprises a plurality of oxide portions that are separated by unoxidized semiconductor material, and that completely penetrates the semiconductor fin;
a first semiconductor device formed on the first active region; and
a second semiconductor device formed on the second active region.

US Pat. No. 10,892,180

LIFT PIN ASSEMBLY

APPLIED MATERIALS, INC., ...

1. A system to lift an apparatus off of a substrate support, the system comprising:the substrate support;
a platform independently movable with respect to the substrate support;
a shutter disk that is rotatable and independently movable from a lift pin assembly, the substrate support, and the platform, wherein the shutter disk is configured to protect the substrate support from damage during a process; and
the lift pin assembly including a sheath and a pin extending through the sheath, extending from the platform and comprising a first material providing a first upward support surface configured to support a substrate and a second material providing a second upward support surface configured to support the shutter disk, wherein the first material is different than the second material, wherein the first material is an electrically conductive polymer, wherein the second material is metallic, wherein the pin is formed of the first material and the sheath is formed of the second material and is configured to extend at least to an uppermost surface of the substrate support, wherein the sheath is directly mounted to a top surface of the platform, wherein the second upward support surface is disposed radially outward of the first upward support surface, wherein the first upward support surface is an upper surface of the pin and the second upward support surface is an upper surface of the sheath, and wherein the first upward support surface is above the second upward support surface.

US Pat. No. 10,892,179

ELECTROSTATIC CHUCK INCLUDING CLAMP ELECTRODE ASSEMBLY FORMING PORTION OF FARADAY CAGE FOR RF DELIVERY AND ASSOCIATED METHODS

Lam Research Corporation,...

1. An electrostatic chuck, comprising:a base plate formed of an electrically conductive material;
a ceramic layer attached to a top surface of the base plate using a bond layer disposed between the base plate and the ceramic layer, the ceramic layer having a top surface including an area configured to support a substrate;
a clamp electrode assembly positioned within the ceramic layer in an orientation substantially parallel to the top surface of the ceramic layer and at an upper location within the ceramic layer such that a region of the ceramic layer between the clamp electrode assembly and the top surface of the ceramic layer is substantially free of other electrically conductive material, wherein the clamp electrode assembly is configured to extend horizontally through the ceramic layer to at least span an area underlying the area of the top surface of the ceramic layer that is configured to support the substrate; and
a plurality of RF power delivery connection modules distributed in a substantially uniform manner about a perimeter of the ceramic layer, each of the plurality of RF power delivery connection modules configured to form an electrical connection from the base plate to the clamp electrode assembly at its respective location so as to form an RF power transmission path from the base plate to the clamp electrode assembly at its respective location, wherein the base plate, the plurality of RF power delivery connection modules, and the clamp electrode assembly together form a Faraday cage to direct RF power transmission around an internal volume of the electrostatic chuck, and
wherein each of the plurality of RF power delivery connection modules includes a first electrical connection extending from the base plate to an exposed embedded conductive segment within the ceramic layer, wherein a portion of the exposed embedded conductive segment is exposed at a bottom of the ceramic layer, and wherein each of the plurality of RF power delivery connection modules includes a second electrical connection extending from the exposed embedded conductive segment through the ceramic layer to the clamp electrode assembly.

US Pat. No. 10,892,178

SUBSTRATE PROCESSING SYSTEM, METHOD OF CONTROLLING SUBSTRATE PROCESSING SYSTEM, COMPUTER-READABLE STORAGE MEDIUM, AND METHOD OF MANUFACTURING ARTICLE

CANON KABUSHIKI KAISHA, ...

14. A substrate processing system having a plurality of substrate processing apparatuses operable to process a substrate, a host control apparatus operable to control operation of the plurality of substrate processing apparatuses, and a management apparatus operable to manage maintenance of each of the plurality of substrate processing apparatus,the management apparatus comprising:
a determination unit configured to determine a substrate processing apparatus that needs maintenance processing, based on operation information collected from each of the plurality of substrate processing apparatuses; and
a notification unit configured to notify, to the host control apparatus, information for executing the maintenance processing with respect to the substrate processing apparatus determined by the determination unit to need the maintenance processing, and
the host control apparatus comprising
a controller configured to monitor an operation state of each of the plurality of substrate processing apparatuses, and, based on the operation state of the substrate processing apparatus determined by the determination unit to need the maintenance processing, control a timing of performance of the maintenance processing with respect to the substrate processing apparatus.

US Pat. No. 10,892,177

SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS

SCREEN Holdings Co., Ltd....

1. A substrate processing method, processing a substrate having a metal layer on a surface thereof, the method comprising:a metal oxide layer forming step, forming a metal oxide layer formed of one atomic layer or several atomic layers on a surface layer of the metal layer by supplying an oxidizing liquid to the surface of the substrate;
a first rinse liquid supplying step of supplying a first rinse liquid to the surface of the substrate, after the metal oxide layer forming step;
a metal oxide layer removing step, selectively removing the metal oxide layer from the surface of the substrate by supplying an etchant to the surface of the substrate, after the first rinse liquid supplying step; and
a second rinse liquid supplying step of supplying a second rinse liquid to the surface of the substrate, after the metal oxide layer removing step,
wherein an etching amount of the metal layer is controlled with an accuracy of nanometers or smaller by executing an etching process which includes multiple cycles of the metal oxide layer forming step and the metal oxide layer removing step as one cycle.

US Pat. No. 10,892,176

SUBSTRATE PROCESSING APPARATUS HAVING TOP PLATE WITH THROUGH HOLE AND SUBSTRATE PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus comprising: a substrate holder configured to hold a substrate; a top plate installed to face the substrate held on the substrate holder, and having a through hole formed therethrough at a position facing a center of the substrate; a gas supply configured to supply an atmosphere adjustment gas; an ejection nozzle provided in the top plate and connected to the gas supply, the ejection nozzle configured to supply the atmosphere adjustment gas to a space between the substrate holder and the top plate; a processing liquid nozzle configured to eject a processing liquid to the substrate; and an arm configured to hold the processing liquid nozzle and move the processing liquid nozzle between a processing position where the processing liquid nozzle is inserted into the through hole such that processing liquid is ejected from the processing liquid nozzle through the through hole and a standby position where the processing liquid nozzle is removed from the through hole; wherein the top plate includes an inflow suppressor configured to suppress a gas different from the atmosphere adjustment gas from flowing into the space between the substrate and the top plate via the through hole.

US Pat. No. 10,892,175

STABLE HEATER REBUILD INSPECTION AND MAINTENANCE PLATFORM

SAMSUNG ELECTRONICS CO., ...

1. A stand for a heater pedestal, comprising:a base member; and
a support member detachably coupled to the base member,
the support member comprising a plurality of ring members and at least one spacer member being arranged in a first direction from the base member,
at least one of the ring members being separated from another of the ring members by the at least one spacer member,
the ring members each comprising an aperture extending therethrough in the first direction,
the at least one spacer member forming at least one opening between two adjacent ring members, the at least one opening extending in a second direction substantially perpendicular to the first direction, and
the ring members are configured to support a heater pedestal by receiving a susceptor of the heater pedestal through the aperture of the ring members.

US Pat. No. 10,892,174

SUBSTRATE CLEANING BRUSH AND SUBSTRATE CLEANING APPARATUS

SCREEN Holdings Co., Ltd....

1. A substrate cleaning brush configured to clean a substrate, comprising:a brush main body comprising:
an upper surface;
a lower surface configured to come into contact with the substrate; and
a structure comprising porous sponge or a large number of bristles, which a liquid is permeable from the upper surface to the lower surface;
a main flow path forming body comprising a main flow path through which a processing liquid supplied from the outside passes; and
a plurality of sub flow paths branching off from the main flow path, extending outward in a width direction perpendicular to a vertical direction of the brush main body, and communicating with the upper surface of the brush main body so that the processing liquid is able to pass therethrough,
wherein the main flow path forming body comprises a facing surface facing the upper surface of the brush main body,
the facing surface of the main flow path forming body forms an annular flow path together with the upper surface of the main brush body, the annular flow path extending along with an outer circumferential portion of the main brush body, and
each of the plurality of sub flow paths communicates with the main flow path and the annular flow path and between the main flow path and the annular flow path.

US Pat. No. 10,892,173

SUBSTRATE CLEANING ROLL, SUBSTRATE CLEANING APPARATUS, AND SUBSTRATE CLEANING METHOD

Ebara Corporation, Tokyo...

1. A substrate cleaning apparatus comprising:a substrate holding member configured to hold a substrate;
at least one substrate cleaning roll;
a substrate cleaning roll holding member configured to hold the at least one substrate cleaning roll, the at least one substrate cleaning roll having a cylindrical shape, the at least one substrate cleaning roll comprising:
a plurality of first nodules on a surface of the cylindrical shape; and
an edge nodule at an outermost position of the cylindrical shape, the edge nodule comprising a first sloping surface,
wherein a height of the edge nodule is 4 mm to 7 mm and a height of each of the plurality of first nodules is 3 mm to 4.5 mm, and a difference of the height of the edge nodule and the height of each of the plurality of first nodules is at least 1 mm; and
wherein a cross-section of the edge nodule is a trapezoidal shape and a top surface of the trapezoidal shape is parallel to the surface of the cylindrical shape.

US Pat. No. 10,892,172

REMOVAL OF PROCESS EFFLUENTS

Planar Semiconductor, Inc...

1. A substrate cleaning and drying apparatus, the apparatus comprising:a vertical substrate holder configured to hold and rotate the substrate vertically at various speeds;
an inner shield and an outer shield configured to at least partially surround the vertical substrate holder during operation of the apparatus, each of the inner shield and the outer shield being configured to rotate vertically and independently from each other in at least one of rotational speed and direction from the other shield;
a front-side spray jet array and a back-side spray jet array, each of the front-side spray jet array and the back-side spray jet array being configured to spray at least one fluid onto both sides of the substrate and edges of the substrate substantially concurrently; and
at least one substantially-planar turbine disk coupled vertically and in proximity to at least one of the inner shield and the outer shield and configured to remove an excess amount of the at least one fluid, the at least one turbine disk having a plurality of spaced-apart fins, each of the fins being separated from adjacent fins by an opening formed within and near a periphery of the turbine disk, the fins being arranged to evacuate the at least one fluid and other process effluents away from both the substrate and a volume between the inner shield and the outer shield surrounding the substrate.

US Pat. No. 10,892,171

REMOVAL APPARATUS FOR REMOVING RESIDUAL GAS AND SUBSTRATE TREATING FACILITY INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A removal apparatus for removing a residual gas, comprising:a housing;
a gas supply configured to provide a non-reactive gas into the housing;
a supporting member provided to support a substrate and positioned in the housing;
a heat radiating member spaced apart from the supporting member and positioned in the housing; and
a heating unit configured to provide heat toward the supporting member, wherein the heating unit is positioned between the heat radiating member and the supporting member;
wherein the housing comprises:
a floor section that supports the supporting member;
a covering section that is spaced apart from and faces the floor section;
a first circumferential section that extends toward the covering section from a boundary of the floor section; and
a second circumferential section that extends toward the floor section from a boundary of the covering section,
the first circumferential section comprising:
a first sidewall having a first opening therethrough;
a second sidewall having a second opening therethrough and facing the first sidewall;
a third sidewall connecting a side of the first sidewall to a side of the second sidewall; and
a fourth sidewall facing the third sidewall and connecting an opposite side of the first sidewall to an opposite side of the second sidewall.

US Pat. No. 10,892,170

FABRICATING AN INTEGRATED CIRCUIT CHIP MODULE WITH STIFFENING FRAME AND ORTHOGONAL HEAT SPREADER

International Business Ma...

1. A method comprising:attaching a stiffening frame to a carrier, the stiffening frame comprising a central opening to accept a semiconductor chip, a base portion, a first pair of opposing sidewalls, and a second pair of opposing sidewalls;
electronically coupling the semiconductor chip to the carrier concentrically arranged within the central opening;
thermally contacting a first directional heat spreader to the semiconductor chip, the first directional heat spreader arranged to transfer heat from the semiconductor chip in a first opposing bivector direction towards the first pair of opposing sidewalls; and
thermally contacting a second directional heat spreader to the first directional heat spreader, the second directional heat spreader arranged to transfer heat from the first directional heat spreader in a second opposing bivector direction towards the second pair of opposing sidewalls.

US Pat. No. 10,892,169

3D SEMICONDUCTOR DEVICE AND STRUCTURE

MONOLITHIC 3D INC., San ...

1. A multi-level semiconductor device, the device comprising:a first level comprising a plurality of single crystal first transistors;
a second level comprising a plurality of second transistors,
wherein said first level is overlaid by said second level;
a third level comprising a plurality of single crystal third transistors,
wherein said second level is overlaid by said third level,
wherein said device comprises Input/Output (“1/0”) circuits for connecting said device to an external device,
wherein at least one of said Input/Output circuits comprises at least one of said third transistors,
wherein at least one of said Input/Output circuits is connected to at least one of said first transistors; and
a plurality of vias providing connections between said first transistors and said second transistors,
wherein said plurality of vias each have a diameter of less than 400 nm and greater than 5 nm wherein said third level comprises a first power distribution grid, wherein said first level comprises a second power distribution grid, wherein said first power distribution grid connectivity is at least double that of said second power distribution grid connectivity.

US Pat. No. 10,892,168

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING A SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A method for forming a semiconductor device, the method comprising:incorporating recombination center atoms into a semiconductor substrate;
after incorporating the recombination center atoms into the semiconductor substrate, implanting noble gas atoms into a doping region of a diode structure and/or a transistor structure, the doping region being arranged at a surface of the semiconductor substrate; and
before incorporating the recombination center atoms into the semiconductor substrate, incorporating dopants of a first type into the semiconductor substrate to form a very highly doped portion of the doping region at the surface of the semiconductor substrate,
wherein a maximal doping concentration of the very highly doped portion of the doping region is at least 1*1018 dopants per cm3.

US Pat. No. 10,892,167

GAS PERMEABLE SUPERSTRATE AND METHODS OF USING THE SAME

CANON KABUSHIKI KAISHA, ...

1. A superstrate, comprising:a body, wherein the body comprises a contact surface; and
an amorphous fluoropolymer layer on the contact surface of the body, wherein the amorphous fluoropolymer layer is permeable to gases having an atomic mass greater than 4, wherein the amorphous fluoropolymer layer has a helium permeability coefficient of greater than 2.5×10?8 cm3*cm/cm2*S*cmHg.

US Pat. No. 10,892,166

SYSTEM AND METHOD FOR LIGHT FIELD CORRECTION OF COLORED SURFACES IN AN IMAGE

1. A computer-implemented method for correcting a makeup or skin effect to be rendered on a surface region of an image of a portion of a body of a person, which accounts for a light field of the image, the method comprising:calculating a light intensity estimation of the image as an average light intensity of pixels in a first region of the image;
determining a minimum light field estimation of the image as a minimum light intensity of pixels in a second region of the image;
receiving color effect parameters of the makeup or skin effect;
correcting the color effect parameters through a non-linear transformation accounting for the light intensity estimation and the minimum light field estimate to generate a light field corrected makeup or skin effect;
rendering the light field corrected makeup or skin effect on the surface region to generate a corrected image; and
displaying the corrected image.

US Pat. No. 10,892,165

SEMICONDUCTOR MANUFACTURING DEVICE AND METHOD OF POLISHING SEMICONDUCTOR SUBSTRATE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor manufacturing device comprising:a polishing head that is capable of retaining a semiconductor substrate;
a polishing pad having a processing surface to be abutted to the semiconductor substrate retained by the polishing head, the processing surface including grooves;
a platen that is capable of rotating about a rotary shaft running along a direction intersecting the processing surface, in a state in which the polishing pad is retained by the platen;
a measuring section that is disposed above the polishing pad on a circumference of a same circle centered about the rotary shaft of the platen as the polishing head, and that is configured to output a measurement value indicating a height of the processing surface at predetermined locations on the circumference of the same circle centered about the rotary shaft of the platen;
a derivation section that that is configured to derive a depth of the grooves from the measurement value of the measuring section;
a slurry supply nozzle that is configured to supply slurry to the processing surface of the polishing pad; and
a gas ejection nozzle that is disposed upstream of the measuring section in a direction of rotation of the platen, and that is disposed downstream of the slurry supply nozzle in the direction of rotation of the platen.

US Pat. No. 10,892,164

DUAL HARD MASK REPLACEMENT GATE

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a semiconductor device, the method comprising:depositing a first hard mask layer on a recessed gate stack arranged between gate spacers, the first hard mask layer comprising a low-k dielectric, and the recessed gate stack comprising a gate metal; and
depositing a second hard mask layer on the first hard mask layer between the gate spacers.

US Pat. No. 10,892,163

SEMICONDUCTOR DEVICE WITH SIDE WALL PROTECTION FILM FOR BOND PAD AND WIRING

ABLIC INC., Chiba (JP)

1. A semiconductor device, comprising:a bonding pad and a wiring each in the same wiring layer composed of a metal-containing film, and adjacent to each other across a distance of 1 ?m or less;
side wall protection films on side surfaces of the bonding pad and side surfaces of the wiring, the side wall protection films comprising one of silicon oxide films and silicon nitride films; and
a passivation film covering a top surface of the bonding pad, a top surface of the wiring, and surfaces of the side wall protection films, and having an opening portion exposing a part of the top surface of the bonding pad,
the passivation film in direct contact with the top surface of the bonding pad and the top surface of the wiring.

US Pat. No. 10,892,162

SILICON FILM FORMING METHOD AND SUBSTRATE PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A method of forming a silicon film, the method comprising:a film forming step of forming the silicon film on a base, the silicon film having a film thickness thicker than a desired film thickness; and
an etching step of reducing the film thickness of the silicon film by supplying an etching gas containing bromine or iodine to the silicon film,
wherein concave-convex portions are formed in a surface of the base,
wherein the etching step includes etching the silicon film formed on the concave-convex portions of the base in a conformal manner,
wherein the film forming step and the etching step are successively performed in a same processing chamber,
wherein the etching step is performed at a temperature higher than a temperature in the film forming step, and
wherein, in the etching step, the temperature is equal to or higher than 550 degrees C.

US Pat. No. 10,892,161

ENHANCED SELECTIVE DEPOSITION PROCESS

Applied Materials, Inc., ...

16. A method of forming a structure with desired materials on a substrate for semiconductor applications comprising:selectively forming a passivation layer on a first material of a substrate, wherein the passivation layer comprises a metal material having hydro-group (—H) or —OCH3 group attached thereto;
selectively forming self assembled monolayers on a second material of the substrate; and
selectively forming a material layer on the passivation layer using an atomic layer deposition process.

US Pat. No. 10,892,160

METHOD FOR PRODUCING ELECTROTECHNICAL THIN LAYERS AT ROOM TEMPERATURE, AND ELECTROTECHNICAL THIN LAYER

DYNAMIC SOLAR SYSTEMS AG,...

1. A capacitive storage device having a combination of electrotechnical thin layers forming a sequence of a multitude of electrotechnical layers, the sequence comprising: electrode layers (a), comprising at least one anode layer (a1), at least one cathode layer (a2); at least one dielectric layer (b) and electrode substrate layers (c), comprising at least one anode substrate layers (c1) and at least one cathode substrate layer (c2), all these layers forming at least one sequence (a1)(c1)(b)(c2)(a2) of layers, wherein the one sequence of layers is obtained by a room temperature method, the method comprising providing electrically conductive and/or semiconductive, inorganic agglomerates in a dispersion over an area of a carrier and curing the dispersion to form an electrotechnical thin layer, characterized in thatat least for each dielectric layer (b) and electrode substrate layer (c):
the curing is conducted at room temperature,
the room temperature being in the range of 10° C. to 60° C.,
the layer being a thin layer, having a thickness of 0.1 up to 200 micrometers,
the thin layer has an inorganic content of at least 80 percent by weight,
the remainder consisting of inorganic modifiers and auxiliaries and nonaromatic polymeric additions; and
wherein the dispersion is provided in the form of an aqueous moist dispersion to aqueous wet dispersion
and
the curing is accelerated by contacting with at least one reagent,
wherein the first thin layer is combined with further thin layers in accordance with this method,
the combination of layers being arranged as a dielectric deposited between two two-dimensional electrodes layers (a).

US Pat. No. 10,892,159

SEMIPOLAR OR NONPOLAR GROUP III-NITRIDE SUBSTRATES

Saphlux, Inc., Branford,...

1. A method, comprising:forming, on a growth template, an epitaxial layer of a group III-nitride material comprising a surface with a first crystallographic orientation, wherein the first crystallographic orientation comprises a semipolar orientation or a nonpolar orientation; and
separating the epitaxial layer of the group III-nitride material from the growth template to produce a group III-nitride substrate comprising the epitaxial layer of the group III-nitride material, wherein the growth template comprises a semiconductor layer of the group III-nitride material, and wherein the size of the epitaxial layer separated from the growth template is substantially the same as the size of the growth template.

US Pat. No. 10,892,158

MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND A PLASMA PROCESSING APPARATUS

HITACHI HIGH-TECH CORPORA...

1. A manufacturing method of a semiconductor device comprising:a first step for performing plasma processing on a semiconductor substrate including at least a silicon layer and a silicon germanium layer formed on the silicon layer under a first condition to expose the silicon germanium layer; and
a second step for performing plasma processing on the semiconductor substrate to segregate silicon on the surface of the exposed silicon germanium layer under a second condition,
wherein the first condition is a condition under which the silicon germanium layer or layers lying adjacent to the silicon germanium layer can be etched,
the second condition is a condition under which hydrogen plasma processing is performed, and
the first step and the second step are executed in series in the same processing chamber of a plasma processing apparatus.

US Pat. No. 10,892,157

METHODS FOR DEPOSITING BLOCKING LAYERS ON CONDUCTIVE SURFACES

Applied Materials, Inc., ...

1. A method of selectively depositing a blocking layer, the method comprising exposing a substrate comprising a conductive material having a first surface and a dielectric material having a second surface to a gaseous alkyl phosphonic acid to selectively form the blocking layer on the first surface over the second surface and form a blocked first surface, the alkyl phosphonic acid comprising at least one compound with a general formula RP(O)(OR?)2, where R is selected from a C4-C20 alkyl group, a C4-C20 perfluoroalkyl group, a C4-C20 alkenyl group or a C4-C20 alkynyl group and each R? is independently selected from C1-C12 alkyl or aryl, wherein the C4-C20 groups are straight chain, branched or cyclic.

US Pat. No. 10,892,156

METHODS FOR FORMING A SILICON NITRIDE FILM ON A SUBSTRATE AND RELATED SEMICONDUCTOR DEVICE STRUCTURES

ASM IP Holding B.V., Alm...

1. A method for forming a silicon nitride film on a substrate, the method comprising:forming a cyclical silicon nitride film on the substrate by a cyclical deposition process, wherein the cyclical deposition process comprises at least one cycle of:
contacting the substrate with a first reactant comprising a silicon halide source, and
contacting the substrate with a second reactant comprising a nitrogen source;
after the at least one cycle, exposing the cyclical silicon nitride film to a plasma to finish a complete deposition cycle and to form a plasma treated silicon nitride film, wherein the step of exposing renders a surface of the plasma treated silicon nitride film reactive, and wherein a wet etch rate of the plasma treated silicon nitride film is less than a wet etch rate of the cyclical silicon nitride film;
after the complete deposition cycle, and thus after forming the plasma treated silicon nitride film, repeating the forming and the exposing steps to perform multiple complete deposition cycles to form multiple plasma treated silicon nitride films; and
after repeating the forming and the exposing steps to perform multiple complete deposition cycles; passivating a surface of the plasma treated silicon nitride film, wherein the step of passivating comprises one or more of a plasma process and exposing the plasma treated silicon nitride film to nitrogen (N2), wherein the step of passivating differs from the step of exposing the cyclical silicon nitride film to the plasma, and wherein the step of passivating reduces a reactivity of a surface of the plasma treated silicon nitride film.

US Pat. No. 10,892,155

SEMICONDUCTOR CLEANER SYSTEMS AND METHODS

Brooks Automation (German...

1. A bot handler for handling a workpiece comprising a first component and a second component connectable to each other in accordance with a predetermined cleanliness relationship between the first component and the second component, the bot handler comprising:a moving mechanism; and
a gripper connected to the moving mechanism, the gripper being configured to grip and handle the workpiece, wherein the gripper is arranged corresponding to the predetermined cleanliness relationship to grip and handle both the first component and the second component, with the second component disconnected from a connection to the first component, so as to effect the grip and handle of the workpiece with the gripper,
wherein the gripper forms a first component handling portion disposed so as to have, upon handling the workpiece, a predetermined level of cleanliness and forms a second component handling portion separate and distinct from the first component handling portion and at a different location on the gripper than the first component handling portion so as to grip and handle the second component independent of grip and handle of the first component with the first component handling portion, wherein the second component handling portion is disposed so as to have, upon handling the workpiece, a second predetermined level of cleanliness different than the predetermined level of cleanliness of the first component handling portion and is sized and shaped conformal to the second component different than the first component.

US Pat. No. 10,892,154

LED LIGHT BULB APPARATUS AND LED LIGHT APPARATUS

XIAMEN ECO LIGHTING CO. L...

1. A LED light bulb apparatus, comprising:a first conductive base, comprising a first connecting point;
a second conductive base, comprising multiple second connecting points; and
multiple filaments, each filament having a first elastic hook to be fixed to the first connecting point and having a second elastic hook to be fixed to the second connecting point so as to keep the multiple filaments spreading as a three-dimensional light source.

US Pat. No. 10,892,153

ROBUST ION SOURCE

MKS Instruments, Inc., A...

1. An ion source for a mass spectrometer having a mass filter, the ion source comprising:an evacuated ionization volume evacuated by a vacuum pump;
a gas source to deliver gas to the evacuated ionization volume, the gas source being at a substantially higher pressure than that of the evacuated ionization volume;
a nozzle between the gas source and the ionization volume, there being no restricted-conductance ionization chamber restricting flow from the nozzle to the vacuum pump such that gas passing through the nozzle freely expands through an ionization region of the ionization volume;
an electron source configured to emit electrons, the electrons passing close to the nozzle through the freely expanding gas in the ionization region to ionize at least a portion of the expanding gas; and
electrodes configured to create electrical fields for ion flow of the ionized gas from the ionization region to the mass filter, the electrodes being located at distances from the nozzle and oriented to limit direct exposure of the electrodes to the gas.

US Pat. No. 10,892,152

ADJUSTABLE DWELL TIME FOR SRM ACQUISITION

1. A method of analyzing a sample, comprising:setting initial dwell times for a plurality of transitions, the initial dwell times are equal for each of the plurality of transitions, the initial dwell times are based on an expected intensity for the plurality of transitions, or the initial dwell times are based on a required detection level for compounds corresponding to the plurality of transitions;
monitoring the transitions during a mass spectrometry analysis;
detecting a signal intensity above a first threshold for a first transition of the plurality of transitions;
increasing a dwell time for the first transition in response to the signal intensity being above the first threshold;
detecting the signal intensity for the first transition falling below a second threshold;
decreasing the dwell time for the first transition in response to the signal intensity falling below the second threshold.

US Pat. No. 10,892,151

LOCK MASS LIBRARY FOR INTERNAL CORRECTION

Micromass UK Limited, Wi...

1. A method of calibrating or optimising an analytical instrument comprising:analysing analyte from a sample using an analytical instrument by measuring one or more physico-chemical properties of said analyte;
determining a sample type of said sample based on one or more measured physico-chemical properties of analyte from said sample, wherein:
said sample type is one or more of: (a) a phenotypic characteristic, (b) a genotypic characteristic, and/or (c) a disease state of said sample, or
said sample is a microbial sample and said sample type is one or more of: (A) information about the genus, (B) information about the species, and/or (C) information about a strain of a microbe present in said sample;
identifying one or more species of said analyte that are known to be endogenous to said determined sample type; and
calibrating or optimising said analytical instrument using one or more measured physico-chemical properties of said one or more identified endogenous species;
wherein said step of identifying one or more species of said analyte that are known to be endogenous to said determined sample type comprises determining whether one or more species of said analyte correspond to one or more species for said determined sample type that are present in a predetermined list or library, wherein said predetermined list or library includes one or more selected species that are endogenous to each of a plurality of known sample types.

US Pat. No. 10,892,150

IMAGING MASS SPECTROMETER

SHIMADZU CORPORATION, Ky...

1. An imaging mass spectrometer capable of executing mass analysis of a two-dimensional area on a sample by irradiating a plurality of first measurement points with an ionization probe, the imaging mass spectrometer comprising:a processor configured to:
a) set a region of interest on the sample and define a first plurality of measurement points positioned discretely within the region of interest;
b) set one or more measurement areas that partially overlap with the region of interest, and define a second plurality of measurement points positioned discretely within each of the measurement areas, the second plurality of measurement points positioned so as not to completely overlap with the first plurality of measurement points or with measurement points within other measurement areas, wherein the second plurality of measurement points are set by displacing the first plurality of measurement points;
c) set, to each of the region of interest and the one or more measurement areas, or to each of the measurement areas, a measurement method including an analysis condition for executing the mass analysis; and
d) execute the mass analysis to the first plurality of measurement points and the second plurality of measurement points, the mass analysis being executed according to the measurement method set to each of the region of interest and the measurement areas by the measurement method setting unit.

US Pat. No. 10,892,149

OPTICAL DETECTORS AND METHODS OF USING THEM

PerkinElmer Health Scienc...

1. An optical detector comprising a photocathode configured to receive photons, an anode and a plurality of dynodes between the photocathode and the anode, in which each of the plurality of dynodes is configured to amplify an electron signal representative of the photons received by the photocathode, wherein at least two of the plurality of dynodes are electrically coupled to a respective electrometer, wherein the optical detector further comprises a processor configured to detect a signal from each respective electrometer and terminate signal amplification at a saturated dynode upstream of the anode.

US Pat. No. 10,892,148

INFLATABLE SEAL FOR MEDIA COOLING

SEAGATE TECHNOLOGY LLC, ...

1. A system comprising:a cooling chamber;
a first cooling plate within the cooling chamber;
a second cooling plate positioned opposite the first cooling plate within the cooling chamber;
a carrier configured to move a workpiece into the cooling chamber and position the workpiece between the first cooling plate and the second cooling plate; and
an inflatable seal surrounding a portion of the first cooling plate and the second cooling plate, wherein
the inflatable seal forms a gas channel between the first cooling plate and the second cooling plate when the inflatable seal is inflated, and the inflatable seal removes the gas channel between the first cooling plate and the second cooling plate when the inflatable seal is deflated.

US Pat. No. 10,892,147

METHOD AND APPARATUS FOR CALIBRATING OPTICAL PATH DEGRADATION USEFUL FOR DECOUPLED PLASMA NITRIDATION CHAMBERS

Applied Materials, Inc., ...

1. A method for determining optical path change in a substrate processing chamber including an optical emission spectroscopy measurement system, the method comprising:measuring a reference optical intensity of radiation from a light source through a first reference optical path with a reference spectrometer, the reference optical path in a reference chamber other than the substrate processing chamber, the reference optical path comprising at least one optical window;
measuring a second optical intensity of the radiation from the light source through a second optical path of the substrate processing chamber with the reference spectrometer, the second optical path having an attenuation of the radiation different from an attenuation of radiation of the first reference optical path;
comparing the reference optical intensity with the second optical intensity to obtain a correction factor for the second optical path, the correction factor being determined without opening the substrate processing chamber;
measuring a reference optical plasma intensity generated in the reference chamber through the reference optical path;
measuring a second optical plasma intensity generated in the substrate processing chamber through the second optical path;
comparing the second optical plasma intensity adjusted in accordance with the correction factor with the reference optical plasma intensity; and
creating a calibration table and adjusting a parameter setting of the substrate processing chamber by applying the calibration table.

US Pat. No. 10,892,146

ENDPOINT DETECTING METHOD AND ENDPOINT DETECTING APPARATUS

Tokyo Electron Limited, ...

6. An endpoint detecting apparatus for detecting an endpoint of a plasma process applied to a substrate, the endpoint detecting apparatus comprising:an optical emission spectrometer configured to monitor intensity of a predetermined wavelength component in an emission spectrum by optical emission spectroscopy;
a mass spectrometer configured to monitor intensity of a predetermined component in a mass spectrum by mass spectrometry; and
a controller including a central processing unit (CPU) and a memory storing a computer program that causes the CPU to perform processes including
a) monitoring, by the optical emission spectrometer, the intensity of the predetermined wavelength component in the emission spectrum;
b) monitoring, by the mass spectrometer, the intensity of the predetermined component in the mass spectrum;
c) calculating, by the CPU, a signal by calculating a product of the monitored intensity of the predetermined wavelength component in the emission spectrum and the monitored intensity of the predetermined component in the mass spectrum;
d) repeating a) to c) until an amount of change of the signal within a predetermined time is within a prescribed amount;
e) calculating a signal to noise ratio (S/N) of the signal;
f) determining whether a difference between a predetermined reference value and the S/N is equal to or smaller than a first threshold; and
g) in response to determining that the difference is equal to or smaller than the first threshold, starting another plasma process.

US Pat. No. 10,892,145

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A substrate processing method, comprising:providing a substrate into a process chamber;
introducing a reference light into the process chamber;
generating a plasma light in the process chamber while performing an etching process on the substrate;
receiving the reference light and the plasma light; and
detecting an etching end point by analyzing the plasma light and the reference light,
wherein detecting the etching end point includes a compensation adjustment based on a change rate of an absorption signal of the reference light with respect to a change rate of an emission signal of the plasma light, and
wherein receiving the reference light and the plasma light comprises filtering and receiving at least a portion having a transverse electric wave (TE) mode of the reference light and the plasma light.

US Pat. No. 10,892,144

PLASMA PROCESSING APPARATUS, MONITORING METHOD, AND MONITORING PROGRAM

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus comprising:a storage unit configured to store change information indicating a change in a value for a temperature of a mounting table when a processing condition of plasma processing for a target object mounted on the ting table is changed;
an acquisition unit configured to acquire the value for the temperature of the mounting table in a predetermined cycle; and
a monitoring unit configured to monitor, based on the change information, a change in the processing condition of the plasma processing from the change in the value for the temperature of the mounting table acquired by the acquisition unit.

US Pat. No. 10,892,143

TECHNIQUE TO PREVENT ALUMINUM FLUORIDE BUILD UP ON THE HEATER

Applied Materials, Inc., ...

1. A method for treating a substrate processing chamber, comprising:purging the substrate processing chamber, absent presence of a substrate, by introducing and flowing a purging gas comprising a silicon-containing gas into the substrate processing chamber at a substrate support temperature of about 500 degree Celsius or above and a chamber pressure of about 1 Torr to about 30 Torr, with a throttle valve of a vacuum pump system of the substrate processing chamber in a fully opened position, to deposit an amorphous silicon layer on at least a surface of a substrate support disposed within the substrate processing chamber, wherein the purging gas removes contaminants from the substrate processing chamber and is chemically reactive with deposition residue on exposed surfaces of the substrate processing chamber.

US Pat. No. 10,892,142

SYSTEM FOR FABRICATING A SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A system for fabricating a semiconductor device, comprising:a chamber;
an electrostatic chuck provided in the chamber and used to load a substrate;
a power source configured to supply an RF power having a first frequency to the electrostatic chuck;
an impedance matcher provided between the power source and the electrostatic chuck to connect the power source to the electrostatic chuck; and
a power transmission unit connecting the electrostatic chuck to the impedance matcher, wherein the power transmission unit comprises:
a power rod connected to the electrostatic chuck, the power rod having a first outer diameter; and
a coaxial cable including an inner wire, an outer wire, and a dielectric material between the outer and inner wires,
wherein the inner wire connects the power rod to the impedance matcher and has a second outer diameter less than the first outer diameter,
wherein the outer wire is directly connected to the chamber and is provided to enclose the inner wire and has a first inner diameter less than the first outer diameter and greater than the second outer diameter, and
wherein a ratio of the first inner diameter to the second outer diameter is greater than a dielectric constant of the dielectric material and less than three times the dielectric constant of the dielectric material, and wherein the first outer diameter of the power rod is 120 mm;
wherein the impedance matcher is configured to match chamber impedance of the RF power in the chamber,
wherein the chamber generates second to fourth harmonics having second to fourth frequencies corresponding to integral multiples of the first frequency using the RF power,
wherein the chamber impedance of the chamber includes real values and imaginary values of the second to fourth harmonics,
wherein an absolute value of the imaginary value of the chamber impedance for the third harmonic is greater than 10, and
wherein the chamber impedance of the chamber further includes real value and imaginary values of the RF power,
wherein an absolute value of the imaginary value of the chamber impedance for the RF power is less than 100, and
wherein the first frequency is 60 MHz.

US Pat. No. 10,892,139

ICP ANTENNA AND SUBSTRATE PROCESSING DEVICE INCLUDING THE SAME

EUGENE TECHNOLOGY CO., LT...

1. A method for processing a substrate disposed in a chamber using plasma generated in the chamber by an inductively coupled plasma (ICP) antenna, the ICP antenna comprising a first impedance having a first antenna coil positioned on a first region of the chamber and a second impedance having a second antenna coil positioned on a second region of the chamber, and a variable capacitor connected in parallel to the second antenna coil to form an LC circuit, the first impedance and the second impedance being connected in series to each other so that the ICP antenna having has one end connected to an RF power source through an impedance matching circuit and another end that is grounded, the method comprising:adjusting capacitance of the variable capacitor so that the LC circuit approaches a LC resonance condition;
increasing impedance of the second impedance and a total impedance of the ICP antenna; and
decreasing a total current of the ICP antenna and a density of a first plasma generated by the first antenna coil so that a uniformity of a total plasma generated in the chamber is controlled.

US Pat. No. 10,892,138

MULTI-BEAM INSPECTION APPARATUS WITH IMPROVED DETECTION PERFORMANCE OF SIGNAL ELECTRONS

ASML Netherlands B.V., V...

1. A crossover-forming deflector array of an electro-optical system for directing a plurality of electron beams onto an electron detection device, the crossover-forming deflector array comprising:a plurality of crossover-forming deflectors positioned at or at least near an image plane of a set of one or more electro-optical lenses of the electro-optical system, wherein each crossover-forming deflector is aligned with a corresponding electron beam of the plurality of electron beams.

US Pat. No. 10,892,137

ION IMPLANTATION PROCESSES AND APPARATUS USING GALLIUM

ENTEGRIS, INC., Billeric...

1. An ion source apparatus capable of generating gallium ions, the apparatus comprising:an arc chamber including an interior defined by interior surfaces that include sidewalls, a bottom, and a top; and
a consumable structure disposed in the arc chamber, wherein the consumable structure comprises one or more gallium-containing sheet structures disposed in the interior and covering one or more of the interior surfaces, the one or more gallium-containing sheet structures comprising gallium nitride, gallium oxide, or a combination thereof.

US Pat. No. 10,892,136

ION SOURCE THERMAL GAS BUSHING

Varian Semiconductor Equi...

1. A system for delivering feed gas to an ion source, comprising:a gas tube, having an inner channel in fluid communication with a dopant source; and
a gas bushing, having an inner channel in fluid communication with the inner channel of the gas tube and an ion source chamber, wherein the gas bushing has a thermal conductivity of less than 30 W/m K so as to thermally separate the gas tube from the ion source chamber.

US Pat. No. 10,892,135

X-RAY TUBE AND X-RAY GENERATION DEVICE

HAMAMATSU PHOTONICS K.K.,...

1. An X-ray tube comprising:a vacuum housing configured to include an internal space, the internal space being vacuum;
a target unit disposed in the internal space, and configured to include a target configured to generate an X-ray by using an electron beam incident therein, and a target support unit configured to support the target, the X-ray generated by the target being transmitted through the target support unit;
an X-ray emission window provided so as to face the target support unit, and configured to seal an opening of the vacuum housing, the X-rays transmitted through the target support unit being transmitted through the X-ray emission window;
an elastic member configured to press the target unit in such a direction as to approach the X-ray emission window; and
a target shift unit configured to shift the target unit pressed by the elastic member in a direction crossing an incidence direction of the electron beam.

US Pat. No. 10,892,134

X-RAY GENERATOR

RIGAKU CORPORATION, Akis...

1. An X-ray generator comprising:a target for receiving electrons and generating X-rays;
a separator for dividing an internal space of the target into a coolant inflow path and a coolant outflow path;
a target driving device for rotating said target;
a cooling system for supplying a coolant to said coolant inflow path and recovering the coolant through said coolant outflow path;
a hollow inner tube for supporting said separator so that the separator can rotate about a center of the separator; and
a gap for allowing said separator to rotate independently of the inner tube, the gap being provided to a portion of said inner tube that supports said separator;
wherein said separator rotates in the same rotation direction as said target when the target rotates.

US Pat. No. 10,892,133

X-RAY TUBE

FUJIFILM Corporation, To...

1. An X-ray tube comprising:an envelope that is a case;
a cathode assembly that emits electrons in the envelope; and
an anode including a first member of which at least a portion extends to the outside of the envelope, a second member that is provided in a direction perpendicular to a central axis of the first member, comes into contact with the first member, and has a higher X-ray shielding performance than the first member, and a target that receives the electrons emitted from the cathode assembly and generates X-rays,
wherein the first member is made of copper or an alloy including copper and molybdenum and the second member is made of an alloy including copper and molybdenum, and
wherein the second member has a first content portion whose molybdenum content is a first content and a second content portion whose molybdenum content is a second content higher than the first content, and a distance from the first member to the second content portion is greater than a distance from the first member to the first content portion.

US Pat. No. 10,892,132

SYSTEM AND METHOD FOR XENON RECOVERY

Versum Materials US, LLC,...

1. An apparatus for capture and recovery of a process gas comprising xenon from articles of manufacture, the apparatus comprising:(a) a feed hopper to receive feed comprising articles of manufacture having the process gas contained therein and having a conduit to a pressure vessel, wherein the process gas comprises xenon;
(b) the pressure vessel having a lid with an opening to receive the feed, a bottom which is in communication with a collection vessel, and a crusher contained therein wherein the pressure vessel is in fluid communication with a vacuum line, a valve in said vacuum line and a vacuum pump or a semi-hermetic scroll pump that evacuates the pressure vessel by removing air from said pressure vessel when all access points to said pressure vessel are closed and wherein the crusher crushes the articles of manufacture in the evacuated pressure vessel to provide a crude gas comprising xenon and glass residue;
(c) the collection vessel to receive the glass residue from the pressure vessel;
(d) a dust collection system in fluid communication with the pressure vessel to remove any residual dust that arises from the glass residue;
(e) a recovery line having a connection to the pressure vessel for removing the crude gas comprising xenon from the pressure vessel and sending it to a recovery vessel;
(f) a process controller;
(g) an automatic valve in the recovery line having a signal connection to the process controller; and
(h) the recovery vessel in electrical communication with the process controller wherein the recovery vessel comprises the crude gas comprising xenon.

US Pat. No. 10,892,131

FUSE SWITCH MODULE

GORLAN TEAM, S.L.U, Amor...

1. A fuse switch module comprising:a pair of fixed contacts and a fuse operable as rotary contact, wherein the fuse is rotatable about a rotation axis that extends through a point located between the fixed contacts, wherein the fuse is rotatable between a closed position, in which the rotary contact fuse is electrically connected to both of the fixed contacts to enable current circulation between the fixed contacts, and an open position, in which the rotary contact fuse is electrically isolated from the pair of fixed contacts to prevent current circulation between the fixed contacts;
wherein the fuse has two connection terminals at opposite ends thereof, and wherein the rotation axis extends transversally across the fuse through a point located between the two connection terminals;
wherein the fuse switch module further comprises two conductive blades detachably fitted respectively to the two connection terminals of the fuse and wherein the two conductive blades are configured to contact the fixed contacts when the fuse is in the closed position, and wherein each blade of the two conductive blades includes a generally Y-shaped portion such that each blade of the two conductive blades has a double-walled part that engages respectively with one of the fixed contacts by elastic deformation of the double-walled part, and wherein each blade of the two conductive blades has a single-walled part that can be inserted into one of the fixed contacts;
the fuse switch module further comprising a fuse cartridge made of an electrically insulating material, wherein the fuse is attached to the fuse cartridge such that the fuse and the fuse cartridge can rotate together, and wherein at least one of the two conductive blades protrudes outside the fuse cartridge.

US Pat. No. 10,892,130

PROTECTION DEVICE AND CIRCUIT PROTECTION APPARATUS CONTAINING THE SAME

POLYTRONICS TECHNOLOGY CO...

12. A circuit protection apparatus, comprising:a protection device, comprising:
a first planar substrate;
a second planar substrate attached to a lower surface of the first planar substrate to form a composite structure;
a heating element comprising an insulating layer and a heating layer disposed on the insulating layer, the heating element being disposed on the first planar substrate, the insulating layer being disposed between the first planar substrate and the heating layer; and
a fusible element disposed above the heating element; and
a detector senses a voltage drop or a temperature of a circuit to be protected; and
a switch coupled to the detector to receive signals of the detector;
wherein the switch turns on to allow current to flow through the heating element by which the heating element heats up to blow the fusible element when the detector senses the voltage drop or the temperature exceeding a threshold value.

US Pat. No. 10,892,129

ARC-PREVENTING FAST-BREAKING SURGE PROTECTION DEVICE

GUANGXI NQT ELECTRONIC TE...

1. An arc-preventing fast-breaking surge protection device, wherein the device comprises:an arc-preventing assembly comprising an arc-preventing catapult (4) and an elastic element (3);
a voltage sensitive assembly comprising at least one voltage sensitive element (5);
a response switch assembly comprising a thermosensitive element (30), a front electrode (51) and a tripping electrode (6), the tripping electrode (6) being consisted of a movable electrode slice (6a), an electrode welding end (6b) and a breaking section (6c), the breaking section (6c) being respectively electrically connected the movable electrode slice (6a) and the electrode welding end (6b);
electrode pins comprising a flexible conductor (7), a first electrode pin (8) and a second electrode pin (9); and
a housing comprising an inner shell (1) and an outer cover (2);
wherein the response switch assembly is a normally closed switch in a normal operating state, the thermosensitive element (30) is electrically connected in series and tightly thermally coupled with the voltage sensitive assembly; when the thermosensitive element (30) melts as the thermosensitive element reaches a preset melting temperature, the tripping electrode (6) is separated from the front electrode (51) due to an elastic stress of the elastic element (3), the tripping electrode (6) is rapidly catapulted and concealed in the arc-preventing catapult (4), meanwhile the arc-preventing catapult (4) is rapidly catapulted in a direction away from the front electrode (51) due to an elastic stress of the elastic member (3), thereby preventing arc generated during instantaneous catapulting of the tripping electrode (6) from forming an electrical breakdown and causing a short circuit and an overload;
wherein when an instantaneous surge overvoltage, an overcurrent, a short circuit current or an overloading current through the breaking section (6c) exceeds a preset threshold value, the breaking section (6c) instantaneously melts and vaporizes so that the movable electrode slice (6a) separates from the electrode welding end (6b), while the arc-preventing catapult (4) and the movable electrode slice (6a) are rapidly catapulted in a direction away from the front electrode (51) due to the elastic stress of the elastic element (3), the movable electrode slice (6a) is concealed in the arc-preventing catapult (4), thus preventing arc generated during instantaneous melting and catapulting from forming an electrical breakdown and causing a short circuit and an overload;
wherein a first cavity (1a) and a second cavity (1b) are formed when the inner shell (1) is engaged with the outer cover (2), the arc-preventing assembly and the response switch assembly is arranged in the first cavity (1a), the voltage sensitive element (5) is arranged in the second cavity (1b);
wherein two metal electrode slices are respectively disposed on both sides of the voltage sensitive element (5), the front electrode (51) is disposed on one of the metal electrode slices, the front electrode (51) protrudes from the second cavity (1b) to the first cavity (1a), the other metal electrode slice is provided with a back electrode (52), the back electrode is in the second cavity (1b);
wherein the elastic element (3) is consisted of a first elastic member (3a) and a second elastic member (3b), the first elastic member (3a) is disposed on the arc-preventing catapult (4), the second elastic member (3b) is disposed in the first cavity (1a);
wherein the first cavity (1a) is provided with an inserting groove (14), and the second cavity (1b) is provided with a blocking groove (15); the first electrode pin (8) enters the first cavity (1a) through the inserting groove (14), and the second electrode pin (9) enters the second cavity (1b) through the blocking groove (15); two ends of the flexible conductor (7) are respectively electrically connected to the movable electrode slice (6a) and an inner end (8b) of the first electrode pin (8) by metal alloy soldering or spot welding, the back electrode (52) is electrically connected to an inner end (9b) of the second electrode pin (9) by metal alloy soldering; an outer end (8a) of the first electrode pin (8) and an outer end (9a) of the second electrode pin (9) extends out of the inner shell (1) to form external connection pins;
wherein the front electrode (51) is provided with a slotted hole (51a); the tripping electrode (6) is concealed in the arc-preventing catapult (4), the movable electrode slice (6a) of the tripping electrode (6) is misaligned by the first elastic member (3a); the arc-preventing catapult (4) thereon is misaligned by the second elastic member (3b);
wherein a front end of the arc-preventing catapult (4) is provided with a through hole (4a) which is a port out of which the electrode welding end (6b) protrudes; when the arc-preventing catapult (4) contacts with the front electrode in the first cavity (1a), the through hole (4a) faces the position of the slotted hole (51a); the arc-preventing catapult (4) is provided with an exhaust vent (4b), when the tripping electrode (6) is disposed in the arc-preventing catapult (4) and the electrode welding end (6b) protrudes out of the through hole (4a), the breaking section (6c) faces the position of the exhaust vent (4b).

US Pat. No. 10,892,128

RESIDUAL CURRENT PROTECTION DEVICE AND TRIPPER

ABB S.P.A., Baden (CH)

1. A residual-current protection device, comprising:a flux transformer receiving a residual-current signal;
a tripping output element outputting ON/OFF signals;
an energy storage mechanism adapted to switch between an energy storage state and an energy release state, the energy storage mechanism having a locking unit that locks the energy storage mechanism in the energy storage state; and
a transmission mechanism braked by the flux transformer, which drives the tripping output element to move and drives the energy storage mechanism to switch its state, the transmission mechanism including:
a first rack cooperating with the locking unit;
a second rack driving the tripping output element; and
a reduction gear, having a big gear engaged with the first rack and a small gear engaged with the second rack.

US Pat. No. 10,892,127

CONTACTOR ASSEMBLY FOR DISTRIBUTION BOARD

LSIS CO., LTD., Anyang-s...

1. A contactor assembly connected to a bus-bar of a main circuit-breaker, the assembly including:a housing including an opening defined therein;
a contactor passing through the opening and coupled to the housing, wherein the contactor includes contacting portions projecting forwardly of the opening and coupled portions projecting rearwardly of the opening;
a presser passing through the opening and coupled to the housing, wherein the presser is interposed between the contactor and the housing, wherein the presser is supported on the housing and presses the contacting portions and the coupled portions; and
a connector coupled to the coupled portions of the contactor and electrically connected to the contactor,
wherein the connector includes a protrusion protruding outwardly therefrom and having a circular cross section, wherein the protrusion is configured to be fitted into a space between the coupled portions, wherein the contactor is configured to rotate around the protrusion,
wherein the housing includes side guards defining both side boundaries of the opening respectively, wherein the connector is connected to the coupled portions while the coupled portions and at least a portion of the connector are received between the side guards, wherein each of the side guards includes a spacer protruding toward a center of the opening, wherein each of both sides of the contactor contacts each spacer such that each of the both sides of the contactor is spaced apart by a predetermined gap from each of the side guards.

US Pat. No. 10,892,126

METHOD OF PRODUCING A TEMPERATURE-TRIGGERED FUSE DEVICE

Manufacturing Networks In...

1. A method for producing a temperature-triggered fuse device, the method comprising the steps of:placing a first metal pad and a second metal pad on top of a base substrate, wherein the first metal pad and the second metal pad are separated by a gap formed on the base substrate;
depositing an electrically-insulating de-wetting film on top of the base substrate and below the gap;
depositing a first de-wetting material coating on a portion of the first metal pad and a second de-wetting material coating on a portion of the second metal pad;
depositing a first wetting material bay on a remaining portion of the first metal pad and a second wetting material bay on a remaining portion of the second metal pad; and
placing a solder bridge or a solder ball on top of an inner segment of the first wetting material bay and an inner segment of the second wetting material bay across the gap on the base substrate coated with the electrically-insulating de-wetting film.

US Pat. No. 10,892,125

ELECTROMAGNETIC RELAY

Omron Corporation, Kyoto...

1. An electromagnetic relay comprising: a housing including a first compartment and a second compartment mutually separated by an insulating wall;a first fixed contact terminal secured to the housing and extending from outside the housing to the first compartment, the first fixed contact terminal including a first fixed contact point in the first compartment;
a second fixed contact terminal secured to the housing and extending from outside the housing to the first compartment, the second fixed contact terminal electrically isolated from the first fixed contact terminal and including a second fixed contact point in the first compartment;
a movable contact arranged in the first compartment, and including a first movable contact point and a second movable contact point, the first and second movable contact points facing the first and second fixed contact points which are arranged between the first and second movable contact points and the insulating wall; the first and second movable contact points configured to travel in a contact movement direction in which the first and second movable contact points make contact with and separate from the first and second fixed contact points;
a movable shaft extending from the first compartment to the second compartment in the contact movement direction with one end in the extension direction arranged in the first compartment and the other end in the extension direction arranged in the second compartment via a through-hole that passes through the insulating wall in the contact movement direction, the one end in the extension direction connected to the movable contact in the first compartment and configured to travel together with the movable contact in the contact movement direction; and
a solenoid in the second compartment configured to drive the movable shaft in the contact movement direction;
the solenoid including:
a spool that includes: a through-hole extending in the contact movement direction and accommodating the other end of the movable shaft, a coil, and a drum with the coil wrapped around the drum in the contact movement direction;
a fixed armature secured in a second through-hole to the far end of the second through-hole relative to the insulating wall in the contact movement direction;
a movable armature arranged in the second through-hole between the fixed armature and the insulating wall and attached to the other end of the movable shaft, the movable armature configured to travel with the movable shaft in the contact movement direction between an operation position and a return position;
the housing including:
an alignment part provided in the second compartment at the insulating wall, the alignment part determining the return position of the movable armature,
wherein the alignment part includes a positioning bump, the positioning bump being a plurality of bumps that each protrude from the insulating wall in the contact movement direction toward the movable armature and each touch the movable armature when the movable armature is at the return position.

US Pat. No. 10,892,124

LOAD CONTROL DEVICE HAVING STUCK RELAY DETECTION

Lutron Technology Company...

1. A load control device for controlling power delivered from an AC power source to a light-emitting diode (LED) driver for an LED light source, the load control device comprising:a first electrical connection adapted to be electrically coupled to the AC power source;
a second electrical connection adapted to be electrically coupled to the LED driver;
a relay electrically coupled between the first and second electrical connections and configured to generate a switched-hot voltage at the second electrical connection and control the power delivered from the AC power source to the LED driver;
a detect circuit electrically coupled to the second electrical connection and configured to generate a detect signal indicating a magnitude of the switched-hot voltage; and
a control circuit configured to generate a drive signal for attempting to open and close the relay and configured to determine whether the relay is open or closed based on the detect signal;
wherein the control circuit is further configured to perform a stuck closed procedure in response to determining that the relay is stuck closed, the stuck closed procedure comprising the control circuit attempting to close the relay prior to attempting to open the relay, attempting to open the relay after attempting to close the relay, monitoring the detect signal after attempting to open the relay, and determining whether the relay is stuck closed.

US Pat. No. 10,892,123

SAFETY SWITCH WITH DETECTION OF THE DRIVING OF AN AUXILIARY UNLOCKING CONTROL

PIZZATO ELETTRICA S.R.L.,...

1. A safety switch with detection of a drive of an auxiliary unlocking control adapted to supervise a safety access of a machine or industrial plant, comprising:a switching device (2) adapted to be associated to a fixed part of an access to be supervised and having a casing (4) defining a longitudinal axis (X) and housing switching means (5) adapted to be operatively connected to one or more control and/or service circuits for the control thereof;
an operating device (3) associated to a movable part of the access to interact with said switching means (5) at the time of opening/closing of the access for opening/closing one or more of said circuits;
an unlocking mechanism (13) housed in said casing (4) and having an unlocking pin (14) adapted to translate longitudinally with a maximum predetermined stroke from a locking position of the access to an unlocking position to operate the opening of said switching means (5);
means (17) for detection of the stroke of said unlocking pin (14) having at least one first detector (18) adapted to detect the start of the stroke of said unlocking pin (14);
at least one auxiliary unlocking control (25, 26) operatively connected to said unlocking mechanism (13) and susceptible to move from a rest position to an operative position of unlocking of the access and promote the translation of said unlocking pin (14) even with said actuator device (3) inserted;characterized in that said detection means (17) comprise at least one auxiliary detector (31) adapted to detect the actuation of said at least one auxiliary unlocking control (25, 26).

US Pat. No. 10,892,122

TRIGGER ASSEMBLY WITH A PROTECTIVE COVERING

DEFOND ELECTECH CO., LTD....

1. A trigger assembly for use with an electrical device to operate said electrical device, said electrical device having an electric switch housing with an electrical switch unit disposed therein, the trigger assembly including;a trigger member configured for movement relative to the housing;
an actuator member operably-connected to the trigger member and, responsive to movement of the trigger member relative to the housing, said actuator member being movable in a first direction relative to the housing from an OFF position in which the electrical switch is operably-opened by the actuator member towards an ON position in which the electrical switch is operably-closed by the actuator member, and, movable in a second direction relative to the housing from the ON position towards the OFF position;
a locking assembly mounted on the trigger member, the locking assembly including a locking member configured for rotatable movement relative to the trigger member between a plurality of rotatable positions so as to enable selectable locking of the actuator member in to either of the ON or OFF position depending upon the rotatable position of the locking member relative to the trigger member, the locking assembly further including a torsion spring operable with the locking member so as to urge the locking member towards at least one of the plurality of rotatable positions of the locking member relative to the trigger member;
a covering that is separately formed from the locking member, the covering being configured to complement a shape contour of the torsion spring, and, being configured for fitting around the torsion spring so as to alleviate ingress of dust, water and other particulates in to contact with the torsion spring; and
whereby, the covering is configured to freely rotate about the torsion spring when fitted around the torsion spring and when the locking member is rotated relative to the trigger member.

US Pat. No. 10,892,121

LIGHT-EMITTING KEYSWITCH, CAP STRUCTURE AND CAP STRUCTURE MANUFACTURING METHOD THEREOF

DARFON ELECTRONICS CORP.,...

1. A light-emitting keyswitch comprising:a board;
a lifting mechanism disposed on the board; and
a cap structure assembled with the lifting mechanism to be movable upward and downward relative to the board, the cap structure comprising:
a cap having a top surface and a lateral contour surface; and
a light-emitting layer comprising:
a first pad layer disposed on the lateral contour surface;
at least one lower electrode layer disposed on the top surface to be connected to the first pad layer, the at least one lower electrode layer having an opening;
a second pad layer disposed on the lateral contour surface corresponding to the opening and spaced apart from the at least one lower electrode layer;
a dielectric layer stacked on the lower electrode layer;
an electroluminescent layer stacked on the dielectric layer;
an upper electrode layer stacked on the electroluminescent layer and connected to the second pad layer;
a transparent pattern layer stacked on the upper electrode layer; and
an external trace structure connected to the first pad layer and the second pad layer for transmitting a power to the upper electrode layer and the lower electrode layer via the first pad layer and the second pad layer, so as to drive the electroluminescent layer to emit light to the transparent pattern layer.

US Pat. No. 10,892,120

ELECTRIC SWITCH OF THE NORMALLY OPEN TYPE

1. An electric switch of a normally open type, including: a body made of insulating material; an actuator which is moveably installed with respect to the body between a high rest position in which the actuator abuts against a facing portion of the body, and a low active contact position; a first contact blade supported by the body which is elastically deformable when action of the actuator between: the high rest position in which the first contact blade elastically abuts upwards against a facing portion of the actuator, the actuator being elastically returned to its high rest position by the first contact blade, and the low active contact position; and a second contact blade supported by the body which is elastically deformable downwards from a rest position in which it elastically abuts upwards directly against the facing portion of the body, or indirectly with interposition of a part of the actuator, wherein: a first contact section belonging to the first contact blade extends above a second contact section belonging to the second contact blade, the first and second contact sections are superposed and are vertically distanced from each other when the actuator is in its high rest position, and are in mutual electrical contact when the actuator is in its low active contact position so as to establish an electrical switching path, the first and the second contact sections are arranged in parallel and in opposite directions, and the second contact section includes a central opening which is able to accommodate the first contact section.

US Pat. No. 10,892,119

PUSH SWITCH

PANASONIC INTELLECTUAL PR...

1. A push switch comprising:a first fixture contact;
a second fixture contact;
a member that holds the first fixture contact and the second fixture contact;
a movable member positioned opposite a surface of the member in an operation direction;
a contact member that possesses electrical conductivity, the contact member being positioned on an opposite side of the movable member to the surface of the member in the operation direction; and
a press unit positioned on an opposite side of the movable member to the surface of the member in the operation direction,
wherein
the movable member includes a first movable contact, a second movable contact, and a movable joint, the first movable contact moving between a location at which the first movable contact is in contact with the first fixture contact and a location at which the first movable contact is separated from the first fixture contact, the second movable contact moving between a location at which the second movable contact is in contact with the second fixture contact and a location at which the second movable contact is separated from the second fixture contact, the movable joint joining the first movable contact to the second movable contact, the movable joint electrically connecting the first movable contact to the second movable contact,
the contact member includes a first support and a second support that are supported by the member and a joint that joins the first support to the second support,
the movable joint is disposed between the joint and the member, and
neither the first support nor the second support overlaps the movable member in a planar view, wherein
the movable joint includes a third movable contact,
the third movable contact has a pressure receiving section,
the third movable contact moves between a location at which the third movable contact is in contact with the contact member and a location at which the third movable contact is separated from the contact member,
in a stationary state where no external force acts on the pressure receiving section, the first fixture contact is electrically connected to the contact member, and the first fixture contact is electrically connected to the second fixture contact,
when the stationary state is transited to a first operation state where the pressure receiving section is pressed through the press unit toward the surface of the member in the operation direction, the third movable contact becomes separated from the contact member to break off an electrical connection between the first fixture contact and the contact member, and
when the first operation state is transited to a second operation state where the pressure receiving section is further pressed through the press unit, the first movable contact becomes separated from the first fixture contact and the second movable contact becomes separated from the second fixture contact, to break off an electrical connection between the first fixture contact and the second fixture contact.

US Pat. No. 10,892,118

BUTTON MODULE

Wistron Corporation, New...

1. A button module comprising: a casing comprising a first accommodating recess, a first engaging portion and a retaining platform, the retaining platform being located within the first accommodating recess; a button body disposed in the first accommodating recess, the button body comprising a first positioning portion; an elastic body disposed between the button body and the retaining platform, the elastic body abutting against the retaining platform; and a cover comprising a second engaging portion, a second positioning portion and a retaining portion, the second engaging portion engaging with the first engaging portion, the second positioning portion protruding from a surface of the cover and being disposed in the first positioning portion so that the button body is positioned in the first accommodating recess, the retaining portion abutting against the retaining platform within the first accommodating recess; wherein the button body inclines to the cover, the cover further comprises a second restraining portion, and the second restraining portion abuts against the button body; wherein the casing further comprises a third restraining portion, and the button body is sandwiched in between the second restraining portion and the third restraining portion.

US Pat. No. 10,892,117

METHOD FOR THE INITIAL ADJUSTMENT OF A CONTROL DEVICE FOR ELECTRONIC EQUIPMENT

1. A method for adjustment of a control device for electronic equipment, comprising:applying a preload force simultaneously to shafts of a control device so as to take up initial assembly play, wherein the control device comprises:
an upper actuating element having an upper actuating face, on which a user can exert at least one control action by applying a generally downwardly directed pressure to the upper actuating face,
a lower supporting mounting, the upper actuating element being mounted so as to be movable relative to the lower supporting mounting by a vertical movement between an upper rest position, towards which the upper actuating element may be returned elastically, and an active lower position,
a switch which is actuated by the upper actuating element when the upper actuating element is in the active lower position, and
an articulated structure that is interposed vertically between the upper actuating element and the lower supporting mounting to keep the upper actuating element parallel to a horizontal plane during vertical downward movement of the upper actuating element relative to a frame, wherein the articulated structure comprises at least one of the shafts; and
providing an adjustment stop fixed on the lower supporting mounting and forming a stop surface which interacts with a facing portion of the at least one shaft by:
vertically positioning a stop member relative to the lower supporting mounting in such a way that a front end face of the stop member is in contact with the facing portion of the at least one shaft, wherein the stop member comprises a stop pin that is mounted so as to be axially slidable in a vertical direction in a complementary hole in the lower supporting mounting,
vertically fixing the stop member on the lower supporting mounting to lock the stop member in an adjusted position under the preload force, and
removing the preload force.

US Pat. No. 10,892,116

DURABLE AND SECURED SWITCH ASSEMBLY

1. A durable and secured switch apparatus comprising:an alternate action switch comprising a switch body, a push button on a proximal end of the switch body, and two primary cable terminals on a distal end of the switch body, wherein the two primary cable terminals are configured for in-line coupling of separate ends of a primary cable;
a housing having a lumen configured to securely retain the switch body, wherein said lumen is further configured with a first peripheral spacing between said switch body and a first section of said lumen at the proximal end of said switch body, and a second peripheral spacing between said switch body and a second section of said lumen at the distal end of said switch body, wherein said lumen further includes a stop between said first section and said second section to prevent downward movement of the switch body within said housing and a peripheral notch in said second section, wherein the two primary cable terminals are perpendicular with respect to the peripheral notch and the primary cable channel, wherein said housing further includes a first part of a primary cable channel running across and centered at said distal end of said housing, wherein at least a top surface of the push button is located external to the housing; and
a cover configured to snap fit into said peripheral notch to secure said cover to said housing and enclose said primary cable terminals, wherein said cover includes a cavity for said primary cable terminals, wherein said cover further includes a second part of said primary cable channel running from one side of said cover to an opposing side of said cover, wherein said first part and said second together form said primary cable channel configured for electrically in-line coupling of the primary cable terminals with the primary cable.

US Pat. No. 10,892,115

LASER-CUT BUTTON VENEER FOR A CONTROL DEVICE HAVING A BACKLIT KEYPAD

Lutron Technology Company...

1. A control device comprising a button with a metal veneer that is configured to be secured to a backlit portion of the control device, the control device comprising:a translucent carrier portion configured to be backlit by one or more light emitting diodes;
a metal plate portion having a front surface to be depressed to actuate the button, and a rear surface opposite the front surface, the metal plate portion including one or more indicia defined through the front surface and the rear surface by a laser cutting process, wherein the metal plate portion is configured to be secured to the translucent carrier portion; and
a filler material that is disposed in the one or more indicia of the metal plate portion, wherein the filler material forms a filler surface within the one or more indicia thereby reducing an effective depth of the one or more indicia, wherein the filler surface is at least one of subsurface or convex to the front surface of the metal plate portion.

US Pat. No. 10,892,114

INERTIAL SHORT-CIRCUIT AND SEISMIC HOOK

General Electric Technolo...

1. A circuit disconnect apparatus comprising:a catch device mounted to a first conductor of a circuit, wherein the catch device is connected to the first conductor such that the catch device moves from a first position to a second position along a predetermined first path for a speed of movement below a limiting speed, and that the catch device moves, during a seismic event or an unexpected short circuit event, along a predetermined second path for a speed of movement above the limiting speed;
wherein when moving along the predetermined second path, the catch device engages a stop device, thereby preventing the circuit disconnect apparatus from disconnecting.

US Pat. No. 10,892,113

ROTATING HANDLE DEVICE

1. A rotary handle device comprising:a sliding button;
a grip having:
a first end into which at least a portion of the sliding button is received; and
a second end;
an attachment base having:
a first end into which the second end of the grip is received; and
a second end;
wherein the grip is releasably mounted to the attachment base; and
wherein the grip is rotatable while mounted to the attachment base;
a sliding limiting drive member located within the attachment base;
a fixing cover mounted in proximity to the second end of the attachment base;
a complementary steering guide;
a cruciform-shaped latch; and
pressure fastening engagements snap-fits;
wherein the grip, sliding button, attachment base and fixing cover are engagingly communicative to one another to form the rotary handle device via the pressure fastening engagements snap-fits.

US Pat. No. 10,892,112

METHOD OF MAKING AN ENERGY STORAGE ARTICLE

RAYTHEON TECHNOLOGIES COR...

20. A method of making metal nitride, comprising nitriding particles comprising a metal, NH4VO3, or oxide of a metal selected from molybdenum, titanium, niobium, or tungsten, or combinations comprising any of the foregoing by contacting the particles with a gas mixture comprising nitrogen and hydrogen in a fluidized bed reactor to form particles comprising metal nitride to convert at least 95 wt. % of the metal in the particles to metal nitride.

US Pat. No. 10,892,111

ENERGY STORAGE DEVICE

GS YUASA INTERNATIONAL LT...

1. An energy storage device, comprising:an electrode terminal;
an electrode assembly; and
a current collector which connects the electrode terminal and the electrode assembly,
wherein the current collector includes:
a first connecting portion which is connected with the electrode terminal; and
a second connecting portion which is connected with the electrode assembly and the first connecting portion,
wherein the first connecting portion includes:
a base portion which is connected to the second connecting portion; and
an attachment portion which is provided to protrude from the base portion in a direction which is opposite to a direction toward the electrode terminal,
wherein, in the attachment portion, a through hole through which a shaft portion of the electrode terminal is inserted is formed, and
wherein the first connecting portion further includes a recessed portion which is provided to recess from the base portion in the direction which is opposite to the direction toward the electrode terminal.

US Pat. No. 10,892,110

ELECTROLYTE SOLUTION FOR ELECTROCHEMICAL DEVICE, AND ELECTROCHEMICAL DEVICE

TAIYO YUDEN CO., LTD., T...

1. An electrolyte solution for electrochemical device, comprising:a cyclic carbonate solvent containing 1.0 mol/L to 1.6 mol/L of LiPF6 as an electrolyte;
an oxalate complex salt of lithium whose additive quantity relative to the electrolyte solution accounts for 1.0 percent by weight to 3.0 percent by weight; and
a straight-chain carbonate whose additive quantity relative to the electrolyte solution accounts for 1.0 percent by weight to 9.0 percent by weight.

US Pat. No. 10,892,109

HIGH-VOLTAGE DEVICES

The Regents of the Univer...

1. An energy storage device comprising:an array of electrodes, wherein each electrode comprises:
a current collector; and
an active material directly on a portion of a first surface of the current collector,
wherein the active material comprises two or more expanded and interconnected carbon layers, wherein at least one of the carbon layers is corrugated and one atom thick, and wherein a portion of the carbon layers is separated by a distance of about 25 nm to about 150 nm.

US Pat. No. 10,892,108

ELECTROCHEMICAL DEVICE

TAIYO YUDEN CO., LTD., T...

1. An electrochemical device comprising:a positive electrode having: a positive-electrode collector made of conductive material; and positive-electrode active-material layers formed on the positive-electrode collector;
a negative electrode having: a first and second negative-electrode active-material layers; and a negative-electrode collector having: (i) a first principal face on which the first negative-electrode active-material layer is formed, and (ii) a second principal face having a coated area where the second negative-electrode active-material layer is formed, and uncoated areas, separated by the coated area, where the second negative-electrode active-material layer is not formed, wherein an area of the first principal face opposite correspondingly to the uncoated areas of the second principal face of the negative-electrode collector is a coated area where the first negative-electrode active-material layer is formed, and wherein the negative-electrode collector has multiple through holes that interconnect the first principal face and the second principal face, where a boundary of the coated area and the uncoated area of the second principal face intersects an opening of at least one of the multiple through holes;
separators that insulate the positive electrode and the negative electrode; and
an electrolyte in which the positive electrode, negative electrode, and separators are immersed;
wherein the uncoated areas of the second principal face have: (a) a first uncoated area where a metallic lithium is attached to the first uncoated area and immersed in the electrolyte, to pre-dope the first and second negative-electrode active-material layers with lithium ions, and (b) a second uncoated area where a negative electrode terminal is attached to the second uncoated area, wherein the metallic lithium is separated from the negative-electrode terminal by the coated area of the second principal face.

US Pat. No. 10,892,106

HIGHLY STABLE ELECTRONIC DEVICE EMPLOYING HYDROPHOBIC COMPOSITE COATING LAYER

Global Frontier Center fo...

1. An electronic device, comprising:an assembly including at least one electronic portion or component; and
a composite coating layer covering at least part of the assembly including the at least one electronic portion or component, the composite coating layer comprising an ambiphilic polymer material containing both hydrophilic and hydrophobic organic groups and having nanoparticles embedded therein, wherein the nanoparticles comprise one or more of reduced graphene oxide (rGO), graphene oxide, CeO2, and SnO2.

US Pat. No. 10,892,105

MULTI-LAYER CAPACITOR PACKAGE

International Business Ma...

1. A substrate assembly comprising:a first ceramic layer;
a first layer of one or more electrodes connected to the ceramic layer;
a high dielectric constant layer connected to the first layer of one or more electrodes,
wherein the high dielectric constant layer is composed of different material than the ceramic layer;
a second layer of one or more electrodes connected to the high dielectric constant layer
wherein the high dielectric constant layer is composed of direct contact with the first layer of one or more electrodes and the second layer of one or more electrodes;
a second ceramic layer connected to the second layer of one or more electrodes,
wherein the second ceramic layer is a different material than the high dielectric constant layer;
two or more holes, wherein each of the two or more holes is formed through at least one ceramic layer, at least one layer of one or more electrodes, and at least one high dielectric constant layer; and
electrically conductive structures formed in the two or more holes,
wherein each of the electrically conductive structures is physically connected to at least one of the electrodes, thereby forming sets,
wherein each of the sets is physically separated from at least one of the other sets.

US Pat. No. 10,892,104

MULTILAYER CERAMIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A multilayer ceramic capacitor comprising:a laminated body including a plurality of dielectric layers and a plurality of internal electrodes laminated in a lamination direction; and
a plurality of external electrodes electrically connected to respective ones of the internal electrodes; wherein
the laminated body includes a first principal surface and a second principal surface opposed in the lamination direction, a first side surface and a second side surface opposed in a width direction perpendicular or substantially perpendicular to the lamination direction, and a first end surface and a second end surface opposed in a length direction perpendicular or substantially perpendicular to both the lamination direction and the width direction;
the plurality of internal electrodes include first internal electrodes exposed at the first end surface, and second internal electrodes exposed at the second end surface;
the laminated body includes outer layer portions provided at a top and a bottom of the laminated body in the lamination direction, and an inner layer portion between the outer layer portions;
the plurality of external electrodes include a first external electrode covering the first end surface and electrically connected to the first internal electrodes, and a second external electrode covering the second end surface and electrically connected to the second internal electrodes;
side margin portions sandwich the plurality of dielectric layers in the width direction;
segregation portions in which Si and Mg are segregated are provided at an edge of at least one of the plurality of internal electrodes in the width direction; and
the side margin portions have a dimension of about 5 ?m or more and about 40 ?m or less in the width direction.

US Pat. No. 10,892,103

MULTILAYER CERAMIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A multilayer ceramic capacitor comprising:a laminated body including a plurality of dielectric layers and a plurality of internal electrodes laminated in a lamination direction; and
a plurality of external electrodes electrically connected to respective ones of the internal electrodes; wherein
the laminated body includes a first principal surface and a second principal surface opposed in the lamination direction, a first side surface and a second side surface opposed in a width direction perpendicular or substantially perpendicular to the lamination direction, and a first end surface and a second end surface opposed in a length direction perpendicular or substantially perpendicular to both the lamination direction and the width direction;
the plurality of internal electrodes include first internal electrodes exposed at the first end surface, and second internal electrodes exposed at the second end surface;
the laminated body includes outer layer portions provided at a top and a bottom of the laminated body in the lamination direction, and an inner layer portion between the outer layer portions;
the plurality of external electrodes include a first external electrode covering the first end surface and electrically connected to the first internal electrodes, and a second external electrode covering the second end surface and electrically connected to the second internal electrodes;
side margin portions sandwich the plurality of dielectric layers in the width direction;
each of the side margin portions includes Si; and
in at least one cross sectional view in the width and lamination directions, the Si included in at least one of the side margin portions includes a plurality of Si segregation portions, and at least two of the plurality of Si segregation portions are located in a region that has a dimension extending in the lamination direction of approximately 2.5 ?m and a dimension extending in the width direction of approximately 2.5 ?m.

US Pat. No. 10,892,102

MULTI-LAYER CERAMIC CAPACITOR

Taiyo Yuden Co., Ltd., T...

1. A multi-layer ceramic capacitor, comprising:a ceramic body that includes
ceramic layers laminated along a first axial direction,
first internal electrodes and second internal electrodes that are alternately disposed between the ceramic layers,
a first end surface to which the first internal electrodes are drawn,
a second end surface to which the second internal electrodes are drawn,
a first end margin that forms an interval between the first end surface and the second internal electrodes, and
a second end margin that forms an interval between the second end surface and the first internal electrodes;a first external electrode that covers the first end surface and is connected to the first internal electrodes; anda second external electrode that covers the second end surface and is connected to the second internal electrodes,
the multi-layer ceramic capacitor satisfying the following relationship:
SE?S/400+300,
where S (?m2) represents an area of the ceramic body and SE (?m2) represents a total area of the first internal electrodes and the second internal electrodes in cross sections of the first end margin and the second end margin that are respectively parallel to the first end surface and the second end surface,
wherein main phases of polycrystal constituting the ceramic layers have a composition of CaxZrO3, where 0.90?x?1.15, and
wherein the multi-layer ceramic capacitor satisfies the following relationship:
SE?3000.

US Pat. No. 10,892,101

MULTILAYER CERAMIC CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic capacitor, comprising:a body including a dielectric layer and an internal electrode; and
an external electrode disposed on the body,
wherein the external electrode comprises an electrode layer connected to the internal electrode, a first plating portion disposed on the electrode layer and having a thickness ranging from 0.3 ?m to 1 ?m, and a second plating portion disposed on the first plating portion,
the first plating portion comprises an Sn plated layer, and the second plating portion comprises an Ni plated layer and an Sn plated layer sequentially disposed on the first plating portion,
the first plating portion and the second plating portion have an Sn—Ni intermetallic compound layer disposed at an interfacial area therebetween, and
the Sn—Ni intermetallic compound layer has an outer surface substantially covered by the Sn plated layer of the second plating portion.

US Pat. No. 10,892,100

MULTILAYER CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor, comprising:a capacitor body having a first surface and a second surface opposing each other in a first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposing each other, and a fifth surface and a sixth surface connected to the first surface and the second surface, connected to the third surface and the fourth surface, and opposing each other, and including a plurality of dielectric layers, and pluralities of first internal electrodes, second internal electrodes, and third internal electrodes alternately disposed with the dielectric layers interposed therebetween;
a connecting electrode disposed on the second surface of the capacitor body;
a first external electrode and a second external electrode disposed on the third surface and the fourth surface of the capacitor body, respectively; and
a third external electrode and a fourth external electrode disposed on the fifth surface and the sixth surface of the capacitor body, respectively,
wherein the first internal electrodes are exposed through the fifth surface of the capacitor body, and are connected to the third external electrode,
the second internal electrodes are exposed through the sixth surface of the capacitor body, and are connected to the fourth external electrode,
the third internal electrodes are exposed through the third surface and the fourth surface of the capacitor body, and are connected to the first external electrode and the second external electrode,
the third external electrode contacts portions of the first internal electrodes exposed through the fifth surface and extends onto the second surface of the capacitor body to cover, and overlap in the first direction, a first end of the connecting electrode, and
the fourth external electrode contacts portions of the second internal electrodes exposed through the sixth surface and extends onto the second surface of the capacitor body to cover, and overlap in the first direction, a second end of the connecting electrode opposite to the first end.

US Pat. No. 10,892,099

FRINGE CAPACITOR FOR HIGH RESOLUTION ADC

NXP USA, Inc., Austin, T...

1. A shielded fringe capacitor formed in at least three conductive interconnect layers, comprising:a set of one or more first conductive plates having a first defined finger structure laid out in an interior core position and located in one or more middle conductive interconnect layers to form a top capacitor plate;
a set of second conductive plates located in the one or more middle conductive interconnect layers, a bottom conductive interconnect layer, and a top conductive interconnect layer and connected together by a first set of conductive via structures to form a bottom capacitor plate, each second conductive plate having defined finger structures that are vertically aligned such that the defined finger structures of a second conductive plate formed in the one or more middle conductive interconnect layers are interleaved with the first defined finger structure of the top capacitor plate, such that that bottom capacitor plate vertically and horizontally sandwiches the top capacitor plate; and
a set of third conductive plates formed in the one or more middle conductive interconnect layers, the bottom conductive interconnect layer, and the top conductive interconnect layer to surround and shield the top capacitor plate and bottom capacitor plate on at least a plurality of lateral sides, where the set of third conductive plates are connected together and to a reference voltage by a second set of conductive via structures, thereby shielding the top capacitor plate from parasitic capacitance.

US Pat. No. 10,892,098

MULTILAYER CERAMIC ELECTRONIC COMPONENT

TDK CORPORATION, Tokyo (...

1. A multilayer ceramic electronic component comprising an element body in which dielectric layers and internal electrode layers having different polarities are laminated alternately, whereinthe dielectric layers contain a main component of a perovskite-type compound represented by (Ba1-a-bSraCab)m(Ti1-c-dZrcHfd)O3,
0.94 the dielectric layers contain a first sub-component of 2.5 mol or more to the main component of 100 mol, a second sub-component of 0.2 to 1 mol to the main component of 100 mol, and a third sub-component of 0.1 to 2 mol to the main component of 100 mol,
the first sub-component contains a boron oxide and optionally a lithium oxide, and
the second sub-component contains an oxide of Mn and/or Cr,
the third sub-component is an oxide of a rare earth element R,
the R is at least one of Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu,
the internal electrode layers contain a main component of copper and/or silver,
the boron oxide of the first sub-component is present in an amount of 2.5 mol or more to the main component of 100 mol, and
and a content ratio Bs/Bc is 0.5 to 0.95, in which an amount of boron contained in the dielectric layers located near the outer surface of the element body is Bs and an amount of boron contained in the dielectric layers located at a central portion of the element body is Bc.

US Pat. No. 10,892,097

DIELECTRIC CERAMIC COMPOSITION, METHOD FOR THE PRODUCTION AND USE THEREOF

TDK ELECTRONICS AG, Muni...

1. A ceramic composition comprising:a main component with a quantity ratio Mg(1+x)(1?y)O3+xA(1+x)ySi(1?z)Dz; and
a remainder comprising contaminants,
wherein A is selected from the group consisting of Zn, Ni, Co, Mn and a mixture of Zn, Ni, Co, Mn,
wherein D is selected from the group consisting of Ti, Sn, Zr and a mixture of Ti, Sn, Zr,
wherein 0.01?x?0.30,
wherein 0.00?y?0.20, and
wherein 0.00?z?1.00.

US Pat. No. 10,892,096

MULTILAYER CERAMIC ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic electronic component comprising:a ceramic body including dielectric layers and a plurality of first and second internal electrodes disposed on the dielectric layers and having a first surface and a second surface opposing each other in a first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposing each other in a second direction, and a fifth surface and a sixth surface connected to the first to fourth surfaces and opposing each other in a third direction; and
first and second external electrodes disposed on external surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively,
wherein the dielectric layer includes a dielectric ceramic composition including a base material main component represented by z(Ba(1-x)Cax)TiO3-(1-z)BaTi2O5 including a first main component represented by (Ba(1-x)Cax)TiO3 and a second main component represented by BaTi2O5, 0.7?z?0.8 and 0

US Pat. No. 10,892,095

SOLID ELECTROLYTIC CAPACITOR ASSEMBLY

AVX Corporation, Fountai...

1. A capacitor assembly comprising a capacitor element, the capacitor element comprising;a porous anode body that contains a valve metal compound;
a dielectric that overlies the anode body and includes an oxide of the valve metal compound;
a solid electrolyte that overlies the dielectric, wherein the solid electrolyte includes a conductive polymer and a hydroxy-functional polymer; and
an organofunctional silane compound that is bonded to the oxide of the dielectric and is capable of bonding to the hydroxy-functional polymer, wherein the organofunctional silane compound has the following general formula (I):
whereinR1, R2, and R3 are independently alkyl, alkenyl, aryl, heteroaryl, cycloalkyl, heterocyclyl, halo, haloalkyl, hydroxyalkyl, or a combination thereof; and
X is a functional group that is capable of bonding to a hydroxyl group or is capable of being converted into a functional group that is capable of bonding to a hydroxyl group; and
Z is an organic group that links the functional group X to the silicon atom.

US Pat. No. 10,892,094

BORON NITRIDE AND METHOD OF PRODUCING BORON NITRIDE

Board of Trustees of Nort...

1. h-BN nanosheets,wherein the h-BN nanosheets contain less than 0.1 atomic percent metal impurities and have a full width at half maximum (FWHM) of the X-ray powder diffraction pattern for a d002 peak of at most 0.50 degrees,
the h-BN nanosheets have an aspect ratio of at least 10:1, and
the h-BN nanosheets are not nanofibers.

US Pat. No. 10,892,093

MULTILAYER CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a body including dielectric layers and internal electrodes alternately disposed therein; and
external electrodes disposed on the body and connected to the internal electrodes, respectively,
wherein the internal electrodes include a first internal electrode and a second internal electrode, a thickness of the second internal electrode being less than a thickness of the first internal electrode, and
an area fraction of ceramics included in the first internal electrode with respect to the first internal electrode is greater than that of ceramics included in the second internal electrode with respect to the second internal electrode.

US Pat. No. 10,892,092

CONDUCTIVE POWDER FOR INNER ELECTRODE AND CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A conductive powder for an internal electrode comprising:a metal particle; and
a graphene layer or an oxidized graphene layer disposed on at least a portion of a surface of the metal particle.

US Pat. No. 10,892,091

PERMANENT MAGNET, MOTOR, AND GENERATOR

KABUSHIKI KAISHA TOSHIBA,...

1. A method of manufacturing a permanent magnet, comprising:press-forming alloy powder in a magnetic field to fabricate a compression molded body, wherein a total weight of the compression molded body is not less than 200 g nor more than 2000 g;
sintering the compression molded body to fabricate a sintered body;
performing a solution heat treatment on the sintered body; and
performing an aging heat treatment on sintered body after the solution heat treatment,
wherein the solution heat treatment includes:
performing a heat treatment on a treatment object having the sintered body at a temperature TST of 1100 to 1200° C. inside a heating chamber having a heater;
transferring a cooling member into the heating chamber after the heat treatment and placing the cooling member between the heater and the treatment object, the cooling member including a first layer and a second layer on the first layer, the first layer having a first thermal emissivity of 0.5 or more, the second layer having a second thermal emissivity lower of less than 0.5, the first layer containing carbon, a metal carbide, a metal oxide, or a refractory brick, the second layer containing copper, molybdenum, tungsten, titanium, or stainless steel, and the first layer being faced with the treatment object; and
transferring the treatment object together with the cooling member to the outside of the heating chamber, and cooling the treatment object until a temperature of the treatment object becomes a temperature lower than a temperature TST?200° C.,
wherein in cooling the treatment object, a cooling rate until the temperature of the treatment object becomes the temperature TST?200° C. is 5° C./s or more, wherein the cooling rate is achieved by a combination of absorbing, by the first layer, heat emitted by the treatment object and reflecting, by the second layer, heat emitted from the heater, and
wherein the permanent magnet is expressed by a composition formula:
RpFeqMrCutCo100-p-q-r-t,
where R represents at least one element selected from the group consisting of rare earth elements, M represents at least one element selected from the group consisting of Zr, Ti, and Hf, p is a number satisfying 10.5?p?12.5 atomic percent, q is a number satisfying 27?q?40 atomic percent, r is a number satisfying 0.88?r?4.5 atomic percent, and t is a number satisfying 4.5?t?10.7 atomic percent.

US Pat. No. 10,892,090

MAGNET CORE FOR LOW-FREQUENCY APPLICATIONS AND METHOD FOR PRODUCING A MAGNET CORE FOR LOW-FREQUENCY APPLICATIONS

1. A method for producing a magnet core for low-frequency applications from a soft-magnetic, nanocrystalline strip, the strip essentially having the alloy composition FeRestCoaCubNbcSidBeCf, wherein a, b, c, d, e and f are stated in atomic percent and 0?a?1; 0.7?b?1.4; 2.5?c?3.5; 14.5?d?16.5; 5.5?e?8 and 0?f?1, and cobalt may wholly or partially be replaced by nickel; wherein the strip is provided with a coating, the coating provided on the strip comprising a solution, the solution including a methylate, an ethylate, or a butylate compound in the corresponding alcohol or ether, or the solution including a tri- or tetra-isopropyl alkoxide, or the solution including an acetyl-acetone-chelate complex, the coating provided on the strip further includes a metal, the metal includes an element selected from the group of Mg, Zr, Be, Al, Ti, V, Nb, Ta, Ce, Nd, Gd, elements of Group 2 and Group 3 of the Period Table of the Elements, and elements of the group of rare earth metals of the Period Table of the Elements, which coating forms a seal on the strip during a subsequent heat treatment at a temperature greater than 540° C. for the nanocrystallisation of the strip and thus hinders formation of surface crystallites and a strain-inducing SiO2 surface layer on the strip, wherein the heat treatment is carried out magnetic field-free on non-stacked magnet cores in a continuous annealing process, and wherein, in the heat treatment for the nanocrystallisation of the strip, a saturation magnetostriction ?s of |?s|<2 ppm is achieved, and wherein the strip also has a remanence ratio Br/Bs>70%, a starting permeability ?1 of ?1>100 000, and a maximum permeability ?max of ?max>400 000 after exposure to the temperature of greater than 540° C. and when the core operates at a frequency of 50 Hz.

US Pat. No. 10,892,089

METHOD FOR PRODUCING MAGNETIC COMPONENT USING AMORPHOUS OR NANOCRYSTALLINE SOFT MAGNETIC MATERIAL

TOYOTA JIDOSHA KABUSHIKI ...

1. A method for producing a magnetic component comprising an amorphous soft magnetic material or a nanocrystalline soft magnetic material comprising:preparing a first stacked body comprising a plurality of plate-shaped amorphous soft magnetic materials or nanocrystalline soft magnetic materials;
heating at least a portion of shearing in the first stacked body to a temperature equal to or higher than the crystallization temperature of the soft magnetic materials, wherein the heating includes fusion-cutting the first stacked body at a position outside the portion of shearing so as to remove a fusion-cut stacked body from the first stacked body; and
shearing the fusion-cut stacked body at the portion of shearing after the heating.

US Pat. No. 10,892,088

STATIONARY DEVICE FOR CONTACTLESS ELECTRICAL ENERGY TRANSMISSION

Texas Institute of Scienc...

1. A contactless charging apparatus comprising:a primary electromagnetic structure having an upper end and an interior end, the primary electromagnetic structure including a primary yoke at the upper end, the primary yoke having a plurality of primary wedges extending therefrom at the interior end of the primary electromagnetic structure, the primary yoke magnetically connecting the plurality of primary wedges;
the plurality of primary wedges defining an inner space and a plurality of primary slots interposed therebetween, the plurality of primary slots extending radially through the primary yoke and intersecting the interior of the primary electromagnetic structure;
a secondary electromagnetic structure having a lower end and an interior end, the secondary electromagnetic structure including a secondary yoke at the lower end, the secondary yoke having a plurality of secondary wedges extending therefrom at the interior end of the secondary electromagnetic structure, the secondary yoke magnetically connecting the plurality of secondary wedges;
the plurality of secondary wedges defining an inner space and a plurality of secondary slots interposed therebetween, the plurality of secondary slots extending radially through the secondary yoke and intersecting the interior end of the secondary electromagnetic structure;
each of the primary yoke and the secondary yoke including a soft-magnetic material;
each of the plurality of primary wedges and the plurality of secondary wedges including the soft-magnetic material; and
the primary electromagnetic structure and the secondary electromagnetic structure being disposed in an opposing relationship with the plurality of primary wedges facing the plurality of secondary wedges with a non-magnetic gap therebetween.