US Pat. No. 10,560,171

METHOD FOR REPORTING CHANNEL STATE INFORMATION IN WIRELESS COMMUNICATION SYSTEM SUPPORTING UNLICENSED BAND, AND APPARATUS FOR SUPPORTING SAME

LG ELECTRONICS INC., Seo...

1. A method for operating a User Equipment (UE) in a wireless communication system, the wireless communication system including a base station (BS) and supporting communications in an unlicensed band, the method performed by the UE and comprising:receiving, from the BS, an uplink (UL) grant for scheduling an uplink transmission in the unlicensed band,
wherein the UL grant includes downlink control information (DCI), the DCI including information for scheduling a transmission of a Physical Uplink Shared Channel (PUSCH) that includes aperiodic channel state information (CSI);
based on the UL grant, transmitting the PUSCH to the BS,
wherein the PUSCH only includes the aperiodic CSI, and is transmitted in a single subframe, based on:
a value of a Modulation and Coding Scheme (MCS) field included in the DCI,
a CSI request bit included in the DCI, and
a number of subframes to be used for the PUSCH being set to 1,
wherein the number of scheduled subframes being set to 1 is included in the DCI when the DCI corresponds to a first specific DCI format, or the number of scheduled subframes being set to 1 is preassigned when the DCI corresponds to a second specific DCI format,
wherein the first specific DCI format is DCI format 0B or 4B,
wherein the second specific DCI format is DCI format 0A or 4A, and
wherein the MCS field value is 29.

US Pat. No. 10,560,170

METHOD FOR CHANNEL INFORMATION FEEDBACK IN MULTI-ANTENNA SYSTEM, AND TERMINAL

ZTE CORPORATION, Guangdo...

1. A method for channel information feedback in a multi-antenna system, comprising:receiving, by a terminal, channel state information-reference signals (CSI-RSs) of M ports transmitted by a base station, and obtaining M-dimensional downlink channel information by estimating according to the CSI-RSs;
obtaining, by the terminal, according to the M-dimensional downlink channel information and a transformation function Fk, a kth type of channel information with Nk dimensions, wherein k is greater than or equal to 1 and is less than or equal to K, Nk is an integer greater than or equal to 1, M is an integer greater than or equal to 1, M?Nk, and K?1;
performing, by the terminal, channel information quantization on the kth type of channel information respectively by using a preset Nk-dimensional codebook, to determine a corresponding precoding matrix and precoding matrix indicator information (PMIk); and
selecting, by the terminal, s types of channel information from K types of channel information, and feeding index numbers of the selected channel information and the corresponding PMIs back to the base station, wherein s is an integer greater than or equal to 1.

US Pat. No. 10,560,169

CSI ACQUISITION WITH CHANNEL RECIPROCITY IN MOBILE COMMUNICATIONS

MEDIATEK INC., Hsinchu (...

1. A method, comprising:dividing, by a processor of a user equipment (UE), a plurality of antenna ports at the UE into a first group and a second group;
transmitting, by the processor, to a base station a sounding reference signal (SRS) via the first group of antenna ports through a first channel of a communication link between the UE and the base station;
receiving, by the processor, from the base station a channel state information reference signal (CSI-RS) via the first and second groups of antenna ports through the first channel and a second channel of the communication link;
determining, by the processor, an estimated channel response based on the receiving of the CSI-RS;
determining, by the processor, a matrix such that a product of the matrix and a first channel response of the first channel approximates a second channel response of the second channel; and
transmitting, by the processor, to the base station a CSI feedback indicating the matrix, a transmission rank, and a channel quality indicator (CQI),
wherein the dividing of the plurality of antenna ports at the UE into the first group and the second group comprises dividing the plurality of antenna ports at the UE into the first group comprising n1 antenna ports, 1?n1?N1, and the second group comprising n2 antenna ports, N1+1?n2?N1+N2, with n1, n2, N1, N2, being positive integers and with assumptions that:
the first group is used for both transmitting and receiving, and
the second group used for receiving but not transmitting.

US Pat. No. 10,560,166

TUNABLE PASSIVE TIME-DELAY STRUCTURE FOR ADJUSTING A DIRECTION OF A BEAMFORMING PATTERN

Facebook, Inc., Menlo Pa...

1. A node, comprising:a plurality of passive time-delay structures, wherein each of the passive time-delay structure is operative to generate a plurality of delayed signals, wherein each of the plurality of delayed signals is a delayed version of at least one of a plurality of communication signals connected to the passive time-delay structure, wherein at least one of the plurality of passive time-delay structures includes a tunable element, the tunable element operative to introduce a variable delay to the at least one of the plurality of communication signals propagating through the at least one of the plurality of passive time-delay structures;
an antenna array, wherein the antenna array generates a beamforming pattern corresponding with a selected one of the plurality of the passive time-delay structures; and
a phase delay adjust control operative to adjust the tunable element of the at least one of the plurality of passive time-delay structures, wherein a direction of the one or more beams of the beamforming pattern changes depending upon tuning of the tunable element.

US Pat. No. 10,560,165

COMMUNICATION SYSTEM, METHOD OF CONTROLLING COMMUNICATION SYSTEM, BASE STATION APPARATUS, AND WIRELESS TERMINAL APPARATUS

PANASONIC INTELLECTUAL PR...

1. A communication system, comprising:one or more wireless terminal apparatuses; and
a base station apparatus that performs a wireless communication with the one or more wireless terminal apparatuses, wherein in a transmission beamforming training interval in which beamforming training of a transmission beam is performed,
the base station apparatus transmits to the one or more wireless terminal apparatuses a protocol control frame including a designation field indicating a reception quality measuring method and transmits a plurality of first training frames while sequentially switching a plurality of first transmission beam patterns,
the one or more wireless terminal apparatuses perform an operation including,
receiving the protocol control frame,
receiving the plurality of first training frames using a particular beam pattern,
measuring first reception quality of the received plurality of first training frames according to the reception quality measuring method indicated in the received protocol control frame, and
generating a second feedback frame including the measured first reception quality and transmitting the generated second feedback frame to the base station apparatus, and
the base station apparatus performs an operation including,
receiving the second feedback frame, and
selecting one beam pattern from the plurality of first transmission beam patterns based on the first reception quality included in the second feedback frame.

US Pat. No. 10,560,164

GROUP ADDRESSING FOR BEAMFORMING TRAINING

Marvell International Ltd...

1. A method for performing beamforming training in a wireless communication network, the method comprising:generating, at a first communication device, a beamforming training initiator packet for transmission in the wireless communication network, the beamforming training initiator packet including i) information indicating a start of a beamforming training session, and ii) respective individual identifiers of multiple second communication devices, among a plurality of second communication devices, that alone specify which of the second communication devices among the plurality of second communication devices are to process beamforming training packets transmitted by the first communication device during the beamforming training session;
transmitting, by the first communication device, the beamforming training initiator packet that includes the respective individual identifiers of multiple second communication devices that alone specify which of the second communication devices are to process beamforming training packets transmitted by the first communication device during the beamforming training session; and
after transmitting the beamforming training initiator packet, transmitting, by the first communication device, a plurality of beamforming training packets during the beamforming training session.

US Pat. No. 10,560,163

BEAMFORMING CONFIGURATION WITH ADAPTIVE PORT-TO-ANTENNA MAPPING FOR A MULTI-ANTENNA SYSTEM

Telefonaktiebolaget LM Er...

1. A method for determining a beamforming configuration for a multi-antenna system having at least two antennas and having a port-to-antenna mapping between antenna ports and antennas, wherein the method comprises:obtaining first feedback information originating from a wireless device relating to a multi-antenna transmission based on a first beamforming configuration enabling beamforming according to a first beam form, wherein the first beamforming configuration includes a first port-to-antenna mapping;
obtaining second feedback information originating from the wireless device relating to a multi-antenna transmission based on a second, different beamforming configuration enabling beamforming according to a second, different beam form, wherein the second beamforming configuration includes a second, different port-to-antenna mapping; and
determining, based on the first feedback information and the second feedback information, a third beamforming configuration for the multi-antenna system including a third port-to-antenna mapping to enable beamforming according to a third beam form, wherein the first feedback information and the second feedback information belong to different feedback processes,
wherein the method further comprises transferring information about the determined third beamforming configuration to a network node for enabling multi-antenna transmission of at least one reference signal based on the determined third beamforming configuration.

US Pat. No. 10,560,162

TRANSMIT DIVERSITY METHOD, DEVICE, AND SYSTEM

Huawei Technologies Co., ...

1. A transmit diversity method, comprising:receiving, by a first network device, rank index information and precoding matrix index information that are sent by a second network device;
determining, by the first network device, a diversity coding scheme based on the rank index information, wherein determining, by the first network device, the diversity coding scheme based on the rank index information comprises:
when the rank index information is a first preset rank 2, determining, by the first network device, the diversity coding scheme as a first diversity coding scheme, wherein the first diversity coding scheme is:
X2k,1=d(2k) X2k,2=d(2k+1)
X2k+1,1=?(d(2k+1))* X2k+1,2=(d(2k))*
wherein X2k,1 represents a data symbol to which first-layer data is mapped on a 2kth subcarrier, and corresponds to a data symbol d(2k) of the first data; X2k+1,1 represents a data symbol to which the first-layer data is mapped on a 2k+1th subcarrier, and corresponds to a data symbol ?(d(2k+1))* of the first data; X2k,2 represents a data symbol to which second-layer data is mapped on the 2kth subcarrier, and corresponds to a data symbol d(2k+1) of the first data; X2k+1,2 represents a data symbol to which the second-layer data is mapped on the 2k+1th subcarrier, and corresponds to a data symbol (d(2k))* of the first of the first data; and data symbols of the second data are represented as X; or
X2k,1=d(2k) X2k+1,1=d(2k+1)
X2k,2=?(d(2k+1))* X2k+1,2=(d(2k))*
wherein X2k,1 represents a data symbol to which first-layer data is mapped on a 2kth subcarrier, and corresponds to a data symbol d(2k) of the first data; X2k+1,1 represents a data symbol to which the first-layer data is mapped on a 2k+1th subcarrier, and corresponds to a data symbol d(2k+1) of the first data; X2k,2 represents a data symbol to which second-layer data is mapped on the 2kth subcarrier, and corresponds to a data symbol ?(d(2k+1)* of the first data; X2k+1,2 represents a data symbol to which the second-layer data is mapped on the 2k +1 subcarrier, and corresponds to a data symbol (d(2k))* of the first data; and data symbols of the second data are represented as X, and
when the rank index information is a second preset rank 4, determining, by the first network device, the diversity coding scheme as a second diversity coding scheme;
determining, by the first network device, a precoding matrix based on the precoding matrix index information; and
performing, by the first network device, transmission processing on to-be-transmitted data based on the diversity coding scheme and the precoding matrix, wherein performing, by the first network device, the transmission processing on the to-be-transmitted data based on the diversity coding scheme and the precoding matrix comprises:
performing, by the first network device, coding, scrambling, and modulation processing on the to-be-transmitted data, to obtain the first data,
processing, by the first network device, the first data based on the diversity coding scheme, to obtain second data,
performing, by the first network device, precoding processing on the second data based on the precoding matrix, to obtain third data,
performing, by the first network device, resource block mapping and orthogonal frequency division multiplexing (OFDM) signal generation processing on the third data, and
sending, by the first network device, the third data.

US Pat. No. 10,560,159

PILOT SCHEME FOR A MIMO COMMUNICATION SYSTEM

Apple Inc., Cupertino, C...

1. A method of transmitting demodulation pilot information, the method comprising:a base station performing,
transmitting an assignment of a plurality of subcarriers in one or more blocks of subcarriers for a single carrier frequency division multiple access (SC-FDM) signal, wherein the assignment of the plurality of subcarriers is:
every other subcarrier of the one or more blocks of subcarriers on one or more pilot symbols in a set of pilot and traffic symbols; and
every subcarrier of the one or more blocks of subcarriers on a plurality of traffic symbols in the set of pilot and traffic symbols;
wherein each block of the one or more blocks of subcarriers comprises more than one subcarrier;
receiving, from a first mobile terminal, demodulation pilot information on the one or more pilot symbols and traffic information on the plurality of traffic symbols, wherein the demodulation pilot information is mapped to every other subcarrier of the one or more blocks of subcarriers on the one or more pilot symbols in the set of pilot and traffic symbols, wherein the traffic information is mapped onto every subcarrier of the one or more blocks of subcarriers on the plurality of traffic symbols in the set of pilot and traffic symbols, wherein each of the plurality of traffic symbols of the SC-FDM signal undergoes discrete Fourier transform pre-processing of the traffic information prior to sub-carrier mapping, and wherein each of the at least one pilot symbols of the SC-FDM signal does not undergo discrete Fourier transform pre-processing prior to sub-carrier mapping; and
receiving, from a second mobile terminal, second demodulation pilot information on the one or more pilot symbols and second traffic information on the plurality of traffic symbols, wherein the second demodulation pilot information is mapped to subcarriers different from the assignment of the plurality of subcarriers for the first mobile terminal on the pilot symbols of the set of pilot and traffic symbols, and wherein the second traffic information is mapped to the assignment of the plurality of subcarriers for the first mobile terminal on the traffic symbols of the set of pilot and traffic symbols.

US Pat. No. 10,560,158

TRIGGERED UPLINK TRANSMISSIONS IN WIRELESS LOCAL AREA NETWORKS

NXP USA, Inc., Austin, T...

1. A method for communicating in a wireless communication network, the method comprising:determining, at a first communication device, respective time duration requirements for preparing uplink transmissions by multiple second communication devices as part of an uplink multi-user (MU) transmission;
generating, at the first communication device, a physical layer (PHY) data unit that includes a trigger frame, wherein the trigger frame is for triggering simultaneous uplink transmissions by multiple second communication devices as part of the uplink MU transmission, wherein the trigger frame includes a trigger information portion, and wherein the PHY data unit is generated such that a duration between transmission of an end of the trigger information portion and transmission of an end of the PHY data unit is sufficient to satisfy the respective time duration requirements of the multiple second communication devices;
transmitting, with the first communication device, the PHY data unit; and
receiving, at the first communication device, the simultaneous uplink transmissions, triggered by the trigger frame, from the multiple second communication devices.

US Pat. No. 10,560,157

WIRELESS COMMUNICATION SYSTEM

Canon Kabushiki Kaisha, ...

1. A wireless communication system comprising:a first communication unit comprising a first antenna and a second antenna;
a second communication unit comprising a third antenna and a fourth antenna;
a first communication control unit configured to control wireless data communication based on electromagnetic field coupling between the first antenna and the third antenna;
a second communication control unit configured to control wireless data communication based on electromagnetic field coupling between the second antenna and the fourth antenna; and
a movement control unit configured to move at least one of the first communication unit and the second communication unit relatively to the other while maintaining a positional relationship in which the first antenna faces the third antenna and the second antenna faces the fourth antenna.

US Pat. No. 10,560,156

METHOD AND DEVICE FOR MODULATING AN ACTIVE LOAD

VERIMATRIX, Meyreuil (FR...

1. A method comprising:producing, by an inductive antenna circuit, a first periodic signal that is based on an alternating external magnetic field;
producing, by an oscillator circuit, a second periodic signal that is based on the first periodic signal;
transmitting, in correspondence with a data-carrying modulation signal, a sequence of data bits of a data frame by sequentially and repetitively:
applying, with the oscillator circuit operating in a free oscillation mode, the second periodic signal to the inductive antenna circuit to transmit a portion of the data frame, the second periodic signal being applied to the inductive antenna circuit in response to the data-carrying modulation signal having a first logic value;
after transmitting the portion of the data frame, inhibiting application of the second periodic signal to the inductive antenna circuit, application of the second periodic signal to the inductive antenna circuit being inhibited in response to the data-carrying modulation signal having a second logic value, the second logic value being opposite the first logic value; and
during at least a portion of a period of time that application of the second periodic signal to the inductive antenna circuit is inhibited, placing the oscillator circuit in a synchronous oscillation mode, the placing the oscillator circuit in the synchronous oscillation mode resulting in the second periodic signal being synchronized to the first periodic signal.

US Pat. No. 10,560,153

GUIDED WAVE TRANSMISSION DEVICE WITH DIVERSITY AND METHODS FOR USE THEREWITH

1. A transmission device comprising:a first coupler oriented at an azimuthal angle to a transmission medium, wherein the first coupler is configured to form a first electromagnetic wave that is guided along an outer surface of the transmission medium via at least one guided-wave mode, wherein the first electromagnetic wave has an envelope that varies as a function of angular deviation from the azimuthal angle, wherein the function of angular deviation has a minimum at an angular deviation from the azimuthal angle, and wherein a second electromagnetic wave propagates along the outer surface of the transmission medium in a direction opposite to the first electromagnetic wave; and
a second coupler that receives the second electromagnetic wave from the transmission medium for transmission to a receiver, wherein the second coupler is oriented at the angular deviation from the azimuthal angle.

US Pat. No. 10,560,152

METHOD AND APPARATUS FOR CONFIGURING A COMMUNICATION INTERFACE

1. A method, comprising:generating, by a coupler, first electromagnetic waves; and
inducing, by the coupler, according to the first electromagnetic waves, second electromagnetic waves that propagate along a boundary formed between a plurality of insulating surfaces of an inner bundle of twisted pair cables, the second electromagnetic waves propagating along the boundary formed between the plurality of insulating surfaces of the inner bundle of twisted pair cables without requiring an electrical return path.

US Pat. No. 10,560,151

ACCESS POINT AND METHODS FOR COMMUNICATING WITH GUIDED ELECTROMAGNETIC WAVES

1. An access point comprising:a first communication interface that includes:
a first coupler configured to receive, via a first transmission medium, first guided electromagnetic waves from a first waveguide system of a distributed antenna system, wherein the first guided electromagnetic waves propagate along the first transmission medium without requiring an electrical return path; and
a receiver configured to receive first data from the first guided electromagnetic waves; and
a data switch configured to select first selected portions of the first data for transmission to at least one communication device in proximity to the access point;
wherein the first waveguide system is coupled to a medium voltage power line supported by a utility pole and wherein the first waveguide system sends and receives second guided electromagnetic waves along an outer surface of the medium voltage power line.

US Pat. No. 10,560,149

COMMUNICATING BETWEEN DEVICES IN A DOORBELL SYSTEM USING AC POWER WAVEFORMS

Amazon Technologies, Inc....

1. An audio/video (A/V) recording and communication device configured to be connected in series with a doorbell device in a doorbell circuit, the A/V recording and communication device comprising:a button configured to receive touch input to cause a signaling device to output a sound;
one or more processors;
a first signal relay configured to be disposed in series with the signaling device to perform current switching for controlling AC current that is provided by an AC power source, the first signal relay being selectively configurable to close a first connection such that the AC current is provided by the AC power source and to open the first connection such that the AC current is not provided by the AC power source;
a second signal relay disposed in parallel with the A/V recording and communication device to perform current switching for controlling the AC current that is drawn by the A/V recording and communication device, the second signal relay being selectively configurable to open a second connection such that the AC current is drawn by the A/V recording and communication device through the first signal relay and to close the second connection such that that AC current passes through the first signal relay and the second signal relay to bypass the A/V recording and communication device; and
memory having stored therein instructions that, when executed by the one or more processors, cause the A/V recording and communication device to:
cause the first signal relay to close the first connection;
cause the second signal relay to open the second connection such that the A/V recording and communication device draws a first amount of AC current through the first signal relay;
detect a touch input of the button;
based at least in part on the detecting the touch input of the button, cause the first signal relay to open the first connection such that the doorbell circuit is open, thereby preventing the first amount of AC current from being drawn by the A/V recording and communication device for a first period of time,
wherein the preventing the first amount of AC current from being drawn by the A/V recording and communication device indicates to the signaling device to output the sound;
subsequent to the first period of time:
cause the first signal relay to close the first connection such that the AC current is provided to the doorbell circuit by the AC power source; and
cause the second signal relay to close the second connection such that a second amount of AC current that is drawn by the signaling device to output the sound bypasses the A/V recording and communication device by passing through the first signal relay and the second signal relay, wherein the first signal relay and the second signal relay are closed for a second period of time;
subsequent to the second period of time:
cause the first signal relay to open the first connection for a third period of time; and
cause the second signal relay to open the second connection for the third period of time such that the doorbell circuit is open, thereby preventing the signaling device from drawing the second amount of AC current to output the sound; and
subsequent to the third period of time, cause the first signal relay to close the first connection such that the A/V recording and communication device draws a third amount of AC current through the first signal relay.

US Pat. No. 10,560,148

TRANSMISSION MEDIUM AND METHODS FOR USE THEREWITH

1. A transmission medium comprising:a core; and
an outer conductive layer forming an uninsulated outer surface of the transmission medium, the outer conductive layer configured to impede accumulation of water to support propagation of first electromagnetic waves guided by the uninsulated outer surface, wherein the outer conductive layer comprises a first plurality of conductors, and wherein the first plurality of conductors individually have a sector cross section concentrically truncated to conform with an inner surface of the transmission medium.

US Pat. No. 10,560,146

METHOD AND SYSTEM FOR CALIBRATING MULTI-WIRE SKEW

KANDOU LABS, S.A., Lausa...

1. A method comprising:receiving, over a plurality of consecutive signaling intervals, a plurality of codewords, each codeword received as a plurality of symbols via wires of a multi-wire bus, the plurality of symbols received at a plurality of multi-input comparators (MICs), wherein each symbol is received by at least two MICs;
generating, for each codeword, a corresponding set of MIC outputs by forming linear combinations of the received symbols using the plurality of MICs;
generating a plurality of skew measurement signals over the plurality of consecutive signaling intervals, each skew measurement signal based on an early-late measurement made on at least one MIC output of the corresponding set of MIC outputs undergoing a transition between two consecutive signaling intervals responsive to two or more wires of the multi-wire bus undergoing a signal transition; and
updating, for each skew measurement signal, wire-specific skew values for the two or more wires of the multi-wire bus undergoing the signal transition.

US Pat. No. 10,560,145

METHOD AND APPARATUS FOR LAUNCHING A WAVE MODE THAT MITIGATES INTERFERENCE

10. A waveguide system, comprising:a launcher; and
a processor coupled to the launcher, wherein the processor facilitates performance of operations, comprising:
determining, by the processor, a degradation of an electromagnetic wave propagating along a transmission medium;
responsive to the determining, combining a first instance of a first electromagnetic wave with a second instance of a second electromagnetic wave to generate a combined electromagnetic wave having a hybrid wave mode adapted to mitigate the degradation; and
guiding, by the launcher, the combined electromagnetic wave for propagation along the transmission medium without requiring an electrical return path.

US Pat. No. 10,560,144

TRANSMISSION MEDIUM AND COMMUNICATION INTERFACES AND METHODS FOR USE THEREWITH

1. A method, comprising:generating, by a waveguide system comprising a processor, first electromagnetic waves; and
inducing, by the waveguide system, according to the first electromagnetic waves, second electromagnetic waves that propagate along a hollow conduit formed by an interior portion of a plurality of twisted pair cables, wherein the interior portion is formed by a plurality of inner surfaces of the plurality of twisted pair cables, wherein the plurality of twisted pair cables result in a bundle of cables, and wherein the second electromagnetic waves propagate along the hollow conduit formed by the interior portion of the plurality of twisted pair cables without requiring an electrical return path.

US Pat. No. 10,560,143

DETECTION OF INTERMODULATION ISSUES AND TRANSMISSION SCHEME CONFIGURATION TO REMEDY INTERMODULATION ISSUES

Apple Inc., Cupertino, C...

1. An apparatus, comprising a processing element configured to cause a wireless device to:determine a potential intermodulation issue for a dual connectivity configuration of Long Term Evolution (LTE) and New Radio (NR) at the wireless device for one or more band combinations;
provide, to a base station, based on said determining the potential intermodulation issue, a capability of whether simultaneous transmission on dual uplink carriers is supported for the dual connectivity configuration of LTE and NR for one or more band combinations;
provide, to the base station, an indication that the wireless device supports reporting intermodulation issues associated with dual connectivity on LTE and NR;
receive an indication that the wireless device is allowed to report the intermodulation issues from the base station;
determine that an intermodulation issue associated with dual connectivity of LTE and NR is occurring at the wireless device;
provide an indication of the intermodulation issue to the base station; and
receive first configuration information from the base station, wherein the first configuration information configures the wireless device for single uplink carrier communication, wherein the configuration information is received based at least in part on one or more of the capability and the indication of the intermodulation issue.

US Pat. No. 10,560,140

MIMO WIFI TRANSCEIVER WITH ROLLING GAIN OFFSET PRE-DISTORTION CALIBRATION

QUANTENNA COMMUNICATIONS,...

1. A wireless multiple-input multiple-output (MIMO) transceiver apparatus for wireless communication on a wireless local area network (WLAN), and the wireless MIMO transceiver apparatus comprising:a plurality of antennas;
a plurality of components coupled to one another to form transmit and receive chains coupled to the plurality of antenna for MIMO wireless communications on the WLAN, the plurality of components forming the transmit chains including:
pre-distorter circuits each coupled to a corresponding one of the transmit chains and each accepting input of pre-distortion parameters for pre-distorting an associated signal of a MIMO communication link prior to amplification thereof; and
power amplifiers (PA)s each having an input and an output, and each coupled at the input to a corresponding one of the transmit chains and at the output to a corresponding one of the plurality of antennas, to amplify an associated signal of the MIMO communication link for wireless transmission;
a signal combiner coupled to the outputs of each of the PAs to combine the amplified signals therefrom into a combined output signal; and
a predistortion calibration circuit to calibrate pre-distortion parameters for each of the pre-distorter circuits from the combined output signal, the predistortion calibration circuit having an input simultaneously coupled through the signal combiner to the outputs of all of the PAs, and including:
a chain isolator circuit coupled to the signal combiner, to isolate a selected one of the amplified signals from an associated PA within the combined output signal from the signal combiner; and
an inverter circuit coupled to the chain isolator circuit to determine a mathematical inverse of the associated PA's non-linearity where said non-linearity corresponds to a difference between the selected one of the amplified signals and the un-amplified signal on the corresponding one of the transmit chains; and to provide pre-distortion parameters corresponding to said inverse to the corresponding one of the pre-distorter circuits to compensate for any non-linearity in the amplification provided by the corresponding PA.

US Pat. No. 10,560,139

DYNAMIC CONTROL OF SINGLE SWITCHED UPLINK VERSUS MULTI UPLINK

Skyworks Solutions, Inc.,...

1. A mobile device comprising:a plurality of antennas including a first antenna and a second antenna;
a front end system including a plurality of transmit chains including a first transmit chain electrically connected to the first antenna and a second transmit chain electrically connected to the second antenna; and
a transceiver configured to transmit a first type of radio frequency signal and a second type of radio frequency signal through the front end system, the transceiver operable in a first mode in which transmissions of the first type of radio frequency signal and the second type of radio frequency signal are staggered over time, and a second mode in which transmissions of the first type of radio frequency signal and the second type of radio frequency signal at least partially overlap in time, the transceiver including a transmit control circuit configured to operate the transceiver in the first mode or the second mode based on comparing a transmit parameter to a threshold.

US Pat. No. 10,560,137

MULTIWAY SWITCH, RADIO FREQUENCY SYSTEM, AND WIRELESS COMMUNICATION DEVICE

GUANGDONG OPPO MOBILE TEL...

1. A multiway switch, comprising:five throw (T) ports and four pole (P) ports; the five T ports comprising one first T port and four second T ports, the first T port being coupled with all the four P ports, and each of the four second T ports being coupled with only one of the four P ports; and
the multiway switch being configured to be coupled with a radio frequency circuit and an antenna system of an electronic device operable in a dual-frequency single-transmit mode, to enable a preset function of the electronic device, the antenna system comprising four antennas corresponding to the four P ports, and the preset function being a function of transmitting a sounding reference signal (SRS) through the four antennas in turn.

US Pat. No. 10,560,136

ANTENNA CONTINUITY

Corning Optical Communica...

1. An access unit configured to provide radio frequency (RF) communications to a coverage area, comprising:an antenna component comprising a first resistive element and configured to communicate RF signals into a coverage area;
a base unit, comprising:
a base unit circuit board formed on a first printed circuit board;
a cavity filter block formed on a second printed circuit board and operatively connected to the base unit circuit board, comprising:
processing circuitry, the processing circuitry including at least one filter;
an RF blocking component electrically connected to the first resistive element, and
a second resistive element provided on the second printed circuit board and electrically connected in series with the RF blocking component;
a third resistive element disposed on the first printed circuit board and electrically connected with the second resistive element, wherein the first resistive element, the second resistive element, and the third resistive element collectively form a voltage divider coupled across the antenna component, the second printed circuit board, and the first printed circuit board; and
a controller; and
a communications medium electrically connecting the antenna component to the base unit, wherein
the controller is configured to determine a connected state of the antenna component to the base unit based at least on a voltage difference between the second resistive element and the third resistive element.

US Pat. No. 10,560,135

HEALTH, WELLNESS AND ACTIVITY MONITOR

Life365, Inc., Scottsdal...

1. A device for being attached to a user or the user's clothing, the device comprising:(a) a band having a length, a width, and a thickness, the band including first replaceable software application configured to provide a first functionality, electronic circuitry configured to wirelessly and automatically replace, based on a physical location of the band, the first replaceable software application with a second replaceable software application configured to provide a second functionality that is different from the first functionality, a first power source, and a display; and
(b) the band, electronic circuitry, and display being flexible so as to be functional when manipulated into a circle having a diameter of 4? or more, 5? or more, 6? or more, 7? or more, 8? or more, 9? or more, or 10? or more.

US Pat. No. 10,560,134

MULTIBAND AGGREGATION RECEIVER ARCHITECTURE

HUAWEI TECHNOLOGIES CO., ...

1. A system for multi-band communication, the system comprising:at least one receiver branch, each receiver branch comprising:
a band-isolation stage comprising a plurality of sections, each section comprising:
a band-isolation stage mixer configured to receive a band-isolation stage input signal and down-convert the band-isolation stage input signal to a band-isolation stage frequency value; and
a filter bank comprising a plurality of band pass filters; and
a switch configured to:
select one of the plurality of band pass filters based on a bandwidth associated with a frequency band of interest in the down converted signal, at least one of the bandwidth and the frequency band of interest being identified in received configuration instructions; and
route the down-converted signal through the selected band pass filter.

US Pat. No. 10,560,133

DEVICE FOR RADIO COMMUNICATION USING A PLURALITY OF ANTENNAS

Hitachi Kokusai Electric ...

1. A device comprising:a first amplitude and phase controller configured to:
control a first amplitude and phase of a first receiving signal being input by a first receiving antenna to obtain a first directivity for a desired signal and to output a first desired signal, and
control a first amplitude and phase of a second receiving signal being input by a second receiving antenna to obtain a second directivity for the desired signal and to output a second desired signal;
a second amplitude and phase controller configured to:
control a second amplitude and phase of the first receiving signal to obtain a first directivity for a first undesirable signal by identifying a first arrival direction of the desired signal as a first null point and to output a first null point signal, and
control a second amplitude and phase of the second receiving signal to obtain a second directivity for the first undesirable signal by identifying a second arrival direction of the desired signal as a second null point and to output a second null point signal;
a first receiving synthesizer configured to:
synthesize the first desired signal with the second desired signal, and
output a first receiving synthesized signal;
a second receiving synthesizer configured to:
synthesize the first null point signal with the second null point signal, and
output a second receiving synthesized signal; and
a desired signal generator configured to output a synthesized receiving signal synthesizing the first receiving synthesized signal with the second receiving synthesized signal.

US Pat. No. 10,560,132

RECONFIGURABLE TRANSMITTER AND RECEIVER, AND METHODS FOR RECONFIGURING

Huawei Technologies Co., ...

1. A reconfigurable transmitter, wherein the transmitter comprises:a system adaptive control circuit, configured to generate a control signal according to frequency band information of an input signal, wherein the control signal comprises configuration information required for reconfiguring the transmitter; wherein the configuration information required for reconfiguring the transmitter comprises at least one of: a system clock; a digital intermediate frequency processing rate; a digital-to-analog conversion sampling rate; and an analog-to-digital conversion sampling rate;
a system clock circuit, configured to generate a system clock according to the control signal generated by the system adaptive control circuit;
a preprocessing circuit, configured to preprocess a received baseband signal according to the system clock and the control signal, to generate a frequency band signal;
a digital intermediate frequency processing circuit, configured to process, according to the system clock and the control signal, the frequency band signal generated by the preprocessing circuit, to generate a digital intermediate frequency signal;
a digital-to-analog conversion circuit, configured to process, according to the system clock and the control signal, the digital intermediate frequency signal generated by the digital intermediate frequency processing circuit, to generate an analog signal;
an analog transmitting circuit, configured to transmit the analog signal generated by the digital-to-analog conversion circuit;
wherein the transmitter further comprises a feedback analog-to-digital conversion circuit, configured to process a fed-back analog signal according to the system clock and the control signal, to generate a digital intermediate frequency signal; and
wherein the digital intermediate frequency processing circuit comprises a digital predistortion coefficient training circuit, configured to: perform, according to the system clock and the control signal, digital predistortion coefficient training on the digital intermediate frequency signal generated by the feedback analog-to-digital conversion circuit, to generate a digital predistortion coefficient.

US Pat. No. 10,560,131

FRONT-END MODULE AND COMMUNICATION DEVICE

MURATA MANUFACTURING CO.,...

1. A front-end module, comprising:a substrate; and
a receiving circuit that is provided in or on the substrate and in which carrier aggregation (CA) is executed; wherein
the receiving circuit includes:
a first path and a second path to which a high-frequency signal is inputted when the CA is executed;
a first filter disposed on the first path to filter the high-frequency signal;
a first low noise amplifier (LNA) disposed on the first path to amplify a signal filtered by the first filter;
a first inductor provided on the first path between the first filter and the first LNA to perform impedance matching for the first filter and the first LNA;
a second filter disposed on the second path to filter the high-frequency signal;
a second LNA disposed on the second path to amplify a signal filtered by the second filter; and
a second inductor provided on the second path between the second filter and the second LNA to perform impedance matching for the second filter and the second LNA; and
a coil axis of the first inductor and a coil axis of the second inductor are different from each other.

US Pat. No. 10,560,130

MULTIWAY SWITCH, RADIO FREQUENCY SYSTEM, AND WIRELESS COMMUNICATION DEVICE

GUANGDONG OPPO MOBILE TEL...

1. A multiway switch, comprising:six throw (T) ports and 2n pole (P) ports, the six T ports comprising two first T ports, and each of the two first T ports being coupled with all the 2n P ports; n being an integer and n?2;
the multiway switch being configured to be coupled with a radio frequency circuit and an antenna system of a wireless communication device operable in a dual-frequency single-transmit mode, to implement a preset function of the wireless communication device, the antenna system comprising 2n antennas corresponding to the 2n P ports, and the preset function being a function of transmitting a sounding reference signal (SRS) through the 2n antennas in turn;
wherein
the six T ports further comprise four second T ports;
each of the four second T ports is coupled with one of the 2n P ports, and T ports at the same frequency band in the four second T ports are coupled with different P ports;
each of the 2n P ports is configured to be coupled with a corresponding antenna of the 2n antennas;
the two first T ports at least support a transmission function; and
the four second T ports support only a reception function.

US Pat. No. 10,560,128

CARRIER AGGREGATED SIGNAL TRANSMISSION AND RECEPTION

SAMSUNG ELECTRONICS CO., ...

1. A radio-frequency integrated chip configured to receive a receiving signal composed of at least first and second carrier signals, the radio-frequency integrated chip comprising:a first carrier receiver configured to receive a first portion of the receiving signal and generate therefrom a first digital carrier signal corresponding to the first carrier signal, the first carrier receiver comprising a first analog mixer configured to translate frequencies of the first carrier signal in an analog domain and a first digital mixer configured to further translate frequencies of the first carrier signal in a digital domain and output the first digital carrier signal;
a second carrier receiver configured to receive a second portion of the receiving signal and generate therefrom a second digital carrier signal corresponding to the second carrier signal, the second carrier receiver comprising a second analog mixer configured to translate frequencies of the second carrier signal in the analog domain and a second digital mixer configured to further translate frequencies of the second carrier signal in the digital domain and output the second digital carrier signal; and
a phase-locked loop (PLL) configured to output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver,
wherein the first analog mixer translates the frequencies of the first carrier signal based on a second frequency signal generated by dividing the first frequency signal, and the second analog mixer translates the frequencies of the second carrier signal based on a third frequency signal generated by dividing the first frequency signal.

US Pat. No. 10,560,121

TRANSMISSION METHOD, TRANSMISSION APPARATUS, RECEPTION METHOD AND RECEPTION APPARATUS

PANASONIC CORPORATION, O...

1. A transmission method in a transmission apparatus using a light communication scheme and an encoding method of a low-density parity-check convolutional code (LDPC-CC) of a coding rate of ½ and a time-variant period of 3, the method comprising the steps of:obtaining a parity bit sequence from an information sequence including input data sequence and a bit sequence comprising a plurality of bits each bit having a value of 0, using first to third parity check polynomials that satisfy 0; and
transmitting, by a transmission circuitry in the transmission apparatus using the light communication scheme, a light communication signal generated by using the input data sequence and the obtained parity bit sequence, wherein:
the first parity check polynomial that satisfies 0 is represented by a first Equation of the following three Equations where
(a#1,1,1%3, a#1,1,2%3, a#1,1,3%3) is a combination of different values, and
(b#1,1%3, b#1,2%3, b#1,3%3) is a combination of different values;
the second parity check polynomial that satisfies 0 is represented by a second Equation of the following three Equations where
(a#2,1,1%3, a#2,1,2%3, a#2,1,3%3) is a combination of different values, and
(b#2,1%3, b#2,2%3, b#2,3%3) is a combination of different values;
the third parity check polynomial that satisfies 0 is represented by a third Equation of the following three Equations where
(a#3,1,1%3, a#3,1,2%3, a#3,1,3%3) is a combination of different values, and
(b#3,1%3, b#3,2%3, b#3,3%3) is a combination of different values;
the low-density parity-check convolutional code (LDPC-CC) is defined by periodical switching of the first to third parity check polynomials that satisfies 0 by the time-variant period of 3;

wherein:
Xj(D) is a polynomial representation of the information sequence Xj;
P(D) is a polynomial representation of the parity bit sequence;
a#k,1,1, a#k,1,2, and a#k,1,3 (where k=1, 2, 3) are integers (where a#k,1,1?a#k,1,2?a#k,1,3);
b#k,1, b#k,2, and b#k,3 (where k=1, 2, 3) are integers (where b#k,1?b#k,2?b#k,3); and
“c % d” indicates a remainder obtained by dividing c by d.

US Pat. No. 10,560,119

METHOD FOR PERFORMING ENCODING ON BASIS OF PARITY CHECK MATRIX OF LDPC CODE IN WIRELESS COMMUNICATION SYSTEM AND TERMINAL USING SAME

LG Electronics Inc., Seo...


generating encoded data, by the transmitting device, based on encoding the information with the determined parity check matrix; and
transmitting, by a transceiver of the transmitting device, the encoded data over the communication channel.

US Pat. No. 10,560,118

MULTIPLE LOW DENSITY PARITY CHECK (LDPC) BASE GRAPH DESIGN

Qualcomm Incorporated, S...

1. A method of low density parity check (LDPC) decoding, the method comprising:maintaining a plurality of LDPC base graphs, the plurality of LDPC base graphs comprising at least a first LDPC base graph associated with a first information block length range and a second LDPC base graph associated with a second information block length range, wherein the second information block length range comprises a subset of the first information block length range;
receiving a codeword over a wireless air interface from a transmitter;
selecting a select LDPC base graph from the plurality of LDPC base graphs for decoding the codeword based, at least in part, on an information block length associated with the codeword; and
decoding the codeword utilizing the select LDPC base graph to produce an information block comprising the information block length.

US Pat. No. 10,560,115

FLOATING POINT TO FIXED POINT CONVERSATION USING EXPONENT OFFSET

Imagination Technologies ...

1. A binary logic circuit for converting a number in floating point format having an exponent E of ew bits, an exponent bias B=2ew?1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits, the binary logic circuit comprising:an offset hardware circuit configured to offset the exponent of the floating point number by an offset value equal to (iw?1?sy) to generate a shift value svof sw bits given by sv=(B?E)+(iw?1?sy), the offset value being equal to a maximum amount by which the significand can be left-shifted before overflow occurs in the fixed point format;
a right-shifter operable to receive a significand input comprising a formatted set of bits derived from the significand, the right-shifter being configured to right-shift the significand input by a number of bits equal to the value represented by k least significant bits of the shift value to generate an output result, where bitwidth[min(2ew?1?1, iw?1?sy)+min(2ew?1?2, fw)]?k?sw, where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number.

US Pat. No. 10,560,114

ANALOG TO DIGITAL CONVERTERS WITH OVERSAMPLING

Avnera Corporation, Beav...

1. An analog-to-digital modulator for use at the output of an analog device, the analog-to-digital modulator comprising:a switched-capacitor loop filter including integrators, the integrators operable in a charging phase using a first clock phase and a dumping phase using a second clock phase non-overlapping with the first clock phase such that during the dumping phase at least some of the integrators are decoupled from the remaining integrators.

US Pat. No. 10,560,113

METHOD OF DETECTING USER INPUT IN A 3D SPACE AND A 3D INPUT SYSTEM EMPLOYING SAME

ZEROKEY INC., Calgary, A...

1. A position sensing apparatus for a hand, comprising:a plurality of first sensors positioned about joints of a wrist and one or more fingers of the hand, said sensors detecting angles of the respective joints;
a controller coupled to the first sensors and receiving angle detection data output therefrom;
a communication interface; and
a computing device communicating with the controller via the communication interface;
wherein the apparatus is configured for executing computer-executable code for:
calculating fingertip positions of at least one of the one or more fingers in a three-dimensional (3D) space using the angles detected by the first sensors;
generating one or more commands based on the calculated fingertip positions in the 3D space;
generating a virtual keyboard;
detecting at least one of the fingertips hitting a key of the virtual keyboard using a statistic estimation method; and
generating one or more keystrokes of the virtual keyboard based on the calculated fingertip positions in the 3D space;
wherein said detecting the at least one of the fingertips hitting the key of the virtual keyboard comprise:
determining parameters of a probability space of a hypothesis of “fingertip not hitting any key” and a probability space of a hypothesis of “fingertip hitting a key”; and
calculating a key-pressing threshold for determining the at least one of the one or more fingertips hitting a key of the virtual keyboard.

US Pat. No. 10,560,112

CAPACITOR ORDER DETERMINATION IN AN ANALOG-TO-DIGITAL CONVERTER

TEXAS INSTRUMENTS INCORPO...

1. A method, comprising:determining a respective differential nonlinearity most significant bit (DNL_MSB) error value for a first capacitor and a second capacitor in a capacitor array of an analog-to-digital converter (ADC);
determining a respective differential nonlinearity (DNL) error value for each of the plurality of capacitors based in part on the determined DNL_MSB error values;
determining a respective compensation error value for of the first and second capacitors, wherein the determination is based in part on a largest DNL_MSB value for the first and second capacitors;
determining an order of the first and second capacitors based on the respective DNL error value and the respective compensation error value; and
using, by the ADC, the first and second capacitors in the determined order during conversions of analog signals to digital codes.

US Pat. No. 10,560,111

NESTED CASCADED MIXED-RADIX DIGITAL DELTA-SIGMA MODULATOR

University College Cork-N...

1. A fractional-N frequency synthesizer comprising:a divider controller having a main nth order modulator and an auxiliary nth order modulator, wherein a noise shaping of the auxiliary nth order modulator is the same order as a noise shaping of the main nth order modulator, and wherein n is an integer value greater than one and the divider controller comprises a plurality of error feedback modulator stages connected in a two-level nested cascaded multi-stage noise shaping (MASH) digital delta-sigma modulator (DDSM) with a single error cancellation network.

US Pat. No. 10,560,110

PRECISION MICROWAVE FREQUENCY SYNTHESIZER AND RECEIVER WITH DELAY BALANCED DRIFT CANCELING LOOP

Giga-tronics Incorporated...

1. A signal converter comprising:a first mixer including an input for receiving a signal to be converted;
a second mixer including an output for providing said converted signal;
a variable oscillator for producing a signal (CS) variable at a first scale;
a splitter coupled to said first mixer and said second mixer to form a drift canceling loop, said splitter including an input coupled to receive said signal (CS) from said variable oscillator, a first output coupled to introduce said signal (CS) into said drift canceling loop along a first direction, and a second output coupled to introduce said signal (CS) into said drift canceling loop along a second direction opposite said first direction;
a delay device coupled between said second output of said splitter and an input of said second mixer;
a complementary delay device coupled between said first output of said splitter and an input of said first mixer, at least one of said delay device and said complementary delay device being adjustable;
a second variable oscillator for producing a signal (FS) variable at a second scale finer than said first scale; and
a third mixer coupled between said splitter and said first mixer and having an input coupled to receive said signal (FS) from said second variable oscillator; and wherein
said signal received by said first mixer is up-converted.

US Pat. No. 10,560,107

POWER SUPPLY POWER MANAGEMENT

Apple Inc., Cupertino, C...

1. A method of operating power management circuitry, the method comprising:providing a clock signal having a first frequency to a load circuit;
providing a load current into a load, the load comprising the load circuit;
detecting whether the load current exceeds a high current limit for a first duration;
in response to the load current exceeding the high current limit for the first duration, reducing the frequency of the clock signal to a second frequency, otherwise not reducing the frequency of the clock signal;
detecting whether an average of the load current exceeds an average current limit;
in response to the average load current exceeding the average current limit, reducing the frequency of the clock signal to the second frequency, otherwise not reducing the frequency of the clock signal;
while the frequency of the clock signal is the second frequency, detecting whether an output voltage provided to the load is below a first voltage threshold; and
in response to the output voltage being below the first voltage threshold, further reducing the frequency of the clock signal to a third frequency, otherwise not further reducing the frequency of the clock signal.

US Pat. No. 10,560,105

DELAY-LOCKED LOOP WITH LARGE TUNING RANGE

QUALCOMM Incorporated, S...

1. A delay-locked loop, comprising:a first delay line;
a second delay line;
a controller configured to select between the first delay line and the second delay line based upon a phase difference between a clock signal and a data signal, wherein the controller is further configured to select for the first delay line to delay the clock signal to form a delay-locked loop output clock signal responsive to the phase difference corresponding to a delay within a delay operating range for the first delay line and to select for the second delay line to delay the clock signal to form the delay-locked loop output clock signal responsive to the phase difference corresponding to a delay within a delay operating range for the second delay line;
a clock data recovery circuit configured to produce a control signal responsive to the phase difference between the clock signal and the data signal and to control a delay for the selected delay line responsive to the control signal; and
a demultiplexer configured to receive the control signal, wherein the controller is further configured to control the demultiplexer to demultiplex the control signal to the first delay line responsive to the selection of the first delay line by the controller and to demultiplex the control signal to the second delay line responsive to the selection of the second delay line by the controller.

US Pat. No. 10,560,104

CLOCK SYNCHRONIZATION APPARATUS AND METHOD

Intel Corporation, Santa...

1. An apparatus comprising:a clock multiplier to multiply an input clock by an integer;
a phase locked loop (PLL) coupled to the clock multiplier; and
a clock distribution network coupled to an input and output of the PLL, wherein the clock multiplier is to receive an input from a separate die, which includes a clock synchronization circuit.

US Pat. No. 10,560,103

FLUX-TUNABLE QUBIT DEVICE WITH MULTIPLE JOSEPHSON JUNCTIONS

1. A qubit device comprising:an inductor connected between a first circuit node and a second circuit node;
a first Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node; and
a second Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node,
wherein the qubit device is configured to receive, during operation of the qubit device, a magnetic flux that controls a qubit frequency of the qubit device, and the qubit frequency as a function of the magnetic flux comprises multiple flux sweet spots.

US Pat. No. 10,560,101

COUNT VALUE GENERATION CIRCUIT, PHYSICAL QUANTITY SENSOR MODULE, AND STRUCTURE MONITORING DEVICE

Seiko Epson Corporation, ...

1. A count value generation circuit comprising:a first counter that counts edges of a reference signal in synchronization with an input signal to generate a first count value;
a time digital value generator that generates a time digital value corresponding to a phase difference between the reference signal and the input signal;
a count integrated value combiner that outputs a difference between an integer multiple of the first count value and the time digital value; and
a count value generator that generates a count value based on a difference between a first output value and a second output value output from the count integrated value combiner.

US Pat. No. 10,560,100

APPARATUSES AND METHODS INCLUDING CONFIGURABLE LOGIC CIRCUITS AND LAYOUT THEREOF

Micron Technology, Inc., ...

1. An apparatus, comprising:a first P-channel transistor;
a second P-channel transistor;
a first N-channel transistor;
a second N-channel transistor;
a first node coupled to a gate of the first P-channel transistor and a gate of the first N-channel transistor;
a second node coupled to a gate of the second P-channel transistor and a gate of the second N-channel transistor;
a third node coupled to a source of the first P-channel transistor;
a fourth node coupled to a drain of the first P-channel transistor and a source of the second P-channel transistor;
a fifth node coupled to a drain of the second P-channel transistor;
a sixth node coupled to a drain of the first N-channel transistor;
a seventh node coupled to a source of the first N-channel transistor and a drain of the second N-channel transistor; and
an eighth node coupled to a source of the second N-channel transistor;
wherein the second node, the third node, the fifth node, and the seventh node are arranged along a first line;
wherein the first node, the fourth node, the sixth node, and the eighth node are arrange along a second line, wherein the second line is parallel to the first line.

US Pat. No. 10,560,099

SEMICONDUCTOR APPARATUS USING SWING LEVEL CONVERSION CIRCUIT

SK hynix Inc., Icheon-si...

1. A semiconductor apparatus comprising:an input selection circuit configured to select one of a first input signal and a second input signal in response to a control signal and configured to output the selected input signal as a selection signal, wherein swing levels of the first input signal and the second input signal are different from one another; and
a conversion circuit configured to generate an output signal, in response to the selection signal, wherein the output signal swings to a level substantially identical to a level of the second input signal,
wherein the input selection circuit comprises:
a first input circuit configured to transfer the first input signal to an output circuit;
a second input circuit configured to transfer the second input signal to the output circuit based on the control signal; and
the output circuit configured to perform at least one of an inverting operation and a resistive feedback inverting operation on the first and second input signals, received from the first and second input circuits, based on the control signal and output a result of the operation as the selection signal.

US Pat. No. 10,560,098

MECHANICAL RESONATOR BASED CASCADABLE LOGIC DEVICE

KING ABDULLAH UNIVERSITY ...

1. An apparatus, comprising:a resonator, including a beam having a first fixed end, a second fixed end, and a length between the first and second fixed ends;
a first electrode and a second electrode aligned along a first side of the beam;
a third electrode and a fourth electrode aligned along a second side of the beam and opposite the first and second electrodes;
a DC voltage source coupled to one of the first and second fixed ends of the beam;
wherein at least one of the first, second, third, and fourth electrodes is coupled to a first AC voltage source so that a logic operation is performed by activating a second resonant mode of the resonator.

US Pat. No. 10,560,095

IMPEDANCE-BASED PHYSICAL UNCLONABLE FUNCTION

Analog Devices, Inc., No...

1. An apparatus for providing an impedance based physically unclonable function (PUF), comprising:a first pair of resistors electrically connected in a first current path, the first pair of resistors having a first impedance ratio;
a second pair of resistors electrically connected in a second current path, the second pair of resistors having a second impedance ratio;
an analog-to-digital converter (ADC), configured to generate a plurality of bits based on:
a first voltage signal from the first current path that indicates the first impedance ratio; and
a second voltage signal from the second current path that indicates the second impedance ratio; and
processing circuitry configured to generate a PUF value based on the plurality of bits.

US Pat. No. 10,560,094

ISOLATION MODULE FOR USE BETWEEN POWER RAILS IN AN INTEGRATED CIRCUIT

Intel Corporation, Santa...

1. A system comprising:a processor circuit;
a power converter circuit coupled to the processor circuit and configured to provide, to the processor circuit, regulated DC power supply signals including first and second voltage signals;
wherein the processor circuit comprises a semiconductor die, the semiconductor die including first and second power domains configured to receive the first and second voltage signals, respectively, and wherein the processor circuit further comprises a first integrated inductor circuit and a first integrated capacitor circuit;
wherein each of the first and second power domains includes at least one power rail, and wherein each of the power rails is configured to provide different power signals to respective consumer circuits, and
wherein a first power rail in the first power domain is coupled to a second power rail using the first integrated inductor circuit and the first integrated capacitor circuit.

US Pat. No. 10,560,093

SEMICONDUCTOR DEVICES

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a first mode register configured to store a first selection termination control signal and a second selection termination control signal when a mode register write operation is performed;
a first termination circuit comprising an impedance value and configured to control the impedance value of the first termination circuit based on the first selection termination control signal and a termination control signal; and
a second termination circuit comprising an impedance value and configured to control the impedance value of the second termination circuit based on the second selection termination control signal and the termination control signal,
wherein the impedance values of the first and second termination circuits are controlled to be substantially equal to each other according to a logic level combination of the termination control signal.

US Pat. No. 10,560,092

CONTROL CIRCUIT FOR POWER SWITCH

STMICROELECTRONICS, INC.,...

1. A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, wherein a conduction terminal of a respective one of the first plurality of transistors is coupled to form a node with a conduction terminal of a respective one of the second plurality of transistors, the circuit comprising:a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to the gate of the respective one of the first plurality of transistors; and
a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to the gate of the respective one of the second plurality of transistors, wherein an output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages, and wherein an output current of the respective one of the second plurality of stages is regulated based on a difference between a third value representative of a sum of output currents of each stage of the second plurality of stages and a fourth value representative of a sum of set points assigned the second plurality of stages.

US Pat. No. 10,560,091

SWITCH ASSEMBLY OF REACTIVE POWER COMPENSATION APPARATUS

LSIS CO., LTD., Anyang-s...

1. A switch assembly of a reactive power compensation apparatus, the switch assembly comprising:a support module;
a first switching module having a first stack structure perpendicular to the supporting module; and
a second switching module having a second stack structure perpendicular to the supporting module, the second switching module being connected in parallel with the first switching module,
wherein each of the first and second switching modules comprises:
a plurality of cooling plates stacked along a vertical direction with respect to the supporting module; and
a plurality of switches disposed between the plurality of cooling plates, and
wherein each of the plurality of cooling plates comprises: an engagement portion disposed on one side of an upper surface of each of the plurality of cooling plates to be located at a normal position by guiding the plurality of switches,
wherein the engagement portion comprises at least one or more engagement protrusions having a circular shape, and
wherein the at least one or more engagement protrusions are spaced apart by a radius of each of the plurality of switches from a center of each of the plurality of cooling plates.

US Pat. No. 10,560,090

ONE-WAY CONDUCTION DEVICE

NIKO SEMICONDUCTOR CO., L...

1. A one-way conduction device, having an input end and an output end, comprising:a first transistor, wherein the first end of the first transistor is coupled to the input end, and the second end of the first transistor is coupled to the output end; and
a driving circuit, including:
a first circuit, including a first conduction unit and a first resistor, wherein the first conduction unit is coupled between the input end and one end of the first resistor, and the other end of the first resistor is coupled to a reference voltage;
a second circuit, including a second conduction unit and a second resistor, wherein the second conduction unit is coupled between the output end and the second resistor, and the other end of the second resistor is coupled to the reference voltage; and
a detection circuit, coupled to a node between the first conduction unit and the first resistor, a node between the second conduction unit and the second resistor, and the third end of the first transistor;
wherein the driving circuit detects whether a current flows from the node between the first conduction unit and the first resistor to the node between the second conduction unit and the second resistor through the detection circuit, and accordingly turns on or turns off the first transistor to control the turning on and turning off of the one-way conduction device.

US Pat. No. 10,560,088

TOTEM-POLE CIRCUIT DRIVER

FUJI ELECTRIC CO., LTD., ...

1. A totem-pole circuit driver for driving a totem-pole circuit including a high-side power device and a low-side power device which are cascade-connected, the totem-pole circuit driver comprising:a high-side drive circuit which drives the high-side power device;
a low-side drive circuit which drives the low-side power device;
a pulse generation circuit which receives a high-side input logic signal that has a first edge and a second edge, and generates a set signal for turning on the high-side power device and a reset signal for turning off the high-side power device, based respectively on the first edge and the second edge;
a level shift circuit which transmits the set signal and the reset signal to the high-side drive circuit;
a high-side potential detection circuit which detects a high-side reference potential;
a high-side potential determination circuit which
compares a value of the high-side reference potential detected by the high-side potential detection circuit with a reference voltage, and
outputs an event signal upon detecting that the value of the high-side reference potential exceeds the reference voltage; and
an on-pulse stop circuit which receives a low-side input logic signal, and validates or invalidates the low-side input logic signal based on the high-side input logic signal and the event signal, wherein
when the high-side input logic signal is at a low level, by which the high-side power device is turned off, and upon receiving the event signal,
the pulse generation circuit regenerates the reset signal, and
the on-pulse stop circuit invalidates the low-side input logic signal and outputs a signal at a low level, by which the low-side power device is turned off.

US Pat. No. 10,560,087

PASSIVE LEAKAGE MANAGEMENT CIRCUIT FOR A SWITCH LEAKAGE CURRENT

GE Aviation Systems Limit...

1. A passive leakage management circuit for a switch leakage current comprising:a switch that includes an input electrically coupled with a source of alternating current (AC) and an output electrically coupled with an electrical load, and is operable in a first operating mode, wherein the output supplies an AC output current provided to the input and having a first AC voltage, and in a second operating mode, wherein the output supplies an AC leakage current from the input and having a second AC voltage lower than the first AC voltage;
a rectifying module electrically coupled with the switch output and that rectifies the AC output current to a direct current (DC) output current during the first operating mode and the second operating mode;
a first current path that receives the DC output current and includes a first transistor that conducts current along the first current path based on the switch output; and
a leakage current path that receives the DC output current and includes a second transistor that conducts current along the leakage current path based on the first transistor not conducting current;
wherein at least one of the first current path or leakage current path conducts current based on the switch output, without an additional power source beyond the switch output, and independent of the first or second operating mode of the switch, and wherein only one of the first current path or leakage current path conducts current when the switch is coupled with the source of alternating current.

US Pat. No. 10,560,085

APPARATUSES FOR REDUCING OFF STATE LEAKAGE CURRENTS

Micron Technology, Inc., ...

1. An apparatus comprising:a switch including first through fourth transistors,
the first and second transistors configured to be in an off state when the switch is in the off state based on the first transistor controlled by a first reference voltage and the second transistor controlled by a second reference voltage,
the third and fourth transistors configured to be in a first conductive state when the switch is in the off state based on the third and fourth transistors controlled by a third reference voltage that is less than the first reference voltage and greater than the second reference voltage,
wherein the first reference voltage is coupled to a gate of the fourth transistor when the switch is in an on state, and
wherein the third reference voltage is coupled to the gate of the fourth transistor when the switch is in the off state.

US Pat. No. 10,560,084

LEVEL SHIFT CIRCUIT

Toshiba Memory Corporatio...

1. A level shift circuit comprising:a first PMOS transistor electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, electrically connected to a second node at a source, and electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential different from the first power-supply potential is output;
a first NMOS transistor electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain;
a second PMOS transistor electrically connected to a third node at a gate, electrically connected to a node to be the second power-supply potential at a source, and electrically connected to the second node at a drain;
a third PMOS transistor electrically connected at a gate to a fourth node to which a second signal having an amplitude to be the first power-supply potential and being logical inversion of the first signal is input, electrically connected to a fifth node at a source, and electrically connected to the third node at a drain;
a second NMOS transistor electrically connected to the fourth node at a gate and electrically connected to the third node at a drain;
a fourth PMOS transistor electrically connected to the output terminal at a gate, electrically connected to the node to be the second power-supply potential at a source, and electrically connected to the fifth node at a drain; and
a potential adjusting circuit that is electrically connected to at least the second node, and
wherein the potential adjusting circuit is a charging circuit electrically connected to the second node,
the charging circuit includes a switch electrically inserted between the node to be the second power-supply potential and the second node,
the switch is maintained to be in an on state in a first time period from before a first timing at which the output terminal transitions from a first level to a second level to the first timing, and is maintained to be in an off state in a second time period following the first time period.

US Pat. No. 10,560,083

CONTROL DEVICE FOR POWER SUPPLY LINE

1. A control device to be arranged between two portions of an electrical power supply line, the device comprising:a bipolar transistor comprising a wide bandgap semiconductor material and having its emitter connected to one portion of the power supply line, its collector connected to another portion of the power supply line; and
a control circuit connected to the base of said transistor and configured to operate in an open loop without feedback.

US Pat. No. 10,560,082

PULSE WIDTH MODULATION CIRCUIT, CORRESPONDING DEVICE AND METHOD

STMicroelectronics S.r.l....

1. A circuit comprising:a first circuit block configured to receive a square wave input signal having rising and falling edges and to produce a triangular wave signal from the square wave input signal;
a second circuit block configured to receive a modulating signal and to produce a pulse width modulated signal by comparing the modulating signal with a carrier signal;
a switching circuit block coupled between the first circuit block and the second circuit block, wherein the switching circuit block comprises reference inputs configured to receive reference signals having upper and lower reference values, wherein the switching circuit block is selectively switchable between:
a carrier transfer setting in which the switching circuit block couples the first circuit block to the second circuit block to transfer the triangular wave signal as the carrier signal, and
a carrier forcing setting in which the switching circuit block applies to the second circuit block the reference signals by forcing the carrier signal to respective upper and lower reference values; and
a clock circuit block sensitive to the rising and falling edges of the square wave input signal, the clock circuit block configured to drive the switching circuit block to switch between the carrier transfer setting and the carrier forcing setting at the rising and falling edges of the square wave input signal.

US Pat. No. 10,560,081

METHOD, APPARATUS, SYSTEM FOR CENTERING IN A HIGH PERFORMANCE INTERCONNECT

Intel Corporation, Santa...

1. An interconnect apparatus, comprising:a clock signal generator to generate a clock signal;
a reference voltage shifter to:
shift a reference voltage of the clock signal by a first test voltage at an operational speed of the interconnect; and
shift the reference voltage by a second test voltage;
an error rate detector to:
measure an error rate of the first test voltage;
compare the error rate of the first test voltage to an error rate of the second test voltage; and
select an optimal test voltage; and
an operational voltage selector to select an operational reference voltage of the clock signal based at least in part on the optimal test voltage.

US Pat. No. 10,560,080

DUTY CYCLE CORRECTION

NXP B.V., Eindhoven (NL)...

1. A duty cycle correction circuit, comprising:an input stage to reduce rise time or fall time of an input signal;
an output stage amplifier to amplify an output signal from the input stage to a preselected voltage swing and a target common voltage, wherein an input of the output stage is coupled to a fix voltage reference; and
a feedback component including a feedback amplifier and a low pass filter to filter noise and to correct duty cycle of the signal from an output of the output stage amplifier.

US Pat. No. 10,560,078

ELECTRONIC DEVICE

SK hynix Inc., Gyeonggi-...

1. An electronic device comprising:a ramp signal generation block configured to generate a ramp signal on a basis of a ramp code signal;
a slope adjustment block configured to adjust a slope of the ramp signal so that the ramp signal has a second slope decreased by the first level from a first slope corresponding to an analog gain, on a basis of a gain code signal, the second slope corresponding to decreasing the first slope by the first level;
a first slope correction block configured to basically increase the slope of the ramp signal by the first level and optionally decrease the slope of the ramp signal in a range corresponding to the first level, on a basis of a first correction code signal; and
a second slope correction block configured to optionally increase the slope of the ramp signal by a second level on a basis of a second correction code signal,
wherein the second slope correction block includes at least one second resistor part electrically coupled in parallel to an output terminal of the ramp signal, and
the second resistor part reflects a second resistance value corresponding to the second level in the output terminal on the basis of the second correction code signal.

US Pat. No. 10,560,077

CR OSCILLATOR

TOSHIBA MEMORY CORPORATIO...

1. A CR oscillator comprising:a first logic inversion unit including odd-number stages of logic inversion elements connected in series;
a second logic inversion unit including odd-number stages of logic inversion elements connected in series, the second logic inversion unit being connected to a latter stage of the first logic inversion unit; and
two or more resistors and a capacitor connected in series between an output node of the first logic inversion unit and an output node of the second logic inversion unit,
wherein an electric potential in accordance with an electric potential of an intermediate node between the two or more resistors is supplied to an input node of the first logic inversion unit,
wherein the two or more resistors comprise a first resistor and a second resistor connected in series between the output node of the first logic inversion unit and one terminal of the capacitor,
the electric potential of the intermediate node is an electric potential of a connection node of the first resistor and the second resistor,
a ratio of a resistance value of the first resistor and a resistance value of the second resistor is set so that an electric potential of the input node of the first logic inversion unit is equal to or lower than a power-supply electric potential of the first logic inversion unit but equal to or higher than a ground electric potential of the first logic inversion unit, and
the ratio is set so that expressions (1) and (2) are established, wherein the ratio is X, the power-supply electric potential of the first logic inversion unit and the second logic inversion unit is V, and a threshold voltage of the first logic inversion unit is Vth:

US Pat. No. 10,560,076

FREQUENCY GENERATION IN A QUANTUM CONTROLLER

Quantum Machines, (IL)

1. A system comprising:a quantum controller comprising quantum control pulse generation circuitry, phase parameter generation circuitry, time-tracking circuitry, and signal generation circuitry, wherein:
the quantum control pulse generation circuitry is operable to generate a sequence of two quantum control pulses;
the phase parameter generation circuitry is operable to determine, based on an output of the time-tracking circuitry, a value of a phase parameter that corresponds to a phase of an oscillating signal relative to a reference time;
the signal generation circuitry is operable to:
at the reference time, begin generation of the oscillating signal at a first frequency for modulation of a first of the two quantum control pulses;
at a second time after the reference time, change the oscillating signal to a second frequency for modulation of the second quantum control pulse, wherein the phase of the oscillating signal at the second time is determined by the value of the phase parameter such that the phase of the oscillating signal is as it would have been if the oscillating signal had been oscillating at the second frequency continuously since the reference time.

US Pat. No. 10,560,075

FPGA CONFIGURED VECTOR NETWORK ANALYZER FOR MEASURING THE Z PARAMETER AND S PARAMETER MODELS OF THE POWER DISTRIBUTION NETWORK IN FPGA SYSTEMS

1. A method for measuring the phase of periodic variations of the voltage of a power supply domain of a programmable logic device containing configurable blocks powered from the power supply domain, comprising:configuring the programmable logic device to implement a current load generator that consumes a periodic varying electric current from a power supply domain the said periodic varying electric current having an activate feature and a frequency programming feature;
configuring the programmable logic device to implement a ring oscillator containing configurable blocks powered from said power supply domain;
configuring the programmable logic device to implement a phase and phase modulation measurement function for said ring oscillator;
programming a frequency value of said periodic varying electric current, activating said periodic varying electric current, measuring the phase and phase modulation of said ring oscillator, calculating the phase of the voltage variation of the power supply domain by computations including the measured phase and phase modulation of said ring oscillator.

US Pat. No. 10,560,071

RADIO FREQUENCY SIGNAL ATTENUATOR AND METHOD OF OPERATION THEREOF

STMICROELECTRONICS SA, M...

1. An attenuator, comprising:a plurality of capacitors including a plurality of circuits coupled in series, wherein a respective circuit comprises:
a first capacitor connected between an input node of the respective circuit and an output node of the respective circuit, and
a second capacitor connected between the output node of the respective circuit and a reference node, wherein the output node of the respective circuit, other than a last circuit of the plurality of circuits, is connected to the input node of a successive circuit, and
a third capacitor directly connected between the output node of the last circuit and the reference node; and
a plurality of selectors, wherein the respective circuit is associated with a respective selector, wherein the respective selector is coupled between the output node of the respective circuit and an output node of the attenuator, wherein attenuation values of the attenuator depend only on the capacitance values of the plurality of capacitors.

US Pat. No. 10,560,069

ELASTIC WAVE APPARATUS

MURATA MANUFACTURING CO.,...

1. An elastic wave apparatus comprising:a multilayer substrate including a plurality of wiring layers;
a plurality of filter devices disposed on the multilayer substrate and connected to a common node;
an antenna terminal to be connected to an antenna and to the common node;
a first inductor connected to the antenna terminal; and
a second inductor connected between one of the plurality of filter devices and the common node; wherein
the first inductor is disposed on at least one of the plurality of wiring layers;
the second inductor is disposed on a wiring layer which is different from the at least one of the plurality of wiring layers on which the first inductor is disposed; and
the first and second inductors overlap each other at least partially as viewed from above.

US Pat. No. 10,560,068

MULTIPLEXER

TAIYO YUDEN CO., LTD., T...

1. A multiplexer comprising:a first substrate having a first surface;
a second substrate having a second surface facing the first surface across an air gap;
a first filter including a plurality of first resonators, the plurality of first resonators being located on the first surface and connected between a common terminal and a first terminal;
a second filter including a plurality of second resonators, the plurality of second resonators being located on the second surface and connected between the common terminal and a second terminal, at least a part of a first resonator connected in series between the common terminal and the first terminal and closest to the common terminal among the plurality of first resonators overlapping in plan view with at least a part of a second resonator connected in series between the common terminal and the second terminal and closest to the common terminal among the plurality of second resonators, at least one of first resonators other than the first resonator closest to the common terminal of the plurality of first resonators not overlapping with the plurality of second resonators in plan view, at least one of second resonators other than the second resonator closest to the common terminal of the plurality of second resonators not overlapping with the plurality of first resonators in plan view.

US Pat. No. 10,560,067

BROADBAND PROBES FOR IMPEDANCE TUNERS

Maury Microwave, Inc., O...

12. A slab line impedance tuner system operable over a frequency bandwidth, the tuner system comprising:a slab line transmission including opposed slab conductor planes and a center conductor disposed between the slab conductor planes;
a probe;
a probe carriage carrying the probe;
a carriage drive system for moving the probe carriage in a longitudinal direction parallel to the center conductor;
a probe drive system for moving the probe in a transverse direction relative to the center conductor to position the probe closer to or further away from the center conductor; and
wherein the probe includes:
a tapered conductive probe section having a nominal length dimension along the longitudinal direction, wherein the tapered probe has a cross-sectional profile defining a trough configured to straddle the center conductor as the probe is moved transversely toward the center conductor;
wherein the probe section is supported for movement along the center conductor and in a direction transverse to the center conductor; and
wherein the nominal length dimension is sufficient to provide a desired characteristic impedance transformation for the frequency bandwidth, wherein the characteristic impedance of the tuner system is transformed continuously by the probe to intermediate impedance values to reach a target impedance value.

US Pat. No. 10,560,065

PIEZOELECTRIC RESONATOR MANUFACTURING METHOD AND PIEZOELECTRIC RESONATOR

MURATA MANUFACTURING CO.,...

1. A piezoelectric resonator comprising:a piezoelectric thin film;
a support substrate located at a back surface side of the piezoelectric thin film;
an adhesive layer located at a surface side of the support substrate that faces the back surface side of the piezoelectric thin film; and
a support layer that fixes the piezoelectric thin film to the support substrate so as to provide a space between the piezoelectric thin film and the support substrate; wherein
a corner portion of the support layer at a side of the support substrate, which is exposed to the space, includes a recess defined by a cut in the corner portion;
the support substrate includes an adhered portion at which the support layer and the support substrate are adhered to one another, and a non-adhered portion at which the support layer and the support substrate are not adhered to one another; and
a thickness of a portion of the adhesive layer located at the adhered portion is thinner than a thickness of another portion of the adhesive layer located at the non-adhered portion.

US Pat. No. 10,560,064

DIFFERENTIAL AMPLIFIER INCLUDING CANCELLATION CAPACITORS

TEXAS INSTRUMENTS INCORPO...

1. An operational amplifier input stage comprising:a differential amplifier comprising:
a pair of driver metal oxide semiconductor field effect transistors (MOSFETs);
a first current source including a first pair of bipolar junction transistors (BJTs);
a parasitic capacitor coupled to a voltage source and to a common emitter node, the common emitter node coupled to emitters of the BJTs in the second pair of BJTs; and
a translinear loop coupled to the first current source and including a second pair of BJTs, a first diode coupled to the second pair of BJTs, a first resistor coupled to the first diode, a second diode coupled to the first resistor, a third pair of BJTs coupled to the second diode, a third diode coupled to the third pair of BJTs, a second resistor coupled to the third diode, and a fourth diode coupled to the second resistor;
a transconductance linearization circuit, comprising:
a second current source comprising a fourth pair of BJTs, the fourth pair of BJTs in a cascoded configuration;
at least one translinear loop coupled to the second current source and comprising a plurality of BJTs; and
a BJT positioned between the at least one translinear loop and the first current source, a base of the BJT coupled to bases of the BJTs in the first pair of BJTs; and
a cancellation capacitor coupled to the second current source and to the common emitter node.

US Pat. No. 10,560,060

LINEAR CMOS PA WITH LOW QUIESCENT CURRENT AND BOOSTED MAXIMUM LINEAR OUTPUT POWER

Qorvo US, Inc., Greensbo...

1. A power amplifier (PA) system comprising:a transmit path configured to amplify an input radio frequency (RF) signal, the transmit path comprising:
a first tank circuit; and
a PA stage; and
control circuitry configured to:
detect a power level associated with the input RF signal;
control a quality factor (Q) of the first tank circuit based on a first function of the power level; and
control a first bias signal provided to the PA stage based on a third function of the power level;
wherein the first function and the third function of the power level are polynomial functions.

US Pat. No. 10,560,059

POWER AMPLIFIER MODULE

MURATA MANUFACTURING CO.,...

1. A power amplifier module comprising:an amplifier that amplifies an input signal and outputs an amplified signal from an output terminal;
a matching circuit disposed between the output terminal of the amplifier and a subsequent circuit;
a choke inductor, wherein a power supply voltage is applied to a first end of the choke inductor; and
a first attenuation circuit disposed between the output terminal of the amplifier and a second end of the choke inductor, the first attenuation circuit attenuating a second harmonic of the amplified signal, wherein:
the first attenuation circuit includes:
a first inductor, wherein a first end of the first inductor is connected to the output terminal of the amplifier and a second end of the first inductor is connected to the second end of the choke inductor, and
a first capacitor, wherein a first end of the first capacitor is connected to the second end of the first inductor and a second end of the first capacitor is grounded,
the matching circuit includes:
a second attenuation circuit that attenuates frequencies greater than a fundamental frequency of the amplified signal; and
a filter, and
the second attenuation circuit is a low pass filter,
the first attenuation circuit and the second attenuation circuit are not included as part of a chip of the amplifier.

US Pat. No. 10,560,058

METHOD OF EQUALIZING CURRENTS IN TRANSISTORS AND FLOATING CURRENT SOURCE

1. A current equalizing circuit comprising:a first supply voltage (VDD) and a second supply voltage (VSS);
a first P-channel Metal Oxide Silicon Field Effect Transistor (PMOSFET) having a first PMOSFET gate terminal coupled with a first node, a first PMOSFET source terminal coupled with VDD, and a first PMOSFET drain terminal coupled with a third node;
a second PMOSFET having a second PMOSFET gate terminal coupled with a fifth node, a second PMOSFET source terminal coupled with the third node, and a second PMOSFET drain terminal coupled with a fourth node;
a first N-channel Metal Oxide Silicon Field Effect Transistor (NMOSFET) having a first NMOSFET gate terminal coupled with a second node, a first NMOSFET source terminal coupled with VSS, and a first NMOSFET drain terminal coupled with the fourth node;
a second NMOSFET having a second NMOSFET gate terminal coupled with a sixth node, a second NMOSFET source terminal coupled with the fourth node, and a second NMOSFET drain terminal coupled with the third node;
a first regulating circuit comprising a first regulating circuit input port, and a first regulating circuit output port;
a second regulating circuit comprising a second regulating circuit input port, and a second regulating circuit output port;
wherein the first regulating circuit input port communicates with the third node, and wherein the first regulating circuit output port communicates with the first node and the fifth node; and
wherein the second regulating circuit input port communicates with the fourth node, and where in the second regulating circuit output port communicates with the second node and the sixth node.

US Pat. No. 10,560,056

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a differential circuit;
a bias circuit configured to supply a bias current to the differential circuit;
a reference voltage generation circuit configured to output a reference voltage to the bias circuit;
a switch configured to control supply of a power supply voltage to the reference voltage generation circuit; and
a holding circuit configured to hold the reference voltage,
wherein the holding circuit comprises a first transistor and a capacitor,
wherein the bias circuit comprises a second transistor,
wherein the first transistor comprises an oxide semiconductor film comprising a channel formation region,
wherein one of a source and a drain of the first transistor is electrically connected to the reference voltage generation circuit,
wherein the other of the source and the drain of the first transistor is electrically connected to the bias circuit,
wherein the capacitor is electrically connected to the other of the source and the drain of the first transistor,
wherein the first transistor is configured to be turned off while the differential circuit operates and a current flows in the second transistor, and
wherein the switch is configured to stop the supply of the power supply voltage to the reference voltage generation circuit while the differential circuit operates and the current flows in the second transistor.

US Pat. No. 10,560,055

VOLTAGE MODE POWER COMBINER FOR RADIO FREQUENCY LINEAR POWER AMPLIFIER

Skyworks Solutions, Inc.,...

1. A radio frequency power combining amplifier circuit with a circuit input and a circuit output, comprising:a first amplifier connected to the circuit input and to a first bias input;
a first output matching network connected to an output of the first amplifier and to the circuit output, the first output matching network and the first amplifier being optimized for small signal linearity;
a second amplifier connected to the circuit input and to a second bias input, the first and second bias inputs being set such that, when a voltage of an input signal to the circuit input is at a first level, the first amplifier is on and the second amplifier is off and, when a voltage of the input signal is at a second level, the first amplifier is saturated and the second amplifier is on; and
a second output matching network connected to an output of the second amplifier and to the circuit output, the second output matching network and the second amplifier being optimized for maximum linear output power.

US Pat. No. 10,560,054

CIRCUIT SYSTEM

HUAWEI TECHNOLOGIES CO., ...

1. A circuit system, comprising an operational amplification circuit, whereinthe operational amplification circuit comprises:
N stages of operational amplification units that are cascaded, N being greater than or equal to 2, wherein each of the N stages comprises an input terminal and an output terminal and the N stages include a 1st stage, an Nth stage, and an ith stage, wherein
an input terminal of the 1st stage is an input terminal of the operational amplification circuit and is configured to receive an initial input signal,
an output terminal of the Nth stage is an output terminal of the operational amplification circuit, and
the output terminal of the ith stage is connected to the input terminal of the (i+1)th stage, so as to provide an input signal for the (i+1)th stage, wherein i is 1, 2, . . . , or N?1; and
a feedback channel from the output terminal of the Nth stage to the input terminal of each of the N stages of operational amplification units exists, wherein the feedback channel is configured to facilitate a transmission of an output signal of the Nth stage of operational amplification unit to the input terminal of each of the N stages; and, wherein
the operational amplification circuit is a dual-input and single-output operational amplification circuit for receiving a differential signal and driving a single-terminal load circuit;
the Nth stage comprises an operational amplifier, and
the Nth stage further comprises a phase inverter disposed on the feedback channel, the phase inverter and the operational amplifier in the Nth stage of operational amplification unit constituting a pseudo-differential structure.

US Pat. No. 10,560,053

DIGITAL FRACTIONAL FREQUENCY DIVIDER

Qorvo US, Inc., Greensbo...

1. Frequency synthesizer circuitry comprising:multi-phase clock generator circuitry configured to:
receive an input clock signal; and
generate a plurality of multi-phase clock signals based on the input clock signal such that a frequency of each one of the plurality of multi-phase clock signals is equal to a frequency of the input clock signal, a duty cycle of each one of the plurality of multi-phase clock signals is equal to a duty cycle of the input clock signal, and each one of the plurality of multi-phase clock signals has a different phase shift with respect to the input clock signal;
frequency divider circuitry coupled to the multi-phase clock generator circuitry and configured to:
receive the input clock signal; and
generate a reference signal based on the input clock signal such that a frequency of the reference signal is lower than the frequency of the input clock signal and a duty cycle of the reference signal is different from the duty cycle of the input clock signal;
signal retiming circuitry coupled to the multi-phase clock generator circuitry and the frequency divider circuitry and configured to:
receive the reference signal and the plurality of multi-phase clock signals; and
generate a plurality of retiming signals, each based on the reference signal and a different one of the plurality of multi-phase clock signals such that a frequency of each one of the plurality of retiming signals is equal to the frequency of the reference signal, a duty cycle of each one of the plurality of retiming signals is equal to the duty cycle of the reference signal, and a phase of each one of the plurality of retiming signals is shifted with respect to the reference signal by an amount determined by the one of the plurality of multi-phase clock signals used to generate the retiming signal; and
signal combining circuitry configured to combine two retiming signals of the plurality of retiming signals to generate an output clock signal such that a frequency of the output clock signal is equal to the frequency of the reference signal and a duty cycle of the output clock signal is equal to the duty cycle of the input clock signal.

US Pat. No. 10,560,052

PHOTOVOLTAIC MODULE CAPABLE OF OUTPUTTING AC VOLTAGE WITHOUT CONVERTING LEVEL OF DC VOLTAGE

LG ELECTRONICS INC., Seo...

1. A photovoltaic module, comprising:a solar cell module including a plurality of solar cells;
a capacitor unit to receive a direct current (DC) voltage from the solar cell module and to store the DC voltage output from the solar cell module;
an inverter unit to convert the DC voltage stored in the capacitor unit into an alternating current (AC) voltage without converting a level of the DC voltage received from the solar cell module;
a controller to control the inverter unit;
an input current detector to detect an input current flowing into the capacitor unit; and
an input voltage detector to detect an input voltage of both terminals of the capacitor unit,
wherein the solar cell module outputs the DC voltage having a level higher than a peak value of a grid voltage,
wherein the controller calculates a maximum power for the solar cell module and controls the inverter unit to output the AC voltage using a DC voltage corresponding to the maximum power, and
wherein the plurality of solar cells include multi-cutting cells, respectively.

US Pat. No. 10,560,051

PHOTOVOLTAIC APPARATUS

Sumitomo Electric Industr...

1. A photovoltaic apparatus configured to cause a photovoltaic panel to perform operation of tracking the sun, the photovoltaic apparatus comprising:a position changeable part configured to change a position of the photovoltaic panel so as to cause the photovoltaic panel to perform the tracking operation; and
a function part, which has a housing accommodating electronic components therein, located in an area of a back surface side opposite to a light receiving surface of the photovoltaic panel where sunlight is blocked, the function part being supported by an arm extending away from the back surface side whereby a relative positional relation between the function part and the photovoltaic panel is fixed via the arm, wherein the arm includes an arm part which is hollow, wherein
with respect to a direction perpendicular to the light receiving surface, a moment of the photovoltaic panel by gravity centering on the position changeable part and a moment of the function part by gravity centering on the position changeable part are configured to act in reverse directions to each other, and
a wire passing through a hollow portion of the arm part, the wire connecting the position changeable part and the function part with each other, connecting the function part and the photovoltaic panel with each other, or connecting the photovoltaic panel and the position changeable part with each other.

US Pat. No. 10,560,048

PHOTOVOLTAIC ROOFING SYSTEMS WITH BOTTOM FLASHINGS

CertainTeed Corporation, ...

1. A photovoltaic roofing system disposed on a roof deck having a top end, a bottom end, a first lateral side and a second lateral side opposing the first lateral side, the photovoltaic roofing system comprising:a plurality of contiguously-disposed, discrete photovoltaic roofing elements, the photovoltaic roofing elements being photovoltaic roofing shingles, photovoltaic roofing tiles, photovoltaic roofing shakes or photovoltaic roofing slates, each of the photovoltaic roofing elements being disposed directly against the roof deck or directly against one or more sheets of membrane or underlayment disposed against the roof deck, the contiguously-disposed plurality of photovoltaic roofing elements defining a bottom edge, the contiguously-disposed photovoltaic roofing elements including one or more bottom end photovoltaic roofing elements disposed in a row at the bottom edge thereof, each of the bottom end photovoltaic roofing elements having a bottom end;
one or more bottom flashing elements disposed along the bottom edge of the contiguously-disposed plurality of photovoltaic roofing elements such that the one or more bottom flashing elements extend along the entire bottom edge of the contiguously-disposed plurality of photovoltaic roofing elements, each of the one or more bottom flashing elements having an upward-facing surface, a top end and a bottom end, and a first lateral end and a second lateral end, the top end of each of the one of more bottom flashing elements being substantially disposed under at least one of the bottom end photovoltaic roofing elements at the bottom end thereof such that each of the bottom end photovoltaic roofing elements is disposed on one or more of the bottom flashing elements, and such that the bottom end of each of the one or more bottom flashing elements protrudes beyond the bottom edge of the contiguously-disposed photovoltaic roofing elements, and such that the entire bottom edge of the contiguously-disposed photovoltaic roofing elements is disposed over the one or more bottom flashing elements, wherein each of the one or more bottom flashing elements comprises
a top end piece having a top end forming the top end of the bottom flashing element, the top end piece being affixed to the roof; and
a bottom end piece separate from the top end piece, the bottom end piece having a bottom end forming the bottom end of the bottom flashing element, the bottom end piece not being affixed to the roof or to the top end piece, the bottom end piece being removably interlocked with the top end piece so as to hold it in position relative to the top end piece, wherein the plurality of photovoltaic roofing elements do not extend to the bottom end piece of any of the bottom end flashing elements; and
a plurality of non-photovoltaic roofing elements disposed in a row extending along the entirety of the bottom end of the one or more bottom flashing elements, each non-photovoltaic roofing element having an exposure zone at a bottom end thereof and a headlap zone at a top end thereof, the headlap zone of each non-photovoltaic roofing element being disposed under one or more of the bottom end flashing elements at the bottom end thereof, such that each of the bottom flashing elements is disposed on the headlap zone of one or more of the non-photovoltaic roofing elements, and each of the non-photovoltaic roofing elements of the row is overlapped by one or more of the bottom end flashing elements, wherein the one or more non-photovoltaic roofing elements disposed along the bottom end of the one or more bottom flashing elements are affixed to the roof deck by one or more fasteners, the one or more fasteners being disposed under bottom end piece(s) of the one or more bottom end flashing elements.

US Pat. No. 10,560,046

MOTOR CONTROL DEVICE

JTEKT CORPORATION, Osaka...

1. A motor control device that controls an electric motor that has three-phase motor coils in two systems with a phase difference of 60 degrees, 180 degrees, or 300 degrees between the two systems via a first drive circuit that drives three-phase motor coils in a first system, which is one of the two systems, and a second drive circuit that drives three-phase motor coils in a second system, which is the other system, the first drive circuit and the second drive circuit each having sets of upper and lower switching elements for three phases, the motor control device comprising:a setting unit that sets a two-phase current command value corresponding to a target current value for a current that is to flow through the electric motor;
an actual current value computation unit that computes an actual two-phase current value that matches a current that flows through the electric motor;
a first PWM count computation unit that computes a first PWM count for each of three phases in the first system in each PWM cycle on the basis of the two-phase current command value and the actual two-phase current value; and
a second PWM count computation unit that computes a second PWM count for each of three phases in the second system in each PWM cycle in accordance with the phase difference on the basis of the first PWM count for each of the three phases in the first system, wherein
the upper and lower switching elements for each phase in one of the first system and the second system are controlled in accordance with a first pattern in which the upper and lower switching elements are varied in an order of an upper on state, a lower on state, and the upper on state from a time of start of PWM cycles, and the upper and lower switching elements for each phase in the other system are controlled in accordance with a second pattern in which the upper and lower switching elements are varied in an order of a lower on state, an upper on state, and the lower on state from a time of start of PWM cycles.

US Pat. No. 10,560,045

DRIVING DEVICE FOR MULTI-AXIS COMMON-MODE VOICE COIL MOTOR

INDUSTRIAL TECHNOLOGY RES...

1. A driving device for multi-axis common-mode voice coil motor, comprising:a control signal processing interface, configured to generate a plurality of control signals and a plurality of command signals; and
a plurality of drive-stage circuits, configured to receive the control signals and the command signals respectively, and each of the drive-stage circuits being connected to one end of one of coils of a voice coil motor and comprising a half-bridge switch circuit, wherein the drive-stage circuit controls the half-bridge switch circuit to generate a driving current to drive the coil according to the control signal;
wherein the drive-stage circuit implements a current feedback mechanism to compare a feedback signal of the driving current for driving the coil with the command signal to generate an adjustment signal and adjusts the driving current according to the adjustment signal, whereby the driving current tracks the command signal.

US Pat. No. 10,560,043

FLOATING DEVICE GENERATOR

1. A floating power generator, comprising:a boat or vessel having at least one hull;
a frame connected to the boat or vessel and extending upwardly from the boat or vessel;
a paddle wheel supported by the frame at an elevated position of rotation above the at least one hull of the boat or vessel;
an electrical system for generating electrical power and providing a power source, the electrical system located on the boat or vessel, the electrical system comprising:
an electrical generator connected to and driven by the paddle wheel, the electrical generator being located on a side of the paddle wheel and support by the frame at the elevated position above the at least one hull of the boat or vessel;
a generator controller connected to the electrical generator to control the operation of the electrical generator;
a rotational speed sensor configured for detecting the rotational speed of the paddle wheel;
a water flow speed sensor configured for detecting a water flow speed relative to the floating power generator;
a power meter connected to the electrical generator, the power meter serving as a power output for the electrical system; and
a computer for receiving inputs from the rotational speed sensor, the water flow speed sensor, and the power meter, and generating an output signal controlling the generator controller.

US Pat. No. 10,560,042

TURBOCOMPRESSOR COMPRISING A COMPRESSOR MOTOR GENERATING REGENERATIVE ELECTRIC POWER BY REGENERATIVE DRIVING CAPABLE OF DRIVING A COMPRESSOR MOTOR

PANASONIC INTELLECTUAL PR...

1. A turbocompressor apparatus that is connectable to a power source, comprising:a turbocompressor including:
a rotary shaft;
a shaft bearing that supports the rotary shaft;
a compression mechanism that compresses and discharges a cooling medium by rotation of the rotary shaft;
a compressor motor that rotates the rotary shaft; and
a lubricant supply passage through which a lubricant is supplied to the shaft bearing,
a lubrication pump including a pump motor that generates driving force for supplying the lubricant to the shaft bearing through the lubricant supply passage;
a converter that performs electric power conversion between a voltage of the power source and a direct-current voltage of a direct-current voltage unit in a case where electric power is being supplied from the power source to the converter;
a first inverter that performs electric power conversion between the direct-current voltage and a first alternating-current voltage vector of the compressor motor; and
a second inverter that performs electric power conversion between the direct-current voltage and a second alternating-current voltage vector of the pump motor,
the compressor motor generating regenerative electric power by regenerative driving and the pump motor being driven by the regenerative electric power in a case where supply of electric power from the power source to the converter is being cut off,
wherein the turbocompressor apparatus performs a normal operation in which the pump motor is driven by using the voltage of the power source in a case where electric power is being supplied from the power source to the converter;
the turbocompressor apparatus performs a first decelerating operation in which an amplitude of the first alternating-current voltage vector is set equal to or smaller than a value that is R1 times the direct-current voltage in a case where supply of electric power from the power source to the converter is being cut off and where the amplitude of the first alternating-current voltage vector is equal to or larger than a first threshold amplitude; and
the first threshold amplitude is equal to or larger than an amplitude of the second alternating-current voltage vector in the normal operation, R1 is an upper limit value of a ratio of the amplitude of the first alternating-current voltage vector to the direct-current voltage obtained in a case where the first inverter operates in a linear region, and the linear region of the first inverter is an operation region in which the amplitude of the first alternating-current voltage vector linearly changes in theory relative to the direct-current voltage.

US Pat. No. 10,560,040

HARVESTING ENERGY FROM FLUID FLOW

Saudi Arabian Oil Company...

1. An elastic bluff body, comprising:an elastic mount with a central axis;
a conical bluff body with a central axis, the conical bluff body fixedly attached to the elastic mount, the central axis of the elastic mount and the central axis of the conical bluff body being aligned, the conical bluff body being configured to generate vortex shedding when the elastic mount orients the conical bluff body in a flow-line traverse to a fluid flow and vibrates in response to the vortex shedding, wherein the conical bluff body comprises a permanent magnet or electromagnet; and
a harvester coupled to the conical bluff body and aligned with the central axis of the conical bluff body, the harvester comprising a cylinder arranged outside of and aligned with the central axis of the conical bluff body, and a metallic coil circling a circumference of the cylinder, the harvester configured to generate power above a specified threshold in response to the vibration.

US Pat. No. 10,560,038

HIGH TEMPERATURE DOWNHOLE POWER GENERATING DEVICE

Saudi Arabian Oil Company...

1. A high temperature power generating device, the device comprising:a power generator including a first material of one polarity and a second material that is fixed in position relative to the first material and is of opposite polarity of the first material, wherein the first material is configured to be propelled toward the second material based on motion of the high temperature downhole power generator so that the two materials have a maximized point of contact to generate maximum power;
at least one electrode that is connected to the first material or second material;
a bridge rectifier connected to the at least one electrode to transform the power generated into direct current from alternating current;
a storage unit for storing the power generated by the power generator;
a first housing for housing the power generator, the electrode, and the bridge rectifier, wherein the first housing comprises a polymeric material; and
a second housing for housing the storage unit, wherein the second housing comprises a material selected from the group consisting of certain solids, transition metals, as well as high strength alloys and/or compounds of the transition metals, and high temperature dewars.

US Pat. No. 10,560,036

POWER CONVERSION DEVICE FOR RELIABLE CONTROL OF CIRCULATING CURRENT WHILE MAINTAINING VOLTAGE OF A CELL

MITSUBISHI ELECTRIC CORPO...

1. A power conversion device which converts power between a DC circuit and an AC circuit, the power conversion device comprising:a plurality of leg circuits which correspond to respective phases of the AC circuit and are connected in parallel between common first and second DC terminals,
each leg circuit including:
a plurality of converter cells cascaded to one another and each including an energy storage; and
at least one inductor connected in series to the plurality of converter cells,
each of a plurality of specified converter cells which are some of the plurality of converter cells included in each leg circuit including:
a capacitor as the energy storage;
first and second switching elements connected in parallel to the capacitor and connected in series to each other; and
third and fourth switching elements connected in parallel to the capacitor and connected in series to each other,
the capacitor being capable of being charged and discharging through a connection node of the first and second switching elements and a connection node of the third and fourth switching elements; and
a control device which controls operations of the plurality of converter cells included in each leg circuit,
the control device controlling operations of the first and second switching elements of each specified converter cell based on a circulating current which circulates through each leg circuit, wherein the first and the second switching elements are exclusively used to control the circulating current,
the control device controlling operations of the third and fourth switching elements of each specified converter cell based on a voltage of the capacitor of each specified converter cell, wherein the third and fourth switching elements are exclusively used to control a difference between a voltage of the cell capacitor and a command value thereof to zero.

US Pat. No. 10,560,033

SOLAR HYBRID SOLUTION FOR SINGLE PHASE STARTING CAPACITOR MOTOR APPLICATIONS

SunTech Drive, LLC, Boul...

1. A system comprising:an induction-type AC electric motor having a starting winding, and a run winding;
an AC input connection;
a multiphase variable frequency motor (VFD) drive having at least a first and a second phase output;
a switching apparatus having at least a first and a second position;
wherein with the switching apparatus in the first position, a first output of a variable frequency motor drive is coupled to the run winding of the AC electric motor, and a second output of the variable frequency motor drive is coupled to the start winding of the AC electric motor; and
with the switching apparatus in the second position, the run winding of the AC electric motor is coupled to the AC input connection and the start winding of the AC electric motor is coupled through a capacitor and start switch to the AC input connection;
wherein, with the switching apparatus in the first position, the second output of the VFD is configured to discontinue driving the start winding of the motor after the motor begins rotating.

US Pat. No. 10,560,031

BI-DIRECTIONAL DC TO DC SIGNAL CONVERSION USING OBSERVER BASED ESTIMATED CURRENT SENSOR

Hamilton Sundstrand Corpo...

1. A bi-directional DC to DC converter, comprising:a DC to DC conversion circuit; and
a controller operatively connected to the conversion circuit to control a voltage output of the conversion circuit, the controller including an observer based estimated current sensor module configured to simulate a physical current sensor by inputting an estimated output current feedback inner state signal ??o into a voltage output command feedback loop of the controller.

US Pat. No. 10,560,030

CABLE COMPENSATION CIRCUIT AND POWER SUPPLY INCLUDING THE SAME

SEMICONDUCTOR COMPONENTS ...

1. A compensation circuit for compensating for a voltage drop in a cable coupled between a power supply and a load, the compensation circuit comprising:a sensing resistive-capacitive (RC) filter including a first capacitor and configured to receive a voltage from an auxiliary winding of the power supply and generate a sense voltage by RC filtering the received voltage; and
an averaging filter including a second capacitor and configured to generate an average voltage by averaging the sense voltage,
wherein the power supply comprises a transformer including a primary winding, a secondary winding, and the auxiliary winding, a power switch coupled through the primary winding to an input voltage, a rectifying diode coupled between the secondary winding and the output voltage, and a feedback circuit comprising a shunt regulator having a reference end, the shunt regulator configured to control a sink current according to a voltage of the reference end,
wherein the compensation circuit further comprises a third resistor coupled between the average voltage and the reference end of the shunt regulator of the feedback circuit of the power supply, and
wherein the power supply uses the average voltage to control the power switch.

US Pat. No. 10,560,029

CONTROLLER FOR INCREASING EFFICIENCY OF A POWER CONVERTER AND A RELATED METHOD THEREOF

Leadtrend Technology Corp...

1. A controller for increasing efficiency of a power converter, the controller comprising:an enable signal generation unit electrically connected to a direct current (DC) input terminal of a primary side of the power converter through a high voltage pin of the controller, wherein the enable signal generation unit is used for generating an enable signal corresponding to a duty cycle of a gate control signal according to a DC input voltage of the DC input terminal and a feedback voltage corresponding to a secondary side of the power converter, and the feedback voltage corresponds to an output voltage of the secondary side of the power converter; and
a gate signal generation unit having two transistors in parallel, wherein a first terminal of a first transistor of the two transistors and a first terminal of a second transistor of the two transistors are coupled to ground, a second terminal of the first transistor is coupled to a gate pin of the controller through a switch comprised in the gate signal generation unit, a second terminal of the second transistor is directly coupled to the gate pin, and a control terminal of the first transistor and a control terminal of the second transistor receive a pulse width modulation signal;
wherein the gate signal generation unit utilizes the enable signal to control turning-on and turning-off of the switch to change a sink current flowing through the gate pin of the controller, wherein the gate pin is coupled to a power switch of the primary side of the power converter, and the gate signal generation unit is further used for generating a gate control signal to the power switch.

US Pat. No. 10,560,026

POWER CONVERSION EFFICIENCY USING VARIABLE SWITCHING FREQUENCY

SEMICONDUCTOR COMPONENTS ...

1. A power circuit controller, comprising:a voltage sense input;
a main switch output;
an active clamp switch output; and
the power circuit controller configured to:
sense a peak magnitude of a direct current (DC) voltage at the voltage sense input;
generate a main switch signal on the main switch output having an output frequency that varies between a first frequency and a second frequency based on the peak magnitude of the DC voltage at the voltage sense input, and wherein both the first frequency and the second frequency are non-zero; and
generate an active clamp signal on the active clamp switch output having the output frequency.

US Pat. No. 10,560,025

FREQUENCY HOPPING FOR REDUCING SWITCHING POWER CONVERTER NOISE

DIALOG SEMICONDUCTOR INC....

1. A switching power converter comprising:a power switch;
a controller configured to cycle the power switch at a first fixed switching frequency to produce a first peak current through the power switch responsive to an amplitude of a control signal being within a first output power range ending at a boundary control voltage value and to cycle the power switch at a second fixed switching frequency to produce a second peak current through the power switch responsive to the amplitude of the control signal being within a second output power range beginning at the boundary control voltage value, wherein a first ratio of the first peak current to the second peak current at a boundary between the first output power range and the second output power range is a function of a second ratio of the second fixed switching frequency to the first fixed switching frequency, and wherein the control signal is a filtered version of an error between a feedback signal and a reference signal.

US Pat. No. 10,560,023

MULTI-PHASE POWER REGULATOR

Texas Instruments Incorpo...

1. A circuit for use in system with a multi-phase power regulator to supply power to an electrical load, the multi-phase power regulator including a power stage including a first phase and a second phase, the circuit comprising:phase management circuitry to couple to the first phase and the second phase to control the first phase and the second phase;
a first comparator to couple to an output node of the multi-phase power regulator to compare a first output voltage level at the output node of the multi-phase power regulator to a first threshold value to produce a first comparison result; and
a second comparator to couple to the output node of the multi-phase power regulator to compare the first output voltage level to a second threshold value to produce a second comparison result, wherein the second threshold value is less than the first threshold value;
current detection circuitry to detect:
first electrical characteristics associated with providing a first amount of current to the load at the first output voltage level, the first electrical characteristics indicative of an increased current draw by the load; and
second electrical characteristics associated with providing a second amount of current to the load at the first output voltage level, the second electrical characteristics indicative of a decreased current draw by the load;
a load line to lower the first output voltage level based on an increase in current draw by the load; and
phase shedding circuitry coupled to the first comparator and the second comparator, and the phase management circuitry to control the phase management circuitry to activate or deactivate the second phase based at least partially on the first comparison result and the second comparison result.

US Pat. No. 10,560,022

SETTING OPERATING POINTS FOR CIRCUITS IN AN INTEGRATED CIRCUIT CHIP USING AN INTEGRATED VOLTAGE REGULATOR POWER LOSS MODEL

ADVANCED MICRO DEVICES, I...

1. An apparatus that controls voltages, comprising:an integrated circuit chip comprising a set of circuits;
an external voltage regulator separate from the integrated circuit chip;
a plurality of integrated voltage regulators fabricated on the integrated circuit chip, the external voltage regulator providing an output voltage that is received as an input voltage by each of the plurality of integrated voltage regulators, and each integrated voltage regulator of the plurality of integrated voltage regulators providing a local output voltage that is received as a local input voltage by a respective subset of circuits in the set of circuits; and
a controller that:
determines a first combination of operating points for the subsets of the circuits, the first combination of operating points comprising a respective operating point for each of the subsets of the circuits;
determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for the first combination of operating points;
determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits, the adjustment to the operating point compensating for an electrical power loss of the integrated voltage regulator that provides the local input voltage to the at least one of the subsets of the circuits; and
set an operating point of each of the subsets of the circuits to a respective operating point from the second combination of operating points.

US Pat. No. 10,560,021

DC-DC CONVERTER AND DISPLAY APPARATUS HAVING THE SAME

Samsung Display Co., Ltd....

1. A DC-DC converter comprising:a first switch;
a second switch connected to the first switch;
an input terminal for receiving an input voltage;
an output terminal for outputting an output voltage;
an inductor;
a mode selecting circuit configured to select a converting mode from one of at least a first converting mode and a second converting mode based on the input voltage; and
a controller configured to generate a first switching control signal for controlling the first switch based on the selected converting mode, and a second switching control signal for controlling the second switch based on the selected converting mode,
wherein the mode selecting circuit is configured to select the converting mode from one of at least the first converting mode, the second converting mode, and a third converting mode,
wherein, in the first converting mode, the first switch is configured to be repeatedly turned on and off in response to the first switching control signal, and the second switch is configured to be repeatedly turned on and off in response to the second switching control signal,
wherein, in the second converting mode, the first switch is configured to be repeatedly turned on and off in response to the first switching control signal, and the second switch is configured to maintain a turned off state in response to the second switching control signal,
wherein, in the third converting mode, the first switch is configured to be repeatedly turned on and off in response to the first switching control signal, and the second switch is configured to maintain a turned on state in response to the second switching control signal,
wherein in the third converting mode, the second switching control signal is the input voltage,
wherein the second switch is coupled between one end of the first switch and the output terminal, and
wherein the inductor is coupled between the input terminal and the first and second switches.

US Pat. No. 10,560,020

METHOD OF VOLTAGE DROP COMPENSATION ON A CABLE AND CORRESPONDING CIRCUIT

STMICROELECTRONICS (ALPS)...

1. A method for compensating a voltage drop on a cable connected between a source device and a receiver device, the method comprising:increasing, by the source device, a voltage on a channel configuration pin of the source device to a chosen reference voltage by increasing an offset current on the channel configuration pin of the source device;
storing the offset current in the source device as a stored offset current after increasing the voltage to the chosen reference voltage;
absorbing, by the source device, an absorption current originating from the channel configuration pin of the source device, the absorption current depending on the stored offset current and on the voltage drop; and
generating, by the source device, a compensated supply voltage on a power supply pin of the source device, the compensated supply voltage equal to a reference supply voltage increased by the voltage drop to within a first tolerance.

US Pat. No. 10,560,017

CHARGE PUMP, SWITCH DRIVER DEVICE, LIGHTING DEVICE, AND VEHICLE

Rohm Co., Ltd., Kyoto (J...

1. A charge pump comprising:a flying capacitor;
an output capacitor;
a switch group arranged to switch connection states of the capacitors so as to generate an output voltage from an input voltage; and
a feedback control unit arranged to adjust an interterminal voltage of the flying capacitor to a predetermined target value when charging the flying capacitor, wherein
the switch group includes:
a first switch connected between a first terminal of the flying capacitor and an input terminal of the input voltage,
a second switch connected between a second terminal of the flying capacitor and the input terminal of the input voltage,
a third switch connected between the first terminal of the flying capacitor and an output terminal of the output voltage,
a fourth switch connected between the second terminal of the flying capacitor and a ground terminal, and
a fifth switch connected between the first terminal of the flying capacitor and an input terminal of a power supply voltage, wherein
in a low input case where the input voltage is lower than the power supply voltage, the flying capacitor is charged using the power supply voltage,
in a high input case where the input voltage is higher than the power supply voltage, the flying capacitor is charged using the input voltage.

US Pat. No. 10,560,012

ZVS CONTROL CIRCUIT FOR USE IN A FLYBACK POWER CONVERTER

RICHTEK TECHNOLOGY CORPOR...

1. A zero voltage switching (ZVS) control circuit, configured to operably control a flyback power converter including a power transformer having a primary side and a secondary side, the ZVS control circuit comprising:a primary side controller circuit, configured to operably generate a switching signal according to a feedback signal, wherein the switching signal controls a power transformer through a power transistor at the primary side to generate an output voltage at the secondary side; and
a secondary side controller circuit, configured to operably generate the feedback signal, and generate an SR signal to control a synchronous rectifier transistor at the secondary side, wherein the SR signal includes an SR-control pulse and a ZVS pulse, wherein the SR-control pulse controls the synchronous rectifier transistor in response to a demagnetizing period of the power transformer, and wherein the ZVS pulse controls the power transformer through the synchronous rectifier transistor to determine a timing for starting the switching signal to achieve zero voltage switching for the power transistor;
wherein the secondary side controller circuit generates the ZVS pulse after a delay time from an end of a demagnetizing period of the power transformer, wherein within the demagnetizing period, the power transformer is substantially demagnetized, and the delay time is determined according to a time length of the demagnetizing period, wherein the delay time is increased as the time length of the demagnetizing period of the power transformer is decreased.

US Pat. No. 10,560,009

VIBRATION MOTOR

NIDEC SEIMITSU CORPORATIO...

1. A vibration motor comprising:a stationary portion including a casing and a coil;
a vibrating body including a weight and a magnet, the vibrating body being supported so as to be vibratable in one direction relative to the stationary portion;
an elastic member located between the stationary portion and the vibrating body; and
a top plate portion that is disposed above the vibrating body in an up-down direction that is perpendicular to the one direction, wherein
the magnet is disposed above the coil,
the top plate portion faces the magnet in the up-down direction,
the magnet includes a set of first magnets that generate magnetic forces that are opposite to each other in the up-down direction and one or more second magnets that are interposed between the first magnets and each generate a magnetic force in the one direction,
the weight includes a first weight portion that is disposed above the coil and a second weight portion whose lower surface is located below a lower surface of the first weight portion,
the second weight portion faces the coil in the one direction,
the stationary portion further includes a substrate,
the substrate includes a substrate body on which the coil is disposed and an extension portion that extends from the substrate body in the one direction toward an outside of the casing,
the second weight portion includes a groove that extends in the one direction and in which the extension portion is disposed,
the casing includes a base,
the substrate is disposed on the base, and
a relationship HA>HL>HB>HP is satisfied, where HA is a height from the base to the lower surface of the first weight portion, HB is a height from the base to the groove, HL is a height from the base to an upper surface of the coil, and HP is a height from the base to an upper surface of the substrate.

US Pat. No. 10,560,007

MOTOR

MABUCHI MOTOR CO., LTD., ...

1. A motor comprising:a cylindrical housing that houses a rotor;
a first member mounted to an opening of the housing; and
a second member sandwiching the first member as mounted between the second member and the housing, wherein
the housing includes, at an end of the housing that faces the second member, a first locking part that locks a first locked part of the second member, and
the second member is elastically deformed by the first locking part and locked to the housing accordingly and is configured such that a gap is formed between the second member and the housing when the second member is locked to the housing.

US Pat. No. 10,560,002

COOLANT FLOW DISTRIBUTION USING COATING MATERIALS

FORD GLOBAL TECHNOLOGIES,...

1. An electric machine comprising:a stator core, within a transaxle housing, having a channel-less outer surface portion;
one or more layers of an oleophobic or hydrophobic patterned coating defining boundaries wrapping around a perimeter of the stator core; and
one or more layers of an oleophilic or hydrophilic coating on the portion within the boundaries configured to direct coolant flow over the oleophilic or hydrophilic coating within the boundaries.

US Pat. No. 10,560,001

COOLING TOWER HAVING THERMALLY MANAGED MOTOR

Prime Datum Development C...

1. A cooling tower comprising:a cooling tower structure;
fill material supported by the cooling tower structure and configured to receive heated process fluid;
a motor mounted to the cooling tower structure, the motor comprising a casing and a rotatable shaft, the casing having an exterior surface and an interior, the motor being sealed to prevent fluids, moisture, foreign particles and contaminants from entering the casing, the motor further comprising at least one temperature sensor for outputting sensor signals that represent temperature;
a fan connected to the rotatable shaft of the motor, wherein rotation of the rotatable shaft rotates the fan thereby inducing an upward moving mass flow of cool air through the fill material;
a basin attached to the cooling tower structure for collecting cooled fluid;
a temperature-controlled fluid distribution system to distribute cooled fluid from the basin onto the motor to cause a transfer of heat from the casing of the motor to the fluid, the temperature-controlled fluid distribution system being responsive to the sensor signals and configured to distribute cooled fluid from the basin onto the motor when the sensor signals indicate a temperature that exceeds a predetermined threshold and to cease distributing the cooled fluid onto the motor when the sensor signals indicate a temperature that is below the predetermined threshold.

US Pat. No. 10,559,998

MOTOR AND DISK DRIVE APPARATUS

NIDEC CORPORATION, Kyoto...

1. A motor, comprising:a stationary unit including a stator, a base, and a flexible wiring substrate board;
a rotary unit including a rotor magnet; and
a bearing mechanism that supports the rotary unit so as to rotate with respect to the stationary unit about a center axis extending in an axial direction; wherein
the stator is positioned radially inward of the rotor magnet;
the base is positioned axially below the stator and the rotor magnet and includes a hole extending therethrough;
the hole is positioned in a region of the base, the region of the base has an axial height which varies at different locations within the region of the base;
the flexible wiring substrate board extends completely through the hole and supplies electric power to the stator;
the flexible wiring substrate board extends beneath both of the rotor magnet and the stator;
the stator includes at least one stator coil and the flexible wiring substrate board extends beneath a majority of an entire radial dimension of the at least one stator coil;
the flexible wiring substrate includes an electrically conductive solder portion on a lower surface thereof to cover a portion of a lead wire extending from a coil of the stator; and
at least a portion of the solder portion is positioned within an additional hole defined in the base.

US Pat. No. 10,559,997

BRUSH DEVICE, ELECTRIC MOTOR WITH BRUSH DEVICE, AND MANUFACTURING METHOD OF BRUSH DEVICE

DENSO CORPORATION, Kariy...

1. A brush device comprising:a positive side brush sub-assembly having a positive side brush for feeding a commutator, a positive side brush holder for holding the positive side brush, and a positive side plate to which the positive side brush holder is attached, and
a negative side brush sub-assembly having a negative side brush for feeding the commutator, a negative side brush holder for holding the negative side brush, and a negative side plate to which the negative side brush holder is attached, wherein
the positive side brush holder has a positive convex portion engaging with the negative side plate,
the negative side brush holder has a negative convex portion engaging with the positive side plate,
the positive side plate has a positive slit engaging with the negative convex portion,
the negative side plate has a negative slit engaging with the positive convex portion, and
the positive side brush sub-assembly and the negative side brush sub-assembly are combined with each other by the positive convex portion and the negative slit being engaged and the negative convex portion and the positive slit being engaged.

US Pat. No. 10,559,995

MOTOR HAVING A COVER MEMBER FOR GUIDING WATER DROPLETS AWAY FROM ROTARY ENCODER

FANUC CORPORATION, Yaman...

1. A motor comprising:a motor main body having a rotating shaft member; and
a rotary encoder, wherein
the rotary encoder has a cover member, and
an inner surface of the cover member has a first top surface formed having an inclined portion that is inclined relative to a horizontal direction so as to guide a droplet of water when the rotating shaft member is disposed to extend in a vertical direction, and a second top surface formed having an inclined portion that is inclined relative to a horizontal direction so as to guide a droplet of water when the rotating shaft member is disposed to extend in a horizontal direction,
wherein a groove for guiding a droplet of water is formed in the first top surface and/or the second top surface, the groove being linear and extending in a predetermined direction when viewing the first top surface and the second top surface from inside the cover member, and
a hygroscopic material is disposed to be bonded to the first top surface and the second top surface at the boundary between the first top surface and the second top surface of the inner surface of the cover member, and absorbs the droplets of water guided by the first top surface and the second top surface.

US Pat. No. 10,559,994

LINEAR VIBRATION MOTOR

MPLUS CO., LTD., Suwon-s...

1. A linear vibration motor (1) comprising:a casing (2) configured to have an internal space and to comprise a circular casing center extension part (21) which is disposed at a center and has a shape downward extended in multiple stages;
a bracket (3) coupled to a bottom of the casing (2) to form an external appearance of the linear vibration motor and configured to comprise a circular bracket center extension part (31) which is disposed at the center and has a shape upward extended in multiple stages;
a circular coil (4) configured to fix lateral surfaces of the casing center extension part (21) and the bracket center extension part (31) by coupling the casing center extension part (21) and the bracket center extension part (31);
an elastic body (5) configured to have one side fixed to one surface on an inside of the casing (2) and the other side coupled to a vibrator (7); and
an FPCB (6) fixed to one surface on a top of the bracket (3) and configured to electrically connect the coil and an external device.

US Pat. No. 10,559,990

STRUCTURES UTILIZING A STRUCTURED MAGNETIC MATERIAL AND METHODS FOR MAKING

Persimmon Technologies Co...

1. A motor, comprising:a stator comprising at least one core and an outer wall, the outer wall extending in an axial direction;
a coil wound on the at least one core of the stator such that an edge of the outer wall extending in the axial direction is below, even with, or extends beyond a surface of the coil facing in the axial direction and such that the outer wall extends radially beyond an outer edge of the coil;
a rotor having a rotor pole and being rotatably mounted relative to the stator;
at least one magnet disposed between the rotor and the stator; and
a conical air gap between the stator and the at least one magnet;
wherein a separation plane normal to an axis of rotation extends through the stator and the rotor, and wherein the coil, the at least one magnet, and the conical air gap are together configured to allow flux flow between the stator and the rotor in a three-dimensional flux pattern such that the flux flow does not cross the separation plane.

US Pat. No. 10,559,989

ROTOR CARRIER AND LOCKING DIAPHRAGM SPRING

11. A carrier hub of a hybrid drive module including a torque converter and an electric motor including a rotor, the carrier hub comprising:a carrier hub surface including a retention groove configured to interlock the carrier hub to one or more fingers of a diaphragm spring and inhibit rotation and axial movement of the diaphragm spring relative to the carrier hub, wherein the retention groove includes a first and second passageway connected by a third passageway, wherein the first, second, and third passageways extend in different directions to allow the finger to be translated along the retention groove in three different directions.

US Pat. No. 10,559,988

ROTOR FOR ROTARY ELECTRIC MACHINE

MITSUBISHI ELECTRIC CORPO...

1. A rotor for a rotary electric machine, comprising:a first rotor member; and
a second rotor member,
the first rotor member including a first core member and a first magnet group provided to the first core member,
the second rotor member including a second core member and a second magnet group provided to the second core member,
the first core member and the second core member being fixed to each other under a state of being aligned in an axial direction of the rotor,
the first magnet group and the second magnet group being adjacent to each other in the axial direction,
the first magnet group including a plurality of first magnets arrayed in a circumferential direction of the rotor,
the second magnet group including a plurality of second magnets arrayed in the circumferential direction,
the first magnet and the second magnet, which are adjacent to each other and have the same polarity, being shifted from each other in the circumferential direction so as to mutually receive a magnetic repulsive force in the circumferential direction,
one of the first core member and the second core member having a first recessed portion, and another of the first core member and the second core member having a first protruding portion to be engaged with the first recessed portion in the circumferential direction,
at least any one of the first core member and the second core member is formed as a core assembly member including a main body core block and a plurality of arc-shaped core blocks mounted to any one of an outer peripheral portion and an inner peripheral portion of the main body core block,
magnets included in the plurality of first magnets and the plurality of second magnets, which are provided to the core assembly member, are provided to the arc-shaped core blocks,
any one of the main body core block and the plurality of arc-shaped core blocks has a second recessed portion formed thereon, and another of the main body core block and the plurality of arc-shaped core blocks has a second protruding portion formed thereon to be engaged with the second recessed portion in a direction in which the first protruding portion is brought into engagement with the first recessed portion,
the second recessed portion has a second recessed-portion engagement portion having a width which continuously decreases in a direction in which the second protruding portion is brought into engagement with the second recessed portion, and
the second protruding portion has a second protruding-portion engagement portion to be fitted into the second recessed-portion engagement portion.

US Pat. No. 10,559,987

ELECTROMAGNETIC ARMATURE FOR ROTATING ELECTRICAL MACHINE AND METHOD FOR MANUFACTURING SAME

Francecol Technology, Sa...

1. An electromagnetic armature comprising an electromagnetic yoke having a cylindrical surface with an axis z which is designed to be opposite an air gap surface, the cylindrical surface being known as an interaction surface, a plurality of teeth forming magnetic poles, the teeth being associated in a projecting manner with the interaction surface in the direction of the air gap surface, and disposed spaced all around the yoke, characterized in that each tooth comprises a recess arranged in one of the faces of the tooth on a so-called polar plane orthogonal to the direction z, the recess being designed to receive a winding, and in that said teeth are arranged on the yoke such that the recesses are disposed alternately on both sides of the polar median plane which passes through the middle of the yoke.

US Pat. No. 10,559,986

SYSTEM, METHOD, AND APPARATUS FOR WIRELESS CHARGING

CAPITAL ONE SERVICES, LLC...

1. An electronic transaction card comprising:a Near-Field Communication (NFC) antenna;
an energy storage component; and
a processor configured to:
send and receive data packets to and from a terminal system to conduct a transaction using contactless payment technology, wherein the data packets include user authentication information to authenticate payment;
transmit, via the NFC antenna, an advertising packet from the electronic transaction card to a mobile power receiving device;
receive, via the NFC antenna, a response to the advertising packet from the mobile power receiving device, wherein the response indicates a first frequency of energy transmission via the NFC antenna;
alter the first frequency of energy transmission via the NFC antenna to a second frequency of energy transmission via the NFC antenna based on a distance between the electronic transaction card and the mobile power receiving device; and
broadcast, via the NFC antenna, a signal to the mobile power receiving device using the second frequency and configured to charge the mobile power receiving device via inductive charging.

US Pat. No. 10,559,985

WIRELESS POWER TRANSFER SYSTEM, CONTROL METHOD OF WIRELESS POWER TRANSFER SYSTEM, WIRELESS POWER TRANSMITTING APPARATUS, CONTROL METHOD OF WIRELESS POWER TRANSMITTING APPARATUS, AND STORAGE MEDIUM

CANON KABUSHIKI KAISHA, ...

1. A power transmitting apparatus comprising:a member configured to mount a power receiving apparatus;
a power transmitting unit configured to wirelessly transmit power to the power receiving apparatus mounted on the member;
a communication unit configured to communicate with the power receiving apparatus mounted on the member; and
a control unit configured to control the power transmitting unit and the communication unit,
wherein the communication unit transmits information to the power receiving apparatus mounted on the member, thereby the power receiving apparatus displays, based on the information transmitted by the communication unit, a charging message representing a charging speed.

US Pat. No. 10,559,984

POWER TRANSFER SYSTEM, AND POWER RECEIVING APPARATUS, POWER TRANSMITTING APPARATUS, AND CONTROL METHOD THEREOF

CANON KABUSHIKI KAISHA, ...

1. A power receiving apparatus comprising:a first antenna for wirelessly receiving power from a power transmitting apparatus and for performing communication;
a second antenna for performing communication;
one or more memories storing instructions; and
one or more processors executing the instructions to:
perform communication regarding identification information, with the power transmitting apparatus, via the first antenna;
transmit a first signal via the second antenna;
receive a second signal indicating a request for communication via the second antenna after transmitting the first signal;
determine whether a transmission source of the second signal is the power transmitting apparatus with which the identification information is communicated via the first antenna based on identification information included in the second signal;
control to perform communication regarding power receiving control via the second antenna, based on determining the transmission source of the second signal is the power transmitting apparatus with which the identification information is communicated via the first antenna, with the transmission source of the second signal, and control not to perform communication regarding power receiving control via the second antenna, based on determining the transmission source of the second signal is not the power transmitting apparatus with which the identification information is communicated via the first antenna, with the transmission source of the second signal.

US Pat. No. 10,559,982

EFFICIENT ANTENNAS CONFIGURATIONS FOR USE IN WIRELESS COMMUNICATIONS AND WIRELESS POWER TRANSMISSION SYSTEMS

Ossia Inc., Bellevue, WA...

1. A transmitter device, comprising:multiple antennas;
a dielectric material in proximity to the multiple antennas, the dielectric material having disposed therein a non-layered distribution of a high refractive index material and a low refractive index material; and
multiple scattering elements embedded in the dielectric material,
wherein one or more of the multiple scattering elements are configured to increase a number of radiating elements per volume in the transmitter device by creating complex waveforms with increased diversity when excited by one or more signals emitted by the multiple antennas.

US Pat. No. 10,559,981

POWER LINKS AND METHODS FOR IMPROVED EFFICIENCY

Daxsonics Ultrasound Inc....

1. A method of improving transfer efficiency in an ultrasonic power link having a send transducer and configured to transmit at a transmit frequency, in which the send transducer has a fixed resonant global best operating frequency characteristic to the send transducer, the method comprising detecting changes in impedance phase as seen by the send transducer by sweeping the transmit frequency over a range of frequencies, identifying a target frequency at which the impedance phase is at a local minimum that is closest in value to the global best operating frequency, and adjusting the transmit frequency to the target frequency.

US Pat. No. 10,559,980

SIGNALING IN WIRELESS POWER SYSTEMS

WiTricity Corporation, W...

1. A source for providing power wirelessly to, or receiving power wireless from, a vehicle, the source comprising:a source resonator capable of generating a first electromagnetic field to provide power wirelessly to a device resonator configured to be mounted to the vehicle, and to receive power wirelessly via a second electromagnetic field generated by the device resonator;
power and control circuitry coupled to the source resonator and configured to control a direction of flow of the power, including a first direction of flow via the first electromagnetic field during a first time period and a second direction of flow via the second electromagnetic field during a second time period, the power and control circuitry comprising a processor configured to monitor a state of the power and control circuitry corresponding to the direction of flow; and
a user interface coupled to the power and control circuitry and configured to report information based on the monitored state of the power and control circuitry.

US Pat. No. 10,559,979

CHARGING RECHARGEABLE APPARATUS

Nokia Technologies Oy, E...

9. A method comprising:accessing a trigger event comprising a battery level threshold of a rechargeable apparatus;
linking the rechargeable apparatus with a charging apparatus for wireless communication;
determining that the trigger event has occurred and the rechargeable apparatus is outside of a charging range of the charging apparatus;
in response to a determination that the trigger event has occurred and that the rechargeable apparatus is outside of the charging range of the charging apparatus, causing transmission of a wireless communication from the rechargeable apparatus to the charging apparatus;
causing an alert associated with the rechargeable apparatus to be provided by the charging apparatus; and
in an instance the rechargeable apparatus is positioned within the charging range of the charging apparatus, causing the provision of the alert associated with the rechargeable apparatus to be stopped.

US Pat. No. 10,559,976

SYSTEM, METHOD, AND APPARATUS FOR ELECTRIC POWER GRID AND NETWORK MANAGEMENT OF GRID ELEMENTS

CAUSAM ENERGY, INC., Ral...

1. A system for electric power grid management and communication, comprising:at least one grid element constructed and configured in network-based communication with a server via at least one coordinator;
wherein the at least one coordinator is operable to register and introduce the at least one grid element to an electric power grid;
wherein the at least one grid element is transformed into at least one active grid element automatically and/or autonomously upon registration with the at least one coordinator, wherein a security interface is associated with the at least one active grid element, wherein the at least one active grid element is operable to receive security system messages from at least one remotely-located security system via the security interface, wherein the security interface is standards-based or determined by a governing entity that regulates grid operations for utilities, market participants or grid operators;
wherein the at least one active grid element is operable to send and receive messages to and from the server via the at least one coordinator;
wherein the messages have a deliver priority based on virtual private networks, independent identifying addresses, and/or manufacturers specific identifying codes;
wherein the at least one active grid element has a unique grid element identifier which is a combination of an Internet Protocol version 6 (IPv6) address, an international manufacturer equipment identifier (IMEI), and electronic serial numbers or a Media Access Control (MAC) address;
wherein the at least one coordinator is operable to match and prioritize the at least one active grid element;
wherein the at least one coordinator is operable to provide a priority flag on the messages;
wherein the at least one coordinator is operable to track, based on revenue grade metrology, an amount of power supply available for the electric power grid or a curtailment power available from the at least one active grid element; and
wherein the at least one active grid element is operable to actively participate in the electric power grid, and wherein the actively participating is selected from the group consisting of consuming electric power from the electric power grid, supplying power to the electric power grid, and curtailing power consumption from the electric power grid.

US Pat. No. 10,559,975

SYSTEM AND METHOD FOR DISTRIBUTED GRID CONTROL WITH SUB-CYCLIC LOCAL RESPONSE CAPABILITY

Smart Wires Inc., Union ...

1. A system for hierarchical monitoring and control for a high-voltage power grid comprising:i) a plurality of high-voltage transmission lines carrying power from generation locations to distribution centers;
ii) a plurality of impedance injection modules distributed over, and coupled to, the high-voltage transmission lines of the power grid, each impedance injection module coupled to only one high voltage transmission line of the power grid, and comprises:
a controller that senses disturbances on the high-voltage transmission line and reacts by generating and injecting inductive and/or capacitive impedances of appropriate magnitude onto the high-voltage transmission line via an injection transformer coupled to the high-voltage transmission line; and
a transceiver for high-speed communication with other impedance injection modules within a local group of impedance injection modules to enable coordinated response of the other impedance injection modules within the respective local group of impedance injection modules to disturbances on the high-voltage transmission line;
iii) a group of local centers, each local center within the group of local centers having a high-speed transceiver for high-speed communication with impedance injection modules within a respective local group of impedance injection modules and with other local centers to enable coordinated response of all impedance injection modules associated with that group of local centers; and
iv) a communication link to and from a system utility, at each local center, for communication at a lower speed than the high-speed communication between impedance injection modules and between impedance injection modules and local centers.

US Pat. No. 10,559,974

CONSTANT POWER OUTPUT FROM EMERGENCY BATTERY PACKS

Eaton Intelligent Power L...

1. An electrical system comprising:a power supply that provides primary power;
an electrical device comprising at least one electrical load, wherein the electrical device is coupled to the power supply, wherein the at least one electrical load operates when the electrical device receives the primary power;
an energy storage unit comprising at least one energy storage device, wherein the at least one energy storage device charges using the primary power; and
a controller that determines an initial charging period during which the at least one energy storage device is charged using a constant supply of the primary power, wherein the controller changes the constant supply of the primary power to a trickle charge of the primary power at the end of the initial charging period to maintain a minimum charge level of the at least one energy storage device,
wherein the at least one electrical load receives reserve power from the energy storage unit when the power supply ceases providing the primary power and the trickle charge,
wherein the controller further causes the reserve power delivered by the energy storage unit to be substantially constant over time,
wherein the energy storage unit comprises a boost converter,
wherein the reserve power is less than the primary power but greater than a minimum threshold value.

US Pat. No. 10,559,973

ELECTRONIC DEVICE AND POWER SUPPLY METHOD THEREOF

Wistron Corporation, New...

1. An electronic device, comprising:an auxiliary power supply device;
a detachable power supply device; and
a control circuit, coupled to a power supply terminal, wherein the power supply terminal is coupled to a system load, and the control circuit comprises:
a change-over switch, having a first terminal coupled to the power supply terminal and a second terminal coupled to a supply terminal of the auxiliary power supply device;
a first switch, having a first terminal coupled to a control terminal of the change-over switch, and a control terminal of the first switch being coupled to the supply terminal of the detachable power supply device when the detachable power supply device is assembled to the electronic device; and
a second switch, having a first terminal coupled to the control terminal of the change-over switch and a control terminal coupled to the power supply terminal, wherein
when the detachable power supply device is assembled to the electronic device, the first switch is turned on to turn on the change-over switch, the second switch maintains the change-over switch in a conducting state, and the detachable power supplies power to the system load;
wherein when the electronic device is not turned on and the detachable power supply is removed from the electronic device, the change-over switch is not in a conducting state, and the control circuit does not turn on the electronic device by using the auxiliary power supply device, and
when the electronic device is in an on state and the detachable power supply is removed from the electronic device, the changer-over switch is in the conducting state, and the second switch of the control circuit is continuously turned on to maintain the change-over switch in a conducting state, so as to keep supplying power to the electronic device by using the auxiliary power supply device.

US Pat. No. 10,559,968

CHARGE/DISCHARGE CONTROL CIRCUIT AND BATTERY APPARATUS

ABLIC INC., Chiba (JP)

1. A charge/discharge control circuit comprising:a first power supply terminal connected to a first electrode of a secondary battery;
a second power supply terminal connected to a second electrode of the secondary battery;
a discharge control terminal connected to a gate of a discharge control field effect transistor (FET) which controls discharging of the secondary battery;
a discharge control output circuit configured to output a discharge control signal to the discharge control terminal; and
a control circuit configured to control the discharge control output circuit,
the discharge control output circuit comprising:
a first clamp voltage output circuit configured to output a first clamp voltage lower than a voltage of the first power supply terminal to the discharge control terminal to turn on the discharge control FET when the voltage of the first power supply terminal is higher than a first prescribed voltage, and
a first power supply voltage output circuit configured to output the voltage of the first power supply terminal to the discharge control terminal to turn on the discharge control FET when the voltage of the first power supply terminal is equal to or less than the first prescribed voltage.

US Pat. No. 10,559,966

INFORMATION DISPLAYING METHOD AND INFORMATION DISPLAYING DEVICE

PANASONIC INTELLECTUAL PR...

1. A method for displaying information on a display, comprising:receiving a request to display, on the display, information indicating whether each of a plurality of battery packs associated with the display, is mounted on a device of a plurality of devices associated with the display, each of the plurality of battery packs being mountable on the plurality of devices; and
in response to the request, displaying, on a monitor of the display, information indicating whether or not a battery pack of the plurality of battery packs associated with the display is mounted on each device of the plurality of devices associated with the display,
wherein, in the displaying, a first image is displayed in a different manner from a second image, the first image indicating a mounted state of a battery pack on a device of the plurality of devices associated with the display, the second image indicating an unmounted state of a battery pack on a device of the plurality of devices associated with the display.

US Pat. No. 10,559,965

DISPLAY ASSEMBLY HAVING MULTIPLE CHARGING PORTS

MANUFACTURING RESOURCES I...

1. An electronic display assembly comprising:a housing;
a frame having a front perimeter and a rear perimeter, wherein said frame is configured to receive the housing;
a first and second gasket located along the front perimeter and the rear perimeter, respectively, of said frame;
a pass-through device located in said housing and configured to accept one or more utility lines;
a first and second electronic display subassemblies mounted to said frame in a back to back arrangement, wherein each of said first and second electronic display subassemblies comprises:
a transparent layer;
an electronic display layer;
a hinging device configured to permit the electronic display subassembly to rotate between an opened position and a closed position; and
a gap defined by the space between the transparent layer and the electronic display layer;
a substantially sealed closed loop pathway surrounding each of said one or more electronic display subassemblies, wherein said closed loop pathway comprises:
the gap of each respective electronic display subassembly; and
a common cavity located in the space between the first and second electronic display subassemblies and the frame;
a plate positioned within the cavity between and substantially parallel to the rear surfaces of the electronic display subassemblies, wherein said plate is configured to receive at least some of said peripheral devices;
an open loop pathway configured to permit ambient air to pass through said housing and thermally interact with said closed loop pathway without mixing with circulating gas traveling through said closed loop pathway; and
at least two peripheral devices located within said housing, wherein one of said peripheral devices comprises a charging subassembly, and at least one other of said peripheral devices is selected from the group consisting of: a camera, a touchscreen, an additional electronic display, video communications equipment, audio communications equipment, and an emergency notification subassembly.

US Pat. No. 10,559,964

MOBILE TERMINAL AND BATTERY CHARGING METHOD THEREFOR

LG ELECTRONICS INC., Seo...

1. A mobile terminal, comprising:a terminal body comprising a battery;
an adaptor connector formed at one side surface of the terminal body and to which a power supply adaptor is connected;
a plurality of charging units configured to charge the battery between the adaptor connector and the battery; and
a controller configured to generate a control signal for controlling each of the plurality of charging units,
wherein any one of the plurality of charging units is configured to:
detect a level of a voltage of the battery,
compare the voltage of the battery with first to third threshold voltages, and
output first battery voltage data to the controller when the voltage of the battery is lower than the first threshold voltage, output second battery voltage data to the controller when the voltage of the battery is equal to or larger than the first threshold voltage and is lower than the second threshold voltage, and output third battery voltage data to the controller when the voltage of the battery is equal to or larger than the second threshold voltage and is lower than the third threshold voltage.

US Pat. No. 10,559,960

APPARATUS, DEVICE AND COMPUTER IMPLEMENTED METHOD FOR CONTROLLING POWER PLANT SYSTEM

GREENSMITH ENERGY MANAGEM...

1. A computer implemented method for controlling a power plant system, the power plant system including a photovoltaic power source configured to provide photovoltaic DC power to a photovoltaic DC bus, the photovoltaic power source including an inverter including a direct current (DC) power input operationally connected to the photovoltaic DC bus to receive photovoltaic DC power, and an alternating current (AC) power output for supplying AC power to an AC system, a DC-to-DC converter including a first direct current (DC) port to be operationally connected to the photovoltaic DC bus in parallel with the photovoltaic power source, an energy storage and an energy storage manager operationally connected to a second direct current (DC) port of the DC-to-DC converter, the method for controlling the power plant system comprising:receiving a target value for the AC power to be supplied by the inverter;
receiving weather forecast information, energy storage status information and photovoltaic power source parameters;
generating forecasted energy flow information for the photovoltaic power source based on the weather information and the photovoltaic power source parameters;
comparing the forecasted energy flow information and the energy storage status information; and
adjusting the target value for the AC power based on the comparison.

US Pat. No. 10,559,959

MULTI-GENERATOR POWER PLANT ARRANGEMENT, ENERGY SUPPLY NETWORK HAVING A MULTI-GENERATOR POWER PLANT ARRANGEMENT AND METHOD FOR DISTRIBUTING REACTIVE POWER GENERATION IN A MULTI-GENERATOR POWER PLANT ARRANGEMENT

1. A multi-generator power plant arrangement, comprising:a network feeding-in point, which is electrically coupled to an energy supply network;
a plurality of generators, which are in each case electrically coupled to the network feeding-in point and are designed to provide a reactive power in dependence on a first control variable, wherein at least one generator of the plurality of generators is a grid-forming generator, which is designed to provide an output voltage at a specified amplitude and a specified frequency or phase on a basis of a second control variable, wherein the reactive power to be provided by the plurality of generators is divided among the plurality of generators using a predetermined ratio or predetermined rules such that each respective generator of the plurality of generators has a designated reactive power to be fed in; and
a control device, which is designed to calculate a respective second control variable for the output voltage of the at least one grid-forming generator by using the designated reactive power to be fed in by a respective grid-forming generator of the plurality of generators, and to transmit the calculated respective second control variable to the respective grid-forming generator of the plurality of generators.

US Pat. No. 10,559,958

METHOD, CONTROLLER, AND NETWORK FOR CONTROLLING DEVICES IN POWER DISTRIBUTION NETWORK

Upside Energy Ltd., Ches...

1. A method of controlling a plurality of power units in a power distribution network (PDN), comprising:a) receiving one or more requests to increase or decrease the power drawn from, or the power supplied to, the PDN;
b) determining, based on aggregated power and/or energy data regarding the plurality of power units, and the one or more requests, one or more parameters defining properties of power units to be controlled in response to the one or more requests;
c) receiving status updates from the plurality of power units, each status update comprising information about the properties of the power unit that sent the status update; and for each status update determining, based on the received information and the determined parameters, whether the properties of the power unit that sent the status update fulfil the determined parameters; and if the properties of the power unit fulfil the determined parameters, controlling the power unit that sent the status update to change the amount of power drawn from or supplied to the PDN.

US Pat. No. 10,559,956

LOAD CONTROL DEVICE HAVING A REDUCED LEAKAGE THROUGH GROUND

Lutron Technology Company...

1. A load control device for controlling power delivered from an AC power source to an electrical device, the load control device comprising:a first hot detect circuit configured to generate a first hot-detect signal;
a second hot detect circuit configured to generate a second hot-detect signal;
a first switching circuit electrically coupled between the second hot detect circuit and a connection, the connection adapted to be electrically coupled to earth ground or a neutral side of the AC power source; and
a control circuit configured to receive the first hot-detect signal and the second hot-detect signal, configured to render the first switching circuit conductive and non-conductive, and configured to determine whether the first hot-detect signal and the second hot-detect signal are in phase;
wherein, when the control circuit determines that the first hot-detect signal and the second hot-detect signal are in phase, the control circuit is configured to render the first switching circuit non-conductive; and
wherein, when the control circuit determines that the first hot-detect signal and the second hot-detect signal are out of phase, the control circuit is configured to render the first switching circuit conductive.

US Pat. No. 10,559,954

METHODS AND APPARATUS FOR VOLTAGE AND CURRENT CALIBRATION

SEMICONDUCTOR COMPONENTS ...

1. A calibration circuit, comprising:a battery pack comprising a negative pack terminal; and
an intermediate node;
a first protection IC coupled to a first transistor, wherein the first transistor is coupled between the negative pack terminal and the intermediate node;
a second protection IC coupled in parallel with the first protection IC and coupled to a second transistor;
a power source adapted to be coupled in parallel with the first and second protection ICs; and
a current source adapted to be coupled between the negative pack terminal and the intermediate node;
wherein:
the intermediate node is positioned between the first transistor and the second transistor; and
the power source is configured to provide a current to the first protection IC through a first current loop.

US Pat. No. 10,559,953

REDUNDANT AND FAULT-TOLERANT POWER DISTRIBUTION SYSTEM HAVING AN INTEGRATED COMMUNICATION NETWORK

Applied Invention, LLC, ...

1. A power distribution system having an integrated communication network, comprising:a plurality of nodes, wherein each of the nodes includes:
a power port and an associated port monitor;
a load port and an associated port monitor; and
a processing element;
wherein the port monitors associated with the power port and the load port are connected to the processing element, and include a current monitor for measuring current flowing into or out of the corresponding port;
a topology that enables current to flow bi-directionally between the nodes; and
a communication link for conducting data bi-directionally between the nodes;
wherein data passed on the communication link is used for any of:
enabling or disabling any of:
a power source connected to a particular power port at a corresponding node, or
a device connected to a particular load port at a corresponding node.

US Pat. No. 10,559,948

CASING, ELECTRICAL CONNECTION BOX, AND WIRE HARNESS

YAZAKI CORPORATION, Toky...

1. A casing comprising:a frame peripheral wall on which an opening portion is formed at an edge;
a cover that covers the opening portion by rotational movement; and
a packing that is assembled in a packing groove to be formed in the cover and is pressed against the edge during the rotational movement,
wherein a position adjusting portion for adjusting a position of the packing groove with respect to the edge is formed on an inner surface of the frame peripheral wall.

US Pat. No. 10,559,944

SPARK PLUG FOR INTERNAL COMBUSTION ENGINE

DENSO CORPORATION, Kariy...

1. A spark plug for an internal combustion engine comprising:a cylindrical housing;
a cylindrical insulator held inside the housing;
a center electrode held inside the insulator so that a tip end portion protrudes;
a ground electrode forming a spark discharge gap between the center electrode and the ground electrode; and
a conductive glass filled in the insulator so as to be located at a base end side of the center electrode, wherein
the center electrode has a locking portion locked from the base end side to a step portion formed on an inner peripheral surface of the insulator, and an electrode head closer to the base end side than the locking portion is;
the electrode head has a base end surface on which a concave portion is partially formed; and
the concave contour, which is an outer peripheral contour of the concave portion when viewed in a plug axis direction, forms a closed curve which is spaced apart from a head contour, which is an outer peripheral contour of the base end surface of the electrode head, and surrounds the center axis of the center electrode, and
the concave contour has outward portions each protruding toward the head contour and four inward portions each protruding toward the center axis of the center electrode, and wherein
the distance between the concave contour and the head contour is 0.1 mm or more; and
the four inward portions each has an inwardly curved shape protruding toward the center axis.

US Pat. No. 10,559,943

LASER ASSEMBLY WITH SPECTRAL BEAM COMBINING

DAYLIGHT SOLUTIONS, INC.,...

1. A laser assembly that generates an assembly output beam, the laser assembly comprising:a laser subassembly that emits a plurality of spaced apart, substantially parallel laser beams;
a beam adjuster positioned in a path of the laser beams, the beam adjuster adjusting the spacing between the plurality of laser beams;
a transform lens positioned in a path of the laser beams, the transform lens collimating the laser beams and directing the laser beams to spatially overlap at a focal plane of the transform lens;
a wavelength selective beam combiner positioned at the focal plane that combines the lasers beams to provide a combination beam that is directed along a combination axis; and
an output coupler positioned on the combination axis that redirects at least a portion of the combination beam back to the beam combiner as a redirected beam, and transmits a portion of the combination beam as the assembly output beam.

US Pat. No. 10,559,942

LASER DEVICE AND INTERNAL COMBUSTION ENGINE

Ricoh Company, Ltd., Tok...

1. A laser device, comprising:a light source configured to emit light;
an optical system configured to concentrate the light emitted from the light source;
a housing configured to accommodate the optical system; and
a window disposed to the housing, to which the light passed through the optical system is incident, wherein the window includes
an optical window having an exit plane through which the light exits from the optical system, and having a side surface,
an optical window holding member configured to hold the optical window,
a joint between the side surface of the optical window and the optical window holding member to join the optical window to the optical window holding member, and
a protective layer disposed on a surface of the joint, on a side where the light is emitted from the window, wherein the protective layer is a coating.

US Pat. No. 10,559,941

SMALL FORM FACTOR TRANSMITTING DEVICE

INPHI CORPORATION, Santa...

1. A method of implementing a photonic transceiver in a network system comprising:packaging a photonic transceiver in a case with two transmitter devices mounted side-by-side on a PCB board and respectively coupled to a silicon photonics chip, the case comprising a first opening at a front end of the PCB board for mounting an optical input port and an optical output port respectively connected to the silicon photonics chip via optical fibers, and a second opening at a back end for the PCB board with multiple metallic stripes formed thereof as an electrical connector;
plugging the electrical connector to an electrical node of a communication network; and
connecting a pair of external optical fibers respectively to the optical input port and the optical output port, the pair of external optical fibers being connected respectively to an input path for providing incoming optical signals and output path for transmitting optical signals in the communication network,
wherein packaging the photonic transceiver comprises:
providing a base member comprising a planar part extended to an assembling part;
mounting a thermoelectric cooler module, a transmitter module, and an optical coupling lens assembly on a top surface of the planar part;
disposing an optical input port and an optical output port near the first end of the PCB board;
disposing a circuit board bended in step-shape with a first end region sitting on a top surface of the planar part and a second end region being a raised level, the first end region comprising multiple electrical connection patches respectively connected to the thermoelectric module and the transmitter module, the second end region comprising an electrical port for external connection;
disposing a cover member to a fixed position over the planar part to at least cover the thermoelectric module, the transmitter module, the optical coupling lens assembly, and the first end region of the circuit board;
assembling a cylindrical member to the assembling part, the cylindrical member enclosing an isolator aligned to the optical coupling lens assembly along its axial line and connected to a first optical fiber to output optical signal from the transmitter module; and
mounting the base member on the PCB board.

US Pat. No. 10,559,939

FACET ON A GALLIUM AND NITROGEN CONTAINING LASER DIODE

Soraa Laser Diode, Inc., ...

1. A laser device, comprising:a substrate having a surface;
a gallium and nitrogen containing cavity region overlying the surface, the gallium and nitrogen containing cavity region characterized by a first end and a second end, the first end comprising a first etched facet and the second end comprising a second etched facet; and
a passivation layer comprising a polycrystalline layer of Al2O3 directly contacting the first etched facet, wherein the passivation layer is heteroepitaxial and has a crystalline orientation of the first etched facet, and an interface between the passivation layer and the first etched facet is substantially contaminant free.

US Pat. No. 10,559,938

LASER SYSTEM FOR TISSUE ABLATION

Fotona d.o.o., Ljubljana...

1. A laser system for ablating a material such that a debris cloud of ablated particles of the material will form above the ablated material, comprising:a pump,
a laser, and
a controller,
wherein the controller is configured to control the laser system for pulsed operation so that individual laser pulses of a temporally limited pulse duration are generated, and
wherein the controller is configured to modulate the pump such that
(1) the pulses have an intensity that oscillates between maximum values and minimum values during the pulse duration, wherein the laser pulse comprises a plurality of intensity maxima Imax which occur at times {Ti, i=1, N}; and a plurality of intensity minima Imin which occur at times {tk, k=1, . . . (N?1)}, wherein the intensity of the pulse does not vanish at the intensity minima, and wherein an average modulation period TM of the pulse is defined as a mean value of time differences |Ti+1?Ti| between successive intensity maxima,
wherein the intensity oscillations of the laser pulse induce oscillations of a size of the debris cloud so that, during the pulse duration (T0), there are at least two maxima of the size of the debris cloud which occur at times {Tj, j=1, M} and which are located in between two intensity maxima of the laser pulse, and wherein an oscillation of the size of the debris cloud has a rise time tR and a decay time tD; and
(2) the average modulation period TM of the pulse is greater or equal to a sum of a rise time tR and a decay time tD of an oscillation of the debris cloud so that at least 70 percent of the maxima of the size of the debris cloud occurs near an intensity minimum of the pulse such that, for at least 70 percent of the maxima of the size of the debris cloud, the intensity of the pulse I(Tj) at the time of the maximum of the size of the debris cloud is smaller than Imin(tk)+0.5×[Imax(Ti)?Imin(tk)], wherein Imin(tk) is the intensity minimum of the pulse which is closest to the maximum of the size of the debris cloud at time Tj and Imax(Ti) is the intensity maximum of the pulse which is closest to the maximum of the size of the debris cloud at time Tj.

US Pat. No. 10,559,933

MANUAL DISCONNECT WITH CONNECTOR POSITION ASSURANCE ASSEMBLY

Lear Corporation, Southf...

1. A manual disconnect for an electric circuit comprising:a base including primary terminals and an interlock connector;
a plug assembly including fuse terminals and an interlock resistor assembly, the plug assembly adapted to be moved relative to the base between a disconnected position, wherein the fuse terminals are not engaged with respective primary terminals, a primary circuit engaged position, wherein the fuse terminals are engaged with respective primary terminals, and an interlock position, wherein the interlock connector is engaged with the interlock resistor assembly; and
a connector position assurance assembly including a connector position assurance button movable relative to the plug assembly between a pre-lock position and an assurance position, wherein the connector position assurance assembly prevents the plug assembly from rotating relative to the base;
wherein the plug assembly is adapted to be moved in an insertion direction relative to the base to move the plug assembly from the disconnected position to the primary circuit engaged position, and the plug assembly is adapted to be rotated about an axis relative to the base to move the plug assembly from the primary circuit engaged position to the interlock position.

US Pat. No. 10,559,931

HIGH CIRCUIT COUNT ELECTRICAL CONNECTOR

Ford Global Technologies,...

1. An electrical connector comprising: a plurality of contact traces extending along a circumference of a tapered post, on a plurality of respective planes perpendicular to a post axis; and a tapered cup positioned over the tapered post, having a plurality of inward facing terminal contacts corresponding to the plurality of contact traces, wherein the terminal contacts are configured to maintain contact as the tapered cup rotates about the post axis, wherein the tapered post comprises a plurality of channels corresponding to a number of contact traces on the plurality of respective planes, wherein the plurality of channels are positioned on an outside surface of the tapered post and configured to align wiring coupled to the plurality of contact traces, wherein the outside surface corresponds to an outer circumference of the tapered post, and wherein a first plane of the plurality of respective planes comprises a different number of contact traces than a second plane of the plurality of respective planes.

US Pat. No. 10,559,930

INTERCONNECTION SYSTEM

FOXCONN (KUNSHAN) COMPUTE...

1. An electrical interconnection system comprising:a periphery side comprising:
a first printed circuit board;
a plurality of cages mounted on the first printed circuit board, a plurality of cavities formed in the corresponding cages for receiving a plurality of modules therein, respectively;
a plurality of cable receptacle connectors located at rear portions of said receiving cavities, respectively;
a system side comprising:
a second printed circuit board;
an IC chip mounted on the second printed circuit board;
a plurality of board-mount receptacle connectors mounted upon the second printed circuit board; and
a plurality of cables connected between the cable receptacle connectors and the board-mount receptacle connectors; wherein
the board-mount receptacle connectors are arranged in an upper row and a lower row, and mounted on two opposite top and bottom surfaces of the second printed circuit board, wherein the cages and the cable receptacle connectors are arranged in an upper and a lower row, and are mounted on two opposite top and bottom surfaces of the first printed circuit board, wherein each of said cables having one end is connected to one corresponding board-mount receptacle connector, and the other end is connected to two neighboring cable receptacle connectors in the upper row and two neighboring cable receptacle connectors in the lower row, wherein said two neighboring cable receptacle connectors in the upper row are aligned with two neighboring cable receptacle connectors in the lower row in the vertical direction, respectively, wherein each of said cable includes four sets of different pair contacts, and each set includes two pairs.

US Pat. No. 10,559,929

ELECTRICAL CONNECTOR SYSTEM HAVING A PCB CONNECTOR FOOTPRINT

TE CONNECTIVITY CORPORATI...

1. A printed circuit board (PCB) for an electrical connector having signal contacts and ground contacts extending from a mounting end of the electrical connector, the PCB comprising:a substrate having a plurality of layers, the substrate having a connector surface configured to face the electrical connector and a PCB connector footprint on the connector surface defined below a footprint of the electrical connector, the PCB connector footprint being an area defined along a longitudinal axis and a lateral axis perpendicular to the longitudinal axis, the PCB connector footprint being subdivided into PCB column grouping footprints generally arranged in columns parallel to the longitudinal axis;
signal vias at least partially through the substrate, the signal vias being arranged in pairs arranged along a signal pair axis with a plurality of pairs of signal vias in each PCB column grouping footprint, the signal pair axis being non-parallel to the longitudinal axis, the pairs of signal vias being aligned in the corresponding columns parallel to the longitudinal axis, the pairs of signal vias being arranged in corresponding rows parallel to the lateral axis, the signal pair axis being non-parallel to the lateral axis, the signal pair axis being non-parallel to the longitudinal axis, wherein the signal pair axis intersects the longitudinal axis at a greater angle than the signal pair axis intersects the lateral axis; and
ground vias at least partially through the substrate, the ground vias being arranged around each of the pairs of signal vias to provide electrical shielding around each of the pairs of signal vias, wherein at least one ground via is arranged between adjacent pairs of signal vias within the PCB column grouping footprints and wherein at least one ground via is arranged between adjacent pairs of signal vias in adjacent PCB column grouping footprints.

US Pat. No. 10,559,928

ELECTRIC CONNECTOR

DAI-ICHI SEIKO CO., LTD.,...

1. An electric connector comprising:a contact member that electrically connects a signal transmission line of a connecting object to a signal conducting path of a connected object; and
a shell member electrically connects a ground transmission line of the connecting object to a ground conducting path of the connected object;
wherein the shell member includes
a first shell, disposed in a state of facing the connected object, that entirely covers the contact member and
a second shell disposed to face the first shell and disposed between the connecting object and the connected object,
wherein the first shell has a connecting object ground contact point which comes to be electrically connected to the ground transmission line provided on the connecting object, and has a connected object ground contact point which comes to be electrically connected to the ground conducting path provided on the connected object,
the second shell has a connecting object ground contact point which comes to be electrically connected to the ground transmission line provided on the connecting object, and has a connected object ground contact point which comes to be electrically connected to the ground conducting path provided on the connected object, and
wherein the first shell is disposed in a state of entirely covering the contact member without gaps from above,
the second shell is disposed to cover the contact member from below.

US Pat. No. 10,559,927

SWITCHABLE RJ45/ARJ45 JACK

Panduit Corp., Tinley Pa...

1. A communication connector, comprising:a housing configured for receiving a communication plug;
a printed circuit board at least partially within said housing;
a rocker switch at least partially within said housing, said rocker switch configured to rotate about a pivot point for actuating said printed circuit board; and
a translating crossbar at least partially within said housing, said translating crossbar engaging said rocker switch and causing said rocker switch to rotate about the pivot point.

US Pat. No. 10,559,925

COAXIAL CABLE CONNECTOR INTERFACE FOR PREVENTING MATING WITH INCORRECT CONNECTOR

CommScope Technologies LL...

1. An interface blocking coaxial connector, interconnectable with a mating coaxial connector, comprising:an inner contact defining a longitudinal axis;
a cylindrical outer contact with an axially-extending outer body and a plurality of spring fingers positioned radially inward of the outer body, the outer body and the spring fingers forming a gap to receive an outer conductor cylinder of the mating coaxial connector; and
a dielectric sleeve positioned between the inner contact and the spring fingers, the sleeve having a stop face that is substantially aligned with distal ends of the spring fingers, such that the sleeve interferes with the outer conductor cylinder of a mismating connector.

US Pat. No. 10,559,918

ELECTRICAL CONNECTOR ASSEMBLY

Aptiv Technologies Limite...

1. An electrical connector assembly, comprising;a plug including a plug body having a first housing part and a second housing part with a plug-in portion, wherein the first and second housing parts are movable relative to each other along a housing axis, wherein an elastic element is compressed between the first and second housing parts, thereby holding the first and second housing parts against each other, wherein the second housing part on its surface comprises a projection with a first sliding surface diagonally to the housing axis; and
a mating connector, having a plug-receiving portion configured to receive and electrically and mechanically connect the plug-in portion of the plug, comprises a collar which partially surrounds the plug-receiving portion, wherein the collar comprises a second sliding surface which is arranged complementary to the first sliding surface, when the plug is aligned with a plug-in axis while the plug is connected the first and second sliding surfaces cooperate, wherein a plug force is exerted on the plug in an insertion direction and thereby the first sliding surface slides on the second sliding surface, wherein the second housing part is displaced away from the first housing part along the housing axis against a restoring force of the elastic element, the second sliding surface ends at a recess in the collar, in fully assembled state the projection is located in an end plane with the recess, so that the elastic element pulls the projection into the recess and locks the plug body with the mating connector, wherein the first housing part comprises at least one rib which is aligned along the plug-in axis and wherein the mating connector comprises a groove at the side facing the plug-receiving portion, wherein the rib slides into the groove while the plug is connected.

US Pat. No. 10,559,910

ELECTRICAL CONNECTOR HAVING INSTERT-MOLDING CONTACT MODULE EMBEDDED WTIHIN A PAIR OF OVER-MOLDING COVERS

FOXCONN (KUNSHAN) COMPUTE...

1. An electrical connector comprising:a contact module including a plurality of contacts integrally formed within an insulator via an insert-molding process, each of said contacts including a front contacting section, a rear tail section and a middle retaining section therebetween along a front-to-back direction;
an insulative upper cover applied upon at least a top face of the contact module, via a first over-molding process, to form a subassembly while exposing the front contacting sections upwardly to an exterior in a vertical direction perpendicular to the front-to-back direction; and
an insulative lower cover applied upon said subassembly, via a second over-molding process, to cover at least a bottom face of the contact module; wherein
no front contacting sections of the contacts are downwardly exposed to the exterior around a bottom face of the lower cover.

US Pat. No. 10,559,909

TAMPER RESISTANT ELECTRICAL RECEPTACLE

LEVITON MANUFACTURING CO....

1. An electrical receptacle comprising:a cover including two cover apertures configured to receive two contact blades of a plug;
a platform coupled to the cover, the platform including two platform apertures aligned with the two cover apertures, a channel between the two platform apertures, and a pin trap channel separate from the two platform apertures;
a slider positioned between the cover and the platform and coupled to the platform, the slider including a post engaging the channel and shutters connected to the post; and
a coil spring coupled to the slider, the coil spring having a resting state in which the shutters are interposed between the two cover apertures and the two platform apertures, and having a compressed state in which the shutters are not interposed between the two cover apertures and the two platform apertures such that the two contact blades of the plug are permitted to pass through the two platform apertures,
wherein the slider glides along the channel of the platform as the coil spring moves between the resting and compressed states, and
wherein the pin trap channel is positioned to trap a pin that is inserted into one of the two cover apertures and that reaches the platform past the shutters.

US Pat. No. 10,559,903

CARD EDGE CONNECTOR EQUIPPED WITH SOLDER BALLS ON CONTACTS

FOXCONN (KUNSHAN) COMPUTE...

1. An electrical connector for receiving a memory module, comprising:an insulative elongated housing having a pair of elongated side walls extending along a longitudinal direction with a receiving slot formed therebetween in a transverse direction perpendicular to the longitudinal direction;
two rows of the passageways formed in the corresponding side walls, respectively;
two rows of contacts retained in the pair of side walls, respectively, and having corresponding contacting regions exposed in the receiving slot; and
each of said contacts including a retaining section retained in the corresponding passageway, a resilient contacting section extending upwardly from the retaining section and into the receiving slot, and a tail section extending downwardly from the retaining section and including a connecting section linked to the retaining section and a horizontal solder pad at a bottom, the solder pads being categorized with inward solder pads extending toward the receiving slot, and outward solder pads extending away from the receiving slot; wherein
the contacts in a same row are paired for every two neighboring contacts so as to form a plurality of pairs, each pair have either the corresponding inward solder pads or the corresponding outward solder pads, and the pairs having the corresponding inward solder pads and the pairs having the corresponding outward solder pads are alternately arranged with each other in a staggered manner along the longitudinal direction; wherein
in each pair, a distance between centerlines of the solder pads is larger than that between centerlines of the retaining sections.

US Pat. No. 10,559,899

MARKER-HOLDER DEVICE FOR A TERMINAL BLOCK

TE CONNECTIVITY SERVICES ...

1. A marker-holder system for an electrical terminal block comprising a longitudinal marker-holder device according to a direction of extension, the marker-holder device comprising a central part with a thinned portion and a first end in the direction of extension and a second end in the direction opposite to the direction of extension, the system comprising a first fastener disposed on the terminal block, the first end and/or the second end of the marker-holder device being rotatably secured to the first fastener in a removable manner so that the marker-holder device rotates between a first position in which a first face of the marker-holder device is oriented towards the terminal block and a second face of the marker-holder device is oriented in a direction opposite to the terminal block, and a second position in which the first face of the marker-holder device is oriented in a direction opposite to the terminal block and the second face of the marker-holder device is oriented towards the terminal block, so that a first marker positioned on the first face will be visible in the second position, and a second marker positioned on the second face will be visible in the first position, when the marker-holder device is rotatably secured to the first fastener, and wherein the thinned portion is divisible.

US Pat. No. 10,559,893

PULSE PROTECTION CIRCUITS TO DETER THEFT

CPG Technologies, LLC, I...

1. An apparatus, comprising:a guided surface wave receive structure configured to obtain electrical energy in a form of a Zenneck surface wave substantially mode-matched to a Zenneck surface wave mode of a surface of a terrestrial medium based at least in part upon the guided surface wave receive structure providing a phase delay (?) that matches a wave tilt angle (?) associated with a complex Brewster angle of incidence (?i,B) associated with the surface of the terrestrial medium;
an electrical load coupled to the guided surface wave receive structure, the electrical load being experienced as a load at an excitation source coupled to a guided surface waveguide probe generating the Zenneck surface wave, wherein an electrical field strength of the Zenneck surface wave is selectively increased; and
a pulse protection circuit employed to selectively protect the electrical load from an increase in electrical energy received by the guided surface wave receive structure when the electrical field strength is selectively increased.

US Pat. No. 10,559,866

MEASURING OPERATIONAL PARAMETERS AT THE GUIDED SURFACE WAVEGUIDE PROBE

CPG TECHNOLOGIES, INC, I...

1. An apparatus comprising:a guided surface waveguide probe configured to launch a guided surface wave along a surface of a lossy conducting medium, wherein the guided surface waveguide probe comprises:
a charge terminal elevated to a height above the lossy conducting medium;
a support structure that supports the charge terminal;
at least one section of internal coil that is supported within the support structure and is coupled to an excitation source;
a conductive tube having a first end conductively coupled to the at least one section of internal coil, wherein a second end of the conductive tube extends vertically towards the charge terminal, wherein the at least one section of the internal coil is electrically coupled to the charge terminal via the conductive tube;
at least one sensor electrically coupled to the charge terminal or the internal coil, wherein the at least one sensor measures an operational parameter of the guided surface waveguide probe; and
a non-conductive channel connected to the at least one sensor and monitoring equipment of the guided surface waveguide probe by which data associated with the operational parameter is communicated.

US Pat. No. 10,559,749

MAGNETORESISTIVE EFFECT ELEMENT

TDK CORPORATION, Tokyo (...

1. A magnetoresistive effect element comprising:a first ferromagnetic layer as a magnetization fixed layer;
a second ferromagnetic layer as a magnetization free layer; and
a nonmagnetic spacer layer provided between the first ferromagnetic layer and the second ferromagnetic layer,
wherein the nonmagnetic spacer layer comprises an Ag alloy represented by General Formula (1), and thereby lattice mismatch between the nonmagnetic spacer layer, and the first ferromagnetic layer and/or the second ferromagnetic layer is reduced, compared to lattice mismatch when the nonmagnetic spacer layer is formed of Ag,
Ag?X1-?  (1)
where X indicates one element selected from the group consisting of Cu, Ga, Ge, As, Y, La, Sm, Yb, and Pt, and 0 wherein at least one of the first ferromagnetic layer and the second ferromagnetic layer comprises a Heusler alloy represented by General Formula (2),
Co2L?M?  (2)
where L is at least one or more elements of Mn and Fe, M indicates one or more elements selected from the group consisting of Si, Al, Ga, and Ge, 0.7

US Pat. No. 10,559,733

LIGHT-EMITTING DEVICE PACKAGE

LG INNOTEK CO., LTD., Se...

1. A light-emitting device package comprising;a body;
N (N denoting a positive integer of 5 or more) upper pads disposed on the body so as to be spaced apart from each other;
N?1 light-emitting device chips respectively disposed on N?1 upper pads, among the N upper pads; and
a plurality of first wires configured to electrically connect the N?1 light-emitting device chips and the N upper pads to each other,
wherein a first upper pad and an Nth upper pad, among the N upper pads, face each other at an outermost peripheral region of a plane of the light-emitting device package,
wherein the remaining second to N?1th upper pads, excluding the first and Nth upper pads, among the N upper pads are completely surrounded by the first and Nth upper pads in a plan view so that one of the first and Nth upper pads is between each of the remaining second to N?1th upper pads and an edge of the body, and
wherein a light-emitting device chip of the N?1 light-emitting device chips is disposed on one among the first and Nth upper pads and is not disposed on the other among the first and Nth upper pads.

US Pat. No. 10,559,732

SURFACE-MOUNTED LIGHT-EMITTING DEVICE AND FABRICATION METHOD THEREOF

XIAMEN SANAN OPTO ELECTRO...

5. A method of fabricating a surface-mounted light-emitting diode (LED) light-emitting device, the method comprising:1) epitaxial growth: form an LED epitaxial structure over a growth substrate through epitaxial growth;
2) chip fabrication:
determine P and N electrode regions and an isolating region on a surface of the LED epitaxial structure; and
fabricate P and N electrode pads and an insulator over the P and N electrode regions and the isolating region, respectively on the surface of the LED epitaxial structure,
wherein the insulator fabricated on the surface of the LED epitaxial structure has opposite a first insulator surface and a second insulator surface,
wherein the first insulator surface is adjacent to the LED epitaxial structure and the second insulator surface extrudes beyond either of the second electrode surfaces of the P and N electrode pads to prevent the P and N electrode pads from short circuiting when directly applied in the SMT packaging;
wherein the P and N electrode pads have sufficient thicknesses to support the LED epitaxial structure, and the insulator is formed between the P and N electrode pads to prevent the P and N electrode pads from a short circuit;
remove the growth substrate and unitize the LED epitaxial structure to form a LED chip;
3) Surface-Mounted Technology (SMT) packaging:
provide a supporting substrate and directly mount the P and N electrode pads of the LED chip over the supporting substrate through SMT packaging to thereby form the surface-mounted LED light-emitting device;
wherein in step 3), the supporting substrate has a surface coated with a solder layer with a thickness smaller than or equal to a height difference between the second insulator surface and either of the second electrode surfaces of the P and N electrode pads, wherein the insulator extends through the solder layer and is in contact with the solder layer and the supporting substrate, wherein a distance between edges of the P and N electrode pads beyond that of the LED epitaxial structure is D, a minimum thickness of the P and N electrode pads is T, and wherein D/T is 0.5-2.

US Pat. No. 10,559,730

COLLIMATED LED LIGHT FIELD DISPLAY

APPLIED MATERIALS, INC., ...

1. A method of forming a light field display, comprising:forming a plurality of light emitting diodes from a patterned substrate, comprising:
depositing a resist layer on a surface of a substrate, the substrate comprising:
a structural base;
an active layer stack disposed on the structural base; and
a transparent conductive oxide layer disposed on the active layer stack;
patterning the resist layer; and
transferring the pattern formed in the resist layer to the transparent conductive oxide layer and to at least a portion of the active layer stack disposed therebeneath to form the patterned substrate; and
arranging one or more of the plurality of light emitting diodes beneath a light-directing feature of a plurality of light-directing features formed on a substrate panel, wherein each of the light-directing features and at least one of the one or more light emitting diodes positioned there beneath forms a pixel of angular resolution of the light field display.

US Pat. No. 10,559,727

MANUFACTURING METHOD OF COLORFUL MICRO-LED, DISPLAY MODLUE AND TERMINALS

Shenzhen China Star Optoe...

1. A manufacturing method of colorful Micro-LEDs, comprising:providing a substrate, wherein one side of the substrate is configured with an array having a plurality of blue-light micro-LEDs; the plurality of blue-light micro-LEDs comprise first preset blue-light Micro-LEDs, second preset blue-light Micro-LEDs, and third preset blue-light Micro-LEDs; wherein the first preset blue-light Micro-LEDs are disposed between the second preset blue-light Micro-LEDs and the third preset blue-light Micro-LEDs;
configuring a light emitting surface of the blue-light Micro-LEDs of the array to face upward and immersing the whole substrate into the first-color photosensitive solution;
turning on only the first preset blue-light Micro-LEDs of the array without turning on the second preset blue-light Micro-LEDs and the third preset blue-light Micro-LEDs for conducting polymerization on the first preset blue-light Micro-LEDs to form at least one first lens, and forming a first-color pixel on the at least one first lens;
after the at least one first lens and the first-color pixel are formed, configuring the light emitting surface of the blue-light Micro-LEDs of the array to face upward and immersing the whole substrate into the second-color photosensitive solution;
turning on only the second preset blue-light Micro-LEDs of the array without turning on the first preset blue-light Micro-LEDs and the third preset blue-light Micro-LEDs for conducting the polymerization on the second preset blue-light Micro-LEDs to form at least one second lens, and forming a second-color pixel on the at least one second lens;
wherein the first-color pixel is one of a red pixel and a green pixel, and the second-color pixel is the other of the red pixel and the green pixel.

US Pat. No. 10,559,726

LAYERED STRUCTURES AND QUANTUM DOT SHEETS AND ELECTRONIC DEVICES INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A quantum dot sheet comprising:a photoconversion layer comprising a polymer matrix and a plurality of quantum dots dispersed in the polymer matrix; and
a layered structure comprising a first layer comprising a polymerization product of a monomer combination comprising a first monomer having at least two thiol groups at its terminal end and a second monomer having at least two carbon-carbon unsaturated bond-containing groups at its terminal end,
wherein the first monomer comprises a first thiol compound represented by Chemical Formula 1-1 comprising a thioglycolate moiety and a second thiol represented by Chemical Formula 1-2:

wherein in Chemical Formula 1-1,
L1 is a carbon atom, a substituted or unsubstituted C1 to C30 alkylene group, a substituted or unsubstituted C6 to C30 cycloalkylene group, a substituted or unsubstituted C6 to C30 arylene group, a substituted or unsubstituted C3 to C30 heteroarylene group, or a substituted or unsubstituted C3 to C30 heterocycloalkylene group,
Y1 is a single bond or a substituted or unsubstituted C1 to C4 alkylene group,
R1 is same or different and each independently hydrogen or C1 to C3 alkyl group,
n is an integer of 2 to 4,
L1 has a valence of at least n,

wherein in Chemical Formula 1-2,
L1 is a carbon atom, a substituted or unsubstituted C1 to C30 alkylene group, a substituted or unsubstituted C6 to C30 cycloalkylene group, a substituted or unsubstituted C6 to C30 arylene group, a substituted or unsubstituted C3 to C30 heteroarylene group, or a substituted or unsubstituted C3 to C30 heterocycloalkylene group,
Y2 is a single bond; —(OCH2CH2)m— (wherein m is an integer of 1 to 10), sulfonyl (—S(?O)2—), carbonyl (—C(?O)—), ether (—O—), sulfide (—S—), sulfoxide (—S(?O)—), ester (—C(?O)O—), amide (—C(?O)NR—) (wherein R is hydrogen or a C1 to C10 linear or branched alkyl group), —RB— [wherein R is a C1 to C20 substituted or unsubstituted divalent linear or branched alkylene group, a C1 to C20 substituted or unsubstituted divalent linear or branched alkylene group having at least one methylene replaced with sulfonyl (—S(?O)2—), carbonyl (—C(?O)—), ether (—O—), sulfide (—S—), sulfoxide (—S(?O)—), ester (—C(?O)O—), amide (—C(?O)NR—) (wherein R is hydrogen or a C1 to C10 linear or branched alkyl group), or a combination thereof, or —(OCH2CH2)m— (wherein m is an integer of 1 to 10) and B is sulfonyl (—S(?O)2—), carbonyl (—C(?O)—), ether (—O—), sulfide (—S—), sulfoxide (—S(?O)—), ester (—C(?O)O—), amide (—C(?O)NR—) (wherein R is hydrogen or a C1 to C10 linear or branched alkyl group), or a combination thereof], or a combination thereof,
A is a C2 to C4 divalent alkylene group,
n is an integer of 2 to 4,
L1 has a valence of at least n; and
the second monomer comprises an ene compound represented by Chemical Formula 2:

wherein in Chemical Formula 2,
X is —CR?CR2 or —C?CR (wherein R is each independently hydrogen or a C1 to C3 alkyl group),
R2 is selected from hydrogen; a substituted or unsubstituted C1 to C30 linear or branched alkyl group; a substituted or unsubstituted C6 to C30 aryl group; a substituted or unsubstituted C3 to C30 heteroaryl group; a substituted or unsubstituted C3 to C30 cycloalkyl group; a substituted or unsubstituted C3 to C30 heterocycloalkyl group; a C1 to C10 alkoxy group; a hydroxy group; —NH2; a substituted or unsubstituted alkyl amine group (—NRR?, wherein R and R? are independently hydrogen or a C1 to C30 linear or branched alkyl group provided that both of R and R? cannot be hydrogen at the same time); an isocyanate group; a halogen; —ROR? (wherein R is a substituted or unsubstituted C1 to C20 alkylene group and R? is hydrogen or a C1 to C20 linear or branched alkyl group); an acyl halide (—RC(?O)X, wherein R is a substituted or unsubstituted alkylene group and X is a halogen); —C(?O)OR? (wherein R? is hydrogen or a C1 to C20 linear or branched alkyl group); —CN; —C(?O)ONRR? (wherein R and R? are independently hydrogen or a C1 to C20 linear or branched alkyl group); or a combination thereof,
L2 is a carbon atom, a substituted or unsubstituted C1 to C30 alkylene group, a substituted or unsubstituted C6 to C30 cycloalkylene group, a substituted or unsubstituted C6 to C30 arylene group, a substituted or unsubstituted C3 to C30 heteroarylene group, or a substituted or unsubstituted C3 to C30 heterocycloalkylene group,
Y2 is a single bond; a substituted or unsubstituted C1 to C30 alkylene group; a substituted or unsubstituted C2 to C30 alkenylene group; or a C1 to C30 alkylene group or a C2 to C30 alkenylene group wherein at least one methylene (—CH2—) group is replaced by sulfonyl (—S(?O)2—), carbonyl (—C(?O)—), ether (—O—), sulfide (—S—), sulfoxide (—S(?O)—), ester (—C(?O)O—), amide (—C(?O)NR—) (wherein R is hydrogen or a C1 to C10 linear or branched alkyl group), imine (—NR—) (wherein R is hydrogen or a C1 to C10 linear or branched alkyl group), or a combination thereof,
n is an integer of 1 or more,
k3 is an integer of 0 or more,
k4 is an integer of 1 or more, and
the sum of n and k4 is an integer of 3 or more,
provided that n does not exceed the valence of Y2, and
provided that the sum of k3 and k4 does not exceed the valence of L2, and
wherein the layered structure is disposed on at least one surface of the photoconversion layer, wherein the at least one surface of the photoconversion layer faces a surface of the first layer of the layered structure.

US Pat. No. 10,559,722

LIGHT-EMITTING DEVICE

CITIZEN ELECTRONICS CO., ...

1. A light-emitting device comprising:a planar lead frame configured from first and second metal portions which are spaced apart from each other with an insulating resin interposed therebetween;
light-emitting elements mounted on the first metal portion and electrically connected by wires to the first and second metal portions;
a first resin frame disposed on the lead frame so as to enclose the light-emitting elements;
a sealing resin containing a phosphor for converting a wavelength of light emitted from the light-emitting elements, the sealing resin being filled into a region on the lead frame enclosed by the first resin frame to seal the light-emitting elements; and
a second resin frame being harder than the first resin frame and covering an outer surface of the first resin frame at an outer edge of the lead frame.

US Pat. No. 10,559,721

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a substrate;
a light emitting element mounted on the substrate;
a light reflecting resin member surrounding the light emitting element, and configured and arranged to reflect light emitted from the light emitting element;
a sealing member disposed in a region surrounded by the light reflecting, resin member;
an electrically conductive wiring arranged on an upper surface of the substrate such that the substrate includes an exposed region exposed from the electrically conductive wiring with at least a part of the exposed region of the substrate being embedded in the light reflecting resin member, the electrically conductive wiring being electrically connected to the light emitting element; and
a lens member disposed above the light emitting element to reach an outer edge of the substrate, the lens member being in contact with an upper surface of the sealing member and an upper surface and an outer lateral surface of the light reflecting resin member, an entire top surface of the lens member being exposed with the top surface of the lens member defining a part of an outermost surface of the light emitting device.

US Pat. No. 10,559,719

SOLID-STATE RADIATION TRANSDUCER DEVICES HAVING AT LEAST PARTIALLY TRANSPARENT BURIED-CONTACT ELEMENTS, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A light-emitting diode device, comprising:a light-emitting diode including—
a first semiconductor material,
a second semiconductor material, and
an active region between the first semiconductor material and the second semiconductor material;
a first contact electrically coupled to the first semiconductor material;
a second contact including a buried-contact element electrically coupled to the second semiconductor material, wherein the buried-contact element has an end portion directly adjacent to the second semiconductor material, and wherein the end portion of the buried-contact element is transparent; and
an optical component disposed over the second semiconductor material, the optical component including—
a transparent matrix, and
color-converting particles within the matrix, wherein the color-converting particles are configured to absorb radiation from the light-emitting diode at a first wavelength within the first wavelength range and to emit radiation at a second wavelength within the second wavelength range different than the first wavelength range,
wherein the light-emitting diode device has an average reflectivity of backscatter radiation from the color-converting particles at the buried-contact element, and wherein the average reflectivity is greater than 75%.

US Pat. No. 10,559,712

QUANTUM DOTS AND DEVICES INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A core-shell quantum dot including at least two different halogens,the core-shell quantum dot comprising:
a core comprising a first semiconductor nanocrystal; and
a shell disposed on the core, the shell comprising a crystalline or amorphous material,
wherein the core-shell quantum dot does not include cadmium,
wherein a solid state photoluminescence quantum efficiency of the core-shell quantum dot, when measured at 90° C. or greater, is greater than or equal to about 95% of a solid state photoluminescence quantum efficiency of the core-shell quantum dot when measured at 25° C., and
wherein the at least two different halogens comprise fluorine and at least one of chlorine, bromine, and iodine.

US Pat. No. 10,559,711

BURIED ACTIVATED P-(AL,IN)GAN LAYERS

Gallium Enterprises Pty L...

1. A method of fabricating a semiconductor structure comprising a buried activated magnesium-doped p-(Al,In)GaN layer, comprising:(a) growing a magnesium doped p-(Al,In)GaN layer using a gaseous mixture comprising NH3, H2, or a combination thereof, wherein the gaseous mixture has a partial pressure of H2 less than 760 Torr; and
(b) growing a semiconductor layer on the magnesium-doped p-(Al,In)GaN layer in an environment wherein a partial pressure of H2 is greater than a partial pressure of N2;
to provide a semiconductor structure comprising a buried activated magnesium doped p-(Al,In)GaN layer.

US Pat. No. 10,559,701

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Hyundai Motor Company, S...

1. A semiconductor device, comprising:a first n? type of layer, a second n? type of layer, and an n+ type of region sequentially disposed on a first surface of a substrate;
a trench disposed on a side surface of the second n? type of layer;
a p type of region disposed between the second n? type of layer and the trench;
a gate electrode disposed on a bottom surface of the trench;
a source electrode disposed on the n+ type of region; and
a drain electrode disposed on a second surface of the substrate,
wherein the second n? type of layer includes a first concentration layer, a second concentration layer, a third concentration layer, and a fourth concentration layer sequentially disposed on the first n? type of layer,
wherein an ion doping concentration of the second concentration layer is lower than an ion doping concentration of the first concentration layer,
wherein an ion doping concentration of the third concentration layer is lower than the ion doping concentration of the second concentration layer, and
wherein an ion doping concentration of the fourth concentration layer is lower than the ion doping concentration of the third concentration layer.

US Pat. No. 10,559,700

ZERO COST NVM CELL USING HIGH VOLTAGE DEVICES IN ANALOG PROCESS

JONKER LLC, Zephyr Cove,...

1. A programmable non-volatile memory device situated in a high voltage circuit region of a substrate comprising:a floating gate configured to store non-volatile memory data for the device;
wherein said floating gate is comprised of a conductive material that is also used as a common gate layer for a high voltage transistor device also situated in the high voltage circuit region of the substrate;
a source region coupled to a first terminal;
a drain region coupled to a second terminal and overlapping a first portion of said floating gate sufficient to support hot electron injection programming along an edge of said floating gate; and
a drift region overlapping a second portion of the floating drain region;
wherein the drift region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said first terminal of said drain region and second terminal of said source region can be imparted to said floating gate through areal capacitive coupling.

US Pat. No. 10,559,685

VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED EXTERNAL RESISTANCE

International Business Ma...

1. A method for forming a semiconductor structure, the method comprising at least:forming a structure comprising at least a substrate, a first source/drain layer, and at least one semiconductor fin disposed on and in contact with substrate;
forming a silicide in contact with and wrapping around the first source/drain layer;
forming a gate structure in contact with at least the at least one semiconductor fin; and
forming a second source/drain layer above the first source/drain layer.

US Pat. No. 10,559,681

HIGH VOLTAGE LATERAL JUNCTION DIODE DEVICE

TEXAS INSTRUMENTS INCORPO...

1. A method of fabricating an integrated circuit (IC), comprising:forming in a semiconductor surface layer, doped a first conductivity type, a depletion-mode laterally diffused MOSFET (LDMOS device), including forming a source and a drain doped a second conductivity type within said substrate, a channel region between the source and the drain, a gate dielectric over the channel region, a gate over the gate dielectric, and a drift region between said channel region and said drain, wherein said drain also provides a first cathode for a lateral junction diode having a first anode adjacent the source and running in parallel with a path between said source and said drain;
forming a clamp diode including a second cathode and a second anode, wherein said clamp diode is junction-isolated from the LDMOS device by a doped region of the second conductivity type located between said second anode and said source, and
directly connecting said gate to said second anode, and directly connecting said source to said second cathode.

US Pat. No. 10,559,680

SEMICONDUCTOR DEVICE INCLUDING A POWER TRANSISTOR DEVICE AND BYPASS DIODE

Cree, Inc., Durham, NC (...

1. A semiconductor device comprising:a substrate;
a drift layer on the substrate;
a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) comprising:
at least four junction implants in the drift layer opposite the substrate such that the at least four junction implants are separated from one another by a portion of the drift layer;
a gate oxide layer on the drift layer opposite the substrate such that the gate oxide layer at least partially overlaps each one of the at least four junction implants;
a gate contact on the gate oxide layer;
source contacts on the drift layer and above each of the at least four junction implants; and
a drain contact on the substrate; and
junction barrier Schottky bypass diodes comprising a Schottky contact separate from the source contacts on the drift layer opposite the substrate such that the Schottky contact only partially overlaps and runs between two of the at least four junction implants, and is laterally disposed between the source contacts.

US Pat. No. 10,559,675

STACKED SILICON NANOTUBES

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising: forming one or more stacked nanowires comprising a sacrificial material over a substrate, the sacrificial material comprising a first type of semiconductor material; forming a pull-out layer around each of the one or more stacked nanowires; reacting the pull-out layer with the first type of semiconductor material to form a silicon-rich layer on a surface of each of the one or more stacked nanowires; and removing the sacrificial material to define one or more hollow nanotubes comprising the silicon-rich layer.

US Pat. No. 10,559,666

DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A structure, comprising:a semiconductor substrate;
a semiconductor buffer layer disposed over the semiconductor substrate;
an oxide layer disposed over the buffer layer; and
a fin comprising a semiconductor material disposed over the oxide layer,
wherein the semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer, and
wherein a distance between a top surface of the oxide layer and a bottom surface of the buffer layer is more than a distance between a bottom surface of the fin and the bottom surface of the buffer layer.

US Pat. No. 10,559,664

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY REMOVING A BULK LAYER TO EXPOSE AN EPITAXIAL-GROWTH LAYER AND BY REMOVING PORTIONS OF A SUPPORTING-SUBSTRATE TO EXPOSE PORTIONS OF THE EPITAXIAL-GROWTH LAYER

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device, comprising:assigning a plurality of chip regions on an epitaxial-growth layer of a semiconductor substrate, the semiconductor substrate further comprising a bulk layer on which the epitaxial-growth layer has been grown, the bulk layer having a bottom-surface side facing away from the epitaxial-growth layer;
forming a plurality of device structures on the plurality of chip regions, respectively;
bonding an upper supporting-substrate on a top-surface side of the epitaxial-growth layer;
after bonding the upper supporting-substrate on the top-surface side of the epitaxial-growth layer, thinning the semiconductor substrate from the bottom-surface side of the bulk layer by removing the bulk layer from the semiconductor substrate and exposing a bottom-surface side of the epitaxial-growth layer;
bonding a lower supporting-substrate on the bottom-surface side of the epitaxial-growth layer exposed by the thinning;
after bonding the lower supporting-substrate on the bottom-surface side of the epitaxial-growth layer exposed by the thinning, thinning a bottom-surface side of the lower supporting-substrate;
after thinning the bottom-surface side of the lower supporting-substrate, selectively removing portions of the thinned lower supporting-substrate so that portions of the bottom-surface side of the epitaxial-growth layer are exposed, at locations corresponding to positions of each of main current paths in the plurality of device structures, respectively;
after selectively removing the portions of the thinned lower supporting-substrate, adhering a bottom surface of the thinned lower supporting-substrate to an adhesive tape;
applying heat or ultraviolet radiation to neutralize an adhesive force of an adhesive layer which bonds the upper supporting-substrate to the top-surface side of the epitaxial-growth layer, and separating the upper supporting-substrate from the top-surface side of the epitaxial-growth layer while the bottom surface of the thinned lower supporting-substrate is adhered to the adhesive tape;
applying heat or ultraviolet radiation to neutralize an adhesive force of the adhesive tape and separating the bottom surface of the thinned lower supporting-substrate from the adhesive tape; and
dicing the thinned semiconductor substrate having the bulk layer removed, together with the lower supporting-substrate, along dicing lanes between the plurality of the chip regions so as to form a plurality of chips.