US Pat. No. 10,483,679

COMBINATION RECEPTACLE

EATON INTELLIGENT POWER L...

1. A combination receptacle comprising:a first universal serial bus (USB) port having a first type;
a second USB port having a second type;
a shutter structured to have a first state to allow access to the first USB port and block access to the second USB port and a second state to block access to the first USB port and allow access to the second USB port;
circuitry structured to control and provide power to the first and second USB ports,
wherein the first USB port is a USB Type-C power delivery (PD) port and the second USB port is a USB Type-C non-PD port, and
wherein the circuitry is structured to provide a power profile including 5V, 9V, 12V, 15V, and 20V to the first USB port and to provide power at 5V to the second USB port.

US Pat. No. 10,483,677

CONNECTOR

Sumitomo Wiring Systems, ...

1. A connector, comprising:a housing body having a front end that is connectable to a mating housing and having a reference surface extending substantially along a longitudinal direction;
an arm body extending substantially along the longitudinal direction; and
at least one leg coupling an intermediate location of the arm body in the longitudinal direction and the reference surface,
an area on a front side of the intermediate location of the arm body that is coupled to the leg defining a lock and an area on a rear side of the intermediate location of the arm body that is coupled to the leg and substantially opposite to the front side defining a releasing portion; and
in a process of connecting the housing body to the mating housing, the area on the first side of the intermediate location of the arm body initially deflects away from the reference surface and then resiliently returns so that the lock locks a mating lock on the mating housing, whereas the releasing portion is displaced toward the reference surface for separating the lock from the mating lock and releasing a locked state with the mating lock when the arm body is inclined with the leg defining a support, and wherein
the leg is inclined forward from the reference surface toward the arm body.

US Pat. No. 10,483,672

INFORMATION HANDLING SYSTEM MOBILE ADAPTER WITH VIDEO AND COMMUNICATIONS CIRCUIT BOARDS

Dell Products L.P., Roun...

1. A mobile peripheral adapter comprising:a circular housing having plural port openings;
plural ports disposed at the plural port openings, each port operable to accept a predetermined output cable plug;
a first circuit board disposed in the circular housing having a first set of components operable to convert information from a first communication protocol to one or more communication output protocols for communication through one or more of the plural ports;
a second circuit board disposed in the circular housing having a second set of components operable to convert information from the first communication protocol to one or more video output protocols for communication through one or more of the plural ports;
a cable terminating at one end with plural wirelines and at an opposing end at a cable plug associated with the first communication protocol, the cable having a first set of wirelines coupled to the first circuit board to communicate information between the cable plug and the first set of components and a second set of wirelines coupled to the second circuit board to communicate information between the cable plug and the second set of components, the second set of wirelines only communicating video information; and
a flexible cable coupled between the first and second circuit boards to provide power and ground from the first circuit board to the second circuit board.

US Pat. No. 10,483,667

ELECTRONIC DEVICE AND RADAR DEVICE

WISTRON NEWEB CORP., Hsi...

1. An electronic device, comprising:an RF transceiver;
an antenna, coupled to the RF transceiver;
an operational amplifier, coupled to the RF transceiver;
a digital signal processor, coupled to the operational amplifier;
a power converter;
a circuit board, comprising a first circuit board edge, a second circuit board edge, a first coupling unit, and a second coupling portion, wherein the first circuit board edge is parallel to the second circuit board edge, the first coupling unit is located on the first circuit board edge, and the second coupling unit is located on the second circuit board edge, wherein the first coupling unit comprises a plurality of first contacts, and the second coupling unit comprises a plurality of second contacts; and
a U-shaped circuit board structure, comprising a first supporting portion, a second supporting portion, a planar portion, a third coupling unit, and a fourth coupling portion, wherein the planar portion comprises a first planar portion edge and a second planar portion edge, the first planar portion edge is parallel to the second planar portion edge, the first supporting portion is disposed on the first planar portion edge, the second supporting portion is disposed on the second planar portion edge, the third coupling unit is disposed on the first supporting portion, the fourth coupling unit is disposed on the second supporting portion, the third coupling unit is electrically connected to the first coupling unit, the fourth coupling unit is electrically connected to the second coupling unit, the planar portion is parallel to the circuit board, and a receiving space is formed between the planar portion and the circuit board, wherein the power converter is disposed on the U-shaped circuit board structure, such that the U-shaped circuit board structure is interposed between the power converter and the digital signal processor;
wherein the third coupling unit comprises a plurality of first leads, the fourth coupling unit comprises a plurality of second leads, the first leads extend on a first lateral surface of the first supporting portion to a first end surface of the first supporting portion to be connected to the first contacts, and the second leads extend on the second lateral surface of the second supporting portion to a second end surface of the second supporting portion to be connected to the second contacts,
wherein the power converter is disposed on the U-shaped circuit board structure, and the antenna, the RF transceiver, the digital signal processor and the operational amplifier are disposed on the circuit board.

US Pat. No. 10,483,663

TERMINAL BLOCK WITH RETENTION FEATURES FOR A REMOVABLE I/O MODULE

Rockwell Automation Asia ...

1. An input/output device comprising:a terminal base adapted to be mounted to an associated support structure;
a terminal block connected to the terminal base, said terminal block including a plurality of wiring terminals adapted to be electrically connected to associated input/output device field wiring;
a latch comprising a latch body connected to the terminal block, said latch body manually movable to and between an unlatched position and a latched position;
an input/output module connected to the terminal base adjacent the terminal block, said input/output module comprising a locking tab connected thereto;
wherein said latch body, when in said latched position, engages the locking tab of the input/output module and captures the input/output module to the terminal block; and,
wherein said latch body, when in said unlatched position, is disengaged from the locking tab to allow said input/output module to be disconnected from said terminal block;
said latch further comprises a latching slot provided in said terminal block adjacent said input/output module;
said locking tab of said input/output module is received in said latching slot; and,
said latch body at least partially located in said latching slot and movable in said latching slot between said latched and unlatched positions said latch body at least partially overlies the locking tab to capture the locking tab in the latching slot of the terminal block between the latch body and the terminal block when the latch body in located in its latched position.

US Pat. No. 10,483,659

GROUNDING CLIP FOR BONDED VANES

United Technologies Corpo...

1. A grounding clip for an organic matrix composite guide vane with a metallic sheath comprising:the organic matrix composite guide vane comprising a body having a leading edge and a trailing edge opposite the leading edge and a root end extending between said leading end edge and said trailing edge;
the metallic sheath attached proximate said leading edge and extending to said root end;
a metallic attachment fitting having a receiver configured to receive said root end of said organic matrix composite guide vane for coupling said organic matrix composite guide vane to said metallic attachment fitting; and
the grounding clip coupled to said sheath proximate said root end; wherein said grounding clip is electrically connected to said metallic attachment fitting and said metallic sheath.

US Pat. No. 10,483,658

WEIGHT REDUCED SWAGE PARALLEL GROOVE CLAMP

AFL Telecommunications LL...

1. A method for installing a clamp, the method comprising:inserting at least one cable into at least one tap of the clamp, the clamp having a pre-installation size and including a body, the at least one tap defined in the body, and at least one indentation defined in an outermost surface of the body;
providing the clamp into a radial swage press apparatus, the radial swage press apparatus comprising a yoke, a die block, a die disposed between the yoke and the die block, and at least one die insert, the at least one die insert having an inner surface which corresponds to a shape of the at least one indentation;
crimping the clamp with the radial swage press apparatus such that the resulting crimped clamp has an installation size which is less than the pre-installation size and includes the body, the at least one tap, and the at least one indentation.

US Pat. No. 10,483,656

DUAL-NOTCH ANTENNA AND ANTENNA ARRAY THEREOF

CUBTEK INC., Zhubei, Hsi...

1. A dual-notch antenna, comprising: a plurality of radiation members, each of the radiation members formed in a rectangular shape, with two first lateral sides disposed in opposite, and two second lateral sides disposed on two ends of the two first sides, respectively, so as to form the rectangular shape, a middle section of each first lateral side concavely provided with a notch, each of the two notches provided with a feeding side and two cove sides, the feeding side disposed in parallel to the two first lateral sides, the two cove sides connected with two ends of the feeding side; and a plurality of microstrip lines, each microstrip line electrically connected with one of the corresponding feeding sides of the radiation member, such that the plurality of radiation members are connected in series to form a string array; lengths of the first lateral sides between each radiation member from a center of the string array toward the two radiation members at two distal ends of the string array being gradually decreased, such that the radiation member at the center of the string array has the longest first lateral sides, and the radiation members at the two distal ends of the string array have the shortest first lateral sides; wherein one of the microstrip lines is applied as an input end, and the other microstrip line is applied as an output end.

US Pat. No. 10,483,651

TRANSMIT-ARRAY ANTENNA COMPRISING A MECHANISM FOR REORIENTING THE DIRECTION OF THE BEAM

RADIALL, Aubervillers (F...

1. A transmit-array radiofrequency antenna comprising:a support;
a transmit-array arranged in a transmission plane, the transmit-array comprising a printed circuit and a plurality of basic cells produced in a central zone of the printed circuit,
at least one focal source, fixed on the support and arranged at the focal length from the array;
a displacement mechanism for moving the transmit-array, the mechanism being connected to the support and being adapted to translationally move the transmit-array in at least one of the two directions in the transmission plane, the displacement mechanism being connected to the printed circuit in its peripheral zone;
wherein the displacement mechanism comprises:
two servomotors;
two first pantograph devices, each comprising two deformable parallelograms each formed by four articulation segments connected pairwise by a flexible articulation forming a pivot link and one of the segments of which is common to the two parallelograms,
in which displacement mechanism, the common segment of each of the two first pantograph devices is connected to one of the two servomotors, whereas one of the segments parallel to the common segment is fixed on the printed circuit in its peripheral zone and the other one of the segments parallel to the common segment is fixed on the support, the connection between each of the common segments with one of the two servomotors being carried out such that one of the servomotors may move the common segment of one of the two first devices and hence move the printed circuit in approximately one of the two directions (X) in the transmission plane, whereas the other one of the servomotors may move the common segment of one of the two first devices and hence move the printed circuit in approximately the other one of the two directions (Y) in the transmission plane.

US Pat. No. 10,483,650

LENSED ANTENNAS FOR USE IN CELLULAR AND OTHER COMMUNICATIONS SYSTEMS

CommScope Technologies LL...

1. A multi-beam antenna, comprising:a radio frequency (“RF”) lens;
a plurality of radiating elements that are orbitally arranged part of the way around a first side of the RF lens,
wherein the radiating elements are arranged in a plurality of rows and columns, where each row extends in a respective arc in a respective one of a plurality of horizontal planes and each column extends in a respective arc in a respective one of a plurality of vertical planes,
wherein the multi-beam antenna is configured for multi-input-multi-output transmission.

US Pat. No. 10,483,646

ANTENNA DEVICE

SUMIDA CORPORATION, (JP)...

1. An antenna device comprising:a core formed from a magnetic material;
a terminal mounting unit arranged adjacent to one side of the core, the terminal mounting unit having a sidewall member, the sidewall member including opposite sides and a plurality of through holes, each of the plurality of through holes extending from one of the opposite sides to the other of the opposite sides;
a coil which is arranged on an outer circumference of the core, the coil being a wound conductive wire;
a coil which is arranged on an outer circumference of the core, the coil being a wound conductive wire;
a plurality of elongated terminals which are inserted into the plurality of through holes; and
an electronic component provided on the terminal mounting unit,
wherein the plurality of elongated terminals included a first terminal, and the first terminal is configured with a pin-shaped portion at one end and an outward portion at the other end, and
when the first terminal is inserted into one of the plurality of through holes, the pin-shaped portion and the outward portion of the first terminal are partially exposed outside of the sidewall member.

US Pat. No. 10,483,644

EIGHT-FREQUENCY BAND ANTENNA

TAOGLAS GROUP HOLDINGS LI...

1. An eight-frequency band antenna, comprising:a carrier comprising a front face, a top face, a back face and a bottom face, the carrier having a plurality of blind holes defined on the front face and forming a recess into the carrier and at least one rib between two adjacent blind holes; a high-frequency segment arranged on the front face, the top face, the back face, and the bottom face of the carrier comprising a straight shaped radiator, a winding radiator, a double-t shaped radiator, a first L-shaped radiator with a long side parallel to the winding radiator along two faces of the carrier, and a second L-shaped radiator; and a low-frequency segment adjacent the high-frequency segment arranged on the front face, the top face, the back face and the bottom face of the carrier; and
a printed circuit board comprising a top side, a left slanting side, a slanting bottom side, and a right long side, a recessed side, and a right short side, with a first face and a second face, the first face having a first ground metal face, a micro strip and an open area with two fixed ends, the micro strip having a front section and a rear section, wherein the front section extends into the first ground metal face such that a gap is defined between the micro strip and the first ground metal faces and comprises a through hole.

US Pat. No. 10,483,642

COMPOSITE RIGHT/LEFT-HANDED TRANSMISSION LINE ANTENNA

HUAWEI TECHNOLOGIES CO., ...

1. A composite right/left-handed transmission line antenna, comprising:a first radiator;
a second radiator coupled to the first radiator, wherein the first radiator and second radiator together form a ring shape;
a feed-in point of the first radiator or the second radiator;
a matching circuit coupled to the feed-in point; and
a high-frequency splitter coupled to the first radiator or the second radiator.

US Pat. No. 10,483,639

COMMUNICATION DEVICE AND ANTENNA ASSEMBLY THEREOF

ASUSTEK COMPUTER INC., T...

1. A communication device, comprising:a metal rim;
a device metal member, disposed in the metal rim; and
an antenna assembly, comprising:
an insulating substrate, disposed between the device metal member and the metal rim;
two electrical coupling portions, disposed at two opposite ends of the insulating substrate and electrically coupled to the device metal member and the metal rim, a sealed slot section is enclosed by the two electrical coupling portions, the device metal member, and the metal rim;
a feeding part, disposed on the insulating substrate and electrically coupled to the metal rim, so as to divide the sealed slot section into a first slot section and a second slot section whose length is less than that of the first slot section, the feeding part is configured to activate resonance modes of the first slot section in a first frequency band and a second frequency band and activate a resonance mode of the second slot section in a third frequency band; and
a feeding signal source, disposed on the insulating substrate, located between the feeding part and the device metal member, and electrically coupled to the feeding part and the device metal member.

US Pat. No. 10,483,637

METHOD AND APPARATUS FOR BEAM-STEERABLE ANTENNA WITH SINGLE-DRIVE MECHANISM

Viasat, Inc., Carlsbad, ...

14. An antenna assembly comprising:an antenna comprising a reflector and a feed oriented for direct illumination of the reflector to produce a beam;
an antenna positioner comprising a tilt assembly to tilt the reflector relative to the feed to the move the beam in a spiral pattern via drive applied to a single drive interface by a directional motor in response a control signal; and
an auto-peak device to:
provide the control signal to tilt the tilt assembly in a plurality of tilt positions to move the beam along the spiral pattern while measuring corresponding signal strength of a signal communicated via the antenna at each of the plurality of tilt positions;
select a tilt position from the plurality of tilt positions based on the measured signal strength; and
provide the control signal to tilt the tilt assembly to the selected tilt position.

US Pat. No. 10,483,632

DEVICE FOR TRANSMITTING AND/OR RECEIVING RADIOFREQUENCY SIGNALS

INSIGHT SIP, Grasse (FR)...

1. An apparatus for transmitting and/or receiving radiofrequency signals comprising at least a broadband antenna and a substrate; the antenna comprising at least a first radiating surface and being superimposed on the ground plane, the ground plane being located on a first face of the substrate, at least a side tongue of a power supply and at least a side wall connected to at least the first radiating surface, wherein:the antenna comprises at least a second radiating surface excitable by coupling with the first radiating surface,
the side wall is connected to a coupling trace located on a second face of the substrate, the second face opposite to the first face of the substrate, and the side wall and the coupling trace being configured to act as a capacitive coupling between at least the first radiating surface, the second radiating surface and the ground plane, and
wherein the coupling trace is configured to form a coupling capacitor whose value is ?S/e where ? is the dielectric constant of the dielectric material constituting the substrate. S is the surface of the coupling trace and e is the thickness between the coupling trace located on the second face of the substrate and the ground plane located on the first face of the substrate, and
wherein the first face of the substrate is a lower surface of the substrate and the second surface of the substrate is a surface of the substrate above the first face.

US Pat. No. 10,483,628

ANTENNA AND ATTACHMENT METHOD FOR RECHARGEABLE IMPLANTABLE MEDICAL DEVICE

Pacesetter, Inc., Sylmar...

1. An implantable medical device, comprising:a device housing having electronic components therein;
a feedthrough assembly joined to the device housing;
an antenna assembly; and
a header body mounted to the device housing and enclosing the antenna assembly and feedthrough assembly,
the antenna assembly including an inner conductor, an outer conductor and a dielectric material disposed between the inner conductor and the outer conductor, wherein the inner conductor, the dielectric material and the outer conductor are concentrically arranged relative to one another about a longitudinal axis to form a tubular coaxial structure.

US Pat. No. 10,483,624

ANTENNA SYSTEM AND MOBILE TERMINAL

AAC Technologies Pte. Ltd...

1. An antenna system, comprising: a metal rear cover, a first feeding point and a system ground, wherein a U-shaped slot is arranged at a bottom of the metal rear cover, and the U-shaped slot divides the metal rear cover into a radiation portion and a grounding portion, the grounding portion is connected to the system ground, the radiation portion comprises a first end and a second end, and both the first end and the second end are connected to the grounding portion, a breaking joint is defined at the radiation portion, and the radiation portion is electrically connected to the first feeding point, so as to form a main antenna,wherein the main antenna has a first working frequency band, a second working frequency band and a third working frequency band, wherein the first working frequency band is 700 MHz-960 MHz, the second working frequency band is 1710 MHz-2700 MHz, and the third working frequency band is 3300 MHz-3800 MHz,
wherein the first feeding point and the breaking joint divide the radiation portion into a first section, a second section and a third section, wherein the first section is a portion of the radiation portion from the first end to the first feeding point, the second section is a portion of the radiation portion from the first feeding point to the breaking joint, and the third section is a portion of the radiation portion from the breaking joint to the second end, and
wherein a main radiator of the first working frequency band comprises the first section and the second section, a main radiator of the second working frequency band comprises the second section and the third section, and a main radiator of the third working frequency band comprises the first section, the second section and the third section.

US Pat. No. 10,483,623

ANTENNA DEVICE AND ELECTRONIC APPARATUS

Murata Manufacturing Co.,...

1. An antenna device comprising:a planar metallic member; and
an antenna coil that is wound into a loop or a spiral,
wherein the metallic member has an opening whose entire periphery is surrounded by a metal,
wherein the antenna coil is disposed on a side of one principal surface of the metallic member such that both of an inner region and an outer region of the antenna coil overlap the opening in a plan view that is in a direction perpendicular to a plane defined by the side of the one principal surface of the metallic member, and
wherein a magnetic sheet is provided on a side of the antenna coil that is opposite to the metallic member.

US Pat. No. 10,483,621

ANTENNA AND WIRELESS COMMUNICATIONS ASSEMBLY

PERASO TECHNOLOGIES INC.,...

1. An antenna assembly, comprising:a support member having (i) a first surface, (ii) an opposing second surface configured to couple the antenna assembly to an antenna assembly support member, and (iii) a set of electrical contacts;
an antenna carried on the first surface of the support member and electrically connected to the set of electrical contacts, the antenna including (i) a powered element and (ii) a parasitic element;
a conductive inner ring element carried on the first surface and surrounding the antenna; and
a dielectric outer ring element mounted on the first surface and surrounding the conductive inner ring; wherein the dielectric outer ring has an inside perimeter that surrounds an outside perimeter of the conductive inner ring element.

US Pat. No. 10,483,616

ILLUMINATION DEVICE

PANASONIC INTELLECTUAL PR...

1. An illumination device, comprising:a substrate including a light-emitter;
an instrument main body including a substrate arrangement surface, the substrate being on the substrate arrangement surface;
a cover that is attached to the instrument main body, covers the substrate, and is transparent;
an antenna on the cover and configured to receive a signal from an outside of the illumination device;
a driver on the instrument main body and configured to supply power to the light-emitter; and
a controller configured to control the power supplied from the driver to the light-emitter based on the signal received by the antenna,
wherein the cover includes a diffusion factor from 40% to 90%, and
the cover includes a side surface extending in a direction intersecting with the substrate arrangement surface, and the antenna is on the side surface.

US Pat. No. 10,483,614

EHF HINGE ASSEMBLIES

KEYSSA SYSTEMS, INC., Ca...

1. A hinge assembly for use in propagating radio frequency signals, the hinge assembly comprising:a first subassembly comprising a first waveguide, wherein the first waveguide comprises a first self-sustaining signal propagation portion and a first co-dependent signal propagation portion;
a second subassembly that interfaces with the first subassembly and moves at an angular rotation with respect to the first subassembly, the second subassembly comprising a second waveguide, wherein the second waveguide comprises a second self-sustaining signal propagation portion and a second co-dependent signal propagation portion;
wherein, in a first range of angular rotation, the first and second co-dependent signal propagation portions are in direct contact with each other to form a propagation coupling between the first and second waveguides that enables the radio frequency signals to propagate through the hinge assembly; and
wherein, in a second range of angular rotation, the first and second co-dependent signal propagation portions are not in direct contact with each other and the radio frequency signals are not able to propagate through the hinge assembly.

US Pat. No. 10,483,612

SPLITTER AND ELECTRONIC DEVICE

WISTRON NEWEB CORP., Hsi...

1. A splitter with a common port, a first port, and a second port, comprising:a common transmission line, coupled between the common port and a common node;
a first transmission line, coupled between the first port and a first node;
a second transmission line, coupled between the second port and a second node;
a third transmission line, coupled between the common node and the first node;
a fourth transmission line, coupled between the common node and the second node;
a resistor, coupled between the first node and the second node; and
a first reactance circuit, coupled between the first node and the second node, wherein the first reactance circuit comprises a first inductor and a first capacitor coupled in series, but the first reactance circuit does not comprise any resistor;
wherein the splitter operates at a central frequency, and the first reactance circuit is configured to reduce isolation between the first port and the second port at the central frequency.

US Pat. No. 10,483,610

WAVEGUIDE MOUNT FOR MICROSTRIP CIRCUIT AND MATERIAL CHARACTERIZATION

United States of America ...

1. A superconducting film device comprising:a superconducting microstrip device including:
a silicon substrate disposed on a silicon handling wafer;
a microstrip feed line; and
a plurality of superconducting microstrip resonators and a half-wavelength resonator, disposed on said silicon substrate and coupled to said microstrip feed line;
wherein said silicon substrate is a single-crystal silicon substrate of 50 ?m in thickness.

US Pat. No. 10,483,609

DIELECTRIC WAVEGUIDE HAVING A CORE AND CLADDING FORMED IN A FLEXIBLE MULTI-LAYER SUBSTRATE

Texas Instruments Incorpo...

1. A system comprising:a multilayer substrate having at least a core layer having a first dielectric constant value, a top layer adjacent the core layer and a bottom layer opposite adjacent the core layer, wherein the top layer and the bottom layer have a dielectric constant value that is lower than the first dielectric constant value;
a dielectric waveguide (DWG) formed within the multilayer substrate, wherein the dielectric waveguide comprises:
a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer, such that the dielectric core member has the first dielectric constant value; and
a cladding surrounding the dielectric core member formed by the top layer and the bottom layer infilling the corresponding slot portions of the core layer, wherein the cladding has a dielectric constant value that is lower than the first dielectric constant value.

US Pat. No. 10,483,602

BATTERY HOUSING FOR A LITHIUM-ION BATTERY

FORD GLOBAL TECHNOLOGIES,...

1. A vehicle comprising:an engine disposed within an engine compartment;
a traction motor coupled to a battery; and
a housing disposed within the engine compartment and containing the battery, the housing comprising a shell having solid thermal insulation surrounding the battery and forming first and second slots between the battery and the shell, the first slot being configured for connecting to ambient, and the second slot being configured for connecting to a vehicle cooling system, wherein the housing further comprises braces between the shell and the solid thermal insulation.

US Pat. No. 10,483,599

MAGNETICALLY ATTACHED BATTERY PACK WITH AUDIO INTERFACE

Scosche Industries, Inc.,...

1. A device for charging a mobile device, comprising:a housing defined by a distal side and a proximal side separated by a perimeter wall;
a battery internal to the housing, the battery being receptive to power from an alternating current power source;
a single digital interface integrated in to the housing and in electrical communication with the battery;
a digital to analog converter with an input connected to the single digital interface and an output, the digital to analog converter being receptive to a digital signal from the single digital interface;
an analog audio jack integrated in to the housing and connected to the output of the digital to analog converter, the analog audio jack being receptive to a two channel analog signal from the digital to analog converter to drive a load with an impedance of an audio transducer preamplifier; and
a digital port which passes power from a power source to the battery;
wherein with the mobile device connected to the single digital interface, the power from the battery is relayed to the mobile device via the single digital interface, and concurrently, the digital signal being received on the single digital interface from the mobile device is relayed to the input of the digital to analog converter, and connecting a first sensor to the digital port and a second sensor to the single digital interface which sense when there is a connector in the digital port or when the single digital interface is connected to a mobile device, or both.

US Pat. No. 10,483,597

FIBER-CONTAINING MATS WITH ADDITIVES FOR IMPROVED PERFORMANCE OF LEAD ACID BATTERIES

Johns Manville, Denver, ...

1. A fiber-containing mat for a lead acid battery, the mat comprising:a plurality of fibers;
a binder holding the plurality of fibers together in the fiber-containing mat; and
one or more additives incorporated into the fiber-containing mat, wherein the one or more additives comprise benzyl benzoate.

US Pat. No. 10,483,596

SECONDARY BATTERY WITH HYDROXIDE-ION-CONDUCTING CERAMIC SEPARATOR

NGK Insulators, Ltd., Na...

1. A secondary battery comprising:a positive electrode;
a negative electrode;
an alkaline electrolytic solution;
a ceramic separator that is composed of a hydroxide-ion-conductive inorganic solid electrolyte comprising a layered double hydroxide and separates the positive electrode from the negative electrode;
a porous substrate disposed on at least one surface of the ceramic separator; and
a container accommodating at least the negative electrode and the alkaline electrolytic solution,
wherein the inorganic solid electrolyte is in the form of a membrane or layer densified enough to have water impermeability, and the porous substrate has a thickness of 100 to 1,800 ?m.

US Pat. No. 10,483,594

POSITIVE ELECTRODE PLATES FOR NONAQUEOUS ELECTROLYTE SECONDARY BATTERIES, AND NONAQUEOUS ELECTROLYTE SECONDARY BATTERIES

PANASONIC CORPORATION, K...

1. A positive electrode plate for wound nonaqueous electrolyte secondary batteries, comprising:a current collector, and
a mixture layer disposed on the current collector,
the mixture layer having a thin portion with a thickness of less than 200 ?m disposed on an inner coil half of the current collector and a thick portion having a larger thickness than the thin portion, the thick portion having a yield loop height H measured by a stiffness test of 6 mm

US Pat. No. 10,483,593

WOUND ELECTRODE GROUP, ELECTRODE GROUP, AND NONAQUEOUS ELECTROLYTE BATTERY

KABUSHIKI KAISHA TOSHIBA,...

1. A nonaqueous electrolyte battery comprising an electrode group comprising a stack comprising:a positive electrode;
a negative electrode or negative electrodes, each comprising a negative electrode current collector and a negative electrode layer provided on the negative electrode current collector, wherein the negative electrode layer comprises a lithium titanium composite oxide; and
a separator,
wherein the electrode group satisfies the following relational formulae (I) to (III):
10?a1/b1?16  (I);
0.7?D1/E1?1.4  (II); and
E1?85  (III),
wherein a1 is a thickness of the stack; b1 is a thickness of the negative electrode current collector when the stack comprises the negative electrode, or is a total thickness of the negative electrode current collectors when the stack comprises the negative electrodes; D1 is a thickness of the positive electrode; and E1 is a thickness of the negative electrode, wherein a unit of a1 is mm, a unit of b1 is mm, a unit of D1 is ?m, and a unit of E1 is ?m;
a nonaqueous electrolyte; and
a metal container housing the electrode group and the nonaqueous electrolyte.

US Pat. No. 10,483,590

ELECTROLYTE FOR LITHIUM ION BATTERY AND LITHIUM ION BATTERY INCLUDING THE SAME

OPTIMUM BATTERY CO., LTD....

1. An electrolyte for lithium ion battery, comprising:a mixture of organic solvents consisting of ethylene carbonate, ethyl methyl carbonate, dimethyl carbonate and carboxylate ester, wherein a mass ratio of ethylene carbonate, ethyl methyl carbonate, dimethyl carbonate and carboxylate ester is (20%-30%):(45%-55%):(10%-20%):(5%-15%);
a mixture of additives consisting of vinylene carbonate, propane sultone, fluorinated ethylene carbonate and perfluorohexylsulfonyl fluoride; and
a lithium salt.

US Pat. No. 10,483,588

GEL ELECTROLYTE MEMBRANE AND METHOD FOR FORMING THE SAME, ELECTRODE ASSEMBLY, GEL POLYMER LITHIUM-ION BATTERY AND ELECTRIC VEHICLE

Interstellar Solid-State ...

1. A method for forming a gel electrolyte membrane, comprising:providing a cathode and/or an anode;
forming a gel electrolyte precursor; and
forming the gel electrolyte membrane on at least one surface of the electrode by the gel electrolyte precursor through growing in situ;
wherein the gel electrolyte precursor comprises a liquid mixture A and a liquid mixture B, the liquid mixture A comprising a polymer matrix and an organic solvent, and the liquid mixture B comprising a lithium salt, a plasticizer, and an additive;
wherein the gel electrolyte precursor is formed by the following steps:
pre-stirred the liquid mixture A and the liquid mixture B respectively at a speed of 100 to 5000 rpm and at a temperature of ?10 to 30° C. for 0.5 to 96 h until the liquid mixture A and the liquid mixture B are respectively dissolved; and
mixing the dissolved liquid mixture A and liquid mixture B and stirring at a speed of 100 to 5000 rpm and at a temperature of ?10 to 30° C. for 0.5 to 96 h until the mixture of the liquid mixture A and the liquid mixture B are homogenously dispersed.

US Pat. No. 10,483,587

SULFIDE SOLID ELECTROLYTE

IDEMITSU KOSAN CO., LTD.,...

1. A sulfide solid electrolyte, comprising lithium, phosphorus, sulfur, and two or more of elements X selected from the group consisting of halogen elements,wherein the sulfide solid electrolyte comprises an argyrodite-type crystal structure, and
wherein a molar ratio of the sulfur to the phosphorus, b (S/P), and a molar ratio of the elements X to the phosphorus, c (X/P), satisfy formula (1):
0.23

US Pat. No. 10,483,586

ALL-SOLID-STATE BATTERY USING SODIUM ION INTERCALATION CATHODE WITH LI/NA EXCHANGING LAYER

TOYOTA MOTOR EUROPE, Bru...

1. An all-solid-state battery comprising the following elements in order:a positive electrode active material layer (5) comprising a sodium-containing cathode material;
a solid electrolyte layer (4) comprising a sulfide-based sodium-containing solid electrolyte material;
a sulfide-based mixture layer (3);
a solid electrolyte layer (2) comprising a sulfide-based lithium-containing solid electrolyte material;
a negative electrode active material layer (1) comprising a lithium-containing anode material,
wherein the mixture layer (3) comprises a physical mixture of a sulfide-based sodium-containing solid electrolyte material and a sulfide-based lithium-containing solid electrolyte material.

US Pat. No. 10,483,585

ION-CONDUCTING GLASS CERAMIC HAVING GARNET-LIKE CRYSTAL STRUCTURE

SCHOTT AG, Mainz (DE)

1. A lithium-ion conducting glass ceramic comprising a garnet-like main crystal phase having an amorphous proportion of at least 5 wt.-%, wherein said garnet-like main crystal phase has the chemical formula:Li7+x?yMxIIM3?xIIIM2?yIVMyVO12,
wherein MII is a bivalent cation, MIII a trivalent cation, MIv a tetravalent cation, and MV a pentavalent cation.

US Pat. No. 10,483,581

ELECTROCHEMICAL ENERGY STORAGE SYSTEMS AND METHODS FEATURING LARGE NEGATIVE HALF-CELL POTENTIALS

Lockheed Martin Energy, L...

1. A flow battery comprising:a first half-cell comprising:
a first aqueous electrolyte comprising a first redox active material at a concentration in a range of from 0.75 M to about 2.5 M, and a first carbon electrode in contact with the first aqueous electrolyte, the first electrolyte having a pH in the range of from 8 to 13;
a second half-cell comprising:
a second aqueous electrolyte comprising a second redox active material, and a second carbon electrode in contact with the second aqueous electrolyte; and
a separator disposed between the first half-cell and the second half-cell;
wherein the first half-cell has a half-cell potential ranging between ?0.3 V and ?0.7 V with respect to a reversible hydrogen electrode, and
the first redox active material exhibits substantially reversible electrochemical kinetics; wherein
the half-cell potential is the average measured potential of forward and reverse peaks of a cyclic voltammogram of the first aqueous electrolyte, when measured using an ex-situ apparatus using a flat glassy carbon disc electrode at a scan rate of 100 mV/s; and wherein
substantially reversible electrochemical kinetics refers to a condition in which the first aqueous electrolyte exhibits a voltage difference between the anodic and cathodic peaks of less than 0.3 V, when measured by cyclic voltammetry using an ex-situ apparatus using a flat glassy carbon disc electrode at a scan rate of 100 mV/s.

US Pat. No. 10,483,579

SOLID OXIDE FUEL CELL

NISSAN MOTOR CO., LTD., ...

1. A solid oxide fuel cell comprising:a metal support which is formed from a porous metal substrate and which supports a power generation cell, wherein
the metal support includes a power generating area in which the power generation cell is disposed, a buffer area which is formed on an outer side of the power generating area in an in-plane direction, and an outer peripheral area which is formed on an outer side of the buffer area in the in-plane direction, the metal support is located on the anode side of the power generation cell, a separator is located on the anode side of the power generation cell such that a void region is formed between the separator and the buffer area of the metal support,
the power generation cell is formed as a stacked body of an anode electrode, a solid oxide electrolyte, and a cathode electrode, and
a pore in the metal support in the buffer area is filled with a filler material with a thermal conductivity lower than that of a formation material of the metal support.

US Pat. No. 10,483,576

POLYMER ELECTROLYTE MEMBRANE

LG CHEM, LTD., Seoul (KR...

1. A polymer electrolyte membrane comprising:a polymer including a unit represented by the following Chemical Formula 1; and
inorganic particles:

wherein, in Chemical Formula 1, A is —SO3H, —SO3?M+, —COOH, —COO?M+, —PO3H2, —PO3H?M+, —PO32?2M+, —O(CF2)mSO3H, —O(CF2)mSO3?M+, ?O(CF2)mCOOH, ?O(CF2)mCOO?M+, —O(CF2)mPO3H2, —O(CF2)mPO3H?M+or —O(CF2)mPO32?2M+;
m is an integer of 2 to 6;
M is a group 1 element;
R1 and R2 are the same as or different from each other, and each independently a halogen group; and
n is an integer of 2 to 10, and structures in the 2 to 10 parentheses are the same as or different from each other.

US Pat. No. 10,483,574

FUEL CELL SYSTEM WITH MERGED GASES FOR LEAK DETECTION

PANASONIC INTELLECTUAL PR...

1. A fuel cell system comprising:a reformer that generates a hydrogen containing gas from a fuel gas and includes a burner;
a fuel cell that uses the hydrogen containing gas and an oxidant gas to generate power;
an exhaust gas route for an exhaust gas discharged from the fuel cell to flow;
an air supplier that suctions air within the fuel cell system;
an air supply route for the air suctioned by the air supplier;
a merging part that is a part where the exhaust gas flowing in the exhaust gas route and the suctioned air flowing in the air supply route merge with each other;
a discharge route that discharges a mixed gas composed of the exhaust gas and the suctioned air having merged at the merging part to the atmosphere;
a gas-liquid separator disposed on the exhaust gas route between the fuel cell and the merging part; and
a combustible gas detector that is provided in the discharge route and detects concentration of a combustible gas contained in the mixed gas, wherein:
with respect to a flow of the suctioned air flowing in the air supply route and the discharge route, from an upstream side, the air supplier, the merging part, and the combustible gas detector are disposed in this order,
the exhaust gas includes an anode exhaust gas discharged from an anode of the fuel cell, and a cathode exhaust gas discharged from a cathode of the fuel cell,
the exhaust gas route includes an anode exhaust gas route for the anode exhaust gas and a cathode exhaust gas route for the cathode exhaust gas,
the burner is disposed on the anode exhaust gas route to combust the anode exhaust gas and exhaust a combustion gas,
a condenser is disposed on the cathode exhaust gas route,
the anode exhaust gas route downstream of the burner is connected to the cathode exhaust gas route at a position upstream of the condenser,
the cathode exhaust gas route bypasses the burner and is connected to the condenser,
the gas-liquid separator is a condensed water tank storing water obtained from the cathode exhaust gas and the combustion gas by the condenser, and
the condensed water tank is connected to the reformer by a condensed water route.

US Pat. No. 10,483,572

FLOW CONTROL METHOD OF COOLING MEDIUM IN A FUEL CELL SYSTEM, AND FUEL CELL SYSTEM

Toyota Jidosha Kabushiki ...

1. A fuel cell system, comprising:a fuel cell;
an internal flow path of a cooling medium formed inside the fuel cell;
an external flow path formed outside the fuel cell that forms a circulation flow path of the cooling medium by being connected to the internal flow path; and
a control device programmed to:
acquire a temperature of the fuel cell and identify a calorific value of the fuel cell,
during a time period when the temperature of the fuel cell is lower than an end temperature that is predetermined as a temperature at the time of end of a warm-up operation, determine whether or not an inlet temperature, which is the temperature of the cooling medium at an inlet to the internal flow path within the circulation flow path, is equal to or above a lower-limit temperature of a temperature range in which generated water does not freeze within the fuel cell,
when it is determined that the inlet temperature is equal to or above the lower-limit temperature during the time period, execute a first adjustment of a flow rate of the cooling medium in the circulation flow path so as to become greater than a normal flow rate corresponding to the calorific value of the fuel cell,
when it is determined that the inlet temperature is not equal to or above the lower-limit temperature during the time period, execute a second adjustment of the flow rate of the cooling medium in the circulation flow path to be a flow rate that is less than the normal flow rate and that increases in accordance with an increase in the calorific value of the fuel cell, and
adjust the flow rate of the cooling medium in the circulation flow path to be equal to the normal flow rate when the temperature of the fuel cell becomes equal to or above the end temperature, wherein the normal flow rate is a flow rate of the cooling medium determined based on the calorific value of the fuel cell.

US Pat. No. 10,483,570

FUEL CELL AND METHOD FOR OPERATING THE SAME

LG Electronics Inc., Seo...

1. A fuel cell, comprising:a stack comprising:
an electrolyte membrane;
a fuel electrode that is disposed on a first side of the electrolyte membrane, the fuel electrode comprising a first fuel port and a second fuel port that are communicative with each other via a fuel flow path; and
an air electrode disposed on a second side, opposite the first side, of the electrolyte membrane, and comprising a first air port and a second air port that are communicative with each other via an air flow path;
a first fuel feeder communicative with the first fuel port;
a second fuel feeder communicative with the second fuel port;
a first air feeder communicative with the first air port;
a second air feeder communicative with the second air port;
a fuel switching unit provided between the first fuel feeder and the second fuel feeder and configured to switch a fuel supply direction to a first direction from the first fuel feeder to the second fuel feeder, or reversely to a second direction from the second fuel feeder to the first fuel feeder; and
an air switching unit provided between the first air feeder and the second air feeder and configured to switch an air supply direction to a third direction from the first air feeder to the second air feeder, or reversely to a fourth direction from the second air feeder to the first air feeder,
wherein the first fuel port of the stack is connected to a first end of a first fuel pipe, and the second fuel port of the stack is connected to a first end of a second fuel pipe,
wherein a first fuel switching valve is provided on a second end of the first fuel pipe and a first fuel supply pipe and a second fuel discharge pipe are connected to the first fuel switching valve,
wherein a second fuel switching valve is provided on a second end of the second fuel pipe and a second fuel supply pipe and a first fuel discharge pipe are connected to the second fuel switching valve,
wherein the first fuel supply pipe and the second fuel supply pipe are connected to a fuel supply valve that is configured to selectively direct a fuel supply direction,
wherein the first fuel discharge pipe and the second fuel discharge pipe are connected to a fuel discharge valve that is configured to selectively direct a fuel discharge direction,
wherein the fuel supply valve and the fuel discharge valve are configured to be jointly controlled,
wherein the first air port of the stack is connected to a first end of a first air pipe, and the second air port of the stack is connected to a first end of a second air pipe,
wherein a first air switching valve is provided on a second end of the first air pipe, and a first air supply pipe and a second air discharge pipe are connected to the first air switching valve,
wherein a second air switching valve is provided on a second end of the second air pipe, and a second air supply pipe and a first air discharge pipe are connected to the second air switching valve,
wherein the first air supply pipe and the second air supply pipe are connected to an air supply valve that is configured to selectively direct an air supply direction,
wherein the first air discharge pipe and the second air discharge pipe are connected to an air discharge valve that is configured to selectively direct an air discharge direction, and
wherein the air supply valve and the air discharge valve are configured to be jointly controlled.

US Pat. No. 10,483,567

MECHANICAL ENERGY STORAGE IN FLOW BATTERIES TO ENHANCE ENERGY STORAGE

Saudi Arabian Oil Company...

1. A hybrid flow redox battery system comprising an electrochemical cell, an anolyte tank, a catholyte tank, one or more tank separators, a plurality of electrolyte pathways, one or more turbines, and one or more power generation circuits, wherein:the electrochemical cell comprises an ion-exchange membrane positioned between and electrochemically engaged with an anode and a cathode;
at least one of the one or more power generation circuits is electrically coupled to the anode and the cathode;
the anolyte tank includes an upper anolyte opening and a lower anolyte opening positioned below the upper anolyte opening;
the catholyte tank includes an upper catholyte opening and a lower catholyte opening positioned below the upper catholyte opening;
one or more of the plurality of electrolyte pathways extend between the upper anolyte opening and the anode and extend between the lower anolyte opening and the anode to fluidly couple the anolyte tank to the anode;
one or more of the plurality of electrolyte pathways extend between the upper catholyte opening and the cathode and extend between the lower catholyte opening and the cathode to fluidly couple the catholyte tank to the cathode;
the one or more turbines are fluidly coupled to one or more of the plurality of electrolyte pathways;
the one or more tank separators are positioned within one or both of the anolyte tank and the catholyte tank; and
the one or more tank separators are translatable in a downward direction to induce electrolyte flow from one or both of the lower anolyte opening and the lower catholyte opening through the one or more turbines to hydroelectrically generate power.

US Pat. No. 10,483,563

CATHODE SUPPLY FOR A FUEL CELL

Volkswagen AG, Wolfsburg...

1. A cathode supply for a fuel cell of a fuel cell unit for a fuel cell system, the cathode supply comprising:a cathode supply path;
a cathode exhaust gas path; and
at least two fluid pumps for pumping a cathode operating medium for the fuel cell being fluido-mechanically coupled into the cathode supply path;
at least one first fluid pump of the at least two fluid pumps being drivable by enthalpy in a cathode exhaust gas of the fuel cell.

US Pat. No. 10,483,557

LAMINATE-TYPE POWER STORAGE ELEMENT AND CARD ELECTRONIC DEVICE

FDK Corporation, Tokyo (...

1. A laminate-type power storage element, comprising:an exterior body that is formed in a flat bag shape by welding a first laminated film and a second laminated film by thermocompression bonding; and
an electrode body that is sealed inside the exterior body, the electrode body having a sheet-shaped positive electrode and a sheet-shaped negative electrode, wherein
the first laminated film and the second laminated film each includes
a first resin layer that has a property of transmitting a laser beam,
a metal foil that is layered to the first resin layer, and
a second resin layer that is layered to the metal foil and has a thermal weldability,
the exterior body is configured such that the second resin layer of the first laminated film opposes the second resin layer of the second laminated film,
a label is formed in a surface of the metal foil facing the first resin layer of at least on of the first laminated film or the second laminated film by laser marking without altering the first resin layer of the first laminated film or the second laminated film by the laser beam, and
the label is formed at a region where the first laminated film and the second laminated film are welded.

US Pat. No. 10,483,552

CATALYST COMPRISING COBALT CORE AND CARBON SHELL FOR ALKALINE OXYGEN REDUCTION AND METHOD FOR PREPARING THE SAME

Korea Institute of Scienc...

1. A method for preparing a catalyst, consisting of:(a) preparing a dispersion by dispersing a carbon support in a solvent;
(b) preparing a mixture solution by mixing the dispersion with a cobalt precursor and oleylamine;
(c) preparing a catalyst precursor by heat-treating the mixture solution at a low temperature of 250-350° C. under an inert gas atmosphere, wherein an oleylamine-coated cobalt oxide nanoparticle is supported on the carbon support in the catalyst precursor; and
(d) preparing a catalyst by heat-treating the catalyst precursor at a high temperature of 550-800° C. under the inert gas atmosphere, wherein the catalyst contains the carbon support and a core-shell nanoparticle supported on the carbon support,
wherein the core of the core-shell nanoparticle is cobalt metal without having the heterogeneous element and the shell of the core-shell contains carbon.

US Pat. No. 10,483,549

METHOD OF MANUFACTURING ELECTRODE CURRENT COLLECTOR FOR SECONDARY BATTERY AND ELECTRODE INCLUDING ELECTRODE CURRENT COLLECTOR MANUFACTURED USING THE METHOD

LG Chem, Ltd., (KR)

1. A method of manufacturing a current collector for an electrode for a secondary battery, the method comprising:preparing a carbon nanotube (CNT) dispersion by dispersing CNTs in a dispersion solvent;
forming a CNT film on a water surface by spraying the CNT dispersion onto water;
forming a CNT coating layer on a metal foil by unwinding the metal foil and passing the metal foil through the water at an angle such that one surface of the metal foil is brought into contact with one end of the CNT film formed on the water surface; and
curing the CNT coating layer by heat treatment while rewinding the metal foil with the CNT coating layer formed thereon.

US Pat. No. 10,483,540

LITHIUM COMPLEX OXIDE FOR LITHIUM SECONDARY BATTERY POSITIVE ACTIVE MATERIAL AND METHOD OF PREPARING THE SAME

ECOPRO BM CO., LTD., Chu...

1. A lithium complex oxide secondary particle formed by coagulation of a plurality of primary particles, wherein Co concentration at a boundary of the primary particle is higher than Co concentration in an internal part of the primary particle,wherein the secondary particle has a bound energy (P1) of spin-orbit-spit 2p3/2 peak and a bound energy (P2) of 2p1/2 peak in a Co 2p core-level spectrometry obtained through XPS measurement,
wherein the P1 and the P2 are ranged respectively in 779 eV?P1?780 eV and 794 eV?P2?795 eV, and
wherein a primary particle located at a surface part of the secondary particle has a Co concentration gradient reduced by 0.05 to 0.07 mol % per nm toward a center of the primary particle from a surface of the primary particle.

US Pat. No. 10,483,539

POSITIVE ELECTRODE ACTIVE MATERIAL FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERIES, PRODUCTION PROCESS THEREFOR, AND NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY

SUMITOMO METAL MINING CO....

1. A positive electrode active material for a non-aqueous electrolyte secondary battery, the positive electrode active material comprising hexagonal lithium-nickel-cobalt-manganese composite oxide particles represented by the general formula: Li1+sNixCoyMnzMtO2 wherein:
s, x, y, z, and t in the formula fall within the ranges of: ?0.05?s?0.20; 0.1?x?0.7; 0.1?y?0.5; 0.1?z?0.5; and 0?t?0.05, and x, y, z, and t meet x+y+z+t=1,
M in the formula represents one or more additive elements selected from the group consisting of Ca, Mg, Al, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, and W,
the lithium-nickel-cobalt-manganese composite oxide particles have a layered structure comprising secondary particles with aggregated primary particles,
the secondary particles each comprises an outer-shell part that has a high manganese concentration and a central part that has a low manganese concentration that is lower than the high manganese concentration in the outer-shell part of the secondary particle,
the primary particles constitute the outer-shell parts of the secondary particles,
each of the primary particles comprises an outer peripheral part that has a low manganese concentration and an inner part that has a high manganese concentration, and
a ratio of the high manganese concentration in the inner part of the primary particle to the low manganese concentration in the outer peripheral part of the primary particle is in a range of from 1.5 to 2.5.

US Pat. No. 10,483,538

MIXED OXIDE CONTAINING A LITHIUM MANGANESE SPINEL AND PROCESS FOR ITS PREPARATION

Johnson Matthey Public Li...

1. A mixed oxide containinga) a mixed-substituted lithium manganese spinel as a first constituent in which a first portion of the manganese lattice sites are occupied by lithium ions and
b) a boron-oxygen compound as a second constituent,
wherein the mixed oxide is a single-phase homeotype mixed crystal comprising the constituents a) and b), wherein the second constituent is in the same phase as the first constituent, and
wherein the mixed oxide has a composition satisfied by the following formula:
[(Li1-aMa)(Mn2-c-dLicGd)Ox].(bB2O3.f*bLi2O)
wherein:
0?a<0.1;
d<1.2;
3.5 0.01 0 1 M is at least one element selected from the group of Zn, Mg and Cu; and
G is at least one element selected from the group of Al, Mg, Zn, Co, Ni, Cu and Cr; and
wherein in the mixed-substituted lithium manganese spinel an element of G occupying a second portion of the manganese lattice sites is Ni or Co, wherein when Ni is present, the contribution of Ni to “d” is 0.5+/?0.1 or when Co is present, the contribution of Co to “d” is 1+/?0.2, and
the size of the primary crystallites of the mixed oxide, measured as D50, is at least 0.5 ?m.

US Pat. No. 10,483,535

APPARATUS COMPRISING A PLURALITY OF NANOWIRES

Infineon Technologies AG,...

1. A nanowire array comprising:a carrier comprising silicon;
a diffusion barrier layer disposed over the carrier, the diffusion barrier layer comprising a nitride;
a plurality of nanowires disposed over the diffusion barrier layer, the nanowires of the plurality of nanowires comprising silicon;
wherein a majority of the nanowires of the plurality of nanowires are aligned substantially perpendicular to the diffusion barrier layer; and
a silicon layer disposed over the diffusion barrier layer, wherein the nanowires of the plurality of nanowires are formed over the silicon layer.

US Pat. No. 10,483,532

BINDER-FREE AND CARBON-FREE NANOPARTICLE CONTAINING COMPONENT, METHODS AND APPLICATIONS

CORNELL UNIVERSITY, Itha...

1. An electrochemical apparatus comprising:a component comprising:
a substrate; and
a hollow core morphology transition metal based nanoparticle material layer located over the substrate and absent a binder material, absent a polymeric material, and absent a carbon material, wherein the hollow core morphology transition metal based nanoparticle material layer is first formed upon the substrate as a solid core morphology transition metal based nanoparticle material layer using an electrophoretic deposition method, and wherein the solid core morphology transition metal based nanoparticle material layer adhered upon the substrate is treated to provide the hollow core morphology transition metal based nanoparticle material layer;
wherein the electrochemical apparatus is selected from the group consisting of a battery, a fuel cell, a capacitor and a catalytic reactor.

US Pat. No. 10,483,530

CATHODE ACTIVE MATERIAL AND FLUORIDE ION BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A cathode active material used in a fluoride ion battery, the cathode active material comprising:a Ce element, a S element, and a F element; and
a composition represented by CeSF.

US Pat. No. 10,483,518

SECONDARY BATTERY INCLUDING PULL TAB PROTRUDING FROM BOTTOM

Samsung SDI Co., Ltd., Y...

1. A secondary battery, comprising:a battery cell;
a protection circuit module electrically connected to the battery cell;
a top case covering the protection circuit module;
a bottom case covering a bottom surface of the battery cell, the bottom case including a penetration groove located at a center of a bottom surface of the bottom case, and
a pull tab that includes a first region of the pull tab that protrudes to an outside of the bottom case, a second region of the pull tab inside the bottom case, the second region of the pull tab being between a first region of an upper surface of a bottom portion of the bottom case and the bottom surface of the battery cell, and a third region of the pull tab that passes through the penetration groove, the third region of the pull tab being between the first region of the pull tab and the second region of the pull tab.

US Pat. No. 10,483,511

METHOD FOR INSULATING A BATTERY MODULE

Robert Bosch GmbH, Stutt...

1. A method for insulating a battery module (100) which has a multiplicity of battery cells (10), having at least one foldable insulation element (20), the method comprising at least the following steps:a) forming from the insulation element (20) a first receptacle pocket (21) for receiving at least one battery cell (10),
b) closing the first receptacle pocket (21) by means of attachment sections (22) which are arranged laterally on the insulation element (20), as a result of which the battery cell (10) is surrounded at least on five sides by the insulation element (20), as a result of which the individual battery cell (10) is insulated with respect to an adjacent battery cell (10),
c) forming from the insulation element a second receptacle pocket for receiving the adjacent battery cell, the second receptacle pocket formed from the same insulation element as the first receptacle pocket, the second receptacle pocket formed adjacent to and seamlessly connected to the first receptacle pocket via the insulation element, and
d) closing the second receptacle pocket (21) by means of second attachment sections (22) which are arranged laterally on the insulation element (20) such that the adjacent battery cell (10) is surrounded at least on five sides by the insulation element (20) and is insulated with respect to an adjacent battery cell (10).

US Pat. No. 10,483,505

SHEET ATTACHMENT DEVICE FOR BATTERY PACKS

LG CHEM, LTD., Seoul (KR...

1. A sheet attachment device for attaching a label sheet and a sheathing sheet to a battery pack having a plate-shaped battery cell mounted in a pack case, the sheet attachment device comprising:a first loader for moving the battery pack in a direction perpendicular to a ground and in a direction parallel to the ground in order to attach the label sheet to the battery pack; and in
a first jig for fixing the battery pack moved by the first loader;
a first guide frame connected to the first jig via sub robots for guiding the first jig to a first process position;
a first sheet attachment jig for attaching the label sheet to one surface of the battery pack loaded on the first jig;
a rotator for rotating the battery pack having the label sheet attached to the one surface thereof 180 degrees upward and downward;
a pressing roller for pressing an unattached portion of the label sheet that has not been attached to the battery pack to an outer surface of the battery pack in order to attach the label sheet to the battery pack;
a second loader for moving the battery pack in a direction perpendicular to the ground and in a direction parallel to the ground in order to attach the sheathing sheet to the battery pack, the second loader receiving the battery pack from the pressing roller;
a first conveyor for conveying the battery pack having the label sheet attached thereto, which is transferred from the second loader;
a second jig for fixing the battery pack moved by the second loader;
a second guide frame connected to the second jig via sub robots for guiding the second jig to a second process position; and
a second sheet attachment jig for attaching the sheathing sheet to an opposite surface of the battery pack having the label sheet attached thereto, which is loaded on the second jig.

US Pat. No. 10,483,504

SEALED BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A sealed battery comprising:a power generation element;
a case member having a bottomed cylindrical shape, in which the power generation element is housed;
a lid member that closes an opening of the case member and is provided with a through hole;
a collector terminal member having one end connected with the power generation element inside the case member, and the other end that is arranged in the through hole and extended outside the lid member; and
an insulating member arranged between the lid member and the collector terminal member, wherein
the other end of the collector terminal member includes a connecting portion having a columnar shape, that goes through the through hole, and a flange portion that is arranged so as to be approximately parallel with the lid member,
the insulating member includes a cylindrical portion that is positioned between the through hole and the connecting portion and surrounds the connecting portion, and a flat plate portion that is positioned between the lid member and the flange portion, the cylindrical portion and the flat plate portion being integral with the insulating member,
the flat plate portion has a first projecting portion projecting towards the lid member, and a second projecting portion projecting towards the flange portion, the first projecting portion and the second projecting portion being integral with the insulating member,
in a sectional view taken along a virtual plane including a central axis of the connecting portion,
the first projecting portion is provided at a position where a first side of the first projecting portion is linearly symmetrical with a second side of the first projecting portion, opposite from the first side, with respect to the central axis,
the second projecting portion is provided at a position where a first side of the second projecting portion is linearly symmetrical with a second side of the second projecting portion, opposite from the first side, with respect to the central axis,
a peak of the first projecting portion is provided at a position closer to the central axis than a peak position of the second projecting portion
the first projecting portion is provided into a ring shape centering about the central axis,
the second projecting portion is provided into a ring shape centering about the central axis, and
the first projecting portion is in contact with a surface of the lid member and the second projecting portion is in contact with a surface of the collector terminal.

US Pat. No. 10,483,503

BATTERY PACKAGING MATERIAL

DAI NIPPON PRINTING CO., ...

1. A battery packaging material which comprises a laminate including at least a coating layer, a base material layer, an adhesive layer, a barrier layer and a sealant layer in this order, whereinthe coating layer is a cured product of a resin composition containing a thermosetting resin and a curing accelerator, and
the thermosetting resin is a benzoguanamine resin.

US Pat. No. 10,483,496

ELECTROLUMINESCENT DEVICES WITH IMPROVED OPTICAL OUT-COUPLING EFFICIENCIES

NATIONAL TAIWAN UNIVERSIT...

1. An organic electroluminescent device, comprising:an optically reflective concave structure, comprising:
a first optically reflective surface; and
a second optically reflective surface, intersecting said first optically reflective surface at an obtuse angle;
a first light propagation layer in direct contact with said first optically reflective surface and said second optically reflective surface, comprising:
a first refractive surface, parallel to and separated from said first optically reflective surface;
a second refractive surface, parallel to and separated from said second optically reflective surface; and
an electroluminescent area, disposed entirely within said first light propagation layer, between said first optically reflective surface and said first refractive surface, without directly contacting any of said first optically reflective surface, said second optically reflective surface, said first refractive surface and said second refractive surface; and
a second light propagation layer, disposed on the first light propagation layer, wherein said second light propagation layer has a greater refractive index than said electroluminescent area minus 0.2.

US Pat. No. 10,483,495

ORGANIC LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...

1. A lighting device, comprising:a first substrate; and
an organic light emitting diode on a first surface of the first substrate, the organic light emitting diode including a first electrode, an organic light emitting layer, and a second electrode, the organic light emitting diode being divided into a plurality of pixels, each of the pixels having a respective light emitting region,
wherein the first electrode is made of a transparent conductive material having a resistance value within a range of 2,800? to 5,500? in each pixel, and has light scattering particles dispersed therein.

US Pat. No. 10,483,493

ELECTRONIC DEVICE HAVING DISPLAY WITH THIN-FILM ENCAPSULATION

Apple Inc., Cupertino, C...

1. Apparatus, comprising:a glass substrate;
a thin-film encapsulation layer;
a layer of thin-film transistor circuitry including transistors and organic light-emitting diodes that is configured to form a pixel array that displays images, wherein the layer of thin-film transistor circuitry has a first surface that contacts the thin-film encapsulation layer and an opposing second surface that contacts the glass substrate;
a light-blocking layer, wherein the glass substrate layer has a first surface that is contacted by the thin-film transistor circuitry and has a second surface that is contacted by the light-blocking layer; and
a heat spreading layer, wherein the light-blocking layer is interposed between the heat spreading layer and the glass substrate.

US Pat. No. 10,483,492

DISPLAY DEVICE HAVING SEALING LAYER INCLUDING DETECTION ELECTRODE

Japan Display Inc., Toky...

1. A display device, comprising:a substrate having a first surface and a second surface opposite the first surface;
a pixel region provided on the first surface of the substrate in which a plurality of pixels is arranged;
a peripheral region provided outside of the pixel region on the first surface of the substrate;
an organic electroluminescence element arranged in each of the plurality of pixels;
a sealing layer covering a surface of the pixel region on an opposite side of a substrate side of the pixel region;
a first detection electrode extending in a first direction on a first inorganic insulating film above the pixel region on a side of the pixel region where the sealing layer is provided;
a second detection electrode extending in a second direction intersecting the first direction on a different layer than the first detection electrode; and
a polarization plate above the sealing layer, the polarization plate includes a polarizer having circular polarization,
wherein the organic electroluminescence element includes a pixel electrode, an organic layer provided above the pixel electrode, and an opposite electrode provided above the organic layer,
wherein the sealing layer includes at least an organic resin film, the first inorganic insulating film is provided above the opposite electrode and below the organic resin film, and a second inorganic insulating film provided is above the organic resin film,
wherein a first surface of the first inorganic insulating film is in contact with the opposite electrode,
a second surface of the first inorganic insulating film, opposite to the first surface of the first inorganic insulating film, is in contact with a first surface of the first detection electrode,
a second surface of the first detection electrode, opposite to the first surface of the first detection electrode, is in contact with a first surface of the organic resin film,
a second surface of the organic resin film, opposite to the first surface of the organic resin film, is in contact with a first surface of the second detection electrode,
a second surface of the second detection electrode, opposite to the first surface of the second detection electrode, is in contact with a first surface of the second inorganic insulating film,
wherein the pixel region and the peripheral region include at least one other inorganic insulating film on the substrate and at least one organic insulating film above the at least one other inorganic insulating film,
wherein the peripheral region includes an opening portion in which the at least one organic insulating film is removed, and the opening portion continuously surrounds the pixel region in a plan view,
wherein at least part of the first inorganic insulating film and the second inorganic insulating film are in contact with each other in the peripheral region,
wherein the organic resin film is sandwiched between the first inorganic insulating film and the second inorganic insulating film in the pixel region and an edge of the organic resin film is located in the opening portion, and
wherein the opposite electrode overlaps the opening portion.

US Pat. No. 10,483,486

FRAME SEALING GLUE, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A frame sealing glue, comprising:a frame sealing glue body having an inner layer portion and an outer layer portion; and
an intermediate film layer disposed between the inner layer portion and the outer layer portion;
wherein a plurality of enclosed spaces are formed by the intermediate film layer and the inner layer portion or the outer layer portion of the frame sealing glue body,
wherein the intermediate film layer comprises a wave-shaped curved line having a plurality of semicircular curved line portions, the wave-shaped curved line forming a discontinuous curved line such that the intermediate film layer is disconnected at a corner of an enclosed frame formed by the frame sealing glue,
wherein a peak and a valley of the wave-shaped curved line intersect with the inner layer portion and the outer layer portion of the frame sealing glue body, respectively, or with the outer layer portion and the inner layer portion of the frame sealing glue body, respectively,
wherein each of the inner layer portion and the outer layer portion is a continuous closed line, and
wherein the intermediate film layer is made of different material from the frame sealing glue body.

US Pat. No. 10,483,485

DEVICE FOR ENCAPSULATING A SENSITIVE DEVICE AND PROCESS FOR PRODUCING SAID DEVICE

1. An encapsulation device comprising at least one assembly containing particles comprising at least a first material, said assembly having an open porosity,the particles being distributed to form a hexagonal or face-centred cubic stack of said particles wherein a degree of compactness of said particles in the stack is greater than around 50%, and
the particles being at least in part covered conformally by at least one layer referred to as an infiltration layer; wherein at least said infiltration layer is configured to close off the porosity of the assembly comprising the particles covered by said infiltration layer, in the form of pores that are not connected to one another.

US Pat. No. 10,483,484

ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE

Samsung Display Co., Ltd....

15. An organic electroluminescence display device comprising:a base member;
a display member disposed on the base member and including an organic electroluminescent element; and
an encapsulating member disposed on the display member and encapsulating the display member,
wherein the encapsulating member includes at least one organic layer and at least one inorganic layer which are alternately disposed therein, wherein
an inorganic layer from among the at least one inorganic layer disposed most adjacent to the display member has a multilayer structure in which first layers having a first refractive index and second layers having a second refractive index different from the first refractive index are alternately disposed, and
each of the remaining inorganic layers among the at least one inorganic layer except for the inorganic layer disposed most adjacent to the display member and the at least one organic layer has a single layer structure, wherein the inorganic layer disposed most adjacent to the display member comprises:
a first sub inorganic layer disposed on the display member; and
a second sub inorganic layer disposed on the first sub inorganic layer,
wherein each of the first sub inorganic layer, and the second sub inorganic layer includes one of the first layers and one of the second layers.

US Pat. No. 10,483,483

ELECTROLUMINESCENT DEVICE AND ELECTROLUMINESCENT DISPLAY DEVICE INCLUDING THE SAME

LG Display Co., Ltd., Se...

1. An electroluminescent device comprising:an anode and a cathode facing each other;
a light compensation layer located between the anode and the cathode, the light compensation layer having a first refractive index;
an emitting material layer located between the light compensation layer and the cathode, the emitting material layer having a second refractive index higher than the first refractive index; and
a hole injection layer located between the emitting material layer and the light compensation layer or between the light compensation layer and the anode, wherein the hole injection layer has a third refractive index higher than the first refractive index, and
wherein the light compensation layer has a thickness smaller than a thickness of the emitting material layer and a thickness of the hole injection layer.

US Pat. No. 10,483,480

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a pixel electrode, a counter electrode, and an organic layer arranged between the pixel electrode and the counter electrode,
wherein
the organic layer includes a hole injection layer in contact with the pixel electrode, a hole transport layer above the hole injection layer, a light emitting layer and an electron transport layer;
the hole injection layer includes an inorganic material;
the inorganic material has a work function of 4.4 eV or less,
a surface roughness of the pixel electrode is 20 nm or more, and a gap length between a projection and a depression of the surface of the pixel electrode is 40 nm or more, and
a thickness of the hole injection layer is smaller than the surface roughness of the pixel electrode.

US Pat. No. 10,483,479

METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DEVICE AND ORGANIC LIGHT EMITTING DEVICE

PIONEER CORPORATION, Tok...

1. A method of manufacturing a light emitting device, the method comprising:a first step of coating a first region of a substrate, in which a first light emitting unit is formed, with a first solution comprising a light emitting material;
a second step of coating a second region of a substrate, in which a second light emitting unit is formed, with a second solution comprising a coating material, before or after the first step;
a third step of drying the first solution in the first region and the second solution in the second region after the first step and the second step; and
a fourth step of depositing a light emitting material in the second region after the third step.

US Pat. No. 10,483,477

EXCITED STATE MANAGEMENT

THE REGENTS OF THE UNIVER...

1. An emissive layer of an opto-electronic device, the emissive layer comprising:a host material;
a first dopant; and
a second dopant that has a solid state sink energy level,
wherein the first dopant is a blue-emitting, phosphorescent dopant that has a triplet energy level T1 that is lower than the solid state sink energy level of the second dopant, wherein the solid state sink energy level is at least 0.2 eV below the multiply-excited energy level of the first dopant, and
wherein the emissive layer is disposed between an electron-transport layer (ETL) and a hole-transport layer (HTL), and the concentration of the first dopant is graded within the host material from about 20% at the HTL/emitting layer interface to about 8% at the ETL/emitting layer interface.

US Pat. No. 10,483,473

ELECTRONIC DEVICE AND SOLID STATE IMAGING APPARATUS

SONY CORPORATION, Tokyo ...

1. An electronic device, comprising:a first electrode;
a second electrode; and
a photoelectric conversion layer between the first electrode and the second electrode, wherein
the first electrode is formed from a transparent conductive material having a work function ranging from 5.2 to 5.9 eV, and
the transparent conductive material is composed of indium oxide and at least one metal species selected from a group consisting of cerium, gallium, tungsten, and titanium, with the metal species accounting for 0.5 to 10 atom % of a total amount, 100 atom % of indium and the metal species.

US Pat. No. 10,483,472

SCHOTTKY DIODE

Tsinghua University, Bei...

1. A Schottky diode comprising:an insulating substrate and at least one Schottky diode unit, the at least one Schottky diode unit being located on a surface of the insulating substrate, wherein each of the at least one Schottky diode unit comprises:
a first electrode located on the surface of the insulating substrate;
a semiconductor structure comprising a first end and a second end opposite with the first end, the first end is laid on the first electrode, and the first electrode is located between the first end of the semiconductor structure and the surface of the insulating substrate, the second end of the semiconducting structure is located on the surface of the insulating substrate, the semiconducting structure comprises a carbon nanotube structure; and
a second electrode located on the second end of the semiconducting structure, and the second end of the semiconducting structure is located between the second electrode and the surface of the insulating substrate, and the second end of the semiconducting structure is in direct contact with the second electrode.

US Pat. No. 10,483,471

ORGANIC ELECTROLUMINESCENT ELEMENT, METHOD FOR PRODUCING ORGANIC ELECTROLUMINESCENT ELEMENT, DISPLAY, AND LIGHTING DEVICE

Konica Minolta, Inc., To...

1. An organic electroluminescent element including an organic layer provided between at least a pair of a cathode and an anode, whereinthe organic layer is formed of at least one layer including a luminescent layer, and
at least one layer forming the organic layer contains at least one selected from compounds represented by general formulae (A2) and (A5):

wherein in the general formula (A2), X represents an oxygen atom or a sulfur atom;

wherein in the general formula (A5), X1 represents an oxygen atom or a sulfur atom; Z2, Z3, Z5 to Z8 independently represent ?N— or ?C(R1)— respectively; R1 represents a hydrogen atom or a substituent; Z4 is ?N—, Z1 represents ?N— or ?C(R2)—, and R2 represents a nitrogen-containing 6 membered heterocycle of general formula (A5-5) or (A5-6) or a nitrogen-containing 5 membered ring of general formula (A5-2);

in the formula (A5-2), W1 represents —N— or ?C—; W2 to W5 independently represent ?N— or ?C(R4)— respectively; R4 represents a hydrogen atom or a substituent; at least one of W1 to W5 represents ?N—; * represents a linkage position to the general formula (A5), and if two of ?C(R4)— are adjacently placed in series, two of R4 may be condensed together to form a ring;

in the general formula (A5-5), Y1, Y2, and Y5 to Y9 independently represent ?N— or ?C(R3)— respectively; R3 represents a hydrogen atom or a substituent; at least one of Y1, Y2 and Y5 represents ?N—; * represents a linkage position to the general formula (A5), X2 represents one member selected from an oxygen atom, a sulfur atom, —NR2—, and —CR3R4—, wherein R2 and R4 are identical to said R2 and R4, respectively;

in the general formula (A5-6), Y1, Y2 and Y5 to Y9 independently represent ?N— or ?C(R3)— respectively; R3 represents a hydrogen atom or a substituent; at least one of Y1, Y2 and Y5 represents ?N—; * represents a linkage position to the general formula (A5), X2 represents one member selected from an oxygen atom, a sulfur atom, —NR2— or —CR3R4—, wherein R2 and R4 are identical to said R2 and R4, respectively.

US Pat. No. 10,483,463

MEMORY CELLS, MEMORY ARRAYS, AND METHODS OF FORMING MEMORY CELLS AND ARRAYS

Micron Technology, Inc., ...

1. A method of forming a memory array, comprising:forming heater structures over an array of electrical nodes; the heater structures being in one-to-one correspondence with the electrical nodes; the array of electrical nodes having rows extending along a first direction and having columns extending along a second direction substantially orthogonal to the first direction;
forming confined phase change material structures over the heater structures and in one-to-one correspondence with the heater structures, having lateral peripheries of a phase change material, the array having x-direction axes extending through the confined phase change material structures along the first direction and y-direction axes extending through the confined phase change material structures along the second direction;
forming bitlines across the confined phase change material structures, with the bitlines extending along the second direction;
forming conductive material caps between and contacting the bitlines and the confined phase change material structures, the confined phase change material structures and conductive material caps being spaced from one another along the x-direction axes by first insulative material regions comprising a first oxide-containing material having a first pair of opposing vertical sidewalls sandwiched between first nitride-containing materials that extend vertically along an entirety of the first pair of opposing vertical sidewalls, the confined phase change material structures and conductive material caps further being spaced from one another along the y-direction axes by second insulative material regions comprising a second oxide-containing material having a second pair of opposing vertically extending sidewalls sandwiched between second nitride-containing materials that extend vertically along an entirety of the second pair of opposing vertically extending sidewalls; and
the lateral peripheries of the confined phase change material structures, the conductive material caps and the heater structures being entirely laterally surrounded by the first and second nitride-containing materials.

US Pat. No. 10,483,460

METHOD OF MANUFACTURING A MAGNETORESISTIVE STACK/ STRUCTURE USING PLURALITY OF ENCAPSULATION LAYERS

Everspin Technologies, In...

1. A method of manufacturing a magnetoresistive stack/structure from: (i) a first magnetic region including one or more layers of magnetic material, (ii) a dielectric layer disposed over the first magnetic region, (iii) a second magnetic region including one or more layers of magnetic material, wherein the second magnetic region is disposed over the dielectric layer, the method comprising:(a) etching through the second magnetic region to (i) partially form the magnetoresistive stack/structure and provide sidewalls of the second magnetic region and (ii) expose a surface of the dielectric layer in a field region adjacent to the partially formed magnetoresistive stack/structure;
(b) depositing a first encapsulation layer on or over the sidewalls of the second magnetic region and on the exposed surface of the dielectric layer, wherein the first encapsulation layer is a first material;
(c) depositing a second encapsulation layer on the first encapsulation layer disposed (i) on or over the sidewalls of the second magnetic region and (ii) on the exposed surface of the dielectric layer, wherein the second encapsulation layer is a second material;
(d) after step (c), etching the exposed surface of the dielectric layer together with the first encapsulation layer and the second encapsulation layer disposed on or over the exposed surface of the dielectric layer to form a tunnel barrier, wherein, after the etching in step (d), a portion of the first encapsulation layer and a portion of the second encapsulation layer remain on or over the sidewalls of the second magnetic region; and
(e) after etching through the exposed surface of dielectric layer in step (d), etching the first magnetic region to provide sidewalls thereof.

US Pat. No. 10,483,454

PIEZOELECTRIC COMPONENT AND METHOD FOR PRODUCING A PIEZOELECTRIC COMPONENT

1. A method for producing a piezoelectric component, the method comprising:producing a ceramic precursor material of the general formula Pb1-x-y-(2a-b)/2V(2a-b)/2?BaxSry[(TizZr1-z)1-a-bWaREb]O3, where RE is a rare earth metal and V? is a Pb vacancy;
mixing the ceramic precursor material with a sintering aid;
forming a stack which includes alternating layers comprising the ceramic precursor material and a layer comprising Cu; and
debindering and sintering the stack thereby forming the piezoelectric component having Cu electrodes and at least one piezoelectric ceramic layer comprising Pb1-x-y-[(2a-b)/2]-p/2V[(2a-b)/2-p/2]?CupBaxSry[(TizZr1-z)1-a-bWaREb]O3, where 0?x?0.035, 0?y?0.025, 0.42?z?0.5, 0.0045?a?0.009, 0.009?b?0.011, and 2a>b, p?2a-b.

US Pat. No. 10,483,448

FLEXIBLE THERMOELECTRIC DEVICES, METHODS OF PREPARATION THEREOF, AND METHODS OF RECOVERING WASTE HEAT THEREWITH

North Carolina State Univ...

1. A flexible thermoelectric device comprising:a flexible substrate having a surface;
a first conductive ink having a Seebeck coefficient; and
a second conductive ink having a Seebeck coefficient that is different from the Seebeck coefficient of the first conductive ink;
wherein each of the first conductive ink and the second conductive ink independently comprises a carrier and conductive particles;
wherein each of the first conductive ink and the second conductive ink independently has a resistance that is no more than two orders of magnitude greater than the resistance of the conductive particles alone;
wherein the first conductive ink and the second conductive ink are arranged on the surface of the flexible substrate so as to form a series of thermopile junctions; and
wherein the flexible substrate is shaped such that alternating thermopile junctions are positioned so as to be spaced apart from intervening thermopile junctions.

US Pat. No. 10,483,444

METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT, OPTOELECTRONIC SEMICONDUCTOR COMPONENT, AND TEMPORARY CARRIER

OSRAM Opto Semiconductors...

1. A method of producing an optoelectronic semiconductor component comprising:providing a carrier comprising two metal layers, wherein the metal layers are detachable from one another,
applying a photoresist on the first metal layer,
patterning the photoresist such that regions composed of the photoresist comprising a predefined cross section are present on the first metal layer,
electrolytically applying a further metal on free regions of the first metal layer not covered by the photoresist, wherein the further metal comprises a greater thickness than the photoresist and partly projects laterally beyond regions of the photoresist,
removing the photoresist, wherein a body composed of the further metal arises, said body comprising a laterally projecting upper edge region,
securing an optoelectronic semiconductor chip on the further metal, and
mechanically detaching the second metal layer from the first metal layer.

US Pat. No. 10,483,441

PHOSPHOR CONTAINING PARTICLE, AND LIGHT EMITTING DEVICE AND PHOSPHOR CONTAINING SHEET USING THE SAME

SHARP KABUSHIKI KAISHA, ...

1. A phosphor containing particle comprising:a core portion which is a particulate matter of resin including a constitutional unit derived from an ionic liquid with a semiconductor nanoparticle phosphor dispersed therein; and
a shell portion which is a matter in a form of a layer of resin which includes a constitutional unit derived from an ionic liquid and coats at least a portion of the core portion, wherein
the ionic liquids included in the core portion and the shell portion are selected from a group consisting of 2-(methacryloyloxy)-ethyltrimethyl ammonium bis(trifluoromethane sulfonyl) imide, 1-(3-acryloyloxy-propyl)-3-methylimidazolium bis(trifluoromethanesulfonyl)imide, N,N,N-trimethyl-N-propylammonium bis(trifluoromethanesulfonyl) imide, and N,N-dimethyl-N-methyl-2-(2-methoxy ethyl) ammonium bis(trifluoromethanesulfonyl) imide.

US Pat. No. 10,483,440

CADMIUM-FREE QUANTUM DOT NANOPARTICLES

Nanoco Technologies Ltd.,...

1. A quantum dot nanoparticle comprising:a core having an etched surface and comprising indium, phosphorus, magnesium, zinc, and sulfur;
a first shell disposed on the etched surface of the core; and
a second shell disposed on the first shell,
wherein the quantum dot nanoparticle emits light in the green region of the visible spectrum.

US Pat. No. 10,483,438

COMPONENT, SUBSTRATE MODULE, APPARATUS, AND OPTICAL FILTER

SONY CORPORATION, Tokyo ...

1. A component, comprising:a main body including a bottom surface;
a first layer on the bottom surface of the main body, wherein
the first layer includes a bottom surface and an exposed bottom surface area, and
the exposed bottom surface area has a first width; and
a second layer bonded to a metal bonding material, wherein
the metal bonding material is between the second layer and a substrate,
wettability with respect to the metal bonding material in a molten state is higher for the second layer than the first layer,
the second layer protrudes from the bottom surface of the first layer,
at least a part of the bottom surface of the first layer is in contact with an entire outer peripheral side of the second layer, and
in a cross-sectional view of the component along a lamination direction of the first layer and the second layer:
the first width of the exposed bottom surface area of the first layer is larger than a protrusion height of the second layer from the first layer in a protrusion direction.

US Pat. No. 10,483,437

DISPLAY DEVICE

INNOLUX CORPORATION, Chu...

1. A display device, comprising:a display panel comprising:
a first substrate having a first surface; and
a second substrate disposed on the first surface;
a third substrate such that the second substrate is disposed between the first substrate and the third substrate, wherein the third substrate has a second surface facing the first surface;
an adhesion element disposed on the first surface and adjacent to the second substrate, wherein the adhesion element has a first through hole; and
a filler disposed in the first through hole and in contact with the first surface and the second surface;
wherein the first through hole of the adhesion element has an area defined as a first area, the filler has a region in contact with the second surface, an area of the region is defined as a second area, and a ratio of the first area to the second area ranges from 0.5 to 0.99.

US Pat. No. 10,483,436

DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF

Innolux Corporation, Mia...

1. A manufacturing method of a display apparatus, comprising:forming a light-emitting diode body on a substrate, wherein a method of forming the light-emitting diode body comprises:
forming a first conductivity type semiconductor material layer, an active material layer, and a second conductivity type semiconductor material layer on the substrate in order;
forming a first patterned photoresist layer on the second conductivity type semiconductor material layer, wherein the first patterned photoresist layer is formed by a half tone process;
performing a reflow process on the first patterned photoresist layer; and
removing a portion of the first conductivity type semiconductor material layer, a portion of the active material layer, and a portion of the second conductivity type semiconductor material layer using the reflowed first patterned photoresist layer as a mask to form a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; and
forming a reflective structure on a sidewall of the light-emitting diode body, wherein a method of forming the reflective structure comprises:
forming a first material layer and a second material layer on the light-emitting diode body in order;
performing a first etching process on the second material layer using a second patterned photoresist layer as a mask; and
performing a second etching process on the first material layer using the second patterned photoresist layer as a mask.

US Pat. No. 10,483,434

DISPLAY DEVICES AND METHODS FOR FORMING DISPLAY DEVICES

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a thin-film transistor substrate;
a conductive pad disposed on the thin-film transistor substrate;
an adhesion film disposed on the conductive pad, the adhesion film comprising a plurality of conductive particles;
a light-emitting component disposed on the adhesion film, the light-emitting component comprising a first connection feature and a second connection feature; and
a protection layer partially surrounding the light-emitting component, wherein each of the first connection feature and the second connection feature has a lower portion not surrounded by the protection layer and the protection layer between the first connection feature and the second connection feature comprises an organic sub-layer and an inorganic sub-layer, and
wherein the adhesion film has a thickness of T, one of the plurality of conductive particles has a diameter of d, the lower portion of the connection feature has a thickness of t, and 0

US Pat. No. 10,483,427

METHOD OF MANUFACTURING SOLAR CELL

LG Electronics Inc., Seo...

1. A method of manufacturing a solar cell, the method comprising:an overlapping operation of overlapping a first surface of a first semiconductor substrate made of a silicon wafer to a first surface of a second semiconductor substrate made of a silicon wafer to form an overlapped semiconductor substrate, wherein the first surface of the first semiconductor substrate and the first surface of the second semiconductor substrate contact each other;
a semiconductor layer depositing operation of depositing a first semiconductor layer on a second surface of the first semiconductor substrate and a second semiconductor layer on a second surface of the second semiconductor substrate, wherein the second surface of the first semiconductor substrate is positioned at an opposite side of the first surface of the first semiconductor substrate and the second surface of the second semiconductor substrate is positioned at an opposite side of the first surface of the second semiconductor substrate;
a separating operation of separating the overlapped semiconductor substrate into the first semiconductor substrate and the second semiconductor substrate; and
a texturing operation of texturing the first surface of the first semiconductor substrate.

US Pat. No. 10,483,424

SIGNAL COUPLING DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A signal coupling device, comprising:a light-emitting element disposed on a first frame portion and configured to emit light;
a first semiconductor element disposed on a second frame portion and having an operational amplifier with a CMOS circuit, the first semiconductor element being configured to drive the light-emitting element to output an optical signal, the first semiconductor element including a first reference voltage generating circuit configured to generate a first reference voltage, the first semiconductor element including an analog-to-digital converter configured to convert a voltage signal into a digital signal based on the first reference voltage and a modulator configured to generate a modulation signal synchronized with the optical signal based on the digital signal;
a second semiconductor element disposed on a third frame portion and configured to receive the optical signal from the light-emitting element and to convert the optical signal into an electrical signal, the second semiconductor element including a second reference voltage generating circuit configured to generate a second reference voltage, the second semiconductor element including a photoelectric converter, the photoelectric converter configured to convert the optical signal to the electrical signal, a demodulator configured to demodulate the electrical signal, and a digital-to-analog converter configured to convert the electrical signal into an analog voltage signal based on the second reference voltage;
a first silicone gel disposed on the second frame portion and covering the first semiconductor element;
a second silicone gel disposed on the third frame portion and covering the second semiconductor element;
a third silicone gel disposed on the first frame portion and covering the light-emitting element; and
a first resin material encapsulating the light-emitting element, the first semiconductor element, and the second semiconductor element and contacting the first, second, and third silicone gels, wherein
the first silicone gel suppresses variations in the first reference voltage.

US Pat. No. 10,483,423

QUANTUM DOT PHOTODETECTOR APPARATUS AND ASSOCIATED METHODS

EMBERION OY, Espoo (FI)

1. An apparatus comprising a layer of channel material, source and drain electrodes configured to enable a flow of electrical current through the layer of channel material, and a layer of quantum dot material configured to generate electron-hole pairs on exposure to incident electromagnetic radiation to produce a detectable change in the electrical current which is indicative of one or more of the presence and magnitude of the electromagnetic radiation,wherein the layer of quantum dot material is positioned between the layer of channel material and a layer of conductive material, and
wherein the layers of channel and conductive material have work functions such that respective built-in electric fields are created at the interfaces between the layer of quantum dot material and the layers of channel and conductive material, the built-in electric field at each interface acting in the same direction to promote separation of the electrons and holes of the generated electron-hole pairs to facilitate production of the detectable change in electrical current.

US Pat. No. 10,483,416

MEDIUM WAVE INFRARED (MWIR) AND LONG WAVELENGTH INFRARED (LWIR) OPERATING MICROBOLOMETER WITH RAISED STRUT DESIGN

1. A semiconducting microbolometer in which resistance is changed due to absorbance of radiation, comprising of:a substrate,
an insulating layer on the substrate,
a lower cavity on the insulating layer,
a lower support layer on the insulating layer,
an upper support layer on the lower support layer and the lower cavity,
a sensing layer on the upper support layer,
an upper cavity on the upper support layer,
an absorption layer on the upper support layer,
wherein the sensing material is tungsten doped germanium silicon oxide.

US Pat. No. 10,483,415

METHODS TO INTRODUCE SUB-MICROMETER, SYMMETRY-BREAKING SURFACE CORRUGATION TO SILICON SUBSTRATES TO INCREASE LIGHT TRAPPING

STC.UNM, Albuquerque, NM...

1. An optoelectronic device, comprising:a patterned substrate comprising a surface having a plurality of symmetry-breaking surface corrugations, wherein the symmetry-breaking surface corrugations comprise a symmetry selected from at least one of C4, C2v, C2 and C1 wherein the symmetry breaking corrugations comprise a periodicity from 500 nm to 1000 nm in at least two directions; and
at least one layer formed on the patterned substrate.

US Pat. No. 10,483,414

STACK-TYPE IMAGE SENSOR INCLUDING META-FILTER

SAMSUNG ELECTRONICS CO., ...

1. A stack-type image sensor comprising:a photodiode comprising:
a first photodiode configured to absorb first light of a first wavelength band, and
a second photodiode disposed on the first photodiode and configured to absorb second light of a second wavelength band; and
a meta-filter comprising a plurality of nanostructures that satisfy a subwavelength condition, the meta-filter being configured to reflect light of a previously determined wavelength band, and to transmit light of wavelength bands other than the previously determined wavelength band,
wherein the meta-filter further comprises a first meta-filter disposed in a lower portion of the first photodiode, the first meta-filter being configured to reflect the first light of the first wavelength band to the first photodiode.

US Pat. No. 10,483,411

SOLAR CELL AND SOLAR CELL MODULE

Panasonic Corporation, O...

1. A solar cell comprising:a first electrode;
a first hole transport layer containing nickel and lithium;
an inorganic material layer containing titanium;
a light-absorbing layer converting light into electric charge;
a second hole transport layer, located between the first hole transport layer and the inorganic material layer, containing nickel and lithium; and
a second electrode, wherein
the first electrode, the first hole transport layer, the inorganic material layer, the light-absorbing layer, and the second electrode are layered in that order,
the light-absorbing layer contains a perovskite compound represented by a formula AMX3, where A is a monovalent cation, M is a divalent cation, and X is a monovalent anion, and
an atomic ratio of lithium to all metal elements in the second hole transport layer is less than an atomic ratio of lithium to all metal elements in the first hole transport layer.

US Pat. No. 10,483,410

FORMING FRONT METAL CONTACT ON SOLAR CELL WITH ENHANCED RESISTANCE TO STRESS

ALTA DEVICES, INC., Sunn...

1. A photovoltaic assembly comprising:a photovoltaic cell configured to convert light energy to electrical energy, wherein said photovoltaic cell comprises:
a front metal layer comprising a bus bar on a side along a length of said photovoltaic cell and multiple finger electrodes oriented perpendicular to and extending from said bus bar with one end connected to said bus bar,
a photovoltaic layer disposed under said front metal layer, said front metal layer being disposed closer than said photovoltaic layer to a side of said photovoltaic cell intended to face light, and
a substrate layer disposed under said photovoltaic layer;
a front contact disposed above of said front metal layer and thereby above said bus bar and above the end of each of said finger electrodes connected to said bus bar, and said front contact configured to conduct electrical current originated from the photovoltaic cell to external circuitry;
a cushion layer disposed between said front contact and said front metal layer thereby closer to said side of said photovoltaic cell intended to face light than said front metal layer, wherein said cushion layer includes a nonconductive material that is less rigid than said front contact and comprises a plurality of vias filled with a conductive material, wherein each filled via is aligned with and in direct contact with one finger electrode at the end of that finger electrode that is connected with said bus bar to conduct electrical current between said front contact and said photovoltaic layer via said front metal layer, and wherein an excess portion of said front contact and said cushion layer along said length of said photovoltaic cell wraps over an edge of said photovoltaic cell; and
a back metal layer disposed between said photovoltaic layer and said substrate layer, said back metal layer being configured to interconnect said photovoltaic layer with another photovoltaic layer of a different photovoltaic cell in said photovoltaic assembly,
wherein said nonconductive material of said cushion layer includes a flexible polymer material and said substrate layer includes the flexible polymer material.

US Pat. No. 10,483,407

METHODS OF FORMING SI3NX, METHODS OF FORMING INSULATOR MATERIAL BETWEEN A CONTROL GATE AND CHARGE-STORAGE MATERIAL OF A PROGRAMMABLE CHARGE-STORAGE TRANSISTOR, AND METHODS OF FORMING AN ARRAY OF ELEVATIONALLY-EXTENDING STRINGS OF MEMORY CELLS AND A PROGRA

Micron Technology, Inc., ...

1. A method of forming Si3Nx, where “x” is less than 4 and at least 3, comprising:decomposing a Si-comprising precursor molecule into at least two decomposition species that are different from one another within a chamber having a chamber pressure of from 100 to 500 mTorr, at least one of the at least two different decomposition species comprising Si;
after the decomposing the Si-precursor molecule, contacting an outer substrate surface with the at least two decomposition species, at least one of the decomposition species that comprises Si attaching to the outer substrate surface to comprise an attached species; and
after the contacting the outer substrate surface, contacting the attached species with a N-comprising precursor that reacts with the attached species to form a reaction product comprising Si3Nx, where “x” is less than 4 and at least 3.

US Pat. No. 10,483,405

METAL OXIDE THIN-FILM TRANSISTOR AND MANUFACTURING METHOD FOR THE SAME

Shenzhen China Star Optoe...

1. A metal oxide thin-film transistor, comprising:a substrate;
a source electrode, a barrier layer and a drain electrode which are sequentially formed on the substrate; and
a semiconductor active layer formed on side surfaces of the source electrode and the drain electrode;
wherein the semiconductor active layer is respectively connected with the source electrode and the drain electrode;
wherein, in a cross-sectional structure of the metal oxide thin-film transistor, each of the source electrode, the barrier layer and the drain electrode is a trapezoidal structure that a length of an upper surface is less than a length of a lower surface; a length of a lower surface of the drain electrode is the same as a length of an upper surface of the barrier layer, a length of a lower surface of the barrier layer is less than a length of an upper surface of the source electrode such that a portion of the source electrode is exposed outside a covering range of the barrier layer; and
wherein the semiconductor active layer is a patterned semiconductor active layer, the patterned semiconductor active layer includes a first patterned semiconductor active layer located at and simultaneously contacted with a left side of the drain electrode and a left side of the source electrode, and a second patterned semiconductor active layer located at and simultaneously contacted with a right side of the drain electrode and a right side of the source electrode.

US Pat. No. 10,483,399

INTEGRATED CIRCUIT DEVICE

SAMSUNG ELECTRONICS CO., ...

1. An integrated circuit (IC) device, comprising:a pair of first fin-shaped active areas that are adjacent to each other with a first fin separation area having a first width therebetween in a first area on a substrate, the pair of first fin-shaped active areas extending in a first line;
a first fin separation insulating structure that extends in the first fin separation area in a direction that intersects the first line and has a first top surface having a convex rounded top surface profile, the first top surface having a second width that is greater than the first width;
a first normal gate that extends on a region of one selected from the pair of first fin-shaped active areas; and
a first semiconductor epitaxial pattern on a region of the one selected from the pair of first fin-shaped active areas between the first normal gate and the first fin separation insulating structure, the first semiconductor epitaxial pattern being spaced apart from the first fin separation insulating structure,
wherein top surfaces of the one selected from the pair of first fin-shaped active areas at opposite sides of the first semiconductor epitaxial pattern have different heights.

US Pat. No. 10,483,393

METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES

STMicroelectronics, Inc.,...

1. A device, comprising:a substrate having a first portion and a second portion extending away from the first portion, the second portion having a first length in a first direction and a first width in a second direction orthogonal to the first direction;
a microfabricated structure on the substrate, the microfabricated structure having a fin including:
the second portion of the substrate;
a strain-inducing layer on the second portion of the substrate, the strain-inducing layer having a second length in the first direction and a second width in the second direction, the first length approximately equal to the second length and the first width approximately equal to the second width; and
a semiconductor layer on the strain-inducing layer.

US Pat. No. 10,483,392

CAPACITIVE TUNING USING BACKSIDE GATE

QUALCOMM Incorporated, S...

1. A balanced radio frequency (RF) integrated circuit (RFIC) including a stack of switch multi-finger transistors, comprising:a first dual gate transistor having a first gate with a first gate length on a first side of a substrate, and a second gate with a second gate length on a second side of the substrate;
a second dual gate transistor having a third gate with a third gate length on the first side of the substrate, and a fourth gate with a fourth gate length on the second side of the substrate, in which the second gate length is different than the fourth gate length, and the second dual gate transistor is coupled in series with the first dual gate transistor in the RFIC; and
a dielectric layer on the second side of the substrate and in contact with the second gate and the fourth gate.

US Pat. No. 10,483,385

NANOWIRE STRUCTURES HAVING WRAP-AROUND CONTACTS

Intel Corporation, Santa...

10. A semiconductor device, comprising:a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising:
a discrete channel region disposed in the nanowire, the channel region having a length and a perimeter orthogonal to the length, wherein the perimeter of the channel region is a smallest perimeter of the nanowire;
a pair of discrete source and drain regions disposed in the nanowire, on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to the length of the channel region, wherein the perimeters of the source and drain regions are approximately the same, and are greater than the perimeter of the channel region at locations immediately adjacent the channel region, and wherein the smallest perimeter of the nanowire is at the locations where the source and drain regions are immediately adjacent the channel region;
a gate electrode stack surrounding and in contact with the entire perimeter of each of the channel regions;
a pair of conductive contacts, a first of the pair of conductive contacts completely surrounding the perimeter of each of the source regions, and a second of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of each of the drain regions, wherein the pair of conductive contacts has an uppermost surface co-planar with an uppermost surface of the gate electrode stack;
a pair of spacers disposed between the gate electrode stack and the pair of conductive contacts; and
an intervening semiconductor material between and in contact with the plurality of vertically stacked nanowires but not along sidewalls of the nanowires at a location beneath the pair of spacers.

US Pat. No. 10,483,384

TRANSISTOR DEVICE WITH HIGH CURRENT ROBUSTNESS

Infineon Technologies AG,...

1. A transistor device, comprising:a first emitter region of a first doping type, a second emitter region of a second doping type, a body region of the second doping type, a drift region of the first doping type, a field-stop region of the first doping type, and at least one boost structure; and
a gate electrode dielectrically insulated from the body region by a gate dielectric,
wherein the body region is arranged between the first emitter region and the drift region, the field-stop region is arranged between the drift region and the boost structure, and the boost structure is arranged between the field-stop region and the second emitter region,
wherein the at least one boost structure comprises a base region of the first doping type and at least one auxiliary emitter region of the second doping type separated from the second emitter region by the base region,
wherein an overall dopant dose in the drift region and the field-stop region in a current flow direction of the transistor device is higher than a breakthrough charge of a semiconductor material of the drift region and the field-stop region.

US Pat. No. 10,483,383

SEMICONDUCTOR DEVICE INCLUDING A GATE CONTACT STRUCTURE

1. A semiconductor device, comprising:a semiconductor body having a first surface and a second surface opposite to the first surface;
a transistor cell structure in the semiconductor body;
a gate contact structure comprising a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line to form an electrical pathway between the gate pad and the gate electrode layer; and
a gate resistor structure separate from the gate contact structure, integrated in the electrical pathway between the gate pad and the gate electrode layer, and formed on a different isolation layer than the gate contact structure,
wherein an electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.

US Pat. No. 10,483,381

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A semiconductor device, comprising:a tunnel field-effect transistor comprising:
a first substrate; and
a first electrical element, wherein the first electrical element is formed on one side of the first substrate, wherein the first electrical element comprises:
a first drain region;
a second drain region, wherein the first drain region and the second drain region are opposite to each other and separated by a part of the first substrate;
a first shallow trench isolation region;
a second shallow trench isolation region, wherein the first drain region and the second drain region are disposed between the first shallow trench isolation region and the second shallow trench isolation region;
a planar device comprising:
a second substrate; and
a second electrical element, wherein the second substrate and the first substrate are an integrated structure and form a main substrate, wherein the second electrical element is formed on one side of the second substrate, wherein the second electrical element and the first electrical element are disposed on a same side of the main substrate, and wherein the planar device comprises at least one of a metal oxide semiconductor transistor, a capacitor, or a resistor.

US Pat. No. 10,483,377

DEVICES AND METHODS OF FORMING UNMERGED EPITAXY FOR FINFET DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a device having at least one source, at least one drain, and at least one fin on a semiconductor layer;
a first dielectric layer over the device and positioned around at least a portion of the at least one fin;
a first layer of epitaxial growth on the at least one fin, the first layer of epitaxial growth including a first top surface, a first side surface extending away from the first top surface in a first direction at an angle toward the semiconductor layer, and a second side surface extending away from the first top surface in a second direction at an angle toward the semiconductor layer;
second dielectric layer over the first dielectric layer, the second dielectric layer positioned around at least a portion of the first layer of epitaxial growth and at least a portion of the at least one fin;
a second layer of epitaxial growth superimposing the first layer of epitaxial growth;
a first contact region over the at least one source; and
a second contact region over the at least one drain,
wherein the second interlayer dielectric layer contacts the first side surface of the first layer of epitaxial growth and the second side surface of the first layer of epitaxial growth.

US Pat. No. 10,483,372

SPACER STRUCTURE WITH HIGH PLASMA RESISTANCE FOR SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:an active area on a substrate, the active area comprising a source/drain region;
a gate structure over the active area, the source/drain region being proximate the gate structure, wherein the gate structure comprises a metal gate electrode disposed on a high dielectric constant layer;
a spacer feature having a first portion along a sidewall of the gate structure and having a second portion along the source/drain region, wherein the first portion of the spacer feature comprises a bulk spacer layer along the sidewall of the gate structure, wherein the second portion of the spacer feature comprises the bulk spacer layer and a treated seal spacer layer, the treated seal spacer layer being disposed along the source/drain region and between the bulk spacer layer and the source/drain region; and
a contact etching stop layer on the spacer feature.

US Pat. No. 10,483,368

SINGLE CRYSTALLINE EXTRINSIC BASES FOR BIPOLAR JUNCTION STRUCTURES

International Business Ma...

1. A method for forming a bipolar transistor (BJT) structure comprising:providing a substrate with an insulator layer and a device layer over the insulator layer;
forming an intrinsic base from the device layer;
forming emitter and collector regions from the device layer;
after forming i) the intrinsic base and ii) the emitter and collector regions, depositing a single crystalline extrinsic base over the intrinsic base;
prior to depositing the extrinsic base, forming an inter-layer dielectric (ILD) material over the structure;
forming a dummy base, with a hardmask thereon, over the device layer; and
performing chemical-mechanical planarization (CMP) on the structure to planarize the ILD in relation to the hardmask.

US Pat. No. 10,483,364

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A method for manufacturing a semiconductor structure, the method comprising:forming a dielectric layer on at least one gate structure and at least one source drain structure;
forming an opening in the dielectric layer to expose the source drain structure;
forming a protection layer on at least one sidewall of the opening;
forming a conductive plug in the opening, wherein the conductive plug is electrically connected to the source drain structure;
etching back the dielectric layer to expose a sidewall of the protection layer after the forming the conductive plug; and
removing the protection layer after the forming the conductive plug.

US Pat. No. 10,483,361

WRAP-AROUND-CONTACT STRUCTURE FOR TOP SOURCE/DRAIN IN VERTICAL FETS

International Business Ma...

1. A method for forming a wrap-around-contact, the method comprising:forming a bottom source/drain region adjacent a plurality of fins;
disposing encapsulation layers over the plurality of fins;
recessing at least one of the encapsulation layers to expose top portions of the plurality of fins;
forming top spacers adjacent the top portions of the plurality of fins;
disposing a sacrificial liner adjacent the encapsulation layers;
recessing the top spacers;
forming top source/drain regions over the top portions of the plurality of fins;
removing the sacrificial liner to create trenches adjacent the top source/drain regions; and
depositing a metal liner within the trenches and over the top source/drain regions such that the wrap-around-contact is defined to cover an upper area of the top source/drain regions.

US Pat. No. 10,483,359

METHOD OF FABRICATING A POWER SEMICONDUCTOR DEVICE

Infineon Technologies Ame...

1. A method of fabricating a power semiconductor device, said method comprising:forming a gate trench in a semiconductor substrate, said gate trench including a gate electrode; and
forming a field plate trench structure in said substrate separate from said gate trench, wherein forming said field plate trench structure comprises:
forming an upper trench situated over a lower trench in said substrate, said upper trench being wider than said lower trench and extending deeper into said substrate than said gate trench, a width of said lower trench being greater than one half a width of said upper trench;
forming a trench dielectric in said lower trench and on sidewalls of said upper trench, said trench dielectric filling completely said lower trench; and
forming a field plate electrode within said trench dielectric;
wherein said trench dielectric is formed such that a bottom thickness of said trench dielectric is greater than a sidewall thickness of said trench dielectric on said sidewalls of said upper trench.

US Pat. No. 10,483,354

NITRIDE SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A nitride semiconductor device comprising:(i) a first semiconductor layer, which satisfies Alx1Ga(1-x1)N,
wherein x1 is greater than 0 and less than or equal to 1;
(ii) a second semiconductor layer, which satisfies Iny2Alx2Ga(1-x2-y2)N,
wherein x2 is greater than 0 and less than 1,
wherein y2 is greater than 0 and less than 1, and
wherein x2+y2 is greater than 0 and less than or equal to 1;
(iii) a third semiconductor layer, which satisfies Alx3Ga(1-x3)N,
wherein x3 is greater than or equal to 0 and less than 1; and
(iv) a fourth semiconductor layer, which satisfies Iny4Alx4Ga(1-x4-y4)N,
wherein x4 is greater than 0 and less than 1,
wherein y4 is greater than or equal to 0 and less than 1, and
wherein x4+y4 is greater than 0 and less than or equal to 1,
wherein the second semiconductor layer is disposed on the first semiconductor layer,
wherein the third semiconductor layer is disposed on the second semiconductor layer, and
wherein the fourth semiconductor layer is disposed on the third semiconductor layer.

US Pat. No. 10,483,352

HIGH POWER TRANSISTOR WITH INTERIOR-FED GATE FINGERS

Cree, Inc., Durham, NC (...

1. A transistor device, comprising:a semiconductor structure;
a plurality of gate fingers extending on the semiconductor structure in a first direction;
a plurality of gate interconnects that each have a first end and a second end extending on the semiconductor structure in the first direction, wherein each gate interconnect is connected to a respective gate finger by a plurality of first conductive vias; and
a plurality of gate runners extending on the semiconductor structure in the first direction,
wherein at least one of the gate interconnects is connected to one of the gate runners by a second conductive via at an interior position of the at least one gate interconnect that is remote from the first end and the second end of the at least one gate interconnect.

US Pat. No. 10,483,349

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first semiconductor region including a first partial region and a second partial region and being of a first conductivity type;
a second semiconductor region separated from the first partial region in a second direction crossing a first direction, the second semiconductor region being of the first conductivity type, the first direction being from the first partial region toward the second partial region;
a third semiconductor region provided between the first partial region and the second semiconductor region, the third semiconductor region being of a second conductivity type and comprising a third partial region and a fourth partial region, the fourth partial region being positioned between the first partial region and the third partial region;
a first electrode separated from the second partial region in the second direction and separated from the second semiconductor region and the third semiconductor region in the first direction;
a first insulating film comprising a first insulating region and a second insulating region, the first insulating region being provided between the second semiconductor region and the first electrode in the first direction and between the third semiconductor region and the first electrode in the first direction, a portion of the first insulating region contacting the third partial region, the second insulating region being provided between the second partial region and the first electrode in the second direction; and
a fourth semiconductor region comprising a first portion and being of the first conductivity type, the first portion being provided between the fourth partial region and at least a portion of the first insulating film in the first direction,
wherein
an impurity concentration of the second conductivity type in the third partial region is higher than an impurity concentration of the second conductivity type in the fourth partial region,
the third semiconductor region further comprises a fifth partial region provided between the fourth partial region and the first partial region in the second direction, and
the impurity concentration of the second conductivity type in the fourth partial region is higher than an impurity concentration of the second conductivity type in the fifth partial region.

US Pat. No. 10,483,348

SEMICONDUCTOR DEVICE

SOCIONEXT, INC., Kanagaw...

1. A semiconductor device comprising:a substrate;
a first transistor which includes a first impurity region of a first conductivity type formed in the substrate, and which includes a second impurity region of the first conductivity type formed in the substrate;
a first guard ring of a second conductivity type different from the first conductivity type, formed in the substrate, the first guard ring surrounding the first transistor in a plan view;
a first wiring formed on the first guard ring and electrically connected to the first guard ring; and
a ground wiring formed on the first wiring, the ground wiring being electrically connected to the first wiring and the second impurity region,
wherein
the first transistor includes a first part and a second part which are respectively arranged in a first direction in a plan view,
the first part of the first transistor is separated with a first distance from the first guard ring in a second direction which is perpendicular to the first direction in a plan view,
the second part of the first transistor is separated with a second distance from the first guard ring in the second direction in a plan view,
the second distance is shorter than the first distance,
the first part is separated from the ground wiring in a plan view, and
the second part is overlapped with the ground wiring in a plan view.

US Pat. No. 10,483,346

SEMICONDUCTOR DEVICE WITH SUPPORT PATTERN

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a plurality of pillars on a semiconductor substrate; and
a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another,
wherein:
the support pattern includes openings that expose other lateral surfaces of the pillars,
each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and
the second pillar upper portion has a concave slope.

US Pat. No. 10,483,336

ORGANIC LIGHT EMITTING DISPLAY APPARATUS

LG Display Co., Ltd., Se...

1. An organic light emitting display apparatus, comprising:a substrate;
an auxiliary line on the substrate;
an anode electrode on the substrate;
an auxiliary electrode on the substrate;
an organic emission layer on the anode electrode;
a cathode electrode on the organic emission layer and on the auxiliary electrode;
a bank overlapping with a first portion of the auxiliary electrode and exposing a second portion of the auxiliary electrode;
a partition wall on the second portion of the auxiliary electrode; and
a separation space between the partition wall and the bank, the cathode electrode being electrically connected to the auxiliary electrode through the separation space,
wherein the auxiliary line is connected to the second portion of the auxiliary electrode through a contact hole, and
wherein the auxiliary line is disposed between a plurality of the anode electrodes.

US Pat. No. 10,483,335

ORGANIC LIGHT EMITTING DISPLAY DEVICE HAVING PIXEL DEFINING LAYER

LG Display Co., Ltd., Se...

1. An organic light emitting display device, comprising:a first electrode in an emission area of a subpixel;
a pixel defining layer surrounding the first electrode in a non-emissive area of the subpixel;
a light emitting layer on the first electrode;
a second electrode on the light emitting layer;
a first encapsulation layer on the second electrode; and
a color filter on the first encapsulation layer in the subpixel,
wherein the pixel defining layer includes:
a first pixel defining layer;
a second pixel defining layer on the first pixel defining layer, a width of the second pixel defining layer at any height thereof is wider than a width of the first pixel defining layer at any height thereof;
a first metal layer on the second pixel defining layer; and
a third pixel defining layer on the first metal layer;
wherein a thickness of the third pixel defining layer is thicker than a thickness of each of the first pixel defining layer, the second pixel defining layer, and the first metal layer.

US Pat. No. 10,483,331

COLOR FILTER ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE USING THE SAME

LG DISPLAY CO., LTD., Se...

1. A method of fabricating an organic light emitting diode display device, the method comprising:forming a thin film transistor on a first substrate;
forming an organic light emitting element, which is electrically connected to the thin film transistor, on the first substrate;
forming a black matrix, in which openings are formed, on one surface of a second substrate opposite to the first substrate;
forming a color filter layer in the openings;
forming a transparent insulation layer having a first surface and a second surface opposing the first surface on the second substrate, with the first surface of the transparent insulating layer in direct contact with the color filter layer;
forming a plurality of optical patterns at the second surface of the transparent insulation layer; and
attaching the first substrate and the second substrate such that the second surface of the transparent insulating layer is closer to the thin film transistor than the first substrate.

US Pat. No. 10,483,319

PIXILATED DISPLAY DEVICE BASED UPON NANOWIRE LEDS AND METHOD FOR MAKING THE SAME

GLO AB, Lund (SE)

1. A method of forming a pixilated display device, comprising:growing an array of nanowire LEDs on a substrate, each nanowire LED in the array including a vertical stack, from bottom to top, of a first-wavelength light emitting portion including a first material emitting a first-wavelength light and a second-wavelength light emitting portion including a second material emitting a second-wavelength light; and
while masking a first nanowire LED within the array with a patterned masking layer, removing a second-wavelength light emitting portion from a second nanowire LED within the array;
wherein growing the array of nanowire LEDs on the substrate comprises:
forming a growth mask over the substrate, the growth mask having a first aperture in a first area of the first nanowire LED and a second aperture in a second area of the second nanowire LED;
forming a first nanowire core through the first aperture; and
forming a second nanowire core through the second aperture:
wherein:
the first nanowire LED comprises a core-shell nanowire device that comprises the first nanowire core and a first quantum well shell comprising the first-wavelength light emitting portion, the second-wavelength light emitting portion, and a first pyramidal plane quantum well;
the second nanowire LED comprises a core-shell nanowire device that comprises the second nanowire core and a second quantum well shell comprising the first-wavelength light emitting portion, the second-wavelength light emitting portion, and a second pyramidal plane quantum well;
the first quantum well shell is formed by deposition of an InGaN layer and a GaN layer around the first nanowire core;
the second quantum well shell is formed by deposition of the InGaN layer and the GaN layer around the second nanowire core;
the first quantum well shell and the second quantum well shell are deposited during the same deposition steps;
the first-wavelength light emitting portion of the first nanowire LED comprises a lower portion of the first quantum well shell located over m-plane sidewalls of the first nanowire core;
the second-wavelength light emitting portion of the first nanowire LED comprises an eave region of the first quantum well shell located between the lower portion of the first quantum well shell and the first pyramidal plane quantum well of the first quantum well shell located over pyramidal p-plane sidewalls of the first nanowire core;
the first-wavelength light emitting portion of the second nanowire LED comprises a lower portion of the second quantum well shell located over m-plane sidewalls of the second nanowire core; and
the second-wavelength light emitting portion of the second nanowire LED comprises an eave region of the second quantum well shell located between the lower portion of the second quantum well shell and the second pyramidal plane quantum well of the second quantum well shell located over pyramidal p-plane sidewalls of the second nanowire core.

US Pat. No. 10,483,309

IMAGE SENSORS WITH MULTIPART DIFFRACTIVE LENSES

SEMIDUCTOR COMPONENTS IND...

1. An image sensor comprising a plurality of imaging pixels, wherein each imaging pixel of the plurality of imaging pixels comprises:a photodiode; and
a diffractive lens formed over the photodiode,
wherein the diffractive lens has an edge portion with a first refractive index and a center portion with a second refractive index that is different than the first refractive index and wherein the edge portion is adjacent a solid material with a third refractive index that is different than the first and second refractive indices.

US Pat. No. 10,483,306

PHOTOELECTRIC CONVERSION ELEMENT AND PHOTOELECTRIC CONVERSION DEVICE

Sony Corporation, Tokyo ...

1. A photoelectric conversion element, comprising:a photoelectric conversion region inside a semiconductor layer,
the photoelectric conversion region including a region in which a depletion region is to be formed by voltage application to the semiconductor layer,
the semiconductor layer having a first main surface and a second main surface, the depletion region converting light into a photoelectron, and
the light entering from a side on which the first main surface is disposed;
an isoelectronic trap region in the region in which the depletion region is to be formed;
a pair of first impurity regions formed in the first main surface with a predetermined spacing, the pair of the first impurity regions having an identical electrical-conductivity type to an electrical-conductivity type of the semiconductor layer and having a relatively high impurity concentration; and
a pair of second impurity regions formed in the first main surface, with the pair of the first impurity regions interposed between the pair of the second impurity regions, the pair of the second impurity regions having a different electrical-conductivity type from the electrical-conductivity type of the semiconductor layer,
wherein the isoelectronic trap region is formed at least in the spacing between the pair of the first impurity regions.

US Pat. No. 10,483,303

IMAGE SENSOR HAVING MIRROR-SYMMETRICAL PIXEL COLUMNS

OMNIVISION TECHNOLOGIES, ...

1. An image sensor, comprisinga first pixel unit;
a second pixel unit, vertically adjacent to the first pixel unit;
a third pixel unit, horizontally adjacent to the second pixel unit;
a fourth pixel unit, horizontally adjacent to the first pixel unit and vertically adjacent to the third pixel unit, wherein the first, second, third, and fourth pixel units are arranged into a 2×2 array of pixel units;
a first column bit line coupled to the first pixel unit, wherein image data acquired by the first pixel unit is read out through the first column bit line;
a second column bit line coupled to the second pixel unit, wherein image data acquired by the second pixel unit is read out through the second column bit line;
a third column bit line coupled to the third pixel unit, wherein image data acquired by the third pixel unit is read out through the third column bit line, and wherein the second column bit line is between the first column bit line and the third column bit line; and
a fourth column bit line coupled to the fourth pixel unit, wherein image data acquired by the fourth pixel unit is read out through the fourth column bit line, and wherein the third column bit line is between the second column bit line and the fourth column bit line.

US Pat. No. 10,483,300

OPTICALLY RESTORABLE SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING THE SAME, AND FLASH MEMORY DEVICE USING THE SAME

Electronics and Telecommu...

1. An optically restorable semiconductor device comprising:a gate electrode;
a gate insulation film on the gate electrode;
a photo-responsive semiconductor film on the gate insulation film;
an interface charge part disposed adjacent to an interface between the photo-responsive semiconductor film and the gate insulation film; and
a plasma treatment area provided on the gate insulation film,
wherein the interface charge part comprises charge traps,
wherein the interface charge part and the photo-responsive semiconductor film directly contact each other, and
wherein the plasma treatment area directly contacts the interface charge layer and comprises deep traps.

US Pat. No. 10,483,299

LIGHT-RECEIVING ELEMENT, METHOD OF MANUFACTURING LIGHT-RECEIVING ELEMENT, IMAGING DEVICE, AND ELECTRONIC APPARATUS

SONY SEMICONDUCTOR SOLUTI...

1. A light-receiving element, comprising:a substrate;
a photoelectric conversion layer on the substrate, wherein
the photoelectric conversion layer includes a first compound semiconductor, and
the photoelectric conversion layer absorbs a wavelength in an infrared region to generate electric charges;
a semiconductor layer on the photoelectric conversion layer, wherein
the semiconductor layer includes a second compound semiconductor,
the semiconductor layer has an opening in a first selective region of the semiconductor layer, and
a side face of the opening of the semiconductor layer includes an inclined face; and
a first electrode that buries the opening of the semiconductor layer, wherein the first electrode is electrically coupled to the photoelectric conversion layer.

US Pat. No. 10,483,297

ENERGY HARVESTING DEVICES AND METHOD OF FABRICATION THEREOF

Baupil Photonoics, Inc., ...

1. A thermal energy harvester, comprising:a substrate;
a buffer layer;
a first electrode;
a second electrode;
an absorption layer electrically connected between the first and second electrodes comprising,
a first material;
a second material of a different type that the first material; and
a third material of a different type than the second material;wherein at least one of the first material, the second material, and the third materials are selected from the group consisting of InSb, InAs, GaSb, and PbTe, or a combination thereof, wherein when GaSb is selected, at least one of the first material, the second material, or the third material is selected from the group consisting of InSb, GaAs, InP, GaN, AlN, InAs, and PbTe, or a combination thereof, wherein the first, the second, and the third materials are in a p-n or pin junction with each other in the absorption layer comprises two or more p-n or p-i-n junctions comprising three-dimensional-structures, wherein the two or more p-n or pin junctions are in series increasing the open circuit voltage, and wherein the two or more p-n or p-i-n junctions comprising cutoff wavelength between 2 ?m to 40 ?m.

US Pat. No. 10,483,296

TFT AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. An array substrate, comprising a thin-film transistor (TFT) disposed on a base substrate, wherein the TFT includes:an active layer;
a gate electrode, a source electrode, and a drain electrode respectively electrically connected with the active layer; and
a gate insulating layer disposed between the gate electrode and the active layer, wherein the gate electrode, the source electrode, and the drain electrode are formed by a same film layer, and wherein materials of the gate electrode, the source electrode, and the drain electrode are the same,
wherein the gate insulating layer, the gate electrode, the source electrode, and the drain electrode are formed in a same pattering process, and the same patterning process is performed using a single mask.

US Pat. No. 10,483,295

SEMICONDUCTOR DEVICE COMPRISING RESISTOR COMPRISING METAL OXIDE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a resistor comprising a metal oxide film over an insulating surface and a nitride insulating film in contact with the metal oxide film,
wherein when a region in the metal oxide film is observed with a transmission electron diffraction measurement apparatus while changing an observation area one-dimensionally within a range of 300 nm, a diffraction pattern with luminescent spots indicating alignment is observed in 80% or more and less than 100% of the region,
wherein the metal oxide film is a stack of an In-M-Zn oxide film and an In—N—Zn oxide film, M and N being each Al, Ti, Ga, Y, Zr, Sn, La, Ce, or Nd,
wherein the In-M-Zn oxide film is on and in direct contact with the In—N—Zn oxide film, and
wherein the proportion of M atoms in the In-M-Zn oxide film is higher than the proportion of N atoms in the In—N—Zn oxide film.

US Pat. No. 10,483,293

ACTIVE MATRIX DISPLAY DEVICE, AND MODULE AND ELECTRONIC APPLIANCE INCLUDING THE SAME

Semiconductor Energy Labo...

6. A semiconductor device comprising:first to fifth transistors;
a first light-emitting element;
a first capacitor comprising first and second electrodes;
first to third gate wirings; and
first to fourth wirings,
wherein the second transistor, the fourth transistor, and the third transistor are electrically connected in series between the first wiring and the third wiring,
wherein the first electrode is electrically connected to a first node to which the second transistor and the fourth transistor are electrically connected,
wherein one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring,
wherein the second electrode is electrically connected to the first light-emitting element,
wherein a gate of the first transistor is electrically connected to a second node to which the fourth transistor and the third transistor are electrically connected,
wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the first light-emitting element and the other of the source and the drain of the fifth transistor,
wherein the first gate wiring is electrically connected to a gate of the second transistor,
wherein the second gate wiring is electrically connected to a gate of the third transistor,
wherein the third gate wiring is electrically connected to a gate of the fourth transistor,
wherein the first gate wiring is not electrically connected to the second gate wiring, and
wherein the third gate wiring is not electrically connected to the first gate wiring and the second gate wiring.

US Pat. No. 10,483,290

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising a pixel portion, the pixel portion comprising:a transistor comprising:
a first conductive layer;
a first insulating layer over the first conductive layer;
an oxide semiconductor layer comprising In, Ga, and Zn over the first insulating layer; and
a second conductive layer and a third conductive layer each electrically connected to the oxide semiconductor layer; and
a pixel electrode electrically connected to the transistor,
wherein the first conductive layer serves as a gate electrode of the transistor and a gate wiring,
wherein the second conductive layer serves as one of a source electrode and a drain electrode of the transistor and a source wiring,
wherein the third conductive layer serves as the other of the source electrode and the drain electrode of the transistor,
wherein the first conductive layer and the second conductive layer intersect with each other in a cross shape and overlap each other in a first region,
wherein a first transparent conductive layer comprising In, Zn, and oxygen overlaps the first region, and
wherein a width of a region of the first conductive layer not overlapping with the first region and not overlapping with the oxide semiconductor layer is different from a width of the first conductive layer in the first region.

US Pat. No. 10,483,287

DOUBLE GATE, FLEXIBLE THIN-FILM TRANSISTOR (TFT) COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (MOS) (CMOS) CIRCUITS AND RELATED FABRICATION METHODS

QUALCOMM Incorporated, S...

1. A complementary metal-oxide semiconductor (CMOS) circuit, comprising:a flexible substrate;
at least one P-type Field-Effect Transistor (FET) (PFET) formed on a first surface of the flexible substrate, each of the at least one PFET comprising:
a first gate disposed on the first surface of the flexible substrate;
a P-type thin-film semiconductor structure disposed over the first gate in a first axis direction, the P-type thin-film semiconductor structure comprising a first source/drain region, a second source/drain region, and a first channel region between the first and second source/drain regions; and
a second gate disposed over the P-type thin-film semiconductor structure in the first axis direction opposite to the first gate;
at least one N-type FET (NFET) formed on the first surface of the flexible substrate, each of the at least one NFET comprising:
a third gate disposed on the first surface of the flexible substrate;
an N-type thin-film semiconductor structure disposed over the third gate in the first axis direction, the N-type thin-film semiconductor structure comprising a third source/drain region, a fourth source/drain region, and a second channel region between the third and fourth source/drain regions; and
a fourth gate disposed over the N-type thin-film semiconductor structure in the first axis direction opposite to the third gate; and
at least one metal contact electrically coupling the second source/drain region of the at least one PFET and the third source/drain region of the at least one NFET.

US Pat. No. 10,483,286

ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY, THIN FILM TRANSISTOR, AND MANUFACTURING METHOD OF ARRAY SUBSTRATE

Mitsubishi Electric Corpo...

1. An array substrate comprising a first thin film transistor and a second thin film transistor on a substrate, whereinthe first thin film transistor includes
a first gate electrode provided on the substrate,
a gate insulating film provided covering the first gate electrode,
a first oxide semiconductor layer and a second oxide semiconductor layer provided on the gate insulating film while overlapping the first gate electrode in plan view, with a first separation portion separating the first oxide semiconductor layer and the second oxide semiconductor layer from each other,
a first source electrode and a first drain electrode provided extending from above the first oxide semiconductor layer and above the second oxide semiconductor layer, respectively, onto the gate insulating film while overlapping the first oxide semiconductor layer or the second oxide semiconductor layer in plan view, with a second separation portion, greater than the first separation portion, separating the first source electrode and the first drain electrode from each other, and
an amorphous silicon layer provided extending on the first separation portion on the gate insulating film, the second separation portion, a part of the first source electrode, and a part of the first drain electrode, and
the second thin film transistor includes
a second gate electrode provided on the substrate,
the gate insulating film provided covering the second gate electrode,
a third oxide semiconductor layer provided on the gate insulating film while overlapping the second gate electrode in plan view, and
a second source electrode and a second drain electrode provided extending from above the third oxide semiconductor layer onto the gate insulating film while overlapping the third oxide semiconductor layer in plan view, with a third separation portion separating the second source electrode and the second drain electrode from each other.

US Pat. No. 10,483,284

LOGIC SEMICONDUCTOR DEVICE

Korea University Research...

1. A semiconductor device comprising:a plurality of stacked transistors,
wherein:
each of the transistors comprises:
a semiconductor column including a first conductive region of a first conductivity type, a second conductive region of a second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region;
a gate electrode disposed to cover the intrinsic region; and
a gate insulating layer disposed between the gate electrode and the intrinsic region;
wherein not all of the plurality of stacked transistors have a same first conductivity type, and
wherein:
the plurality of stacked transistors include a first transistor disposed at a lower portion and a second transistor disposed above the first transistor,
the first conductivity type of the first transistor is n-type, and
the first conductivity type of the second transistor is p-type.

US Pat. No. 10,483,279

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Institute of Microelectro...

1. A method of manufacturing a semiconductor device, comprising the steps of:forming a gate dielectric layer and a first amorphous channel layer on a substrate;
thinning the first amorphous channel layer;
etching the first amorphous channel layer and the gate dielectric layer until the substrate is exposed;
forming a second amorphous channel layer on the first amorphous channel layer and the substrate;
annealing such that the first amorphous channel layer and the second amorphous channel layer are converted into a polycrystalline channel layer;
thinning the polycrystalline channel layer.

US Pat. No. 10,483,278

NONVOLATILE MEMORY DEVICES AND METHODS FORMING THE SAME

SAMSUNG ELECTRONICS CO., ...

9. A nonvolatile memory device comprising:a substrate; and
first to fourth gate patterns sequentially stacked in a first direction perpendicular to a top surface of the substrate,
wherein a first distance between a bottom surface of the first gate pattern and a bottom surface of the second gate pattern is greater than a second distance between the bottom surface of the second gate pattern and a bottom surface of the third gate pattern,
wherein a third distance between the bottom surface of the third gate pattern and a bottom surface of the fourth gate pattern is less than the second distance, and
wherein the first to fourth gate patterns have the same thickness.

US Pat. No. 10,483,275

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, the method comprising:(a) forming a first insulating film having a first thickness over a main surface of a semiconductor substrate and then forming a second insulating film having a second thickness larger than the first thickness over the first insulating film;
(b) sequentially processing the second insulating film, the first insulating film, and the semiconductor substrate to form a plurality of trenches and to form a plurality of projecting portions which include portions of the semiconductor substrate extending in a first direction along the main surface of the semiconductor substrate and are spaced apart from each other in a second direction orthogonal to the first direction along the main surface of the semiconductor substrate;
(c) depositing a third insulating film over the main surface of the semiconductor substrate such that the third insulating film is embedded in the trenches;
(d) planarizing an upper surface of the third insulating film and an upper surface of the second insulating film;
(e) removing the second insulating film;
(f) performing isotropic dry etching to remove the first insulating film, expose respective upper surfaces of the projecting portions, recess an upper surface and a side surface of the third insulating film, and expose respective side walls of the projecting portions from the upper surface of the third insulating film;
(g) forming a first gate electrode extending in the second direction such that a fourth insulating film is interposed between the first gate electrode and each of the respective upper surfaces and side walls of the projecting portions which are exposed from the upper surface of the third insulating film; and
(h) forming a second gate electrode extending in the second direction such that a fifth insulating film including a trapping insulating film is interposed between the second gate electrode and each of the respective upper surfaces and side walls of the projecting portions which are exposed from the upper surface of the third insulating film and one of side walls of the first gate electrode,
wherein, between the projecting portions adjacent to each other in the second direction, a portion of the upper surface of the third insulating film is higher in level than a first surface obtained by connecting a position of the upper surface of the third insulating film which is in contact with the side wall of one of the projecting portions to a position of the upper surface of the third insulating film which is in contact with the side wall of other projecting portion.

US Pat. No. 10,483,268

SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL ARRAY WITH TRANSISTORS DISPOSED IN DIFFERENT ACTIVE REGIONS

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first conductivity type first MIS transistor electrically connected between a first node with which a first potential is supplied and a second node;
a second conductivity type first MIS transistor electrically connected between the second node and a third node with which a second potential different from the first potential is supplied;
a second conductivity type second MIS transistor electrically connected between the second node and the third node in parallel with the second conductivity type first MIS transistor;
a first conductivity type second MIS transistor electrically connected between the first node and a fourth node;
a second conductivity type third MIS transistor electrically connected between the third node and the fourth node;
a second conductivity type fourth MIS transistor electrically connected between the third node and the fourth node in parallel with the second conductivity type third MIS transistor;
a second conductivity fifth MIS transistor electrically connected between the second node and a fifth node;
a second conductivity type sixth MIS transistor electrically connected between the fourth node and a sixth node;
a first conductivity type first well region;
a first conductivity type second well region; and
a second conductivity type well region arranged between the first conductivity type first well region and the first conductivity type second well region,
wherein the second conductivity type first MIS transistor and the second conductivity type fifth MIS transistor are arranged in a first active region,
wherein the second conductivity type second MIS transistor is arranged in a second active region which is separated from the first active region, and which is arranged next to the first active region,
wherein the second conductivity type third MIS transistor is arranged in a third active region,
wherein the second conductivity type fourth MIS transistor and the second conductivity type sixth MIS transistor are arranged in a fourth active region which is separated from the third active region, and which is arranged next to the third active region,
wherein the first, second, third and fourth active regions are arranged in a first direction, and arranged in sequence, and separated from one another,
wherein, in plan view, the first active region and the second active region are arranged in the first conductivity type first well region,
wherein, in plan view, the third active region and the fourth active region are arranged in the first conductivity type second well region,
wherein a gate electrode of the second conductivity type fifth MIS transistor is comprised of a first part of a first gate wiring which is extended in the first direction, and which is arranged over the first active region,
wherein a gate electrode of the second conductivity type first MIS transistor is comprised of a second part of a second gate wiring which is extended in the first direction, and which is arranged over the first active region and the second active region,
wherein a gate electrode of the second conductivity type second MIS transistor is comprised of a third part of the second gate wiring,
wherein a gate electrode of the second conductivity type third MIS transistor is comprised of a fourth part of a third gate wiring which is extended in the first direction, and which is arranged over the third active region and the fourth active region,
wherein a gate electrode of the second conductivity type fourth MIS transistor is comprised of a fifth part of the third gate wiring,
wherein a gate electrode of the second conductivity type sixth MIS transistor is comprised of a sixth part of a fourth gate wiring which is extended in the first direction, and which is arranged over the fourth active region,
wherein a length of the first active region in a second direction crossing to the first direction is longer than a length of the second active region in the second direction, and
wherein a length of the fourth active region in the second direction is longer than a length of the third active region in the second direction.

US Pat. No. 10,483,267

EIGHT-TRANSISTOR STATIC RANDOM-ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A Static Random Access Memory (SRAM) cell, comprising:a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and
a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each other, gate electrodes of the read pull-down transistor, the second pull-down transistor, and the second pull-up transistors being electrically connected to each other,
wherein a first doping concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doping concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.

US Pat. No. 10,483,266

FLEXIBLE MERGE SCHEME FOR SOURCE/DRAIN EPITAXY REGIONS

Taiwan Semiconductor Manu...

1. A method comprising:forming a first gate stack extending on top surfaces and sidewalls of first semiconductor fins, wherein the first semiconductor fins are parallel to, and are neighboring, each other;
forming a second gate stack extending on top surfaces and sidewalls of second semiconductor fins, wherein the second semiconductor fins are parallel to, and are neighboring, each other;
forming a dielectric layer, wherein the dielectric layer comprises a first portion extending on the first gate stack and the first semiconductor fins, and a second portion extending on the second gate stack and the second semiconductor fins;
in a first etching process, etching the first portion of the dielectric layer to form first fin spacers on sidewalls of the first semiconductor fins, wherein the first fin spacers have a first height;
in a second etching process, etching the second portion of the dielectric layer to form second fin spacers on sidewalls of the second semiconductor fins, wherein the second fin spacers have a second height greater than the first height;
recessing the first semiconductor fins to form first recesses between the first fin spacers;
recessing the second semiconductor fins to form second recesses between the second fin spacers; and
simultaneously growing first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses, wherein the first epitaxy semiconductor regions grown from neighboring ones of the first recesses merge with each other, and the second epitaxy semiconductor regions grown from neighboring ones of the second recesses are separate from each other.

US Pat. No. 10,483,260

SEMICONDUCTOR CARRIER WITH VERTICAL POWER FET MODULE

1. A monolithic power management module, comprising:a chip carrier further comprising surfaces, ground traces, signal and power interconnects;
a three dimensional FET formed on the chip carrier to modulate currents through the chip carrier or on the surfaces;
a toroidal inductor or transformer coil with a ceramic magnetic core formed on the chip carrier adjacent to the three dimensional FET and having a first winding connected to the three dimensional FET, and
a plurality of passive ceramic components formed on the chip carrier surfaces including clock circuitry in a form of an LCR resonator further comprising an inductor coil, a capacitive element and a resistive element; and
wherein the three dimensional FET includes an elongated gate electrode comprising a conductor that forms a resonant transmission line by configuring the conductor to form a serpentine electrode that contains a capacitive element determined by charge-collected beneath the gate, a resistive dement determined by the conductor, length and cross-sectional area, of the conductor used to form the serpentine electrode, and an Inductive element formed by half-turns that loop the serpentine electrode winding back upon itself.

US Pat. No. 10,483,258

SEMICONDUCTOR DEVICES AND METHODS TO ENHANCE ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS, LATCH-UP, AND HOT CARRIER IMMUNITY

INDIAN INSTITUTE OF SCIEN...

2. A semiconductor device comprising at least one ESD protection device and at least one functional device, wherein the at least one ESD protection device comprises one or more fins having a selective epitaxial growth before a silicidation, and wherein the at least one functional device comprises one or more fins fully silicided, without an epitaxial growth.

US Pat. No. 10,483,257

LOW VOLTAGE NPN WITH LOW TRIGGER VOLTAGE AND HIGH SNAP BACK VOLTAGE FOR ESD PROTECTION

NXP USA, Inc., Austin, T...

1. A method of fabricating a semiconductor device comprising:forming a first region of semiconductor material having a first conductivity type over a semiconductor substrate layer;
forming an epitaxial semiconductor layer of a second conductivity type having a first doping level and overlying the semiconductor substrate layer;
forming an upper semiconductor layer of the second conductivity type having a second doping level higher than the first doping level over the epitaxial semiconductor layer;
forming a plurality of shallow trench isolation structures on an upper surface of the semiconductor device to define first and third substrate regions spaced apart on each side from a second substrate region over the semiconductor layer;
forming collector and emitter contact regions of the second conductivity type in each of the first and second substrate regions, respectively;
forming a base contact region of the first conductivity type in the third substrate region;
forming separate halo extension regions to surround and enclose at least the collector and emitter contact regions; and
forming first and second terminals such that the first terminal comprises emitter and base contact terminals in direct contact with the emitter and base contact regions and such that the second terminal comprises a collector contact terminal in electrical contact with the collector contact region, thereby forming a single polarity electrostatic discharge (ESD) clamp coupled between the first and second terminals.

US Pat. No. 10,483,256

OPTOELECTRONIC SEMICONDUCTOR DEVICE AND APPARATUS WITH AN OPTOELECTRONIC SEMICONDUCTOR DEVICE

OSRAM OPTO SEMICONDUCTORS...

1. An optoelectronic semiconductor device comprising:an emission region comprising a semiconductor layer sequence with a first semiconductor layer, a second semiconductor layer and, arranged between the first semiconductor layer and the second semiconductor layer, an active region configured to generate radiation;
a protection diode region; and
a contact for external electrical contacting of the optoelectronic semiconductor device,
wherein the contact comprises a first contact region electrically conductively connected to the emission region,
wherein the contact comprises a second contact region located at a distance from the first contact region and electrically conductively connected to the protection diode region,
wherein the second contact region is not directly electrically connected to the emission region,
wherein the first contact region and the second contact region are externally electrically contactable by a common end of a single connecting lead,
wherein the single connecting lead is a wire bond connection,
wherein the semiconductor layer sequence is arranged on a carrier,
wherein the first semiconductor layer is electrically conductively connected in the emission region to a first connection layer, and
wherein the first connection layer extends in places between the carrier and the emission region.

US Pat. No. 10,483,249

INTEGRATED PASSIVE DEVICES ON CHIP

Intel Corporation, Santa...

1. A device comprising:a semiconductor die;
a semiconductor die package, a first side of the package being coupled with the semiconductor die; and
one or more separate dies to provide a plurality of passive components for operation of the semiconductor die, wherein the plurality of passive components for operation of the semiconductor die includes a plurality of inductors and a plurality of capacitors, and wherein a first separate die includes a first set of passive components on a first side of the first separate die and a second, different set of passive components on a second, opposite side of the first separate die.

US Pat. No. 10,483,248

WAFER LEVEL CHIP SCALE FILTER PACKAGING USING SEMICONDUCTOR WAFERS WITH THROUGH WAFER VIAS

SKYWORKS SOLUTIONS, INC.,...

1. An electronics package comprising:a semiconductor substrate having one or more passive devices formed on the semiconductor substrate and a cavity defined in a first surface of the semiconductor substrate; and
a piezoelectric substrate bonded to the semiconductor substrate and having a microelectromechanical device formed on the piezoelectric substrate, the microelectromechanical device disposed within the cavity defined in the semiconductor substrate.

US Pat. No. 10,483,246

POWER DEVICE CASSETTE WITH AUXILIARY EMITTER CONTACT

Littlefuse, Inc., Chicag...

1. A method comprising:providing a power semiconductor device die so that the power semiconductor device die is disposed between a pedestal of a disc-shaped bottom plate member and a disc-shaped top plate member, wherein the disc-shaped bottom plate member, the disc-shaped top plate member, and the power semiconductor device die are parts of a press pack semiconductor device module;
providing a first conductive path between a first pad on the power semiconductor device die and a first terminal of the press pack semiconductor device module, wherein the first conductive path extends through a first contact pin that contacts the power semiconductor device die, and wherein the first conductive path extends through neither the disc-shaped top plate member nor the disc-shaped bottom plate member; and
providing a second conductive path between a second pad on the power semiconductor device die and a second terminal of the press pack semiconductor device module, wherein the second conductive path extends through a second contact pin that contacts the power semiconductor device die, and wherein the second conductive path extends through neither the disc-shaped top plate member nor the disc-shaped bottom plate member.

US Pat. No. 10,483,244

POWER SEMICONDUCTOR MODULE

ABB Schweiz AG, Baden (C...

1. A power semiconductor module comprising:a first main electrode, a second main electrode, and a control terminal, controllable power semiconductor components arranged between the first main electrode and the second main electrode, wherein each controllable power semiconductor component has a first electrode, a second electrode and a control electrode, and the first electrode of each controllable power semiconductor component is electrically connected to the first main electrode, the second electrode of each controllable power semiconductor component is electrically connected to the second main electrode, and the control electrode of each controllable power semiconductor component is electrically connected to the control terminal, wherein the controllable power semiconductor components are arranged in a plurality of ring arrangements, and
an electrically conductive contact element arranged between the second main electrode of the power semiconductor module and each controllable power semiconductor component, said contact element connecting the second main electrode to the second electrode of the power semiconductor component, wherein the contact element and the power semiconductor component define a current carrying direction that is at least approximately at right angles with respect to the first main electrode,
wherein each ring arrangement of the plurality of ring arrangements has the respective controllable power semiconductor components arranged at least approximately along a first circular line as well as a control conductor track which is arranged on the first main electrode and runs at least approximately along a second circular line, the second circular line of the respective ring arrangement runs concentrically and outside relative to the first circular line of the respective ring arrangement, wherein all of the controllable power semiconductor components are arranged in the plurality of ring arrangements,
wherein the control electrode of each controllable power semiconductor component of the respective ring to the control conductor track of the respective ring arrangement, and the control conductor track of the respective ring arrangement is connected via a further electrical connection to the control terminal, and
wherein the further electrical connection runs at least substantially parallel to the current carrying direction.

US Pat. No. 10,483,243

SEMICONDUCTOR DEVICES INCLUDING STACKED SEMICONDUCTOR CHIPS

Samsung Electronics Co., ...

1. A semiconductor device comprising:a chip stack structure comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip,
wherein the first semiconductor chip comprises:
a first substrate;
a first circuit layer on a front surface of the first substrate; and
a first connecting layer on the first circuit layer, the first connecting layer comprising a first metal pad electrically connected to the first circuit layer,
wherein the second semiconductor chip comprises:
a second substrate;
a second circuit layer on a front surface of the second substrate; and
a second connecting layer on the second circuit layer, the second connecting layer comprising a second metal pad electrically connected to the second circuit layer,
wherein the first connecting layer and the second connecting layer face each other,
wherein the first metal pad and the second metal pad are in contact with each other to couple the first and second semiconductor chips to each other,
wherein the first metal pad comprises a plurality of first metal pad portions separated from each other by first partitions,
wherein the second metal pad comprises a plurality of second metal pad portions separated from each other by second partitions, and
wherein at least one of the first and second semiconductor chips further comprises a through-via penetrating the respective substrate thereof.

US Pat. No. 10,483,241

SEMICONDUCTOR DEVICES WITH THROUGH SILICON VIAS AND PACKAGE-LEVEL CONFIGURABILITY

Micron Technology, Inc., ...

11. A semiconductor device assembly, comprising:a substrate including a substrate contact; and
a plurality of semiconductor dies, each including:
a first contact pad electrically coupled to a first circuit on the semiconductor die including at least one active circuit element,
a first through-silicon via (TSV) electrically coupling the first contact pad to a first backside contact pad of the semiconductor die, and
a second contact pad electrically coupled to a second circuit on the semiconductor die including only passive circuit elements;
wherein the first contact pads, the first TSVs, and the first backside contact pads of all of the plurality of semiconductor dies are electrically coupled to the substrate contact, and
wherein the second contact pads of some, but less than all, of the plurality of semiconductor dies are electrically coupled to the substrate contact.

US Pat. No. 10,483,239

SEMICONDUCTOR DEVICE INCLUDING DUAL PAD WIRE BOND INTERCONNECTION

SanDisk Semiconductor (Sh...

1. A semiconductor die, comprising:a first major surface;
a second major surface opposed to the first major surface;
integrated circuits formed adjacent the first major surface in an active area;
a set of functional die bond pads spaced inward from an edge of the semiconductor die and electrically connected to the integrated circuits by metal interconnects within the active area;
a set of dummy die bond pads at the edge of the semiconductor die and adjacent the set of functional die bond pads, the set of dummy die bond pads configured to receive a first set of bond wires; and
a second set of bond wires electrically interconnecting respective pairs of functional die bond pads from the set of functional die bond pads and dummy die bond pads from the set of dummy die bond pads.

US Pat. No. 10,483,237

VERTICALLY STACKED MULTICHIP MODULES

Semiconductor Components ...

1. A circuit assembly apparatus comprising:a first semiconductor die;
a second semiconductor die;
a first substrate including:
a first insulating layer;
a first metal layer disposed on a first side of the first insulating layer, a first side of the first semiconductor die being disposed on and electrically coupled with the first metal layer;
a second metal layer disposed on a second side of the first insulating layer, the second side of the first insulating layer being opposite the first side of the first insulating layer, a first side of the second semiconductor die being disposed on and electrically coupled with the second metal layer; and
a conductive via disposed through the first insulating layer, the conductive via electrically coupling the first metal layer with the second metal layer,
the first metal layer, the conductive via and the second metal layer electrically coupling the first semiconductor die with the second semiconductor die; and
a second substrate having:
a second insulating layer;
a third metal layer disposed on a first side of the second insulating layer, a second side of the first semiconductor die being disposed on and electrically coupled with the third metal layer, the second side of the first semiconductor die being opposite the first side of the first semiconductor die; and
a fourth metal layer disposed on a second side of the second insulating layer, the second side of the second insulating layer being opposite the first side of the second insulating layer, the fourth metal layer being electrically isolated from the third metal layer by the second insulating layer.

US Pat. No. 10,483,234

CHIP PACKAGES AND METHODS OF MANUFACTURE THEREOF

Taiwan Semiconductor Manu...

1. A chip package comprising:a plurality of first chips laterally adjacent to each other, each of the plurality of first chips having a plurality of first contact pads on a first surface thereof;
first redistribution layers (RDLs) at the first surfaces of the first chips, wherein the first RDLs are separate from each other, wherein each of the first RDLs contacts the first surface of a respective first chip and is laterally conterminous with the respective first chip;
a second chip attached to the first surfaces of the plurality of first chips, the second chip having a plurality of second contact pads on a first surface thereof, wherein the first surface of the second chip faces away from the plurality of first chips, wherein a first portion of the second chip is disposed within lateral extents of a third chip of the plurality of first chips, and a second portion of the second chip is disposed within lateral extents of a fourth chip of the plurality of first chips;
an adhesive layer between the second chip and the plurality of first chips, the adhesive layer being attached to and contacting a second surface of the second chip opposing the first surface of the second chip, the adhesive layer having a same width as the second chip, a first portion of the adhesive layer being attached to the third chip of the plurality of first chips, and a second portion of the adhesive layer being attached to the fourth chip of the plurality of first chips;
a second RDL coupled to the plurality of second contact pads of the second chip, wherein the second chip is between the second RDL and the plurality of first chips;
a plurality of first conductive pillars laterally separated from the second chip, the plurality of first conductive pillars extending from the second RDL to corresponding ones of a first group of the plurality of first contact pads, the first group disposed outside a width of the second chip; and
a molding compound around the plurality of first chips, the second chip, and the plurality of first conductive pillars.

US Pat. No. 10,483,233

SPLIT BALL GRID ARRAY PAD FOR MULTI-CHIP MODULES

International Business Ma...

1. A multi-chip module, comprising:a substrate containing multiple wiring layers, each wiring layer having multiple wires, first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, wherein the first section is connected by a first wire of the multiple wires to a pad of a first group of the first pads, wherein the non-contiguous second section is connected by a second wire of the multiple wires to a pad of a second group of the first pads, and wherein another pad of the second pads is a conventional pad having a contiguous top surface and a contiguous bottom surface;
a first solder ball in direct physical contact with the contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height in a first direction, and wherein the first direction is perpendicular to the contiguous bottom surface of the conventional pad; and
a second solder ball in direct physical contact with the first section and the non-contiguous second section of the split pad, wherein the second solder ball has a second height in the first direction, and wherein the second height is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging,
wherein a first active component is attached to the first group of the first pads and a second active component is attached to the second group of the first pads.

US Pat. No. 10,483,232

METHOD FOR FABRICATING BUMP STRUCTURES ON CHIPS WITH PANEL TYPE PROCESS

PHOENIX PIONEER TECHNOLOG...

1. A method for fabricating a bump structure on a chip with panel type process, comprising in sequential order:providing an integrated carrier and a plurality of semiconductor chips, which has an active side and a reverse side relative to the active side, the active side of each semiconductor chip has a plurality of metal electrode pads and an insulated protecting layer, which is exposed out of the metal electrode pads;
fixing the reverse side of each semiconductor chip on the integrated carrier;
executing an electroless plating process to form an under bump metallurgy (UBM) structure on the metal electrode pad of each semiconductor chip, wherein the coverage range of the UBM structure is equal to the coverage range of the metal electrode pad;
forming a dielectric layer to cover the integrated carrier, the semiconductor chips and the UBM structure;
forming a plurality of via holes through the dielectric layer and are exposed out of the UBM structure by laser drill or lithography including exposure and development processes; and forming a plurality of metal bumps in the corresponding via hole of the dielectric layer, respectively;
wherein the electrode pad is an aluminum metal electrode pad, and the electroless plating process includes an electroless nickel plating process, a first electroless gold plating process, an electroless palladium plating process and a second electroless gold plating process that is forming a nickel metal layer on the aluminum metal electrode pad, forming a first gold metal layer on the nickel metal layer, forming a palladium metal layer on the first gold metal layer and forming a second gold metal layer on the palladium metal layer; and
wherein the order of arrangement from below is respectively the aluminum metal electrode pad, the nickel metal layer, the first gold metal layer, the palladium metal layer, the second gold metal layer and the metal bump.

US Pat. No. 10,483,217

WARPAGE BALANCING IN THIN PACKAGES

Invensas Corporation, Sa...

1. A method of fabricating a microelectronic assembly, comprising:forming a plurality of conductive terminals on a surface of a carrier or a package;
deforming each conductive terminal of the plurality of conductive terminals;
forming a reinforcement layer on the surface of the carrier or the package to add structural support to the carrier or the package, the reinforcement layer surrounding each conductive terminal;
partially or completely detaching each conductive terminal from the reinforcement layer while maintaining a connection of each conductive terminal to the surface of the carrier or the package.

US Pat. No. 10,483,216

POWER MODULE AND FABRICATION METHOD FOR THE SAME

ROHM CO., LTD., Kyoto (J...

1. A power module comprising:a substrate;
a first electrode pattern, a second electrode pattern, a first signal electrode pattern, and a second signal electrode pattern respectively disposed on the substrate;
a semiconductor device disposed on a first surface of the second electrode pattern, the first surface being opposite to a second surface of the second electrode pattern on which the substrate is disposed; and
a leadframe bonded to an upper surface of the semiconductor device, wherein
the leadframe is divided into a plurality of leadframes, wherein
the leadframe divided into the plurality of frames comprises:
a first leadframe configured to conduct a principal current, the first leadframe being bonded to the first electrode pattern and the upper surface of the semiconductor device, and
a second leadframe electrically insulated from the first leadframe, the power module further comprising:
a first bonding wire connecting between the first leadframe and the first signal electrode pattern; and
a second bonding wire connecting between the second leadframe and the second signal electrode pattern.

US Pat. No. 10,483,213

DIE IDENTIFICATION BY OPTICALLY READING SELECTIVELY BLOWABLE FUSE ELEMENTS

STMicroelectronics S.r.l....

1. An integrated circuit, comprising:integrated functional circuitry;
an array of fuse elements, each fuse element having a first terminal and a second terminal, wherein the first terminals are directly connected to a fuse sensing node;
a first switch actuated by a first control signal to apply a programming voltage to the fuse sensing node;
a second switch actuated by a second control signal to apply a reading current to the fuse sensing node; and
a demultiplexing circuit comprising:
a switching circuit connected in series with each fuse element within the array of fuse elements at the second terminal; and
a decoder circuit configured to:
selectively actuate the switching circuits in a first mode when the first control signal actuates the first switch and the second switch is deactuated so as to cause the programming voltage to be applied at the fuse sensing node and across selected ones of the fuse elements within the array of fuse elements which is sufficient to blow the selected fuse element so as to program individual fuse elements within the array of fuse elements with data bits defining a die identification that specifies a location of the integrated circuit die on a wafer from which the integrated circuit die was singulated; and
selectively actuate the switching circuits in a second mode when the second control signal actuates the second switch and the first switch is deactuated so as to cause the reading current to be applied at the fuse sensing node and across the fuse elements within the array of fuse elements to generate an output signal at the fuse sensing node indicating whether the fuse element is blown so as to read the data bits defining the die identification.

US Pat. No. 10,483,211

FAN-OUT PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

MediaTek Inc., Hsin-Chu ...

1. A semiconductor package structure, comprising:a first semiconductor package, comprising:
a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto;
two electronic components respectively disposed on and electrically coupled to the first and second surface of the first RDL structure;
a first semiconductor die disposed on and electrically coupled to the first surface of the first RDL structure;
a first molding compound disposed on the first surface of the first RDL structure and surrounding the first semiconductor die;
a plurality of screen printed solder balls embedded in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure;
wherein the first molding compound comprises a plurality of openings to correspondingly expose the plurality of screen printed solder balls;
wherein the semiconductor package structure further comprises a plurality of first conductive structures that fill the plurality of openings and are in contact with the plurality of screen printed solder balls; and
wherein the semiconductor package structure further comprises a second semiconductor package coupled to the first semiconductor package by the plurality of first conductive structures, the second semiconductor package being spaced within 50 microns of the first semiconductor package.

US Pat. No. 10,483,209

IMPEDANCE CONTROLLED ELECTRICAL INTERCONNECTION EMPLOYING META-MATERIALS

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a plurality of layers to be secured to provide electrical interconnection between a plurality of first bond pads of a first device and a plurality of second bond pads of a second device, wherein the plurality of layers includes:
a first conductor layer arranged to extend continuously along a portion of a length of the first device and the second device, such that the first conductor layer physically contacts the plurality of first bond pads of the first device and the plurality of second bond pads of the second device when secured;
a second conductor layer disposed over the first conductor layer, wherein the second conductor layer includes a plurality of electrically independent conductors arranged to span a length that is about the portion of the length of the first device and the second device when secured; and
a third conductor layer disposed over the second conductor layer, such that the second conductor layer is disposed between the first conductor layer and the third conductor layer, wherein the third conductor layer is arranged to extend continuously along the portion of the length of the first device and the second device when secured.

US Pat. No. 10,483,204

LOGIC CELL STRUCTURE WITH INTERCONNECTION DESIGN AND CONFIGURATION

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:a semiconductor substrate;
a plurality of field-effect transistors (FETs) disposed on the semiconductor substrate, wherein the FETs include gates with elongated shape oriented in a first direction;
a first metal layer disposed over the gates, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction;
a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction; and
a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction, wherein
the first metal lines have a first pitch P1;
the second metal lines have a second pitch P2;
the third metal lines have a third pitch P3; and
the gates have a fourth pitch P4, wherein a ratio of the second pitch over the fourth pitch P2:P4 is about 3:2.

US Pat. No. 10,483,193

ELECTRICAL CONNECTIVITY FOR CIRCUIT APPLICATIONS

Infineon Technologies Ame...

1. A method comprising:aligning a face of a chip substrate with respect to an electrically conductive surface of a host substrate, the chip substrate fabricated to include first switch circuits and second switch circuits, a sequence of nodes of the second switch circuits disposed on the face of the chip substrate alongside and substantially parallel to a sequence of nodes of the first switch circuits; and
coupling the sequence of nodes of the first switch circuits and the sequence of nodes of the second switch circuits to an electrically conductive surface of the host substrate.

US Pat. No. 10,483,190

THERMAL CONDUCTION STRUCTRURE AND MANUFACTURING METHOD THEREOF

TAIWAN MICROLOOPS CORP., ...

1. A thermal conduction structure, comprising:a vapor chamber, including an upper casing, a lower casing sealed and engaged with the upper casing, and a cavity formed between the lower casing and the upper casing, and the upper casing having at least one through hole communicated with the cavity, and a first capillary tissue being disposed on the internal surface of the upper casing, and the first capillary tissue being a braided metal mesh having at least one penetrating hole formed thereon and configured to be corresponsive to the at least one through hole, and a plurality of dividing lines formed around an outer periphery of the at least one penetrating hole;
at least one heat pipe, including a tube and a second capillary tissue, the tube having an open end and a closed end, and the second capillary tissue being coated on an inner surface of the tube without filling the tube, and further extended out from the tube to define an exposed section; after the at least one heat pipe being passed through and coupled to the at least one through hole, the exposed section being passed through the at least one penetrating hole to force the first capillary tissue around the periphery of the at least one penetrating hole to bend and deform to be against the exposed section; and
a working fluid, filled in the cavity;
wherein an inner surface of the lower casing has a third capillary tissue disposed thereon, the exposed section is inserted into the cavity without contacting the third capillary tissue; and
wherein a bottom surface of the tube at the open end is coplanar with an inner side of a top surface of the upper casing, so the tube is not inserted inside the vapor chamber.

US Pat. No. 10,483,188

COMPENSATION OF AN ARC CURVATURE GENERATED IN A WAFER

1. Method for performing compensation of a bow generated in a wafer made from a material, the wafer comprising opposite first and second surfaces, the material of the wafer having a coefficient of thermal expansion noted ?0; the method comprising the steps of:a) forming a set of first trenches on the first surface of the wafer, the first surface being designed to comprise electronic components;
b) forming a set of second trenches on the second surface of the wafer, at least partially facing the first trenches;
c) filling the first trenches with a first material having a coefficient of thermal expansion ?1;
d) filling the second trenches with a second material having a coefficient of thermal expansion ?2, and verifying ?2>?0 or ?2?0 or ?1 wherein step a) is executed in such a way that first trenches of the set of first trenches define a cutting path of the wafer and step b) is executed in such a way that the set of second trenches are totally facing said first trenches of the set of first trenches.

US Pat. No. 10,483,183

SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor element;
a temperature detecting element provided at a central part of a surface of the semiconductor element; and
a heat conductor jointed to the surface of the semiconductor element via a jointing element,
wherein
the jointing element comprises a central part positioned over the temperature detecting element, and a peripheral part positioned on a periphery of the central part of the jointing element, and
the heat conductor comprises a metal part being in contact with the central part of the jointing element, and a graphite part being in contact with the peripheral part of the jointing element.

US Pat. No. 10,483,179

SEMICONDUCTOR DEVICE WITH SEALING PORTION TO SUPPRESS CONNECTION CORROSION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor element having a first pad formed of AlSiCu or AlCu;
a frame member having a second pad;
a connection member that contains at least one of copper and silver and connects the first pad and the second pad; and
a sealing portion that is formed of resin composition containing no sulfur in excess of 100 ppm as measured by extraction from the sealing portion by ion chromatographic analysis under an extraction condition that the temperature is 150° C. and the duration of time is 100 hours, the sealing portion sealing the semiconductor element, the frame member, and the connection member,
wherein arithmetic mean roughness of an upper surface of the first pad is equal to or greater than 0.02 ?m.

US Pat. No. 10,483,178

SEMICONDUCTOR DEVICE INCLUDING AN ENCAPSULATION MATERIAL DEFINING NOTCHES

Infineon Technologies AG,...

1. A semiconductor device comprising:a first contact element on a first side of the semiconductor device;
a second contact element on a second side of the semiconductor device opposite to the first side;
a semiconductor chip electrically coupled to the first contact element and the second contact element; and
an encapsulation material encapsulating the semiconductor chip and portions of the first contact element and the second contact element, the encapsulation material defining at least two notches on a third side of the semiconductor device extending between the first side and the second side, the third side having a length extending between the first side and the second side and having a width perpendicular to the length, wherein the width is less than the length, wherein the at least two notches extend across the width.

US Pat. No. 10,483,176

SEMICONDUCTOR MODULE

Mitsubishi Electric Corpo...

1. A semiconductor module comprising:a base plate;
at least one semiconductor chip disposed above a region of the base plate inside of an outer peripheral region of the base plate; and
a case joined to the outer peripheral region of the base plate with an adhesive, and containing the at least one semiconductor chip, wherein
a protrusion is disposed on an upper surface of the base plate or the upper surface of the base plate comprises a recess, the recess or the protrusion being adjacent to an inner wall of the case and between the inner wall of the case and the at least one semiconductor chip in a plan view,
the adhesive comprises a fillet-shaped portion between the inner wall of the case and the recess or the protrusion, and
the fillet-shaped portion extends in a direction towards the at least one semiconductor device along the upper surface of the base plate from the inner wall of the case to an outermost side of the recess or protrusion adjacent to the inner wall of the case.

US Pat. No. 10,483,172

TRANSISTOR DEVICE STRUCTURES WITH RETROGRADE WELLS IN CMOS APPLICATIONS

GLOBALFOUNDRIES Inc., Gr...

1. A device, comprising:a substrate comprising an N-active region and a P-active region;
a layer of silicon-carbon positioned on an upper surface of said N-active region but not on an upper surface of said P-active region;
a first layer of a first semiconductor material positioned on said layer of silicon-carbon, wherein an upper surface of said first layer of said first semiconductor material is substantially level with an upper surface of an isolation region defining said N-active region;
a second layer of said first semiconductor material positioned on said upper surface of said P-active region;
a layer of a second semiconductor material positioned on said second layer of said first semiconductor material;
an N-type transistor positioned in and above said N-active region; and
a P-type transistor positioned in and above said P-active region.

US Pat. No. 10,483,168

LOW-K GATE SPACER AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A method comprising:forming a dielectric surface over an active area on a substrate;
forming an inhibitor layer on an exposed surface of the active area;
after forming the inhibitor layer, selectively depositing a low-k spacer along the dielectric surface, the low-k spacer having a dielectric constant equal to or less than 3.9 , wherein a portion of an upper surface of the inhibitor layer remains free of a layer of a material of the low-k spacer while selectively depositing the low-k spacer; and
after selectively depositing the low-k spacer, forming a gate structure along the low-k spacer.

US Pat. No. 10,483,166

VERTICALLY STACKED TRANSISTORS

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a vertically stacked nanosheet semiconductor device, the method comprising:forming a nanosheet stack by epitaxially growing alternating layers of a first material and a second material on a substrate and patterning a gate structure on the nanosheet stacks;
performing a first reactive ion etch on the nanosheet stack forming recesses on the substrate;
performing a second reactive ion etch on the alternating layers of the first material and the second material;
depositing inner spacers and a shallow trench isolation layer in the recesses;
forming source or drain (S/D) regions in a channel formed by the shallow trench isolation layer;
growing a first epitaxial layer on the source or drain regions, forming a first pFET structure and a second pFET structure;
etching away a portion of the first pFET structure and the second pFET structure and depositing a dielectric layer on the first pFET structure and the second pFET structure; and
growing a second epitaxial layer on the source or drain regions, forming a first nFET structure and a second nFET structure;
wherein at least one of the first pFET structure and the first nFET structure or the second pFET structure and the second nFET structure have individual contacts, wherein the individual contacts enable independent voltage control across the semiconductor device.

US Pat. No. 10,483,162

SEMICONDUCTOR STRUCTURE OF INTERCONNECT AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method of forming a semiconductor structure, comprising:providing a substrate;
forming a dielectric layer with an opening on the substrate;forming a first barrier layer on sidewall and bottom surfaces of the opening, wherein the first barrier layer is made of a material including tantalum nitride doped with manganese, the first barrier layer is formed by an atomic layer deposition process, and forming the first barrier layer comprises:introducing a tantalum source gas to the substrate, a portion of the tantalum source gas being adsorbed on the substrate;
evacuating the tantalum source gas that is not adsorbed on the substrate;
introducing a manganese source gas to the substrate, a portion of the manganese source gas being adsorbed on the substrate;
evacuating the manganese source gas that is not adsorbed on the substrate;
introducing a nitrogen source gas to the substrate, a portion of the nitrogen source gas being adsorbed on the substrate; and
evacuating the nitrogen source gas that is not adsorbed on the substrate, wherein the atomic layer deposition process uses:
the tantalum source gas including C10H30N5Ta, with a flow rate in a range of approximately 500 standard ml/min˜1500 standard ml/min;
the manganese source gas including (C5H5)2Mn, with a flow rate in a range of approximately 50 standard ml/min˜150 standard ml/min;
the nitrogen source gas including ammonia gas, with a flow rate in a range of approximately 500 standard ml/min˜2000 standard ml min;
a deposition temperature in a range of approximately 250° C.˜350° C.; and
a pressure in a reaction chamber in a range of approximately 2 Torr˜10 Torr; and
forming a metal interconnect on the first barrier layer, the metal interconnect being located within the opening.

US Pat. No. 10,483,159

MULTI-METAL FILL WITH SELF-ALIGN PATTERNING

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate with a metallization layer;
a dielectric layer formed over the metallization layer;
first conductive structures formed of a first conductive material and embedded in the dielectric layer; and
second conductive structures formed of a second conductive material and embedded in the dielectric layer, wherein the first conductive material and the second conductive material are different from one another, the first and second conductive structures have an alternating arrangement, and the first and second conductive structures have coplanar top surfaces with the dielectric layer.

US Pat. No. 10,483,154

FRONT-END-OF-LINE DEVICE STRUCTURE AND METHOD OF FORMING SUCH A FRONT-END-OF-LINE DEVICE STRUCTURE

GLOBALFOUNDRIES Inc., Gr...

14. A method, comprising:etching a first trench into a semiconductor substrate;
consecutively forming first and second insulating liners in said first trench;
forming a first insulating filling material on said first and second insulating liners in said first trench;
performing a recessing process after said first insulating filling material is formed, wherein an upper portion of said first insulating filling material is removed and an upper portion of said second insulating liner is exposed;
performing a pullback etching process, wherein said exposed upper portion of said second insulating liner material is removed and an upper surface portion of said first insulating liner is exposed; and
filling said first trench with a second insulating filling material, wherein said exposed upper surface portion of said first insulating liner is directly contacted by said second insulating filing material.

US Pat. No. 10,483,149

WAFER PROCESSING METHOD FOR DIVIDING A WAFER, INCLUDING A SHIELD TUNNEL FORMING STEP

DISCO CORPORATION, Tokyo...

1. A wafer processing method for dividing a wafer including a single-crystal silicon substrate having on a face side thereof a plurality of devices disposed in respective areas demarcated by a plurality of intersecting projected dicing lines, into individual device chips, the method comprising:a protective member placing step of placing a protective member on the face side of the wafer;
a shield tunnel forming step of, after performing the protective member placing step, applying a laser beam, which has a wavelength that is transmittable through single-crystal silicon, to areas of the wafer that correspond to the projected dicing lines from a reverse side of the wafer, thereby successively forming a plurality of shield tunnels in the wafer, each including a fine pore extending from the reverse side to the face side of the wafer and an amorphous region surrounding the fine pore; and
a dividing step of, after performing the shield tunnel forming step, dividing the wafer into individual device chips by etching the shield tunnels according to plasma etching,
wherein the pulsed laser beam used in the shield tunnel forming step has a wavelength of 1950 nm or higher.

US Pat. No. 10,483,146

ELECTROSTATIC CHUCK HEATER

NGK Insulators, Ltd., Na...

1. An electrostatic chuck heater comprising:an electrostatic chuck in which an electrostatic electrode is embedded in a ceramic sintered body;
a small-zone formation region provided inside the ceramic sintered body or a heater support body that is integrated with the ceramic sintered body, the small-zone formation region including a plurality of small zones in which small heater electrodes are wired;
a power source to which the plurality of small heater electrodes are connected in parallel; and
a small-zone control apparatus that performs control such that desired electric power is supplied to each of the small heater electrodes by using an output ratio to a suppliable output corresponding to each of the small heater electrodes,
wherein among the plurality of small heater electrodes, a small heater electrode that is wired in a small zone including a cool spot has a resistance that is set to a smaller value than that of the other small heater electrodes.

US Pat. No. 10,483,145

WAFER EDGE MEASUREMENT AND CONTROL

APPLIED MATERIALS, INC., ...

1. An apparatus for processing a substrate, comprising:a chamber body defining an inner volume;
a substrate positioning assembly disposed in the inner volume, wherein the substrate positioning assembly is capable of positioning and rotating the substrate at least within a horizontal plane;
a first capacitive sensor disposed in the inner volume, wherein the first capacitive sensor is positioned to detect a location of an edge of the substrate at a first edge location;
a second capacitive sensor disposed in the inner volume, wherein the second capacitive sensor is positioned to detect the location of the edge of the substrate at a second edge location;
a third capacitive sensor disposed in the inner volume at a position between the first and second capacitive sensors, wherein the third capacitive sensor is positioned to detect a vertical location of the substrate; and
a controller coupled to the first, second, and third capacitive sensors, wherein the controller is programmed to determine a first time period when a non-uniform portion on the edge of the substrate passes through a field of view of the first capacitive sensor and to determine a second time period when the non-uniform portion passes through a field of view of the second capacitive sensor.

US Pat. No. 10,483,144

METHOD FOR DETERMINING FRONT AND BACK OF SINGLE-CRYSTAL WAFER

SHIN-ETSU HANDOTAI CO., L...

1. A method for determining a front and a back of a single-crystal wafer comprising:using, as the single-crystal wafer, one having a crystal plane which is laterally asymmetrical to a reference direction connecting a center of a cut for orientation identification formed in an end face of the single-crystal wafer with a center of the single-crystal wafer;
noticing the laterally asymmetrical crystal plane, applying an X-ray to the single-crystal wafer, and detecting a diffracted X-ray to measure an angle formed between an orientation of the noticed crystal plane and the reference direction; and
determining whether a surface of the single-crystal wafer is a front surface or a back surface from a value of the measured angle.

US Pat. No. 10,483,143

END EFFECTOR AND SUBSTRATE CONVEYING ROBOT

KAWASAKI JUKOGYO KABUSHIK...

1. An end effector capable of holding two or more substrates, comprising:a base at least a part of which advances below a lowermost substrate or above an uppermost substrate of a plurality of substrates stored in substrate storage;
a substrate holder provided on the base so as to hold the two or more substrates including the lowermost substrate or the uppermost substrate, the substrate holder comprising
a substrate support provided on a distal end side of an end effector body including the base, the substrate support including a surface supporting a bottom surface edge portion of the substrate, and
a connector comprising a rotary spindle connecting the substrate support to the distal end side of the end effector body so that the substrate support pivots in response to an external force when the external force is applied to the substrate support; and
a servo motor for changing a protrusion amount of the substrate holder from a reference surface including a surface of the base opposed to the lowermost substrate or the uppermost substrate,
wherein the servo motor is configured for applying a drive force to a whole of the substrate holder, and
wherein a vertical pitch of the two or more substrates held by the substrate holder is changed by changing the protrusion amount of the substrate holder by the servo motor.

US Pat. No. 10,483,142

VACUUM ROBOT POSITIONING SYSTEM WITH REDUCED SENSITIVITY TO CHAMBER PRESSURE

Lam Research Corporation,...

1. An apparatus comprising:a support structure for mounting a vacuum robot arm to a horizontally elongate vacuum transfer module for a semiconductor processing tool, the support structure including:
a first set of one or more vacuum transfer module mount points collectively having a first centroid;
a second set of one or more vacuum transfer module mount points collectively having a second centroid; and
a set of one or more robot base mount points configured to connect the support structure with a base of the vacuum robot arm such that a rotational axis of a rotational joint in the base of the vacuum robot arm that connects the base with an arm segment of the vacuum robot arm is interposed between the first centroid and the second centroid, wherein:
a first distance between the first centroid and the second centroid when viewed along the rotational axis is at least 70% of a horizontal width of the horizontally elongate vacuum transfer module along the short axis of the horizontally elongate vacuum transfer module, and
a second distance between the first centroid and the rotational axis when viewed along the rotational axis is, when the support structure is connected with the base of the vacuum robot arm, at most 25% of the horizontal width of the vacuum transfer module along the short axis of the horizontally elongate vacuum transfer module.

US Pat. No. 10,483,139

SUBSTRATE PROCESSING APPARATUS, METHOD OF OPERATING THE SAME AND NON-TRANSITORY STORAGE MEDIUM

Tokyo Electron Limited, ...

1. A substrate processing apparatus comprising:a plurality of processing units each processing unit being configured to accommodate one substrate of a plurality of substrates therein, the plurality of substrates including a monitor substrate and a product substrate;
a substrate transfer mechanism that transfers substrates to the plurality of processing units; and
a control device,
wherein the control device controls an operation mode of each of the processing units, the operation mode including one of a normal mode or a monitoring mode, the monitoring mode being an operation mode for subjecting the monitor substrate to a first predetermined process based on a characterizing processing condition for the first predetermined process, the normal mode being an operation mode for subjecting the product substrate to a second predetermined process based on a characterizing processing condition for the second predetermined process,
wherein the control device is configured to compare the characterizing processing condition of the second predetermined process, related to the normal mode, with the characterizing processing condition of the first predetermined process, related to the monitoring mode,
wherein the control device is configured to judge, based on a result of the comparison, whether loading of the product substrate to be subjected to the second predetermined process in the processing unit set in the monitoring mode is allowed or prohibited,
wherein the control device is configured to judge that the loading of the product substrate to be subjected to the second predetermined process in the processing unit set in the monitoring mode is allowed, if the characterizing processing condition of the second predetermined process is different from the characterizing processing condition of the first predetermined process, and
wherein the control device is configured to control the substrate transfer mechanism to load the product substrate into one of a processing unit set in the normal mode or a processing unit set in the monitoring mode into which loading of the product substrate is allowed by the judgment.