US Pat. No. 10,461,829

MULTIPLE ACCESS METHOD IN A MASSIVE MIMO SYSTEM

TELEFONAKTIEBOLAGET LM ER...

1. A method performed by a Radio Network Node (RNN), wherein the RNN serves a first wireless device and a second wireless device in a wireless communications system, the method comprising:assigning a shared uplink pilot signal to the first wireless device and to the second wireless device;
transmitting, to the first wireless device, an indication of how possible second data intended for the second wireless device will be comprised in a transmission signal to be transmitted from the RNN to the first wireless device;
estimating a combined channel based on a received shared uplink pilot signal from the first wireless device and/or the second wireless device;
determining a beamforming vector for the estimated combined channel; and
transmitting, by using the beamforming vector, the transmission signal to the first wireless device, wherein
the transmission signal comprises first data and the possible second data and
the first data is decodable only by the first wireless device.

US Pat. No. 10,461,824

LINEAR PRECODING IN FULL-DIMENSIONAL MIMO SYSTEMS AND DYNAMIC VERTICAL SECTORIZATION

QUALCOMM Incorporated, S...

1. A method for wireless communication by a base station, comprising:generating a port precoding matrix which compresses a larger number of antenna elements to a smaller number of antenna ports;
transmitting user equipment (UE)-specific port reference signals to a UE using the port precoding matrix, wherein each of the UE-specific port reference signals corresponds to one of the antenna ports;
receiving feedback regarding channel state information (CSI) measured by the UE based on the UE-specific port reference signals, wherein the CSI comprises quantized measurements for at least one of the antenna ports corresponding to more than one of the antenna elements;
mapping multiple data layers to UE-specific antenna ports based on the feedback regarding CSI;
mapping each of the UE-specific antenna ports to physical antenna elements, wherein mapping each of the UE-specific antenna ports to physical antenna elements occurs after mapping the multiple data layers to the UE-specific antenna ports; and
transmitting data to the UE, based on the mapping of the multiple data layers and the mapping of antenna ports to the physical antenna elements.

US Pat. No. 10,461,817

ENHANCED MULTIPLE-INPUT MULTIPLE-OUTPUT BEAM REFINEMENT PROTOCOL TRANSMIT SECTOR SWEEP

Intel IP Corporation, Sa...

1. A device of an initiator for performing multiple-input multiple-output (MIMO) beamforming training the device comprising processing circuitry and storage, the processing circuitry coupled to the storage, and the processing circuitry configured to:establish a first communication link using a first antenna transmit chain of one or more transmit chains of the initiator, wherein the one or more antenna transmit chains further comprise a second antenna transmit chain;
initiate a MIMO beam refinement protocol (BRP) transmit sector sweep (TXSS) over the one or more antenna transmit chains;
map a single space-time stream over the one or more antenna transmit chains;
cause to send, to a responder device, an enhanced directional multi-gigabit (EDMG) frame using spatial expansion based on the mapping of the single space-time stream;
identify a feedback frame from the responder device; and
determine one or more antenna weight vectors (AWVs) to use in a MIMO phase of the MIMO beamforming training based on the feedback frame.

US Pat. No. 10,461,816

TRANSMISSION/RECEPTION APPARATUS AND METHOD FOR SUPPORTING MIMO TECHNOLOGY IN A FORWARD LINK OF A HIGH RATE PACKET DATA SYSTEM

Samsung Electronics Co., ...

1. A method of a transmitter for transmitting data in a communication system with a plurality of antennas, the method comprising the steps of:generating, by the transmitter, a first pilot signal and a second pilot signal; and
transmitting data, the first pilot signal, and the second pilot signal over a wireless network,
wherein the first pilot signal is transmitted at a first position in each slot for the data in a time domain and over each frequency that is used to transmit the data in a frequency domain, and the second pilot signal is transmitted at a second position, which is defined in the transmitter and a receiver, in the time domain and the frequency domain,
wherein each slot for the data comprises a first part of the slot for transmitting data and a second part of the slot for transmitting data,
wherein the first position is located adjacent to the first part and the second part in the time domain, and
wherein the defined second position comprises only one specific position within one slot, in the time domain.

US Pat. No. 10,461,812

NEAR-FIELD COMMUNICATION (NFC) TAGS OPTIMIZED FOR HIGH PERFORMANCE NFC AND WIRELESS POWER RECEPTION WITH SMALL ANTENNAS

NAN JING QIWEI TECHNOLOGY...

1. A device for concurrent near-field communication (NFC) and wireless power reception (WPR) using a magnetic field, comprising:a low-Q antenna resonant circuit configured to perform the NFC, and including
a first antenna for magnetic flux of the magnetic field to flow therethrough, to thereby receive a NFC signal for the NFC, and
a first antenna matching circuit that is connected to the first antenna and is so configured that a quality factor (Q-factor) of the low-Q antenna resonant circuit is no higher than 25; and
a high-Q antenna resonant circuit configured to perform the WPR, and including
a second antenna for the magnetic flux of the magnetic field to flow therethrough, to thereby receive wireless power for the WPR, and
a second antenna matching circuit that is connected to the second antenna and is so configured that the Q-factor of the high-Q antenna resonant circuit is no lower than 50, wherein
the low-Q and high-Q antenna resonant circuits are separate from each other,
the high-Q antenna resonant circuit operates to perform WPR, responsive to strength of the magnetic field being larger than a predetermined threshold, and
the high-Q antenna resonant circuit and the low-Q antenna resonant circuit operate to perform NFC, responsive to the strength of the magnetic field being no larger than the predetermined threshold.

US Pat. No. 10,461,801

USING HARMONICS FOR FULFILLING MULTIPLE JOBS SIMULTANEOUSLY

Raytheon Company, Waltha...

1. A device comprising:transmit circuitry;
a memory including job data indicating characteristics of jobs to be completed using the transmit circuitry, the characteristics indicating a frequency, power, and location of a transmission required to complete a job of the jobs;
at least one hardware processor coupled to the transmit circuitry and the memory, the at least one hardware processor configured to:
determine whether, based on the job characteristics and in completing a first job of the jobs with a signal at a fundamental frequency, a harmonic frequency of the fundamental frequency satisfies all characteristics of a second job of the jobs, the first job associated with a first device and the second job associated with a different, second device;
in response to a determination that the harmonic frequency of the fundamental frequency does not satisfy all characteristics of the second job, adjusting a beam width of the fundamental frequency of the signal so that the harmonic frequency of the signal satisfies the second job; and
cause the transmit circuitry to transmit the signal including the fundamental frequency and the harmonic frequency to fulfill the first and second jobs, respectively and simultaneously.

US Pat. No. 10,461,799

INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE, TRANSCEIVER, AND RELATED METHOD

TAIWAN SEMICONDUCTOR MANU...

1. A transceiver comprising:an antenna; and
a first package comprising:
an integrated circuit die comprising:
a die-side part of a transmitter path network, the die-side part of the transmitter path network including first and second portions, wherein the first portion of the die-side part of the transmitter path network comprises a power amplifier comprising a plurality of metal-oxide-semiconductor field effect transistors (MOSFETs);
a die-side part of a receiver path network;
a transmitter electrically connected to the first portion of the die-side part of the transmitter path network, wherein the transmitter is connected to a gate of a MOSFET of the plurality of MOSFETs; and
a receiver connected to the die-side part of the receiver path network;
the second portion of the die-side part of the transmitter path network including a selectable capacitance unit; and
a package-side part of the transmitter path network electrically connected to the die-side part of the transmitter path network and the antenna, the package-side part of the transmitter path network is directly connected to the first portion of the die-side part of the transmitter path network; and
a package-side part of the receiver path network electrically connected to the die-side part of the receiver path network and the antenna;
at least one of the package-side part of the transmitter path network or the package-side part of the receiver path network including an inductor.

US Pat. No. 10,461,797

NARROWBAND COMMUNICATION FOR DIFFERENT DEVICE CAPABILITIES IN UNLICENSED SPECTRUM

QUALCOMM Incorporated, S...

1. A method for wireless communication, comprising:transmitting an indication of a capability of a wireless device on resources of a first carrier in a first narrowband region of a radio frequency spectrum band;
receiving a configuration message on the resources of the first carrier;
identifying, based at least in part on the configuration message, a configuration of one or more additional carriers that are in a different narrowband regions of the radio frequency spectrum band, wherein the configuration of the one or more additional carriers is based at least in part on the capability of the wireless device;
receiving, on the resources of the first carrier, an assignment of resources on the one or more additional carriers in the different narrowband regions of the radio frequency spectrum band; and
communicating on the one or more additional carriers in the different narrowband regions of the radio frequency spectrum band according to the assignment.

US Pat. No. 10,461,789

LOW-POWER RECEIVING USING A JAMMING DETECTION MODE

APPLE INC., Cupertino, C...

1. A receiver system, comprising:a first receiver configured to receive and decode data signals from an antenna;
a second receiver configured to receive waveforms from the antenna, wherein the second receiver consumes relatively lower power than the first receiver when both of the receivers are in operation, wherein the second receiver is configured to receive the waveforms from the antenna that indicate whether jamming signals coexist with data to be received by the first receiver; and
receiver logic configured to control the first receiver based at least in part on an indication of whether jamming signals coexist with data to be received by the first receiver.

US Pat. No. 10,461,785

APPARATUS AND METHODS FOR FRONT-END SYSTEMS WITH REACTIVE LOOPBACK

Skyworks Solutions, Inc.,...

1. A front-end system comprising:a plurality of ports including an antenna port, a transmit port, and a receive port;
an antenna switch configured to selectively provide a transmit signal from the transmit port to the antenna port;
a low noise amplifier having an input electrically connected to the antenna port and an output electrically connected to the receive port; and
a loopback circuit including a reactive loopback impedance and a back switch electrically connected in series between the antenna switch and the receive port, the reactive loopback impedance including a plurality of capacitors in series with the back switch and operable to provide a portion of the transmit signal to the receive port when the back switch is activated.

US Pat. No. 10,461,775

COMPRESSION AWARE SSD

Samsung Electronics Co., ...

1. A compression system on a storage drive comprising:one or more compressibility inputs;
a compression predictor configured to predict the compressibility of data based on the one or more compressibility inputs;
a compressor configured to compress the data;
one or more compression inputs,
wherein at least one of the compression predictor or the compressor is configured to determine how to compress the data based on the one or more compression inputs.

US Pat. No. 10,461,760

ALKALI VAPOR CELL

1. An alkali vapor cell comprising a sealed chamber enclosing an alkali atomic gas therein and having at least one optically transparent window, the chamber and the transparent window defining an optical beam path through which a light beam can pass and interact with the alkali atomic gas in the chamber, wherein said alkali vapor cell comprises at least one localized condensation area of alkali atoms at a predetermined location in the sealed chamber, said at least one localized condensation area comprising a metal layer, wherein the metal of said metal layer is made of copper, tantalum, gold, platinum, nickel, or a combination thereof.

US Pat. No. 10,461,758

RING OSCILLATOR HAVING A FLAT FREQUENCY CHARACTERISTIC CURVE

Infineon Technologies AG,...

1. A ring oscillator comprising:a feedback chain including a plurality of inverters, and
for at least one of the inverters of the feedback chain: a further inverter, which is connected in parallel with a corresponding inverter of the feedback chain by a capacitor and which comprises an input that is directly coupled with an input of the corresponding inverter of the feedback chain.

US Pat. No. 10,461,748

ANTI-INTERFERENCE INTEGRATED CIRCUIT

AU OPTRONICS CORPORATION,...

1. An anti-interference integrated circuit (IC), adapted for avoiding an error in a frequency pulse caused by an interference of an adjacent IC, wherein the anti-interference IC outputs a first time signal, the adjacent IC outputs a second time signal, and the anti-interference IC comprises:a logic circuit, receiving the second time signal, and outputting a gate pulse according to a sequence of the second time signal;
an adder, connected to the logic circuit, and adding a first signal and the gate pulse;
a comparator, connected to the adder, and outputting the frequency pulse according to a signal adding result of the adder, wherein a period of the frequency pulse is the same as a period of the first time signal; and
a constant-on-time (COT) control circuit, outputting a first original time signal according to the period of the frequency pulse, wherein the first original time signal is a digital signal, and is a time signal originally generated when the anti-interference IC is not interfered with by the adjacent IC;
wherein the first signal is the first time signal, the adder adds the first time signal and the gate pulse to output an added signal, the comparator compares a reference signal with the added signal, and when the reference signal has a voltage value greater than or equal to that of the added signal, the comparator outputs the frequency pulse.

US Pat. No. 10,461,741

POWER SWITCH AND SEMICONDUCTOR DEVICE THEREOF

UPI SEMICONDUCTOR CORPORA...

1. A power switch, comprising:a first transistor cell comprising a first electrode;
a second transistor cell comprising a second electrode;
a body region disposed between the first transistor cell and the second transistor cell; and
a conductive layer electrically connected with the body region, the first electrode and the second electrode respectively,
wherein the body region has a base electrode voltage selectively maintained at a lower one of a first voltage and a second voltage, the first transistor cell is controlled by the second voltage and the second transistor cell is controlled by the first voltage.

US Pat. No. 10,461,740

CLAMP FOR A HYBRID SWITCH

Power Integrations, Inc.,...

1. A switch having a drain terminal, a source terminal and a control terminal, the switch comprising:a normally-on device including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the normally-on device is the drain terminal of the switch and the control terminal of the normally-on device is coupled to the source terminal of the switch;
a normally-off device including a first terminal, a second terminal, and a control terminal, wherein the control terminal of the normally-off device is coupled to the control terminal of the switch, the second terminal of the normally off-device is the source terminal of the switch, and the first terminal of the normally-off device is coupled to the second terminal of the normally-on device; and
a clamp circuit coupled across the normally-off device, wherein the clamp circuit comprises:
a first transistor coupled to the first terminal of the normally-off device;
a resistor coupled to the first transistor and to the second terminal of the normally-off device; and
a second transistor coupled between the first terminal and the second terminal of the normally-off device.

US Pat. No. 10,461,739

TRANSISTOR DEVICE

Infineon Technologies Aus...

1. A transistor device comprising:a unipolar transistor coupled between a first terminal and a second terminal; and
a bipolar transistor coupled in parallel to the unipolar transistor between the first terminal and the second terminal,
wherein the bipolar transistor has a threshold voltage higher than a threshold voltage of the unipolar transistor,
wherein a difference between the threshold voltage of the bipolar transistor and the threshold voltage of the unipolar transistor is at least 1 V, and
wherein the bipolar transistor is configured to carry a majority of a current flowing through the transistor device, from the first terminal to the second terminal, when the current exceeds a predetermined threshold; and
gate control circuitry configured to switch the bipolar transistor on only upon detection of an overcurrent event, wherein the gate control circuitry is configured to distinguish the overcurrent event between a short circuit event and a surge current event and to switch on the bipolar transistor only if the overcurrent event is a surge current event.

US Pat. No. 10,461,737

CONFIGURABLE CLAMP CIRCUIT

Infineon Technologies Aus...

1. A circuit comprising:a clamp driver circuit comprising a pull-up circuit coupled between a first power supply terminal and an output terminal of the clamp driver circuit, and a pull-down circuit coupled between a second power supply terminal and the output terminal of the clamp driver circuit;
a voltage regulator coupled between the first power supply terminal and the pull-up circuit; and
a logic circuit coupled to the pull-up circuit and the pull-down circuit, the logic circuit comprising a clamp driver configuration input and a clamp driver input, wherein the logic circuit is configured to:
operate the pull-up circuit and the pull-down circuit according to a first polarity when the clamp driver configuration input is in a first state, and
operate the pull-up circuit and the pull-down circuit according to a second polarity opposite the first polarity and deactivate the voltage regulator when the clamp driver configuration input is in a second state different from the first state.

US Pat. No. 10,461,736

SEMICONDUCTOR DEVICE

DENSO CORPORATION, Kariy...

1. A semiconductor device controlling a power switching device to turn on and off, the power switching device having a gate terminal and output terminals between which an output current is produced by a gate voltage applied to the gate terminal, the semiconductor device comprising:an output current detector configured to detect a current value correlated with the output current;
a voltage detector configured to detect a voltage, which is across the output terminals of the power switching device or is correlated with the voltage across the output terminals;
a clamp circuit configured to clamp the gate voltage at a predetermined value; and
a controller configured to control the clamp circuit to adjust the gate voltage based on the voltage detected by the voltage detector, wherein:
the controller controls the clamp circuit to set the gate voltage to be at a minimum voltage according to the detected voltage to cause the output current, which flows during having a short circuit in the power switching device, to be larger than a threshold current required for detecting the short circuit in the power switching device.

US Pat. No. 10,461,734

ACTIVE LOAD GENERATION CIRCUIT AND FILTER USING SAME

REALTEK SEMICONDUCTOR COR...

1. An active load generation circuit comprising:a transistor that provides an impedance and has a control terminal and an input terminal, wherein the control terminal receives a control voltage, the input terminal receives an input signal, and the impedance is related to the control voltage;
a voltage control circuit configured to generate an intermediate voltage according to a power supply voltage and a first reference voltage;
a voltage offset and tracking circuit coupled between the voltage control circuit and the transistor and configured to generate the control voltage according to the input signal and the intermediate voltage, wherein the control voltage varies with the input signal; and
a temperature sensing circuit coupled to the voltage control circuit and configured to sense an ambient temperature of the active load generation circuit and adjust the first reference voltage according to the ambient temperature.

US Pat. No. 10,461,724

RELAXATION OSCILLATOR WITH OVERSHOOT ERROR INTEGRATION

Analog Devices Global, H...

1. A method of using a relaxation oscillator to generate a clock signal, the method comprising:charging a first oscillation capacitor with a current from a first current source or sink during a first charging phase, until a first comparator determines that a first oscillation capacitor voltage meets a target voltage;
in response to the first oscillator capacitor voltage meeting the target voltage, interrupting charging of the first oscillation capacitor before a first error integration phase commences;
during the first error integration phase, adjusting the target voltage by integrating an overshoot error of a voltage on the first oscillation capacitor beyond a reference voltage, the reference voltage generated by passing a current from the first current source or sink, or a replicate thereof through an oscillation resistor to generate the reference voltage, after the charging of the first oscillation capacitor has been interrupted;
after the first error integration phase, interrupting integration of the overshoot error of the voltage on the first oscillation capacitor before a first reset phase commences; and
during the first reset phase, discharging the first oscillation capacitor.

US Pat. No. 10,461,723

FULL RANGE REALIGNMENT RING OSCILLATOR

Taiwan Semiconductor Manu...

1. A realignment ring-cell circuit, comprising:a single-to-differential unit having an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output;
an OR gate, wherein the first output for outputting is a first input to the OR gate;
an AND gate, wherein the second output for outputting is a first input to the AND gate;
a first P-type metal-oxide-semiconductor transistor, wherein a gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate; and
a first N-type metal-oxide-semiconductor transistor, wherein a gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate, wherein a drain of the P-type metal-oxide-semiconductor transistor and a drain of the N-type metal-oxide-semiconductor transistor are electrically connected to each other and are further electrically connected to a second input of the OR gate and a second input of the AND gate.

US Pat. No. 10,461,721

SEMICONDUCTOR APPARATUS, DEGRADATION VALUE DETERMINATION SYSTEM AND PROCESSING SYSTEM

RENESAS ELECTRONICS CORPO...

1. A semiconductor apparatus comprising:an operation oscillator;
a reference oscillator;
a first operation switch connected in series with the operation oscillator between a power supply potential and a ground potential;
a first reference switch connected in series with the reference oscillator between the power supply potential and the ground potential;
a second reference switch connected in parallel with the reference oscillator between the power supply potential and the ground potential;
an operation counter configured to count a number of first output pulses from the operation oscillator in a predetermined measurement period;
a reference counter configured to count a number of second output pulses from the reference oscillator in the predetermined measurement period;
a first gating component inputs the number of first output pulses; and
a second gating component inputs the number of second output pulses,
wherein the predetermined measurement period is set as a period during which the first gating component and the second gating component are in a through state.

US Pat. No. 10,461,718

ACOUSTIC WAVE RESONATOR, FILTER, AND MULTIPLEXER

TAIYO YUDEN CO., LTD., T...

1. An acoustic wave resonator comprising:a piezoelectric substrate; and
an IDT that is located on the piezoelectric substrate and includes first regions and second regions alternately arranged in an extension direction of electrode fingers, which excite an acoustic wave, in an overlap region in which the electrode fingers overlap, at least one electrode finger of the electrode fingers in the second regions having a different width from the at least one electrode finger in the first regions, a width of an outer second region of the second regions in the extension direction differing from a width of an inner second region of the second regions,
wherein a width of an outermost first region of the first regions in the overlap region in the extension direction is less than a width of an inner first region of the first regions in the extension direction.

US Pat. No. 10,461,712

AUTOMATIC VOLUME LEVELING

AMAZON TECHNOLOGIES, INC....

1. A method of automatic volume leveling, the method comprising:receiving, by an audio device, an audio signal;
receiving, by the audio device, indicator data indicating that the audio signal is of a first type;
determining a volume index value of the audio device, wherein the volume index value is a user-selected volume setting of the audio device;
determining a first gain of the audio signal, wherein the first gain is determined by using the volume index value to lookup the first gain in a volume curve table for signals of the first type;
determining an estimated root mean square (RMS) value of a first portion of the audio signal using a formula: x2rms(n)=(1?k)·x2rms (n?1)+k·[x(n)]2 where x2rms(n?1) represents a previous estimated RMS value for a previous portion of the audio signal sampled prior to the first portion, x(n) represents the first portion of the audio signal, and k=1?exp(?2.2/(fs*t/1000)), where t is a time constant in milliseconds, and fs is a sampling rate of the audio signal;
determining a second gain of the first portion of the audio signal, wherein the second gain is determined by using the estimated RMS value of the first portion to lookup the second gain on a static level curve of input level versus gain;
generating a modified first portion of the audio signal by multiplying the first portion of the audio signal by the second gain;
equalizing the modified first portion of the audio signal by reducing an audio level for a first frequency range of the modified first portion of the audio signal to reduce an output level of a loudspeaker at the first frequency range; and
outputting the modified first portion of the audio signal to the loudspeaker.

US Pat. No. 10,461,684

DEVICE AND METHOD OF A ROTATABLE PHOTOVOLTAIC PANEL MOUNT

Kim Rubin, Menlo Park, C...

1. A device to rotate a photovoltaic (PV) panel comprising:a fixed frame, configured to be permanently mounted on a support structure, comprising a spring mount;
a moving frame, configured to receive the photovoltaic (PV) panel, configured to rotate around a hinge axis, comprising a first rotational position and a second rotational position;
a hinge comprising the hinge axis, operatively connected between the fixed frame and the moving frame;
a spring, operatively connected between the moving frame and the spring mount;
a rotational damper operatively connected between the fixed frame and the moving frame;
a release latch operatively connected between the fixed frame and the moving frame;
a release handle operatively connected to the release latch;
wherein the moving frame is configured to rotate around the hinge axis from the first rotational position to the second rotational position;
wherein the spring provides a rotational force on the moving frame from the first rotational position to the second rotational position;
wherein the release latch holds the moving frame in the first rotational position until released by a first motion of the release handle without tools;
wherein the fixed frame circumferentially defines a roof access region;
wherein the moving frame, when the PV panel is attached to the moving frame, blocks access by a person to at least a first portion of the roof access region;
wherein the moving frame, when in the second position, does not block access by the person to the first portion of the roof access region; and
wherein the rotational damper limits a rotational speed of the moving frame, as the moving frame moves from the first rotational position to the second rotational position, to a predetermined maximum rotational speed.

US Pat. No. 10,461,680

METHOD FOR OPERATING A UNIVERSAL MOTOR

Robert Bosch GmbH, Stutt...

1. A method for operating a universal motor, the method comprising:measuring a first physical operating variable corresponding to a rotational speed of an armature in the universal motor;
measuring a second physical operating variable corresponding to one of an amperage, armature voltage, and armature field voltage, in the universal motor;
ascertaining with a control device a synthetic variable corresponding to a mathematical combination of the first physical operating variable and the second physical operating variable; and
operating the universal motor with the control device to influence a firing angle to adjust the second physical operating variable to maintain the synthetic variable at or below a predetermined level while the rotational speed of the armature in the universal motor changes during at least one of a braking and a start-up operation to reduce or eliminate sparking from a plurality of brushes in the universal motor.

US Pat. No. 10,461,675

CONTROL DEVICE, OPTICAL APPARATUS, CONTROL METHOD, AND STORAGE MEDIUM

Canon Kabushiki Kaisha, ...

1. A control device comprising:at least one processor which functions as:
a generation unit configured to generate a detection signal for a rotation position of a rotation portion of a stepping motor;
a rotation speed detection unit configured to detect a rotation speed of the rotation portion;
an advance angle detection unit configured to detect an advance angle based on the detection signal and a control waveform;
a storage unit configured to store information indicating a plurality of loci each indicating a relationship between the advance angle and the rotation speed at each driving voltage;
a target advance angle calculation unit configured to calculate a target advance angle depending on a target rotation speed of the rotation portion, based on the information stored in the storage unit;
an advance angle control unit configured to control the advance angle to be the target advance angle;
a voltage control unit configured to control the driving voltage of the stepping motor, based on the information stored in the storage unit; and
a switching unit configured to switch between a first control state and a second control state,
wherein the target advance angle calculation unit sets a target rotation speed by controlling the advance angle along one locus among the plurality of loci, in the first control state,
wherein the voltage control unit sets the target rotation speed by controlling the voltage in a state where the advance angle is fixed, in the second control state, and
wherein the switching unit switches between the first control state and the second control state, according to the locus, the target advance angle, and the driving voltage.

US Pat. No. 10,461,669

WIND POWER GENERATION DEVICE

TOYODA IRON WORKS CO., LT...

1. A wind power generation system including a power generation unit having an elastically deformable base material in a shape of a longitudinal flat plate and a piezoelectric element disposed on the base material, in which the power generation unit is held at its both longitudinal ends and is placed at a position where wind blows, and which generates electricity as the power generation unit is vibrated so that an intermediate portion of the power generation unit in a longitudinal direction reciprocates in a thickness direction of the power generation unit and the piezoelectric element is repeatedly bent and deformed by the vibration,a piezoelectric film made of resin being used as the piezoelectric element, and the piezoelectric element being stacked on the base material,
at least one of the longitudinal ends of the power generation unit being coupled to a movable member that is movable in the longitudinal direction of the power generation unit,
the wind power generation system being configured to include a tension adjusting device that, when a wind speed is increased, moves the movable member to increase a tensile force that pulls the power generation unit in the longitudinal direction, and
the tension adjusting device being a lift generating member that is formed integrally with the movable member so as to be extended and to have wing shape to both sides of the movable member and that moves the movable member based on lift generated according to the wind speed.

US Pat. No. 10,461,667

VIBRATION ACTUATOR AND ELECTRONIC APPARATUS USING VIBRATION ACTUATOR

Canon Kabushiki kaisha, ...

1. A vibration actuator comprising:a vibration body that has an electro-mechanical energy conversion element;
a driven body that contacts with said vibration body in a first direction and that relatively moves with respect to said vibration body in a second direction that intersects perpendicularly with the first direction;
a holding member that holds said vibration body; and
a support member that supports said holding member,
wherein one of said holding member and said support member has two projections projected in the first direction, and the other has two holes into which the two projections are respectively fitted to form a first fitting part and a second fitting part, and
wherein the projection contacts with the hole at least one part in the second direction and in a third direction that intersects perpendicularly with both the first and second directions in the first fitting part, the projection contacts with the hole at least one part in the third direction in the second fitting part, and a contact range of the projection and the hole in the third direction in the first fitting part differs from that in the second fitting part.

US Pat. No. 10,461,666

ENERGY HARVESTER FOR ELECTROSTATIC ENERGY

SAMSUNG ELECTRONICS CO., ...

1. An energy harvester comprising:a lower electrode;
a ferroelectric material layer which is disposed on the lower electrode and formed of a negatively poled ferroelectric material or a positively poled ferroelectric material, the ferroelectric material layer having a first electric susceptibility;
a friction-charged body which is adapted to be repeatedly contacted with and separated from the ferroelectric material layer and has a second electric susceptibility different from the first electric susceptibility; and
an upper electrode provided on the friction-charged body,
wherein the ferroelectric material layer is formed of the negatively poled ferroelectric material and has a negative charging property in relation to the friction-charged body, or
wherein the ferroelectric material layer is formed of the positively poled ferroelectric material and has a positive charging property in relation to the friction-charged body.

US Pat. No. 10,461,658

CONTROL DEVICE OF A SWITCHING POWER SUPPLY

STMICROELECTRONICS S.R.L....

1. A control device for controlling a switching converter that includes a switch and a sense resistor coupled to the switch, said control device comprising:a zero crossing detector configured to:
receive from the sense resistor of the switching converter an input signal indicative of a current though the sense resistor of the switching converter,
detect a first zero crossing of the current though the sense resistor of the switching converter by detecting a zero crossing of said input signal, the first zero crossing occurring after the switch is turned off and while the switch is off and in a same switching cycle as the turn off of the switch,
detect a second zero crossing of the current though the sense resistor of the switching converter, the second zero crossing immediately following the first zero crossing and occurring in an opposite direction with respect to the first zero crossing, the second zero crossing occurring in the same switching cycle of the switch as the first zero crossing, and
output a detection signal in response to detecting said second zero crossing; and
a synchronizer configured to start an on time period of the switch in response to the detection signal indicating that the zero crossing detector has detected said second zero crossing of said input signal.

US Pat. No. 10,461,652

FLYBACK POWER CONVERTER AND SECONDARY SIDE CONTROL CIRCUIT THEREOF

RICHTEK TECHNOLOGY CORPOR...

1. A flyback power converter, which is configured to operably convert an input voltage to an output voltage at an output terminal of the flyback power converter, the flyback power converter comprising:a transformer, including a primary winding coupled to the input voltage and a secondary winding coupled to the output voltage;
a power switch coupled to the primary winding, wherein the power switch is configured to be turned ON or OFF according to an operation signal, to control the primary winding so that the input voltage is converted to the output voltage;
a switch control unit coupled to the power switch, wherein the switch control unit is configured to operably generate the operation signal according to a feedback signal related to the output voltage;
a synchronous rectifier switch, which is coupled in serial to the secondary winding, wherein the synchronous rectifier switch and the secondary winding are coupled between the output terminal and a ground voltage level, and the synchronous rectifier switch and the secondary winding are coupled to each other through a secondary phase node, wherein the synchronous rectifier switch is configured to be turned ON or OFF according to a synchronous rectifier switch signal, so as to provide a synchronous rectification function; and
a secondary side control circuit, which is coupled to the synchronous rectifier switch and the secondary winding, the secondary side control circuit including:
a switch signal generation circuit, which is configured to operably generate the synchronous rectifier switch signal selectively according to a first power or a second power, to control the synchronous rectifier switch, wherein the first power is related to the output voltage and the second power is not the first power; and
a first power conversion circuit, which is configured to operably convert a secondary phase signal, to generate the second power, wherein the secondary phase signal is a voltage signal on the secondary phase node;
wherein the switch signal generation circuit includes:
a power selection circuit, which is configured to operably compare a level of the first power with a first reference threshold, to determine whether to select the first power or the second power, and convert the selected one to a third power; and
a driver circuit, which is configured to operably generate the synchronous rectifier switch signal by adopting the third power as a power source of the driver circuit;
wherein, when the level of the first power is greater than the first reference threshold, the power selection circuit selects the first power and converts the first power to the third power;
wherein, when the level of the first power is smaller than the first reference threshold, the power selection circuit, during at least a period, selects the second power and converts the second power to the third power.

US Pat. No. 10,461,650

CONTROL DEVICE FOR DC-DC CONVERTER

DENSO CORPORATION, Kariy...

1. A control device applied to a DC-DC converter including a transformer including input winding and output winding magnetically coupled together via a core and drive switches connected to the input winding, the control device operating the drive switches to control an output voltage output via the output winding to a target voltage, the control device comprising:a voltage acquiring unit acquiring the output voltage; and
a frequency setting unit setting a switching frequency for the drive switches based on the output voltage acquired by the voltage acquiring unit, wherein
the frequency setting unit sets, for the switching frequency, a value increasing with a value of the output voltage, and sets the switching frequency such that an increase in the value of the output voltage increases a frequency increase rate corresponding to an amount of increase in the switching frequency per unit amount of increase in the output voltage.

US Pat. No. 10,461,643

COMPOSITE EMBEDDED VOLTAGE REGULATOR (CEVR)

nanoHenry, Inc., San Die...

1. A composite embedded voltage regulator (CEVR) comprising:a system-on-chip (SoC) comprising:
a single substrate having a maintenance power interface;
a functional unit formed on the substrate, having an input supply to accept power;
an embedded voltage regulator (EVR) formed on the substrate, having an input supply connected to the maintenance power interface to accept a voltage, and having an output supply connected to the functional unit input supply to provide a regulated voltage;
a bulk current interface connected to the functional unit input supply;
a bulk current source having a control input to accept a current control signal responsive to the functional unit current demand, and an output supply connected to the SoC bulk current interface to only supply current to the functional unit input supply when enabled in response to the current control signal;
wherein the functional unit, in a first period of time, creates a dynamic increase demand for a first current;
in an initial portion of the first period of time, the EVR supplying the first current; and,
in a subsequent portion of the first period of time:
the EVR supplying a second current less than the first current;
the bulk current source supplying a third current equal to the first current minus the second current;
wherein the functional unit, in a second period of time following the first period of time, creates a dynamic decrease demand for a fourth current, less than the third current;
wherein the EVR supplies the fourth current in the second period of time; and,
wherein the bulk current source ceases to supply current in the second period of time.

US Pat. No. 10,461,642

BOOSTING A REGENERATIVE VOLTAGE AND SELECTING A BOOST CONVERTER BASED ON EFFICIENCY

YAZAKI CORPORATION, Toky...

1. A voltage conversion device, comprising:a first converter that boosts a direct current input voltage that is equal to or higher than a predetermined reference voltage to a direct current first voltage;
a second converter that boosts the direct current input voltage that is lower than the reference voltage to a direct current second voltage that is lower than the direct current first voltage;
a controller that switches between the first converter and the second converter; and
a power storage unit that includes a plurality of battery cells, the power storage unit storing therein an electric power output from the first converter or the second converter, wherein
the first converter boosts the direct current input voltage that is equal to or higher than the reference voltage to the direct current first voltage more efficiently than the second converter boosting the direct current input voltage that is equal to or higher than the reference voltage to the direct current first voltage,
the second converter boosts the direct current input voltage that is lower than the reference voltage to the direct current second voltage more efficiently than the first converter boosting the direct current input voltage that is lower than the reference voltage to the direct current second voltage,
the controller turns on the first converter and turns off the second converter, causing the first converter to boost the direct current input voltage when the direct current input voltage is equal to or higher than the reference voltage, thereby increasing a ratio of an electric power output than when the second converter boosts the direct current input voltage,
the controller turns off the first converter and turns on the second converter, causing the second converter to boost the direct current input voltage when the direct current input voltage is lower than the reference voltage, thereby increasing a ratio of an electric power output than when the first converter boosts the direct current input voltage, and
when a first connection mode is a state of forming a total battery cell group in which all the battery cells are connected in series, and a second connection mode is a state of forming a plurality of divided battery cell groups in which a part of the battery cells are connected in series, and each of the divided battery cell groups includes battery cells differing from one another, the controller charges the power storage unit in the first connection mode when the first converter boosts the direct current input voltage to the direct current first voltage, and charges the power storage unit in the second connection mode when the second converter boosts the direct current input voltage to the direct current second voltage.

US Pat. No. 10,461,638

DC-DC CONVERTER

Cirrus Logic, Inc., Aust...

9. A DC-DC converter configured to transition between a discontinuous conduction mode, DCM, and a continuous conduction mode, CCM, wherein the DC-DC converter is configured to power a signal processing system within an integrated circuit, the DC-DC converter comprising a controller comprising:an input configured to receive input data for input into the signal processing system;
a determination block configured to determine an amplitude of the input data; and
a transitioning block configured to cause the DC-DC converter to transition between the DCM and the CCM based on the amplitude of the input data.

US Pat. No. 10,461,637

DC-DC CONVERTER

OMRON Corporation, Kyoto...

1. A DC-DC converter that boosts a DC input voltage to obtain a DC output voltage, the DC-DC converter comprising:a switching circuit of which both terminals are connected to an output unit that outputs the DC output voltage and in which four switching elements are connected in series in an order of a first switching element, a second switching element, a third switching element, and a fourth switching element;
a flying capacitor that is connected between a connection portion between the first switching element and the second switching element and a connection portion between the third switching element and the fourth switching element;
a reactor that is connected between a connection portion between the second switching element and the third switching element and a positive electrode of an input unit to which the DC input voltage is input; and
a control circuit that determines a period of a first mode according to a predetermined timing and current peak value, and turns on or turns off each switching element in the switching circuit at the predetermined timing,
wherein the control circuit turns on or turns off each of the switching elements based on the period of the first mode so that a maximum value in a reactor current flowing through the reactor becomes equal to or smaller than a predetermined value.

US Pat. No. 10,461,626

ACTIVE CLAMP CIRCUIT

Silanna Asia Pte Ltd, Si...

1. An active clamp circuit comprising:an active clamp switch having a drain node and a source node;
an active clamp capacitor coupled in a series combination with the active clamp switch;
a delay circuit; and
an active clamp controller circuit coupled to the active clamp switch and to the delay circuit, the active clamp controller circuit being configured to i) receive an active clamp switch voltage based on a voltage developed across the drain node and the source node of the active clamp switch, ii) enable the active clamp switch based on a voltage amplitude of the active clamp switch voltage, and iii) disable the active clamp switch based on a delay signal generated by the delay circuit;
wherein the delay circuit comprises:
a resistor divider circuit to receive a bias voltage and a voltage from the source node of the active clamp switch to generate a delay threshold voltage;
a resistor-capacitor (RC) circuit to receive an active clamp switch control signal and the voltage from the source node of the active clamp switch to generate a ramp signal in response to the active clamp switch control signal, the active clamp switch control signal being configured to enable and disable the active clamp switch; and
a first voltage comparison circuit configured to i) receive the delay threshold voltage, ii) receive the ramp signal, iii) compare the ramp signal to the delay threshold voltage, and iv) disable the active clamp switch based on a comparison of the ramp signal and the delay threshold voltage.

US Pat. No. 10,461,624

POWER SWITCH CONTROL CIRCUIT AND OPEN DETECTION METHOD THEREOF

RICHTEK TECHNOLOGY CORPOR...

1. A power switch control circuit, configured to operably generate an operation signal at an operation signal output pin therein according to an input signal, so as to control a power switch, the power switch control circuit comprising:a current injection circuit, which is connected to the operation signal output pin, and is configured to operably provide a predetermined current to the operation signal output pin according to an enable signal;
an open detection circuit, which is coupled to the current injection circuit, and is configured to operably determine whether a connection between the operation signal output pin and the power switch is open according to a level of the operation signal output pin at a detection time point or during a detection time period, or a level variation of the operation signal output pin during a detection time period, and to generate an open detection signal accordingly; and
an inrush current protection circuit, which is coupled to the operation signal output pin, and is configured to operably clamp a level of the operation signal output pin when the predetermined current is provided to the operation signal output pin, such that the level does not exceed an upper limit;
wherein the input signal is transmitted to the operation signal output pin through a driver circuit which includes a half-bridge circuit, wherein the half-bridge circuit includes:
an upper switch and a lower switch connected at a common node;
an upper buffer, which is configured to operably control the upper switch according to the input signal; and
a lower buffer, which is configured to operably control the lower switch according to the input signal, wherein the upper switch and the lower switch are transistors with opposite conductive types, or are transistors with a same conductive type wherein one and only one of the upper buffer and the lower buffer is an inverter buffer;
wherein the inrush current protection circuit includes:
the lower switch; and
a switch, which is electrically connected between a gate and a current inflow terminal of the lower switch, and is controlled by the enable signal;
wherein when the enable signal is at an enable state, the lower switch forms a diode clamper circuit.

US Pat. No. 10,461,622

POWER GENERATOR WITH DC MOTOR AND AC GENERATOR COUPLED WITH SPROCKETS

1. A power generator comprising:a battery;
a motor powered by the battery and comprising a first rotating shaft, a first sprocket coupled to a first end of the first rotating shaft, a first gear coupled to a second end of the first rotating shaft, and a first bearing, wherein the second end of the first rotating shaft is rotatably disposed within the first bearing;
a first fan coupled to the first rotating shaft in between the motor and the first sprocket and configured to cool the motor;
an electrical generator comprising a second rotating shaft rotatably disposed within a second bearing and a third bearing, and a second sprocket coupled to the second rotating shaft, wherein the first sprocket and the second sprocket interlock such that the first rotating shaft rotates the second rotating shaft;
a second fan coupled to the second rotating shaft in between the second sprocket and the third bearing and configured to cool the electrical generator;
a kinetic mass secured to a third rotating shaft, wherein the third rotating shaft is rotatably disposed within a fourth bearing and a fifth bearing, the third rotating shaft comprising a second gear interlocked with the first gear such that a rotation of the kinetic mass rotates the third rotating shaft, which in turn aids with the rotation of the first rotating shaft;
a voltage regulator electrically connected in between the electrical generator and the battery; and
a power inverter electrically connected to the battery.

US Pat. No. 10,461,621

MICRO SCALE ELECTRO HYRDODYNAMIC (EHD) MODULAR CARTRIDGE PUMP

United States of America ...

1. An electro hydrodynamic pump apparatus, the apparatus comprising:a cartridge body member including an interior cavity portion and openings on either end of the body member;
a first electrode member disposed within the interior cavity portion of the cartridge body member, the first electrode member comprising a conductive bar member with a plurality of spaced apart elements extending therefrom;
a second electrode member disposed within the interior cavity portion of the cartridge body member, the second electrode member comprising a conductive bar with a plurality of spaced apart elements extending therefrom; and
wherein the elements of the first electrode member are configure to be interspersed with the elements of the second electrode member when the first electrode member and the second electrode member are disposed within the interior cavity portion of the cartridge body member; a first element of the first electrode member is spaced apart from a first element of the second electrode member by a first distance and the first element of the second electrode member is spaced apart from a second element of the first electrode member by a second distance; andsaid device further comprisinga spacer member disposed between an element of the second electrode member and an element of the first electrode member; and
a fluid flow channel, the fluid flow channel extending from an opening on one end of the body member through an opening on an other end of the cartridge body member, the fluid flow channel being defined by corresponding openings in the spaced apart elements of the first electrode member, the spaced apart elements of the second electrode member and the spacer members.

US Pat. No. 10,461,618

PMDC MOTOR HAVING A STRUCTURE FOR PRODUCING LOW NOISE

Johnson Electric Internat...

1. A permanent magnet direct current motor comprising:stator comprising: a housing, a stator magnet disposed in an interior of the housing, and an end cap assembly,
a rotor comprising: a shaft, a rotor core mounted on the shaft and disposed within the stator magnet, rotor windings wound around the rotor core, a commutator fixed on the shaft, a plurality of commutator segments disposed on an outer surface of the commutator,
wherein the end cap assembly comprises: a plastic end cap fitted to one end of the housing, a cover disposed on an outer side of the end cap, and brushes mounted to the end cap, and
a ratio of an outer diameter of the rotor core to the outer diameter of the housing is from 0.60 to 0.659, inclusive,
an outer diameter of the rotor core is 15.9 mm, the stator magnet has a radial thickness of 3.2 mm, and the outer diameter of the housing is 24.6 mm.

US Pat. No. 10,461,607

SYSTEM FOR LIQUID COOLING FOR A PUMP MOTOR

Regal Beloit America, Inc...

1. A system for liquid cooling for a motor for a pump, said system comprising:a motor configured to be coupled to a pump to move a liquid from an inlet side of the pump associated with a first pressure to an outlet side of the pump associated with a second pressure that is greater than the first pressure, said motor comprising a motor housing that encloses internal components of said motor, said motor housing comprising an inner surface oriented toward the internal components of said motor and an outer surface that defines an exterior of said motor;
a motor controller coupled to said motor within said motor housing and configured to control operation of said motor; and
a heat transfer tube positioned internally within said motor housing adjacent to at least a portion of the internal components of said motor and enclosing said motor controller, wherein said heat transfer tube comprises at least one channel extending from the inner surface to the outer surface of said housing, wherein said channel is configured to couple to a first port of the pump and receive at least a portion of the liquid from the outlet side of the pump via the first port and transfer heat away from said motor and said motor controller using the liquid.

US Pat. No. 10,461,578

OPTIMIZING THE DISTRIBUTION OF ELECTRICAL ENERGY

Siemens Aktiengesellschaf...

1. A method for optimizing the distribution of electrical energy in an electrical power grid comprising autonomous grid regions, comprising the following method steps:receiving input data by at least two dispatcher entities, wherein the input data represent energy intervals requested by the autonomous grid regions, and wherein the system does not include an individual central management node including a calculating device for calculating a solution of the distribution of electrical energy among all the autonomous grid regions based on the input data;
calculating at least one solution of the distribution of electrical energy among all the autonomous grid regions based on the input data, wherein calculating is performed by each of the at least two dispatcher entities;
selecting one of the calculated solutions for the distribution of electrical energy in the power grid;
implementing, by each of the at least two dispatcher entities, the selected calculated solution and distributing electrical energy among all the autonomous grid regions in the power grid based upon the selected calculated solution.

US Pat. No. 10,461,577

INVERTER PARALLELING CONTROL SYSTEM AND METHOD

SCHNEIDER ELECTRIC IT COR...

1. An Uninterruptible Power Supply (UPS) system comprising:an input configured to be coupled to an AC source and to receive input AC power from the AC source;
an output configured to provide output AC power to a load;
a converter coupled to the input and configured to convert the input power into DC power;
an inverter having an inverter output coupled to the output of the UPS, the inverter configured to convert the DC power into the output AC power and provide the output AC power to the output; and
a controller configured to operate the inverter to introduce a voltage droop to the output AC power, wherein the controller includes an active power droop controller coupled to the inverter output, the active power droop controller including:
a first moving average filter configured to sample instantaneous active power of the inverter to obtain instantaneous active power samples and calculate a first DC component of the instantaneous active power samples; and
a first Min-Max filter configured to receive the first DC component of the instantaneous active power samples from the first moving average filter and output a second DC component of the instantaneous active power samples having a convergence time less than a convergence time of the first DC component,
wherein the active power droop controller is configured to calculate the voltage droop based on the second DC component.

US Pat. No. 10,461,576

UNINTERRUPTIBLE POWER SUPPLY APPARATUS

TOSHIBA MITSUBISHI-ELECTR...

1. An uninterruptible power supply apparatus comprising:a converter configured to convert AC power supplied from a commercial AC power source into DC power;
an inverter configured to convert DC power into AC power and supply the AC power to a load; and
a control device configured to control the converter and the inverter,
during a normal time when the AC power is supplied from the commercial AC power source, the DC power generated in the converter being supplied to the inverter and stored in a power storage device, and during a power failure time when supply of the AC power from the commercial AC power source is stopped, the DC power in the power storage device being supplied to the inverter,the control device being configured to execute a mode selected from a first mode and a second mode, in the first mode, a first AC voltage with a sinusoidal waveform and with no waveform distortion being supplied to the load, and in the second mode, a second AC voltage with a waveform distortion within an allowable range for the load being supplied to the load,the control device being configured to:
when the first mode is selected during the normal time, control the converter to output a first DC voltage and control the inverter to output the first AC voltage with a sinusoidal waveform and with an amplitude smaller than one-half of the first DC voltage; and
when the second mode is selected during the normal time, control the converter to output a second DC voltage smaller than the first DC voltage and control the inverter to output the second AC voltage with a sinusoidal waveform and with an amplitude larger than one-half of the second DC voltage.

US Pat. No. 10,461,556

CHARGER, ELECTRONIC DEVICE, AND CHARGING METHOD

SHENZHEN ROYOLE TECHNOLOG...

1. A charger, comprising:a charge port, comprising a power pin, a first data pin, a second data pin, and a ground pin, the first data pin always being disconnected from the second data pin, the charge port being configured to connect to an electronic device;
a controller, connected to the first data pin and the second data pin;
a connection switching circuit, connected to the power pin, the first data pin, the second data pin, and the ground pin, and the controller;
wherein, the controller is configured to control the connection switching circuit to connect the first data pin to the power pin and connect the second data pin to the ground pin, when a handshake between the charger and the electronic device connected to the charge port is created successfully.

US Pat. No. 10,461,554

METHOD OF OPERATING ELECTROCHEMICAL CELLS COMPRISING ELECTRODEPOSITED FUEL

NANTENERGY, INC., Scotts...

1. A process for operating an electrochemical cell system, wherein the electrochemical cell system comprises:(i) at least two fuel electrodes for receiving electrodeposited metal fuel;
(ii) at least one oxidant electrode spaced apart from the fuel electrodes;
(iii) at least one charging electrode;
(iv) an ionically conductive medium communicating the electrodes of the electrochemical cell system for conducting ions to support electrochemical reactions at the fuel, oxidant, and charging electrodes, the ionically conductive medium comprising reducible metal fuel ions;
wherein the process comprises:
(i) assigning the fuel electrodes into units, the units comprising: a discharging unit and a charging unit;
(ii) operating said cell system in a discharge mode wherein the metal fuel is oxidized at each fuel electrode in the discharging unit and an oxidant is reduced at the at least one oxidant electrode to generate an electrical discharge current therebetween for application to a load;
(iii) operating said cell system in a charging mode wherein a reducible species of the fuel is reduced to electrodeposit the fuel on each fuel electrode in the charging unit and oxidize an oxidizable species of the oxidant at the charging electrode by application of an electrical charge current therebetween from a power source;
(iv) monitoring each of the fuel electrodes in the discharging unit during said discharge mode, wherein each fuel electrode in the discharging unit meeting a predetermined depletion criteria is assigned from the discharging unit to the charging unit, and wherein each fuel electrode not meeting the predetermined depletion criteria remains assigned to the discharging unit including for a subsequent discharge mode; and
(v) monitoring each of the fuel electrodes in the charging unit during said charging mode, wherein each fuel electrode in the charging unit meeting a predetermined loading criteria is assigned from the charging unit to the discharging unit, and wherein each fuel electrode not meeting the predetermined loading criteria remains assigned to the charging unit including for a subsequent charge mode.

US Pat. No. 10,461,542

POWER DISTRIBUTION NETWORK

GE AVIATION SYSTEMS LLC, ...

1. A power system comprising:a first power source and a second power source arranged in a series to define a power source series;
a first electrical load and a second electrical load arranged in series with to define a load series, the load series in series with the power source series; and
a set of bypass current paths, each independently associated with one of at least a subset of: the first power source, the second power source, the first electrical load, and the second electrical load, and wherein the set of bypass current paths are configured to be selectably enabled to allow current to bypass a pair of components comprising at least one of the first power source and the second power source, and at least one of the first electrical load and the second electrical load.

US Pat. No. 10,461,538

SYSTEM STABILIZATION CONTROL DEVICE AND POWER SYSTEM CONTROL SYSTEM

HITACHI, LTD., Tokyo (JP...

1. A system stabilization control device for controlling a control instrument installed within a power system based on measurement information from a plurality of measurement points within the power system, comprising:an equipment information database for storing information of system equipment that is interconnected with the power system;
a control priority determining unit for determining a control priority of the control instrument based on information of the system equipment;
a control target determining unit for determining a control target based on the measurement information from the plurality of measurement points and the control priority, wherein the control target determining unit determines the control target by using an electrical distance or impedance between the measurement points in which unstable oscillation was observed and the control instrument interconnected points;
a destabilization time calculating unit for calculating destabilization time of the power system from the measurement information from the plurality of measurement points; and
a control time determining unit for determining control time of the control instrument based on the destabilization time and the information of the system equipment, and
wherein the system stabilization control device controls the determined control instrument for the determined control time.

US Pat. No. 10,461,534

STARTING METHOD AND STOPPING METHOD FOR A STATIC SYNCHRONOUS SERIES COMPENSATOR

NR ELECTRIC CO., LTD, Na...

1. A starting method for a static synchronous series compensator (SSSC), the SSSC consisting essentially of a converter, a shunt transformer, a series transformer, and at least one bypass switch of the series transformer, wherein the shunt transformer is connected to an alternating-current line on one end and to the current converter on another end, wherein the shunt transformer comprises an incoming line switch connected to the alternating-current line, wherein the series transformer is connected to the current converter on one end and to a transmission line on another end, wherein the at least one bypass switch is connected to the series transformer and to the transmission, the starting method comprising the following steps:(a1) setting an initial status of starting the SSSC;
(a2) connecting the converter to the shunt transformer, closing an incoming line switch of the shunt transformer, and charging the converter, entering step (a3) after the charging ends;
(a3) disconnecting the converter from the shunt transformer, and connecting the converter to the series transformer, entering step (a4) after current or voltage stabilization;
(a4) deblocking the converter in a zero current control mode of the bypass switch;
(a5) controlling a current of the bypass switch of the series transformer to be gradually reduced below a current threshold, and opening the bypass switch of the series transformer; and
(a6) after the transmission line is stably operated, enabling the SSSC to enter a normal operation mode, thereby completing a starting process.

US Pat. No. 10,461,533

APPARATUS AND METHOD FOR AUTOMATED VALIDATION, ESTIMATION, AND EDITING CONFIGURATION

ENEL X NORTH AMERICA, INC...

1. An apparatus for configuring validation, estimation, and editing (VEE) rules for performing VEE on a plurality of interval based energy consumption streams, the apparatus comprising:a post VEE readings data stores, configured to provide a plurality of tagged energy consumption data sets that are each associated with a corresponding one of the plurality of interval based energy consumption streams, each of said plurality of tagged energy consumption data sets comprising:
first groups of contiguous interval values tagged as having been validated; and
second groups of contiguous interval values tagged as having been edited;
a rules processor, configured to read said post VEE readings data stores upon initiation of an event and, for said each of said plurality of tagged energy consumption data sets, configured to create a plurality of anomalies having a plurality of different durations using only said first groups of contiguous interval values, said first groups of contiguous interval values corresponding to correct data, and configured to generate a plurality of estimates for said plurality of anomalies by employing a plurality of estimation techniques for each of said plurality of different durations, and, for said each of said plurality of different durations, configured to select a corresponding one of said plurality of estimation techniques for subsequent employment when performing VEE of subsequent energy consumption data associated with said each of said plurality of different durations for said corresponding one of the plurality of interval based energy consumption streams; and
a process control element, coupled to said post VEE readings stores, wherein the process control element executes functions on the plurality of interval based energy consumption streams translated by said rules processor, and directs one or more of system elements to change state.

US Pat. No. 10,461,523

ELECTROMAGNETIC STREAMER SAFETY

PGS Geophysical AS, Oslo...

1. A system, comprising:a control circuit configured to be coupled to a constant-current power supply unit (PSU) that is operable to supply power to a plurality of loads that are in a series configuration;
wherein the control circuit is configured to:
detect an unexpected change in an output associated with the constant-current PSU; and
power down the constant-current PSU based on a magnitude and a duration of the unexpected change in output;
wherein the control circuit comprises a microcontroller configured to:
monitor a current output by the constant-current PSU via a current sensor coupled to an analog-to-digital controller;
monitor a voltage across a first and second rail of the constant-current PSU via respective first and second resistors; and
monitor, via an isolating circuit, a voltage between a given one of the first and second rails and ground.

US Pat. No. 10,461,522

PROTECTION DEVICE AND PROTECTION SYSTEM

MITSUBISHI ELECTRIC CORPO...

1. A protection device for a power converter provided between a DC line forming a DC power transmission system and an AC system, the protection device comprising:a current input unit configured to receive an input of an AC current value obtained between a transformer connected to the AC system and the power converter capable of converting AC power into DC power;
a current change rate input unit configured to receive an input of a change rate of a direct current detected by an air core coil provided between the DC line and the power converter, the DC line receiving DC power from the power converter;
a fault determination unit configured to determine whether a fault occurs or not in one of the power converter and the DC line, based on the AC current value received by the current input unit and the change rate received by the current change rate input unit; and
an output unit configured to output information for protecting the power converter based on a determination result of the fault determination unit.

US Pat. No. 10,461,521

DRIVING CIRCUIT, CONTROL DEVICE, AND PROTECTION METHOD FOR DRIVING CIRCUIT

DENSO TEN Limited, Kobe-...

1. A driving circuit comprising:a driving unit that supplies a driving current from a power source to a load to drive the load based on a control signal input from a controller;
a first temperature detecting unit that detects a temperature and outputs a signal of a level according to the detected temperature;
an overheat protecting unit that causes the driving unit to block supply of the driving current to the load when the level of the signal output from the first temperature detecting unit is not less than a temperature threshold;
a second temperature detecting unit that detects a temperature and outputs a signal of a level according to the detected temperature to the controller; and
a failure-for-overheat diagnosing unit that performs a failure diagnosis on the first temperature detecting unit, and when it is determined that the first temperature detecting unit breaks down, causes the driving unit to block supply of the driving current to the load and causes the second temperature detecting unit to output a signal of a level corresponding to a temperature out of a temperature range detectable by the second temperature detecting unit to the controller.

US Pat. No. 10,461,515

PROTECTOR AND WIRING STRUCTURE

YAZAKI CORPORATION, Toky...

1. A protector comprising:a main body having a support surface that supports a wiring material and a back surface on an opposite side from the support surface and having a first wall and a second wall erected with respect to the first wall from a first edge that is one edge of the first wall in a width direction, wherein
the main body has an insertion hole into which a band portion of a band member is inserted and a locking portion that locks a head portion, the band member having the band portion and the head portion into which the band portion is inserted,
the locking portion includes a pair of protrusions protruding from the back surface,
each of the pair of protrusions has a width direction wall extending in a direction intersecting an extending direction of the first wall and a locking wall protruding from the width direction wall toward the other one of the pair of protrusions,
the locking wall is formed at a second edge that is the other edge of the first wall in the width direction, and distal ends of the locking walls face each other,
an interval between the distal ends of the locking walls is an interval that allows passage of the band portion and regulates passage of the head portion,
the width direction walls store the head portion between the width direction walls, and
a groove extends along the distal ends of the locking walls, allows passage of the band portion, guides the band portion to between the distal ends of the locking walls, and is formed on an end surface of the first wall on a side of the second edge.

US Pat. No. 10,461,512

SYSTEMS AND METHODS FOR AERIAL TREATMENT OF OVERHEAD CABLING

GENERAL CABLE TECHNOLOGIE...

1. A multi-carriage aerial cable treatment system, comprising:a first carriage and a second carriage, wherein the first and second carriages are each independently translatable along an aerial cable under treatment, wherein the first carriage comprises:
a first housing having a first longitudinal axis;
a first forward traction wheel and a first rear traction wheel that are each coupled to the first housing and positioned along the first longitudinal axis, wherein at least one of the first forward traction wheel and the first rear traction wheel are drivable to propel the first housing along the aerial cable under treatment; and
a cable surface abrasion assembly positioned to contact the aerial cable under treatment; and
wherein the second carriage comprises:
a second housing having a second longitudinal axis;
a second forward traction wheel and a second rear traction wheel that are each coupled to the second housing and positioned along the second longitudinal axis, wherein at least one of the second forward traction wheel and the second rear traction wheel are drivable to propel the second housing along the aerial cable under treatment;
a coating storage tank;
a coating applicator assembly; and
a coating pump operative to pump a coating material from the coating storage tank to the coating applicator assembly.

US Pat. No. 10,461,504

VERTICALLY-COUPLED SURFACE-ETCHED GRATING DFB LASER

ElectroPhotonic-IC Inc., ...

1. A device comprising:a mesa formed by a semiconductor structure comprising an epitaxial layer stack comprising a plurality of semiconductor layers grown on a semiconductor substrate;
the plurality of semiconductor layers comprising a lower emitter layer, a lower separate confinement heterostructure, a multi-quantum well active gain region, an upper separate confinement heterostructure, and an upper emitter layer;
a surface-etched grating comprising a set of periodic trenches defined along a top surface of the mesa to form a vertically coupled waveguide Bragg grating supporting a fundamental optical mode,
a first electrical contact to the upper emitter layer provided on the top surface of the mesa each side of the surface-etched grating;
a second electrical contact to the lower emitter layer provided each side of the mesa;
wherein the upper and lower separate confinement heterostructures provide vertical optical confinement of the fundamental optical mode; and
at least one layer of the plurality of semiconductor layers underlying the multi-quantum well active gain region is laterally undercut to define sidewalls of the mesa having a lateral profile that provides lateral optical confinement of the fundamental optical mode and lateral confinement of current injection.

US Pat. No. 10,461,499

SYSTEMS AND METHODS FOR CALIBRATING, OPERATING, AND SETTING A LASER DIODE IN A WEAPON

Axon Enterprise, Inc., S...

1. A weapon that cooperates with a provided tester, the weapon comprising:a processing circuit; a laser diode that provides a light; a photo diode that detects the light; a resistor coupled in series with the photo diode; and
a memory having computer-executable instructions stored thereon that, in response to execution by the processing circuit, cause the weapon to:
provide a signal at a duty cycle to establish a power of the light provided by the laser diode, the light induces a first current through the photo diode, the first current is related to the power of the light the first current flows through the resistor thereby inducing a first voltage across the resistor, the first voltage is related to the power of the light:
provide the light to the tester, the tester measures a magnitude of the power of the light and sends a message to the weapon to report the magnitude of the power:
receive the message from the tester regarding the magnitude of the power as measured by the tester;
compare the magnitude of the power as measured by the tester to a predetermined range, the predetermine range associated with a geographic region where the laser diode will be used:
adjust the duty cycle responsive to the comparison;
repeat providing the light to the tester, receiving the message from the tester, comparing the magnitude, and adjusting the duty cycle until the magnitude of the power as measured by the tester is within the predetermined range; and
record a magnitude of the first voltage in the memory whereby the magnitude of the first voltage corresponds to the predetermined range.

US Pat. No. 10,461,498

COMMON CATHODE LASER DRIVING CIRCUIT

Google LLC, Mountain Vie...

1. A method comprising:delivering, by a laser driving circuit, a bias current to an anode of a gain-section diode disposed on a shared substrate of a tunable laser;
receiving, at the laser driving circuit, a burst mode signal indicative of a burst-on state or a burst-off state;
when the burst mode signal is indicative of the burst-off state, sinking, by the laser driving circuit, a sink current away from the bias current at the anode of the gain-section diode, the sink current less than the bias current delivered to the anode of the gain-section diode; and
when the burst mode signal is indicative of the burst-on state, modulating, by the laser driving circuit, the tunable laser by a capacitively coupled modulation stage of the laser driving circuit to the anode of the gain-section diode, resulting in an alternating current (AC) modulation current.

US Pat. No. 10,461,495

SUBSTRATE TECHNOLOGY FOR QUANTUM DOT LASERS INTEGRATED ON SILICON

Cisco Technology, Inc., ...

1. A method of creating an optically active element, comprising:bonding a III-V semiconductor material with a silicon substrate;
removing excess III-V semiconductor material bonded with the substrate to leave a III-V semiconductor material base layer of a predetermined thickness bonded with the substrate; and
after removing the excess III-V semiconductor material, epitaxially growing at least one layer on the III-V semiconductor material base layer, the at least one layer comprising a quantum dot layer.

US Pat. No. 10,461,494

LASER APPARATUS AND EXTREME ULTRAVIOLET LIGHT GENERATION SYSTEM

GIGAPHOTON INC., Tochigi...

1. A laser apparatus comprising:a master oscillator configured to output laser light;
a plurality of amplifiers each configured to include carbon dioxide as a laser medium and amplify the laser light;
a first optical path pipe configured to cover a laser optical path between the amplifiers;
a gas supply port configured to supply gas into the first optical path pipe, the gas having lower carbon dioxide concentration than carbon dioxide concentration of air;
a first carbon dioxide densitometer configured to measure carbon dioxide concentration in the first optical path pipe; and
an alarm device to which a measurement result of the first carbon dioxide densitometer is input, the alarm device being configured to issue an alarm when the carbon dioxide concentration measured by the first carbon dioxide densitometer exceeds a preset prescribed value of carbon dioxide concentration.

US Pat. No. 10,461,491

LASER RESONATOR AND LASER RESONATOR ARRAY

SAMSUNG ELECTRONICS CO., ...

1. A laser resonator comprising:a metal body; and
a ring-shaped gain medium layer having an inner radius and an outer radius, and at least partially embedded into the metal body,
wherein the ring-shaped gain medium layer is formed of a semiconductor material and configured to generate a laser light through optical absorption by coupling electromagnetic waves and plasmons on a boundary between the metal body and the ring-shaped gain medium layer,
wherein the laser resonator further comprises at least one absorption member provided in the ring-shaped gain medium layer,
wherein the ring-shaped gain medium layer comprises a base portion and at least one protruding portion protruding from an upper surface of the base portion and
wherein a laser light of a specific mode is selected or separated by adjusting at least one of a number and position of the at least one absorption member.

US Pat. No. 10,461,484

ELECTRICAL OUTLET AND REMOVABLE POWER MODULE

EATON INTELLIGENT POWER L...

1. An electrical outlet structured to be electrically connected with a 1 doctor and a neutral conductor of an AC power source, the electrical outlet comprising:a base;
an electrical apparatus situated on the base;
the electrical apparatus comprising a first connector, a second connector, a third connector, and a fourth connector;
the base having a receptacle formed therein, the first connector and the second connector being situated inside the receptacle, the receptacle being structured to receive therein the power module with the first electrical contact being electrically connected with the first connector and with the second electrical contact being electrically connected with the second connector; and
the third connector being electrically connectable with one of the line conductor and the neutral conductor, and the fourth connector being electrically connectable with the other of the line conductor and the neutral conductor;
the electrical apparatus also comprising a power module having a first electrical contact, a second electrical contact, and a power outlet electrically connected with the first and second electrical contacts, the power module being receivable in the receptacle with the first electrical contact being electrically connected with the first connector and with the second electrical contact being electrically connected with the second connector; and
the electrical apparatus further comprising a pair of springs situated on the base and additionally comprising a pair of electrical conductors that are electrically connected with the third and fourth connectors, the first and second connectors being situated on the pair of springs, the first and second connectors being movable on the pair of springs with respect to the base from a first position wherein the first and second connectors are interposed between and are electrically connected between the pair of electrical conductors and the first and second electrical contacts when the power module is fully received in the receptacle to a second position wherein the first and second connectors are biased by the pair of springs away from the pair of electrical conductors and are electrically disconnected therefrom after the power module has been removed from the receptacle.

US Pat. No. 10,461,483

STRUT END CONDITION, END BLOCK, AND CONNECTOR

ARCHITECTURAL BUSSTRUT CO...

1. A strut assembly, comprising:a strut;
an insulator having a distal end;
at least one conductor wire oriented within the insulator;
an end block oriented within an end of the strut, the end block nesting within the strut; and
an isolator having dividers, each divider having a divider base with a divider base proximal end,
wherein the divider base proximal end engages the distal end of the insulator and prevents the isolator from extending past a desired point on the insulator, and
wherein the isolator is oriented between the end block and the strut such that the end block fits within the interior of the isolator.

US Pat. No. 10,461,477

SHIELD CONNECTOR AND CONNECTOR ASSEMBLY INCLUDING THE SHIELD CONNECTOR

Molex, LLC, Lisle, IL (U...

1. A connector that is connected to a mating connector, the connector comprising:an outer housing; and
an inner housing module fit in the outer housing, wherein
the inner housing module includes:
a resin portion including an attachment portion and a base portion extending from the attachment portion;
upper surface shield plates and side surface shield plates that are provided on an outer side of the base portion, and are electrically connected to each other; and
a signal terminal provided on an inner side of the base portion, and
the upper surface shield plates, the side surface shield plates, the signal terminal, and the resin portion are integrally formed in a monolithic construction.

US Pat. No. 10,461,476

CONNECTOR

Tyco Electronics (Shangha...

1. A connector, comprising:a housing;
a connector body disposed in the housing;
a conductive terminal disposed in the connector body; and
a conductive shielding sleeve disposed in the housing such that at least a part of an outer end of the conductive shielding sleeve extends to an exterior of the housing when the conductive shielding sleeve is fully mounted in the housing, the outer end of the conductive shielding sleeve has an outwardly turning lip disposed outside the housing and spaced apart from the housing by a predetermined distance.

US Pat. No. 10,461,463

SEALING INSERT

1. A sealing system for a cable lead-through device into a housing, said cable lead-through device, having at least one U-shaped frame with at least two limbs and a first web connecting the two limbs at one end in each case, and at least one sealing insert configured to be inserted into or arranged in the frame, wherein the sealing insert(s) arranged in the frame is configured to be ultimately compressed by attaching a second web for strain relief and sealing of the cable, wherein the second web is a constituent part of the housing, and wherein the at least one sealing insert is formed from at least one elastically deformable material and has at least one through-opening configured for guiding through of the at least one cable, wherein the sealing insert possesses at least one slit along the through-opening which forms two mutually opposing slit surfaces so that the sealing insert assumes an opened state for inserting or removing the cable laterally and a closed state for sealing and strain relief of the cable, and wherein the sealing insert, without an influence of external forces, is located in its opened state in which it has a gap at its slit, by which the two slit surfaces are automatically separated from one another.

US Pat. No. 10,461,455

ELECTRICAL CONNECTOR ASSEMBLY

YAZAKI EUROPE LTD., Hert...

1. An electrical connector assembly comprising:a first connector having a first main contact element and a first auxiliary contact element, said first auxiliary contact element being electrically connected to said first main contact element,
a second connector having a second main contact element and a second auxiliary contact element, said second auxiliary contact element being electrically connected to said second main contact element,
wherein the first connector and the second connector are mateable in a mating direction parallel to a longitudinal axis L of the electrical connector assembly,
wherein the first and second main contact elements are configured to disconnect from each other before the first and second auxiliary contact elements dis-connect from each other during unmating the first and second connectors,
wherein in a fully mated condition the first and second main contact elements are in contact and the first and second auxiliary contact elements are disconnected from each other
wherein the first auxiliary contact element extends at least substantially parallel and radially distanced to the first main contact element, and
wherein the second auxiliary contact element extends at least substantially parallel and radially distanced to the second main contact element.

US Pat. No. 10,461,452

PROCESS FOR MAKING CORROSION-RESISTANT ELECTRICAL CONTACTS IN A WIDE RANGE OF COLORS

Apple Inc., Cupertino, C...

1. An electronic device, comprising:a housing that is characterized by a color; and
an electrical contact having an upper surface that is visible at an exterior surface of the housing, wherein the electrical contact comprises a metal substrate and an electrically conductive metal oxide that corresponds to the color of the housing corresponding to an optical path difference between the upper surface and an interface between the electrically conductive metal oxide and the metal substrate.

US Pat. No. 10,461,445

METHODS AND DEVICES FOR IMPEDANCE MULTIPLICATION

PSIQUANTUM CORP., Palo A...

1. An electric circuit, comprising:a first superconducting component having a first terminal, a second terminal, and a constriction region between the first terminal and the second terminal;
a second superconducting component having a third terminal and a fourth terminal; and
a first electrically-insulating component that thermally couples the first superconducting component and the second superconducting component such that heat produced at the constriction region is transferred through the first electrically-insulating component to the second superconducting component;
wherein the second superconducting component has a first portion between the third terminal and the fourth terminal; and
wherein the second superconducting component is positioned so that the first portion of the second superconducting component is in proximity with the first superconducting component such that heat produced at the first superconducting component transfers to the first portion.

US Pat. No. 10,461,439

FLEXIBLE POLYMER ANTENNA WITH MULTIPLE GROUND RESONATORS

TAOGLAS GROUP HOLDINGS LI...

1. An antenna assembly, comprising:an antenna radiating element; and
a ground conductor comprising a plurality of at least three sub-elements, wherein the sub-elements are ground resonators, and wherein the sub-elements are progressively larger in at least one dimension farther from the antenna radiating element;
wherein the antenna radiating element is positioned adjacent to the ground conductor.

US Pat. No. 10,461,437

MULTI-LAYER ABSORBER

ARC Technologies LLC, Am...

1. A multi-layer absorber, comprising:a plurality of polymeric layers disposed relative to one another to form a polymeric stack having an input layer and an output layer such that said input layer includes a radiation-receiving surface for receiving incident electromagnetic radiation and said output layer includes an exit surface through which at least a portion of the received radiation, if any, exits the stack, wherein the number of the plurality of polymeric layers is greater than 2 and equal to or less than 20,
a plurality of radiation-absorbing additives distributed within at least one of said plurality of polymeric layers, wherein a concentration of the plurality of radiation-absorbing additives is greater in said input layer relative to a concentration of said radiation-absorbing additives in said output layer, wherein said plurality of radiation-absorbing additives is capable of absorbing electromagnetic energy at one or more frequencies in a range of about 1 GHz to about 110 GHz,
wherein the real dielectric constants of said polymeric layers progressively increase from the input layer to the output layer for one or more frequencies in a range of about 1 GHz to about 110 GHz, and
wherein the absorber exhibits a coefficient of reflection equal to or less than about 0.3 and a coefficient of transmission equal to or less than about 0.3 for at least one incident radiation frequency in the range of about 1 GHz to about 110 GHz.

US Pat. No. 10,461,419

ANTENNA ADJUSTMENT APPARATUS AND REMOTE ELECTRICAL TILT ANTENNA

Huawei Technologies Co., ...

1. An antenna adjustment apparatus, configured to adjust a downtilt angle of an antenna assembly;wherein the antenna assembly comprises a plurality of phase shifters;
wherein the antenna adjustment apparatus comprises:
a first drive wheel, a first rotating shaft;
a gear carrier;
a first gear;
a second drive wheel;
a second gear; and
a plurality of output gears;
wherein the first drive wheel is meshed with the first gear;
wherein the second drive wheel is meshed with the second gear, and an axis of the second gear coincides with an axis of the first drive wheel;
wherein the plurality of output gears are connected to the plurality of phase shifters in a one-to-one correspondence manner;
wherein the gear carrier is sleeved on the first rotating shaft;
wherein the second gear is fixedly connected to the gear carrier;
wherein the first gear is configured to rotate together with the gear carrier;
wherein the second drive wheel is configured to propel the second gear to rotate and drive the first gear to revolve around the axis of the second gear, so that the first gear is selectively meshed with one of the plurality of output gears; and
wherein the first drive wheel is configured to propel the first gear to rotate and drive the output gear meshed with the first gear to rotate, and the output gear is configured to propel the phase shifter connected to the output gear.

US Pat. No. 10,461,411

ANTENNA AND ELECTRONIC DEVICE INCLUDING THE SAME

Samsung Electronics Co., ...

1. An electronic device comprising:a front glass cover defining a front surface of the electronic device;
a rear cover defining a rear surface of the electronic device;
a display comprising a screen area exposed through the front cover;
a non-metal structure disposed in the electronic device and comprising a first surface facing the front cover and a second surface facing the rear cover;
a metal structure disposed through a portion of the non-metal structure, such that a predetermined area of the metal structure is exposed through the first surface to the second surface of the non-metal structure; and
an antenna structure disposed at a portion of the first surface or the second surface of the non-metal structure and being electrically connected to the metal structure,
wherein the antenna structure comprises:
a second bonding layer attached to a portion of the second surface of the non-metal structure, and including a first opening corresponding to the metal structure, an antenna element pattern arranged on the second bonding layer and electrically connected to the metal structure through the first opening, a first bonding layer arranged on the antenna element pattern and an insulation layer arranged on the first bonding layer,
wherein the first bonding layer and the insulation layer form a second opening above the first opening, and
wherein the metal structure contacts to a conductive connector for supplying a power, and the conductive connector is distinct from the metal structure.

US Pat. No. 10,461,408

ELECTRICAL TILT APPARATUS, ANTENNA, AND ELECTRICAL TILT METHOD

HUAWEI TECHNOLOGIES CO., ...

1. An electrical tilt apparatus, comprising:a remote control unit (RCU), at least one combiner unit, and multiple phase shifters connected to the RCU;
wherein each of the at least one combiner unit is configured to:
connect to a different serial port on the RCU and connect to at least two radio frequency (RF) modules,
receive, at a time point, an electrical tilt signal sent by one of the at least two RF modules, and
send the electrical tilt signal to the RCU;
wherein the RCU is configured to:
receive the electrical tilt signal sent by each combiner unit, and
drive, according to the electrical tilt signal, a first phase shifter that corresponds to a first RF module to move, to adjust a phase of an RF signal input to the first phase shifter, wherein the first RF module is configured to send the electrical tilt signal and the RF signal, and the first phase shifter is one of the multiple phase shifters; and
wherein each combiner unit comprises a direct current power end, an on-off keying (OOK) output end, a resistance-capacitance (RC) circuit connected to the OOK output end, at least two OOK input ends, and at least two combiner modules connected to both the direct current power end and the RC circuit, the at least two combiner modules are connected to the at least two OOK input ends in a one-to-one correspondence manner, each of the at least two combiner modules is connected to different RF modules via one of the at least two OOK input ends, and the direct current power end and the OOK output end are connected to a same serial port on the RCU.

US Pat. No. 10,461,400

HOUSING INCLUDING ANTENNA, MANUFACTURING METHOD OF HOUSING, AND ELECTRONIC DEVICE HAVING HOUSING

Samsung Electronics Co., ...

1. An electronic device comprising:a housing that includes:
a first non-conductive structure including a first surface that surfaces in a first direction and a second surface that surfaces in a second direction that is opposite to the first direction; and
a second non-conductive structure formed integrally with a portion of the first non-conductive structure, and forming at least a portion of a third surface that surfaces in a third direction that is different from the first direction and the second direction;
a first conductive pattern formed to be in physical contact with the first surface of the first non-conductive structure;
a second conductive pattern formed to be in physical contact with the second surface of the first non-conductive structure;
a third conductive pattern electrically connected to the second conductive pattern;
at least one conductive connection part that electrically interconnects the first conductive pattern and the second conductive pattern; and
a communication circuit that uses at least a portion of the first conductive pattern, the second conductive pattern, the third conductive pattern, and the conductive connection part as a radiation pattern,
wherein the second non-conductive structure does not overlap with the first conductive pattern or the second conductive pattern when viewed from above the first surface, and
wherein the third conductive pattern is formed to be in physical contact with the third surface extending to surface in the third direction from the second surface of the first non-conductive structure.

US Pat. No. 10,461,388

MILLIMETER WAVE FABRIC NETWORK OVER DIELECTRIC WAVEGUIDES

INTEL CORPORATION, Santa...

1. A radio frequency (RF) communication system between semiconductor package substrates, comprising:an RF waveguide having a first end and a second end, wherein the RF waveguide comprises a structure that is at least partially hollow;
a first semiconductor package substrate that includes a first RF transceiver communicably coupled to the first end of the RF waveguide;
wherein the first RF transceiver includes a first RF signal producing die having a top mounting face and a bottom mounting face; and
a first serializer/deserializer (SERDES) communicably coupled to the first semiconductor package substrate and to the first RF signal producing die;
wherein the first end of the RF waveguide and the first SERDES are disposed on opposite mounting faces of the first RF signal producing die; and
a second semiconductor package substrate that includes a second RF transceiver communicably coupled to the second end of the RF waveguide to provide a RF communication pathway between one or more devices communicably coupled to the first semiconductor package substrate and one or more devices communicably coupled to the second semiconductor package substrate, the second semiconductor package substrate disposed remote from the first semiconductor package substrate.

US Pat. No. 10,461,381

BATTERY COOLING APPARATUS

DENSO CORPORATION, Kariy...

1. A battery cooling apparatus comprising:a case for housing battery cells arranged in the casing;
a fan device disposed in the case and configured to blow air to cool the battery cells;
a circulation passage formed inside the case and including a collective passage, a top plate side passage and battery passages extending in parallel from portions of the top plate side passage, wherein the circulation passage is configured so that the air blown from the fan device is sucked into the fan device after having circulated through the circulation passage, and having collected in the collective passage after having exchanged heat with the battery cells each of the battery passages extends from a portion of the top plate side passage to the collective passage through a respective one of the battery cells so that a portion of the air, after moving through the top plate passage, flows along a surface of one of the battery cells to the collective passage; and
a discharge passage configured to provide communication between inside and outside of the case to allow part of the air that circulates through the circulation passage to leak to outside the case through the discharge passage after having exchanged heat with the battery cells, the discharge passage including a pressure valve that is configured to open when a predetermined pressure condition is satisfied so that the discharge passage discharges air;
wherein
the fan device includes a first inflow passage and a second inflow passage,
the first inflow passage is part of the circulation passage and configured to allow the air having exchanged heat with the battery cells to be sucked into the fan device through the first inflow passage,
the second inflow passage is configured to provide communication between the outside of the case and the fan device to allow air outside the case to be sucked into the circulation passage through the second inflow passage by negative pressure which is produced by the fan device in the second inflow passage and arises from the discharge of the air through the pressure valve,
the collective passage extends in a direction along which the battery cells are arranged and each of the battery cells is exposed to the collective passage, and
the discharge passage is disposed downstream of a first passage part of the circulation passage and upstream of the first inflow passage so that the air blown from the fan device can exchange heat with the battery cells while passing through the first passage part.

US Pat. No. 10,461,367

MANUFACTURING METHOD FOR AMINO-SUBSTITUTED PHOSPHAZENE COMPOUND, MANUFACTURING METHOD FOR ELECTROLYTE SOLUTION FOR NONAQUEOUS SECONDARY BATTERY, AND MANUFACTURING METHOD FOR NONAQUEOUS SECONDARY BATTERY

FUJIFILM Corporation, To...

1. A manufacturing method for an amino-substituted phosphazene compound, comprising:reacting a fluorinated phosphazene compound and an amine compound in presence of a catalyst consisting of a compound consisting of a specific element M below and an oxygen atom as constituent elements; and
obtaining an amino-substituted phosphazene compound by substitution reaction between a fluorine atom of the fluorinated phosphazene compound and an amino group of the amine compound,
Specific element M: At least one selected from magnesium, titanium, zirconium, vanadium, lithium, calcium, aluminum, molybdenum, silicon, or boron;
wherein the amino-substituted phosphazene compound is a compound represented by Formula (1) below,

in the formula, Y1 represents —NR1R2, Y2 represents a fluorine atom or —NR3R4, R1 to R4 each independently represent a monovalent substituent or a hydrogen atom, R1 and R2 or R3 and R4 may form a ring, and n represents 1 or 2;
wherein the fluorinated phosphazene compound is represented by Formula (2) below,

in the formula, n represents 1 or 2.

US Pat. No. 10,461,366

ELECTROLYTE COMPOSITIONS FOR BATTERIES

ENEVATE CORPORATION, Irv...

1. An energy storage device, comprising:a first electrode and a second electrode, wherein at least one of the first electrode and the second electrode comprises a self-supporting composite material film, the composite material film comprising:
greater than 0% and less than about 90% by weight of silicon particles,
greater than 0% and less than about 90% by weight of one or more types of carbonized carbon phases, wherein at least one of the one or more types of carbonized carbon phases comprises hard carbon that is a continuous phase that holds the composite material film together such that the silicon particles are distributed throughout the composite material film, and
a silicon carbide layer between the silicon particles and the hard carbon;
a separator between the first electrode and the second electrode; and
an electrolyte in contact with the first electrode, the second electrode, and the separator, wherein the electrolyte comprises at least one of a fluorine-containing cyclic carbonate, a fluorine-containing linear carbonate, and a fluoroether.

US Pat. No. 10,461,352

CONCENTRATION MANAGEMENT IN FLOW BATTERY SYSTEMS USING AN ELECTROCHEMICAL BALANCING CELL

Lockheed Martin Energy, L...

1. A method comprising:providing a first electrochemical balancing cell comprising a membrane disposed between two half-cells;
establishing fluid communication between a first aqueous electrolyte solution of a flow battery system and a first half-cell of the first electrochemical balancing cell; and
applying a current to the first electrochemical balancing cell to change a concentration of one or more components in the first aqueous electrolyte solution;
wherein applying the current causes water to migrate across the membrane, either to or from the first aqueous electrolyte solution, and a rate of water migration is a function of current.

US Pat. No. 10,461,348

FUEL CELL SYSTEM AND METHOD OF CONTROLLING THE SAME

Hyundai Motor Company, S...

1. A fuel cell system, comprising:a supplying pipe configured to supply hydrogen and air to a stack;
a gas concentration sensor configured to sense impurities of the hydrogen and the air supplied to the supplying pipe;
a supplying valve disposed in the supplying pipe to adjust the supplying of the hydrogen and the air;
a discharging pipe configured to discharge the hydrogen and the air from the stack;
a discharging valve disposed in the discharging pipe to adjust the discharging of the hydrogen and the air;
a controller configured to be operated together with the gas concentration sensor to detect introduction of the impurities; and
exhaust valves disposed at a front end and a rear end of the stack to remove a polluted fuel in response to detecting the introduction of the impurities,
wherein the controller is further configured to:
determine whether a stack voltage is dropped due to the impurities of the hydrogen;
control the supplying valve and the exhaust valves to exhaust hydrogen and air in the stack and to supply hydrogen and air into the stack when it is determined that the stack voltage is dropped due to the impurities of the hydrogen; and
perform a logic of repeating start-on/off of the fuel cell system for predetermined times.

US Pat. No. 10,461,345

FUEL GAS STORAGE AND SUPPLY SYSTEM

Toyota Jidosha Kabushiki ...

1. A fuel gas storage and supply system that supplies fuel gas to a fuel cell, comprising:a filling port that includes a first check valve;
a decompression valve that adjusts a pressure of the fuel gas;
a fuel gas pipe that connects the filling port to the decompression valve;
one or more gas tanks that are connected to the fuel gas pipe;
an upstream shut valve that is disposed in the fuel gas pipe between an upstream gas tank closest to the filling port among the one or more gas tanks and the filling port;
a second check valve that is disposed in the fuel gas pipe between the filling port and the upstream shut valve;
a pressure sensor that is disposed in the fuel gas pipe between the upstream shut valve and the decompression valve; and
a controller configured to control opening and closing of the upstream shut valve using a measured pressure value of the pressure sensor,
wherein the controller is configured to repeatedly acquire the measured pressure value from the pressure sensor over time when the one or more gas tanks are filled with the fuel gas via the filling port and close the upstream shut valve when an increasing rate of the measured pressure value is less than a predetermined increasing rate threshold value.

US Pat. No. 10,461,344

MULTI-TANK METHANOL-WATER MIXTURE STORAGE SYSTEM OF FUEL CELL VEHICLE

GUANGDONG HYDROGEN ENERGY...

1. A multi-tank methanol-water mixture storage system of a fuel cell vehicle, characterized by comprising a main accommodating tank, wherein the main accommodating tank is fixedly provided with multiple explosion-proof methanol-water mixture storage tank bodies, and the explosion-proof methanol-water mixture storage tank bodies are connected with each other through a delivery channel provided with a delivery pump; each explosion-proof methanol-water mixture storage tank body is provided with a methanol inlet, a methanol outlet and a vent valve, the methanol inlet and the explosion-proof methanol-water mixture storage tank body are in form of an integrated structure, and all the methanol inlets are connected to a methanol inlet assembly disposed on the main accommodating tank through a liquid path pipeline; the vent valve is disposed on the methanol inlet and connected to the inside space of the main accommodating tank and/or a main vent hole disposed on the main accommodating tank through a gas path pipeline; and the methanol outlet is disposed at the bottom of the explosion-proof methanol-water mixture storage tank body and connected to hydrogen production device of the fuel cell vehicle through a pipeline, wherein the pipeline is provided with a multi-way valve, and the multi-way valve is connected to each methanol outlet assembly to output methanol-water mixture.

US Pat. No. 10,461,335

SOLID OXIDE FUEL CELLS WITH CATHODE FUNCTIONAL LAYERS

REDOX POWER SYSTEMS, LLC,...

1. A solid oxide fuel cell comprising:a cathode;
a solid electrolyte for conducting oxygen ions from the cathode to an anode;
an anode for reacting oxygen ions from the solid electrolyte with a hydrogen-containing fuel; and
disposed between the cathode and the solid electrolyte, a functional layer for improving conduction within the solid oxide fuel cell,
wherein (i) the functional layer contains cobalt, (ii) the solid electrolyte comprises a first layer and a second layer disposed on the first layer, (iii) the first layer of the solid electrolyte contains cobalt, and (iv) the second layer of the solid electrolyte is free of cobalt.

US Pat. No. 10,461,323

COMPOSITE LITHIUM BORATES AND/OR PHOSPHATES AND POLYMER COATINGS FOR ACTIVE MATERIAL PARTICLES

Storedot Ltd., Herzeliya...

1. Anode active material particles comprising:metalloid cores comprising at least one of Si, Ge and Sn, having diameter in a range of 20-500 nm, and
a composite coating on said metalloid cores, said composite coating comprising lithium borates and/or lithium phosphates and polymer molecules,
wherein the lithium borates and/or lithium phosphates alternate with polymer molecules within the composite coating, with the lithium borates and/or lithium phosphates interconnecting the polymer molecules, and
wherein the polymer molecules are anchored by the lithium borates and/or lithium phosphates to the metalloid cores.

US Pat. No. 10,461,306

BATTERY AND METHOD OF ATTACHING SAME TO A GARMENT

KONINKLIJKE PHILIPS N.V.,...

1. A battery comprising:a source of voltage;
at least one positive voltage connection on the source of voltage;
at least one negative voltage connection on the source of voltage;
a first magnetic element that is collocated with the at least one positive voltage connection; and
a second magnetic element that is collocated with the at least one negative voltage connection; wherein the battery comprises a first surface and a second surface that is opposite the first surface;
wherein the at least one positive voltage connection comprises a first positive voltage connection on the first surface and a second positive voltage connection on the second surface;
wherein the at least one negative voltage connection comprises a first negative voltage connection on the first surface and a second negative voltage connection on the second surface; and
wherein the first and second magnetic elements have an “N” pole on the first surface and an “S” pole on the second surface.

US Pat. No. 10,461,305

BATTERY CELL AND BATTERY SYSTEM

Robert Bosch GmbH, Stutt...

1. A battery cell (2) comprising a prismatically-designed cell housing (3) having a cover surface (31), on which a negative terminal (11) and a positive terminal (12) are arranged projecting outwardly from the cover surface (31), and comprising at least one electrode coil (10) arranged within the cell housing (3), the electrode coil having a cathode (14), which has cathode contact lugs (24), and the electrode coil having an anode (16), which has anode contact lugs (26), wherein the cathode contact lugs (24) and the anode contact lugs (26) extend adjacently from the electrode coil (10) toward precisely one end surface (35, 36) of the cell housing (3), and wherein the end surface (35, 36) is oriented at right-angles to the cover surface (31).

US Pat. No. 10,461,296

BATTERY SEPARATOR FILM, NONAQUEOUS ELECTROLYTE SECONDARY BATTERY SEPARATOR, AND NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SUMITOMO CHEMICAL COMPANY...

1. A battery separator film which curls with respect to a width direction of the battery separator film, the battery separator film being a laminated porous film including a functional layer having a uniform thickness comprising a wholly aromatic polyamide, wherein the functional layer is provided on only one surface of the laminated porous film;wherein the battery separator film exhibits a difference of not more than 5 mm between (i) a width of the battery separator film and (ii)
a projection width of a part of the battery separator film which part is smallest in projection width when seen from a direction perpendicular to a surface of the battery separator film while the battery separator film, to which a tension of 90 N/m is applied, is stretched between two rollers that are provided in parallel with each other at an interval of 1 m at a temperature of 23 degrees Celsius and a relative humidity of 50%.

US Pat. No. 10,461,293

MICROPOROUS MEMBRANES, SEPARATORS, LITHIUM BATTERIES, AND RELATED METHODS

Celgard, LLC, Charlotte,...

1. A microporous battery separator membrane comprising:a microporous polyolefin separator membrane modified with low energy electron beam radiation in a dosage ?70 kGy and ?120 kGy in a nitrogen atmosphere, and having a thickness less than about 14 ?m and wherein:
said microporous polyolefin separator membrane has an onset of thermal shutdown occurring at a temperature ?138° C.;
said microporous polyolefin separator membrane has % machine direction thermal shrinkage at 120° C. for one hour of ?7.5%; and/or
said microporous polyolefin separator membrane has % transverse direction thermal shrinkage at 120° C. for one hour ?1%.

US Pat. No. 10,461,281

LIGHT EMITTING DEVICE

Industrial Technology Res...

1. A light emitting device, comprising:a substrate;
a first electrode disposed on the substrate;
a light emitting layer disposed on the first electrode;
a second electrode disposed on the light emitting layer, wherein the first electrode, the light emitting layer, and the second electrode are sequentially stacked on the substrate to constitute a light emitting unit;
a heat shrinkable film disposed on the light emitting unit;
a first adhesive layer disposed between the heat shrinkable film and the second electrode;
a gas barrier substrate, wherein the light emitting unit, the first adhesive layer and the heat shrinkable film are disposed between the substrate and the gas barrier substrate; and
a second adhesive layer disposed between the heat shrinkable film and the gas barrier substrate, wherein an adhesion strength between the second adhesive layer and the heat shrinkable film is smaller than an adhesion strength between the first adhesive layer and the heat shrinkable film.

US Pat. No. 10,461,280

DOUBLE-SIDED ELECTROLUMINESCENT DISPLAY PANEL AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A double-sided electroluminescent display panel, comprising:a double-sided light-emitting transparent electroluminescent structure;
a first absorption polarization structure disposed on a first light-emitting surface of the transparent electroluminescent structure; and
a first reflective polarization structure disposed on a second light-emitting surface of the transparent electroluminescent structure, wherein transmission axes of the first absorption polarization structure and the first reflective polarization structure are perpendicular to each other, the first absorption polarization structure is configured to absorb light of a first wave component and transmit light of a second wave component, and the first reflective polarization structure is configured to transmit the light of the first wave component and reflect the light of the second wave component.

US Pat. No. 10,461,276

ORGANIC OPTOELECTRONIC COMPONENT AND METHOD OF PREVENTING THE ANALYSIS OF THE MATERIAL COMPOSITION OF AN ORGANIC OPTOELECTRONIC COMPONENT

OSRAM OLED GmbH, Regensb...

1. A method of preventing an analysis of the material composition of an organic optoelectronic component comprising:A) providing an organic optoelectronic component comprising a functional component part and a camouflage layer, and
B) determining an overall analysis spectrum of the organic optoelectronic component by IR or X-ray radiation,
wherein the overall analysis spectrum is composed of a first analysis spectrum of the functional component part and a second analysis spectrum of the camouflage layer, and
determination of the first and/or second analysis spectrum from the overall analysis spectrum is prevented so that, due to the camouflage layer, determination of the material composition of the functional component part is prevented.

US Pat. No. 10,461,266

LUMINESCENT COMPOUNDS AND METHODS OF USING SAME

1. A compound having general formula (1):
wherein G is oxygen, aliphatic, methylene, carbonyl, amine, silylene, phosphine, phosphine oxide, sulfur, sulfonyl, or a combination thereof;
R1 and R2 are independently a hydrogen, an aliphatic moiety, or fluorine, with the proviso that if one of R1 and R2 is aliphatic, CF3, or fluoro, then the other is hydrogen;
R3 is independently H, or a substituted or unsubstituted aliphatic moiety, substituted or unsubstituted aryl moiety, a substituted or unsubstituted amine, halo, thioether, ether, or any combination thereof, and the R3 of one triazolyl ring can be joined to the R3 of the other triazolyl ring; and
R4 is optionally further substituted, and is a non-aromatic carbocycle or heterocycle, an aryl group (which includes a heteroaryl) that is attached as a fused ring or as a substituent, a hydroxy group, nitro, amino, halo, BR2, B(aryl)2, aryl-B(aryl)2, NR2, OR, a nitrile group, —C(halo)3, and R, where R is a substituted or unsubstituted aliphatic group having 1-24 carbon atoms which may be straight, branched or cyclic H, a substituted or unsubstituted aliphatic moiety, halo, a substituted or unsubstituted aryl moiety, or any combination thereof.

US Pat. No. 10,461,261

COMPOUND, LIGHT EMITTING MATERIAL, AND ORGANIC LIGHT EMITTING DEVICE

KYUSHU UNIVERSITY, NATION...

1. A compound represented by the following generalformula (2):
wherein in the general formula (2), R1 to R5 each independently represent a hydrogen atom, a cyano group or an alkyl group having from 1 to 10 carbon atoms, provided that R2 and at least one of R1, R4 and R5 represent a cyano group; R6 to R10 each independently represent a hydrogen atom, a cyano group or an alkyl group having from 1 to 10 carbon atoms, provided that at least R7 and two of R6, R9 and R10 represents a cyano group; and R11 to R17 and R21 to R27 each independently represent a hydrogen atom or an alkyl group having from 1 to 10 carbon atoms.

US Pat. No. 10,461,250

MAGNETORESISTIVE STACK/STRUCTURE AND METHOD OF MANUFACTURING SAME

EVERSPIN TECHNOLOGIES, IN...

1. A method of manufacturing a magnetoresistive stack/structure from: (i) a first magnetic region including one or more layers of magnetic material, (ii) an intermediate layer disposed over the first magnetic region, and (iii) a second magnetic region including one or snore layers of magnetic material, wherein the second magnetic region is disposed over the intermediate layer, the method comprising:using a first etch process to etch through the second magnetic region to form one or more first sidewalls and expose an area of the intermediate layer, wherein the one or more first sidewalls and the area of the intermediate layer exposed by the first etch process form exposed surfaces, and wherein at least a portion of the exposed surfaces, after the first etch process, includes re-deposited material;
depositing a first encapsulation layer on the exposed surfaces after the first etch process;
after depositing the first encapsulation layer, using a second etch process to remove at least a portion of the re-deposited material from the exposed surfaces; and
after removing at least a portion of the re-deposited material, etching through the intermediate layer to form one or more second sidewalls; and
depositing a second encapsulation layer on the one or more second sidewalls.

US Pat. No. 10,461,248

BOTTOM ELECTRODE FOR MRAM APPLICATIONS

INTERNATIONAL BUSINESS MA...

1. A process of forming a bottom electrode in a magnetoresistive random access memory (MRAM) device, the process comprising:providing a structure comprising a dielectric layer including a patterned feature lined with a barrier layer and a metal conductor;
planarizing a surface of the structure stopping at the dielectric layer to remove an overburden of the metal conductor;
forming a recess in the metal conductor;
depositing a conductive liner material in the recess of the metal conductor and on the dielectric layer;
depositing tantalum nitride cap layer in the recess on the conductive liner material and on the dielectric layer; and
polishing the tantalum nitride cap layer to the dielectric layer with a chemical mechanical planarization process to form the bottom electrode, wherein a height differential between upper surfaces of the tantalum nitride cap layer and the dielectric layer is less than 3 nanometers, wherein the conductive liner material is harder than the tantalum nitride.

US Pat. No. 10,461,242

ANTIFERROMAGNETIC EXCHANGE COUPLING ENHANCEMENT IN PERPENDICULAR MAGNETIC TUNNEL JUNCTION STACKS FOR MAGNETIC RANDOM ACCESS MEMORY APPLICATIONS

SPIN MEMORY, INC., Fremo...

1. A magnetic memory element, comprising:a magnetic free layer;
a magnetic reference layer;
a non-magnetic barrier layer located between the magnetic reference layer and the magnetic free layer; and
a synthetic antiferromagnetic structure exchange coupled with the magnetic reference layer, the synthetic antiferromagnetic structure further comprising:
a first magnetic structure;
a second magnetic structure; and
an antiferromagnetic exchange coupling structure located between the first and second magnetic structures, the antiferromagnetic exchange coupling structure including a layer of Ru located between first and second layers of Pt.

US Pat. No. 10,461,227

METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE, AND LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device, comprising:a light emitting element,
a package having a recess in which the light emitting element is located, and
a sealing resin filling the recess,
wherein the package includes a projection extending from an upper surface of the package, the projection at least partially surrounding the recess,
wherein a roughened surface section is formed on an upper surface of the projection,
wherein the upper surface of the projection on which the roughened surface section is formed is inclined in a direction away from the light emitting element, and
wherein the upper surface of the projection has an inner edge and an outer edge, and the roughened surface section on the upper surface of the projection extends from the inner edge to the outer edge.

US Pat. No. 10,461,219

LIGHT EMITTING ELEMENT

NICHIA CORPORATION, Anan...

1. A light emitting element comprising:a semiconductor layered structure comprising an n-side semiconductor layer and a p-side semiconductor layer each made of a nitride semiconductor and at least partially overlapped with each other;
an n-pad electrode disposed on an upper surface of the n-side semiconductor layer in a different region from where the p-side semiconductor layer is disposed;
a light-transmissive electrically conductive film disposed on an upper surface of the p-side semiconductor layer; and
a p-pad electrode disposed on an upper surface of the light-transmissive electrically conductive film,
wherein, when viewed in a plan view,
an outer peripheral shape of the semiconductor layered structure has a pentagonal shape having a first side, a second side adjacent to the first side at a right angle to the first side, a third side adjacent to the first side at a right angle to the first side, a fourth side adjacent to the second side at an obtuse angle to the second side, and a fifth side adjacent to the third side and the fourth side at an obtuse angle to the third side, the fourth side and the fifth side meet to form a first vertex,
the n-pad electrode is disposed closer to the first side than to the first vertex, and
the p-pad electrode is disposed closer to the first vertex than the n-pad electrode is disposed to the first vertex.

US Pat. No. 10,461,217

VERTICAL STRUCTURE LEDS

LG INNOTEK CO., LTD., Se...

20. A method for manufacturing a light emitting diode, comprising:forming a GaN-based semiconductor structure with a thickness of a less than 5 microns on a substrate, the GaN-based semiconductor layer comprising:
a p-type GaN-based semiconductor layer;
an active layer on the p-type GaN-based semiconductor layer; and
an n-type GaN-based semiconductor layer on the active layer;
forming a p-type electrode having multiple metal layers on the p-type GaN-based semiconductor layer with contacting a bottom surface of the Gall-based semiconductor structure;
forming a metal support layer comprising Ti and non-metal material on the p-type electrode, a top surface of the metal support layer contacting the p-type electrode;
removing the substrate from the GaN-based semiconductor structure to expose an upper surface of the GaN-based semiconductor structure;
forming an n-type electrode comprising Ti and Al on the upper surface of the GaN-based semiconductor structure, with overlapping at least a portion of the p-type electrode in a thickness direction of the GaN-based semiconductor structure;
forming an insulating layer including at least one of SiO2 or Si3N4, on the upper surface of the GaN-based semiconductor structure and on an entire side surface of the GaN-based semiconductor structure, wherein a first part formed on the upper surface of the GaN-based semiconductor structure in the insulating layer contacts the upper surface of the GaN-based semiconductor structure;
forming an open space exposing the n-type electrode by patterning the first part of the insulating layer; and
forming a metal pad layer at the open space, an uppermost surface of the metal pad layer being formed at a higher position than the first part of the insulating layer,
wherein a second part formed on the entire side surface of the GaN-based semiconductor structure in the insulating layer does not contact the n-type electrode.

US Pat. No. 10,461,216

GALLIUM NITRIDE CROSS-GAP LIGHT EMITTERS BASED ON UNIPOLAR-DOPED TUNNELING STRUCTURES

Wright State University, ...

1. A solid-state device, comprising:a unipolar doped light emitting diode or laser diode comprising:
a bottom n-type layer;
a top n-type layer;
an undoped or n-type doped middle layer inserted between the top layer and bottom layer, where the middle layer comprises at least two materials which serve as one or more heterojunction tunnel barriers;
and where the top layer and the middle layer, the bottom layer and the middle layer, or both form an interband tunnel barrier for electrons that generate holes by interband Zener tunneling through the forbidden energy gap, and where the middle layer forms at least one intraband tunnel barrier to control the interband Zener tunneling within the active region of the light emitting diode or the laser diode.

US Pat. No. 10,461,195

SEMICONDUCTOR DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate;
channel semiconductor patterns vertically stacked and spaced apart from each other on the substrate;
a gate electrode running across the channel semiconductor patterns;
source/drain regions at opposite sides of the gate electrode, the source/drain regions being connected to the channel semiconductor patterns;
an interlayer dielectric layer covering the source/drain regions; and
air gaps between the substrate and bottom surfaces of the source/drain regions so that the bottom surfaces of the source/drain regions do not contact the substrate,
wherein, when viewed in cross section, top surfaces of the air gaps are defined by the bottom surfaces of the source/drain regions, and side surfaces of the air gaps are defined by the interlayer dielectric layer,
wherein the substrate comprises on its upper portion a fin-shaped active pattern including a first region under the gate electrode and second regions on the opposite sides of the gate electrode,
wherein the channel semiconductor patterns are disposed on the first region, and
wherein the bottom surfaces of the source/drain regions are lower than a bottom surface of a lowermost one of the channel semiconductor patterns and higher than top surfaces of the second regions.

US Pat. No. 10,461,189

FIN FIELD EFFECT TRANSISTORS HAVING LINERS BETWEEN DEVICE ISOLATION LAYERS AND ACTIVE AREAS OF THE DEVICE

SAMSUNG ELECTRONICS CO., ...

1. An integrated circuit device comprising:a substrate;
a first fin active area protruding from the substrate;
a second fin active area protruding from the substrate;
a first insulating liner disposed on a first portion of the substrate and on a sidewall of the first fin active area;
a first stress liner disposed on the first insulating liner;
a first device isolation layer disposed on the first stress liner;
a second insulating liner disposed on a second portion of the substrate and on a sidewall of the second fin active area;
a second stress liner disposed on the second insulating liner; and
a second device isolation layer disposed on the second stress liner,
wherein the first stress liner is a single layer formed between the first device isolation layer and the first insulating liner,
the second stress liner is a single layer formed between the second device isolation layer and the second insulating liner,
a thickness of the first insulating liner is greater than a thickness of the second insulating liner,
an upper surface of the first device isolation layer has an inclined edge portion, the inclined edge portion being closer to the substrate as a distance from the first tin active area increases, and
wherein an upper surface of the inclined edge portion is lower than an upper surface of an end portion of the first stress liner.

US Pat. No. 10,461,172

VERTICAL TRANSISTORS HAVING IMPROVED GATE LENGTH CONTROL USING UNIFORMLY DEPOSITED SPACERS

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming a channel fin structure across from a major surface of a substrate, wherein the channel fin structure comprises a plurality of channel fins, wherein a first spacing is defined between adjacent ones of a first set of the plurality of channel fins, wherein a second spacing is defined between adjacent ones of a second set of the plurality of channel fins, wherein the first spacing is not equal to the second spacing;
forming an initial gate structure over the plurality of channel fins;
forming spacers along vertical sidewall portions of the initial gate structure, each of the spacers having a predetermined spacer height dimension, wherein a thickness dimension of each of the spacers is insufficient to allow any one of the spacers to fill the first spacing or the second spacing; and
subsequent to forming the spacers along the vertical sidewall portions of the initial gate structure, removing portions of the initial gate structure where the vertical sidewall portions of the initial gate structure are not covered by the spacers to define a plurality of gate structures each having a gate structure height dimension defined by the spacer height dimension;
wherein a gate length dimension of each of the plurality of gate structures comprises the gate height dimension.

US Pat. No. 10,461,171

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH METAL GATE STACKS

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device structure, comprising:forming a first dummy gate stack and a second dummy gate stack over a semiconductor substrate;
forming a dielectric layer over the semiconductor substrate to surround the first dummy gate stack and the second dummy gate stack;
removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer;
respectively forming a first metal gate stack and a second metal gate stack in the first trench and the second trench;
partially removing the first metal gate stack, the second metal gate stack, and the dielectric layer to form a recess, wherein the recess penetrates through the first metal gate stack and the second metal gate stack; and
forming an insulating structure to at least partially fill the recess, wherein the insulating structure has a first portion between two parts of the first metal gate stack, a second portion between two parts of the second metal gate stack, and a third portion linking the first portion and the second portion.

US Pat. No. 10,461,156

LDMOS TRANSISTOR AND METHOD OF FORMING THE LDMOS TRANSISTOR WITH IMPROVED RDS*CGD

TEXAS INSTRUMENTS INCORPO...

1. A transistor, comprising:a semiconductor substrate having a top surface;
a gate positioned above the top surface;
a first drain drift region positioned near the top surface and extending partially under the gate;
a first back gate region staggering with the first drain drift region under the gate;
a second drain drift region positioned directly under the first drain drift region and staggering with the first back gate region under the gate; and
a second back gate region positioned directly under the first back gate region and the second drain drift region,
a first drain dopant concentration peak (DCP) between the top surface and the first drain drift region, the first drain DCP extending partially under the gate;
a first back gate DCP between the top surface and the first back gate region, the first back gate DCP extending partially under the first drain DCP;
a second drain DCP between the first drain drift region and the second drain drift region, the second drain DCP extending partially under the first backgate DCP;
a second back gate DCP between the first back gate region and the second back gate region, the second back gate DCP extending partially under the second drain DCP; and
a third back gate DCP below the second back gate region, the third back gate DCP extending under and across the second drain DCP.

US Pat. No. 10,461,149

ELEVATIONALLY-ELONGATED CONDUCTIVE STRUCTURE OF INTEGRATED CIRCUITRY, METHOD OF FORMING AN ARRAY OF CAPACITORS, METHOD OF FORMING DRAM CIRCUITRY, AND METHOD OF FORMING AN ELEVATIONALLY-ELONGATED CONDUCTIVE STRUCTURE OF INTEGRATED CIRCUITRY

Micron Technology, Inc., ...

1. A method of forming an array of capacitors, comprising:providing a substrate comprising an array of horizontally-elongated and laterally-spaced conductive-line structures, conductive vias being laterally between and spaced longitudinally along immediately-laterally-adjacent of the conductive-line structures;
forming conductive material directly above the conductive-line structures and directly above and directly against the conductive vias, the conductive material having an upper surface and a first sidewall that are directly above individual of the conductive vias in a vertical cross-section, the conductive material having a second sidewall directly above an immediately-laterally-adjacent of the conductive-line structures in the vertical cross-section;
forming covering material directly above individual of the upper surfaces and against individual of the first sidewalls directly above the individual conductive vias, the covering material comprising a composition different from that of at least some of the conductive material;
etching completely through at least some of the covering material that is directly above the individual upper surfaces to the conductive material directly there-below and etching into said conductive material below uppermost surfaces of the conductive-line structures, the covering material that is against the individual first sidewalls masking the individual first sidewalls from being etched during said etchings; and
forming a plurality of capacitors individually comprising a lower conductive electrode, an upper conductive electrode, and a capacitor insulator there-between; individual of the lower conductive electrodes comprising the conductive material directly above said immediately-laterally-adjacent individual conductive-line structures.

US Pat. No. 10,461,122

LIGHT EMITTING DIODE DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A light emitting diode display panel, comprising:a substrate;
a plurality of light emitting diodes arranged in an array on the substrate;
a plurality of polarization layers, located on a light exit side of the plurality of light emitting diodes respectively, and the plurality of polarization layers are in a one-to-one correspondence to the plurality of light emitting diodes;
wherein the plurality of polarization layers comprise a plurality of first polarization layers and a plurality of second polarization layers having different polarization directions.

US Pat. No. 10,461,119

SOLID-STATE IMAGING DEVICE, IMAGING SYSTEM, AND METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE

Canon Kabushiki Kaisha, ...

1. A solid-state imaging device, comprising:a pixel including a photoelectric conversion element and a charge holding portion to which a charge generated by the photoelectric conversion element is transferred in a pixel region;
a peripheral circuit that processes a signal from the pixel in a peripheral region;
a light-shielding layer that is disposed in the pixel region and the peripheral region and that is electrically connected to a substrate at a contact portion in the peripheral region;
a first insulating layer that has a side surface between the charge holding portion and the contact portion in a plan view and that is disposed between the substrate and the light-shielding layer in a section perpendicular to a plane of the plan view; and
a first insulating member that is disposed on the side surface of the first insulating layer,
wherein an angle formed between an upper surface of the first insulating layer and a side surface of the first insulating member is larger than an angle formed between the upper surface of the first insulating layer and the side surface of the first insulating layer, and
wherein a portion of the light-shielding layer that overlaps the first insulating member in the plan view has an upper surface having a shape following a shape of the first insulating member.

US Pat. No. 10,461,116

SEMICONDUCTOR PACKAGING METHOD AND SEMICONDUCTOR DEVICE BASED ON MOLDING PROCESS

NINGBO SUNNY OPOTECH CO.,...

1. An image processing assembly, comprising:an encapsulated component;
a photosensitive element, supported by at least one portion of a top surface of the encapsulated component;
a compensation part, disposed in a portion of the top surface of the encapsulated component other than the at least one portion, and in contact with a side portion of the photosensitive element; and
a packaging component, configured to embed at least two of the photosensitive element, the encapsulated component, and the compensation part; wherein the compensation part is distributed around the photosensitive element to form a frame.

US Pat. No. 10,461,115

PHOTODIODE ARRAY

HAMAMATSU PHOTONICS K.K.,...

1. A photodiode array comprising a plurality of photodiodes formed in a semiconductor substrate,wherein each of the photodiodes includes:
a first semiconductor region of a first conductivity type, and provided in the semiconductor substrate;
a second semiconductor region of a second conductivity type, provided with respect to the first semiconductor region on one surface side of the semiconductor substrate so as to surround a predetermined region, and constituting a light detection region together with the first semiconductor region; and
a through-electrode provided within a through-hole passing through the one surface and another surface of the semiconductor substrate so as to pass through the first semiconductor region and the predetermined region, and electrically connected to the second semiconductor region, wherein:
the through-hole includes a portion expanded from the one surface toward the another surface,
the predetermined region is surrounded by one monolithic or a plurality of second semiconductor regions electrically connected to the through-electrode so that the predetermined region is surrounded by an inner edge of the one monolithic second semiconductor region that is electrically connected to the through-electrode, or so that the predetermined region is surrounded by each inner edge of the plurality of second semiconductor regions that are electrically connected commonly to the through-electrode,
each of the one or more inner edges of the one monolithic or plurality of second semiconductor regions is separated from an aperture edge of the through-hole on the one surface side of the semiconductor substrate,
a portion of the first semiconductor region is included in the predetermined region between the inner edge of the second semiconductor region and the aperture edge of the through-hole on the one surface side,
each of the photodiodes includes a contact electrode formed on the one surface and electrically connecting the second semiconductor region and the through-electrode, and
the contact electrode comprises metal, covers an aperture of through-hole on the one surface side, and extends to the predetermined region surrounded by the second semiconductor region.

US Pat. No. 10,461,114

MARKING SYSTEM AND METHOD

LMD Power of Light Corpor...

1. An infrared laser emitting system comprising:a quantum cascade laser emitter configured to generate a beam of infrared radiation;
an optical system downstream of the quantum cascade laser emitter, the optical system being configured to receive the beam of infrared radiation and to emit a cone of divergent infrared laser radiation from the infrared laser emitting system; and
a driver configured to control at least one of the quantum cascade laser emitter or the optical system to vary a divergence of the beam, the cone emitted from the infrared laser emitting system having a varying divergence such that when the cone is detected by a thermal imager remote from the quantum cascade laser emitter, the cone is distinguishable from a background object in a corresponding image generated by the thermal imager.

US Pat. No. 10,461,075

EMBEDDED TUNGSTEN RESISTOR

Texas Instruments Incorpo...

1. An integrated circuit, comprising:a substrate;
a well formed in the substrate;
a silicide layer formed in the well;
a tungsten resistor formed over the silicide layer;
a first polysilicon lead formed over the silicide layer; and
a second polysilicon lead formed over the silicide layer and adjacent to the first polysilicon lead to define a resistor trench above the substrate.

US Pat. No. 10,461,068

HIGHLY INTEGRATED RF POWER AND POWER CONVERSION BASED ON GA2O3 TECHNOLOGY

The United States of Amer...

1. An integrated circuit, comprising:a first substrate with a first thermal conductivity;
an active layer deposited on the first substrate;
at least one native device fabricated on the active layer;
a window formed in the active layer and exposing a portion of the first substrate; and
a non-native device fabricated in a second substrate with a second thermal conductivity lower than the first thermal conductivity,
wherein the non-native device is mounted in the window on the first substrate using a flip chip mount and electrically connected to the at least one native device,
wherein the non-native device added a circuit or electrical functionality to the first substrate, and
wherein the non-native device is thermally connected to the first substrate such that heat generated by the non-native device is removed through the first substrate.

US Pat. No. 10,461,053

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:(a) a semiconductor substrate of substantially rectangular shape having a pair of long edges and a pair of short edges;
(b) an internal circuit including a plurality of MISFETs formed over the semiconductor substrate;
(c) a plurality of protection elements formed over the semiconductor substrate so as to protect the internal circuit against static electricity;
(d) a first insulating film formed over the semiconductor substrate so as to cover the plurality of MISFETs and the plurality of protection elements; and
(e) a plurality of bump electrodes formed over the first insulating film, the plurality of bump electrodes being arranged along a first long edge of the pair of long edges,
wherein the plurality of bump electrodes are bump electrodes for receiving input signals from an external device,
wherein the plurality of protection elements are electrically coupled between the respective plurality of bump electrodes and the internal circuit,
wherein the plurality of bump electrodes include a first bump electrode and a second bump electrode,
wherein the plurality of protection elements include a first protection element and a second protection element,
wherein the first protection element electrically coupled to the first bump electrode is disposed at a position overlapped with the first bump electrode in a planar view when viewed from a direction perpendicular to the substrate, and
wherein the second protection element electrically coupled to the second bump electrode is disposed at a position different from a position overlapped with the second bump electrode in a planar view when viewed from a direction perpendicular to the substrate.

US Pat. No. 10,461,048

INTEGRATED CIRCUITS AND METHODS OF MANUFACTURING

LEONARDO MW LTD., Basild...

7. A method according to claim 6, in which:the manufacturing step (a) comprises:
manufacturing the amplifier with a first smaller gate size, and
the manufacturing step (b) comprises:
manufacturing a carrier chip having the second stage amplifier with a second gate size larger than that in the first portion.

US Pat. No. 10,461,046

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first region;
a second region surrounding an outer periphery of the first region; and
an annular seal ring formed in the second region,
wherein the second region includes:
an SOI substrate comprised of a semiconductor substrate of a first conductivity type, a buried insulating film over the semiconductor substrate, and a semiconductor layer over the buried insulating film; and
an interlayer insulating film formed over the semiconductor layer,
wherein the seal ring includes:
an annular electrode portion comprised of a conductive film buried in the interlayer insulating film;
the semiconductor layer; and
the buried insulating film, and
wherein the electrode portion is electrically connected with the semiconductor layer,
wherein an element isolation portion is formed in the semiconductor substrate between the first region and the second region, and the element isolation portion is thicker than the buried insulating film, and
wherein the semiconductor substrate under the buried insulating film has more than one PN junction portion.

US Pat. No. 10,461,037

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH OVERLAY GRATING

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device structure, comprising:forming a first overlay grating over a substrate, wherein the first overlay grating has a first strip portion and a second strip portion, the first strip portion and the second strip portion are elongated in a first elongated axis and are spaced apart from each other, there is a first distance between a first sidewall of the first strip portion and a second sidewall of the second strip portion, the first sidewall faces away from the second strip portion, and the second sidewall faces the first strip portion;
forming a first layer over the first overlay grating, wherein the first layer has a first trench elongated in a second elongated axis, the second elongated axis is substantially perpendicular to the first elongated axis, and the first trench extends across the first strip portion and the second strip portion; and
forming a second overlay grating over the first layer, wherein the second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, and the first distance is substantially equal to the second distance,
wherein the first layer further has a second trench elongated in the second elongated axis, the second trench extends across the first strip portion and the second strip portion, there is a third distance between a first inner wall of the first trench and a second inner wall of the second trench, the first inner wall faces away from the second trench, the second inner wall faces the first trench, and the third distance is less than the second distance.

US Pat. No. 10,461,036

MULTI-STACKED PACKAGE-ON-PACKAGE STRUCTURES

Taiwan Semiconductor Manu...

1. A device comprising:a first substrate;
a first integrated circuit die over the first substrate;
a second integrated circuit die over the first substrate, the second integrated circuit die having a different function than the first integrated circuit die;
a passive device over the second integrated circuit die, the passive device comprising a second substrate and through silicon vias (TSVs) extending through the second substrate; and
a first redistribution structure over the passive device, the first integrated circuit die, and the second integrated circuit die, the TSVs of the passive device electrically connecting the second integrated circuit die to the first redistribution structure.

US Pat. No. 10,461,035

SEMICONDUCTOR PACKAGE STRUCTURE

Industrial Technology Res...

1. A semiconductor package structure, comprising:a redistribution structure comprising a redistribution layer and a first dielectric layer disposed on the redistribution layer;
a chip disposed the on the redistribution structure;
an upper dielectric layer disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials;
a plurality of conductive members disposed between the redistribution layer and the chip, with each conductive member having a first end adjacent to the chip and a second end adjacent to the redistribution structure;
wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer; and
an encapsulation layer filled between the redistribution structure, the chip and the plurality of conductive members,
wherein Young's modulus of the upper dielectric layer is A, Young's modulus of the encapsulation layer is B, and Young's modulus of the first dielectric layer is D, wherein the semiconductor package structure satisfies the following inequalities:
A/B<1; and D/B<1.

US Pat. No. 10,461,006

ENCAPSULATED SEMICONDUCTOR PACKAGE

Amkor Technology, Inc., ...

1. An integrated circuit package comprising:a substrate comprising a first substrate side, a second substrate side opposite the first substrate side, and a plurality of lateral substrate sides that extend between the first substrate side and the second substrate side;
an integrated circuit die comprising a first die surface, a second die surface opposite the first die surface, and a plurality of lateral die surfaces that extend between the first die surface and the second die surface, where the second die surface is coupled to the first substrate side; and
an encapsulant that covers at least the plurality of lateral die surfaces and the plurality of lateral substrate sides,
wherein the substrate comprises a plurality of conductive layers comprising:
a first conductive layer comprising a plurality of conductive interconnects at the first substrate side, wherein:
each of the conductive interconnects is coupled to a respective pad of the integrated circuit die;
each of the conductive interconnects comprises a metal positioned outside a footprint of the integrated circuit die; and
each of the conductive interconnects comprises a laterally outermost surface that is positioned laterally inward from an outermost periphery of the substrate; and
a second conductive layer comprising a plurality of lands at the second substrate side.

US Pat. No. 10,460,993

FIN CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a first direction;
a first isolation structure separating a first end of a first portion of the fin from a first end of a second portion of the fin along the first direction, the first isolation structure having a width along the first direction, the first end of the first portion of the fin having a surface roughness;
a gate structure comprising a gate electrode over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin, wherein the gate structure has the width along the first direction, and wherein a center of the gate structure is spaced apart from a center of the first isolation structure by a pitch along the first direction; and
a second isolation structure over a second end of a first portion of the fin, the second end opposite the first end, the second isolation structure having the width along the first direction, and the second end of the first portion of the fin having a surface roughness less than the surface roughness of the first end of the first portion of the fin, wherein a center of the second isolation structure is spaced apart from the center of the gate structure by the pitch along the first direction.

US Pat. No. 10,460,988

REMOVAL METHOD AND PROCESSING METHOD

Tokyo Electron Limited, ...

1. A removal method for selectively removing a plurality of types of metal oxide films in a plurality of recesses formed in a substrate that is arranged in a processing chamber, the removal method comprising process steps of: exposing the plurality of types of metal oxide films to BCl3 gas or a BCl3 gas plasma generated by introducing BCl3 gas; stopping introduction of the BCl3 gas and performing a purge process; exposing the plurality of types of metal oxide films and a plurality of types of metal films underneath the plurality of types of metal oxide films to a plasma generated by introducing an inert gas; and stopping introduction of the inert gas and performing the purge process; wherein the process steps are repeated a plurality of times; and wherein the process step of exposing the plurality of types of metal oxide films and the plurality of types of metal films underneath the plurality of types of metal oxide films to the plasma includes performing a first process step of exposing the plurality of types of metal oxide films to one plasma generated from a single gas of the inert gas, and a second process step of exposing the plurality of types of metal films to two different plasmas each generated from a single gas selected from a plurality of types of gases including the inert gas.

US Pat. No. 10,460,974

WAFER PROCESSING METHOD AND ADHESIVE TAPE

Disco Corporation, Tokyo...

1. A wafer processing method for dividing a wafer into individual chips by applying to the wafer a laser beam having such a wavelength as to be absorbed in the wafer, the laser processing method comprising:an adhesive tape attaching step of attaching the wafer to an adhesive tape that emits plasma light different from plasma light emitted by the wafer upon application of a laser beam thereto;
a holding step of holding the adhesive tape side on a chuck table so as to expose the wafer, after performing the adhesive tape attaching step;
a dividing step of dividing the wafer while relatively moving the chuck table and the laser beam, after performing the holding step; and
a plasma light detection step of detecting plasma light generated at the time of the dividing step,
wherein in the plasma light detection step, complete division of the wafer is confirmed by detecting plasma light generated upon application of the laser beam to the adhesive tape.

US Pat. No. 10,460,963

PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing method of processing a processing target object, in which an organic film, a mask film and a resist film are stacked in sequence, by plasma, the plasma processing method comprising:a process of supplying a modifying gas, which is a H2 gas, a hydrogen halide gas, or a mixed gas containing a rare gas and a H2 gas or a hydrogen halide gas, into a chamber accommodating therein the processing target object in which a preset pattern is formed on the resist film;
a modifying process of modifying the resist film of the processing target object by plasma of the modifying gas at a processing temperature equal to or less than ?20° C.,
a process of supplying a first processing gas for etching into the chamber; and
a first etching process of etching the mask film with the resist film modified in the modifying process as a mask by plasma of the first processing gas at a processing temperature within a range from 0° C. to 40° C.

US Pat. No. 10,460,951

GAS REACTION TRAJECTORY CONTROL THROUGH TUNABLE PLASMA DISSOCIATION FOR WAFER BY-PRODUCT DISTRIBUTION AND ETCH FEATURE PROFILE UNIFORMITY

Lam Research Corporation,...

1. A method for delivering gases to a plasma processing chamber having a substrate support for supporting a substrate, a dielectric window disposed over the substrate support, a center region of the dielectric window includes a gas feed injector that has an inner feed and an outer feed that surrounds the inner feed, and an electrode is disposed over the dielectric window, the method comprising:convectively flowing a reactant gas into the plasma processing chamber via the inner feed of the gas feed injector;
diffusively flowing a tuning gas into the plasma processing chamber via the outer feed of the gas feed injector, the tuning gas having a different chemical composition than the reactant gas, the tuning gas is fed via the outer feed and into the plasma processing chamber at an angle that is away from the reactant gas that is fed via the inner feed and into the plasma processing chamber, wherein the angle causes a fraction of the tuning gas to flow toward the dielectric window that is under the electrode and wherein said reactant gas is flown separately into the plasma process chamber from the tuning gas;
providing radio frequency (RF) power to the electrode, wherein the fraction of the tuning gas that is diffusively flown into the plasma processing chamber is exposed to the RF power and dissociated before mixing with the reactant gas that is convectively flown into the plasma processing chamber, wherein the RF power is configured to ignite a plasma using a mixture of the tuning gas, the fraction of tuning gas that is dissociated, and the reactant gas; and
adjusting a rate of flow of one or both of the convectively flown reactant gas and the diffusively flown tuning gas to control etch uniformity across a surface of the substrate.

US Pat. No. 10,460,950

SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE PROCESSING METHOD

Tokyo Electron Limited, ...

1. A substrate processing system comprising:a memory including a program;
a processor configured to execute the program to operate the substrate processing system;
an etching apparatus configured to supply a gas containing fluorocarbon to generate plasma so as to perform an etching process on a film including silicon formed on a substrate, wherein the etching process is performed by using plasma through a mask formed on the film including silicon;
a film forming apparatus configured to supply a gas containing carbon so as to form a film including carbon on the etched film including silicon, wherein the film forming apparatus is provided separately from the etching apparatus;
the processor is configured to execute the program to cause the etching apparatus to perform:
a first etching step in which the film including silicon is partway etched by using plasma; and
a second etching step in which the film including silicon, on which the film including carbon is formed, is further etched by using plasma,
the processor is further configured to execute the program to cause the film forming apparatus to perform a film forming step in which the film including carbon is formed on the film including silicon on which the first etching step has been performed,
wherein the processor is configured to execute the program to cause the film forming apparatus to further perform a treatment process with any of a single gas of monosilane (SiH4) and a mixed gas containing monosilane after the film forming step and before the second etching step.

US Pat. No. 10,460,947

METHOD FOR POLISHING SILICON WAFER

SHIN-ETSU HANDOTAI CO., L...

1. A method for polishing a silicon wafer, the method comprising:recovering a used slurry containing polishing abrasive grains and obtained from a slurry that had been supplied to the silicon wafer and used for polishing; and
circulating and supplying the recovered used slurry to the silicon wafer to polish the silicon wafer, wherein
a mixed alkali solution containing
a chelating agent and
either or both of a pH adjuster and a polishing rate accelerator is added to the recovered used slurry without adding unused polishing abrasive grains, and the recovered used slurry is circulated and supplied to the silicon wafer to polish the silicon wafer,
and further comprising:
measuring a concentration of the chelating agent in the recovered used slurry by an absorbance measuring method when the used slurry is circulated and supplied;
quantifying the chelating agent in the used slurry based on a result of the measurement; and
setting a mixing condition of the chelating agent in the mixed alkali solution based on a result of the quantification such that the concentration of the chelating agent in the used slurry is kept constant.

US Pat. No. 10,460,940

MASK FORMATION BY SELECTIVELY REMOVING PORTIONS OF A LAYER THAT HAVE NOT BEEN IMPLANTED

Taiwan Semiconductor Manu...

1. A method for semiconductor processing, the method comprising:forming a dielectric layer over a substrate; and
forming a mask over the dielectric layer, forming the mask comprising:
depositing a first layer over the dielectric layer;
implanting in a first implant process a dopant species through a patterned material and into the first layer at a first energy;
after implanting in the first implant process, implanting in a second implant process the dopant species through the patterned material and into the first layer at a second energy greater than the first energy; and
forming mask portions of the mask comprising selectively removing portions of the first layer that are not implanted with the dopant species.

US Pat. No. 10,460,928

PROCESS FOR DEPOSITION OF TITANIUM OXYNITRIDE FOR USE IN INTEGRATED CIRCUIT FABRICATION

ASM IP Holding B.V., Alm...

1. A process for depositing a titanium oxynitride thin film comprising:contacting a substrate comprising silicon with a titanium reactant;
subsequently contacting the substrate with a second reactant comprising a plurality of reactive species generated by plasma, wherein the plurality of reactive species comprises nitrogen and oxygen; and
repeating the contacting steps until a titanium oxynitride thin film having a thickness of from about 1 nm to about 50 nm has been formed on the substrate, wherein the titanium oxynitride thin film is deposited at a temperature from 70° C. to 200° C.

US Pat. No. 10,460,919

AUTOMATED DETERMINATION OF MASS SPECTROMETER COLLISION ENERGY

THERMO FINNIGAN LLC, San...

1. A method for identifying an intact protein within a sample containing a plurality of intact proteins using a mass spectrometer, the method comprising:(a) introducing the sample to an ionization source of the mass spectrometer;
(b) using the ionization source, generating a plurality of ion species from the plurality of intact proteins, whereby each protein gives rise to a respective subset of the plurality of ion species, wherein each ion species of each subset is a multi-protonated ion species generated from a respective one of the intact proteins;
(c) performing a mass analysis of the plurality of ion species using a mass analyzer of the mass spectrometer;
(d) automatically recognizing each subset of the plurality of ion species and assigning a charge state, z, to each recognized ion species and a molecular weight, MW, to each intact protein by mathematical analysis of data generated by the mass analysis;
(e) selecting a one of the ion species;
(f) automatically calculating a collision energy, CE, to be employed for fragmentation of the selected ion species, using the relationship
CE(Dp)=c+(1/k)[ln(1/Dp)?1],where Dp is a portion of the selected ion species that is desired to remain unfragmented after the fragmentation and c and k are functions only the charge state, z, of the selected ion species and the molecular weight, MW, of the intact protein from which the selected ion species was generated;(g) isolating the selected ion species and fragmenting said species so as to form fragment ion species therefrom using the automatically calculated collision energy; and
(h) mass analyzing the fragment ion species.

US Pat. No. 10,460,909

CHARGED PARTICLE BEAM WRITING METHOD AND CHARGED PARTICLE BEAM WRITING APPARATUS

NuFlare Technology, Inc.,...

1. A charged particle beam writing method using a charged particle beam writing apparatus including an emitting unit, a current limiting aperture, a blanking deflector, a blanking aperture, and an electron lens, the emitting unit emitting a charged particle beam, the current limiting aperture being provided with an opening through which part of the charged particle beam passes, the blanking deflector switching between beam ON and beam OFF so as to control an irradiation time by deflecting the charged particle beam having passed through the current limiting aperture, the blanking aperture blocking the charged particle beam deflected by the blanking deflector in such a manner that the beam OFF state is entered, the electron lens being disposed between the current limiting aperture and the blanking aperture, the method comprising:substituting a lens value into a given function and calculating an offset time, the lens value being set for the electron lens;
adding the offset time to an irradiation time for writing a pattern, and correcting the irradiation time; and
switching between the beam ON and the beam OFF by using the blanking deflector based on the corrected irradiation time.

US Pat. No. 10,460,897

MAGNETIC TRIP DEVICE FOR CIRCUIT BREAKER

LSIS CO., LTD., Anyang-s...

1. A magnetic trip device for a circuit breaker, comprising:an actuator coil part that has a plunger configured to move to an advanced position or a retracted position according to the magnetization or demagnetization of a coil;
an output plate that is rotatably provided on the movement path of the plunger to rotate in a first direction by the pressing of the plunger;
a micro switch that has an operation lever portion protruding outwardly and is configured to output an electrical signal indicating a state of the circuit breaker according to whether or not the operation lever portion is pressed;
a switch driving lever mechanism that is configured to rotate to a first position for pressing the operation lever portion or a second position for releasing the operation lever portion so as to open or close the micro switch;
a driving lever bias spring that is provided at a predetermined position to elastically bias the switch driving lever mechanism to rotate to the second position;
an automatic reset mechanism that is configured to press the plunger of the actuator coil part to the retracted position in connection with a main switching shaft of the circuit breaker subsequent to a trip operation; and
a driving lever latch that is configured to rotate to a restraining position for preventing the switch driving lever mechanism from rotating to the first position so as to allow the micro switch to maintain a trip indicating state subsequent to a trip operation even when the plunger is moved to the retracted position by the automatic reset mechanism, and a release position for allowing the switch driving lever mechanism to rotate to the first position, and the driving lever latch is provided adjacent to the switch driving lever mechanism.

US Pat. No. 10,460,895

SAFETY SWITCHING DEVICE FOR FAIL-SAFELY DISCONNECTING AN ELECTRICAL LOAD

1. A safety switching device for fail-safely disconnecting an electrical load, comprising:an input part for receiving at least one safety-relevant input signal,
a logic part connected to the input part for processing the at least one safety-relevant input signal, and
an output part which comprises a relay coil and a first relay contact, a second relay contact, a third relay contact, and a fourth relay contact,
wherein the first and the second relay contacts are arranged electrically in series with one another,
wherein the third and the fourth relay contacts are arranged electrically in series with one another,
wherein the first and the third relay contacts are mechanically coupled to each other so as to form a first group of positively driven relay contacts,
wherein the second and the fourth relay contacts are mechanically coupled to each other so as to form a second group of positively driven relay contacts,
wherein the first and the third relay contacts can move mechanically separately from the second and the fourth relay contacts,
wherein the logic part is connected to the output part and redundantly controls the first group of positively driven relay contacts and the second group of positively driven relay contacts in order to selectively allow, or to interrupt in a fail-safe manner, a current flow to the electrical load, in response to the at least one safety-relevant input signal, and
wherein the relay coil comprises a single relay coil that is electromagnetically coupled to the first group and to the second group of positively driven relay contacts so that the logic part can control the first relay contact, the second relay contact, the third relay contact, and the fourth relay contact together via the single relay coil.

US Pat. No. 10,460,889

LOCKOUT DEVICE

1. A lockout device comprising a first unit and a second unit; the first unit comprising a hook portion, a middle portion, and a lock portion; said middle portion located between and directly connected to the hook portion and the lock portion; and the second unit comprising a support means and a locking means; the support means connected to the locking means; the locking means disposed substantially parallel to the middle portion of the first unit; a forward element of the locking means being substantially linear; and the locking means closing with the hook portion placing the lockout device in a locked position by holding together a lever lock point of an on/off switch lever and a stub lock point of an off stub of an electrical disconnect box.

US Pat. No. 10,460,879

PHOTOELECTRIC CONVERSION ELEMENT, DYE-SENSITIZED SOLAR CELL, METAL COMPLEX DYE, DYE SOLUTION, DYE-ADSORBED ELECTRODE, AND METHOD FOR PRODUCING DYE-SENSITIZED SOLAR CELL

FUJIFILM Corporation, To...

1. A photoelectric conversion element, comprising an electrically conductive support, a photoconductor layer containing an electrolyte, a charge transfer layer containing an electrolyte, and a counter electrode, wherein the photoconductor layer contains semiconductor fine particles carrying a metal complex dye represented by the following Formula (I):M(LA)(LD)(LX)mX·(CI)mY  formula (I)
wherein, in the formula, M represents a metal ion,
LA represents a tridentate ligand represented by the following Formula (AL),
LD represents a bidentate ligand or a tridentate ligand different from LA, in which, at least one of coordinating atoms which bond to the metal ion M in the bidentate ligand or the tridentate ligand is an anion,
LX represents a monodentate ligand; mX is 1 when LD is the bidentate ligand and mX is 0 when LD is the tridentate ligand;
CI represents a counter ion necessary for neutralizing an electric charge;
mY represents an integer of 0 to 3;

wherein, in the formula, the ring A, the ring B, and the ring C each independently represent a nitrogen-containing aromatic heterocyclic ring, herein, the bond between Z1 and the N atom and the bond between Z2 and the N atom may be a single bond or a double bond; Z1 and Z2 each independently represent a carbon atom or a nitrogen atom;
Anc1 to Anc3 each independently represent an acidic group; l1 and l3 each independently are an integer of 1 to 4, and l2 is an integer of 1 to 5, respectively;
X1 and X3 each independently represent a single bond or a linking group; each combinations of X1 and the ring A, and X3 and the ring C may bond to each other to form a fused ring; m1 and m3 each independently represent an integer of 0 to 4, and m2 represents an integer of 1 to 3;
X2 represents the following Formula (X-1):

wherein, in Formula (X-1), RX1 and RX2 are both a hydrogen atom; * represents a bonding position with the ring B, and ** represents a bonding position with Anc2;
R1 to R3 each independently represent a substituent that does not have any of Anc1 to Anc3; n1 and n2 each independently represent an integer of 0 to 3, and n3 represents an integer of 0 to 4; when a plurality of R1s, a plurality of R2s, or a plurality of R3 exist, each of these may bond with each other to form a ring.

US Pat. No. 10,460,878

MULTILAYER CAPACITOR

Palo Alto Research Center...

1. A capacitor device, comprising:a plurality of capacitors arranged into a shape, each capacitor of the plurality of capacitors having a first external electrode on a first side of the capacitor and a second external electrode on a second side of the capacitor opposing the first side;
a first plate proximate and electrically coupled to the first external electrodes of the capacitors; and
a second plate proximate and electrically coupled to the second external electrodes of the capacitors, each of the first plate and the second plate comprising:
a substrate comprising one of a semiconducting material and an insulating material, the substrate having a first side facing towards the first and second external electrodes and a second side facing away from the first and second external electrodes; and
a metal layer disposed on the first side of the substrate.

US Pat. No. 10,460,865

INDUCTOR ASSEMBLY

Ford Global Technologies,...

1. An inductor assembly comprising:a flat conductor;
a core having a pair of axially oriented elements, the elements including a post defining an axial aperture therethrough and more than two projections extending axially from a base, the projections being radially spaced from the post and angularly spaced apart to define openings between the projections and configured to receive and direct a splashed fluid toward the conductor disposed in a single layer over the post;
a pair of insulated bobbins, disposed between the conductor and the posts, each having radial flanges at an end configured to be received in the openings; and
a bolt extending through the aperture and fastened to a transmission.

US Pat. No. 10,460,863

PARALLEL DIPOLE LINE TRAP WITH VARIABLE GAP AND TUNABLE TRAP POTENTIAL

International Business Ma...

1. A parallel dipole line (PDL) trap, comprising:a pair of dipole line magnets separated from one another by a variable gap g;
a diamagnetic object levitating above the dipole line magnets, wherein the gap g is less than a critical gap gc beyond which the diamagnetic object is no longer levitated, and wherein the gap g determines a height by which the diamagnetic object levitates above the dipole line magnets; and
a fixed or a variable gap fixture in which the dipole line magnets are affixed to separate mounts, wherein each of the dipole line magnets is cylindrical, wherein the mounts only partially surround a circumference of each of the dipole line magnets such that the mounts are in a non-contact position with the dipole line magnets at a center of the PDL trap in between the dipole line magnets, and wherein the mounts are affixed only to ends of each of the dipole line magnets and only partially surround the circumference of each of the dipole line magnets at the ends of each of the dipole line magnets.

US Pat. No. 10,460,857

SKIN BUTTON WITH FLAT CABLE

HeartWare, Inc., Miami L...

1. A method of forming a percutaneous connector assembly, comprising:assembling a plurality of conductors adjacent to each other, each of the plurality of conductors defining a length;
coupling a portion of the plurality of conductors to each other along the length to define a flat portion of a cable assembly;
rearranging a free length of each of the plurality of conductors to define a round portion of the cable assembly, the round portion being opposite the flat portion of the cable assembly;
applying a jacket over the round portion of the cable assembly;
connecting the cable assembly to a feedthrough assembly; and
coupling a skirt to a body of the feedthrough assembly, the skirt extending radially outwardly therefrom.

US Pat. No. 10,460,855

FLEXIBLE FLAT ROUND CONDUCTIVE CABLE AND SEGMENTAL CALENDERING DEVICE FOR FLEXIBLE FLAT CABLE

1. A flexible flat round cable, comprising:a plurality of cables, including:
a plurality of round regions each having a first distance with a first electrical clearance between every two neighboring cables therein; and
a plurality of flat regions each having a second distance with a second electrical clearance between every two neighboring cables, wherein the first distance and the second distance are different, and the first electrical clearance is greater than the second electrical clearance;
wherein the plurality of cables are parallelly arranged, and an insulation film is disposed on a surface of the plurality of cables; and
wherein the plurality of flat and round regions are alternately arranged in form of one by one cycle in longitudinal direction, and the plurality of flat regions are molded by a segmental calendering device through a sub rolling method.

US Pat. No. 10,460,854

SUPERCONDUCTING WIRE

Sumitomo Electric Industr...

1. A superconducting wire comprising:a multilayer stack including a substrate having a main surface, and a superconducting material layer formed on the main surface; and
a covering layer disposed on at least the superconducting material layer,
the covering layer located on the superconducting material layer having a front surface portion in a concave shape.

US Pat. No. 10,460,848

DEVICE FOR SUSPENDING AN X-RAY GRID, ARRANGEMENT WITH AN X-RAY GRID AND METHOD FOR OPERATING AN X-RAY GRID

Siemens Healthcare GmbH, ...

1. A device for suspending an x-ray grid, the device comprising:a first rotating frame configured to support the x-ray grid therein or thereon; and
two first flexible hinge elements connected to said first rotating frame and mounting said first rotating frame for reversible rotation about a first axis.

US Pat. No. 10,460,846

EXAMINATION AND TEST SYSTEM FOR NUCLEAR-GRADE CONTROL VALVE

Institute of Nuclear Ener...

1. An examination and test system for nuclear-grade control valve, used for examining and testing a control valve, said control valve comprising a valve base, a valve rod, and a driving unit, said valve base including a communicating opening therein, said valve rod including a valve plug capable of closing said communication opening, said valve rod being movable by said driving unit, said valve plug blocking said communicating opening and forming openness of various degrees according to the traveling distance of said valve rod, the examination and test system comprising:a hermetic first chamber, including a second chamber with controllable ambient conditions including at least one of temperature, pressure and humidity, and said second chamber used for accommodating said control valve;
a base, disposed outside said hermetic first chamber;
a guide unit, disposed on at least one of said control valve and said base;
a winder, disposed on said base;
a steel cable, connected with said valve rod at one end and extending out of said hermetic first chamber to connect with said winder at the other end, wound on said guide unit, wound up by said winder, and rendered taut at any time; and
a length measurement device, disposed on said base, and including a body and a measurement element, said measurement element movable with respect to said body and coupled to said steel cable, and said length measurement device displaying the displacement of said measurement element relative to said body.

US Pat. No. 10,460,843

PROBABILISTIC PARAMETER ESTIMATION USING FUSED DATA APPARATUS AND METHOD OF USE THEREOF

1. A method for estimating state of a biomedical system, comprising the steps of: providing a cardiac stroke volume analyzer, said cardiac stroke volume analyzer comprising a system processor, said cardiac stroke volume analyzer further comprising: a probabilistic processor; and a dynamic state-space model; connecting said system processor to: (1) an auxiliary blood pressure cuff medical device and (2) an auxiliary pulse oximeter medical device; said cardiac stroke volume analyzer receiving discrete first cardiovascular input data, from said auxiliary blood pressure cuff medical device, related to a first sub-system of the biomedical system; said cardiac stroke volume analyzer receiving discrete second cardiovascular input data, from said auxiliary pulse oximeter medical device, related to a second sub-system of the biomedical system, fusing the first input data and the second input data into fused data using said system processor, said step of fusing comprising the step of said probabilistic processor converting the fused data into a probability distribution function indirectly related to an output of either of the blood pressure cuff and the pulse oximeter medical device; at least one probabilistic model, of said dynamic state-space model, operating on said probability distribution function, iteratively circulating said probability distribution function in said dynamic state-space model in synchronization with receipt of at least one of: updated first cardiovascular input data from said auxiliary blood pressure cuff medical device; and updated second cardiovascular input data from said pulse oximeter medical device; and said system processor processing the probability distribution function to generate an output related to the state of the biomedical system, said output comprising a left ventricle stroke volume of a heart of a patient and arterial compliance of the patient, said output displayed to at least one of a patient and a doctor.

US Pat. No. 10,460,840

DIAGNOSTICS-BASED HUMAN HEALTH EVALUATION

JIANGSU HUABEN HEALTH LIF...

1. A method of evaluating a health condition of a patient based on a diagnostic aspect of the patient, comprising:obtaining, by a diagnostics measurement device, a measurement value of the diagnostic aspect of the patient;
calculating, by a processor communicatively coupled to the diagnostics measurement device, a relative ratio by dividing the measurement value by a standard average value of the diagnostic aspect;
calculating, by the processor, a health deviation by subtracting a baseline value from the relative ratio; and
designating, by the processor, a health indicator based on the health deviation, the health indicator indicating the health condition of the patient,
wherein:
the diagnostics measurement device comprises a blood test device,
the measurement value is a result of a blood test performed by the blood test device on the patient,
the standard average value comprises an arithmetic mean of a standard upper limit and a standard lower limit that are medically defined for the diagnostic aspect,
the baseline value comprises an arithmetic sum of a medium value, a variation upper limit, a variation lower limit, and a tier size, and
the health indicator is a rounded integer of a ratio of the health deviation to the tier size.

US Pat. No. 10,460,836

MEDICAL DEVICE SYSTEM AND METHOD FOR ESTABLISHING WIRELESS COMMUNICATION

1. A system for establishing wireless communication between at least one medical device having a predefined unique identification (ID) and at least one communication unit having a primary two-way wireless data communication interface, the system comprising:means for wirelessly performing primary two-way data communication including receiving and transmitting information between the medical device and the communication unit;
secondary one-way wireless communication means for communicating the predefined unique identification (ID) of the medical device through the secondary one-way wireless communication, wherein the secondary one-way wireless communication means includes means for non-encrypted wireless communication, and the means for wirelessly performing primary two-way data communication comprises an encrypted secure primary two-way wireless data communication interface;
means for ensuring that the primary two-way wireless data communication can be carried out if and only if the communication unit positively and in advance has identified the predefined unique identification (ID) of the medical device;
wherein the medical device comprises an activation member that is configured to be triggered by mechanical activation of the activation member, and secondary communication means for sending at least one signal to the communication unit upon the activation member being triggered, wherein the secondary one-way wireless communication means is for sending the at least one signal in real time, whereby the medical device is activated and sends at least one response signal to the secondary one-way wireless communication means to determine said predefined unique identification of the medical device; and
wherein the communication unit comprises means for providing interactive training of a user of the medical device on a real-time basis.

US Pat. No. 10,460,826

TEST METHODS OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS USED THEREIN

SK hynix Inc., Icheon-si...

1. A semiconductor system comprising:a medium controller configured to output an address that is sequentially counted in a test mode, configured to sense levels of data corresponding to the address in the test mode to determine if the data has a row error or a chip error, and configured to change a combination of a host address to generate and store a spare address if a combination of the address corresponds to the chip error in the test mode; and
a semiconductor module configured to include a plurality of semiconductor devices,
wherein each of the semiconductor devices comprises a spare area and a redundancy area,
wherein the semiconductor module repairs the address to output the data from the redundancy area of a chip if a combination of the address corresponds to the row error, and
wherein the semiconductor module outputs the data from the spare area selected by the spare address of the chip if a combination of the address corresponds to the chip error,
wherein the row error corresponds to an error which occurs in any one of the plurality of semiconductor devices; and
wherein the chip error corresponds to an error which occurs in at least two of the plurality of semiconductor devices.

US Pat. No. 10,460,822

MEMORY WITH A CONTROLLABLE I/O FUNCTIONAL UNIT

ARM Limited, Cambridge (...

1. A circuit comprising:a controller;
a clock generator;
a bitcell array comprising a plurality of bitlines; and
a first I/O functional unit comprising:
a first multiplexer having an output port, wherein depending upon the controller, the first multiplexer selects a first input port or selects a first bitline input port that is coupled to a first bitline among a first group of bitlines in the plurality of bitlines;
a first latch having an input port and an output port, wherein the input port of the first latch is coupled to the output port of the first multiplexer, and wherein the first latch is clocked by the clock generator to latch the output port of the first multiplexer;
a second multiplexer having an output port, wherein depending upon the controller, the second multiplexer selects a second input port or selects a second bitline input port that is coupled to a second bitline among a second group of bitlines in the plurality of bitlines, wherein the second input port is coupled to the output port of the first latch; and
a second latch having an input port and an output port, wherein the input port of the second latch is coupled to the output port of the second multiplexer, and wherein the second latch is clocked by the clock generator to latch the output port of the second multiplexer, and wherein the first multiplexer, the first latch, the second multiplexer, and the second latch are coupled together in series.

US Pat. No. 10,460,820

HIGH-SPEED TRACK-AND-HOLD DEVICE USING RF LINEARIZATION TECHNIQUE

INDUSTRY-ACADEMIC COOPERA...

1. A high-speed track-and-hold device, comprising:a buffer stage circuit comprising a PMOS source follower and a post linear circuit; and
a sampling stage circuit that is responsible for supplying a source voltage (VSS) to the buffer stage circuit and that is arranged so that a switch connected to a gate is connected to the source voltage (VSS) and a NMOS transistor of a sampling stage is turned off in hold operation.

US Pat. No. 10,460,809

MEMORY SYSTEM AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. An operating method of a memory system that includes a plural-level cell memory block capable of storing N-bit data in a single memory cell, comprising:accessing a plural-level cell memory block in an N-bit cell mode;
determining a degree of disturbance of the plural-level cell memory block;
designating one or more memory cells in an erase state included in an open memory area of the plural-level cell memory block as an M-bit group, where M is an integer smaller than N, according to a result of the determination; and
accessing the M-bit group in an M-bit cell mode.

US Pat. No. 10,460,808

MEMORY DEVICE AND PROGRAMMING OPERATION METHOD THEREOF WITH DIFFERENT BIT LINE VOLTAGES

MACRONIX INTERNATIONAL CO...

1. An operation method for a memory device having a memory array including a plurality of memory cells, a plurality of word lines and a plurality of bit lines, the operation method for the memory device including:applying a program voltage to at least a selected word line of the word lines; and
during a high level period of the program voltage, based on respective locations of a plurality of selected bit lines of the bit lines on the word lines, generating and applying a plurality of different bit line voltages to the selected bit lines; the plurality of different bit line voltages generated and applied to the selected bit lines have different rising edges; and in generating the different bit line voltages, the bit line voltage having an earliest rising edge and a highest bit line voltage is generated for applying to a plurality of first selected bit lines of the selected bit lines, which are closest to a head of the word lines, and the plurality of the different bit line voltages are not corresponding to the program voltage.

US Pat. No. 10,460,802

APPARATUSES AND METHODS FOR EFFICIENT WRITE IN A CROSS-POINT ARRAY

Ovonyx Memory Technology,...

9. An apparatus, comprising:a memory cell having a first node and a second node;
a first voltage source;
a second voltage source different than the first voltage source; and
a circuit configured to:
bias the first node of the memory cell using the first voltage source;
detect, while the first node is biased using the first voltage source, a transition of the memory cell from a first state to a second state that has a lower resistance than the first state; and
access the memory cell based at least in part on the detected transition, wherein the accessing comprises biasing the first node of the memory cell using the second voltage source.

US Pat. No. 10,460,801

MULTI-LEVEL PHASE CHANGE DEVICE

WESTERN DIGITAL TECHNOLOG...

1. A method for programming a memory cell, comprising:changing the memory cell to a first resistance state by providing a first voltage to the memory cell; and
changing the memory cell to a second resistance state by providing a second voltage to the memory cell, wherein the memory cell comprises a first phase change material layer separated from a second phase change material layer by a diffusion barrier layer wherein at least one of the first phase change material layer and the second phase change material layer comprises any of selenium tellurium (SeTe), silicon tellurium (SiTe), antimony selenide (SbSe), tin selenide (SnSe), tin tellurium (SnTe), tin antimony (SnSb), germanium antimony (GeSb) and silicon antimony (SiSb), wherein the first phase change material layer and the second phase change material layer comprise different alloys of the same phase change material, wherein altering a resistance state of the memory cell through application of the first voltage comprises setting the memory cell to a first resistance state, and altering the resistance state of the memory cell through application of the second voltage comprises transitioning the memory cell from the first resistance state to a second resistance state.

US Pat. No. 10,460,800

DATA SENSING IN CROSSPOINT MEMORY STRUCTURES

Hewlett Packard Enterpris...

1. A data storage device, comprisinga memory cell array; and
sense circuitry to detect a data value stored to a memory cell of the memory cell array;
the controller to bias the sense circuitry during a read phase of a write operation;
wherein:
the sense circuitry is to sample a sneak current and subtract the sneak current from the current measured through the memory cell; and
to bias the sense circuitry, the sneak current is further increased or decreased compared the sampled sneak current.

US Pat. No. 10,460,798

MEMORY CELLS HAVING A PLURALITY OF RESISTANCE VARIABLE MATERIALS

Micron Technology, Inc., ...

1. A method of forming memory cells, the method comprising:forming a first plug material and a second plug material;
forming a material stack on a portion of the first plug material and a portion of the second plug material, wherein the material stack includes a plurality of resistance variable materials separated by respective dielectric materials;
forming a first conductive material on the first plug material, the first conductive material serving as a first conductive contact for the plurality of resistance variable materials of a first memory cell;
forming a second conductive material that serves as a second conductive contact for the plurality of resistance variable materials of both the first memory cell and an adjacent memory cell and is separated from the first plug material by a dielectric material, wherein the second conductive material is formed subsequent to forming the first conductive material; and
forming a third conductive material on the second plug material, the third conductive material serving as a first conductive contact for the plurality of resistance variable materials of the adjacent memory cell.

US Pat. No. 10,460,789

METHODS OF READING AND WRITING DATA IN A THYRISTOR RANDOM ACCESS MEMORY

TC Lab, Inc., Gilroy, CA...

1. A method of operating a volatile memory array having anodes coupled to anode lines and having cathodes coupled to cathode lines, the method to program a selected thyristor ‘on’ comprising performing steps of:applying to the anode line to which the selected thyristor is connected a positive potential;
applying to the cathode line to which the selected thyristor is connected a lower potential, the difference between the positive potential and the lower potential being greater than a potential difference to turn on the thyristor;
applying to the anode lines to which all other thyristors except the selected thyristor are connected a first potential;
applying to the cathode lines to which all thyristors other than the selected thyristor are connected a second potential, the difference between the first potential and the second potential being smaller than a potential difference to turn on or off any of the non-selected thyristors.

US Pat. No. 10,460,785

PARALLEL WRITE SCHEME UTILIZING SPIN HALL EFFECT-ASSISTED SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY

QUALCOMM Incorporated, S...

1. An apparatus comprising:a magnetoresistive random access memory (MRAM), comprising:
a heavy metal layer coupled to a source line; and
a plurality of bit cells coupled to a word line, and a plurality of bit lines, and the heavy metal layer, such that the heavy metal layer is a continuous layer coupling the bit cells to the source line, wherein each of the bit cells comprises a magnetic tunnel junction (MTJ) and a transistor, a gate of the transistor being coupled to the word line, and at least one of a source or a drain of the transistor being coupled to the MTJ or at least one of the bit lines; and
a controller coupled to the MRAM and configured to:
apply a first voltage to at least a portion of the heavy metal layer and a second voltage lower than the first voltage at another portion of the heavy metal layer during a first phase; and
apply a third voltage to the heavy metal layer during a second phase, the third voltage being between the first voltage and the second voltage.

US Pat. No. 10,460,784

MAGNETIC MEMORY AND MEMORY SYSTEM

Kabushiki Kaisha Toshiba,...

1. A magnetic memory comprising:a memory cell including a first magnetoresistive effect element;
a reference circuit including a second magnetoresistive effect element having a first resistance state and a third magnetoresistive effect element having a second resistance state; and
a read circuit configured to read data in the memory cell based on a first signal based on an output from the memory cell and a second signal based on an output from the reference circuit,
wherein at a time of reading of the data,
a first voltage is applied to the first magnetoresistive effect element, and
a second voltage higher than the first voltage is applied to the second magnetoresistive effect element and the third magnetoresistive effect element.

US Pat. No. 10,460,776

SEMICONDUCTOR MEMORY DEVICE AND READING METHOD FOR THE SAME

WINBOND ELECTRONICS CORP....

1. A semiconductor memory device comprising:a column selection circuit selecting n-bit data from data read from a memory cell array according to a column selection signal and outputting the selected n-bit data to an n-bit data bus;
a sensing circuit sensing the n-bit data on the n-bit data bus in response to an activation signal;
an output circuit selecting m-bit data from the n-bit data sensed by the sensing circuit in response to an internal clock signal synchronized with a serial clock signal applied from outside and outputting the selected m-bit data from output terminals; and
a verification circuit comparing the data n-bit sensed by the sensing circuit with the m-bit data output by the output circuit to verify correctness of read-out data,
wherein m is an integer which is equal to 1 or larger than 1 and n?m, and the internal clock signal having n/m cycles is generated in one cycle of the activation signal.

US Pat. No. 10,460,770

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a substrate;
a control circuit on the substrate, the control circuit comprising a transistor;
a first pad region comprising a pad above the substrate;
n (n is a natural number equal to or larger than 3) interconnect layers above the substrate, the n interconnect layers being located at different levels from the substrate, each of the n interconnect layers comprising an interconnect; and
a first interconnect region between an end of the control circuit and an end of the substrate in a direction of a first axis beside the first pad region in a direction of a second axis, the first interconnect region comprising no transistor, the first interconnect region comprising no contact coupled to the substrate, and the first interconnect region comprising an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.

US Pat. No. 10,460,761

DEFECT REGISTRATION METHOD

Kabushiki Kaisha Toshiba,...

1. A defect registration method comprising:measuring, on a unit-area basis, performance of a storage area of a magnetic disk including a plurality of unit areas, the storage area including a redundant area of a set capacity;
performing first extracting of unit areas up to the set capacity from the plurality of unit areas; and
registering the extracted unit areas of the set capacity as defect locations, wherein
the first extracting includes second extracting one or more unit areas in order of increasing the performance.

US Pat. No. 10,460,755

PERPENDICULAR RECORDING MEDIUM WITH OXIDE GRADIENT LAYER

Seagate Technology LLC, ...

1. An apparatus comprising:a substrate;
a recording layer supported by the substrate and comprising a granular magnetic recording layer, a continuous magnetic recording layer, and an oxide gradient layer, the granular magnetic recording layer comprising a first material having a first oxide content, and the oxide gradient layer disposed between the respective granular magnetic recording layer and the continuous magnetic recording layer, the oxide gradient layer comprising a third material having a second oxide content that is greater than zero and less than the first oxide content; and
a non-magnetic grain boundary continuously extending from the granular magnetic recording layer through the oxide gradient layer into, but not completely through, the continuous magnetic recording layer, the continuous magnetic recording layer comprising a second material having nominally no oxide content other than the non-magnetic grain boundary.

US Pat. No. 10,460,745

AUDIO CONTENT SEGMENTATION METHOD AND APPARATUS

HUAWEI TECHNOLOGIES CO., ...

1. A method implemented by a server for segmenting audio content, the method comprising:receiving, by the server, a segmentation location message from a user equipment (UE), wherein the segmentation location message includes at least one piece of first segmentation location information of audio content and an audio identifier of the audio content, wherein the at least one piece of first segmentation location information indicates a selected time piece of the audio content;
identifying, by the server and based on the audio identifier of the audio content, at least one piece of second segmentation location information having an audio identifier that matches the audio identifier of the audio content;
determining, by the server, at least one piece of target segmentation location information based on the at least one piece of first segmentation location information;
determining, by the server, at least one piece of reference segmentation location information based on the at least one piece of first segmentation location information and the at least one piece of second segmentation location information;
if a difference between a quantity of each piece of target segmentation location information of the at least one piece of target segmentation location information and a quantity of corresponding reference segmentation location information is less than a first preset value, determining, by the server, at least one piece of third segmentation location information based on the at least one piece of target segmentation location information and the reference segmentation location information corresponding to each piece of target segmentation location information; and
sending, by the server, a segmentation location recommendation message to the UE, wherein the segmentation location recommendation message includes the audio identifier of the audio content and the at least one piece of third segmentation location information, wherein:
the segmentation location recommendation message further includes weight information corresponding to the at least one piece of third segmentation location information,
the weight information is used to indicate a priority of the at least one piece of third segmentation location information, and
the priority of the at least one piece of third segmentation location information indicates a closeness of the at least one piece of third segmentation location information to the at least one piece of first segmentation location information.

US Pat. No. 10,460,740

METHODS AND APPARATUS FOR ADJUSTING A LEVEL OF AN AUDIO SIGNAL

Dolby Laboratories Licens...

1. A method performed in an audio decoder for reconstructing N audio channels from an audio signal having M audio channels, the method comprising:receiving a bitstream containing the M audio channels and a set of spatial parameters, wherein the set of spatial parameters includes an amplitude parameter, a correlation parameter, wherein the amplitude parameter is differentially encoded across time;
decoding the M encoded audio channels, wherein each audio channel is divided into a plurality of frequency bands, and each frequency band includes one or more spectral components;
extracting the set of spatial parameters from the bitstream;
applying a differential decoding process across time to the differentially encoded amplitude parameter to obtain a differentially decoded amplitude parameter;
analyzing the M audio channels to detect a location of a transient, wherein the location of the transient is detected based on a filtering operation;
decorrelating the M audio channels to obtain a decorrelated version of the M audio channels, wherein a first decorrelation technique is applied to a first subset of the plurality of frequency bands of each audio channel and a second decorrelation technique is applied to a second subset of the plurality of frequency bands of each audio channel;
deriving N audio channels from the M audio channels, the decorrelated version of the M audio channels, and the set of spatial parameters, wherein N is two or more, M is one or more, and M is less than N; and
synthesizing, by an audio reproduction device, the N audio channels as an output audio signal,
wherein both the analyzing and the decorrelating are performed in a frequency domain, the first decorrelation technique represents a first mode of operation of a decorrelator, the second decorrelation technique represents a second mode of operation of the decorrelator, and the audio decoder is implemented at least in part in hardware.

US Pat. No. 10,460,739

POST-QUANTIZATION GAIN CORRECTION IN AUDIO CODING

TELEFONAKTIEBOLAGET LM ER...

1. A gain adjustment method, performed by a gain adjustment apparatus, in decoding an audio signal that has been encoded with separate gain and shape representations, said method comprising:estimating an accuracy measure of the shape representation for a frequency band of the audio signal, wherein the shape representation encodes a shape vector comprising coefficients of the audio signal for the frequency band, and wherein the shape vector has been encoded using a pulse vector coding scheme where pulses may be added on top of each other to form pulses of different height, and the accuracy measure is based on the number of pulses used for encoding the shape vector and a height of the maximum pulse in the shape representation;
determining, based on the estimated accuracy measure, a gain correction; and
adjusting the gain representation for the frequency band based on the determined gain correction.

US Pat. No. 10,460,738

ENCODING APPARATUS FOR PROCESSING AN INPUT SIGNAL AND DECODING APPARATUS FOR PROCESSING AN ENCODED SIGNAL

Fraunhofer-Gesellschaft z...

1. An encoding apparatus for processing an input signal, comprising:a perceptual weighter; and
a quantizer,
wherein the perceptual weighter comprises a model provider and a model applicator, wherein the model provider is configured for providing a perceptually weighted model based on the input signal, and wherein the model applicator is configured for providing a perceptually weighted spectrum by applying the perceptually weighted model to a spectrum based on the input signal, and
wherein the quantizer is configured to quantize the perceptually weighted spectrum and for providing a bitstream, wherein the quantizer comprises a random matrix applicator and a sign function calculator, wherein the random matrix applicator is configured for applying a random matrix to the perceptually weighted spectrum in order to provide a transformed spectrum, and wherein the sign function calculator is configured for calculating a sign function of components of the transformed spectrum in order to provide the bitstream.

US Pat. No. 10,460,736

METHOD AND APPARATUS FOR RESTORING AUDIO SIGNAL

SAMSUNG ELECTRONICS CO., ...

9. A method of extending a bandwidth of an audio signal, the method comprising:extending an audio signal of a first bandwidth to an audio signal of a second bandwidth;
determining a ratio between a first frequency value and a second frequency value if an audio signal of the second frequency value included in the second bandwidth is reconstructed based on an audio signal of the first frequency value in the first bandwidth;
determining a phase shift amount in preset unit of time with respect to the second frequency value, based on the determined ratio; and
adjusting a phase with respect to the second frequency value, based on the determined phase shift amount.

US Pat. No. 10,460,730

ANNOUNCEMENT SIGNALING ON BOARD AN AIRCRAFT

AIRBUS OPERATIONS GMBH, ...

1. A method of signaling speech signal related text messages on board an aircraft, wherein the method comprises:providing a speech signal related to an announcement to passengers of the aircraft;
obtaining a text message containing text corresponding to spoken words of the speech signal by applying speech recognition to the speech signal;
determining one or more mobile devices to which the text message is to be signaled as recipients of the text message; and
signaling the text message to the one or more mobile devices determined as the recipients of the text message on board the aircraft by transmitting the text message in multicast,
wherein the step of determining the one or more mobile devices comprises
determining one or more of the mobile devices on which a respective application is installed;
wherein the method is carried out by an apparatus on board the aircraft; and
wherein said providing a speech signal comprises generating the speech signal in real time on board the aircraft;
wherein the one or more mobile devices determined as the recipients of the text message are brought on board the aircraft by the passengers of the aircraft,
wherein the method comprises detecting a preferred language for each of the one or more mobile devices determined as recipients of the text message based on information related to the respective mobile device and the step of signaling comprises transmitting the text message containing text in the detected preferred language;
wherein said information related to the respective mobile device that is used to detect the preferred language comprises at least one of:
information about a Subscriber Identity Module, SIM, card of the respective mobile device;
information about a telephone number of the respective mobile device; or
information about an operating system running on the respective mobile device.

US Pat. No. 10,460,720

GENERATION OF LANGUAGE UNDERSTANDING SYSTEMS AND METHODS

MICROSOFT TECHNOLOGY LICE...

1. A method for providing language understanding on a computer, comprising:receiving an utterance;
building, by the computer, two separate models in isolation from one another, the building of the two separate models comprising:
building a user intent detection model based on a user intent determined from the received utterance, the user intent detection model for determining a user intent in a subsequent utterance, wherein the user intent detection model is updateable via interactive learning to identify an unlabeled user intent associated with functionality within an associated application;
building an entity extraction model based on one or more language entities determined from the received utterance, the entity extraction model for determining one or more language entities in the subsequent utterance, wherein the entity extraction model is updateable via interactive learning to identify unlabeled language entities associated with functionality within the associated application;
automatically generating labeling for the user intent and the one or more language entities determined from the received utterance;
building a function call for calling a function in the associated application from the automatically generated labeling;
wherein in response to receiving the subsequent utterance:
the user intent detection model and the entity extraction model are applied against the subsequent utterance to identify, based on the automatically generated labeling for the subsequent utterance, the function call;
the function call is passed to the associated application to execute the function on the computer; and
the function is executed by the associated application on the computer.

US Pat. No. 10,460,718

AMBIENT NOISE REDUCTION ARRANGEMENTS

Cirrus Logic, Inc., Aust...

1. An ambient noise reducing system comprising:an earphone housing, comprising a circular outer rim;
a loudspeaker, wherein the loudspeaker is supported within said housing, and wherein the housing has an outlet port for sound generated by the loudspeaker;
a plurality of microphones, each microphone having a respective microphone inlet port in the circular outer rim of the housing surrounding the loudspeaker outlet port, such that said microphones are positioned to sense ambient noise approaching said housing from different respective directions; and
feedforward noise cancellation circuitry for passing the electrical signals generated by said plurality of microphones in parallel to an amplifier to form a summed electrical signal, and applying the summed electrical signal to said loudspeaker to generate an acoustic signal,
wherein a system response time is defined as a sum of an intrinsic response time of the loudspeaker and a propagation time of said acoustical signal from the loudspeaker to an eardrum of a listener having the earphone housing close to an ear, and
wherein said system response time is matched to a time taken for said ambient noise to travel from one of said microphones to the eardrum of the listener to achieve noise cancellation at the eardrum of the listener.

US Pat. No. 10,460,713

ACOUSTIC WAVE CLOAKING METHOD AND DEVICE CONSIDERING GENERALIZED TIME DEPENDENCY

University of Seoul Indus...

1. A method of cloaking an acoustic wave, comprising:transforming an acoustic propagation mathematical model, predetermined for propagation of an acoustic wave, into an acoustic wave cloaking mathematical model corresponding to an electromagnetic wave mathematical model predetermined for an electromagnetic wave and including a time variable for time dependency in a 4D coordinate system, based on a correlation between the acoustic propagation mathematical model and the electromagnetic wave mathematical model;
obtaining a target characteristic of a meta-material by using the acoustic wave cloaking mathematical model; and
blocking a region including a target object, from an acoustic wave by disposing the meta-material having the obtained target characteristic to surround the region,
wherein a target characteristic of the meta-material is calculated based on a space-time meta-material analysis based on the General Theory of the Relativity,
wherein an empty space of a physical space corresponding to the target region to be hidden with the target object is transformed into a virtual space that has a point the empty space of the physical space is transformed thereto, so that the empty space of the physical space is hidden from external acoustic waves, and
where the transformation of the physical space into the virtual space is obtained using covariant Maxwell's equations based on the General Theory of the Relativity, and using a coordinate transformation equation according to a spatial topology of the target region and the meta-material.