US Pat. No. 10,340,946

ENCODERS, DECODERS, AND METHODS

Gurulogic Microsystems Oy...

1. An encoder including data processing hardware for encoding input data to generate corresponding encoded data, characterized in that the encoder is operable to process at least one sequence of elements in the input data, wherein:(i) the elements have corresponding symbols;
(ii) the at least one sequence of elements is processed from a first element thereof to a last element thereof;
(iii) the encoder is operable to compute probabilities of symbols present in the at least one sequence of elements, wherein the probabilities of the symbols are computed whilst disregarding those elements of the at least one sequence that have already been encoded into the encoded data, and wherein the probabilities of the symbols used by the encoder for generating the encoded data are adaptively changed as the at least one sequence of elements is progressively encoded into the encoded data; and
(iv) the encoder is operable to deliver information describing the probabilities of the symbols.

US Pat. No. 10,340,945

MEMORY COMPRESSION METHOD AND APPARATUS

iDensify LLC, Austin, TX...

1. A method comprising:receiving at least one first integer from an input stream;
storing the at least one first integer as a temporary integer;
generating a list equal to a temporary ordered list of integers concatenated with the temporary integer;
determine that the list is in a dictionary;
setting the temporary ordered list of integers to the list;
representing the at least one first integer as at least one first token using a uniquely decodable coding technique; and
transmitting the at least one first token.

US Pat. No. 10,340,944

FLOATING-POINT ADDER, SEMICONDUCTOR DEVICE, AND CONTROL METHOD FOR FLOATING-POINT ADDER

Renesas Electronics Corpo...

1. An image recognition device that acquires image information of an image including an object to be recognized, executes recognition processing to recognize the object from a plurality of feature vectors of the image information, wherein the plurality of feature vectors is represented by floating-point numbers, the image recognition device comprising:a floating point adder that includes:
a first register that stores a first fixed-point number having a first predetermined number of digits;
a first conversion unit configured to convert an input first floating-point number into a second fixed-point number having the first predetermined number of digits;
a second register that stores the second fixed-point number;
an adder that is connected to the first register and the second register as inputs of the adder, is further connected to the first register as output of the adder, adds the second fixed-point number stored in the second register and the first fixed-point number stored in the first register, and stores the output of the adder in the first register to accumulate a plurality of floating point numbers, the input first floating-point number being accumulated as one of the plurality of floating point numbers; and
a second conversion unit configured to convert the first fixed-point number stored in the first register into a second floating-point number and output the second floating-point number,
wherein the first conversion unit is further configured to convert a mantissa part of the input first floating-point number into a signed third fixed-point number, and sign-extend the signed third fixed-point number into the first predetermined number of digits,
wherein a first left shifter of the first conversion unit is configured to shift the sign-extended third fixed-point number to the left by a number of bits corresponding to a value of an exponent part of the input first floating-point number, and output the shifted third fixed-point number as the second fixed-point number, and
wherein the first predetermined number of digits is a total value of a number of digits of a sign part of the input first floating-point number, a number of digits of the mantissa part of the input first floating-point number, and a number of bits corresponding to the value of the exponent part of the input first floating-point number.

US Pat. No. 10,340,943

DATA CONVERSION APPARATUS AND METHOD

SK hynix Inc., Gyeonggi-...

1. A data conversion apparatus comprising:a receiver suitable for receiving input data; and
a controller suitable for selectively converting the input data based on a distribution of a preset bit value included in the input data, and outputting any one of the input data and the converted data as output data, the converted data having a smaller size than the input data.

US Pat. No. 10,340,942

DEVICE FOR GENERATING ANALOGUE SIGNALS AND ASSOCIATED USE

THALES, Courbevoie (FR) ...

1. An analog signals generating device comprising a current pump controlled by a digital control code generated by a module for calculating the digital code with shaping of noise, said module for calculating the digital code with shaping of noise comprising at least one quantizer and receiving as input a digital signal representative of the analog signal to be generated,said device wherein said module for calculating the digital code with shaping of noise comprises a quantization error compensating stage,
and wherein said current pump comprises:
a first and a second group of at least one electric current generator, each generator of the first group being complementary to a generator of the second group, two complementary generators delivering currents of opposite amplitude
a differential amplifier exhibiting a predominantly capacitive input impedance,
a first and a second group of at least one switching means, the first group of switching means independently directing the electric current delivered by each generator of the first group of at least one electric current generator either toward a first input or toward a second input of the differential amplifier and the second group of switching means independently directing the electric current originating either from the first input or from the second input of the differential amplifier toward each generator of the second group of at least one electric current generator, the inputs of said differential amplifier being connected in series between the two groups of switching means,
the first group of switching means being controlled by the digital control code and the second group of switching means being controlled by a complementary code (cmd) of said digital control code; and,
said current pump further comprising a regulation module configured to regulate a mean amplitude of a voltage on one of the inputs of the differential amplifier, said regulation module receiving as input a signal representative of the amplitude of the voltage at said input of the differential amplifier as well as a reference voltage of predetermined amplitude and delivering as output a control signal in a direction of each generator of one of the two groups of electric current generator, said control signal being configured to modify the amplitude of an output currents of the generators so as to compensate a possible imbalance between the amplitudes of the current delivered by the complementary current generators.

US Pat. No. 10,340,941

TRIM DIGITAL-TO-ANALOG CONVERTER (DAC) FOR AN R2R LADDER DAC

TEXAS INSTRUMENTS INCORPO...

1. A digital-to-analog converter (DAC), comprising:a first stage comprising a plurality of first circuit arms coupled together, each first circuit arm including a resistor;
a second stage comprising a plurality of second circuit arms coupled together, each second circuit arm comprising a first resistor and a pair of series-connected resistors, the first resistors of the second circuit arms connected in series; and
a current digital-to-analog converter (IDAC) trim circuit connected to a plurality, but not all, of the second circuit arms of the second stage, the IDAC trim circuit comprising a plurality of first current sources, each first current source coupled to a respective node between a pair of the series-connected resistors of a corresponding second circuit arm, and each of the first current sources is configured to produce a same current level as the other first current sources.

US Pat. No. 10,340,940

VARIABLE STEP SWITCHED CAPACITOR BASED DIGITAL TO ANALOG CONVERTER INCORPORATING HIGHER ORDER INTERPOLATION

UNIVERSITY COLLEGE DUBLIN...

1. A digital to analog converter (DAC) for generating a desired output voltage, comprising:an input circuit for receiving first digital input codes representing sample points of the desired output voltage;
an interpolator circuit coupled to said input circuit and including one or more dynamically programmable capacitor arrays, said interpolator circuit operative to interpolate the samples points in an analog domain in accordance with a desired interpolation profile;
an output circuit coupled to said interpolator circuit; and
wherein said interpolator circuit is operative to generate the output voltage between said input sample points by incremental charge transfer at a rate corresponding to said interpolation profile.

US Pat. No. 10,340,939

SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH KICKBACK LINEARIZATION

TEXAS INSTRUMENTS INCORPO...

1. A successive approximation register (SAR) analog-to-digital converter (ADC), comprising:a signal input terminal configured to receive a signal to be digitized;
a capacitive digital-to-analog converter, comprising:
a first capacitor array comprising a plurality of capacitors;
a second capacitor array comprising a plurality of capacitors;
a coupling capacitor that connects the first capacitor array to the second capacitor array, the coupling capacitor comprising:
a top plate connected to a top plate of each of the capacitors of the first capacitor array; and
a bottom plate coupled to a top plate of each of the capacitors of the second capacitor array;
a first switch configured to switchably connect a bottom plate of each of the capacitors of the first capacitor array to the signal input terminal; and
a second switch configured to conduct a voltage on the bottom plate of the coupling capacitor to the signal input terminal.

US Pat. No. 10,340,938

ANALOG TO DIGITAL CONVERTOR (ADC) USING A COMMON INPUT STAGE AND MULTIPLE PARALLEL COMPARATORS

Intel Corporation, Santa...

1. An Analog to Digital converter (ADC) comprising:a first circuitry to sample an analog input signal;
a summation block to iteratively generate a subtraction signal, which is based on a difference between the analog input signal and a feedback signal;
a second circuitry to receive the subtraction signal; and
a plurality of comparison and latch circuitries arranged in parallel, wherein individual ones of the plurality of parallel comparison and latch circuitries is to sequentially receive an output of the second circuitry.

US Pat. No. 10,340,937

VOLTAGE AMPLIFIER FOR A PROGRAMMABLE VOLTAGE RANGE

1. A voltage amplifier for a programmable voltage range, whereby the voltage amplifier has at least a first and a second operating point relative to an input voltage signal, and whereby the voltage amplifier is configured to linearly transform a first range of the input voltage signal into a first output signal by means of the first operating point, and whereby the voltage amplifier is also configured to linearly transform a second range of the input voltage signal into a second output signal by means of the second operating point, whereby the voltage amplifier has a control stage, at least one input reference resistor arrangement and an amplifier circuit, whereby the control stage is configured to transform the input voltage signal into an input current signal, the input reference resistor arrangement is configured to use the input current signal in order to provide a first image of the first range of the input voltage signal and a second image of the second range of the input voltage signal, so that the first image encompasses the first operating point relative to the input voltage signal, and the second image encompasses the second operating point relative to the input voltage signal, and whereby the amplifier circuit is configured to transform the first image into the first output signal and the second image into the second output signal.

US Pat. No. 10,340,936

ANALOG-TO-DIGITAL CONVERSION AND METHOD OF ANALOG-TO-DIGITAL CONVERSION

ams Sensors Belgium BVBA,...

1. An analog-to-digital converter for an imaging device comprising:an analog signal input for receiving an analog signal from a pixel array of the imaging device;
N ramp signal inputs for receiving N ramp signals, where N is an integer ?2, the N ramp signals having different slopes;
a clock input for receiving at least one clock signal;
a comparison stage connected to the ramp signal inputs and to the analog signal input, the comparison stage comprising a minimum of two comparators and being configured to compare the ramp signals with the analog signal during a conversion period and to provide comparison outputs;
a counter stage; and
a control stage which is configured to:
control the counter stage based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period, wherein the handover point is indicative of a point at which a comparison output of a different one of the ramp signals with the analog signal is operable to control the counter stage,
determine, during the conversion period, if a comparison output of the Nth ramp signal has changed state before the handover point associated with a comparison output of an nth ramp signal has been reached, where n is an integer in the range 1 . . . N?1; and
use the comparison output of the nth ramp signal to control the counter stage, if the comparison output of the Nth ramp signal has changed state before the handover point associated with the comparison output of the nth ramp signal has been reached.

US Pat. No. 10,340,935

THERMOMETER DIGITAL TO ANALOG CONVERTER

Dialog Semiconductor (UK)...

1. An n-bit thermometer-coded Digital to Analog Converter (DAC), comprising:‘m’ banks of resistors connected together in ‘p’ strings,
wherein an mth resistor of a first of said strings is connected to an mth resistor of a second of said strings, wherein a 1st resistor of said second of said strings is connected to a 1st resistor of a third of said strings, and with connections between remaining strings continuing in a similar pattern until a pth string;
a set of ‘p’ switches connected to each of said resistors in each of said banks; and
an up/down counter configured to control said set of ‘p’ switches, with a DAC code separated into lower bits and higher bits.

US Pat. No. 10,340,934

SIGNAL PATH LINEARIZATION

ANALOG DEVICES, INC., No...

1. An integrated circuit having on-chip signal path linearization, the integrated circuit comprising:a digital-to-analog converter for generating test signals;
a controller for providing a digital input signal to the digital-to-analog converter;
an analog-to-digital converter for receiving the test signals provided to a signal path and converting the test signals to a digital output signal; and
a processor for estimating coefficients corresponding to non-idealities of the signal path based the digital output signal resulting from the test signals;
wherein the test signals comprises tonal inputs having respective frequencies sweeping across one or more Nyquist zones of the analog-to-digital converter.

US Pat. No. 10,340,933

TIME INTERLEAVED DIGITAL-TO-ANALOG CONVERTER CORRECTION

Tektonix, Inc., Beverton...

1. A method for calibrating pre-processing filters for a time-interleaved digital-to-analog converters (TIDACs) system, comprising:converting a first discrete waveform at a first frequency at a first digital-to-analog converter (DAC) of the TIDACs system to a first analog signal and at a second DAC of the TIDACs system to a second analog signal;
converting a second discrete waveform at a second frequency at the first DAC to a third analog signal and at the second DAC to a fourth analog signal;
combining the first analog signal and the second analog signal into a first combined analog signal and combining the third analog signal and the fourth analog signal into a second combined signal;
converting via an analog-to-digital converter (ADC) the first combined analog signal to a first digital signal and second combined analog signal to a second digital signal;
determining an actual frequency response of the TIDACs system by transforming the first digital signal and the second digital signal to a respective frequency response signal by discrete Fourier transform and generating an actual frequency response matrix based on the respective frequency responses;
receiving a desired frequency response matrix of the TIDACs system; and
generating a pre-processing filter for at least one of the first DAC and the second DAC based on the actual frequency response matrix of the TIDACs system and the desired frequency response matrix of the TIDACs system.

US Pat. No. 10,340,932

TECHNIQUES FOR POWER EFFICIENT OVERSAMPLING SUCCESSIVE APPROXIMATION REGISTER

ANALOG DEVICES, INC., No...

1. A system for a noise-shaping successive approximation register analog-to-digital-converter comprising:a successive approximation register (SAR) for receiving an analog input signal and outputting a digital decision;
a digital-to-analog converter (DAC) and logic circuitry for converting the digital decision of the SAR to a present analog residue for a present conversion cycle; and
a filter for processing a previous analog residue from a previous conversion cycle, and for feeding a processed previous analog residue back to the SAR, wherein the filter includes a capacitor array having a first plurality of capacitors for filtering the previous analog residue to generate the processed previous analog residue; and
a summer for summing the processed previous analog residue from the filter and the present analog residue, and generating a summer output.

US Pat. No. 10,340,931

DYNAMIC DELAY ADJUSTMENT FOR MULTI-CHANNEL DIGITAL-TO-ANALOG CONVERTER SYNCHRONIZATION

Tektronix, Inc., Beavert...

1. An arbitrary waveform generator, comprising:a first processor configured to output first digital data;
a second processor configured to output second digital data;
a first digital-to-analog converter to receive the first digital data from the first processor and output a first analog signal representing the first digital data;
a second digital-to-analog converter to receive the second digital data from the second processor and output a second analog signal representing the second digital data;
a system phase detector to receive the first analog signal and the second analog signal and determine a phase difference between the first analog signal and the second analog signal; and
a controller configured to receive the phase difference from the system phase detector and determine a delay time for the first processor to delay an output of third digital data based on the phase difference.

US Pat. No. 10,340,930

QUANTUM INTERFERENCE DEVICE, AN ATOMIC OSCILLATOR, AN ELECTRONIC APPARATUS, AND A VEHICLE

Seiko Epson Corporation, ...

1. A quantum interference device comprising:an atom cell module including an atom cell in which alkali metal is encapsulated, a light source that emits light adapted to excite the alkali metal, and a heater that heats the atom cell and the light source;
a package that houses the atom cell module; and
a controller adapted to control drive of the heater so that the light source becomes at a set temperature,
wherein the following is satisfied:
R<(Tv?Tout)/Qv
where R [° C./W] is a thermal resistance between the atom cell module and the package, Tv [° C.] is the set temperature, Tout [° C.] is an upper limit value of a usage environmental temperature set to a value lower than the set temperature, Qv [W] is an amount of heat generation of the light source.

US Pat. No. 10,340,929

VOLTAGE CONTROLLED OSCILLATOR AND PHASE LOCKED LOOP COMPRISING THE SAME

YONSEI UNIVERSITY INDUSTR...

1. A voltage controlled oscillator comprising:an oscillator comprising a plurality of inverters connected as a ring form for generating a plurality of signals having different phases with each other, and a plurality of feed forward circuits formed between the inverters; and
a controller for controlling the plurality of inverters and the plurality of feed forward circuits based on a detected noise by detecting a noise of a power voltage.

US Pat. No. 10,340,928

PHASE-LOCKED LOOP

Stichting IMEC Nederland,...

1. A method comprising:generating, by a clock module, a reference clock signal;
adjusting, by a first digital-to-time converter, the reference clock signal in accordance with a first control signal;
generating, by the first digital-to-time converter, a first input signal corresponding to the adjusted reference clock signal;
receiving, by a time-to-digital converter, the first input signal;
generating, by the time-to-digital converter, an output signal based on the first input signal;
generating an output high-frequency clock signal based on the output signal from the time-to-digital converter;
generating a derived signal from the output high-frequency clock signal;
adjusting, by a second digital-to-time converter, the derived signal in accordance with a second control signal, wherein a value of the first control signal and a value of the second control signal are centered about a midpoint value, M, and offset from the midpoint value by a fraction, x, such that the values of the first and second control signals are respectively defined as (M+x) and (M?x);
generating, by the second digital-to-time converter, a second input signal corresponding to the adjusted derived signal; and
receiving, by the time-to-digital converter, the second input signal, wherein the time-to-digital converter generates the output signal based on both the first input signal and the second input signal.

US Pat. No. 10,340,927

DIGITAL PHASE LOCKED LOOP SYSTEM

MARVELL INTERNATIONAL LTD...

1. A system comprising:a phase locked loop (PLL) circuit comprising:
a time-to-digital converter (TDC) configured to compare a reference clock signal to a feedback clock signal to generate an error signal;
a digital loop filter configured to process the error signal in accordance with gain coefficients to generate an oscillator control signal;
a digitally controlled oscillator (DCO) configured to generate an output clock signal based on the oscillator control signal while the PLL circuit is operating in a closed-loop configuration; and
a divider circuit configured to generate the feedback clock signal from the output clock signal in accordance with N/R values; and
a digital control unit coupled with the PLL circuit, the digital control unit comprising circuitry configured to:
receive a frequency word corresponding to a desired output frequency of the output clock signal;
determine a preset value for the DCO corresponding to the received frequency word;
determine initial gain coefficients and final gain coefficients for the digital loop filter corresponding to the received frequency word, where each of the initial gain coefficients has a larger value than a corresponding final gain coefficient of the final gain coefficients;
determine N/R values for the divider circuit corresponding to the received frequency word;
while the PLL circuit is operating in an open-loop configuration, provide the determined preset value to the DCO, the determined initial gain coefficients to the digital loop filter, and the determined N/R values to the divider circuit;
after providing the determined preset value, the determined initial gain coefficients, and the determined N/R values, initiate operation of the PLL circuit in the closed-loop configuration; and
in response to detection of a phase lock of the PLL circuit operating in the closed-loop configuration, provide the determined final gain coefficients to the digital loop filter;
wherein the PLL circuit further comprises a multiplexer configured to provide the oscillator control signal or the determined preset value to the DCO based on a preset enable signal; and
wherein the digital control unit is configured to provide the preset enable signal to the multiplexer.

US Pat. No. 10,340,926

FAST SETTLING SAWTOOTH RAMP GENERATION IN A PHASE-LOCKED LOOP

Analog Devices Global, H...

1. A phase-locked loop comprising:an input configured to receive a frequency command word, wherein the frequency command word is an input sawtooth ramp signal;
a loop filter configured to provide a sawtooth ramp signal, wherein the sawtooth ramp signal is periodic and based on the frequency command word, wherein the sawtooth ramp signal has a settling time associated with a transition from a first ramping portion of a first period of the sawtooth ramp signal to a second ramping portion of a second period of the sawtooth ramp signal, and wherein the settling time is less than 1 microsecond; and
an oscillator coupled to the loop filter, the oscillator configured to generate an oscillating signal based on the sawtooth ramp signal.

US Pat. No. 10,340,925

DIGITAL LOCKING LOOP CIRCUIT AND METHOD OF OPERATION

Marvell International Ltd...

1. A digital locking loop circuit comprising:a digitally-controlled frequency generator;
a digital loop filter configured to output a digital control signal for inputting to the digitally-controlled frequency generator; and
a multi-stage time-to-digital converter configured to detect phase error between an input reference clock signal and an output signal fed back from the digitally-controlled frequency generator, and to output a digital phase error signal, representative of magnitude of the phase error, as a control input to the digital loop filter, to cause the digital control signal output by the digital loop filter to adjust the digitally-controlled frequency generator to decrease the phase error, the multi-stage time-to-digital converter including:
a plurality of time-to-digital converter stages, each respective time-to-digital converter stage being configured to detect a respective phase error component at a respective resolution, the respective resolution of each respective time-to-digital converter stage being different from the respective resolution of each other time-to-digital converter stage; and
combinatorial logic configured to combine the respective phase error components into the digital phase error signal.

US Pat. No. 10,340,923

SYSTEMS AND METHODS FOR FREQUENCY DOMAIN CALIBRATION AND CHARACTERIZATION

Intel Corporation, Santa...

1. A system for providing calibration to an oscillator circuit, comprising:an oscillator circuit configured to generate an output clock signal;
a frequency measurement circuit configured to measure frequencies of the output clock signal and generate a measurement signal representative of the measured frequencies; and
control circuitry configured to generate an adjustment signal based on a comparison of the measurement signal with a reference value,
wherein the frequency measurement circuit includes a first counter and a second counter, where the first counter receives the output clock signal and the second counter receives a reference clock, and wherein the frequency measurement circuit uses the outputs of the first and second counters to generate the measured frequencies.

US Pat. No. 10,340,922

BIAS CIRCUIT FOR TEMPERATURE-COMPENSATED VARACTOR

QUALCOMM Incorporated, S...

1. A bias circuit, comprising:a diode-connected transistor;
a first transistor coupled in series with the diode-connected transistor;
a first output terminal for tuning a varactor, the first output terminal coupled to the source of the diode-connected transistor;
a resistor coupled in series with the diode-connected transistor;
a second output terminal for tuning the varactor, the second output terminal coupled to a first terminal of the resistor; and
a common-mode feedback circuit configured to control an output voltage biasing a gate of the first transistor so that a common-mode voltage for a differential voltage across the first output terminal and the second output terminal equals a reference voltage.

US Pat. No. 10,340,921

APPARATUSES AND METHODOLOGIES FOR VIBRATION EFFECTS CORRECTION IN OSCILLATORS

VT IDIRECT, INC., Herndo...

1. A method for vibration correction in an oscillator, the method comprising:sensing vibrations along one or more axes via at least one accelerometer mounted on the oscillator;
determining a g-sensitivity vector of the oscillator using measurements obtained using a vibration table and a spectrum analyzer;
calculating corrective factors as a function of the g-sensitivity vector;
storing the corrective factors in a look-up table;
determining particular corrective factors based on an acceleration signal received from the at least one accelerometer by referencing the corrective factors in the look-up table; and
controlling the oscillator based on at least the particular corrective factors.

US Pat. No. 10,340,920

HIGH PERFORMANCE FPGA ADDITION

INTEL CORPORATION, Santa...

1. Adder circuitry on an integrated device, the adder circuitry comprising:input circuitry configured to receive a first input and a second input;
first arithmetic logic circuitry communicatively coupled to the input circuitry, wherein the first arithmetic logic circuitry is configured to:
determine a first sum of a first bit of the first input and a first bit of the second input; and
determine a propagate signal and a generate signal based at least in part on the first sum; and
output circuitry communicatively coupled to the first arithmetic logic circuitry, wherein the output circuitry is configured to concurrently output the generate signal, the propagate signal, and the first sum.

US Pat. No. 10,340,919

CIRCUIT FOR MONITORING TRANSIENT TIME IN ANALOG AND DIGITAL SYSTEMS

Taiwan Semiconductor Manu...

1. A circuit for monitoring a transient time in a device under test, the circuit comprising:a transient edge clipper circuit arranged to be electrically coupled to the device under test, the transient edge clipper circuit configured to remove voltage levels of a voltage waveform of the device under test which exceed a threshold range to generate a clipped voltage waveform;
logic circuitry electrically coupled to the transient edge clipper circuit, the logic circuitry configured to generate a time delayed pulse signal representation of the clipped voltage waveform by injecting a predetermined time delay; and
a converter circuit electrically coupled to the logic circuitry and configured to generate a current signal based on the pulse signal representations.

US Pat. No. 10,340,918

LEVEL SHIFTER

MSTAR SEMICONDUCTOR, INC....

1. A level shifter, comprising:a bias voltage providing circuit, comprising:
a first bias voltage providing unit, disposed between a first operating voltage and a ground voltage, providing a first bias voltage; and
a second bias voltage providing circuit, disposed between the first operating and the ground voltage, providing a second bias voltage;
a level shifting circuit, comprising:
a high level shifting unit, receiving a first control signal and connected to the first operating voltage, determining whether to conduct the high level shifting unit according to the first control signal to accordingly determine whether to output the first operating voltage; and
a low level shifting unit, receiving the first control signal and connected to the second operating voltage, determining whether to conduct the low level shifting unit according to the first control signal to accordingly determine whether to output the second operating voltage;
an output switching circuit;
a first switch element, comprising a control terminal, a first path terminal and a second path terminal; wherein, the first control terminal receives a first control voltage, the first path terminal receives an output of the level shifting circuit, the first switch element is conducted when the level shifting circuit outputs the first operating voltage such that the output switch circuit outputs the first operating voltage, and the first switch element is cut off when the level shifting circuit outputs the second operating voltage;
a second switch element, comprising a control terminal, a first path terminal and a second path terminal; wherein, the control terminal receives a second control voltage, the first path terminal receives a second control signal designed to match an operation of the second switch element, the second switch element is cut off when the first switch element is conducted, and the second switch element is conducted when the first switch element is cut off such that that the output switching circuit outputs the ground voltage; wherein, the first switch element is a first-type switch element, the second switch element is a second-type switch element, and a type of the first switch element is opposite to a type of the second switch element;
wherein, when the high level shifting unit is in a cut-off state, the high level shifting unit further receives the first bias voltage such that the high level shifting unit is in a partially cut-off state; when the low level shifting unit is in the cut-off state, the low level shifting unit further receives the second bias voltage such that the low level shifting unit is in the partially cut-off state.

US Pat. No. 10,340,917

RECEIVER CIRCUITRY AND METHOD FOR CONVERTING AN INPUT SIGNAL FROM A SOURCE VOLTAGE DOMAIN INTO AN OUTPUT SIGNAL FOR A DESTINATION VOLTAGE DOMAIN

ARM Limited, Cambridge (...

1. Receiver circuitry for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain, the source voltage domain operating from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, the receiver circuitry being configured to operate from the supply voltage of the source voltage domain and comprising:first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range;
second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range;
signal evaluation circuitry configured to establish a logic high voltage threshold and a logic low voltage threshold dependent on the supply voltage, and further configured to employ the first and second internal signals in order to detect based on the logic high voltage threshold and logic low voltage threshold when the input signal transitions between a logic low level and a logic high level;
assist circuitry coupled to the signal evaluation circuitry and configured to cause a logic high voltage threshold to be reached more quickly than the signal evaluation circuitry relying on transitions of the first and second internal signals to cause the logic high voltage threshold to be reached, wherein the assist circuity is activated to be used instead of the signal evaluation circuitry based on a determination that the supply voltage is above a predetermined threshold; and
output generation circuitry configured to generate the output signal in dependence on the detection performed by the signal evaluation circuitry;
wherein the first voltage range and the second voltage range are such that the first internal signal and second internal signal will not exceed the stressing threshold of components in the signal evaluation circuitry.

US Pat. No. 10,340,916

USING ISLANDS TO CONTROL OPERATING PARAMETERS FOR FUNCTIONAL BLOCKS IN AN ELECTRONIC DEVICE

ADVANCED MICRO DEVICES, I...

1. An electronic device, comprising:a plurality of hardware functional blocks, the hardware functional blocks being logically grouped into two or more islands, with each island including a different one or more of the hardware functional blocks, wherein the hardware functional blocks that are logically grouped into at least one of the islands include hardware functional blocks that are operable at a sub-Vmin voltage and the hardware functional blocks that are logically grouped into at least one other of the islands include hardware functional blocks that are not reliably operable at the sub-Vmin voltage, wherein the sub-Vmin voltage is a voltage that is sufficiently low that only circuits having circuit elements designed to be operable at the sub-Vmin voltage operate reliably;
a hardware controller that is configured to:
determine a present activity being performed by at least one of the hardware functional blocks; and
based on the present activity, configure supply voltages for the hardware functional blocks in some or all of the islands.

US Pat. No. 10,340,915

FREQUENCY AND MATCH TUNING IN ONE STATE AND FREQUENCY TUNING IN THE OTHER STATE

Lam Research Corporation,...

1. A method for achieving reduction in power reflected towards a radio frequency (RF) generator, comprising:providing a plurality of set points to the RF generator, wherein the plurality of set points include a frequency set point for a first state of a digital pulsed signal and a frequency set point for a second state of the digital pulsed signal;
adjusting an impedance matching circuit to reduce a variable for the first state to be below a pre-determined variable threshold;
determining whether the variable for the first state is stable;
adjusting the impedance matching circuit and the frequency set point for the first state upon determining that the variable for the first state is not stable;
determining whether a variable for the second state is stable; and
changing the frequency set point for the first state in response to determining that the variable for the second state is not stable, wherein said changing the frequency set point for the first state is performed to achieve the reduction in the power reflected towards the RF generator.

US Pat. No. 10,340,913

APPARATUSES AND METHODS FOR PARTIAL BIT DE-EMPHASIS

Micron Technology, Inc., ...

1. An apparatus comprising:an external terminal; and
an output driver coupled to the external terminal, the output driver configured to:
receive a first signal having a first logical value,
receive a second signal following the first signal, the second signal having a second logical value different from the first logical value, and
drive, in response to receiving the second signal, the external terminal from a first voltage to a second voltage by way of a third voltage, wherein the third voltage is a de-emphasized first voltage based at least in part on a de-emphasis time,
wherein the output driver receives a third signal having the second logical value, wherein the first signal is received following the third signal.

US Pat. No. 10,340,911

METHOD FOR PROGRAMMING A TWO-WIRE SENSOR AND PROGRAMMABLE TWO-WIRE SENSOR

TDK - Micronas GmbH, Fre...

1. A method for programming a two-wire sensor having at least two sensor units, the method comprising the steps of:switching on the at least two sensor units;
activating one of the at least two sensor units;
capturing operating states of the at least two sensor units;
detecting an operating state in which one individual sensor unit is active; and
sending a programming command to the detected, active sensor unit.

US Pat. No. 10,340,910

DRIVE CIRCUIT

Kabushiki Kaisha Toshiba,...

1. A drive circuit comprising:a first level shift circuit configured to receive an input high-side driving signal and output a first switch signal which is obtained by shifting the
high-side driving signal to a predetermined first signal level;
a second level shift circuit configured to output a second switch signal which is obtained by shifting signal level of the high-side driving signal to a predetermined second signal level set to be not higher than the predetermined first signal level;
a pre-driver including a first switch portion which switches to either connection to or disconnection from a feed channel for a first power supply voltage in accordance with the first switch signal and a second switch portion which is connected to the first power supply voltage through switching by the first switch portion and outputs a gate signal in accordance with the second switch signal; and
a high-side transistor connected to a second power supply voltage set to be lower than the first power supply voltage and configured to generate a high-side output signal with the second power supply voltage that is fed in accordance with the gate signal and output the high-side output signal to an output terminal.

US Pat. No. 10,340,909

BUFFER CIRCUIT AND SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A buffer circuit connected between an input terminal and a gate of a semiconductor switching element, the buffer circuit comprising:an NPN transistor and a PNP transistor that constitute a complementary single ended push pull circuit;
a first resistor connected between the gate and an emitter of the NPN transistor;
a second resistor connected between the gate and an emitter of the PNP transistor;
a first load element comprising one end directly connected between an end of the first resistor and the gate and another end connected to a base of the NPN transistor;
a second load element comprising one end directly connected between an end of the second resistor and the gate and another end connected to a base of the PNP transistor;
a third resistor connected between the input terminal and the base of the NPN transistor; and
a fourth resistor connected between the input terminal and the base of the PNP transistor.

US Pat. No. 10,340,908

HALF-BRIDGE DRIVER FAULT DIAGNOSTIC SYSTEM AND METHOD

Continental Automotive Sy...

1. An apparatus for controlling the application of electrical power to a load having a first electrical terminal and a second electrical terminal, the apparatus comprising:a controller;
a high side driver electrically connected to a voltage supply and to the first electrical terminal of the load, the high side driver controllable to an on state wherein current flow from the voltage supply to the load is enabled and to an off state wherein current flow from the voltage supply to the load is disabled;
a low side driver electrically connected to the second electrical terminal of the load and to a ground connection, the low side driver controllable to an on state wherein current flow from the load to the ground connection is enabled and to an off state wherein current flow from the load to the ground connection is disabled;
a diagnostic circuit configured to sense a fault condition and to generate a signal indicative of the fault condition;
wherein the diagnostic circuit is configured to sense and identify a first fault condition wherein the first fault condition is an open load fault condition;
wherein the diagnostic circuit is configured to sense and identify a second fault condition wherein the second fault condition is a high-side short circuit to battery fault condition;
wherein the diagnostic circuit is configured to sense and identify a third fault condition wherein the third fault condition is a low-side short circuit to ground fault condition;
wherein the diagnostic circuit is configured to sense and identify a fourth fault condition wherein the fourth fault condition is a high-side short circuit to ground fault condition;
wherein the diagnostic circuit is configured to sense and identify a fifth fault condition wherein the fifth fault condition is a low-side short circuit to battery fault condition;
wherein the diagnostic circuit is configured to sense and identify a sixth fault condition wherein the sixth fault condition is a short circuited load fault condition;
wherein the diagnostic circuit is configured to sense and identify a condition wherein none of the first fault condition, the second fault condition, the third fault condition, the fourth fault condition, the fifth fault condition, and the sixth fault condition are present,
wherein the diagnostic circuit comprises a high-side on-state diagnostic circuit and a low-side on-state diagnostic circuit;
wherein the high-side on-state diagnostic circuit is configured to monitor a current through the high side driver from the voltage supply to the first electrical terminal of the load and to generate a high-side overcurrent logic signal indicative of whether the current through the high side driver is above or below a predetermined high-side current threshold;
wherein the low-side on-state diagnostic circuit is configured to monitor a current through the low side driver from the second electrical terminal of the load to the ground connection and to generate a low-side overcurrent logic signal indicative of whether the current through the low side driver is above or below a predetermined low-side current threshold;
the apparatus further including a first latch configured to capture the state of the high-side overcurrent logic signal and a second latch configured to capture the state of the low-side overcurrent logic signal.

US Pat. No. 10,340,907

DRIVE DEVICE FOR SEMICONDUCTOR ELEMENT

Mitsubishi Electric Corpo...

1. A drive device to drive a semiconductor element comprising:an identification signal generating circuit generating an identification signal depending on a type of an input error signal;
a protection operation signal generating circuit generating a protection operation signal, wherein the protection operation signal has a pulse width equal to that of one of the error signal and the identification signal, based on which has a longer pulse width;
an other-phase identification signal terminal inputting an identification signal from an other-phase drive device or outputting the identification signal to the other-phase drive device;
a other-phase protection operation signal terminal inputting a protection operation signal from the other-phase drive device or outputting the protection operation signal to the other-phase drive device; and
a protection circuit performing an error protection operation depending on the protection operation signal generated by the protection operation signal generating circuit and the other-phase protection operation signal input through the protection operation signal terminal.

US Pat. No. 10,340,906

INTEGRATED BOOTSTRAP HIGH-VOLTAGE DRIVER CHIP AND TECHNOLOGICAL STRUCTURE THEREOF

SOUTHEAST UNIVERSITY, Wu...

1. An integrated bootstrap high-voltage driver chip based on a driver circuit of a half-bridge structure, comprising a low-side channel logic circuit (001) and a high-side channel logic circuit (002), wherein the high-side channel logic circuit (002) comprises a high-side signal input circuit (004), a narrow pulse generation circuit (005), a high-voltage level shift circuit (006) and a high-side channel high-basin logic circuit (007) composed of two pulse filtering circuits with the same structure, an RS trigger and a high-side signal output circuit; the low-side channel logic circuit (001) comprises a low-side signal input circuit (008), a low-side delay circuit (009) and a low-side signal output circuit (010); a high-side input signal (HIN) is connected to the input end of the high-side signal input circuit (004), an output signal (CIN1) of the high-side signal input circuit (004) is connected to the input end of the narrow pulse generation circuit (005), a low-voltage set signal (SET) and a low-voltage reset signal (RESET) outputted by the narrow pulse generation circuit (005) are respectively connected to two input ends of the high-voltage level shift circuit (006), a high-voltage set signal (VRS) and a high-voltage reset signal (VRR) outputted by the high-voltage level shift circuit (006) are respectively connected to two input ends of the high-side channel high-basin logic circuit (007), and a high-side output signal (HO) outputted by the high-side channel high-basin logic circuit (007) is used as a gate driving signal of a high-side tube in the half-bridge structure; a low-side input signal (LIN) is connected to the input end of the low-side signal input circuit (008), an output signal (CIN2) of the low-side signal input circuit (008) is connected to the input end of the low-side delay circuit (009), the output end of the low-side delay circuit (009) is connected to the input end of the low-side signal output circuit (010), and the output of the low-side signal output circuit (010) is a low-side output signal (LO) and is used as a gate driving signal of a low-side tube in the half-bridge structure; in the circuits above, the high-voltage level shift circuit (006) and the high-side channel high-basin logic circuit (007) are located in a high-voltage circuit area and powered by a high-side floating power supply (VB), the other circuits are all located in a low-voltage circuit area and powered by a low-side fixed power supply (VCC); in order to increase the utilization efficiency of the power supply, the half-bridge driver chip is powered by a single power supply, wherein the low-voltage area circuit is directly powered by a direct current power supply, while the high-voltage area circuit is in a floating state, and is powered by an external bootstrap diode (DB?) and an external bootstrap capacitor (CB?) in a bootstrap manner; the power supply of the high-side signal input circuit (004), the narrow pulse generation circuit (005) and the low-side channel logic circuit (001) is the low-side fixed power supply (VCC), a logic ground is a ground signal (COM), the power supply of the high-side channel high-basin logic circuit (007) is the high-side floating power supply (VB), a logic ground is a high-side floating ground (VS), and the bootstrap capacitor (CB?) is connected between the high-side floating power supply (VB) and the high-side floating ground (VS); the high-voltage level shift circuit (006) is used as an interface of the high-voltage area circuit and the low-voltage area circuit, and comprises two subcircuits with the same structure, each subcircuit comprises a high-voltage switch tube, a Zener clamping diode and a load, the Zener clamping diode is connected to the load in parallel, the drain of the high-voltage switch tube in each subcircuit is connected to the anode of the Zener clamping diode in the subcircuit and the connecting end of the load, cathodes of the Zener clamping diodes in the two subcircuits are mutually connected to the connecting ends of the loads, and are connected to the high-side floating power supply (VB); in the two subcircuits, the grid of the high-voltage switch tube of one subcircuit is connected to the low-voltage set signal (SET) outputted by the narrow pulse generation circuit (005), the drain of the high-voltage switch tube of the subcircuit outputs the high-voltage set signal (VRS), the grid of the high-voltage switch tube of the other subcircuit is connected to the low-voltage reset signal (RESET) outputted by the narrow pulse generation circuit (005), and the drain of the high-voltage switch tube of the subcircuit outputs the high-voltage reset signal (VRR);wherein, the bootstrap diodes (DB?) is at least one parasitic diode implemented by integration technology, and matched with the bootstrap control circuit (003) provided to realize a bootstrap charging process together, the input signals of the bootstrap control circuit (003) are respectively the output signal (CIN1) of the high-side signal input circuit (004) and the output signal (CIN2) of the low-side signal input circuit (008), the output signal of the bootstrap control circuit (003) is a reference ground (PGD), the reference ground (PGD) is connected to sources of two high-voltage switch tubes in the high-voltage level shift circuit (006), when one parasitic diode is provided, the parasitic diode is defined as a first parasitic diode (DB1), the anode of the first parasitic diode (DB1) is connected to the reference ground PGD, and the cathode of the bootstrap control circuit is connected to the high-side floating power supply VB;
when the output signal (PGD) of the bootstrap control circuit (003) is at a low level which is a ground signal (COM), the high-voltage level shift circuit (006) conducts level shift to the high-side signal; when the output signal (PGD) of the bootstrap control circuit (003) is at a high level which is a low-side fixed power supply voltage (VCC), and when the input signal of the high-voltage level shift circuit (006) is at a low level which is the ground signal (COM), the high-voltage level shift circuit (006) can also be used as a current channel for the VCC to charge the external bootstrap capacitor, which realizes to charge the bootstrap capacitor by the low-side fixed power supply (VCC) under the premise of guaranteeing the normal work of the high-voltage level shift circuit;
the charging process is as follows:
when the input signal (CIN1) of the bootstrap control circuit (003) is at a low level which is the ground signal (COM), and the input signal (CIN2) is at a high level which is the low-side fixed power supply (VCC), the output signal (PGD) of the bootstrap control circuit (003) is at a high level which is the low-side fixed power supply (VCC), at the moment, the reference ground (PGD) charges the bootstrap capacitor (CB) through the first parasitic diode DB1; when the input signal (CIN1) of the bootstrap control circuit (003) is at a low level, and the input signal (CIN2) is at a low level which is the ground signal (COM), the output signal (PGD) is at a high level (the low-side fixed power supply (VCC), at the moment, the PGD charges the bootstrap capacitor through the first parasitic diode (DB1); when the input signal (CIN1) is at a high level, and the input signal (CIN2) is at a low level, or when the input signals (CIN1) and (CIN2) are at a high level at the same time, the output signal (PGD) is at a low level which is the ground signal (COM), at the moment, the first parasitic diode (DB1) is in a turned-off state, and a charging action is stopped.

US Pat. No. 10,340,905

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a circuit block including at least a MOSFET, and having two operating modes, namely, an operating mode and a standby mode;
a voltage generation circuit configured to generate and output a predetermined output voltage; and
a bias control circuit coupled between the circuit block and the voltage generation circuit and configured to receive the predetermined output voltage from the voltage generation circuit, and further configured to store an electrical charge while the circuit block is in the operating mode, supply the stored electrical charge to a substrate of the MOSFET included in the circuit block when the circuit block transitions from the operating mode to the standby mode, and subsequently supply the predetermined output voltage to the substrate of the MOSFET, the bias control circuit including at least one capacitor configured to selectively couple to an output of the voltage generation circuit in the operation mode and the standby mode,
wherein the predetermined output voltage is a back bias voltage of the substrate of the MOSFET in the standby mode.

US Pat. No. 10,340,904

METHOD AND APPARATUS FOR PHASE-ALIGNED 2X FREQUENCY CLOCK GENERATION

Altera Corporation, San ...

1. A multiple-channel serializer circuit comprising:a central clocks generator that generates a plurality of clock signals;
a clock network for distributing the plurality of clock signals from the central clocks generator; and
a plurality of one-channel serializers, each one-channel serializer comprising a series of serializer circuits that use the plurality of clock signals from the clock network to serialize a parallel data input signal,
wherein a one-channel serializer of the plurality of one-channel serializes further comprises a local 2× frequency clock generator with a non-divider structure that generates a local 2× frequency clock signal that has a frequency which is twice that of a 1× frequency clock signal output from the central clocks generator, wherein the 1× frequency clock signal is used for timing a parallel data signal input to the one-channel serializer.

US Pat. No. 10,340,903

SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF

1. A semiconductor device comprising:a target circuit including a transistor;
a monitoring circuit configured to measure a temperature of the target circuit and a delay time between an input and an output of the target circuit; and
a voltage controller configured to:
adjust, according to the measurement of the temperature and the measurement of the delay time, 1) a driving voltage for driving the target circuit to be less than or equal to a critical voltage and 2) a back-bias voltage for adjusting a threshold voltage of the transistor, and
provide the driving voltage and the back-bias voltage to the target circuit,
wherein when the driving voltage is less than or equal to the critical voltage, as the temperature increases, the delay time decreases, and
wherein when the driving voltage is greater than the critical voltage, as the temperature increases, the delay time increases.

US Pat. No. 10,340,901

RANDOM NUMBER GENERATOR, RANDOM NUMBER GENERATION DEVICE, NEUROMORPHIC COMPUTER, AND QUANTUM COMPUTER

TDK CORPORATION, Tokyo (...

1. A random number generator comprising:a ferromagnetic metal layer;
a spin-orbit torque wiring extending in a first direction intersecting a lamination direction of the ferromagnetic metal layer and being joined to the ferromagnetic metal layer; and
an external magnetic field applying part configured to apply a magnetic field to the ferromagnetic metal layer;
wherein a direction of spin injected from the spin-orbit torque wiring into the ferromagnetic metal layer and an easy magnetization direction of the ferromagnetic metal layer intersect each other.

US Pat. No. 10,340,900

SENSE AMPLIFIER FLIP-FLOP WITH EMBEDDED SCAN LOGIC AND LEVEL SHIFTING FUNCTIONALITY

Apple Inc., Cupertino, C...

1. An apparatus, comprising:a first latch circuit including a first discharge node, a second discharge node, a true storage node and a complement storage node, wherein the first latch circuit is configured to pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal;
a discharge circuit including:
a first transconductance device located in a first discharge path between the first discharge node and a ground reference; and
a second transconductance device in a second discharge path between the first discharge node and the ground reference;
wherein the discharge circuit is configured to:
in response to a determination that a scan mode signal is asserted, selectively discharge, based on a value of a scan data signal on a gate terminal of the first transconductance device, either the true storage node via the first discharge node, or the complement storage node via the second discharge node, wherein the scan data signal transitions between a ground voltage level and a second voltage level different than the first voltage level;
otherwise selectively discharge, based on a value of a data signal on a gate terminal of the second transconductance device, either the true storage node via the first discharge node, or the complement storage node via the second discharge node, wherein the data signal transitions between the ground voltage level and a third voltage level different than the first and second voltage levels;
a second latch circuit coupled to the first latch circuit, wherein the second latch circuit is configured to store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node; and
at least one logic gate coupled to a respective output node of at least one output node of the second latch circuit, the logic gate configured to block propagation of a respective output signal in response to a determination that the scan mode signal is de-asserted.

US Pat. No. 10,340,899

HIGH PERFORMANCE LOW RETENTION MODE LEAKAGE FLIP-FLOP

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:a retention circuit configured to retain the state of a circuit node, the retention circuit including:
a first inverter having an input and an output;
a second inverter having an input and an output, wherein the input of the second inverter is connected to the output the first inverter and the output of the second inverter is connected to the input of the first inverter;
a transmission gate having a first terminal connected to the circuit node and a second terminal connected to the input of the first inverter, wherein the transmission gate is configured to be controlled by a retention mode signal that indicates whether a retention mode is active or inactive to isolate the first terminal and the second terminal from each other when the retention mode signal indicates that the retention mode is active and to connect the first terminal and the second terminal to each other when the retention mode signal indicates that the retention mode is inactive; and
a third inverter having an input and an output, wherein the third inverter is a tristate inverter, wherein the input of the third inverter is connected to the output of the first inverter, wherein the output of the third inverter is connected to the circuit node by a signal path that extends between the output of the third inverter and the circuit node and does not include another inverter, and wherein the tristate inverter is configured to be controlled by the retention mode signal to isolate the output of the third inverter from the circuit node when the retention mode signal indicates that the retention mode is inactive and to supply an output signal to the circuit node when the retention mode signal indicates that the retention mode is active, the output signal supplied by the output of the third inverter being an inverse of an output signal supplied by the output of the first inverter.

US Pat. No. 10,340,898

CONFIGURABLE LATCH CIRCUIT

XILINX, INC., San Jose, ...

1. A pulsed latch circuit, comprising:first and second latch circuits, each latch circuit having a respective data input node, a respective data output node, and a respective clock input node, the data output node of the first latch circuit being coupled to the data input node of the second latch circuit; and
a clock control circuit coupled to the first and second latch circuits and configured to:
selectively provide, in response to a first state of a control signal, a first clock pulse that is based on an input clock signal to the clock input node of the second latch circuit and a second clock pulse that is based on an inversion of the first clock pulse to the clock input node of the first latch circuit to cause the first and second latch circuits to store values from two successive clock cycles,
wherein in a single cycle of the input clock signal, the second latch circuit, responsive to the first clock pulse, opens and stores state of the signal at the output node of the first latch circuit, and the first latch circuit, responsive to the second clock pulse, opens and stores state of a signal at the input node of the first latch; and
selectively provide, in response to a second state of the control signal, the input clock signal to the clock input nodes of the first and second latch circuits to cause the first and second latch circuits to cooperate to store a value from a single clock cycle.

US Pat. No. 10,340,897

CLOCK GENERATING CIRCUIT AND METHOD OF OPERATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A clock circuit, comprising:a first latch configured to generate a first latch output signal based on a first control signal, an enable signal and an output clock signal;
a second latch coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal;
a first trigger circuit coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal; and
a clock trigger circuit coupled to the first latch and the first trigger circuit by a first node, configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.

US Pat. No. 10,340,896

ELECTRONIC SYSTEM AND SIGNAL SWITCHING CIRCUIT

WIWYNN CORPORATION, New ...

1. A signal-switching circuit for use in an electronic system, wherein the electronic system comprises a plurality of hardware circuits, the signal-switching circuit comprising:a control circuit, arranged to receive a trigger signal generated by a trigger circuit of the electronic system, and change a mode signal generated by the control circuit in response to the trigger signal; and
a switch circuit, arranged to electrically connect transmission signals from one of the hardware circuits to a test board external to the electronic system via a transmission interface of the electronic system in response to the mode signal,
wherein the trigger signal is a pulse signal,
wherein the signal-switching circuit comprises more than two operation modes, and the control circuit changes the mode signal according to the trigger signal to sequentially switch between the operation modes,
wherein the control circuit includes N serially-connected D flip-flops (DFFs), and each of the N DFFs comprises a data input pin, a clock input pin, a data output pin, and an inverse data output pin, and the inverse data output pin is connected to the data input pin in each of the N DFFs,
wherein the clock input pin of the first DFF of the N DFFs receives the trigger signal,
wherein the data output pin of each DFF is connected to the block input pin of the next DFF for each of the first DFF to the (N?1)-th DFF,
wherein the data output pin of each of the N DFFs is connected to the switch circuit.

US Pat. No. 10,340,895

REDUCED-POWER ELECTRONIC CIRCUITS WITH WIDE-BAND ENERGY RECOVERY USING NON-INTERFERING TOPOLOGIES

Rezonent Corporation, Lo...

1. A digital driver having a wide operating frequency range, comprising:a pulldown switch;
a pullup switch;
an energy saving component coupled in series with the pulldown switch and the pullup switch; and
a reference supply connected in series with the energy saving component that is configured to enable the digital driver to resonate with a load capacitance and reuse electrical energy at the load capacitance without interfering with a signal path of the digital driver having the wide operating frequency range due to the energy saving component being electrically coupled to the signal path periodically, wherein the pullup switch is designed with a first ratio of width to length that is less than a second ratio of width to length of the pulldown switch due to functionality of the pullup switch being partially performed with energy recycling resonance when the driver resonates with the load capacitance.

US Pat. No. 10,340,894

STATE RETENTION CIRCUIT THAT RETAINS DATA STORAGE ELEMENT STATE DURING POWER REDUCTION MODE

Silicon Laboratories Inc....

1. A state retention circuit for retaining the state of a data storage element during a power reduction mode, comprising:a storage latch powered by a retention supply voltage that remains powered during the power reduction mode, having a data input for coupling to an output node of the data storage element, and having a retention input coupled to a retention node that is toggled from a first state to a second state and back to said first state to cause said storage latch to store a state of the data storage element during a normal mode before entering the power reduction mode; and
a retention latch, comprising:
a retention transistor having a first current terminal coupled to said retention node, having a second current terminal coupled to a supply voltage having a same voltage during the power reduction mode as said normal mode, and having a control terminal; and
a retention inverter powered by said retention supply voltage, having an input coupled to said retention node and having an output coupled to said control terminal of said retention transistor.

US Pat. No. 10,340,893

SYSTEMS AND METHODS FOR PROVIDING COMPENSATION OF ANALOG FILTER BANDEDGE RIPPLE USING LPF

Marvell International Ltd...

11. A system for compensating the bandedge ripple of an analog filter, using a low pass filter, the system comprising control circuitry configured to:receive, at the analog filter, a plurality of tones of different frequencies from a tone generator;
measure, an amplitude of each tone in the plurality of tones after each tone is processed by the analog filter;
store the measured amplitudes and frequencies in a database;
measure a bandedge ripple by measuring a difference in amplitude between a first tone and a second tone from the plurality of tones; and
select a low pass filter, from a plurality of low pass filters, based on the measured difference.

US Pat. No. 10,340,892

MULTI-CHANNEL DIGITAL STEP ATTENUATOR ARCHITECTURE

pSemi Corporation, San D...

1. A multi-channel digital step attenuator comprising a two-dimensional array of N channels of B selectable attenuator cells series-connected between an input port and an output port, where N is an integer greater than one and n is a channel number within the N channels, and B is an integer greater than one and b is a bit position within the B selectable attenuator cells, wherein more than one channel of B selectable attenuator cells can be active at one time.

US Pat. No. 10,340,891

DIFFERENTIAL ELLIPTIC FILTER WITH A SINGLE OP-AMP

QUANTENNA COMMUNICATIONS,...

1. A differential elliptic filter circuit comprising:a pair of differential signal inputs;
a differential amplifier including a pair of inputs and differential signal outputs;
an upper pair and a lower pair of inverting feedback paths between a corresponding one the differential signal outputs and an inverting one of the pair of inputs of the differential amplifier, configured to provide two complex conjugate poles of the elliptic filter circuit, and to establish upper and lower virtual grounds at the inputs of the differential amplifier, wherein the upper and lower pair of inverting feedback paths each comprise a capacitor coupled in parallel with series coupled resistors between the corresponding one of the differential amplifier's outputs and the corresponding one of the virtual grounds, to provide complex conjugate poles of a low pass elliptic filter circuit, and the inverting and non-inverting feedforward paths cross-coupled and configured to provide complex conjugate zeros of the low pass elliptic filter circuit;
an upper inverting feedforward path of the inverting feedforward path coupling a passive node of the upper pair of inverting feedback paths to the lower one of the virtual grounds, and a lower inverting feedforward path of the inverting feedforward path coupling a passive node of the lower pair of inverting feedback paths to the upper one of the virtual grounds, and the upper and lower inverting feedforward paths configured to provide two zeros of the elliptic filter circuit; and
an upper non-inverting feedforward path coupling an upper one of the pair of differential signal inputs to the upper one of the virtual grounds, and a lower non-inverting feedforward path coupling a lower one of the pair of differential signal inputs to the lower one of the virtual grounds, to enable positioning of the two zeros of the filter circuit on an imaginary axis of a pole-zero plot of the elliptic filter circuit.

US Pat. No. 10,340,890

HIGH ORDER FILTER CIRCUIT

NUVOTON TECHNOLOGY CORP.,...

1. A high order filter circuit including:a plurality of second order filter units for filtering inputted signals;
a plurality of switch units for connecting the plurality of second order filter units in a cascade to form a high order filter unit when the switch units are closed, and for restoring the high order filter unit to the plurality of second order filter units when the switch units are opened;
an analog-to-digital converter (ADC) having a first working status and a second working status, for detecting peaks of predetermined band signals outputted from the second order filter units and digitalizing the peaks when the ADC is in the first working status, and for detecting and converting the predetermined band signals from the second order filter units to digital signals and outputting the digital signals when the ADC is in the second working status; and
a digital correction unit for comparing the digitalized peaks with a default value and generating comparison results, and according to the comparison results, the digital correction unit generating frequency control signals and working status control signals and sending them as feedbacks respectively to the second order filter units for adjusting their working frequencies and to the ADC for switching its working status.

US Pat. No. 10,340,889

LOW NOISE NON-FOSTER CIRCUIT

HRL Laboratories, LLC, M...

1. A bias circuit for a non-Foster circuit, the non-Foster circuit being coupled in use with a DC power supply, the non-Foster circuit having a pair of transistors, one of the transistors of said pair being coupled to an input of said non-Foster circuit and the other one of the transistors of said pair being coupled to an output of said non-Foster circuit, the bias circuit including:(a) first inductors connected with (i) current carrying electrodes of the one of the transistors coupled to an input of said non-Foster circuit and (ii) said DC power supply;
(b) second inductors connected with (i) current carrying electrodes of the other one of the transistors coupled to an output of said non-Foster circuit and (ii) said DC power supply; and wherein a sum of the inductances of the first inductors is greater than a sum of the inductances of the second inductors.

US Pat. No. 10,340,888

ELASTIC WAVE FILTER, DUPLEXER, AND ELASTIC WAVE FILTER MODULE

MURATA MANUFACTURING CO.,...

1. An elastic wave filter comprising:a piezoelectric substrate;
an IDT electrode provided on the piezoelectric substrate;
a first shield electrode provided on the piezoelectric substrate;
a first insulating film laminated on the piezoelectric substrate and extending onto the first shield electrode;
a first signal terminal provided on the first insulating film;
a second signal terminal provided on the piezoelectric substrate; and
a ground terminal provided on the piezoelectric substrate and connected to a ground potential; wherein
the first shield electrode is not electrically connected to the IDT electrode and the first and second signal terminals;
the first signal terminal is included in the first shield electrode when seen from above; and
one of the first signal terminal and the second signal terminal is an output terminal and the other of the first signal terminal and the second signal terminal is an input terminal.

US Pat. No. 10,340,887

BAND PASS FILTER AND FILTER MODULE

MURATA MANUFACTURING CO.,...

1. A band pass filter comprising:an LC high pass filter including a first input terminal, a first output terminal, a first path connecting the first input terminal and the first output terminal, a first elastic wave resonator and a first capacitor connected in series in the first path, and a first inductor connected between the first path and a ground potential;
an LC low pass filter including a second input terminal, a second output terminal, a second path connecting the second input terminal and the second output terminal, a second elastic wave resonator and a second capacitor connected between the second path and a ground potential, and a second inductor connected in series in the second path; wherein
the LC high pass filter and the LC low pass filter are connected in series;
the first elastic wave resonator includes a first electrode and a piezoelectric first base board in or on which the first electrode is provided;
the second elastic wave resonator includes a second electrode and a piezoelectric second base board in or on which the second electrode is provided; and
a type of the first base board and a type of the second base board are different from each other, and/or a configuration of the first electrode and a configuration of the second electrode are different from each other.

US Pat. No. 10,340,886

CERAMIC SUBSTRATE, LAYERED BODY, AND SAW DEVICE

SUMITOMO ELECTRIC INDUSTR...

1. A ceramic substrate formed of a polycrystalline ceramic and having a supporting main surface,wherein the supporting main surface has a roughness of 0.01 nm or more and 3.0 nm or less in terms of Sa, and
a number of projections and depressions with a height of 1 nm or more in a square region with 50 ?m sides on the supporting main surface is less than 5 on average, and a number of projections and depressions with a height of 2 nm or more in the square region is less than 1 on average.

US Pat. No. 10,340,884

ARRANGEMENT COMPRISING A DMS FILTER AND A STEEP RIGHT EDGE

SnapTrack, Inc., San Die...

1. An arrangement comprising a DMS filter,wherein the DMS filter (DMS) has first and second converters (W1,W2) that are arranged alternately on a piezoelectric substrate between two reflectors (R1, R2) and are each connected to an input or output of the arrangement,
wherein at least one of the transducers (W1, W2) is symmetrically divided into two sub-transducers electrically connected in parallel, and
wherein the sub-transducers are shifted apart from each other by an amount of approximately one half wavelength with respect to their original position in such a way that their signals cancel each other out at a frequency in a stopband.

US Pat. No. 10,340,883

HIGH-FREQUENCY MODULE

MURATA MANUFACTURING CO.,...

1. A high-frequency module comprising:a module substrate;
a surface acoustic wave filter disposed on a main surface of the module substrate and including a piezoelectric substrate and an electrode pattern provided on the piezoelectric substrate;
a resin member covering the surface acoustic wave filter; and
a wiring pattern connected to the electrode pattern and provided in or on the resin member; wherein
the electrode pattern and the wiring pattern are inductively coupled, capacitively coupled, or inductively coupled and capacitively coupled with each other.

US Pat. No. 10,340,882

BULK ACOUSTIC WAVE FILTER

Samsung Electro-Mechanics...

15. A bulk acoustic wave filter, comprising:a first electrode and a second electrode disposed on a substrate;
a piezoelectric layer comprising a piezoelectric material, the piezoelectric layer disposed between the first and second electrodes;
a housing comprising a passive element disposed on one surface thereof, wherein the housing is coupled to the substrate to accommodate the piezoelectric layer, the first electrode and the second electrode;
a second piezoelectric layer having one surface disposed on the second electrode;
a third electrode disposed on the other surface of the second piezoelectric layer;
a first via formed on the other surface of the first electrode;
a second via formed on one surface of the second electrode; and
third and fourth vias formed on the substrate,
wherein one surface of each of the first and third electrodes is in contact with the substrate.

US Pat. No. 10,340,881

BONDED SUBSTRATE, SURFACE ACOUSTIC WAVE ELEMENT, SURFACE ACOUSTIC WAVE DEVICE, AND METHOD OF MANUFACTURING BONDED SUBSTRATE

THE JAPAN STEEL WORKS, LT...

1. A bonded substrate comprising: a quartz substrate; and a piezoelectric substrate which is bonded on or above the quartz substrate and on which a surface acoustic wave propagates, wherein the quartz substrate and the piezoelectric substrate are covalently bonded at an interface.

US Pat. No. 10,340,880

STRUCTURES OF PLANAR TRANSFORMER AND BALANCED-TO-UNBALANCED TRANSFORMER

REALTEK SEMICONDUCTOR COR...

1. A planar transformer structure comprising:a first planar coil comprising a first ring structure, a second ring structure and a connecting section, wherein the connecting section connects the first ring structure and the second ring structure;
a second symmetric planar coil having at least two turns, wherein a range of the second symmetric planar coil partially or entirely overlaps a range of the first ring structure, and an outmost turn of the first ring structure is arranged inside an outmost turn of the second symmetric planar coil; and
a third symmetric planar coil having at least two turns, wherein a range of the third symmetric planar coil partially or entirely overlaps a range of the second ring structure, and an outmost turn of the second ring structure is arranged inside an outmost turn of the third symmetric planar coil;
wherein, a transformer is constituted by the first planar coil and the second planar coil or by the first planar coil and the third planar coil;
wherein a current entering the first ring structure flows through all metal segments of the first ring structure before leaving the first ring structure;
wherein the current flowing in the first ring structure is opposite in direction to a current flowing in the second ring structure.

US Pat. No. 10,340,879

SWITCHING CIRCUIT

RENO TECHNOLOGIES, INC.

3. A semiconductor processing tool comprising:a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and
an impedance matching circuit operably coupled to the plasma chamber, matching circuit comprising:
an RF input configured to be operably coupled to an RF source;
an RF output operably coupled to the plasma chamber;
a first circuit comprising a first variable component providing a first variable capacitance or inductance; and
a second circuit comprising a second variable component providing a second variable capacitance or inductance;
wherein each of the first circuit and the second circuit comprises a plurality of switching circuits configured to provide the first variable capacitance or inductance and the second variable capacitance or inductance, respectively, each of the plurality of switching circuits comprising:
a diode; and
a driver circuit operably coupled to the diode and configured to switch the diode, the driver circuit comprising:
a first switch;
a second switch coupled in series with the first switch; and
a filter circuit that is coupled at a first end between the first switch and the second switch, and is operably coupled at a second end to the diode;
a first driver operably coupled to the first switch;
a second driver operably coupled to the second switch; and
a third driver operably coupled to the first and second drivers, the third driver configured to:
provide a first signal to the first driver; and
provide a second driving signal to the second driver;
wherein, in providing the first and second signals, the third driver is configured to increase and decrease a duration of a dead time between (a) the third driver driving the first driver on and the second driver off, or (b) the third driver driving the second driver on and the first driver off.

US Pat. No. 10,340,878

CARRIER AGGREGATION CIRCUIT ALLOWING CARRIER WAVES WITH DIFFERENT FREQUENCIES TO SHARE THE SAME AMPLIFIER

RichWave Technology Corp....

1. A carrier aggregation circuit comprising:a signal input terminal configured to receive a radio frequency signal having a first carrier wave with a first carrier wave frequency and a second carrier wave with a second carrier wave frequency;
a signal output terminal;
a first filter coupled between the signal input terminal and the signal output terminal, configured to filter out signals with frequencies other than the first carrier wave frequency, and having an input terminal and an output terminal;
a first output transform circuit coupled between the output terminal of the first filter and the signal output terminal, and having an output impedance effectively equivalent to an open circuit at the second carrier wave frequency;
a second filter coupled between the signal input terminal and the signal output terminal, configured to filter out signals with frequencies other than the second carrier wave frequency, and having an input terminal and an output terminal; and
a second output transform circuit coupled between the output terminal of the second filter and the signal output terminal, and having an output impedance effectively equivalent to an open circuit at the first carrier wave frequency.

US Pat. No. 10,340,877

ANTENNA MATCHING CIRCUIT, ANTENNA DEVICE, AND COMMUNICATION TERMINAL APPARATUS

MURATA MANUFACTURING CO.,...

1. An antenna matching circuit comprising:an impedance converter circuit connected to a feeder circuit; and
an impedance-conversion-ratio adjustment circuit connected between the impedance converter circuit and an antenna port; wherein
the impedance converter circuit includes a first inductance element and a second inductance element that are coupled to each other through magnetic fields, a first end of the first inductance element is connected to the feeder circuit, a first end of the second inductance element is connected to a second end of the first inductance element, and a second end of the second inductance element is connected to ground;
the impedance-conversion-ratio adjustment circuit includes a third inductance element that is series-connected between the impedance converter circuit and the antenna port, and a capacitance element that is shunt-connected between the antenna port and ground, and the impedance-conversion-ratio adjustment circuit corrects an impedance conversion ratio of the impedance converter circuit in accordance with a frequency band; and
a first end of the third inductance element is directly connected to the impedance converter circuit, and a second end of the third inductance element is directly connected to the antenna port.

US Pat. No. 10,340,876

TUNABLE AND INTEGRATED IMPEDANCE MATCHING AND FILTER CIRCUIT

pSemi Corporation, San D...

1. A combined tunable impedance matching and filtering circuit including:(a) a coupled merged inductor having at least three ports, including an input port configured to receive an input signal and having a first characteristic impedance, an output port configured to output a filtered impedance matched output signal and having a second characteristic impedance, and at least one internal port situated between the input port and the output port, wherein the at least one internal port has a corresponding characteristic impedance;
(b) a plurality of tuning circuits, each electrically connected to a corresponding one of the at least three ports of the coupled merged inductor; and
(c) at least one filter circuit, each configured as a notch filter electrically connected to at least one internal port of the coupled merged inductor and comprising circuit components distinct from the plurality of tuning circuits, configured to filter selected radio frequencies at the corresponding characteristic impedance of the at least one internal port.

US Pat. No. 10,340,875

ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. An electronic component comprising:a laminate including a plurality of insulator layers laminated in a lamination direction; and
a first LC parallel resonator, a second LC parallel resonator, and a third LC parallel resonator; wherein
the first LC parallel resonator includes a first inductor and a first capacitor;
the third LC parallel resonator includes a third inductor and a third capacitor;
the second LC parallel resonator includes a second inductor and a second capacitor coupled to each other in parallel;
the first inductor and the third inductor respectively include a first inductor conductor and a third inductor conductor that are wound when viewed in a plan view from the lamination direction;
the second capacitor includes a second capacitor conductor and a second ground conductor that face each other;
the second inductor includes a second inductor conductor that includes a first coupling portion and a second coupling portion, the first coupling portion being electrically coupled to the second capacitor conductor, the second coupling portion being electrically coupled to the second ground conductor;
a first region surrounded by the first inductor conductor and the second inductor conductor is smaller in area than a second region surrounded by the third inductor conductor and the second inductor conductor when viewed in the plan view from the lamination direction; and
a second region forming portion and a first region forming portion are electrically coupled in series in this order on a path from the first coupling portion to the second coupling portion, the second region forming portion being included in the second inductor conductor and surrounding the second region, the first region forming portion being included in the second inductor conductor and surrounding the first region.

US Pat. No. 10,340,874

FILTER CIRCUIT, RF FRONT END CIRCUIT, AND COMMUNICATION APPARATUS

MURATA MANUFACTURING CO.,...

1. A filter circuit comprising:a fixed filter having a pass band that overlaps with a frequency band corresponding to a predetermined communication signal; and
a tunable filter having a stop band that is frequency-tunable, the stop band having a frequency tuning range that covers a frequency band adjacent to the frequency band corresponding to the predetermined communication signal,
wherein the fixed filter and the tunable filter are connected in series,
wherein the tunable filter comprises a first tunable filter and a second tunable filter,
wherein the first tunable filter has a stop band, the stop band having a frequency tuning range that covers a frequency band located adjacent to and on a high frequency side of the frequency band corresponding to the predetermined communication signal, and
wherein the second tunable filter has a stop band, the stop band having a frequency tuning range that covers a frequency band located adjacent to and on a low frequency side of the pass band of the fixed filter.

US Pat. No. 10,340,873

BAND PASS FILTER AND LAMINATE BAND PASS FILTER

MURATA MANUFACTURING CO.,...

1. A band pass filter comprising:a first input/output terminal;
a second input/output terminal;
a ground terminal; and
a plurality of LC parallel resonators; wherein
an inductor and a capacitor are connected in parallel with each other in each of the plurality of LC parallel resonators;
the plurality of LC parallel resonators include:
an LC parallel resonator at a first input/output stage;
at least one LC parallel resonator at an intermediate stage; and
an LC parallel resonator at a second input/output stage; wherein
one end of the LC parallel resonator at the first input/output stage, one end of the at least one LC parallel resonator at the intermediate stage, and one end of the LC parallel resonator at the second input/output stage are sequentially connected between the first input/output terminal and the second input/output terminal;
another end of the LC parallel resonator at the first input/output stage, another end of the at least one LC parallel resonator at the intermediate stage, and another end of the LC parallel resonator at the second input/output stage are connected to the ground terminal;
the inductors of adjacent LC parallel resonators of the plurality of LC parallel resonators are magnetically coupled to one another;
the inductor of the at least one LC parallel resonator at the intermediate stage is divided into a first inductor and a second inductor connected in parallel with each other; and
the first inductor is magnetically coupled to the inductor of one of the adjacent LC parallel resonators, and the second inductor is magnetically coupled to the inductor of another of the adjacent LC parallel resonators.

US Pat. No. 10,340,872

AUDIO FILTER DEVICE FOR ELECTRONIC INTERFERENCE WITH AUDIO SIGNALS

1. An audio filter device connected between a source of audio signals and a device with an audio signal input, comprising:a common ground wire to which the audio signals are referenced,
a passive band pass filter requiring no external power, with input from the source of audio signals and output to the device with an audio signal input,
where the band pass filter consists of a high-pass R-C filter consisting of a 80 pF capacitor and a 10 kOhm resistor, and a low-pass R-C filter consisting of a 10 kOhm resistor and a 150 pF capacitor,
and an additional 1 kOhm resistor connected between the output of the band pass filter and the common ground wire.

US Pat. No. 10,340,871

COMPACT BYPASS AND DECOUPLING STRUCTURE FOR MILLIMETER-WAVE CIRCUITS

QUALCOMM Incorporated, S...

1. A radio frequency integrated circuit, comprising:a grounded substrate;
a mid-metal ground plane;
a bypass capacitor disposed between the grounded substrate and the mid-metal ground plane, the bypass capacitor configured to close a current loop in the radio frequency integrated circuit; and
a decoupling inductor disposed over the mid-metal ground plane, the decoupling inductor configured to provide damping in a supply network associated with the radio frequency integrated circuit.

US Pat. No. 10,340,870

TRANSFORMING AUDIO CONTENT FOR SUBJECTIVE FIDELITY

WARNER BROS. ENTERTAINMEN...

1. A method for processing an audio signal, comprising:receiving, by a hardware processor for an audio player device, an encoded audio signal for content comprising at least one of music or an audio track for video content;
identifying, by the hardware processor based on metadata of the encoded audio signal, a person and an audiometric reference profile for the person representing the person's hearing acuity at multiple frequencies;
receiving, by the hardware processor based on an identifier for one or more users of the audio player device, an audiometric listener profile for the one or more users representing the one or more users' hearing acuity at multiple frequencies; and
transforming, by the hardware processor, the encoded audio signal using the hardware processor into an output audio signal, based on an audiometric difference between the audiometric reference profile and the audiometric listener profile so that the output audio signal compensates for the audiometric difference and enables the one or more users to hear the content more like the person identified by the hardware processor based on metadata of the encoded audio signal.

US Pat. No. 10,340,869

ADJUSTING DYNAMIC RANGE OF AN AUDIO SIGNAL BASED ON ONE OR MORE DYNAMIC EQUALIZATION AND/OR DYNAMIC RANGE CONTROL PARAMETERS

Dolby Laboratories Licens...

2. An apparatus for decoding audio signals, comprising:one or more processors;
memory configured to store instructions, which when executed by the one or more processors, cause the processors to perform operations comprising:
receiving, by a decoding device, encoded audio information and metadata associated with an audio signal, the metadata including one or more dynamic range control (DRC) parameters, and one or more dynamic equalization parameters; and
modifying, by the decoding device, the audio information using the one or more DRC parameter values to adjust the dynamic range of the audio signal in accordance with the dynamic equalization parameters.

US Pat. No. 10,340,868

AMPLIFIER CIRCUIT INCLUDING FIRST INPUT BRANCH CIRCUIT, SECOND INPUT BRANCH CIRCUIT, FEEDBACK CAPACITOR, AND OPERATIONAL AMPLIFIER AND PULSE-WAVE MEASURING DEVICE

PANASONIC INTELLECTUAL PR...

1. An amplifier circuit comprising:a first input branch circuit including a first sampling capacitor that, in operation, samples an input voltage in a first time period and outputs a first voltage;
a second input branch circuit including a second sampling capacitor, an averaging capacitor, and a subtraction capacitor, the second sampling capacitor, in operation, sampling the input voltage in the first time period and outputting a second voltage, the averaging capacitor, in operation, taking an average of the second voltage in the second time period and outputting a third voltage, the subtraction capacitor, in operation, receiving the third voltage in the first time period, the subtraction capacitor, in operation, subtracting the first voltage from the third voltage and outputting a fourth voltage in the second time period;
a feedback capacitor; and
an operational amplifier that is connected to the feedback capacitor and, in operation, amplifies the fourth voltage,
wherein the first time period and the second time period are repeated alternately.

US Pat. No. 10,340,867

AMPLIFIER WITH BUILT IN TIME GAIN COMPENSATION FOR ULTRASOUND APPLICATIONS

Butterfly Network, Inc., ...

1. An ultrasound apparatus, comprising:an ultrasonic transducer to provide an analog electrical signal;
an amplifier having time gain compensation (TGC) functionality coupled to the ultrasonic transducer and configured to receive and amplify the analog electrical signal by a time-dependent amount;
wherein:
the amplifier comprises amplification circuitry and feedback circuitry with a variable impedance; and
the feedback circuitry comprises a plurality of resistors in a series arrangement, and wherein a subset of the plurality of resistors have respective resistance values that increase sequentially in a logarithmic fashion.

US Pat. No. 10,340,866

SINGLE-ENDED TRANS-IMPEDANCE AMPLIFIER (TIA) FOR ULTRASOUND DEVICE

Butterfly Network, Inc., ...

1. An ultrasound apparatus, comprising:an ultrasonic transducer; and
a single-ended trans-impedance amplifier (TIA) having an input terminal coupled to the ultrasonic transducer and configured to receive and amplify an analog electrical signal from the ultrasonic transducer;
wherein:
the ultrasonic transducer is a first ultrasonic transducer and the single-ended TIA is a first single-ended TIA;
the ultrasound apparatus comprises a plurality of ultrasonic transducers including the first ultrasonic transducer and a plurality of respective single-ended TIAs coupled to the respective ultrasonic transducers, the plurality of respective single-ended TIAs including the first single-ended TIA; and
the ultrasound apparatus further comprises:
an averaging circuit having an input coupled to the plurality of respective single-ended TIAs;
a filter and a time gain compensation (TGC) circuit, the filter being coupled electrically between the averaging circuit and the TGC circuit;
an analog-to-digital converter (ADC) coupled to an output terminal of the TGC circuit; and
an ADC driver coupled to the ADC and configured to drive the ADC, the ADC driver comprising a folded cascode super source follower.

US Pat. No. 10,340,865

AMPLIFIER

Kabushiki Kaisha Toshiba,...

1. An amplifier comprising:a pair of current sources;
a plurality of first differential input transistors comprising:
a first plurality of transistors having first ends connected to one of the pair of current sources, and control ends to which positive a phase input signal is inputted, and
a second plurality of transistors respectively constituting differential pairs with the first plurality of transistors, the second plurality of transistors having first ends connected to the other of the pair of current sources, and control ends to which negative a phase input signal is inputted;
a plurality of second differential input transistors comprising:
a third plurality of transistors having first ends connected to one of the pair of current sources, and control ends to which the positive phase input signal is inputted, and
a fourth plurality of transistors respectively constituting differential pairs with the third first plurality of transistors, the fourth plurality of transistors having first ends connected to the other of the pair of current sources, and control ends to which the negative phase input signal is inputted, the number of the second plurality of differential input transistors being the same as the number of the number of the first differential input transistors;
a plurality of resistance adjusting transistors having first ends respectively connected to second ends of the plurality of first differential input transistors, second ends connected to reference potential points, and control ends to which control signals are inputted;
a plurality of wirings that connect the second ends of the plurality of first differential input transistors that constitute the differential pairs of the plurality of first differential input transistors;
a plurality of linearity improving transistors having first ends respectively connected to second ends of the plurality of second differential input transistors, second ends connected to the reference potential points, and control ends to which the control signals are inputted; and
a control circuit configured to change a linearity improvement effect while controlling an operating point, by supplying the control signals to the control ends of the plurality of resistance adjusting transistors and to the control ends of the plurality of linearity improving transistors.

US Pat. No. 10,340,864

TRANSMITTER CIRCUIT AND METHOD FOR CONTROLLING OPERATION THEREOF

Infineon Technologies AG,...

1. A method for controlling the operation mode of a transmitter circuit, the method comprising:detecting a state of a message field within a data message to be sent by the transmitter circuit indicating a bit rate to be used for transmission by the transmitter circuit;
switching the mode of operation of the transmitter circuit from a first data transmission mode to a second data transmission mode using a switching signal;
wherein a terminating resistor is coupled between a first transmission line and a second transmission line and wherein the first transmission line and the second transmission line form a pair of conductors for differential signaling;
wherein, when the switching signal indicates the switching mode of operation is the first data transmission mode, a first circuit configured to transmit data is used, the first circuit being configured to provide a first transmission value of the differential signaling by applying a potential between a first conductor that is coupled to a first transmission line and a second conductor that is coupled to the second transmission line, wherein the potential is determined by the terminating resistor coupled between the first transmission line and the second transmission line, and a second transmission value of the differential signaling by applying a first reference potential to the first conductor and a second reference potential, which is different from the first reference potential, to the second conductor; and
wherein, when the switching signal indicates the switching mode of operation is the second data transmission mode, a second circuit configured to transmit data is used, the second circuit being configured to provide the first transmission value of the differential signaling by applying a third reference potential to the first conductor and a fourth reference potential to the second conductor, and the second transmission value of the differential signaling by applying the fourth reference potential to the first conductor and the third reference potential to the second conductor; wherein a logic gate is configured to output a second output signal to control the second circuit.

US Pat. No. 10,340,863

POWER AMPLIFIER MODULE

MURATA MANUFACTURING CO.,...

1. A power amplifier module comprising:an output-stage amplifier;
a driver-stage amplifier that is connected to an input of the output-stage amplifier;
an input switch configured to selectively connect one of a plurality of input signal paths to an input of the driver-stage amplifier;
an output switch configured to selectively connect one of a plurality of output signal paths to an output of the output-stage amplifier;
an input matching circuit configured to connect the input switch and the driver-stage amplifier;
an inter-stage matching circuit configured to connect the driver-stage amplifier and the output-stage amplifier;
an output matching circuit configured to connect the output-stage amplifier and the output switch; and
a control circuit configured to control the input switch, the output switch, the driver-stage amplifier, and the output-stage amplifier, wherein
the input switch, the output switch, and the control circuit are integrated into a first integrated circuit (IC) chip, and
the control circuit is physically arranged between the input switch and the output switch.

US Pat. No. 10,340,862

METHODS FOR POWER AMPLIFICATION WITH SHARED COMMON BASE BIASING

Skyworks Solutions, Inc.,...

1. A method of power amplification at a controller of a power amplification system comprising a plurality of cascode amplifier sections, the method comprising:receiving a band select signal indicative of one or more frequency bands of a radio-frequency input signal to be amplified and transmitted;
biasing a common base stage of each of the plurality of cascode amplifier sections based on the received band select signal, including sending a respective control signal to a respective common base biasing component coupled to a respective common base stage of each respective one of the plurality of cascode amplifier sections; and
biasing a common emitter stage of a subset of the plurality of cascode amplifier sections.

US Pat. No. 10,340,861

APPARATUS AND METHODS FOR LOW NOISE AMPLIFIERS

Skyworks Solutions, Inc.,...

1. A wireless communication device comprising:a low noise amplifier including a mode control circuit configured to operate the low noise amplifier in a selected mode chosen from a plurality of modes including a first gain mode and a bypass mode, a first gain circuit electrically connected between an input terminal and an output terminal and operable to provide inverting amplification to a radio frequency input signal received at the input terminal in the first gain mode, and a bypass circuit electrically connected in parallel with the first gain circuit between the input terminal and the output terminal, the bypass circuit including a balun operable to provide an inversion to the radio frequency input signal in the bypass mode so as to compensate for a difference in phase delay between the bypass circuit and the first gain circuit; and
an antenna configured to provide the radio frequency input signal to the low noise amplifier.

US Pat. No. 10,340,860

MULTI-MODE LOW NOISE AMPLIFIER

QUALCOMM Incorporated, S...

1. A circuit, comprising:a passive low gain low noise amplifier (LNA) configured to receive a communication signal;
an active low gain LNA configured to receive the communication signal;
a shared coupling circuit, outputs of the passive low gain LNA and the active low gain LNA coupled to the shared coupling circuit;
an output circuit, an output of the shared coupling circuit coupled to the output circuit; and
a high gain LNA configured to receive the communication signal, the high gain LNA coupled to the output circuit along a path that bypasses the shared coupling circuit.

US Pat. No. 10,340,859

CLASS-D POWER AMPLIFIER NESTED INSIDE LOW-NOISE DIFFERENTIAL OP-AMP FEEDBACK LOOP

Tymphany HK Limited, Wan...

1. An amplifier system, comprising:a power amplifier integrated circuit;
a differential operational amplifier; and
a current drive circuit,
wherein the power amplifier integrated circuit is nested within at least one feedback loop of the differential operational amplifier, and
wherein the current drive circuit is connected between the differential operational amplifier and an input.

US Pat. No. 10,340,858

LINEARIZED DISTRIBUTED AMPLIFIER ARCHITECTURE

Qorvo US, Inc., Greensbo...

1. A distributed amplifier (DA) comprising:a first plurality of inductive elements coupled in series between an output termination input and a DA output to form a first plurality of connection nodes, such that each of the first plurality of connection nodes is coupled to a corresponding adjacent pair of the first plurality of inductive elements;
a second plurality of inductive elements coupled in series between a DA input and an input termination input to form a second plurality of connection nodes, such that each of the second plurality of connection nodes is coupled to a corresponding adjacent pair of the second plurality of inductive elements; and
a plurality of amplifier cells, such that each of the plurality of amplifier cells comprises:
a main transistor having a first current output terminal coupled to a fixed voltage node, a first current input terminal, and a first control terminal;
a cascode transistor having a second current output terminal coupled to the first current input terminal, a second current input terminal coupled to a corresponding one of the first plurality of connection nodes, and a second control terminal configured to bias the cascode transistor;
an input transistor having a third current output terminal coupled to the first control terminal of the main transistor, a third control terminal coupled to a corresponding one of the second plurality of connection nodes, and a third current input terminal configured to bias the input transistor; and
current source circuitry coupled between the third current output terminal and a DA bias terminal.

US Pat. No. 10,340,857

AMPLIFIER CIRCUIT

TOSHIBA MEMORY CORPORATIO...

1. An amplifier circuit comprising:a first differential amplifier circuit including a first transistor having a gate to which a first signal is input, a second transistor having a gate to which a second signal is input, a first electric current source that supplies an electric current to the first and second transistors, and a second electric current source that is configured to supply an electric current to the first and second transistors via a first switch element;
a second differential amplifier circuit including a third transistor having a gate to which the first signal is input, a fourth transistor having a gate to which the second signal is input, a third electric current source that supplies an electric current to the third and fourth transistors, and a fourth electric current source that is configured to supply an electric current to the third and fourth transistors via a second switch element;
a detection circuit which outputs a third signal based on the first and second signals; and
a first inverter coupled between an output node of the third signal, and the second switch element,
wherein the first switch element is controlled by the third signal, the second switch element is controlled by a fourth signal, and the third signal and the fourth signal are complementary.

US Pat. No. 10,340,856

RESONANCE MITIGATION IN RF HIGH POWER AMPLIFIER ENCLOSURE

CENTRE FOR DEVELOPMENT OF...

1. A radio frequency high power Amplifier (RFPA) configured in an enclosure, wherein the enclosure is further configured with a metallic post positioned at a suitable location with respect to the RFPA to dampen and shift out resonance, and wherein the suitable location is determined by:evaluating electric field generated by other components of the RFPA;
evaluating poynting vector which is proportional to square of the electric field; and
determining the suitable location inside the enclosure of the RFPA where the poynting vector is maximum.

US Pat. No. 10,340,855

DOHERTY AMPLIFIER

Mitsubishi Electric Corpo...

1. A Doherty amplifier comprising:division circuitry configured to split, between a first transmission line and a second transmission line, a signal to be amplified;
first amplifier circuitry inserted into the first transmission line;
second amplifier circuitry inserted into the second transmission line; and
a power combiner configured to combine signals amplified by the first and second amplifier circuitry,
wherein the division circuitry includes
a first filter to which the signal to be amplified is input,
a second filter connected between the first filter and the first amplifier circuitry,
a third filter to which the signal to be amplified is input,
a fourth filter connected between the third filter and the second amplifier circuitry, and
a resistor connected to an output side of the first filter and an output side of the third filter,
wherein each of the first and third filters is a low-pass filter while each of the second and fourth filters is a high-pass filter, or wherein each of the first and third filters is a high-pass filter while each of the second and fourth filters is a low-pass filter, and
wherein, when each of the low-pass filters is formed by a ?-type circuit, each of the high-pass filters is formed by a T-type circuit, and when each of the low-pass filters is formed by a T-type circuit, each of the high-pass filters is formed by a ?-type circuit.

US Pat. No. 10,340,854

SELECTING BETWEEN BOOSTED SUPPLY AND BATTERY SUPPLY

QUALCOMM Incorporated, S...

1. An envelope tracking power supply, comprising:a linear amplifier having an output coupled to a power supply node of an amplifier, wherein a power supply node of the linear amplifier is coupled to a first voltage supply node over a first path;
a switch mode power supply (SMPS) having an output coupled to the power supply node of the amplifier; and
a circuit having a first switch coupled to the first voltage supply node and a second switch coupled to a second voltage supply node, wherein a power supply node of the SMPS is coupled to the first switch and the second switch at an output of the circuit over a second path, the first path being separate from the second path, and the output of the SMPS being separate from the second path.

US Pat. No. 10,340,853

RADIO FREQUENCY RECEIVING CIRCUIT AND RADIO FREQUENCY RECEIVER

SHENZHEN JOINTWAY IC DESI...

1. A radio frequency receiving circuit, comprising:a tail current source, configure to be multiplexed to input radio frequency signals and amplify the radio frequency signals for producing a radio frequency current;
a clock signal input unit, in connection with the tail current source and configured to input clock signals;
a sampling-and-holding unit, in connection with the clock signal input unit and configured to output an orthogonal signal having a frequency of one half of a clock frequency; and
a load unit, in connection with the sampling-and-holding unit, wherein the radio frequency current flowing through the load unit is converted into a voltage which is modulated by the orthogonal signal, and a medium frequency signal having a frequency equivalent to a difference between a radio frequency signal frequency and an orthogonal signal frequency is output.

US Pat. No. 10,340,852

BIAS BOOSTING CIRCUIT FOR AMPLIFIER

NORTHROP GRUMMAN SYSTEMS ...

1. An amplification system comprising:an amplifier comprising a field effect transistor (FET) that amplifies an input signal to drive a load and an amplifier transistor; and
a bias boosting circuit comprising:
a negative bias booster that applies a charge to an input node of the amplifier in response to a negative half-cycle of the input signal that exceeds a boost threshold level, wherein the negative bias booster includes a negative bias boost transistor;
a positive bias booster that discharges the input node of the amplifier during a positive half-cycle of the input signal that exceeds the boost threshold level, wherein the discharging by the positive bias booster is slower than the charging by the negative bias booster to induce a bias voltage increase from a quiescent bias voltage on the input node of the amplifier, wherein the positive bias booster includes a positive bias boost transistor;
a biasing node that couples the negative bias booster and the positive bias booster;
an impedance block that couples the biasing node to the input node, wherein the impedance block comprising a resistive component and an inductive component; and
wherein a channel width of the negative bias boost transistor and a channel width of the positive bias boost transistor are smaller than a channel width of the amplifying transistor and a source impedance of the negative bias boost transistor is smaller than a drain impedance of the positive bias boost transistor.

US Pat. No. 10,340,851

DIFFERENTIAL CASCODE AMPLIFIER WITH SELECTIVELY COUPLED GATE TERMINALS

QUALCOMM Incorporated, S...

1. An apparatus comprising:a differential cascode amplifier comprising a first cascode transistor and a second cascode transistor;
a transistor including:
a source terminal coupled to a gate terminal of the first cascode transistor of the differential cascode amplifier;
a drain terminal coupled to a gate terminal of the second cascode transistor of the differential cascode amplifier; and
a terminal configured to receive an enable signal, the transistor configured to selectively couple the gate terminal of the first cascode transistor to the gate terminal of the second cascode transistor based on the enable signal having a first value, the transistor further configured to substantially isolate the gate terminal of the first cascode transistor from the gate terminal of the second cascode transistor responsive to the enable signal having a second value;
a first high impedance element coupled to the source terminal of the transistor, wherein the first high impedance element comprises a first resistor or a first inductor; and
a second high impedance element coupled to the first high impedance element and to the drain terminal, wherein the second high impedance element comprises a second resistor or a second inductor.

US Pat. No. 10,340,850

CRYSTAL OSCILLATOR DEVICE AND METHOD OF MEASURING CRYSTAL OSCILLATOR CHARACTERISTIC

FUJITSU LIMITED, Kawasak...

1. A crystal oscillator device, comprising:a crystal oscillator including a casing, a crystal piece, a pair of excitation electrodes configured to excite a main vibration, and a pair of sub vibration electrodes configured to excite a sub-vibration; and
an alarm generator configured to generate an alarm based on a signal whose amplitude is equal to or less than a reference value, the signal being generated in the sub vibration electrodes.

US Pat. No. 10,340,849

DIAGNOSIS SYSTEM AND DIAGNOSIS METHOD FOR PHOTOVOLTAIC POWER GENERATION SYSTEM

Hitachi, Ltd., Tokyo (JP...

1. A diagnosis system for a photovoltaic power generation system, comprising:a power collection unit configured to couple a plurality of photovoltaic cell arrays, each including a plurality of photovoltaic cells, in parallel;
a control unit coupled to the power collection unit; anda monitoring unit configured to diagnose the photovoltaic power generation system,the control unit comprising:
a first current measurement apparatus configured to measure a current of the plurality of photovoltaic cell arrays input from the power collection unit; and
a first voltage measurement apparatus configured to measure a voltage of the plurality of photovoltaic cell arrays input from the power collection unit,
the control unit being configured to control a current and a voltage to be output so that power becomes maximum based on a current value measured by the first current measurement apparatus and a voltage value measured by the first voltage measurement apparatus,
the power collection unit comprising a plurality of second current measurement apparatuses each respectively configured to measure currents of the plurality of photovoltaic cell arrays,
the monitoring unit comprising:
a storage unit configured to hold the current value measured by the first current measurement apparatus, the voltage value measured by the first voltage measurement apparatus, and current values measured by the plurality of second current measurement apparatuses; and
a computing unit coupled to the storage unit,
the computing unit being configured to:
estimate a solar radiation amount and an operating temperature of the plurality of photovoltaic cell arrays based on the current value measured by the first current measurement apparatus and the voltage value measured by the first voltage measurement apparatus by using an expression expressing a relationship between the solar radiation amount, the operating temperature, and a number of photovoltaic cells, and an output current;
correct the estimated solar radiation amount and the estimated operating temperature to values matching the current values measured by the plurality of second current measurement apparatuses based on the current value measured by the first current measurement apparatus and the current values measured by the plurality of second current measurement apparatuses by using the expression; and
calculate a theoretical value of the current of each of the plurality of photovoltaic cell arrays based on the corrected solar radiation amount and the corrected operating temperature by using the expression.

US Pat. No. 10,340,848

I-V MEASUREMENT DEVICE FOR SOLAR CELL, MANUFACTURING METHOD FOR SOLAR CELL, AND SOLAR CELL MODULE

KANEKA CORPORATION, Osak...

1. An I-V measurement device for a solar cell comprising an I-V measurement section that is configured to supply current to the solar cell to perform I-V measurement, whereinthe I-V measurement section includes a flexible metal foil to be in direct, detachable contact with the solar cell under pressure during the I-V measurement,
at least a portion of the flexible metal foil to be in contact with the solar cell, the flexible metal foil is formed of at least one selected from the group consisting of Sn, Ag, Ni, In and Cu,
the flexible metal foil has an opening, and
the solar cell is suctioned via the opening such that a transparent electrode on a second surface side of the solar cell is pressed against the flexible metal foil.

US Pat. No. 10,340,847

POWER SUPPLY CONTROL CIRCUIT, ENERGY HARVESTING DEVICE, AND CONTROL METHOD OF ENERGY HARVESTING DEVICE

FUJITSU LIMITED, Kawasak...

1. A power supply control circuit comprising:a power supply control switch provided between a load and a capacitor which stores power from an energy harvester in which a plurality of power generation cells are coupled in series and supplies stored power to the load and configured to select whether or not to supply the stored power in the capacitor to the load; and
a controller configured to control the power supply control switch based on a first potential extracted from a first coupling node of the plurality of power generation cells and a second potential extracted from a second coupling node different from the first coupling node,
wherein the capacitor is coupled between first and second power supply lines, and the power supply control switch and the load are coupled in series between the first and second power supply lines.

US Pat. No. 10,340,846

PHOTOVOLTAIC JUNCTION BOX

Tyco Electronics (Shangha...

1. A photovoltaic junction box, comprising:a base having a receiving chamber with a peripheral edge surrounding the receiving chamber and a plurality of slots disposed on an outer side of the receiving chamber;
a cover fully mounted on the base closing the receiving chamber, the cover having a plurality of resilient protrusions formed on a side of the cover and extending from a peripheral edge of the cover, a portion of the cover disposed between the plurality of resilient protrusions extends beyond the peripheral edge of the cover in a plane of the cover and overlays the peripheral edge of the base when the cover is mounted on the base; and
a plurality of ventilation passageways disposed between the peripheral edge of the cover and the peripheral edge of the receiving chamber, the plurality of ventilation passageways integrally formed in at least one of the peripheral edge of the cover and the peripheral edge of the receiving chamber and extending along an entirety of each of a pair of opposite sides of at least one of the peripheral edge of the cover and the peripheral edge of the receiving chamber, the plurality of ventilation passageways communicating between the receiving chamber and an area external of the photovoltaic junction box when the cover is fully mounted on the base.

US Pat. No. 10,340,845

POWER STORAGE SYSTEM, VOLTAGE TRANSFORMER AND POWER STORAGE POWER CONDITIONER

OMRON Corporation, Kyoto...

1. A power storage system comprising:a voltage transformer; and
a power storage power conditioner,
wherein the voltage transformer comprises
a first input part to which direct-current power output from a power generator is input,
a first voltage transform part that transforms a voltage of the direct-current power input to the first input part into a first predetermined voltage, and
a first output part that outputs the direct-current power transformed into the first predetermined voltage to the power storage power conditioner,
wherein the power storage power conditioner comprises
a second input part to which the direct-current power output from the first output part is input,
a second voltage transform part that transforms the first predetermined voltage of the direct-current power input to the second input part into a second predetermined voltage,
a first input and output part that outputs the direct-current power transformed into the second predetermined voltage to a battery unit and to which direct-current power is input from the battery unit,
a conversion part that converts the direct-current power input to the second input part into alternating-current power, and
a second input and output part that outputs the alternating-current power to a power system or a load and to which alternating-current power is input from the power system,
wherein the conversion part converts the alternating-current power input to the second input and output part into direct-current power,
wherein the second voltage transform part transforms a voltage of the direct-current power converted by the conversion part into the second predetermined voltage and transforms a voltage of the direct-current power input to the first input and output part into a third predetermined voltage, and
wherein the conversion part converts the direct-current power transformed into the third predetermined voltage by the second voltage transform part into alternating-current power.

US Pat. No. 10,340,844

HIGH-PERFORMANCE PLANAR SOLAR CONCENTRATORS BASED ON NANOPARTICLE DOPING

WASHINGTON STATE UNIVERSI...

1. A light scattering-based solar concentrator (LSSC) for photovoltaic (PV) applications, comprising:a plurality of solar cells;
dielectric oxide nanoparticles (NPs) having a refractive index greater than 2.0 dispersed in a binder formed as a waveguide attached to the plurality of solar cells,
wherein the NPs are confined to a central scattering layer sandwiched between non-scattering layers within the waveguide and said non-scattering layers do not contain NPs,
said LSSC having at least one layer of nanostructure combining anti-reflective and light trapping on a surface toward an inside of the waveguide to reduce photon surface loss, and
one or more reflectors are attached to one or more surfaces of the waveguide to reflect transmitted light,
wherein the LSSC has a device concentration ratio C>1 and a device power conversion efficiency (?SC) from 5.26% to 7.58%, where C is the device concentration ratio, which is the ratio between output electrical power from the solar concentrator (PSC) and the output electrical power of the solar cells (Pcell) under the same incident condition as defined by the following equation:
where G is device geometric gain and is defined as the ratio between ASC and Acell, where ASC is top surface area of the device and Acell is the area of the solar cells, P is device optical efficiency defined as the ratio between the device power conversion efficiency (?SC) and the cell conversion efficiency (?cell), and Hin is the incident power density.

US Pat. No. 10,340,843

SOLAR PANEL WITH FLEXIBLE OPTICAL ELEMENTS

Airbus Defence and Space ...

1. A solar array for a spacecraft, comprising:a solar concentrator that is provided with photovoltaic cells and reflective areas configured for reflecting solar radiation towards the photovoltaic cells, wherein the reflective areas and the photovoltaic cells are provided on opposite surfaces of concentrator reflector sheet members, which are repositionable from a retracted state wherein the concentrator reflector sheet members are in a substantially flat arrangement, to an extended state wherein the concentrator reflector sheet members are raised to allow the reflective areas to reflect solar radiation towards the exposed photovoltaic cells, and
a support panel defining a mounting surface onto which the concentrator reflector sheet members are attached so that the support panel and concentrator reflector sheet members form an assembly, the concentrator reflector sheet members being flexible to allow bending away from the support panel to assume the extended state;
wherein the support panel has a planar shape in mechanical equilibrium corresponding to a deployed state of the solar array, said planar shape enabling the concentrator reflector sheet members to assume the extended state wherein the reflective areas extend in a linearly symmetric manner along the support panel and are co-aligned so that parallel light rays from the sun that impinge on said reflective areas are reflected and concentrated towards parallel focal lines and towards the exposed photovoltaic cells;
and wherein the support panel is elastically bendable into a curved shape corresponding to a stowed state of the solar array and a retracted state of the concentrator reflector sheet members, said curved shape providing geometrical stiffness and an increased resonance frequency of the assembly.

US Pat. No. 10,340,842

MULTI-ORTHOGONAL PHOTONIC ENERGY COLLECTION SYSTEM

Jesse Timron Brown, Masp...

1. A solar cell module for collecting incident light, comprising:A housing with a clear top;
A solar cell within the housing and including at least one collection surface that is oriented normal to the clear top; and
A refracting medium provided within the housing and surrounding the solar cell, the refracting medium refracts incident light entering the module in all directions within the refracting medium,
Wherein the solar cell comprises a coiled configuration including the at least one collection surface extending along the length thereof.

US Pat. No. 10,340,841

DUAL AXIS SOLAR PANEL TRACKING COMPLETE MECHANICAL ARRANGEMENT

GOVERNMENT COLLEGE OF TEC...

1. A dual axis solar panel tracking complete mechanical arrangement comprising:a base frame assembly (1);
a middle frame assembly (2), wherein the middle frame assembly (2) comprises a tube assembly (2a), two middle frames (2b), two middle frame supports (2c) and a mounting flange (2d);
a top frame assembly (3);
one or more photovoltaic (PV) panels;
a first slewing drive (4); and
one or more second slewing drives (11);
wherein the base frame assembly (1) comprises a base plate (1a) fitted with a base vertical tube (1b),
wherein one or more bush bearings (5) are fitted to the base vertical tube (1b) for the distribution of the radial load of the structure comprising the photovoltaic (PV) panels mounted on the top frame assembly (3) fitted to the middle frame assembly (2),
wherein the upper end of the base vertical tube (1b) is closed by a thrust bearing mounting plate (7) to mount a thrust bearing (8) to transmit the entire axial load of the structure comprising the photovoltaic (PV) panels mounted on the top frame assembly (3) fitted to the middle frame assembly (2),
wherein the middle frame assembly (2) comprises a tube assembly (2a) having tube (2a1) with inside diameter providing a sliding fit with the bush bearings (5) mounted on the base vertical tube (1b),
wherein the upper end of the tube (2a1) is closed by a steel plate (2a2), the bottom portion of which rests on the thrust bearing (8) on mounting of the middle frame assembly (2) on the base frame assembly (1),
wherein a mounting flange (2d) is rigidly fitted at the lower end of the tube (2a1) to connect the middle frame assembly (2) with the first slewing drive (4) fitted on the base frame assembly (1) fitted with a flange (1d),
wherein a plurality of bearing blocks (9), each fitted with a bearing, are mounted on the middle frame (2b) of the middle frame assembly (2) to support the oscillatory motion of the top frame assembly (3),
wherein the top frame assembly (3) is constructed with one or more trusses (3a) fitted with a plurality of C-frames (3b) and are detachably mounted on tubular longitudinal member (3c),
wherein a drive coupling flange (10) is fitted at the drive end of the tubular longitudinal member (3c) to drivingly connect the top frame assembly (3) to the one or more second slewing drives (11),
wherein the top frame assembly (3) supports the photovoltaic (PV) panels and wherein the motors of the first slewing drive (4) and one or more second slewing drives (11) are connected to a control arrangement to provide required oscillatory movement to the middle frame assembly (2) and the top frame assembly (3) carrying the photovoltaic (PV) panels.

US Pat. No. 10,340,840

OSCILLATION BRAKE FOR SOLAR TRACKING SYSTEM

SolarCity Corporation, S...

1. A solar-tracking photovoltaic array, comprising:a torque tube having a first end and a second end opposite the first end;
a plurality of photovoltaic modules coupled with and distributed along the torque tube;
a locking mechanism coupled with and configured to prevent movement of the first end of the torque tube; and
an orientation motor coupled with the second end of the torque tube,
wherein the locking mechanism releases the first end of the torque tube during actuation of the orientation motor.

US Pat. No. 10,340,839

DYNAMIC DAMPING SYSTEM FOR SOLAR TRACKERS

SolarCity Corporation, S...

1. A solar-tracking photovoltaic array, comprising:a torque tube having a first end and a second end opposite the first end;
a plurality of photovoltaic modules supported by the torque tube;
an orientation motor mechanically coupled to the torque tube and configured to rotate the torque tube in a manner that keeps the plurality of photovoltaic modules oriented towards the sun;
a sensor configured to provide data corresponding to angular rotation of the second end of the torque tube;
a controller that in response to receiving data from the sensor indicative of oscillations of the torque tube commands the orientation motor to move the torque tube to dampen the oscillations.

US Pat. No. 10,340,838

HYBRID SOLAR PANEL MOUNTING ASSEMBLY WITH A TILTED LEDGE

Unirac Inc., Albuquerque...

1. A trim-rail for use in a solar panel mounting assembly, comprising:a first vertical wall;
a horizontal wall intersecting with the first vertical wall;
a second vertical wall intersecting with the horizontal wall and extending downwardly from the horizontal wall, the second vertical wall having a free end that terminates a distance apart from the horizontal wall, and the second vertical wall being spaced apart from the first vertical wall such that a gap exists therebetween, the gap sized to receive a portion of a footer;
a proximal support portion extending horizontally from the free end of the second vertical wall in a direction away from the gap; and
a tilted spring support ledge integrally joined to, and cantilevered from, the proximal support portion,
wherein a photovoltaic module is elastically supportable on the tilted spring support ledge when the photovoltaic module is installed on the tilted spring support ledge.

US Pat. No. 10,340,837

SLOPED ROOF SOLAR PANEL MOUNTING SYSTEM

Ecolibrium Solar, Inc, A...

1. A support surface attachment device, said support surface attachment device configured to attach one or more photovoltaic modules to a support surface, said support surface attachment device comprising:a base assembly configured to be attached to a support surface;
a clamp assembly configured to engage one or more photovoltaic modules, said clamp assembly including a lower clamp member and an upper clamp member, said upper clamp member connected to said lower clamp member by a fastener member, said lower clamp member including one or more first teeth disposed thereon, and said upper clamp member including one or more second teeth disposed thereon, said one or more first teeth on said lower clamp member configured to engage said one or more second teeth on said upper clamp member when said fastener member is being tightened so as to maintain a minimum gap between said upper clamp member and said lower clamp member for receiving one or more photovoltaic module frames of said one or more photovoltaic modules when said one or more photovoltaic modules are pivotably installed into a first side of said clamp assembly; and
a glider member coupling said upper and lower clamp members of said clamp assembly to said base assembly;
wherein said clamp assembly is capable of being selectively positioned along a length of said base assembly prior to being fixed in place relative to said base assembly so as to permit adjustability when said one or more photovoltaic modules are being attached to said support surface, said glider member configured to slide relative to said base assembly so as to allow said clamp assembly to be selectively positioned along said length of said base assembly prior to being fixed in place relative to said base assembly; and
wherein said upper and lower clamp members of said clamp assembly are configured to rotate together relative to said glider member, and wherein an upstanding base member of said base assembly is configured to rotate relative to said support surface, whereby the rotation of said upper and lower clamp members relative to said glider member and the rotation of said upstanding base member of said base assembly relative to a flashing member of said support surface attachment device enables a lateral position of said clamp assembly to be adjusted by an installer.

US Pat. No. 10,340,836

INTERLOCK SYSTEM FOR MOUNTING AND JOINING PHOTOVOLTAIC MODULES

SolarCity Corporation, S...

1. An assembly for mounting photovoltaic (PV) modules, the assembly comprising:a bracket comprising two openings, and a slot positioned between the two openings, wherein the two openings are configured to receive interlock couplings to attach at least two adjacent PV modules together to the bracket; and
a support coupling member attached to the bracket, the support coupling member comprising a housing and a coupling shaft extending from a surface of the housing,
wherein the coupling shaft is positioned in the slot directly attaching the support coupling member to the bracket,
wherein the housing is configured to be directly attached to a supporting foot, and
wherein the support coupling member is configured to attach to the bracket by first inserting the shaft of the support coupling member through the slot at a first angle relative to the bracket and then lock the support coupling member to the bracket by rotating the entire support coupling member to a second angle relative to the bracket.

US Pat. No. 10,340,835

CHIP EVACUATION DEVICE DRIVEN BY SYNCHRONOUS MOTOR

FANUC CORPORATION, Yaman...

1. A chip evacuation device that evacuates chips produced in a machine tool to outside of the machine tool, the chip evacuation device comprising:a synchronous motor as a power source for the chip evacuation device,
a load monitoring unit that monitors a load on the synchronous motor or on a driving unit of the chip evacuation device which is operated by the synchronous motor,
a threshold storage unit that stores at least one threshold of the load on the synchronous motor or on the driving unit of the chip evacuation device which is operated by the synchronous motor,
a comparison unit that makes comparison between the load monitored by the load monitoring unit and the threshold stored in the threshold storage unit, and
a synchronous motor control unit that changes a number of rotation or a direction of rotation of the synchronous motor in accordance with results of the comparison made by the comparison unit,
wherein the at least one threshold stored in the threshold storage unit defines a first load region, and
wherein the synchronous motor control unit increases at least either of the number of rotation and a frequency of operation of the synchronous motor when the load monitored by the load monitoring unit is in the first load region in the results of the comparison.

US Pat. No. 10,340,834

DRIVE SYSTEM

TOYOTA JIDOSHA KABUSHIKI ...

1. A drive system, comprising:a motor;
an inverter including a plurality of switching elements and a plurality of diodes that are connected in parallel to the plurality of switching elements, the inverter configured to drive the motor by switching of the plurality of switching elements;
a power storage device connected with the inverter via a power line; and
a control device configured to control the inverter,
the drive system further comprising:
a current sensor configured to detect a phase current of each phase of the motor, wherein
the control device shifts the inverter from a gate blocking state to a three phase-on state, wherein
when it is determined that electric current flows in a diode of an upper arm by referring to the phase current of each phase, the control device turns on a switching element of the upper arm and thereby shifts the inverter to an upper arm three phase-on state, or
when it is determined that electric current flows in a diode of a lower arm by referring to the phase current of each phase, the control device turns on a switching element of the lower arm and thereby shifts the inverter to a lower arm three phase-on state.

US Pat. No. 10,340,833

LOAD DRIVE DEVICE

Hitachi Automotive System...

1. A load drive device comprising:a first switching element, including either a first source terminal or a first drain terminal connected to a side of power source potential and either the first drain terminal or the first source terminal connected to one end terminal of a coil load;
a second switching element including either a second drain terminal or a second source terminal connected to a side of ground potential and either the second source terminal or the second drain terminal connected to either the first drain terminal of the first switching element or the second source terminal;
a third switching element including either a third source terminal or a third drain terminal connected to the side of the power source potential and either the first drain terminal or the first source terminal connected to another terminal of the load;
a fourth switching element including either a fourth drain terminal or a fourth source terminal connected to the side of the ground potential and either the fourth source terminal or the fourth drain terminal connected to either the third drain terminal or the third source terminal of the third switching element;
a capacitor including both end terminals connected between the power source potential and the ground potential;
a voltage measurement unit configured to measure a voltage across the capacitor; and
a control unit configured to individually turn the first to fourth switching elements ON or OFF,
wherein the voltage measurement unit detects whether a value of the voltage across the capacitor is not less than a predetermined voltage value set based on withstand voltage values of the first to fourth switching elements or is less than the predetermined voltage value,
the control unit performs switching control between a first mode and a second mode in an operation mode in which the first to fourth switching elements connected to the load are turned ON or OFF, or performs, after control in either the first or second mode starts, the switching control in mode into the second mode or the first mode,
the control unit operates the first to fourth switching elements in the first mode in a case where the voltage across the capacitor is not less than the predetermined voltage value, and operates the first to fourth switching elements in the second mode in a case where the voltage across the capacitor is less than the predetermined value,
the first mode is the operation mode in which all the first to fourth switching elements are turned OFF,
the second mode turns either the second or fourth switching element ON and turns all the other first to fourth switching elements OFF so as to form a closed current path including the coil load and the ground potential,
a capacitance value of the capacitor is determined based on a difference energy value between an energy value stored in the load at time at which occurrence of an excess current in the load is detected and an energy value consumed by either the second or fourth switching element with a current flowing into either the second or fourth switching element in the second mode after the detection of the excess current, and
the voltage across the capacitor is determined to a value of the predetermined voltage value or less, the voltage across the capacitor rising with electrical energy supplied, through the load and diode elements connected in parallel to the first to fourth switching in the first operation mode, to the diodes.

US Pat. No. 10,340,832

HYDRIDE GENERATION SYSTEM

ELEMENTAL SCIENTIFIC, INC...

1. A sampling system, comprising:a sampling assembly configured to draw a sample into a mixing path; and
a hydride generation assembly configured to introduce selected amounts of a first hydride generation reagent and a second hydride generation reagent into the mixing path, the hydride generation assembly including: a source of the first hydride generation reagent; a source of the second hydride generation reagent; a first chamber configured to contain the first hydride generation reagent; a second chamber configured to contain the second hydride generation reagent; a first plunger configured to translate within the first chamber and cause a displacement of the first hydride generation reagent; a second plunger configured to translate within the second chamber and cause a displacement of the second hydride generation reagent; and a base coupling the first plunger and the second plunger together, the base movable relative to the first chamber in a direction of translation of the first plunger within the first chamber;
a nebulizer fluidically coupled with the mixing path, the nebulizer configured to introduce at least a portion of the sample received from the mixing path into a spray chamber; and
a sample analysis instrument configured to receive the at least a portion of the sample from the nebulizer, the spray chamber being fluidically coupled with or forming a portion of the sample analysis instrument, the sample analysis instrument comprising a spectrometer.

US Pat. No. 10,340,831

WIND POWER GENERATOR VIBRATION INHIBITION METHOD AND DEVICE

8. A vibration suppression device of a wind power generator, comprising:a calculation module, configured to calculate a specified value of a flux-weakening control parameter of the generator based on a preset value of an electromagnetic active power of the generator and a frequency of the generator; and
a control module, configured to control the generator based on the specified value of the flux-weakening control parameter of the generator,
wherein:
the flux-weakening control parameter includes a specified value of a direct-axis current of the generator and a specified value of a quadrature-axis current of the generator;
the calculation module is further configured to calculate the specified value of the direct-axis current of the generator and the specified value of the quadrature-axis current of the generator based on the preset value of the electromagnetic active power of the generator and the frequency of the generator; and
the control module is further configured to perform a current vector control on the generator based on the specified value of the direct-axis current of the generator and the specified value of the quadrature-axis current of the generator, or
wherein:
the flux-weakening control parameter includes a specified value of a flux linkage of the generator and a specified value of an electromagnetic torque of the generator;
the calculation module is further configured to obtain the specified value of the flux linkage of the generator and the specified value of the electromagnetic torque of the generator based on the preset value of the electromagnetic active power of the generator and the frequency of the generator; and
the control module is further configured to perform a direct torque control on the generator based on the specified value of the flux linkage of the generator and the specified value of the electromagnetic torque of the generator.

US Pat. No. 10,340,830

APPARATUS AND METHOD FOR VARIABLY CONTROLLING ALTERNATOR

Hyundai Motor Company, S...

1. An apparatus for variably controlling an alternator, comprising:a controller configured to determine a state of an engine of a vehicle and calculate a target generation rate;
an alternator configured to generate electricity based on the target generation rate and produce generation power, the alternator variably adjusting responsiveness to the generation based on the determination of the state of the engine; and
a battery configured to be charged by the generation power,
wherein the variable adjustment includes dividing the state of the engine of the vehicle into an idle region and a driving region and variably adjusting the responsiveness of the alternator according to whether the state of the engine is the idle region or the driving region, and
wherein the responsiveness of the alternator is set to a slowest mode in the idle region so as to control revolution per minute (RPM) oscillation, and the responsiveness of the alternator is set to a normal mode in the driving region so as to prevent momentary battery overvoltage.

US Pat. No. 10,340,829

ELECTRICAL POWER CIRCUIT AND METHOD OF OPERATING SAME

General Electric Company,...

1. A method for operating an electrical power circuit connected to a power grid, the electrical power circuit having a power converter comprising a DC link, the power converter electrically coupled to a generator having a rotor and a stator, the method comprising:operating rotor connections of the rotor of the generator in a wye configuration during a first rotor speed operating range, the first rotor speed operating range comprising rotor speeds equal to and above a synchronous speed of the generator;
monitoring a rotor speed of the rotor of the generator; and,
transitioning the rotor connections of the rotor from the wye configuration to a delta configuration if the rotor speed changes to a second rotor speed operating range, the second rotor speed operating range comprising rotor speeds below the synchronous speed of the generator,
wherein transitioning from the wye configuration to the delta configuration and vice versa comprises rotor speed hysteresis to avoid excessive transitioning.

US Pat. No. 10,340,828

DISTURBANCE OBSERVER FOR PERMANENT MAGNET DIRECT CURRENT MACHINES

STEERING SOLUTIONS IP HOL...

1. A motor control system of a motor, the motor control system comprising:an observer module configured to:
receive an input voltage signal of the motor;
receive an output current signal from the motor; and
compute a disturbance estimate of the motor control system as a measured state of a plant model of an electrical subsystem of the motor control system, the disturbance estimate expressed as d=?Ke?m?vB, where d is the disturbance estimate, Ke is a back-emf constant, ?m is a motor velocity, and vB is brush-drop voltage; and
computing the motor velocity of the motor based on the disturbance estimate as
where V0 and I0 are estimated state variables and ia is a motor current.

US Pat. No. 10,340,827

FAULT TOLERANT CURRENT MEASUREMENT IN MOTOR CONTROL SYSTEMS

STEERING SOLUTIONS IP HOL...

1. A system for determining a sensor failure in a motor control system with at least three phase current measurements, the system comprising:a current controller configured to generate an input voltage command for a motor using feedforward control;
a failed sensor identification module, in response to the current controller operating using the feedforward control, configured to:
determine that a current offset error is indicative of a failure of a current sensor, the current offset error determined based on a magnitude and a phase of a diagnostic current; and
determine that the current offset error is indicative of a multi-point failure based on a determination that the magnitude of the diagnostic current is above a first predetermined threshold, and that the current offset error is indicative of a single point failure based on a determination that the magnitude is between a second predetermined threshold and the first predetermined threshold.

US Pat. No. 10,340,826

METHOD OF CONTROLLING A BRUSHLESS PERMANENT-MAGNET MOTOR

Dyson Technology Limited,...

1. A method of controlling a brushless permanent-magnet motor, the method comprising:sequentially exciting and freewheeling a phase winding of the motor using a controller, wherein the controller outputs control signals to sequentially excite and freewheel the phase winding, and wherein the phase winding is freewheeled when a phase current exceeds an upper threshold and freewheeling comprises-freewheeling until the phase current falls below a lower threshold;
measuring a parameter corresponding to a time interval between either the start and end of freewheeling or the start and end of excitation, wherein the time interval is measured using the controller, and wherein the time interval between the start and end of freewheeling begins when the phase current exceeds the upper threshold and ends when the phase current falls below the lower threshold;
comparing the measured parameter against a saturation threshold, using the controller;
determining that the rotor is at a predetermined position when the measured parameter is less than the saturation threshold using the controller; and
in response to determining that the rotor is at the predetermined position, commutating the phase winding using the controller after a commutation period has elapsed, wherein the commutation period includes a predetermined period of time after the determination that the rotor is in the predetermined position wherein the phase winding continues to be sequentially excited and freewheeled, wherein commutating the phase winding includes outputting control signals from the controller to commutate the phase winding after the commutation period has elapsed, and wherein the length of the commutation period is set such that the motor rotates through a predetermined angle of rotation, and wherein the predetermined angle of rotation is based on the predetermined position determined when the measured parameter is less than the saturation threshold.

US Pat. No. 10,340,825

MOTOR DRIVING DEVICE, METHOD, AND PROGRAM

RENESAS ELECTRONICS CORPO...

1. A motor driving device, comprising:an inverter circuit coupled to each of coils with a plurality of phases of a brushless DC motor including a rotor having a permanent magnet with a plurality of poles and a stator having the coils with the phases;
an electrical conduction control part which controls electrical conduction to each of the coils with the phases through the inverter circuit;
voltage signal generation parts each of which includes a plurality of resistors coupled to the coils with the phases and generates a voltage signal corresponding to an electric current flowing the coils;
a filter part including a first filter and a second filter whose filter constant is smaller than that of the first filter;
a filter selection part which selects one of the first filter and the second filter;
a comparator which compares the voltage signal inputted through the filter selected by the filter selection part with a predetermined reference voltage; and
a control part which performs an initial position determination process for determining the initial position of the rotor and a rotation driving process for rotating the rotor with use of a comparison result in the comparator,
wherein the control part controls the filter selection part to select the first filter when performing the initial position determination process and controls the filter selection part to select the second filter when performing the rotation driving process.

US Pat. No. 10,340,824

MOTOR DRIVEN INTEGRATED CIRCUIT, MOTOR DEVICE, AND APPLICATION APPARATUS

JOHNSON ELECTRIC INTERNAT...

1. A motor driver integrated circuit, comprising:a plurality of position comparators, each of the plurality of position comparators receiving a pole detection signal denoting a position of a rotor of a motor;
a timer receiving a timing interrupt signal output by the plurality of position comparators when a predetermined edge of the pole detection signal generated and recording a time of the predetermined edge;
a logic selection circuit coupled between the plurality of position comparators and the timer, the logic selection circuit selecting two adjacent edges of the pole detection signal and controlling the timer to start; and
a central processing unit obtaining a rotation speed of the motor according to a time difference between two adjacent edges selected by the logic selection circuit.

US Pat. No. 10,340,823

METHOD OF DETERMINING THE ROTOR POSITION OF A PERMANENT-MAGNET MOTOR

Dyson Technology Limited,...

1. A method of determining the position of a rotor of a brushless permanent-magnet motor, the method comprising:exciting and freewheeling a phase winding of the motor, wherein the phase winding is freewheeled when a phase current exceeds an upper threshold and freewheeling comprises freewheeling until the phase current falls below a lower threshold;
measuring a first time interval between the start and end of freewheeling or the start and end of excitation, wherein the first time interval is measured using a controller, and wherein the first time interval begins when the phase current exceeds the upper threshold and ends when the phase current falls below the lower threshold;
using the measured first time interval to define a saturation threshold, wherein the saturation threshold is defined such that when the measured first time interval is less than the saturation threshold, the rotor is in a pre-determined position;
sequentially exciting and freewheeling the phase winding using the controller, wherein the controller outputs control signals to sequentially excite and freewheel the phase winding, wherein the phase winding is freewheeled when the phase current exceeds the upper threshold and freewheeling comprises freewheeling until the phase current falls below the lower threshold;
measuring a second time interval corresponding to the time interval between either the start and end of freewheeling or the start and end of excitation, wherein the second time interval is measured using the controller, and wherein the second time interval begins when the phase current exceeds the upper threshold and ends when the phase current falls below the lower threshold;
comparing the measured second time interval against the saturation threshold using the controller; and
determining, using the controller, that the rotor is at a predetermined position when the measured second time interval is less than the saturation threshold.

US Pat. No. 10,340,822

MOTOR CONTROL SYSTEM

Delta Electronics, Inc., ...

1. A motor control system capable of controlling turning-on and turning-off of a plurality of motor windings, the motor control system comprising:an electric motor comprising:
a stator including an iron core with a plurality of slots formed therein along a radial direction of the stator;
a rotor surrounded by the stator; and
a winding structure having a plurality of hairpin wires with pins disposed in the slots, the hairpin wires forming a plurality of layers of conduction-wire, wherein the winding structure is configured to provide a plurality of phase windings and each phase winding includes a plurality of motor windings; and
an inverter connected to the motor windings, the inverter including a switching controller configured to control the turning-on and turning-off of the motor windings of each phase winding of the winding structure,
wherein when the electric motor operates in a high-speed mode, the switching controller controls the turning-on and turning-off of the motor windings of each phase winding such that a number of the phase windings turned-on is ? less than a number of all the phase windings.

US Pat. No. 10,340,821

ROTOR FLUX ANGLE AND TORQUE TRAJECTORY CONTROL APPARATUS AND METHODS

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit (“IC”), comprising:a low speed estimator to generate a low speed estimate of a flux angle of a rotor (“LS_?_EST”) in a motor;
a high speed estimator to generate a high speed estimate of the rotor flux angle (“HS_?_EST”) in the motor; and
an acceleration control logic module coupled to the low speed estimator and to the high speed estimator and configured to:
track a low speed estimate of an angular velocity of the rotor (“LS_?_EST”) relative to a low rotorangular velocity threshold value (“? LOW THRS”) and a high speed estimate of an angular velocity of the rotor (“HS_?_EST”) relative to a high rotor angular velocity threshold value (“?_HIGH_THRS”); and
select LS_? EST or HS_?_EST as an estimated rotor flux angle based on LS_?_EST relative to_LOW_THRS and HS_?_ESET relative to ?_HIGH_THRS.

US Pat. No. 10,340,820

ELECTRICAL SYSTEM FOR UNMANNED AERIAL VEHICLES

Wing Aviation LLC, Mount...

1. An unmanned aerial vehicle comprising:a power source;
a processor module comprising one or more processors; and
a plurality of boom arms, each boom arm being physically connected to a printed circuit board (PCB) and a plurality of propellers;
wherein a PCB of each boom arm comprises a power hub electrically connected to the power source and to corresponding propellers of the boom arm, and a signal hub electrically connected to at least one processor of the one or more processors and to the corresponding propellers;
wherein the power hub of each PCB comprises a plurality of selector switches corresponding to each of the plurality of corresponding propellers, wherein the power hub of each PCB is configured to transfer power from the power source to the corresponding propellers when the selector switches are in the engaged state, and wherein the signal hub of each PCB is configured to transfer signals from the one or more processors to the corresponding propellers, wherein the processor module controls the plurality of propellers.

US Pat. No. 10,340,819

FAULT SHUTDOWN CONTROL OF AN ELECTRIC MACHINE IN A VEHICLE OR OTHER DC-POWERED TORQUE SYSTEM

GM Global Technology Oper...

1. A direct current (DC)-powered torque system comprising:a DC power supply;
a polyphase electric machine having an output shaft operable for transmitting an output torque;
a DC voltage bus;
an alternating current (AC) voltage bus;
a contactor pair;
a power inverter module (PIM) having a plurality of semiconductor switches, wherein the PIM is selectively connected to the DC power supply via the contactor pair and the DC voltage bus, and is directly connected to the electric machine via the AC voltage bus;
a DC link capacitor in electrical parallel with the plurality of semiconductor switches;
a voltage sensor configured to measure a DC link voltage across the DC link capacitor; and
a controller having memory programmed with a set of calibrated values, including an inductance of the electric machine and a DC link capacitance of the DC link capacitor, wherein the controller is programmed to execute a control action with respect to the torque system in response to a predetermined fault condition, wherein the predetermined fault condition results in an opening of the contactor pair and a polyphase short condition, the control action including:
calculating a back electromotive force of the electric machine using the set of calibrated values and the DC link voltage from the voltage sensor; and
transmitting switching control signals to the semiconductor switches to transition from the polyphase short condition to a polyphase open condition only when the calculated back electromotive force is less than a calibrated value and a voltage rise on a DC side of the PIM is less than a calibrated voltage rise.

US Pat. No. 10,340,818

ACTUATOR, SHUTTER DEVICE, FLUID CONTROL DEVICE, SWITCH, AND TWO-DIMENSIONAL SCANNING SENSOR DEVICE

National University Corpo...

1. An actuator comprising:an electrostatic actuation mechanism including a stationary electrode and a movable electrode, the stationary electrode and the movable electrode being disposed in a planar arrangement;
a first movable part provided with the movable electrode and driven by the electrostatic actuation mechanism;
a first elastic support part that elastically supports the first movable part to enable the movable electrode to be displaced by sliding in a same plane with respect to the stationary electrode;
an electret formed in at least one of the stationary electrode and the movable electrode of the electrostatic actuation mechanism; and
a drive control unit that controls application of voltage to the electrostatic actuation mechanism, wherein:
a lower end of the movable electrode and a lower end of the stationary electrode in a direction perpendicular to a displacement direction of the movable electrode are positioned on a same single plane that is parallel to the displacement direction of the movable electrode;
in the actuator a plurality of stable states are set in which the first movable part is positioned at a stable position at which an electrostatic force generated by the electret matches with an elastic force exerted by the first elastic support part or at a stable position near such stable position; and
the drive control unit controls the electrostatic force generated by the electrostatic actuation mechanism to be weakened temporarily by applying a voltage to the electrostatic actuation mechanism to change any one of the stable states to another of the stable states to displace the first movable part from any stable position to another stable position.

US Pat. No. 10,340,817

SILICON CARBIDE MOSFET INVERTER CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide MOSFET inverter circuit, comprising:a first silicon carbide MOSFET and a second silicon carbide MOSFET connected in series, each of the first and second silicon carbide MOSFETs having a built-in diode therein;
a first external freewheeling diode connected in anti-parallel to the first silicon carbide MOSFET; and
a second external freewheeling diode connected in anti-parallel to the second silicon carbide MOSFET,
wherein the first and second silicon carbide MOSFETs, the first and second freewheeling diodes, and wirings that interconnects the first and second silicon carbide MOSFETs and the first and second freewheeling diodes are configured such that during a deadtime in an inverter operation cycle in which the first silicon carbide MOSFET and the second silicon carbide MOSFET are both OFF, thereby causing freewheeling current to flow, a pulse width of a transient current that flows in the built-in diode of the first silicon carbide MOSFET or the built-in diode of the second silicon carbide MOSFET in response to the freewheeling current during the deadtime is less than 2 ?s.

US Pat. No. 10,340,816

SEMICONDUCTOR DEVICE AND MULTIPHASE SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor module internally having first and second partial circuit units and externally having first and second external terminals for said first and second partial circuit units;
first and second control substrates which are arranged on said semiconductor module and on which first and second control circuits for said first and second partial circuit units are provided, said first and second control substrates respectively having first and second main regions on which first and second control main portions are formed; and
an insulation material inserted between said first and second control substrates so as to overlap said first and second main regions in plan view,
wherein said first and second control substrates further respectively have first and second protrusion regions in which first and second circuit parts electrically connected to said first and second external terminals are formed,
said first control circuit including said first circuit part and said first control main portion, and said second control circuit including said second circuit part and said second control main portion, and
said first protrusion region does not overlap said second control substrate in plan view, said second protrusion region does not overlap said first control substrate in plan view, and each of said first and second protrusion regions does not overlap said insulation material in plan view.

US Pat. No. 10,340,815

LIQUID EJECTING APPARATUS AND CIRCUIT BOARD

Seiko Epson Corporation, ...

1. A liquid ejecting apparatus comprising:a first ejecting section that includes a first drive element and ejects liquid by driving the first drive element;
a first drive circuit that includes a first transistor and outputs a first drive signal to the first drive element;
a second drive circuit that includes a second transistor and outputs a second drive signal to the first drive element; and
a circuit substrate on which the first drive circuit and the second drive circuit are mounted, wherein
the first drive circuit is mounted on a first surface of the circuit substrate,
the second drive circuit is mounted on a second surface of the circuit substrate on an opposite side from the first surface, and
the first transistor and the second transistor are disposed at positions that do not overlap one another in plan view of the circuit substrate.

US Pat. No. 10,340,814

GATE-BLOCKING A DC/DC CONVERTER BASED UPON OUTPUT CURRENT OF AN AC REACTOR IN A POWER CONVERSION DEVICE

Sumitomo Electric Industr...

1. A power conversion device provided between a DC power supply and an AC electric path and performing DC/AC power conversion in a state in which a DC voltage of the DC power supply is lower than a peak value of an AC voltage of the AC electric path, the power conversion device comprising:a DC/DC converter provided between the DC power supply and a DC bus;
an intermediate capacitor connected to the DC bus and having such a small capacitance as not to smooth a pulsation that is included in a voltage of the DC bus and has a frequency twice as high as a frequency of the AC voltage;
an inverter connected to the DC bus;
a filter circuit provided between the inverter and the AC electric path and having an AC reactor and an AC-side capacitor;
a current sensor configured to detect a current flowing through the AC reactor; and
a control unit configured to perform control such that, for generating the AC voltage from the DC voltage, a period during which the DC/DC converter boosts the DC voltage and the inverter performs one of polarity non-inversion passing and polarity inversion passing, and a period during which the DC/DC converter is stopped and the inverter performs step-down operation and one of polarity non-inversion passing and polarity inversion passing, arise alternately in one AC cycle, wherein
the control unit temporarily performs gate blocking for only the DC/DC converter, upon occurrence of a phenomenon in which, by start of power feeding to a load connected to the AC electric path, an absolute value of the current flowing through the AC reactor reaches a predetermined converter gate block threshold value lower than an instantaneous overcurrent protection threshold value.

US Pat. No. 10,340,813

ELECTRONIC POWER CONVERTER AND COMPUTER PROGRAM

1. A polyphase power converter for outputting polyphase alternating current, comprising:at least two semiconductor switches connected in a half-bridge circuit for controlling each phase of the polyphase alternating current output by the polyphase power converter;
a control device configured for processing a setpoint value signal fed to the control device as an input signal in a form of a bit stream having a width of one bit or a plurality of bits for each phase, wherein the control device is configured for generating by space vector modulation actuation signals of the at least two semiconductor switches depending on the bit stream fed as the input signal; and
a switching logic for generating switching sequences of the space vector modulation which utilizes
state bits which correspond to the actuation signals of the at least two semiconductor switches, and
at least one additional bit in a form of a cycle bit which indicates a running direction in a cycle of a voltage space vector,
wherein the space vector modulation executed by the control device has an angle hysteresis of the voltage space vector, and
wherein the angle hysteresis is realized by the cycle bit,
wherein the space vector modulation utilized by the control device has one or a plurality of limit values, wherein the control device has a comparator configured for comparing the magnitude of the voltage space vector with the one or the plurality of limit values and for triggering a switching function in a case where a magnitude of a voltage space vector exceeds the one or the plurality of limit values, and
wherein the control device is configured such that upon a highest limit value of the one or the plurality of limit values being exceeded, a reset signal for targeted reduction of values stored in digital accumulators of the control device is implemented.

US Pat. No. 10,340,812

FLEXIBLE POWER CONVERTER ARCHITECTURE BASED ON INTERPOSER AND MODULAR ELECTRONIC UNITS

RAYTHEON COMPANY, Waltha...

14. An electronic transceiver/receiver (T/R) unit included in a Transmit or Receive Integrated Microwave Module (T/RIMM) installed in a modular high-power converter system, the comprising:a power amplifier connected to an antenna to perform at least one of signal transmission or signal reception; and
a modular direct current-to-direct current (DC/DC) converter configured to convert a first DC voltage into a reduced second DC voltage that drives the power amplifier, the modular-based DC/DC converter including a plurality of modular power converter units configured to generate the second DC voltage,
wherein each modular converter unit configured to be independently interchangeable with a different modular converter unit,
each modular power converter unit configured to perform a different electronic power conversion operation with respect to one another, wherein each modular converter unit is configured to be independently removed without disconnecting the modular-based DC/DC converter.

US Pat. No. 10,340,811

INVERTER SWITCHING DEVICES WITH GATE COILS TO ENHANCE COMMON SOURCE INDUCTANCE

FORD GLOBAL TECHNOLOGIES,...

1. A half-bridge power module comprising;a body encapsulating a pair of transistor dies and positive, negative, and AC conductive tracks for carrying bridge currents;
a pair of gate drive pins projecting from the body; and
a pair of gate drive coils connecting a respective gate drive pin and transistor die, wherein each gate drive coil has at least one winding turn, and wherein the gate drive coils are encapsulated in a region disposed between the positive and negative conductive tracks containing a flux generated by the currents having a locally greatest rate of change.

US Pat. No. 10,340,810

BIDIRECTIONAL DC CONVERTER ASSEMBLY HAVING CASCADE OF ISOLATED RESONANT CONVERTER AND STEP-UP/STEP-DOWN CONVERTER

1. A bidirectional DC/DC converter assembly for an electric vehicle having a high-voltage (HV) level and a low-voltage (LV) level, the bidirectional DC/DC converter assembly comprising:a first DC/DC converter having a first port and a second port, the first DC/DC converter connected to the HV level by the first port being connected to the HV level;
a second DC/DC converter having a third port and a fourth port, the second DC/DC converter connected to the first DC/DC converter by the third port being connected to the second port, the second DC/DC converter connected to the LV level by the fourth port being connected to the LV level, wherein the second DC/DC converter is a series resonant switching converter formed by a DC/AC converter, a transformer, and an AC/DC converter;
wherein when energy is to flow in a first direction from the HV level to the LV level the first DC/DC converter is operable as a buck converter to convert a high DC voltage inputted to the first port into an intermediate DC voltage that is outputted at the second port;
wherein when energy is to flow in a second direction from the LV level to the HV level the first DC/DC converter is operable as a boost converter to convert at intermediate DC voltage inputted to the second port into a high DC voltage that is outputted at the first port; and
a peak current controller associated with the first DC/DC converter, the peak current controller including a current sensor for measuring an inductor current of an inductor of the first DC/DC converter,
wherein, when the inductor current is a bidirectional inductor current having a polarity that changes between positive and negative during a change in the flow of energy between the first and second directions, the peak current controller generates a modified current variable that is a summation of the bidirectional inductor current and an offset value, the offset value being such that the modified current variable has a constant polarity,
wherein the peak current controller uses the modified current variable as a set point in controlling power switches of the first DC/DC converter during a change in operation of the first DC/DC converter between the buck converter and the boost converter in correspondence with the change in the flow of energy between the first and second directions.

US Pat. No. 10,340,809

BIDIRECTIONAL DC-DC RESONANT CONVERTER

Eltek AS, Drammen (NO)

1. Bi-directional DC-DC resonant converter with bi-directional voltage control, comprising:primary converter terminals defining a primary voltage;
secondary converter terminals defining a secondary voltage;
a transformer device having primary transformer terminals and secondary transformer terminals;
a resonant tank device having first and second primary resonant tank terminals defining a primary resonant tank voltage and first and second secondary resonant tank terminals defining a secondary resonant tank voltage, wherein the primary tank terminals are connected to the secondary transformer terminals;
a primary switching circuit connected between the primary converter terminals and the primary transformer terminals; and
a secondary switching circuit connected between the secondary resonant tank terminals and the secondary converter terminals;
wherein the resonant tank device comprises a configuration switch for configuration of the converter between a first state, in which power is transferred from the secondary converter terminals to the primary converter terminals, and a second state, in which power is transferred from the primary converter terminals to the secondary converter terminals;
wherein the resonant tank device comprises a resonant inductor, a magnetizing inductor and a resonant capacitor connected to the configuration switch;
wherein a first gain is defined as the ratio between a first harmonic approximation of the secondary resonant tank voltage and a first harmonic approximation of the primary resonant tank voltage when operating at a first series resonance frequency in the first state;
wherein a second gain is defined as the ratio between a first harmonic approximation of the secondary resonant tank voltage and a first harmonic approximation of the primary resonant tank voltage when operating at a second series resonance frequency in the second state; and
wherein the first gain is different from the second gain.

US Pat. No. 10,340,807

GATE DRIVE APPARATUS FOR RESONANT CONVERTERS

Futurewei Technologies, I...

1. A device comprising:a gate drive bridge coupled between a bias voltage of a power converter and ground, wherein the gate drive bridge comprises two high-side switches and two low-side switches, and wherein a duty cycle of the two low-side switches is greater than a duty cycle of the two high-side switches; and
a transformer connected to the gate drive bridge, wherein the transformer comprises:
a primary winding connected to two legs of the gate drive bridge respectively; and
a plurality of secondary windings configured to generate gate drive signals for low side switches, high side switches and secondary switches of the power converter.

US Pat. No. 10,340,805

RESONANT STEP DOWN DC-DC POWER CONVERTER AND METHODS OF CONVERTING A RESONANT STEP DOWN DC-DC CONVERTER

Danmarks Tekniske Univers...

1. A resonant step-down DC-DC power converter comprising:a primary side circuit and a secondary side circuit coupled through a capacitor based galvanic isolation barrier,
the primary side circuit comprising a positive input terminal and a negative input terminal for receipt of an input voltage and an input capacitor coupled between the positive and negative input terminals,
the secondary side circuit comprising an output capacitor chargeable to a converter output voltage between a first positive electrode and a second negative electrode of the output capacitor,
a resonant network configured for alternatingly being charged from the input voltage and discharged to the output capacitor through the galvanic isolation barrier by a semiconductor switch arrangement in accordance with a switch control signal to produce the converter output voltage,
an electrical short-circuit connection across the galvanic isolation barrier connecting, in a first case, the second negative electrode of the output capacitor to the positive input terminal of the primary side circuit or, in a second case, connecting the second positive electrode of the output capacitor to the negative input terminal of the primary side circuit thereby establishing in both the first and second cases a series coupling of the output capacitor and the input capacitor, and
a load connection, in the first case, between the first positive electrode of the output capacitor and the positive input terminal or, in the second case, between the second negative electrode of the output capacitor and the negative input terminal.

US Pat. No. 10,340,804

POWER SUPPLY CIRCUIT INCLUDING CONVERTER AND POWER SUPPLY SYSTEM USING THE SAME

KABUSHIKI KAISHA TOYOTA C...

1. A power supply circuit comprising:a first converter circuit that includes a first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor, a first switching element, and a second switching element, and in which a first port and a second port are provided; and
a second converter circuit that includes a fourth capacitor, a fifth capacitor, a sixth capacitor, a third inductor, a fourth inductor, a third switching element, and a fourth switching element, and in which a third port is provided, wherein
the first converter circuit and the second converter circuit are electrically insulated from each other;
the first switching element and the second switching element are alternately switched based on a phase of a first switching of the first converter circuit so that only one of first switching element and the second switching element is switched on during any period of the phase of switching of the first converter, and the third switching element and the fourth switching element are alternately switched based on a phase of a second switching of the second converter so that only one of the third switching element and the fourth switching element is switched on during any period of the phase of switching of the second converter,
the first inductor and the second inductor, and the third inductor and the fourth inductor are respectively magnetically connected to each other by a common magnetic core, and are wound in directions to generate a magnetic flux in the same direction with each other in the magnetic core when a phase difference between the phase of the switching of the first converter circuit and the phase of the switching of the second converter circuit is zero, and
a change of a duty of the first switching is equal to a change of a duty of the second switching, and a phase difference between the phase of the first switching and the phase of the second switching is adjustable.

US Pat. No. 10,340,803

DC-DC CONVERTER HAVING PREDICTED ZERO INDUCTOR CURRENT

Texas Instruments Incorpo...

1. A DC-to-DC voltage converter comprising:a converter input for receiving a DC voltage;
a first switch coupled between the input and a first node;
a second switch coupled between the first node and a ground;
an inductor coupled between the first node and a converter output;
a capacitor coupled between the converter output and the ground;
an output voltage synthesizer coupled to the converter input and the converter output for synthesizing the voltage at the converter output and for generating a control signal for at least one of the first switch and the second switch in response to the synthesized voltage at the converter and to predict zero inductor current using volt*second balance of the inductor;
the synthesizer comprising:
a synthesizer input coupled to the converter input;
a third switch coupled between the synthesizer input and a second node;
a fourth switch coupled between the second node and the ground;
a resistor coupled between the second node and a third node;
the capacitor coupled between the third node and the ground;
an integrating transconductance stage for comparing the voltage at a first input to the voltage at a second input and generating an output signal in response to the comparison, wherein the first input is coupled to the third node and the second input is coupled to the converter output;
at least one of the first switch, the second switch, the third switch, and the fourth switch being controlled in response to the output signal of the integrating transconductance stage;
further comprising a fifth switch coupled to the output of the integrating transconductance stage, the fifth switch coupling the output of the integrating transconductance stage to the capacitor for sampling and holding the output signal of the integrating transconductance stage.

US Pat. No. 10,340,802

POWER CONVERSION APPARATUS WITH LOW POWER CONSUMPTION AND LOW COST

Power Forest Technology C...

1. A power conversion apparatus, comprising:a synchronous rectification (SR) transistor;
an SR controller, coupled to the SR transistor to control the SR transistor, wherein a ground terminal of the SR controller is coupled to a source terminal of the SR transistor, and a power terminal of the SR controller receives a system voltage;
a snubber circuit, having a first terminal coupled to a drain terminal of the SR transistor and a second terminal coupled to the power terminal of the SR controller,
wherein the snubber circuit obtains power from the drain terminal of the SR transistor and provides the system voltage accordingly; and
a power supply circuit, coupled to the second terminal of the snubber circuit and the source terminal of the SR transistor,
wherein the snubber circuit and the power supply circuit operate in cooperation to suppress a voltage surge between the drain terminal and the source terminal of the SR transistor and generate the system voltage according to a voltage drop between the drain terminal and the source terminal of the SR transistor.

US Pat. No. 10,340,801

DECENTRALIZED OSCILLATOR-BASED CONVERTER CONTROL

Alliance for Sustainable ...

1. A device comprising:a control unit comprising an oscillator circuit comprising a negative conductance element, an inductor, and a capacitor connected in parallel, the control unit configured to generate, based on the oscillator circuit, at least one switching signal; and
a direct current (DC)-to-DC conversion circuit comprising at least one electronic switch that is operatively coupled to the control unit, wherein the DC-to-DC conversion circuit is configured to convert, based on the at least one switching signal, a DC input voltage to a DC output voltage,
wherein the control unit is further configured to input, to the oscillator circuit, a current signal that is generated based on a measured output current of the DC-to-DC conversion circuit.

US Pat. No. 10,340,800

SHORT CIRCUIT PROTECTION FOR A POWER CONVERTER

Dialog Semiconductor (UK)...

1. A switched mode power converter configured to convert electrical power between a first voltage at a first port and a second voltage at a second port; wherein the first and second voltages are relative to a reference potential; wherein the power converter comprisesan inductive element having a first side and a second side; wherein the first side of the inductive element is coupled to the first port;
a power switch configured to couple or to decouple the second side of the inductive element to or from the reference potential;
a capacitive element having a first side and a second side; wherein the first side of the capacitive element is coupled to the power switch; wherein the second side of the capacitive element is coupled to the second port and wherein the second side of the inductive element is coupled to the first side of the capacitive element;
an auxiliary switch configured to couple or to decouple the second side of the capacitive element to or from the reference potential; and
a control unit configured to control the power switch and the auxiliary switch in a repetitive manner to convert electrical power, wherein the control unit is configured to detect a short circuit situation at the first or second port and in reaction to this, put both the power switch and the auxiliary switch in an off-state such that the capacitive element and the inductive element are arranged in series between the first and second port.

US Pat. No. 10,340,799

STEP-UP/DOWN POWER SUPPLY AND POWER SUPPLY CIRCUIT

Hitachi Automotive System...

1. A step-up/down power supply comprising:a step-down unit that generates an output voltage lower than an input voltage by turning on or off a step-down switch in which the input voltage of the step-up/down power supply is applied to an end of the step-down switch;
a step-up unit that generates an output voltage higher than the input voltage by turning on or off a step-up switch in which a ground is applied to an end of the step-down switch; and
a step-down gate voltage control circuit that controls a gate voltage of the step-down switch,
wherein the step-down gate voltage control circuit includes a gate voltage generating circuit that generates a first voltage and a second voltage for turning on the step-down switch, and a gate voltage switching circuit that switches between the first voltage and the second voltage,
wherein the gate voltage generating circuit includes a first generating circuit generating the first voltage and a second generating circuit generating the second voltage,
wherein a load current for driving the second generating circuit is greater than that of the first generating circuit,
wherein the gate voltage switching circuit:
when the input voltage is equal to or lower than a first voltage threshold corresponding to the output voltage and a voltage generated from the first generating circuit becomes the first voltage, switches a voltage for turning on the step-down switch to the first voltage, and
when the input voltage is higher than the first voltage threshold, switches the voltage for turning on the step-down switch to the second voltage,
wherein the gate voltage switching circuit includes:
an initiation determining circuit in which output is transitioned from Low to High in order to initiate the first generating circuit;
a voltage determining circuit in which output is transitioned from Low to High in a case in which a voltage generated from the first generating circuit is the first voltage; and
a step-up/down determining circuit in which output is transitioned from Low to High in a case in which the input voltage is equal to or lower than the first voltage threshold corresponding to the output voltage, and output of the voltage determining circuit is from Low to High, and
wherein the initiation determining circuit is reset by an operation of switching the output of the step-up/down determining circuit from High to Low, and a state of the first generating circuit becomes a stop state from an operation state by switching the output from High to Low.

US Pat. No. 10,340,798

SWITCHING CONTROL METHOD FOR A DUAL AUXILIARY POWER SUPPLY

Dong Guan Juxing Power Co...

1. A switching control method for a dual auxiliary power supply, wherein said dual auxiliary power supply comprises a main auxiliary power supply, a sleep auxiliary power supply, and a master control module serving as a switching control module, wherein said main auxiliary power supply and said sleep auxiliary power supply are both powered by an energy storage battery;said main auxiliary power supply and said sleep auxiliary power supply are connected respectively to two power supply terminals of said master control module;
said master control module controls said main auxiliary power supply by a switch control unit;
said master control module is further coupled to a trigger detection circuit which is powered by the sleep auxiliary power supply;
said main auxiliary power supply outputs a control signal to an energy conversion module; and
said sleep auxiliary power supply is constantly in an operation state, and said control is conducted according to a signal detected by said trigger detection circuit or an instruction received by said master control module, where
(1) when no trigger signal is detected by said trigger detection circuit or a detected trigger signal is invalid, said main auxiliary power supply is in a lockout state under said control of said switch control unit; and
(2) when a trigger signal is detected by said trigger detection circuit or a start-up instruction is received by the master control module, said main auxiliary power supply is in an operation state under said control of said switch control unit,
wherein said switch control unit comprises a first transistor of PMOS-type, a second transistor of NMOS-type, and a third transistor of PNP-type;
SPS_CNTL is an enabling control signal for controlling said main auxiliary power supply, a SPS_CNTL terminal is connected to a first pole of said third transistor; a second pole of said third transistor is grounded; a first resistor is connected between a third pole of said third transistor and said SPS_CNTL terminal;
and a second resistor is connected between said third pole and said second pole of said third transistor;
said third pole of said third transistor is further connected to a first pole of said second transistor; a third pole of said second transistor is grounded; and a second pole of said second transistor is connected via a third resistor to a first pole of said first transistor; and
a third pole of said first transistor is connected to a BAT+ terminal of a power supply voltage; a second pole of said first transistor powers said main auxiliary power supply; and
a forth resistor is connected between said second pole and said third pole of said first transistor.

US Pat. No. 10,340,797

REGULATOR CONTROL INTEGRATED CIRCUIT HAVING COT AND VALLEY CURRENT MODES

Active-Semi, Inc., (VG)

1. A voltage regulator control integrated circuit having a valley current (VC) mode and a constant on-time (COT) mode, the voltage regulator control integrated circuit comprising:a sequential logic element having a set input lead, a reset input lead, and an output lead;
a comparator circuit that supplies a set signal SET to the sequential logic element;
a osc/one-shot circuit that supplies a reset signal RESET to the sequential logic element, wherein in the COT mode the reset signal RESET is a delayed one-shot pulse signal, and wherein in the VC mode the reset signal RESET is a free-running oscillating signal;
a compensation signal generator circuit that supplies a compensation voltage signal VC to the comparator circuit, wherein in the COT mode the compensation voltage signal VC is an AC ground signal, and wherein in the VC mode the compensation voltage signal VC is a ramp signal;
a current sense circuit that outputs a voltage signal VCURRENT indicative of a magnitude of a current, wherein the current sense circuit supplies the voltage signal VCURRENT to the comparator circuit; and
an error amplifier circuit that supplies an error voltage signal VE to the comparator circuit.

US Pat. No. 10,340,796

CONSTANT ON TIME BOOST CONVERTER CONTROL

Cirrus Logic, Inc., Aust...

1. A controller for controlling at least one switch of a boost switching converter comprising an inductor coupled to a first terminal of a power supply, a first switch coupled between the inductor and an output of the boost switching converter, and a second switch coupled between the inductor and a second terminal of the power supply, the controller comprising:a current estimator configured to determine an estimated inductor current through the inductor during a first phase of a particular switching cycle of the boost switching converter in which the inductor is discharging, the first switch is activated, and the second switch is deactivated, wherein the current estimator is configured to estimate the inductor current by applying volt-second balance calculations to determine the estimated inductor current based on: (a) a previous sample of a current through the inductor during a second phase of the particular switching cycle of the boost switching converter in which the inductor is charging, the second switch is activated, and the first switch is deactivated, (b) a power supply voltage between the first terminal of the power supply and the second terminal of the power supply, and (c) an output voltage at the output of the boost switching converter; and
a switch control configured to control activation and deactivation of the at least one switch based on the estimated inductor current.

US Pat. No. 10,340,795

SYSTEMS AND METHODS FOR OUTPUT CURRENT REGULATION IN POWER CONVERSION SYSTEMS

On-Bright Electronics (Sh...

1. A system controller for regulating a power converter, the system controller comprising:a driver configured to output a drive signal to a switch to affect a current flowing through an inductive winding of a power converter, the drive signal being associated with a switching period including an on-time period and an off-time period;
wherein:
the switch is closed in response to the drive signal during the on-time period;
the switch is opened in response to the drive signal during the off-time period;
a duty cycle is equal to a duration of the on-time period divided by a duration of the switching period; and
one minus the duty cycle is equal to a parameter;
wherein the system controller is configured to keep a multiplication product of the duty cycle, the parameter and the duration of the on-time period approximately constant.

US Pat. No. 10,340,794

REVERSE CAPACITOR VOLTAGE BALANCING FOR HIGH CURRENT HIGH VOLTAGE CHARGE PUMP CIRCUITS

Linear Technology LLC, M...

1. A switched capacitor converter, comprising:a primary switching circuit comprising:
a plurality of switching transistors connected in series; and
an output capacitor and one or more flying capacitors including a first flying capacitor; and
a pre-balancing circuit comprising:
a first comparator circuit of one or more comparator circuits configured to monitor a voltage of the first flying capacitor of the primary switching circuit and, when the voltage of the first flying capacitor is outside a first voltage range, to activate a first current source of one or more current sources coupled to the first flying capacitor to discharge the first flying capacitor until the voltage of the first flying capacitor is within the first voltage range for a predetermined first amount of time, wherein the first comparator circuit is configured to keep the plurality of switching transistors of the primary switching circuit turned off when the first current source is activated; and
a second comparator circuit of the one or more comparator circuits configured to monitor a voltage of the output capacitor of the primary switching circuit and, when the voltage of the output capacitor is outside a second voltage range, to activate a second current source of the one or more current sources coupled to the first flying capacitor to charge the first flying capacitor until the voltage of the output capacitor is within the second voltage range for a predetermined second amount of time, wherein when the second current source is activated, the second comparator circuit is configured to keep at least one of the plurality of switching transistors of the primary switching circuit turned off and to turn on or off one or more remaining switching transistors of the plurality of switching transistors of the primary switching circuit according to a switching cycle.

US Pat. No. 10,340,793

DIGITAL CONTROL OF CHARGE PUMP

Wuhan Xinxin Semiconducto...

1. A charge pump system, for generating digital control signals according to an output of a charge pump, the charge pump system comprising:a differential amplifier, for receiving a feedback voltage and a reference voltage, and generating an output signal according to a difference between the feedback voltage and the reference voltage;
an oscillating circuit for generating clock pulses at a rate according to the output signal;
a charge pump for receiving the clock pulses and generating an output voltage which is input to the differential amplifier as the feedback voltage;
a current sink comprising an NMOS having a source coupled to the output of the charge pump and a drain coupled to ground;
a first pair of cascode transistors coupled between a voltage supply and ground for generating a digital signal, comprising:
a PMOS having a source coupled to the voltage supply and a gate coupled to the output signal from the differential amplifier; and
an NMOS having a source coupled to a drain of the PMOS, a drain coupled to ground, and a gate coupled to a constant bias; and
an inverter coupled to the drain of the PMOS, for inverting the digital signal to generate a first digital signal according to the output signal, wherein the first digital signal is input to a gate of the current sink;
wherein when the feedback voltage is higher than the reference voltage, the first digital signal will be generated and the current sink will be turned on, and when the feedback voltage is lower than the reference voltage, the first digital signal will not be generated and the current sink will be turned off.

US Pat. No. 10,340,792

PMIC BOOT TIMING CIRCUIT AND PMIC BOOT TIMING DETERMINATION METHOD

SHENZHEN CHINA STAR OPTOE...

1. A PMIC boot timing circuit, comprising a PMIC, a first capacitor, a second capacitor, and a triode, wherein the PMIC comprises a first buck module, a second buck module, a third buck module and a direct current source; one end of the first capacitor is connected to the direct current source, and the other end of the first capacitor is grounded; one end of the second capacitor is connected to one end of the direct current source, and the other end of the second capacitor is connected to a drain of the triode; a source of the triode is grounded, and a gate of the triode is connected to the PMIC.

US Pat. No. 10,340,791

CHARGE PUMP

Dialog Semiconductor (UK)...

7. A DC-DC voltage converter circuit comprising:a charge pump;
a measurement circuit adapted to:
measure at a first time an output voltage of the charge pump;
store said first measured voltage:
measure and store at a second later time a second output voltage of said charge pump;
compare said stored second measured voltage with said stored first measured voltage; and
a logic circuit arranged to cooperate with the measurement circuit to optimize a charge pump efficiency during a charge pumping operation, by adjusting an operational parameter of the charge pump based on the comparison.

US Pat. No. 10,340,790

INTEGRATED VOLTAGE CORRECTION USING ACTIVE BANDPASS CLAMP

COOLSTAR TECHNOLOGY, INC....

1. A voltage correction circuit configured to work in conjunction with a voltage source to supply current to a load operatively coupled with the voltage correction circuit, the voltage correction circuit comprising:a high-pass filter coupled with the load at a first node, the high-pass filter including an impedance network having a frequency response defining a lower frequency boundary of a passband of the voltage correction circuit; and
an active clamp coupled with the high-pass filter in a closed-loop feedback arrangement and being adapted to receive, from the voltage source, an input voltage to be regulated, the active clamp having a frequency response defining an upper frequency boundary of the passband of the voltage correction circuit, an output of the active clamp generating a regulated output voltage of the voltage correction circuit;
wherein a loop gain of the voltage correction circuit is greater than or equal to one within the passband and is less than one for frequencies lower than the lower frequency boundary and higher than the upper frequency boundary.

US Pat. No. 10,340,789

DYNAMIC THRESHOLD SELECTION FOR TRANSIENT DETECTION IN A COVERTER

TEXAS INSTRUMENTS INCORPO...

1. A circuit for use with or as part of a converter, the circuit comprising:a sense circuit to provide a sense signal corresponding to a voltage output of the converter;
dynamic threshold circuitry to selectably provide stepwise injection thresholds, including at least a first injection threshold, and a last injection threshold,
the first injection threshold set near a target converter output voltage, so as to account for a pre-defined ripple voltage during normal operation for the converter, and
each injection threshold after the first injection threshold lower than a preceding injection threshold;
injection enable circuitry operable
when the sense signal is lower than the first injection threshold to provide a first injection enable signal, and
to change the first injection threshold stepwise to a next injection threshold, and
when the sense signal is lower than the next injection threshold, to provide a next injection enable signal;
energy injection circuitry responsive to the injection enable signal to cause the injection of additional energy to increase the converter output voltage.

US Pat. No. 10,340,788

POWER SOURCE INTERFACE MODULE WITH COMPACT EMI FILTER

TELEFONAKTIEBOLAGET LM ER...

1. A power source interface module for electronic circuits supplied by power from a power source, comprising:a first-circuit board carrying components and comprising a number of stacked circuit board layers as well as at least two openings,
a filter comprising at least one pair of magnetically coupled inductive coils, and
a core with two core legs, each core leg stretching through a corresponding opening in the first circuit board, wherein each magnetically coupled inductive coil is wound around a corresponding core leg, turns of the magnetically coupled inductive coils stretch through the stacked circuit board layers, and each layer between an upper outer layer and a lower outer layer of the stacked circuit board layers comprises at least a part of one turn, wherein the two core legs are interconnected by an upper yoke and a lower yoke, each yoke comprising a wing stretching out in a direction away from the two core legs.

US Pat. No. 10,340,786

HIGH FREQUENCY WIRELESS POWER RECTIFIER STARTUP CIRCUIT DESIGN

Integrated Device Technol...

1. A rectifier, comprising:a first transistor and a second transistor coupled in series between a rectifier output and a ground, wherein a first AC input is coupled to a first node between the first transistor and the second transistor;
a third transistor and a fourth transistor coupled in series between the rectifier output and the ground, wherein a second AC input is coupled to a second node between the third transistor and the fourth transistor;
a first control circuit coupled between a gate of the first transistor and a gate of the fourth transistor to control operation of the first and the fourth transistors;
a first startup circuit directly connected between the gate of the first transistor and the first node, the first startup circuit controlling the gate of the first transistor in a startup time period prior to an operating period of the rectifier, wherein the first startup circuit maintains a low impedance between the gate of the first transistor and the first node during a startup time and maintains a high impedance between the gate of the first transistor and the first node during the operating period of the rectifier; and
a second startup circuit directly connected between the gate of the fourth transistor and the ground.

US Pat. No. 10,340,785

IMPLEMENTING VOLTAGE SENSE POINT SWITCHING FOR REGULATORS

International Business Ma...

1. A method for implementing voltage sense point switching for regulators comprising:providing a first sense point at a non-switched sense location, said first sense point being always on;
providing a second sense point at a location to be switched; said second sense point optionally being switched off controlled using a transistor switch;
providing a first operational amplifier coupled to said first sense point and a second operational amplifier coupled to said second sense point, and connecting a first diode to an output of said first operational amplifier and connecting a second diode to an output of said second operational amplifier;
providing a circuit output at said first and second diodes to a remote sense input to a regulator;
providing switched loads having gains at each of said first and second sense points to make up for a voltage drop in said transistor switch at maximum load; and said first sense point functioning as an over-voltage protection to limit the voltage drop in said transistor switch.

US Pat. No. 10,340,784

POWER ELECTRONIC SYSTEM AND METHOD FOR SYNCHRONIZING POWER MODULES

SIEMENS AKTIENGESELLSCHAF...

1. A power electronic system for operating a three-phase load, the system comprising:a number of power modules connected to the three-phase load, each of the power modules comprising at least one switching element and a local actuator;
a superordinate controller for actuating the number of power modules to supply a three-phase output to operate the three-phase load;
a device bus connected to the superordinate controller and to the number of power modules and via which the control signals for actuating the number of power modules are transmitted during operation of the system;
the superordinate controller transmitting the control signals for at least three switching states of the system in respective messages at predefined intervals of time to the number of power modules via the device bus;
all power modules configured to scan a first communication edge of a respectively received message from the superordinate controller and process it as a common time base of the system for processing the control signals.

US Pat. No. 10,340,783

APPARATUS AND METHOD FOR CONTROLLING PULSE OUTPUT

Nuctech Company Limited, ...

1. A pulse modulating power source, which comprises:a plurality of discharging modules all connected in series during discharging;
a plurality of triggers corresponding to said plurality of discharging modules such that every discharging module of said plurality of discharging modules has a trigger, wherein each trigger provides a trigger signal to a corresponding discharging module to turn the corresponding discharging module on;
a control logic module for controlling the trigger signals so as to turn on said plurality of discharging modules successively with a time delay thereby setting each trigger of the plurality of triggers with the time delay, wherein each discharging module of said plurality of discharging modules separately turns on with the time delay and the control logic module is configured to adjust the time delay according to ?t1 ˜?t(m?1) to adjust the slope of the output voltage; and
an output terminal for outputting a voltage, wherein the output terminal is not connected in series with an inductor.

US Pat. No. 10,340,782

METHOD OF REDUCING SOUND FROM LIGHT FIXTURE WITH STEPPER MOTORS

Harman Professional Denma...

1. A light fixture comprising:at least one light source generating a light beam; and
a stepper motor including a stepper motor stator and a stepper motor rotor, where the stepper motor rotor comprises a stepper motor axle and is rotatable around a stepper motor axis; the stepper motor is connected to a movable object and is configured to move the movable object in relation to a reference point to modify the light beam as generated by the at least one light source;
wherein a damping mass is attached to the stepper motor axle, the damping mass having a rotational inertia in relation to the stepper motor axis which is at least as large as the rotational inertia of the stepper motor rotor in relation to the stepper motor axis.

US Pat. No. 10,340,781

LINEAR MOTOR

AAC TECHNOLOGIES PTE. LTD...

1. A linear motor comprising:a housing;
a vibrating assembly arranged in the housing, the vibrating assembly including a weight and a plurality of coils connecting with the weight;
a magnet assembly connecting with the housing, the magnet assembly including a main magnet and a side magnet; and
an elastic connecting piece supporting the vibrating assembly in the housing elastically; wherein
the coils are arranged around the main magnet; and the side magnet is arranged adjacent to peripheries of the coils;
wherein the elastic connecting piece comprises a main body part for fixing the coils and an elastic connecting part extending respectively from two sides of the main body part; and the elastic connecting part is connected with the housing.

US Pat. No. 10,340,780

TRANSVERSE FLUX MACHINE

Kabushiki Kaisha Toshiba,...

1. A transverse flux machine comprising:a stator including a winding wound along a rotational direction of a rotation axis, and a first ferromagnetic unit having L (L is integer number) magnetic poles holding the winding; and
a rotor rotatable relatively to the stator around the rotation axis, the rotor including a second ferromagnetic unit divided into L pieces, the L pieces having L magnetic poles facing the L magnetic poles of the first ferromagnetic unit;
wherein
if an order of harmonic component of torque ripple to be reduced is (N×1), (N×2), . . . , (N×(M?1)) (M and N are integer numbers. ML), among the L magnetic poles in the first and second ferromagnetic units, a relative position of M magnetic poles along the rotational direction is shifted by ?1 ((180°/N/M)?1(540°/N/M)) in order,
magnetic poles of at least one of the first and second ferromagnetic units are divided into I pieces (I is integer number) respectively,
if the order of harmonic component of torque ripple to be reduced is (N×1), (N×2), . . ., (N×(J?1)) (J is integer number, JI), among I magnetic poles divided, a relative position of J magnetic poles along the rotational direction is shifted by ?2 ((180°/N/J)?2(540°/N/J)) in order.

US Pat. No. 10,340,779

LINE START PERMANENT MAGNET MOTOR USING A MODULAR ROTOR

Coreteq Systems Ltd., Su...

1. A method of operating a rotor system for a downhole motor comprising at least one permanent magnet rotor section, and at least one induction rotor section, the permanent magnet rotor section and the induction rotor section being joined in series by a connection, the method including using the induction rotor section to turn the permanent magnet rotor section until the permanent magnet rotor section is operating at synchronous speed.

US Pat. No. 10,340,778

PARALLEL MAGNETIC CIRCUIT MOTOR

QM Power, Inc., Kansas C...

1. A machine, comprising:a rotor without magnets; and
a stator comprising a plurality of phase sections, each phase section corresponding to one of a plurality of electrically independent phases of the machine and each phase section having pairs of pole faces of permanent magnets arranged with same facing magnetic poles in which a magnetic pole of a permanent magnet faces a same magnetic pole of another permanent magnet, a plurality of stator poles between the same facing permanent magnet pole faces, and a winding on each of the stator poles.

US Pat. No. 10,340,777

LINE START PERMANENT MAGNET MOTOR

COREteQ Systems Ltd., Ba...

1. A downhole electric submersible pump, comprising at least one pump unit having a pump inlet, and an electric motor system to power the pump, the electric motor system comprising an induction motor and permanent magnet motor, the induction motor being capable of turning the permanent magnet motor until the permanent magnet motor can operate at synchronous speed.

US Pat. No. 10,340,775

APPARATUS FOR WINDING AND TERMINATING DYNAMO ELECTRIC MACHINE CORES

1. Apparatus for winding and terminating coils wound with at least one electric wire on a core of a dynamo electric machine; the core having a longitudinal axis; the apparatus comprising:a wire dispenser; the dispenser having a tubular portion for passage of the wire and an exit from where the wire reaches the core;
a first motor for translating the dispenser with respect to the core during winding or the termination of leads;
tubular support for supporting the core;
a second motor for rotating the tubular support of the core around a rotation axis;
a pulley wheel where the wire is wound before entering the passage portion of the dispenser;
a recovery device of the wire that draws the wire returning from the pulley wheel;
characterized in that the feeding the wire comprises:
a device for applying torque in two directions on the pulley wheel as a function of the position of the dispenser in the translation and the position of the core in the rotation.

US Pat. No. 10,340,774

TEMPERATURE ESTIMATING DEVICE OF ELECTRIC MOTOR

FANUC CORPORATION, Yaman...

1. A temperature estimating system for estimating an actual temperature of a measurement target part of an electric motor, the temperature estimating system comprising:the electric motor;
a temperature sensor attached to the measurement target part of the electric motor, the measurement target part being a winding of the electric motor, and the temperature sensor comprises a temperature detecting element and a resin covering the temperature detecting element;
a memory configured to store a detected temperature detected by the temperature sensor;
a processor that performs processing for correcting the detected temperature stored in the memory to an estimated temperature on the basis of the detected temperature; and
an alarm that generates an alarm sound or displays an alarm message upon receiving a respective command from the processor,
wherein the processor is programmed to:
acquire the detected temperature detected by the temperature sensor to successively store the detected temperature in the memory at a predetermined sampling period;
calculate a first estimated temperature by weighting the detected temperature on the basis of amount of change of the detected temperature per unit time or average value of amounts of change thereof and a coefficient that is predetermined so that an estimated temperature of the measurement target part approaches the actual temperature of the measurement target part, and further calculate a second estimated temperature by weighting the first estimated temperature on the basis of the amount of change of the detected temperature per unit time or the average value of amounts of change thereof and the coefficient; and
judge whether the electric motor is in an overheated state by comparing the second estimated temperature with a predetermined threshold value and issue a warning command to the alarm when it is judged that the electric motor is in the overheating state;
wherein the first estimated temperature Tcn at time tn, where “n” is a whole number of 2 or more, is calculated using the equation:

wherein:
Tn is the detected temperature of the measurement target part at the time tn,
K is the coefficient,
tn?1 is time before the time tn,
Aavr is the average value of amounts of change of the detected temperature per the unit time, and
Tn?1 is the detected temperature of the measurement target part at the time tn?1, and
wherein the second estimated temperature Tcn+1 at time ttn+1, where “n” is a whole number of 2 or more is calculated, using the following equation:

wherein:
tn+1 is time after the time tn,
A(n+1) is the amount of change of the detected temperature per the unit time during the time period from the time tn to the time tn+1, and
Tn+1 is the detected temperature of the measurement target part at the time tn+1.

US Pat. No. 10,340,773

BRUSHLESS MOTOR HAVING AN OUTER ROTOR AND AN ANNULAR SEPARATION PLATE BETWEEN THE DRIVE MAGNET AND THE POSITION DETECTION MAGNET

Tokyo Parts Industrial Co...

1. A brushless motor having an outer rotor whereinthe rotor has a rotary shaft, a rotor case fixed to the rotary shaft, and a cylindrical drive magnet and a cylindrical position detection magnet fixed to the inside of the rotor case, along the axial direction,
the drive magnet and the position detection magnet are alternately magnetized to N poles and S poles, in the circumferential direction,
an annular separation plate is disposed between the drive magnet and the position detection magnet, and
the separation plate has a positioning part for positioning the drive magnet and the position detection magnet in the circumferential direction.

US Pat. No. 10,340,772

ELECTRONICALLY COMMUTATED FAN MOTORS AND SYSTEMS

Orange Motor Company L.L....

1. A refrigeration system comprising:a refrigerant line coupling a compressor, a condenser, a valve mechanism, and an evaporator;
an evaporator fan comprising an electronically commutated fan motor;
a cooling system control circuit electrically coupled to the electronically commutated fan motor; and
the electronically commutated fan motor comprising
a motor housing comprising an exterior wall;
a shaft;
a shaft drive assembly rotatably coupled to the shaft;
a power input connector;
a control input connector;
a switch attached to the motor housing comprising a base and an actuator accessible outside the motor housing, the actuator comprising a first actuator position and a second actuator position;
a controller configured to control the shaft drive assembly based on a control signal from the control input connector, a power signal from the power input connector, and a switch signal from the switch;
wherein operation of the shaft drive assembly and the shaft is characterized by a rotation speed and a rotation direction; and
the controller is configured to control the rotation direction of the shaft drive assembly and the shaft based on the switch signal and the power signal;
wherein the controller is configured to switch the direction of rotation in response to the actuator moving from the first actuator position to the second actuator position;
wherein the controller configured to sense when a power signal is present at the power input connector;
wherein the controller is configured to disable changes to the rotation direction of the evaporator fan when a power signal is detected at the power input connector; and
the control circuit configured to provide a control signal to the control input connector for adjusting a speed of a blower fan.

US Pat. No. 10,340,771

FAN MOTOR WITH HEAT SINK AND DISCHARGE SECTION

DENSO CORPORATION, Kariy...

1. A fan motor comprising:a motor body including a stator and a rotor that rotates in response to a magnetic field of the stator;
a fan that rotates accompanying rotation of the rotor;
a controller that includes a circuit board configuring a control circuit to control passing of current to the stator and a circuit element attached to the circuit board;
a heat sink that is attached to the controller and that includes a heat dissipating section for dissipating heat from the controller, the heat dissipating section including at least a projection configuring the heat dissipating section;
a case body that includes a motor holder provided at a periphery of the rotor, and a center piece supporting the stator, with the heat dissipating section disposed between the center piece and the motor holder and the center piece forming an airflow passage along which airflow passes;
an introduction section through which airflow flowing toward the heat dissipating section is introduced;
a discharge section through which the airflow that has been introduced through the introduction section is discharged toward the fan side; and
a facing wall that is disposed at a downstream side of the airflow passing through the projection with respect to the heat dissipating section, that extends in a direction to obstruct the airflow, and that extends along an axial direction of the motor,
wherein the projection and the facing wall are disposed facing each other in a radial direction of the motor.

US Pat. No. 10,340,770

STATOR UNIT, MOTOR, AND PARALLEL FAN

NIDEC CORPORATION, Kyoto...

1. A stator unit comprising:a cylindrical bearing housing extending along a central axis extending in a vertical direction;
a base member fixing the bearing housing;
a stator fixed to an outer circumferential surface of the bearing housing; and
a mold resin portion covering the stator; wherein
the stator includes:
a stator core including a plurality of teeth projecting radially outward;
an insulator covering a portion of a surface of the stator core; and
a plurality of coils each of which is defined by a conducting wire wound around a separate one of the teeth with the insulator therebetween; and
a sealing agent is located between the outer circumferential surface of the bearing housing and the insulator, and/or between the insulator and the stator core.

US Pat. No. 10,340,769

AUXILIARY DRIVE DEVICE

BorgWarner Inc., Auburn ...

1. An auxiliary drive device comprisingan electric motor having a rotor, which is rotatable about an axis, and a stator that is received within the rotor; and
a viscous clutch having a housing, a clutch disk and a reservoir, the housing being coupled to the rotor for common rotation about the axis, the clutch disk being received in the housing and being rotatable about the axis relative to the housing, the housing and the clutch disk forming a working chamber, the reservoir being coupled in fluid communication to the working chamber.

US Pat. No. 10,340,768

FLYWHEEL ENERGY STORAGE DEVICE WITH INDUCTION TORQUE TRANSFER

1. A system for transferring torque, said system comprising:a plurality of electric coils arranged in the shape of a toroid and configured so that, upon the application of electric current through the plurality of coils, adjacent coils generate magnetic fields of opposing polarities;
a primary rotor having a plurality of permanent primary magnets positioned within the plurality of electric coils for passing through the plurality of electric coils and configured as a primary cylinder having a primary magnetic field, said primary magnets comprising circumferentially oriented permanent magnets;
a secondary rotor mounted coaxially with the primary rotor externally of the plurality of coils and for rotation relative to the plurality of electric coils, the secondary rotor including a plurality of permanent secondary magnets configured as a secondary cylinder having a secondary magnetic field directed toward the primary rotor and configured to magnetically couple with the primary cylinder, and wherein the plurality of permanent primary magnets are configured as a primary cylinder having a primary magnetic field directed toward the secondary rotor and are configured to magnetically couple with the secondary cylinder, to thereby effectuate the transfer of torque from the primary rotor to the secondary rotor;
an induction cylinder positioned between said primary rotor and said secondary rotor, wherein said induction cylinder comprises an electrically conductive material.

US Pat. No. 10,340,767

MOTOR WITH BUSBAR UNIT MOUNTED ON BEARING FLANGE

NIDEC CORPORATION, Kyoto...

1. A motor comprising:a rotor comprising a shaft having a central axis as a center thereof;
a stator arranged radially outside of the rotor;
a bearing arranged on an upper side of the stator and structured to rotatably support the shaft;
a tubular housing arranged to hold the stator;
a bearing holder arranged on the upper side of the stator and structured to hold the bearing; and
a busbar unit arranged on an upper side of the bearing holder and structured to supply an electric drive current to the stator;
wherein the rotor comprises a rotor magnet directly or indirectly fixed to the shaft;
the stator comprises:
an annular core back;
teeth arranged to extend radially inward from the core back; and
coils wound around the teeth;
the housing comprises a housing tubular portion;
the housing tubular portion comprises a housing inner circumferential surface arranged to hold the stator;
the bearing holder is arranged to be in contact with the housing inner circumferential surface; and
the busbar unit is arranged to be in contact with the housing inner circumferential surface;
wherein the busbar unit comprises:
at least one busbar electrically connected to the stator; and
a busbar holder arranged to hold the at least one busbar;
the busbar holder comprises:
a holder body portion; and
a plurality of abutment portions each of which is arranged to project downward from the holder body portion;
the plurality of abutment portions are arranged at regular intervals along a circumferential direction; and
a lower surface of each abutment portion is arranged to be in contact with an upper surface of the bearing holder, and
wherein a gap is defined between the holder body portion and the bearing holder.

US Pat. No. 10,340,766

WATERPROOF STABILIZER AND WATERPROOFING METHOD THEREOF

1. A waterproof stabilizer, comprising: a fixing assembly, a rotating assembly, a circuit board and a waterproof assembly, wherein the rotating assembly comprises a first motor, a second motor, a third motor, a first connecting arm and a second connecting arm, wherein the first motor, the second motor and the third motor are orthogonally arranged in space, a rotor of the first motor is connected with the fixing assembly, a stator of the first motor is fixedly connected with a rotor of the second motor via the first connecting arm, a stator of the second motor is fixedly connected with a rotor of the third motor via the second connecting arm, and the first motor, the second motor and the third motor are respectively connected to the circuit board via a connecting base;a first protective case and a first protective cover are arranged on an outside of the first motor, a side wall of the first protective case is connected to the first connecting arm, and the first protective cover is covered on the first protective case; a second protective case and a second protective cover are arranged on an outside of the second motor, a side wall of the second protective case is connected to the second connecting arm, and the second protective cover is covered on the second protective case;
a waterproof assembly comprises a first sealing ring, a second sealing ring, a third sealing ring, a fourth sealing ring, a first waterproof plug, a second waterproof plug, a third waterproof plug, a first waterproof layer, a second waterproof layer, a third waterproof layer, and a waterproof membrane;
wherein the first sealing ring is arranged between the fixing assembly and the rotor of the first motor;
the second sealing ring is arranged between the first protective case and the first protective cover;
the third sealing ring is sleeved on a shaft of the second motor;
the fourth sealing ring is arranged between the second protective case and the second protective cover;
the first waterproof plug is arranged between the side wall of the first protective case and the first connecting arm;
the second waterproof plug is arranged between the side wall of the second protective case and the second connecting arm;
the third waterproof plug is arranged at an end of a shaft of the third motor, and a shaft hole of the third motor is plugged by the third waterproof plug;
the first waterproof layer is arranged on a surface of the circuit board, the second waterproof layer is covered on the first waterproof layer, and the third waterproof layer is covered on the second waterproof layer; and
the waterproof membrane is covered on a surface of the connecting base.

US Pat. No. 10,340,765

DRIVE APPARATUS HAVING MOTOR UNIT RECEIVED IN MOTOR CASE

DENSO CORPORATION, Kariy...

1. A drive apparatus comprising:a motor unit;
a motor case that is shaped into a tubular form and has a first space, which receives the motor unit;
a frame that contacts an inner peripheral wall of the motor case at a contact location and is fixed to an inside of the motor case;
at least one cutout that is formed in at least one of the inner peripheral wall of the motor case and an outer peripheral wall of the frame and is located on an opposite side of the contact location, which is opposite from the first space, wherein the at least one cutout forms a seal groove, which is located between the motor case and the frame and extends in a circumferential direction;
a cover that covers the seal groove and forms a second space on an opposite side of the frame, which is opposite from the first space; and
a seal material that is received in the seal groove and contacts each of the motor case, the frame and the cover in a radial direction relative to an axis of the motor unit, wherein:
the cover includes an inserting portion that is inserted into an inside of the at least one cutout and inserted into the seal material, and
the seal material includes one portion, which seals between the inserting portion and the frame, and another portion, which seals between the inserting portion and the motor case.

US Pat. No. 10,340,763

ISOLATION RING FOR ELECTRIC MOTOR END WINDINGS

GM GLOBAL TECHNOLOGY OPER...

1. An electric motor for a vehicle drive unit, comprising:a housing;
a stator fixed within the housing and including a plurality of end windings;
a rotor disposed within the housing and connected to a drive shaft;
an isolating ring made from a dielectric material and having a thickness of 1 mm or less is disposed within the housing between the end windings and the housing and defining an air gap completely between the end windings and the isolating ring, wherein the isolation ring is sprayed on an interior surface of the housing.

US Pat. No. 10,340,762

STATOR FOR ELECTRIC ROTARY MACHINE AND METHOD FOR PRODUCING THE STATOR

HONDA MOTOR CO., LTD., T...

1. A stator for an electric rotary machine comprising:a stator core, which has plural slots; and
a coil, which is attached to the stator core, wherein:
the coil has plural slot coils and plural connection coils, each slot coil being inserted into the slot, each connection coil connecting the slot coils in a position lying further axially outwards than an axial end face of the stator core, and the coil being constituted in such a way that the slot coil and the connection coil are joined at an abutment portion;
the connection coil is accommodated in an accommodating portion, which is provided in an insulation plate that is made of an insulation material and that is disposed outwards of the axial end face of the stator core;
the connection coil is such that a connection coil main body extends from one side to an other side in a circumferential direction;
the connection coil main body abuts against the insulation plate in such a state that the connection coil is accommodated in the accommodating portion; and
in a hole portion, where the abutment portion is accommodated, of the insulation plate, the connection coil and the slot coil are spaced apart from the insulation plate in the circumferential direction to thereby form a first gap portion.