US Pat. No. 10,217,989

POUCH-TYPE SECONDARY BATTERY CONTAINING ELECTROLYTE HOLDING PART

LG Chem, Ltd., Daejeon (...

1. A secondary battery, comprising:an electrode assembly that is sealed in a receiving portion of a pouch-type battery case together with an electrolyte,
wherein the pouch-type battery case is formed from a laminate sheet having an exterior coating layer, a metal layer and an interior adhesive layer; and
an electrolyte holding portion for replenishing an electrolyte that is depleted during the manufacturing process or the use of the secondary battery is contained in the laminate sheet, without contacting the electrolyte disposed in the receiving portion of the battery case.

US Pat. No. 10,217,988

SECONDARY BATTERY

NEC ENERGY DEVICES, LTD.,...

1. A secondary battery comprising a battery electrode assembly in which a positive electrode and a negative electrode are alternately laminated while a separator is interposed therebetween, whereineach of said positive electrode and said negative electrode comprises a current collector and an active material that is applied on said current collector,
each surface of said current collector is provided with an application portion and a non-application portion, said application portion being a portion on which said active material is applied, said non-application portion being a portion on which said active material is not applied, and
said active material comprises a thin portion whose thickness is small, at least at a part of an outer edge portion of said application portion, and a charging capacity ratio A/C between said negative electrode and said positive electrode that face each other at the outer edge portion containing said thin portion is higher than the charging capacity ratio A/C between said negative electrode and said positive electrode that face each other at a center side with respect to the outer edge portion, the charging capacity ratio A/C being a ratio between a charging capacity A of said negative electrode and a charging capacity C of said positive electrode.

US Pat. No. 10,217,987

SYSTEMS AND METHODS FOR MANUFACTURING BATTERY PARTS

Water Gremlin Company, W...

17. A battery part manufacturing machine, comprising:a shaft configured to support a battery part having a sealing feature; and
a tool having a forming portion and positioned adjacent to the battery part, wherein the forming portion is configured to engage the sealing feature of the battery part, wherein the tool is rotatable about an axis of rotation, and wherein the axis of rotation of the tool is movable in a first direction toward the battery part and in a second direction away from the battery part.

US Pat. No. 10,217,986

BATTERY CONNECTION BODY AND BATTERY PACK PROVIDED WITH THE BATTERY CONNECTION BODY

YAZAKI CORPORATION, Toky...

1. A battery connection body comprising:a plurality of connection conductors which electrically connect respective battery cells forming a battery assembly;
a casing to which the connection conductors are mounted, and which comprises a first side and a second side different from the first side; and
a plurality of first electric wires and a plurality of second electric wires, which are wired in the casing,
wherein the casing comprises:
a connection conductor mounting portion;
a first electric wire housing portion; and
a second electric wire housing portion,
wherein the first side of the casing is opposite to the second side of the casing in a direction perpendicular to a longitudinal arrangement of the plurality of the first and second electric wires,
wherein the connection conductors are mounted to the connection conductor mounting portion from the first side of the casing,
wherein the first electric wires are configured to be received into the first electric wire housing portion from a first direction,
wherein the second electric wires are configured to be received into the second electric wire housing portion from a second direction opposite to the first direction, and
wherein the electric wires are voltage detection lines and the second electric wires are thermistor lines.

US Pat. No. 10,217,985

SEPARATOR FOR LITHIUM SECONDARY BATTERY, LITHIUM SECONDARY BATTERY USING THE SEPARATOR, AND METHOD OF MANUFACTURING THE LITHIUM SECONDARY BATTERY

Samsung SDI Co., Ltd., Y...

1. A separator for a lithium secondary battery, the separator comprising:a porous base, at least a portion of the porous base comprising at least one selected from polyethylene terephthalate, polybutylene terephthalate, polyester, polyacetal, polyamide, polycarbonate, polyimide, polyether ether ketone, polyether sulfone, polyphenylene oxide, polyphenylene sulfide, polyvinylidene fluoride, polyethylene oxide, polyacrylonitrile, a polyvinylidene fluoride-hexafluoropropylene copolymer, polyethylene, and polypropylene; and
a first coating layer directly on a surface of the portion of the porous base and a second coating layer on a surface of the porous base opposite to the first coating layer, the first coating layer and the second coating layer each comprising a (meth)acrylic acid ester-based polymer having a glass transition temperature of about 10° C. to about 60° C.,
wherein the (meth)acrylic acid ester-based polymer is a polymerization product of an ethylenically unsaturated carboxylic acid ester and a monomer that is copolymerizable with the ethylenically unsaturated carboxylic acid ester,
wherein the ethylenically unsaturated carboxylic acid ester is a mixture of 2-ethylhexyl acrylate, isobornyl acrylate, and hydroxyethyl acrylate, or a mixture of methyl acrylate, ethyl acrylate, and hydroxyethyl acrylate, and
the monomer that is copolymerizable with the ethylenically unsaturated carboxylic acid ester is a mixture of acrylonitrile, methacrylic acid, acrylic acid, and ethylene dimethacrylate.

US Pat. No. 10,217,984

SEPARATOR AND LITHIUM ION SECONDARY BATTERY INCLUDING THE SAME

TDK CORPORATION, Tokyo (...

1. A separator comprising a porous base material including a thermoplastic resin, whereinthe porous base material has a heat-resistant porous layer on at least one surface thereof, and
the heat-resistant porous layer contains inorganic particles, a resin, and sulfur,
the sulfur is distributed unevenly in the heat-resistant porous layer so as to exist in larger amount near a surface thereof opposite to the porous base material.

US Pat. No. 10,217,981

BATTERY MODULE

Samsung SDI Co., Ltd., Y...

1. A battery module comprising:a plurality of battery cells aligned in a first direction; and
a housing portion fixing the plurality of battery cells,
wherein central parts of the plurality of battery cells are concave such that a concave part of one of the plurality of battery cells faces the central part of an adjacent one of the battery cells along the first direction, and
wherein first adhesive members are between adjacent ones of the battery cells, the first adhesive members being located at boundary portions of the plurality of battery cells and defining an opening that corresponds to the concave parts of the plurality of battery cells.

US Pat. No. 10,217,980

SECONDARY BATTERY

Samsung SDI Co., Ltd., Y...

1. A secondary battery comprising:a case defining an inner space;
an electrode assembly in the case, the electrode assembly comprising:
a first electrode plate;
a second electrode plate; and
a separator between the first and second electrode plates;
a cap plate sealing the case and electrically connected to the first electrode plate of the electrode assembly, the cap plate comprising a safety vent and a vent opening, the safety vent being coupled to the cap plate at the vent opening to seal the vent opening, the safety vent being electrically connected to the cap plate;
an electrode terminal part extending through the cap plate; and
a connector having a first end electrically connected to the electrode terminal part and a second end electrically connected to the safety vent,
wherein the safety vent comprises:
a fixed part fixed to the cap plate at the vent opening;
a rupture part inside the fixed part and defining a notch;
a coupling part inside the rupture part, and electrically coupled to the second end of the connector; and
a connection part connecting the coupling part to the rupture part, wherein the connection part has a concave shape in which a lower surface of the coupling part protrudes inwardly toward the inside of the case,
wherein the coupling part has a thickness that is greater than thicknesses of the fixed part, the rupture part, and the connection part.

US Pat. No. 10,217,979

CONTAINMENT SYSTEM AND METHOD FOR HIGH ENERGY DENSITY DEVICES

The Boeing Company, Chic...

1. A containment system comprising:a primary containment layer at least partially defining a primary containment volume configured to at least partially receive a high energy density device, said primary containment layer comprising a thermal material;
a secondary containment layer at least partially defining a secondary containment volume, said secondary containment layer comprising a layered structure and a gas capturing material incorporated into said layered structure, wherein said gas capturing material comprises at least one of an adsorbent and an absorbent, and wherein said primary containment layer is positioned in said secondary containment volume; and
a tertiary containment layer at least partially defining a tertiary containment volume, said tertiary containment layer comprising a ballistic material, wherein said secondary containment layer is positioned in said tertiary containment volume to define an air space between said secondary containment layer and said tertiary containment layer, and wherein said secondary containment layer fluidly isolates said secondary containment volume from said air space.

US Pat. No. 10,217,978

ENERGY STORAGE DEVICE ARRANGEMENT INCLUDING RECEIVING PARTS HAVING THROUGH OPENINGS FOR LASER ENERGY

AUDI AG, Ingolstadt (DE)...

1. An energy storage device arrangement, comprising:a first receiving part having a plurality of first bore-like receiving spaces for respectively receiving a first plurality of electrical energy storage devices;
a second receiving part that is or can be connected with the first receiving part, having a plurality of second bore-like receiving spaces for respectively receiving a second plurality of electric energy storage devices,
wherein each of the first plurality of electrical energy storage devices and the second plurality of electrical energy storage devices have a front contacting pole on a first face and a rear contacting pole on a second face;
at least one plate-like electrical connecting part, which is or can be arranged between the first receiving part and the second receiving part that are or can be arranged adjacently, for electrical contacting of the first plurality of electrical energy storage devices and the second plurality of electric energy storage devices,
wherein the first and second receiving parts are or can be arranged adjacently in such a way that the front contacting poles of each of the first plurality of electrical storage devices are proximate the at least one plate-like electrical connecting part and the rear contacting poles of each of the second plurality of electrical energy storage devices are proximate the at least one plate-like electrical connecting part; and
a plurality of first separate through-openings in the first receiving part and a plurality of second separate through-openings in the second receiving part for the through-passage of laser energy,
wherein all the plurality of the first bore-like receiving spaces is wholly arranged so as to be distributed in a matrix-like manner forming a first matrix arrangement,
all the plurality of the second bore-like receiving spaces is wholly arranged so as to be distributed in the matrix-like manner forming a second matrix arrangement, and
the first matrix arrangement is wholly offset relative to the second matrix arrangement,
the at least one plate-like electrical connecting part includes a first contacting region which the front contacting poles of each of the first plurality of electrical storage devices are proximate and a second contacting region which the rear contacting poles of each of the second plurality of electrical energy storage devices are proximate, and
the first contacting region is offset relative to the second contacting region.

US Pat. No. 10,217,977

BATTERY PACK WITH CELLS OF DIFFERENT CAPACITIES ELECTRICALLY COUPLED IN PARALLEL

Apple Inc., Cupertino, C...

1. A battery pack, comprising:a first set of cells electrically coupled in a first parallel configuration, the first set of cells comprising a first cell, second cell, and third cell; and
wherein the first cell, second cell and third cell each have different capacities and dimensions;
wherein the capacity of the first cell is substantially the same as the cumulative capacity of the second cell and third cell;
wherein the first set of cells has a first overall capacity;
a second set of cells electrically coupled in a second parallel configuration, the second set of cells comprising a fourth cell, fifth cell, and sixth cell;
wherein the fourth cell, fifth cell, and sixth cell each have different capacities and dimensions;
wherein the capacity of the fourth cell is substantially the same as the cumulative capacity of the fifth cell and sixth cell;
wherein the second set of cells has a second overall capacity;
wherein the first set of cells and the second set of cells are arranged in an asymmetric configuration;
wherein the first overall capacity is substantially the same as the second overall capacity, and
wherein the first set of cells and the second set of cells are electrically coupled in a series configuration.

US Pat. No. 10,217,976

SECONDARY BATTERY AND SECONDARY BATTERY PACK INCLUDING THE SAME

SAMSUNG SDI CO., LTD., Y...

5. The secondary battery as claimed in claim 3, wherein at least the second region and the third region in the first coverlay and the second coverlay are coated by an insulating film.

US Pat. No. 10,217,975

PACKAGING MATERIAL FOR POWER STORAGE DEVICE AND POWER STORAGE

TOPPAN PRINTING CO., LTD....

1. A packaging material for a power storage device, comprising:in order from a first surface of a metal foil, a first corrosion protection layer and a coating layer; and
in order from a second surface of the metal foil, a second corrosion protection layer, an adhesive layer, and a sealant layer, and,
wherein the coating layer contains at least one resin selected from the group consisting of fluorine resins and amorphous polyester resins,
and wherein a) the metal foil is in direct contact with the first corrosion protection layer without an adhesive layer in between and b) the first corrosion protection layer in is in direct contact with the coating layer.

US Pat. No. 10,217,974

SEALANT FILM FOR PACKAGING MATERIAL OF POWER STORAGE DEVICE, PACKAGING MATERIAL FOR POWER STORAGE DEVICE, AND POWER STORAGE DEVICE

SHOWA DENKO PACKAGING CO....

1. A sealant film for a packaging material of a power storage device, comprising:a laminated body of two or more layers,
wherein the laminated body includes
a first resin layer containing 50 mass % or more of a random copolymer containing propylene and another copolymer component other than propylene as copolymer components,
a second resin layer formed by a mixed resin containing a first elastomer-modified olefin based resin having a melting point of 155° C. or higher and a crystal melting energy of 50 J/g or more, and a second elastomer-modified olefin based resin having a melting point is 135° C. or higher and a crystal melting energy of 30 J/g or less,
wherein the first elastomer-modified olefin based resin is made of elastomer-modified homopolypropylene and/or elastomer-modified random copolymer,
wherein the second elastomer-modified olefin based resin is made of elastomer-modified homopolypropylene and/or elastomer-modified random copolymer,
wherein the elastomer-modified random copolymer is an elastomer-modified product of a random copolymer containing propylene and another copolymer component other than propylene as copolymer components, and
wherein in the second resin layer, a total value of a content rate of the first elastomer-modified olefin based resin and a content rate of the second elastomer-modified olefin based resin is 50 mass % or more.

US Pat. No. 10,217,973

PRISMATIC SECONDARY BATTERY

SANYO Electric Co., Ltd.,...

1. A prismatic secondary battery, comprising:a first electrode sheet including a first exposed core portion;
a second electrode sheet including a second exposed core portion;
a flat wound electrode body obtained by winding the first electrode sheet and the second electrode sheet with a separator interposed therebetween and winding a separator as an outermost layer;
a non-aqueous electrolyte solution;
an exterior body that has an opening and that contains the wound electrode body and the non-aqueous electrolyte solution;
a sealing plate that closes the opening;
a first current collector connected to the first exposed core portion;
a second current collector connected to the second exposed core portion;
a first terminal that is connected to the first current collector and that is mounted in the sealing plate; and
a second terminal that is connected to the second current collector and that is mounted in the sealing plate,
wherein a winding axis of the wound electrode body is parallel to a longitudinal direction of the sealing plate,
wherein the first exposed core portion is disposed along an end portion of the wound electrode body in a direction in which the winding axis extends, and the second exposed core portion is disposed along the other end portion,
wherein the first current collector includes a first base disposed along the sealing plate and a first lead that is connected to an end portion of the first base and that extends toward the wound electrode body,
wherein the second current collector includes a second base disposed along the sealing plate and a second lead that is connected to an end portion of the second base and that extends toward the wound electrode body,
wherein the first lead is connected to the first exposed core portion,
wherein the second lead is connected to the second exposed core portion,
wherein a distance between an end portion of the wound electrode body facing the sealing plate and a surface of the first base facing the wound electrode body at an end portion of the first base on a central side in the longitudinal direction of the sealing plate is shorter than a distance between the end portion of the wound electrode body facing the sealing plate and a surface of the second base facing the wound electrode body at an end portion of the second base on the central side in the longitudinal direction of the sealing plate, and
wherein an insulating buffer that differs from the separators is disposed between the wound electrode body and the surface of the first base facing the wound electrode body at the end portion of the first base on the central side in the longitudinal direction of the sealing plate.

US Pat. No. 10,217,972

BATTERY PACK

Sony Corporation, Tokyo ...

1. A battery comprising:a pack main body having a front side and a back side in a length direction, a top side and bottom side in a height direction, and opposite sides in a width direction in which a battery cell is embedded; and
a terminal portion provided on the front side of the pack main body,
wherein the pack main body includes first bevelled portions at corner portions formed by the top side and the opposite sides and second bevelled portions at corner portions formed by the bottom side and the opposite sides, and
wherein the terminal portion protrudes from the front side of the pack main body at a position biased to one side with respect to center lines in the width direction and the height direction, and
wherein third bevelled portions are formed at corner portions formed by the front side, and the top side, and the bottom side of the pack main body and a fourth bevelled portions are formed at corner portions formed by the back side, and the top side, and the bottom side of the pack main body, and
wherein the fourth bevelled portions are smaller than the third bevelled portions, and
wherein the first bevelled portions and the second bevelled portions are differently shaped.

US Pat. No. 10,217,971

POWER STORAGE UNIT AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A power storage unit comprising:a positive electrode comprising a positive electrode current collector;
a negative electrode;
a separator between the positive electrode and the negative electrode;
an electrolyte solution;
a positive electrode lead; and
an exterior body,
wherein the positive electrode current collector comprises a positive electrode tab,
wherein the positive electrode tab comprises a bend portion and a connection region,
wherein the connection region is electrically connected to the positive electrode lead,
wherein the positive electrode, the negative electrode, the separator, the bend portion, the connection region, and the electrolyte solution are in the exterior body,
wherein the exterior body comprises a surface at least part of which includes alternating projections and depressions,
wherein a first cross-sectional shape of the surface is a wave shape formed by the projections and the depressions,
wherein a second cross-sectional shape of the surface is a closed loop without a seam, and
wherein the bend portion comprises a depression shape and a projection shape.

US Pat. No. 10,217,970

STEEL PLATE FOR FORMING BATTERY CAN AND ALKALINE BATTERY

FDK CORPORATION, Tokyo (...

1. A steel plate for forming a battery can to be formed into the battery can by presswork, the steel plate for forming the battery can comprising:an iron and nickel diffusion layer or an iron and nickel-cobalt alloy diffusion layer formed by forming a nickel plated layer or a nicker-cobalt alloy plated layer with a thickness of 0.5 to 2.0 ?m on an inner surface of a battery can of a steel plate as a base material, and subsequently performing heat diffusion treatment on the nickel plated layer or the nickel-cobalt alloy plated layer,
wherein an average number of crystal grains per 0.25 mm2 unit area of the steel plate as the base material is equal to or more than 12.3 and equal to or less than 14.0.

US Pat. No. 10,217,969

ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR FABRICATING THE SAME

LG DISPLAY CO., LTD., Se...

1. An OLED display device comprising:first and second electrodes on a substrate;
a red light-emitting layer, a green light-emitting layer and a blue light-emitting layer between the first and second electrodes;
a hole transport layer between each of the red light-emitting layer, the green light-emitting layer and the blue light-emitting layer, and the first electrode;
an electron transport layer formed between each of the red light-emitting layer, the green light-emitting layer and the blue light-emitting layer, and the second electrode;
a reflective layer on a surface of the substrate; and
a conducting polymer layer between the reflective layer and the first electrode,
wherein the conducting polymer layer has a first thickness, a second thickness, and a third thickness in regions respectively corresponding to the red light-emitting layer, the green light-emitting layer and the blue light-emitting layer,
wherein the first thickness, the second thickness, and the third thickness of the conducting polymer layer are each greater than zero and different from each other, and
wherein the first thickness of the conducting polymer layer corresponds to the red light-emitting layer, the second thickness of the conducting polymer layer corresponds to the green light-emitting layer, and the third thickness of the conducting polymer layer corresponds to the blue light-emitting layer, and
wherein the first thickness is greater than the second thickness, and the second thickness is greater than the third thickness.

US Pat. No. 10,217,968

ELECTRO-OPTICAL PANEL INCLUDING STRETCH FILM

LG Display Co., Ltd., Se...

1. An electro-optical panel comprising:an electro-optical element emitting a light or adjusting a transmittance of a light; and
a stretch film including a polymeric material,
wherein a main stretching axis direction of the stretch film is disposed within 30° with respect to a side of the electro-optical panel.

US Pat. No. 10,217,967

ORGANIC ELECTROLUMINESCENT DEVICE

Rohm Co., Ltd., Kyoto (J...

1. A display device comprising an organic electroluminescent element comprising a plurality of light emissive units, each of which has at least one light emissive layer, provided between a first electrode and a second electrode opposed to said first electrode,wherein said light emissive units are partitioned from each other by at least one charge generation layer,
wherein said charge generation layer comprises an electron accepting material and an electron donating material and has a resistivity of not less than 1.0×102 ?cm,
wherein the organic electroluminescent element is configured to emit light from an area where the first electrode and the second electrode are vertically superimposed, and
wherein the area comprises a plurality of areas, each of the plurality of areas corresponding to pixels of the display device.

US Pat. No. 10,217,966

METHOD AND AN APPARATUS FOR AN ELECTROLUMINESCENT DEVICE WITH IMPROVED OUTCOUPLING

KONINKLIJKE PHILIPS N.V.,...

1. An electroluminescent device comprising:a substrate;
a substrate electrode disposed on the substrate;
a counter electrode;
at least one organic electroluminescent layer disposed between the substrate electrode and the counter electrode; and
at least one optically transparent body disposed on the substrate electrode,
wherein the optically transparent body is arranged to increase the outcoupling of light generated by the at least one organic electroluminescent layer,
wherein the at least one organic electroluminescent layer covers at least a portion of the optically transparent body;
wherein a first surface of the counter electrode that faces the substrate is covered with a reflecting material.

US Pat. No. 10,217,965

ORGANIC LIGHT EMITTING DIODE DEVICE AND DISPLAY APPARATUS

WUHAN CHINA STAR OPTOELEC...

1. A method of fabricating an organic light emitting diode device, comprising:providing a glass substrate;
forming a first electrode on the glass substrate, wherein a material of the first electrode is a transparent material;
forming an organic light emitting layer on the first electrode;
forming a second electrode on the organic light emitting layer; and
forming a light extracting enhanced layer below the glass substrate,
wherein a material of the light extracting enhanced layer comprises hollow polyimide balls with a first index of refraction and a polyimide matrix with a second index of refraction,
wherein forming the light extracting enhanced layer below the glass substrate comprises:
forming the hollow polyimide balls using a chemical imidization method;
adding the hollow polyimide balls into a dispersing liquid; and
coating the hollow polyimide balls with the dispersing liquid below the glass substrate, wherein the polyimide matrix is below the glass substrate; and
wherein the first index of refraction is less than the second index of refraction, and a thickness of the light extracting enhanced layer is between 2 ?m and 6 ?m.

US Pat. No. 10,217,964

OPTICAL MEMBER AND DISPLAY APPARATUS HAVING SAME

Changkang Chemical Co., L...

1. An optical member, comprising:a first layer comprising a convex part, which comprises a plurality of protrusions, and a cover, which has a refractive index lower than that of the convex part; and
a second layer located on at least one side of the first layer and comprising a plurality of scattering particles dispersed in an interior thereof;
wherein the cover is disposed on an upper part of the convex part to planarize the first layer, and a refractive index difference between the cover and the convex part is smaller than a refractive index difference between the convex part and air;
wherein a refractive index of the cover ranges from 1.3 to 1.5,
wherein a refractive index difference between the convex part and the cover ranges from 0.01 to 0.4,
wherein the second layer comprises a base material and the plurality of scattering particles are dispersed within the base material,
wherein a refractive index of the scattering particles ranges from 1.5 to 2.7,
wherein a refractive index difference between the base material and the scattering particles ranges from 0.01 to 0.7,
wherein a diameter of the scattering particles ranges from 0.1 ?m to 1 ?m,
wherein a thickness of the first layer ranges from 0.2 ?m to 130 ?m, a thickness of the second layer ranges from 0.1 ?m to 130 ?m, and the thickness of the first layer is greater than or equal to the thickness of the second layer, and
wherein, when a thickness of the first layer is 100 ?m, a height of the convex part ranges from 60 to 100 ?m.

US Pat. No. 10,217,963

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A display device, comprising:a flexible substrate;
a display element unit disposed on a first surface of the flexible substrate and comprising a thin-film transistor (TFT) and an organic light-emitting element coupled to the TFT; and
a protective layer comprising an organic material and disposed directly on a second surface of the flexible substrate, the second surface being opposite to the first surface,
wherein the protective layer comprises at least one material of Formula 1:

where n is a natural number equal to or greater than 2, m is an integer number between 0 and 4, X is a halogen, and R is halogen or alkyl, alkenyl, alkynyl, cycloalkyl, cycloalkenyl, cycloalkynyl, aryl, or a halide thereof having 1 to 8 carbon atoms,
wherein the protective layer comprises two or more layers having different densities or Young's moduli, and
wherein the protective layer has a structure in which more than one first layer and more than one second layer having a lower density than the first layer are alternately stacked.

US Pat. No. 10,217,962

ORGANIC EL DISPLAY DEVICE

Japan Display Inc., Toky...

1. An organic EL display device comprising:a substrate having an insulating surface;
a lower electrode on the insulating surface;
a bank covering an edge of the lower electrode, the bank has an opening exposing a part of the lower electrode and has a concave portion away from the opening;
a first inorganic barrier layer covering the lower electrode and the bank;
a first organic portion on the first inorganic barrier layer;
a second organic portion on the first inorganic barrier layer; and
a second inorganic barrier layer covering the first organic portion and the second organic portion, wherein
the first organic portion overlaps with an exposed surface of the lower electrode at the opening,
the second organic portion overlaps with the concave portion, and does not overlap with the exposed surface of the lower electrode, and
the first inorganic insulating layer and the second inorganic insulating layer are in contact with each other directly above at least a part of the opening.

US Pat. No. 10,217,961

METHOD OF MANUFACTURING DISPLAY APPARATUS AND DISPLAY APPARATUS MANUFACTURED USING THE SAME

Samsung Display Co., Ltd....

1. A display apparatus, comprising:a substrate comprising a display area where display elements are located and a pad area outside of and spaced apart from the display area;
a pad directly on an insulating layer over the pad area, the pad covering a portion of the pad area; and
an encapsulation layer covering the display area to cover the display elements,
wherein the pad does not extend into the display area such that the pad has an end surface facing the display area and located outside of the display area,
wherein the encapsulation layer comprises a first inorganic encapsulation layer covering the display area and a portion of the pad area, an organic encapsulation layer over the first inorganic encapsulation layer and having an area less than an area of the first inorganic encapsulation layer, and a second inorganic encapsulation layer over the organic encapsulation layer and contacting the first inorganic encapsulation layer outside of the organic encapsulation layer, and the portion of the pad area covered by the first inorganic encapsulation layer is adjacent to the display area, and
wherein a part of the encapsulation layer where the second inorganic encapsulation layer contacts the first inorganic encapsulation layer extends to the portion of the pad area covered by the first inorganic encapsulation layer, a first end surface of the part of the encapsulation layer facing the pad being spaced apart from the end surface of the pad.

US Pat. No. 10,217,960

OLED ENCAPSULATION METHOD

SHENZHEN CHINA STAR OPTOE...

1. An organic light-emitting diode (OLED) encapsulation method, comprising the following steps:Step 1: providing a backing plate, forming an OLED device on the backing plate, and forming a water-contact-to-release-heat layer on the backing plate to correspond to an outer circumference of the OLED device;
Step 2: providing a cover plate and coating a circle of frit on the cover plate to correspond to the outer circumference of the OLED device, such that the frit is located to correspond to the water-contact-to-release-heat layer;
Step 3: conducting high temperature sintering on the frit;
Step 4: laminating a side of the cover plate on which the frit is coated and a side of the backing plate on which the OLED device is formed to each other in a vacuum environment so as to make the frit contacting the water-contact-to-release-heat layer; and
Step 5: introducing a water-containing gas to cause reaction of the water-contact-to-release-heat layer to release heat for heating and melting the frit for bonding with the backing plate and the cover plate;
wherein the water-contact-to-release-heat layer undergoes a chemical reaction with water contained in the water-containing gas so introduced to release heat so as to be converted from a first form into a second form that is different from the first form.

US Pat. No. 10,217,959

PACKAGING MATERIAL INCLUDING RARE EARTH METAL OXIDE, ORGANIC LIGHT-EMITTING DIODE DEVICE AND METHOD FOR PACKAGING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A packaging material for a transparent device, comprising:a primary ingredient comprising a rare earth metal oxide, zinc oxide, aluminum oxide and silicon dioxide; and
an adhesive for adhering the primary ingredient,
wherein the rare earth metal oxide has a primary adsorption wavelength within a wavelength range of infrared or ultraviolet light,
wherein the primary ingredient comprises 40 wt % of Yb2O3, 20 wt % of zinc oxide, 20 wt % of aluminum oxide, and 20 wt % of silicon dioxide; or the primary ingredient comprises 75 wt % of Eu2O3 and Tb2O3 at a mass ratio of 1:1, 13 wt % of zinc oxide, 2 wt % of aluminum oxide, and 10 wt % of silicon dioxide.

US Pat. No. 10,217,958

METHOD OF MANUFACTURING CURVED DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A method of manufacturing a curved display device, the method comprising:providing a frame;
providing a flexible display panel that includes a driving circuit configured to generate an image;
attaching a first area of the flexible display panel to the frame by laminating;
attaching a second area of the flexible display panel to the frame by laminating, wherein the providing of the flexible display panel comprises attaching a release paper to a surface of the flexible display panel, the release paper comprising first and second release areas respectively corresponding to the first and second areas of the flexible display panel;
removing the first release area from the flexible display panel before attaching the first area; and
removing the second release area from the flexible display panel before attaching the second area,
wherein the first and second release areas are divided by a cutting line.

US Pat. No. 10,217,957

ORGANIC EL DISPLAY DEVICE AND METHOD OF MANUFACTURING ORGANIC EL DISPLAY DEVICE

SHARP KABUSHIKI KAISHA, ...

1. An organic EL display device, comprising:a first support member having flexibility;
an organic EL layer formed in a matrix form on the first support member; and
a second support member having flexibility and disposed opposite the first support member with the organic EL layer interposed between the first support member and the second support member,
wherein the first support member and the second support member each include an outside surface on which a plurality of bulging portions is formed,
grooves between the bulging portions of the first support member and grooves between the bulging portions of the second support member overlap with one another,
the grooves formed on one of the first support member and the second support member that is located on an image display surface side overlap with pixels on which the organic EL layer is disposed, and shapes of the grooves overlapping with the pixels are the same, and
a pitch of the pixels is an integer multiple of a distance between the grooves formed on one of the first display member and the second display member that is located on the image display surface side.

US Pat. No. 10,217,956

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a base material having an edge;
a display region over the base material;
a wiring over the base material, the wiring extending from the display region to an outside of the display region; and
a metal film over the base material, wherein
the edge of the base material is located at the outside the display region,
the base material is configured to provide a bent region and two flat regions sandwiching the bent region, and
the metal film continuously extends to the edge of the base material through the bent region and the two flat regions.

US Pat. No. 10,217,955

METHOD FOR MANUFACTURING DISPLAY PANEL, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a display panel, comprising:providing a thin film transistor (TFT) substrate;
dispersing a composite material formed from graphene and metal nanowires in a hydrophilic solvent to form a hydrophilic conductive ink;
applying the hydrophilic conductive ink onto the TFT substrate to form a composite electrode layer;
forming, on the composite electrode layer, a pixel defining layer having a plurality of openings at least partially exposing the composite electrode layer;
applying hydrophilic organic ink into the plurality of openings of the pixel defining layer to form an organic layer;
drying the composite electrode layer and the organic layer to form a first electrode and an organic light emitting structure; and
forming a second electrode on the organic light emitting structure and the pixel defining layer.

US Pat. No. 10,217,954

COMPOUND, MATERIAL FOR ORGANIC ELECTROLUMINESCENT ELEMENT, ORGANIC ELECTROLUMINESCENT ELEMENT, AND ELECTRONIC DEVICE

IDEMITSU KOSAN CO., LTD.,...

1. A compound represented by a formula (1) below,where: R3 each independently represents a hydrogen atom, a halogen atom, a hydroxyl group, a cyano group, a substituted or unsubstituted alkyl group having 1 to 30 carbon atoms, a substituted or unsubstituted alkylsilyl group having 3 to 30 carbon atoms, a substituted or unsubstituted arylsilyl group having 6 to 60 ring carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 30 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 30 ring carbon atoms, a substituted or unsubstituted alkylamino group having 2 to 30 carbon atoms, a substituted or unsubstituted arylamino group having 6 to 60 ring carbon atoms, a substituted or unsubstituted alkylthio group having 1 to 30 carbon atoms, a substituted or unsubstituted arylthio group having 6 to 30 ring carbon atoms, a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, or a substituted or unsubstituted heterocyclic group having 5 to 30 ring atoms;R2 is a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms;
when R2 has a substituent, the substituent is a halogen atom, a hydroxyl group, a cyano group, a nitro group, a carboxy group, an unsubstituted alkyl group having 1 to 30 carbon atoms, an unsubstituted alkenyl group having 2 to 30 carbon atoms, an unsubstituted alkynyl group having 2 to 30 carbon atoms, an unsubstituted alkylsilyl group having 3 to 30 carbon atoms, an unsubstituted arylsilyl group having 6 to 60 ring carbon atoms, an unsubstituted alkoxy group having 1 to 30 carbon atoms, an unsubstituted aryloxy group having 6 to 30 ring carbon atoms, an unsubstituted arylthio group having 6 to 30 ring carbon atoms, an unsubstituted oxygen-containing heterocyclic group having 5 to 30 ring carbon atoms, an unsubstituted sulfur-containing heterocyclic group having 5 to 30 ring carbon atoms, or an unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms;
when the aryloxy group and the arylthio group respectively have substituents, adjacent ones of the substituents are bonded to form a ring or are not bonded;
L1 is a single bond or a linking group and the linking group in L1 is an alkenylene group, an alkynylene group, a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a substituted or unsubstituted heterocyclic group having 5 to 30 ring atoms, a multiple linking group provided by bonding two to four groups selected from the above aromatic hydrocarbon group, a multiple linking group provided by bonding two to four groups selected from the above heterocyclic group, or a multiple linking group provided by bonding two to four groups selected from the above aromatic hydrocarbon group and the above heterocyclic group;
the above aromatic hydrocarbon group and the heterocyclic group forming the multiple linking group are mutually the same or different and adjacent ones thereof are bonded to further form a ring or are not bonded;
L2 is a linking group and the linking group represents the same as the linking group in L1 with the proviso that the heterocyclic group is selected from the group consisting of a pyridyl group, pyrimidinyl group, pyrazinyl group, pyridazynyl group, triazinyl group, quinolyl group, isoquinolinyl group, naphthyridinyl group, phthalazinyl group, quinoxalinyl group, quinazolinyl group, phenanthridinyl group, acridinyl group, phenanthrolinyl group, imidazolyl group, pyrazolyl group, triazolyl group, tetrazolyl group, indolyl group, benzimidazolyl group, indazolyl group, imidazopyridinyl group, benzotriazolyl group, furyl group, thienyl group, oxazolyl group, thiazolyl group, isoxazolyl group, isothiazolyl group, oxadiazolyl group, thiadiazolyl group, benzofuranyl group, benzothiophenyl group, benzoxazolyl group, benzothiazolyl group, benzisoxazolyl group, benzisothiazolyl group, benzoxadiazolyl group, benzothiadiazolyl group, dibenzofuranyl group, dibenzothiophenyl group, piperidinyl group, pyrrolidinyl group, piperazinyl group, morpholyl group, phenazinyl group, phenothiazinyl group, and phenoxazinyl group,
and with the proviso that the above aromatic hydrocarbon group and the heterocyclic group forming the multiple linking group for L2 are mutually the same or different and adjacent ones thereof are not bonded to further form a ring;
n and m are each independently an integer of 1 to 5;
when n is an integer of 2 to 5, a plurality of Cz are mutually the same or different;
when m is an integer of 2 to 5, Az are mutually the same or different;
Cz is represented by a formula (1a) below; and
Az is a group represented by a formula (11) below,
where: X1 to X8 are each independently CR or a nitrogen atom;R and R1 each independently represent a hydrogen atom, a halogen atom, a hydroxyl group, a cyano group, a substituted or unsubstituted alkyl group having 1 to 30 carbon atoms, a substituted or unsubstituted alkylsilyl group having 3 to 30 carbon atoms, a substituted or unsubstituted arylsilyl group having 6 to 60 ring carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 30 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 30 ring carbon atoms, a substituted or unsubstituted alkylamino group having 2 to 30 carbon atoms, a substituted or unsubstituted arylamino group having 6 to 60 ring carbon atoms, a substituted or unsubstituted alkylthio group having 1 to 30 carbon atoms, a substituted or unsubstituted arylthio group having 6 to 30 ring carbon atoms, a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, or a substituted or unsubstituted heterocyclic group having 5 to 30 ring atoms,
provided that the heterocyclic group having 5 to 30 ring atoms for R is selected from the group consisting of a pyridyl group, pyrimidinyl group, pyrazinyl group, pyridazynyl group, triazinyl group, quinolyl group, isoquinolinyl group, naphthyridinyl group, phthalazinyl group, quinoxalinyl group, quinazolinyl group, phenanthridinyl group, acridinyl group, phenanthrolinyl group, pyrrolyl group, imidazolyl group, pyrazolyl group, triazolyl group, tetrazolyl group, indolyl group, benzimidazolyl group, indazolyl group, imidazopyridinyl group, benzotriazolyl group, 9-carbazolyl group, furyl group, thienyl group, oxazolyl group, thiazolyl group, isoxazolyl group, isothiazolyl group, oxadiazolyl group, thiadiazolyl group, benzofuranyl group, benzothiophenyl group, benzoxazolyl group, benzothiazolyl group, benzisoxazolyl group, benzisothiazolyl group, benzoxadiazolyl group, benzothiadiazolyl group, dibenzofuranyl group, dibenzothiophenyl group, piperidinyl group, pyrrolidinyl group, piperazinyl group, morpholyl group, phenazinyl group, phenothiazinyl group, and phenoxazinyl group;
adjacent ones of R are mutually bonded to form a ring or are not bonded;
when a plurality of R are present, the plurality of R are the same or different;
one of R and R1 is a single bond to be bonded to L1 in the formula (1); and
R1 and adjacent R are mutually bonded to form a ring or are not bonded,
where: X9 is CR9 or a nitrogen atom;X10 is CR10 or a nitrogen atom;
R4 to R6, R9 and R10 each independently represent a hydrogen atom, a halogen atom, a hydroxyl group, a cyano group, a substituted or unsubstituted alkyl group having 1 to 30 carbon atoms, a substituted or unsubstituted alkylsilyl group having 3 to 30 carbon atoms, a substituted or unsubstituted arylsilyl group having 6 to 60 ring carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 30 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 30 ring carbon atoms, a substituted or unsubstituted alkylamino group having 2 to 30 carbon atoms, a substituted or unsubstituted arylamino group having 6 to 60 ring carbon atoms, a substituted or unsubstituted alkylthio group having 1 to 30 carbon atoms, or a substituted or unsubstituted arylthio group having 6 to 30 ring carbon atoms;
adjacent groups of R4 to R6, R9 and R10 are not bonded; and
one of R4 to R6, R9 and R10 is a single bond to be bonded to L2.

US Pat. No. 10,217,953

QUANTUM DOT LIGHT-EMITTING DEVICE, FABRICATING METHOD THEREOF, AND DISPLAY SUBSTRATE

BOE Technology Group Co.,...

1. A quantum dot light-emitting device, comprising:a base substrate; and
a first electrode layer, a light-emitting layer, a second electrode layer and an encapsulation layer which are sequentially formed on the base substrate,
wherein the light-emitting layer comprises a quantum dot light-emitting material;
a fluorescent material is disposed between the first electrode layer and the second electrode layer;
one of the first electrode layer and the second electrode layer is an anode layer, and the other of the first electrode layer and the second electrode layer is a cathode layer;
wherein the fluorescent material comprises a thermally activated delayed fluorescence material; and
at least a portion of a fluorescence emission spectrum of the thermally activated delayed fluorescence material overlaps an absorption spectrum of the quantum dot light-emitting material, and an overlap area accounts for not less than 30% of an area of the fluorescence emission spectrum of guest material.

US Pat. No. 10,217,952

NANO-SCALE TRANSISTOR

Tsinghua University, Bei...

19. A nano-scale transistor comprising:a source electrode, a drain electrode, a gate electrode, and a nano-heterostructure; the nano-heterostructure being electrically coupled with the source electrode and the drain electrode, the gate electrode being insulated from the nano-heterostructure, the source electrode and the drain electrode via an insulating layer; and, the nano-heterostructure comprises:
a first carbon nanotube oriented along a first direction;
a semiconductor layer with a thickness ranging from 1 nanometer to 200 nanometers, and the semiconductor layer comprising a first surface and a second surface opposite to the first surface;
a second carbon nanotube oriented along a second direction; and
wherein the first carbon nanotube is located on the first surface, the second carbon nanotube is located on the second surface, the semiconductor layer is sandwiched between the first carbon nanotube and the second carbon nanotube, and the first carbon nanotube and the second carbon nanotube are crossed with each other, the source electrode is electrically coupled with the first carbon nanotube, the drain electrode is electrically coupled with the second carbon nanotube.

US Pat. No. 10,217,951

HIGH MOBILITY POLYMER ORGANIC FIELD-EFFECT TRANSISTORS BY BLADE-COATING SEMICONDUCTOR:INSULATOR BLEND SOLUTIONS

THE REGENTS OF THE UNIVER...

1. An organic field effect transistor (OFET), comprising:a film comprising semiconducting polymers and insulating polymers, wherein:
a total weight (WIP) of the insulating polymers in the film is at least 50% of a total weight (WTOT) of the film,
a total weight of the semiconducting polymers in the film is at most 50% of the total weight of the film (WTOT), and
the semiconducting polymers each have a donor-acceptor copolymer backbone,
the film comprises a polymer blend of the semiconducting polymers and the insulating polymers,
the semiconducting polymers and the insulating polymers are phase separated in the film and form separate domains, and
the semiconducting polymers include a plurality of interconnected polymer chains;
a source contact and a drain contact to the semiconducting polymers;
a gate contact; and
a dielectric between the gate contact and the semiconducting polymers, wherein the dielectric is nearer to the semiconducting polymers than the insulating polymers.

US Pat. No. 10,217,950

STRETCHABLE FILMS, METHODS OF MANUFACTURING THE SAME AND DISPLAY DEVICES INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A stretchable film, comprising:a first region comprising a plurality of first stretchable patterns and a first boundary pattern that separates the plurality of first stretchable patterns from each other and surrounds the plurality of first stretchable pattern;
a second region comprising a plurality of second stretchable patterns and a second boundary pattern that separates the plurality of second stretchable patterns from each other and surrounds the plurality of second stretchable pattern; and
a buffer region between the first region and the second region,
wherein the plurality of first stretchable patterns comprise at least one of polydimethylsiloxane (PDMS) and photo-patternable silicon (PPS),
wherein the plurality of second stretchable patterns comprise at least one of polydimethylsiloxane (PDMS) and photo-patternable silicon (PPS), and
wherein the buffer region comprises first, second, third, and fourth buffer openings having different closed shapes from one another and that are sequentially arranged in a direction extending from the first region to the second region.

US Pat. No. 10,217,949

ORGANIC ELECTROLUMINESCENT MATERIALS CONTAINING CARBOLINE GROUP AND ORGANIC ELECTROLUMINESCENT DEVICE BY USING THE SAME

YUAN ZE UNIVERSITY, Chun...

3. An organic electroluminescent device, comprising:a first electrode layer;
a second electrode layer; and
an organic luminescent unit, disposed between the first electrode layer and the second electrode layer, wherein the organic luminescent unit has at least an organic luminescent material as shown in General Formula (1),

wherein R3 is an ?-carboline group, ?-carboline group or ?-carboline group, R13 is a carbazole group, R1 to R2, R4 to R12 and R14 to R20 are each independently selected from the group consisting of a hydrogen atom, a fluorine atom, a cyano group, an alkyl group, a cycloalkyl group, an alkoxy group, a haloalkyl group, a thioalkyl group, a silyl group and an alkenyl group, the ?-carboline group, ?-carboline group or ?-carboline group is attached to General Formula (1) by the nitrogen atom of the five-membered ring of the ?-carboline group, ?-carboline group or ?-carboline group, and the carbazole group is attached to General Formula (1) by the nitrogen atom of the five-membered ring of the carbazole group.

US Pat. No. 10,217,948

ORGANIC ELECTROLUMINESCENCE DEVICE AND NOVEL COMPOUND

IDEMITSU KOSAN CO., LTD.,...

1. A compound represented by the following formula (I):
wherein in the formula (I),
one or more pairs of adjacent two or more of R1 to R4 and R10 to R13 may form a substituted or unsubstituted, saturated or unsaturated ring;
R1 to R4, R10 to R13 and R17 that do not form the substituted or unsubstituted, saturated or unsaturated ring are independently a hydrogen atom, a substituted or unsubstituted aryl group including 6 to 20 ring carbon atoms or a substituted or unsubstituted monovalent heterocyclic group including 5 to 20 ring atoms;
two R17s may be the same or different; and
RA, RB, RC and RD are independently a substituted or unsubstituted aryl group including 6 to 20 ring carbon atoms.

US Pat. No. 10,217,946

DIBENZOFURANS AND DIBENZOTHIOPHENES

IDEMITSU KOSAN CO., LTD.,...

7. An electronic device, comprising a compound according to claim 1.

US Pat. No. 10,217,945

COMPOUND, ORGANIC ELECTROLUMINESCENT ELEMENT MATERIAL USING SAME, ORGANIC ELECTROLUMINESCENT ELEMENT USING THIS MATERIAL, AND ELECTRONIC DEVICE

IDEMITSU KOSAN CO., LTD.,...

1. A compound represented by formula (1):wherein:A represents N;
one of R1 or R2 is represented by formula (b) and the other is selected from the group consisting of a hydrogen atom, an aryl group having 6 to 60 ring carbon atoms, and a heteroaryl group having 5 to 60 ring carbon atoms;
R3, R4, R6, R7, and R8 are hydrogen,
R5 is selected from the group consisting of a hydrogen atom, an aryl group having 6 to 60 ring carbon atoms, and a heteroaryl group having 5 to 60 ring carbon atoms
wherein:* represents a bonding site to the carbon atom in formula (1) to which R1 or R2 is bonded;
L5 represents a single bond, or an arylene group having 6 to 60 ring carbon atoms;
L5 may have a substituent selected from an alkyl group having 1 to 20 carbon atoms, a cycloalkyl group having 3 to 18 ring carbon atoms, an alkoxy group having 1 to 20 carbon atoms, a cycloalkoxy group having 3 to 20 ring carbon atoms, an aryloxy group having 6 to 18 ring carbon atoms, an amino group, a silyl group, a fluorine atom, a cyano group, an aryl group having 6 to 18 ring carbon atoms, and a heteroaryl group having 5 to 18 ring atoms;
Y1 and Y2 each represent a hydrogen atom, an aryl group having 6 to 60 ring carbon atoms, or a heteroaryl group having 5 to 60 ring carbon atoms;
a and b each represent an integer of 1 or 2, and when a or b is 2, groups Y1 or groups Y2 may be the same or different; and
adjacent groups Y1 and adjacent groups Y2 may be bonded to each other to form a saturated or unsaturated ring, respectively; and
groups selected from R1 to R8 which are bonded to adjacent carbon atoms may be bonded to each other to form a saturated or unsaturated ring structure.

US Pat. No. 10,217,944

COMPOUND FOR ORGANIC ELECTRONIC ELEMENT, ORGANIC ELECTRONIC ELEMENT USING THE SAME, AND AN ELECTRONIC DEVICE THEREOF

DUK SAN NEOLUX CO., LTD.,...

1. A compound of Formula 1:
wherein,
L is
wherein * indicates the position to which the nitrogen atom (N) of the amine group in Formula 1 is linked,Ar1 to Ar3 are each independently selected from the group consisting of a C6-C60 aryl group; a fluorenylene group; a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C1-C50 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C1-C30 alkoxy group; a C6-C30 aryloxy group; and combinations thereof,
a, b and m are each an integer of 0 to 4, and n is an integer of 0 to 3,
R1 to R4 are each independently selected from the group consisting of i) deuterium; tritium; halogen; a C6-C60 aryl group; a fluorenyl group; a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C1-C50 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C1-C30 alkoxy group; a C6-C30 aryloxy group; -L?-N(Ra)(Rb); and combinations thereof, or ii) at least one of any two adjacent groups may be linked to form a ring and the group(s) of R? to R4 not forming a ring are the same as defined in i) above,
L? is selected from the group consisting of a single bond; a C6-C60 arylene group; a fluorenylene group; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P,
Ra and Rb are each independently selected from the group consisting of a C6-C60 aryl group; a fluorenyl group; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P,
each of the above aryl group, fluorenyl group, heterocyclic group, fused ring group, alkyl group, alkenyl group, alkynyl group, alkoxy group, aryloxy group, arylene group and fluorenylene group may be substituted with one or more substituents selected from the group consisting of deuterium; halogen; a silane group; a siloxane group; a boron group; a germanium group; a cyano group; a nitro group; a C1-C20 alkylthio group; a C1-C20 alkoxy group; a C1-C20 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C6-C20 aryl group; a C6-C20 aryl group substituted with deuterium; a fluorenyl group; a C2-C20 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a C3-C20 cycloalkyl group; a C7-C20 arylalkyl group; and a C8-C20 arylalkenyl group.

US Pat. No. 10,217,943

ORGANIC ELECTROLUMINESCENCE DEVICE AND ANTHRACENE DERIVATIVE

IDEMITSU KOSAN CO., LTD.,...

1. An organic electroluminescence device which comprises:a cathode,
an anode and
an organic thin film layer disposed between the cathode and the anode,
wherein:
the organic thin film layer comprises at least one layer which comprises a light emitting layer;
the light emitting layer comprises a host and a dopant;
the host is at least one anthracene derivative of formula (2):

wherein:
Ar is an unsubstituted 1-naphthyl group or an unsubstituted 2-naphthyl group;
Ar? is an unsubstituted 1-naphthyl group or an unsubstituted 2-naphthyl group;
a is 0;
b is 0;
n is 1; and
the dopant is at least one arylamine compound of formula (B):

wherein:
Ar5 to Ar7 are each independently a substituted or unsubstituted aryl group having 5 to 40 nuclear carbon atoms; and
q is an integer of 1 to 4.

US Pat. No. 10,217,942

ORGANIC SEMICONDUCTOR ELEMENT, MANUFACTURING METHOD THEREOF, COMPOUND, COMPOSITION FOR FORMING ORGANIC SEMICONDUCTOR FILM, AND ORGANIC SEMICONDUCTOR FILM

FUJIFILM CORPORATION, To...

1. An organic semiconductor element comprising:an organic semiconductor layer containing an organic semiconductor having a repeating unit represented by Formula 1,

in Formula 1, X11 and X12 each independently represent any one of CH2, CR112, O, Se, and SiR112, R11's each independently represent a monovalent organic group, Y11 and Y12 each independently represent O, S, N—CN, or CQ2, Q represents CN, CF3, C(?O)R12, C(?O)OR12, or SO2R12, R12's each independently represent a monovalent organic group, a plurality of R12's may be bonded to each other to form a ring, Ar11, Ar12, and Ar13 each independently represent an aromatic hydrocarbon group, an aromatic heterocyclic group, a vinylene group, or an ethynylene group, m11 represents an integer of 0 to 2, m12 represents an integer of 0 to 4, m13 represents an integer of 0 to 2, and a sum of m11, m12, and m13 is 1 or greater.

US Pat. No. 10,217,941

METHOD FOR PRODUCING AN ORGANIC LIGHT-EMITTING DIODE AND ORGANIC LIGHT-EMITTING DIODE

OSRAM OLED GmbH, Regensb...

1. A method for producing an organic light-emitting diode, the method comprising:providing a substrate having a continuous application surface;
generating a plurality of adhesion regions on the application surface by a targeted application of an adhesive coating in places such that the adhesive coating is present only in the adhesion regions, wherein the adhesion regions are completely surrounded by the application surface and wherein the adhesive coating is a scattering layer that comprises an organic matrix material and scattering particles embedded therein;
applying metal nanowires over the entire surface of the application surface;
removing the metal nanowires outside of the adhesion regions by washing with a solvent so that remaining metal nanowires completely or partially form a translucent electrode of the organic light-emitting diode; and
applying an organic layer sequence onto the translucent electrode.

US Pat. No. 10,217,940

OPTOELECTRONIC DEVICE

OSRAM OLED GMBH, Regensb...

1. A method for producing an optoelectronic device, the method comprising:applying a light transmissive first electrode to a carrier;
printing an electrically conductive track, which comprises a metal, on a side of the first electrode which faces away from the carrier; and
applying a functional organic region, which comprises at least one active region, on a side of the first electrode and the electrically conductive track which faces away from the carrier,
wherein the electrically conductive track is in direct contact with the first electrode and the functional organic region;
wherein the electrically conductive track is formed by a metallic ink;
wherein the metallic ink comprises a dopant for the functional organic region; and
wherein the dopant is configured to deactivate another opposite-type dopant present in an adjacent functional organic region such that, in a boundary region between the electrically conductive track and the functional organic region, at least one area that is free from charge carriers or reduced in charge carriers is formed.

US Pat. No. 10,217,939

SUBSTRATE AND EVAPORATION DEVICE USED FOR MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY PANEL

WUHAN CHINA STAR OPTOELEC...

6. A substrate used for manufacturing an organic light emitting display panel, comprising:a base plate;
a plurality of layer formation areas spaced from one another on the base plate, wherein the layer formation areas are where an organic light emitting layer is formed;
a plurality of first spacers disposed on the base plate at a clearance region between the layer formation areas; and
a plurality of second spacers disposed on the base plate at outer peripheries of the layer formation areas, wherein each of the second spacers includes a photoresist material and a plurality of magnetic polymer microsphere.

US Pat. No. 10,217,938

HOLE TRANSPORT COMPOSITIONS AND RELATED DEVICES AND METHODS (I)

NISSAN CHEMICAL INDUSTRIE...

1. A composition comprising:at least one first compound and at least one second compound different from the first,
wherein the at least one first compound comprises a hole transporting core which is a fluorene core or a biphenyl core, wherein the hole transporting core is covalently bonded to a first arylamine group and also covalently bonded to a second arylamine group, and wherein the core is further covalently bonded to at least two solubilizing groups comprising at least four carbon atoms and selected from substituted or unsubstituted C4 to C30 alkyl or heteroalkyl groups, and wherein the solubilizing groups are optionally substituted with intractability groups;
wherein the at least one second compound comprises a hole transporting core which is a fluorene or a biphenyl core, wherein the hole transporting core is covalently bonded to a first arylamine group and also covalently bonded to a second arylamine group, wherein the second compound further comprises at least one intractability group which is bonded to the first arylamine group, or to the second arylamine group, or to both;
wherein the first and second compounds have molecular weight of about 5,000 g/mole or less.

US Pat. No. 10,217,937

ASYMMETRIC CORRELATED ELECTRON SWITCH OPERATION

ARM Ltd., Cambridge (GB)...

1. A correlated electron switch (CES) device comprising:first and second terminals; and
one or more contiguous layers of a correlated electron material (CEM) formed between the first and second terminals,
wherein the one or more contiguous layers of the CEM are capable of being placed in a conductive or low impedance state responsive to a first or second write operation, or an insulative or high impedance state responsive to a third or fourth write operation,
wherein the one or more contiguous layers of the CEM further comprises at least one layer of intrinsic CEM and one or more doped layers of CEM, and
wherein the first write operation is asymmetric with the second write operation.

US Pat. No. 10,217,936

APPARATUSES INCLUDING ELECTRODES HAVING A CONDUCTIVE BARRIER MATERIAL AND METHODS OF FORMING SAME

Micron Technology, Inc., ...

1. An apparatus, comprising:a memory array comprising:
a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
a first chalcogenide structure;
a second chalcogenide structure;
a first electrode portion coupled to the first chalcogenide structure;
a second electrode portion coupled to the second chalcogenide structure; and
an electrically conductive barrier material disposed between the first and second electrode portions;
a plurality of bit lines, each memory cell electrically coupled to a respective bit line of the plurality of bit lines; and
a plurality of word lines, each memory cell electrically coupled to a respective word line of the plurality of word lines.

US Pat. No. 10,217,935

CORRELATED ELECTRON DEVICE FORMED VIA CONVERSION OF CONDUCTIVE SUBSTRATE TO A CORRELATED ELECTRON REGION

ARM Ltd., Cambridge (GB)...

1. A method of constructing a device, comprising:forming a plurality of layers of a conductive substrate; and
forming a correlated electron material (CEM) film over the plurality of layers of the conductive substrate, wherein
the CEM film is formed by converting at least a portion of at least one layer of the conductive substrate of the plurality of layers of the conductive substrate to a material comprising an atomic concentration of at least 90.0% of a CEM.

US Pat. No. 10,217,934

METHOD FOR MANUFACTURING MAGNETIC MEMORY CELLS

Avalanche Technology, Inc...

1. A method for manufacturing a memory cell that includes a magnetic memory element electrically connected to a selection element comprising a two-terminal selector, the method comprising the steps of:depositing a selector film stack for the two-terminal selector on a substrate;
depositing a magnetic memory element film stack for the magnetic memory element on top of the selector film stack, the magnetic memory element film stack including a magnetic reference layer film and a magnetic free layer film with an insulating tunnel junction layer film interposed therebetween;
etching the magnetic memory element film stack with an etch mask formed thereon to remove at least a first portion of the insulating tunnel junction layer film not covered by the etch mask to form a magnetic memory element pillar that includes a second portion of the insulating tunnel junction layer film;
depositing a first conforming dielectric layer over the magnetic memory element pillar, including a sidewall thereof, and surrounding surface;
etching a portion of the first conforming dielectric layer covering the surrounding surface to form a first protective sleeve around at least the second portion of the insulating tunnel junction layer film of the magnetic memory element pillar; and
etching the selector film stack using the etch mask and the first protective sleeve as a composite mask to form a memory cell pillar.

US Pat. No. 10,217,933

METHOD FOR ETCHING MULTILAYER FILM

TOKYO ELECTRON LIMITED, ...

1. A method of etching a multilayer film of a processing target using a plasma processing apparatus,the processing target including an underlying layer, a lower magnetic layer provided on the underlying layer, an insulating layer provided on the lower magnetic layer, an upper magnetic layer provided on the insulating layer, and a mask provided on the upper magnetic layer,
the plasma processing apparatus including a processing container, a gas supply system that supplies a rare gas and a hydrogen-containing gas into the processing container, a high frequency power supply for plasma generation, and a support structure that supports the processing target, and
the method comprising:
sequentially etching the upper magnetic layer, the insulating layer, the lower magnetic layer and the underlying layer by plasma generated from the rare gas supplied into the processing container while modifying, by the hydrogen-containing gas, one of the upper magnetic layer, the insulating layer, the lower magnetic layer and the underlying layer that is being etched, and wherein the etching of the upper magnetic layer is terminated on a surface of the insulating layer, the etching of the insulating layer is terminated on a surface of the lower magnetic layer, and the etching of the lower magnetic layer is terminated on a surface of the underlying layer,
wherein each etching step generates a deposit formed on a surface of the processing target,
wherein after each step of etching the upper magnetic layer, the insulating layer, the lower magnetic layer, and the underlying layer, the sequentially etching comprises:
a step of rotating the support structure about a first axis passing horizontally through the support structure to tilt the support structure at a predetermined angle with respect to a second axis extending orthogonal to the first axis, while simultaneously rotating the processing target about the second axis such that ions of the rare gas intersect at an incident direction with the deposit formed on the surface of the processing target, thereby removing the deposit, and
wherein the step of removing the deposit, a pulse-modulated DC voltage as a bias voltage for ion attraction is applied to the support structure,
further comprising:
after the step of removing the deposit generated during the step of etching the upper magnetic layer and before the step of etching the insulating layer, transferring the processing target to a film forming apparatus and forming an insulating film on a surface of the processing target; and
after the step of forming the insulating film, etching a top surface of the mask and a top surface of the insulating layer in the plasma processing apparatus by plasma generated from one of a hydrofluorocarbon gas and a fluorocarbon gas.

US Pat. No. 10,217,932

ELECTRONIC DEVICE

SK hynix Inc., Icheon-si...

1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises:a free layer including a plurality of magnetic layers each having a variable magnetization direction;
a tunnel barrier layer formed over the free layer; and
a pinned layer formed over the tunnel barrier layer and having a pinned magnetization direction;
wherein the plurality of magnetic layers in the free layer includes a first magnetic layer in contact with the tunnel barrier layer and a second magnetic layer not in contact with the tunnel barrier layer and a sum of an exchange field between the first magnetic layer and the second magnetic layer and a stray field generated by the first magnetic layer is larger than or the same as a difference between a uniaxial anisotropy field of the second magnetic layer and a demagnetizing field due to a shape of the second magnetic layer.

US Pat. No. 10,217,931

MAGNETIC ELEMENT, SKYRMION MEMORY, SOLID-STATE ELECTRONIC DEVICE, DATA-STORAGE DEVICE, DATA PROCESSING AND COMMUNICATION DEVICE

RIKEN, Saitama (JP)

1. A magnetic element for generating a skyrmion, the magnetic element comprising a two-dimensional stacked film, whereinthe two-dimensional stacked film is at least one or more multiple layered films including a magnetic film and a non-magnetic film stacked on the magnetic film,
the magnetic film includes ferromagnetic insulating material or ferromagnetic metal material and the non-magnetic film includes non-magnetic insulating material or non-magnetic metal material having a large constant of a spin-orbit interaction, and
in the two-dimensional stacked film, the skyrmion appears by applying a magnetic field substantially perpendicular to a two-dimensional surface having a thin layer shape.

US Pat. No. 10,217,930

METHOD OF MANUFACTURE FOR SINGLE CRYSTAL ACOUSTIC RESONATOR DEVICES USING MICRO-VIAS

AKOUSTIS, INC., Huntersv...

1. A method for fabricating an acoustic resonator device, the method comprising:providing a piezoelectric substrate having a piezoelectric layer formed overlying a seed substrate and a substrate surface region as a top surface of the piezoelectric layer;
forming a topside metal electrode overlying a portion of the substrate surface region;
forming a topside micro-trench within a portion of the piezoelectric layer different from the portion where the topside metal electrode is formed that extends through the piezoelectric layer;
forming one or more bond pads overlying one or more portions of the piezoelectric layer different from the one or more portions where the topside metal electrode and the topside micro-trench are formed;
forming a topside metal overlying the piezoelectric layer and having a topside metal plug within the topside micro-trench and electrically coupled to at least one of the bond pads;
thinning the seed substrate to form a thinned seed substrate;
forming a first backside trench within the thinned seed substrate from a bottom surface of the thinned seed substrate and underlying the topside metal electrode;
forming a second backside trench within the thinned seed substrate from a bottom surface of the thinned seed substrate and underlying the topside micro-trench;
forming a backside metal electrode underlying one or more portions of the thinned seed substrate, within the first backside trench, and underlying the topside metal electrode; and
forming a backside metal plug underlying one or more portions of the thinned seed substrate, within the second backside trench, and underlying the topside micro-trench, the backside metal plug being electrically coupled to the topside metal plug and the backside metal electrode, wherein the topside micro-trench, the topside metal plug, the second backside trench, and the backside metal plug form a micro-via that extends through the piezoelectric substrate.

US Pat. No. 10,217,929

PIEZOELECTRIC FILM, PIEZOELECTRIC ELEMENT, AND LIQUID DISCHARGE APPARATUS

FUJIFILM Corporation, To...

1. A piezoelectric film comprising:a perovskite oxide which is represented by General Formula P,
A1+?B1-x-yNbxNiyOz  General Formula P
where A contains at least Pb, B contains at least Zr and Ti, and x and y respectively satisfy 0.1?x?0.3 and 0.2x?y?0.4x,
wherein, although standard values of ? and z are ?=0 and z=3, these values may deviate from the standard values in a range in which a perovskite structure is capable of being obtained.

US Pat. No. 10,217,928

CURVED PIEZOELECTRIC DEVICE

Korea Institute of Scienc...

1. A curved piezoelectric device, comprising:a curved substrate; and
a piezoelectric material provided on one surface or both surfaces of the curved substrate,
wherein when a stress is applied, a neutral plane in which a compressive stress and a tensile stress are balanced is located in the curved substrate,
wherein the location of the neutral plane is determined by y1 and y2 of Equation 1 below, and
wherein the location of the neutral plane is controllable by adjusting a thickness (d) and a Young's modulus (E) of each of the curved substrate and the piezoelectric material:

where y1 is a distance between a center line of the curved substrate and the neutral plane, y2 is a distance between a center line of the piezoelectric material and the neutral plane, d1 is a thickness of the curved substrate, d2 is a thickness of the piezoelectric material, E1 is a Young's modulus of the curved substrate, and E2 is a Young's modulus of the piezoelectric material, with the proviso that

US Pat. No. 10,217,927

METHOD FOR PRODUCING A MULTILAYER COMPONENT

EPCOS AG, Munich (DE)

1. A method for producing a fully active stack or a green precursor of the fully active stack, the method comprising:providing a sintered or unsintered stack having sides A, B, C and D running in each case in a stacking direction, the stack comprising a plurality of alternately successive ceramic dielectric layers and internal electrode layers, wherein the internal electrode layers are internal electrodes and are embodied in each case in a continuous fashion with respect to the sides A and C and are embodied in each case in a non-continuous fashion with respect to either the side B or the side D, such that one portion of the internal electrodes makes contact with the side B, but not with the side D, and another portion of the internal electrodes makes contact with the side D, but not with the side B;
combining and temporarily contacting the internal electrodes that make contact with one of the side B or the side D via an external contact with temporary isozones, such that the internal electrodes that make contact with the side B or the side D are selectively electrically drivable;
etching back at least one portion of the internal electrodes that make contact with the side B or the side D before electrochemically coating;
electrochemically coating the internal electrodes that make contact with the side B or the side D on the sides A and C beyond an etching depth, wherein the electrochemically coating is effected by a plating technology;
converting the electrochemical coating into an insulating oxide coating by electrochemical oxidation; and
singulating the stack to form the fully active stack or the green precursor of the fully active stack with the coated internal electrodes on sides A? and C?, wherein the sides A? and C? correspond to the sides A and C, respectively, after the stack is singulated.

US Pat. No. 10,217,926

METHOD FOR PRODUCING A MULTI-LAYER ELECTRODE SYSTEM

Robert Bosch GmbH, Stutt...

1. A method for producing a multi-layer electrode system, the method comprising:applying a multi-layer stack to an upper face of a carrier substrate, the carrier substrate having a recess in the upper face, at least one wall of the recess inclined with respect to a lower face of the carrier substrate, the lower face lying opposite to the upper face, the multi-layer stack including at least one first electrode layer, a second electrode layer and a piezoelectrical layer that is arranged between the at least one first electrode layer and the second electrode layer; and
covering at least the wall and a base of the recess with at least one section of the multi-layer stack in order to form the multi-layer electrode system, wherein:
applying the multi-layer stack includes:
applying the multi-layer stack to an edge region of the upper face of the carrier substrate, said edge region being adjacent to the recess; and
removing the multi-layer stack down to a level of the upper face of the carrier substrate in order to form a planar contacting surface area with the upper face in order to make electrical contact with the at least one first electrode layer and the second electrode layer.

US Pat. No. 10,217,925

METHOD FOR PRODUCING AN ELECTRONIC STRUCTURAL ELEMENT AS A STACK

CONTINENTAL AUTOMOTIVE GM...

1. An electronic structural element comprising:a plurality of first electrode layers;
a plurality of second electrode layers stacked alternately between individual layers of the plurality of first electrode layers;
a plurality of material layers, the material reacting to application of an electrical field, each material layer sandwiched alternately between a respective first electrode layer and a respective second electrode layer;
the first electrode layers, second electrode layers, and material layers forming a stack with at least two circumferential regions;
a first contacting structure and a second contacting structure, each applied to a respective stack circumferential region such that every first electrode layer is contacted electrically by the first contacting structure and every second electrode layer is contacted electrically by the second contacting structure;
wherein the first contacting structure directly contacts a first stack circumferential region including each of the plurality of first electrode layers radially projecting from the first stack circumferential region and thereby embedded in an electrically conductive manner into the first contacting structure; and
wherein the second contacting structure is applied to a solvent-free insulating structure on a second stack circumferential region of the stack and connected electrically to each of the plurality of second electrode layers.

US Pat. No. 10,217,924

SYSTEM FOR RECAPTURING ENERGY LOST TO PLASMA OR IONIZATION HEATING

The Boeing Company, Chic...

1. A method for recapturing energy, comprising:thermally attaching a plurality of thermoelectric generator assemblies to an exterior surface of a nozzle of a thruster, wherein the nozzle is heated by plasma heating or ionization heating of propellant gases being discharged through the nozzle, each thermoelectric generator assembly comprising:
a first level thermoelectric generator module, the first level thermoelectric generator module comprising a hot side thermally attached to the exterior surface of the nozzle, a cold side opposite to the hot side and a plurality of thermoelectric generator devices disposed between the hot side and the cold side, the plurality of thermoelectric generator devices generates an electric current based on a temperature differential across each of the plurality of thermoelectric generator devices;
a second level thermoelectric generator module stacked on the first level thermoelectric generator module, the second level thermoelectric generator module comprising a hot side thermally attached to the cold side of the first level thermoelectric generator module, a cold side opposite to the hot side and a plurality of thermoelectric generator devices disposed between the hot side and the cold side, the plurality of thermoelectric generator devices generates an electric current based on a temperature differential across each of the plurality of thermoelectric generator devices, wherein the hot side and the cold side of the first level thermoelectric generator module and the second level thermoelectric generator module are each a continuous sheet of material, and the first level thermoelectric generator module and the second level thermoelectric generator module are arranged in a stacked configuration using a pyramid geometry for increased temperature differential across each of the thermoelectric generator modules, an area of the hot side and the cold side of the second level thermoelectric generator module being smaller than an area of the hot side and cold side of the first level thermoelectric generator module and wherein the first level thermoelectric generator module and the second level thermoelectric generator module each comprise a radial radius of curvature and an axial radius of curvature to match a contour of the exterior surface; and
an electrical wiring system comprising electrical conductors that electrically connect the second level thermoelectric generator module to the first level thermoelectric generator module in series;
capturing heat from the nozzle by the plurality of thermoelectric generator assemblies; and
converting the captured heat by the plurality of thermoelectric generator assemblies into electrical power.

US Pat. No. 10,217,923

METHOD FOR THE PRODUCTION OF A THERMOELECTRIC MODULE

MAHLE INTERNATIONAL GMBH,...

1. A thermoelectric module having the following features:a metallic housing element, wherein the metallic housing element has a mechanically roughened surface;
a ceramic layer which is applied by spraying on the metallic housing element, wherein the ceramic layer mechanically interlocks with the roughened surface of the metallic housing element, wherein the ceramic layer has a rough surface opposite the metallic housing element;
an electrically conductive region directly applied to the ceramic layer;
at least one thermoelectrically active material directly arranged on the electrically conductive region; and
a further housing element which is arranged on a side of the metallic housing element having the ceramic layer, wherein the further housing element and the metallic housing element are connected to form a fluid-tight housing,
wherein the at least one thermoelectrically active material is arranged in the fluid-tight housing, wherein a coefficient of thermal expansion of the ceramic layer and a coefficient of thermal expansion of the electrically conductive region are each within 20% of a coefficient of thermal expansion of the metallic housing element.

US Pat. No. 10,217,922

METHODS FOR THICK FILM THERMOELECTRIC DEVICE FABRICATION

BERKEN ENERGY LLC, Lovel...

1. A process for producing a thick film precursor composition with a free volume microstructure, the process comprising the steps of:(a) forming a powder comprising of one or more elements, alloys, or compounds;
(b) combining the powder with a vehicle and a thinning agent to form a paste;
(c) depositing the paste to form a layer on a surface;
(d) drying the layer to remove the thinning agent; and
(e) at least partially sintering the layer, wherein most of the vehicle is volatized leaving the free volume within the layer, andwherein the powder becomes an interconnected microstructure with the free-volume within the layer.

US Pat. No. 10,217,921

DISPLAY APPARATUS

SAMSUNG ELECTRONICS CO., ...

1. A display apparatus comprising:a display panel;
a chassis configured to support the display panel;
a backlight unit configured to emit light to the display panel; and
an electric generator configured to convert heat generated by the backlight unit to electricity, the electric generator comprising:
at least one thermoelectric device;
at least one heat storage unit; and
a heat transfer unit comprising:
a first surface in direct contact with the backlight unit to exchange heat therebetween; and
a second surface in direct contact with the at least one heat storage unit and the at least one thermoelectric device to exchange heat therebetween.

US Pat. No. 10,217,920

BURIED SENSOR SYSTEM

RAYTHEON BBN TECHNOLOGIES...

1. A system for underground sensing, comprising:a sensor;
a first thermal contact surface for making contact with soil;
a second thermal contact surface for making contact with soil;
a thermoelectric generator having:
a first heat exchange surface;
a second heat exchange surface;
a first electrical contact; and
a second electrical contact;
a first thermally conductive member connecting the first thermal contact surface to the first heat exchange surface;
a second thermally conductive member connecting the second thermal contact surface to the second heat exchange surface; and
a processing unit, the system having the shape of a rod having a length greater than a diameter of the rod,
a part of the first heat exchange surface being neither parallel to nor perpendicular to the length direction of the system,
the thermoelectric generator being configured to provide electrical power at the first electrical contact and the second electrical contact in response to a difference between a temperature at the first heat exchange surface and the second heat exchange surface, and
the processing unit being configured to receive electrical power produced by the thermoelectric generator,
the system being installed entirely underground, with the first thermal contact surface in contact with soil at a first depth, and the second thermal contact surface in contact with soil at a second depth, the second depth differing from the first depth by at least 48 inches.

US Pat. No. 10,217,919

LED MODULE

Air Motion Systems, Inc.,...

1. A light emitting diode (LED) module, comprising:a base portion including a first side that extends between a first end and a longitudinally opposing second end;
a first reflector portion secured to the first side of the base portion and extending between the first and second ends of the base portion;
a second reflector portion secured to the first side of the base portion and extending between the first and second ends of the base portion; and
an LED package disposed along the first side of the base portion,
wherein a first gap is defined between the first reflector portion and the first side of the base portion,
wherein a second gap is defined between the second reflector portion and the first side of the base portion,
wherein the LED package is partially disposed in each of the first and second gaps, and
wherein the first and second reflector portions facilitate an electrical connection and establish a thermal connection with the LED package.

US Pat. No. 10,217,918

LIGHT-EMITTING ELEMENT PACKAGE

LG INNOTEK CO., LTD., Se...

1. A light emitting element package comprising:a substrate;
a conductive layer disposed on the substrate;
at least one light emitting chip disposed on the substrate;
a wavelength conversion unit disposed on an upper surface of the at least one light emitting chip and having a through hole;
a wire provided with a first end passing through the through hole and connected to the at least one light emitting chip and a second end connected to the conductive layer; and
a molding part disposed on the substrate so as to enclose the at least one light emitting chip and the wire and to expose an upper surface of the wavelength conversion unit,
wherein the wavelength conversion unit is spaced apart from the first end of the wire connected to the at least one light emitting chip, and
wherein the through hole has an opening opened to a side surface of the wavelength conversion unit,
wherein the molding part fills an inside of the through hole of the wavelength conversion unit,
wherein the molding part seals a first portion of the wire from the first end of the wire to a highest point of the wire,
wherein the first portion of the wire is disposed in the opening of the through hole, and the first portion of the wire sealed by molding part is located at a lower position than the upper surface of the wavelength conversion unit and an upper surface of the molding part, and
wherein a distance from the upper surface of the at least one light emitting chip to the upper surface of the wavelength conversion unit is greater than a value acquired by adding 37 ?m to a distance from the upper surface of the at least one light emitting chip to the highest point of the wire.

US Pat. No. 10,217,917

NANOSTRUCTURED LED

GLO AB, Lund (SE)

1. A flip-chip light emitting diode (LED) device comprising:a carrier wafer including a first conductive pad and second conductive pads on a top surface thereof:
a buffer layer located over the carrier wafer and having a first surface that faces the top surface of the carrier wafer;
multiple light emitting diodes (LEDs) located on areas of the first surface of the buffer layer and protruding downward toward the carrier wafer;
light-reflecting or transparent contact layers located on a bottom side of a respective one of the multiple LEDs, wherein each of the LEDs includes a respective pn or p-i-n junction of which a first terminal is electrically connected to the buffer layer and of which a second terminal is electrically connected to a respective one of the light-reflecting or transparent contact layers;
a group of contact pads located on a bottom surface of a respective one of the light-reflecting or transparent contact layers; and
soldering bumps bonded to a respective one of the second conductive pads and to a respective one of the group of contact pads,
wherein the buffer layer is electrically connected to the first conductive pad on the top surface of the carrier wafer through a conductive material.

US Pat. No. 10,217,916

TRANSPARENT LIGHT EMITTING DIODES

THE REGENTS OF THE UNIVER...

1. A light emitting device, comprising:a lead frame having a transparent plate therein; and
a light emitting diode (LED) chip, mounted on the lead frame and placed on or above the transparent plate in the lead frame, emitting light through at least front and back sides of the LED chip;
wherein the transparent plate in the lead frame allows the light emitted from the LED chip to be extracted out of the LED chip from the front or back sides of the LED chip and through the transparent plate in the lead frame.

US Pat. No. 10,217,915

OPTOELECTRONIC SEMICONDUCTOR COMPONENT

OSRAM Opto Semiconductors...

1. An optoelectronic semiconductor device comprisinga carrier having a carrier top side,
at least one optoelectronic semiconductor chip arranged at the carrier top side and having a radiation main side remote from the carrier top side,
at least one bonding wire via which electrical contact is made with the semiconductor chip,
at least one covering body on the radiation main side that projects beyond the bonding wire in a direction away from the carrier top side and traverse or perpendicularly to the radiation main side, and
at least one reflective potting compound surrounding the semiconductor chip in a lateral direction and extending from the carrier top side at least as far as the radiation main side, wherein
the bonding wire is completely covered by the reflective potting compound or completely covered by the reflective potting compound and the covering body,
the bonding wire is fixed to the semiconductor chip in an electrical connection region on the radiation main side, and
the electrical connection region is free of the covering body and covered partly or completely by the reflective potting compound.

US Pat. No. 10,217,914

SEMICONDUCTOR LIGHT EMITTING DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor light emitting device comprising:a light emitting structure comprising a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer respectively providing a first surface and a second surface, opposite to each other, of the light emitting structure, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, and a plurality of regions of the first conductivity-type semiconductor layer being open by a plurality of holes penetrating through the second conductivity-type semiconductor layer and the active layer;
a first electrode disposed on the plurality of regions of the first conductivity-type semiconductor layer;
a second electrode disposed on a region of the second conductivity-type semiconductor layer;
an insulating layer disposed on the second surface of the light emitting structure;
a first solder pad and a second solder pad connected to the first electrode and the second electrode, respectively;
a transparent support substrate disposed on the first surface of the light emitting structure; and
a transparent adhesive layer disposed between the first surface of the light emitting structure and the transparent support substrate,
wherein at least one of the transparent support substrate and the transparent adhesive layer comprises a wavelength conversion material converting at least a portion of light having a first wavelength and generated by the active layer into light having a second wavelength, and
wherein the first surface of the light emitting structure, which is a surface of the first conductive-type semiconductor layer, comprises a concavo-convex portion,
wherein the first electrode has an extension portion extending onto the insulating layer, and the insulating layer, the extension portion of the first electrode, the first solder pad are sequentially stacked on a portion of the second electrode.

US Pat. No. 10,217,913

METHOD FOR PRODUCING OPTOELECTRONIC SEMICONDUCTOR DEVICES AND OPTOELECTRONIC SEMICONDUCTOR DEVICE

OSRAM OPTO SEMICONDUCTORS...

1. A method for producing a plurality of optoelectronic semiconductor devices, comprising the steps of:a) providing a plurality of semiconductor chips, which are spaced from one another in a lateral direction;
b) forming a package body assembly, which is arranged at least in part between the semiconductor chips;
c) forming a plurality of fillets, which each adjoin a semiconductor chip and which are delimited in the lateral direction by a side face of the respective semiconductor chip and the package body assembly; and
d) singulating the package body assembly into a plurality of optoelectronic semiconductor devices, wherein each semiconductor device comprises at least one semiconductor chip and a part of the package body assembly as its package body and wherein the semiconductor chips are each free of package body material on a radiation exit face of the semiconductor device opposite a mounting surface,
wherein to form the fillets the semiconductor chips are encapsulated prior to step b) with an auxiliary material in such a way that the side faces of the semiconductor chips are at least partly covered and the auxiliary material is encapsulated in step b) by a molding composition for the package body assembly,
wherein the auxiliary material is applied to an auxiliary carrier and the semiconductor chips are pressed into the auxiliary material such that the auxiliary material covers the side faces of the semiconductor chips at least in part, and
wherein the semiconductor chips extend right through the package bodies body.

US Pat. No. 10,217,912

LIGHT EMITTING DIODE MODULE FOR SURFACE MOUNT TECHNOLOGY AND METHOD OF MANUFACTURING THE SAME

SEOUL VIOSYS CO., LTD., ...

1. A light emitting diode (LED) comprising:a substrate;
a stacked structure including a first semiconductor layer, an active layer formed over the first semiconductor layer and a second semiconductor layer formed over the active layer;
an insulation layer formed over the stacked structure and shaped to expose selective portions of the second semiconductor layer; and
a reflective layer formed over the stacked structure and contacting the second semiconductor layer through the exposed selective portions of the second semiconductor layer, the reflective layer electrically coupled to the second semiconductor layer.

US Pat. No. 10,217,911

MONOLITHIC IMAGE CHIP FOR NEAR-TO-EYE DISPLAY

GLO AB, Lund (SE)

1. A semiconductor structure including light emitting devices, comprising:a first light emitting device containing a first nanowire located on a substrate, wherein the first nanowire comprises a first active region, the first active region including a first lower active region having a first band gap and a first upper active region having a second band gap, wherein the first band gap is greater than the second band gap; and
a second light emitting device containing a second nanowire located on the substrate, wherein the second nanowire comprises a second active region having the first band gap and does not include, nor is in physical contact with, any material having the second band gap.

US Pat. No. 10,217,910

METHOD OF PRODUCING A LIGHT-EMITTING ARRANGEMENT

OSRAM Opto Semiconductors...

1. A method of producing a light-emitting arrangement, comprising:providing a carrier comprising a top side,
attaching a multitude of first conversion elements on the top side of the carrier, wherein the first conversion elements are arranged in a lateral direction spaced apart from one another,
attaching an encapsulation on the top side of the carrier, wherein the encapsulation covers the carrier and the first conversion elements at least sectionally,
removing the encapsulation in regions between the first conversion elements, and
attaching optoelectronic semiconductor chips between the first conversion elements.

US Pat. No. 10,217,909

OPTOELECTRONIC SEMICONDUCTOR COMPONENT

OSRAM Opto Semiconductors...

1. An optoelectronic semiconductor component comprising:at least one optoelectronic semiconductor chip for generating primary radiation in a near-ultraviolet or in a visible spectral range;
at least one phosphor for partial or complete conversion of the primary radiation into a longer-waved secondary radiation that is in the visible spectral range; and
at least one filter substance for partial absorption of the longer-waved secondary radiation,
wherein the phosphor and the filter substance are closely connected to the at least one optoelectronic semiconductor chip,
wherein the filter substance is permeable to the primary radiation and does not or not significantly absorb the primary radiation,
wherein the filter substance spectrally absorbs in a narrow-band type manner in a wavelength range greater than at least 530 nm with a spectral full width at half maximum of at most 20 nm,
wherein the phosphor and the filter substance are randomly mixed through with one another so that no phase separation between the phosphor and the filter substance is present and the phosphor and the filter substance each are present in a homogenously distributed manner, and
wherein a color rendering index and a feeling of contrast index of a mixed radiation, comprising the primary radiation and the longer-waved secondary radiation emitted by the optoelectronic semiconductor component, are increased by the filter substance.

US Pat. No. 10,217,908

SEMICONDUCTOR NANOPARTICLE-BASED LIGHT EMITTING MATERIALS

Nanoco Technologies Ltd.,...

1. A light emitting device comprising:a light emitting diode;
a light diffuser in spaced-apart relation to the light-emitting diode and having a first surface oriented towards the light emitting diode and an opposing second surface oriented away from the light emitting diode; and
a light emitting layer in direct contact with the opposing second surface of the light diffuser and in optical communication with the light diffuser, said light emitting layer comprising a plurality of light emitting particles embedded within a host matrix material, each of said light emitting particles comprising a population of semiconductor nanoparticles embedded within a polymeric encapsulation medium,
wherein the polymeric encapsulation medium comprises a first polymer and the host matrix material comprises a second polymer and the first and second polymers are formed from a reverse emulsion so as to form microbeads encompassing the semiconductor nanoparticles.

US Pat. No. 10,217,907

METHOD OF PRODUCING NITRIDE FLUORESCENT MATERIAL, NITRIDE FLUORESCENT MATERIAL, AND LIGHT EMITTING DEVICE USING THE SAME

NICHIA CORPORATION, Anan...

1. A method of producing a nitride fluorescent material having a composition containing: at least one element selected from the group consisting of Ca, Sr, Ba, and Mg; at least one element selected from the group consisting of Li, Na, and K; at least one element selected from the group consisting of Eu, Ce, Tb, and Mn; Al; and N, the method comprising:preparing a calcined product having the composition; and
bringing the calcined product in contact with fluorine gas and heat-treating the calcined product at a temperature in a range of 200° C. or more and 350° C. or less in an atmosphere containing fluorine gas in a range of 2% by volume to 20% by volume and nitrogen gas of 80% by volume or more.

US Pat. No. 10,217,906

LIGHT-EMITTING DEVICE

EPISTAR CORPORATION, Hsi...

1. A light-emitting device, comprising:a semiconductor structure comprising a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer;
a surrounding part surrounding the semiconductor structure and exposing a surface of the first semiconductor layer;
a first insulating structure formed on the semiconductor structure, including a plurality of protrusions covering portions of the surface of the first semiconductor layer and a plurality of recesses exposing other portions of the surface of the first semiconductor layer;
a first contact portion formed on the surrounding part and contacting the other portions of the surface of the first semiconductor layer by the plurality of recesses;
a first pad formed on the semiconductor structure; and
a second pad formed on the semiconductor structure.

US Pat. No. 10,217,905

LIGHT-EMITTING ELEMENT

LG INNOTEK CO., LTD., Se...

1. A light-emitting element comprising:a light-emitting structure including a first semiconductor layer a second semiconductor layer, an active layer disposed between the first semiconductor layer and the second semiconductor layer, and a plurality of recesses passing through the second semiconductor layer and the active layer and disposed up to a partial region of the first semiconductor layer;
a first insulating layer disposed at a side surface and an upper surface of the plurality of recesses and having a plurality of holes disposed at the upper surface of the plurality of recesses;
a first conductive layer connected to the first semiconductor layer through the plurality of holes;
a second conductive layer electrically connected to the second semiconductor layer; and
an electrode pad spaced away from the light-emitting structure,
wherein the plurality of holes comprises a first hole which is closest to the electrode pad, a second hole which is farthest from the electrode pad, and a third hole disposed between the fist hole and the second hole,
wherein a diameter of the fist hole is smaller than a diameter of the second hole, and
wherein a diameter pf the third hole is larger than the diameter of the first hole and is smaller than the diameter of the second hole.

US Pat. No. 10,217,904

LIGHT-EMITTING DEVICE WITH METALLIZED MOUNTING SUPPORT STRUCTURE

EPISTAR CORPORATION, Hsi...

1. A light-emitting device with a first outermost sidewall and a second outermost sidewall, comprising:a light-emitting diode, having a side surface and a pad with a bottommost surface in a cross sectional view;
an insulation structure, in the cross sectional view, having an outermost surface and a portion which is directly formed on the bottommost surface; and
an electrode, formed on the portion in a configuration of being electrically connected to the pad, and having a segment, a first protrusion, and a second protrusion,
wherein the segment extends beyond the side surface in the cross sectional view,
wherein in a bottom view, the first protrusion and the second protrusion are formed integrally with the segment, and the first protrusion extended in a first direction from the segment to the first outermost sidewall, and the second protrusion is extended in a second direction from the segment to the second outermost sidewall, and
wherein the segment and the first protrusion are directly formed under the outermost surface.

US Pat. No. 10,217,903

OPTOELECTRONIC SEMICONDUCTOR CHIP AND OPTOELECTRONIC MODULE

OSRAM Opto Semiconductors...

1. An optoelectronic semiconductor chip comprising a carrier and a semiconductor body arranged on the carrier with a semiconductor layer sequence, whereinthe semiconductor layer sequence comprises an active region arranged between a first semiconductor layer and a second semiconductor layer and generates or receives electromagnetic radiation,
the first semiconductor layer connects to a first contact in an electrically-conductive manner,
the first contact is formed on a rear side of the carrier facing away from the semiconductor body,
the second semiconductor layer connects to both a second contact and a third contact in an electrically-conductive manner, and
the second contact is formed on the front side of the carrier facing towards the semiconductor body and the third contact on the rear side of the carrier facing away from the semiconductor body.

US Pat. No. 10,217,902

LIGHT EMITTING DEVICE AND LIGHTING APPARATUS INCLUDING THE SAME

LG INNOTEK CO., LTD., Se...

1. A light-emitting device, comprising:a substrate;
first and second electrode pads;
first to M-th light-emitting cells disposed on the substrate and arranged in a line in a first direction between the first and second electrode pads (M being a positive integer that is equal to or greater than 2); and
first to N-th connection wires for electrically connecting the first to M-th light-emitting cells (N being a positive integer satisfying 1?N?M?1),
wherein each of the first to M-th light-emitting cells comprises a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, which are sequentially disposed on the substrate,
wherein the first electrode pad is connected to the second conductive semiconductor layer of the first light-emitting cell while the second electrode pad is connected to the first conductive semiconductor layer of the M-th light-emitting cell,
wherein an n-th (n being a positive integer satisfying 1?n?N) connection wire electrically connects the first conductive semiconductor layer of an n-th light-emitting cell to the second conductive semiconductor layer of an (n+1)-th light-emitting cell, which are adjacent to each other,
wherein the n-th connection wire comprises a plurality of connection metal layers disposed so as to be isolated from each other in a second direction, which is different from the first direction,
wherein the connection metal layers included in one selected from among the first to N-th connection wires and the connection metal layers of another selected from among the first to N-th connection wires are disposed so as to be staggered from each other in the first direction, and
wherein a number of connection metal layers included in each of the first to N-th connection wires gradually increases as approaching a center line crossing between the first light-emitting cell and the M-th light-emitting cell.

US Pat. No. 10,217,901

LIGHT EMITTING DEVICE WITH IMPROVED EXTRACTION EFFICIENCY

Lumileds LLC, San Jose, ...

1. A light emitting device comprising:a hexagonal oxide substrate; and
a III-nitride semiconductor structure adjacent the hexagonal oxide substrate, the III-nitride semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region, the hexagonal oxide substrate having an in-plane coefficient of thermal expansion (CTE) within 30% of a CTE of the III-nitride semiconductor structure, and the n-type region having a thickness between 0.5 ?m and 2.0 ?m.

US Pat. No. 10,217,900

LIGHT EMITTING DIODE STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:forming a buffer layer on a substrate, the buffer layer having at least a lattice mismatch with the substrate; and
relaxing the buffer layer by pixelating the buffer layer into discrete islands, prior to formation of a quantum well,
wherein the buffer layer is a metastable buffer layer of AlN/GaN.

US Pat. No. 10,217,899

LIGHT EMITTING DIODE WITH REFLECTIVE PART FOR UVA AND BLUE WAVELENGTHS

Lumens Co., Ltd., Yongin...

1. A light emitting diode comprising:a first conductivity type semiconductor layer having a front side and a back side;
a second conductivity type semiconductor layer having a front side and a back side;
an active layer formed between the back side of the first conductivity type semiconductor layer and the front side of the second conductivity type semiconductor layer;
a first reflective layer formed on the back side of the second conductivity type semiconductor layer; and
a reflective part formed on the back side of the first reflective layer opposite the second conductivity type semiconductor layer to reflect light of a short wavelength (UVA wavelength) band and light of a blue wavelength,
wherein the first reflective layer comprises distributed Bragg reflector (DBR) unit layers for reflecting light of a short wavelength band of 315 nm to 420 nm, each of the DBR unit layers comprises a low refractive index layer and a high refractive index layer adjacent to the low refractive index layer,
wherein the reflective part comprises a second conductivity type intermediate layer for improving ohmic contact and a reflective metal layer for reflecting light of a short wavelength band and light of a blue wavelength band.

US Pat. No. 10,217,898

SEMICONDUCTOR DEVICE HAVING AN INTERNAL-FIELD-GUARDED ACTIVE REGION

1. A semiconductor device, comprising a layer sequence formed by a plurality of polar single crystalline semiconductor material layers that each have a crystal axis pointing in a direction that coincides with a direction of crystalline polarity and with a stacking direction of the layer sequence; whereinthe layer sequence is formed by a core layer sequence and shell layer sequences on opposite sides of the core layer sequence in the stacking direction; and wherein the core layer sequence is formed by
an active region made of an active layer stack or a plurality of repetitions of the active layer stack, the active layer stack being formed by an active layer having a first material composition that is associated with a first band gap energy, and by carrier-confinement layers embedding the active layer on at least two opposite sides thereof and having a second material composition that is associated with a second band gap energy larger than the first band gap energy, wherein the active layer and the carrier-confinement layers are configured to effect a quantum-confinement of charge carriers in the active layer in one, two or three spatial dimensions; and
a pair of polarization guard layers adjacent to the active region and embedding the active region on opposite sides thereof, both polarization guard layers having the first material composition.

US Pat. No. 10,217,897

ALUMINUM NITRIDE-ALUMINUM OXIDE LAYERS FOR ENHANCING THE EFFICIENCY OF GROUP III-NITRIDE LIGHT-EMITTING DEVICES

Wisconsin Alumni Research...

1. A light-emitting device comprising:a hole injection layer comprising a single-crystalline p-type doped Group III-nitride semiconductor;
an electron injection layer comprising a single-crystalline n-type doped Group III-nitride semiconductor;
a light-emitting active region comprising intrinsic or n-type doped Group III-nitride semiconductor layers disposed between the hole injection layer and the electron injection layer, the light-emitting active region comprising a multiple quantum well structure comprising alternating barrier layers and quantum well layers;
a layer of aluminum nitride on the hole injection layer; and
a layer of aluminum oxide on the layer of aluminum nitride, wherein the hole injection layer is disposed between the layer of aluminum nitride and the light-emitting active region and the layer of aluminum nitride is disposed between the layer aluminum oxide and the hole injection layer.

US Pat. No. 10,217,896

LIGHT EMITTING DIODE CHIP HAVING TEMPERATURE COMPENSATION OF THE WAVELENGTH

OSRAM Opto Semiconductors...

1. An optoelectronic semiconductor chip comprising:a p-type semiconductor region;
an n-type semiconductor region;
an active layer arranged between the p-type semiconductor region and the n-type semiconductor region, wherein the active layer is embodied as a multiple quantum well structure, the multiple quantum well structure comprising:
a first region containing alternating first quantum well layers and first barrier layers; and
a second region containing at least one second quantum well layer and at least one second barrier layer,
wherein the at least one second quantum well layer has an electronic bandgap EQW2 which is smaller than an electronic bandgap EQW1 of the first quantum well layers,
wherein the at least one second barrier layer has an electronic bandgap EB2 which is larger than an electronic bandgap EB1 of the first barrier layers, and
wherein the second region is arranged closer to the p-type semiconductor region than is the first region.

US Pat. No. 10,217,895

METHOD OF FORMING A LIGHT-EMITTING DEVICE

EPISTAR CORPORATION, Hsi...

1. A method of forming a light-emitting device comprising:providing a growth substrate having a front side and a rear side;
forming a sacrificial layer on the front side of the growth substrate;
forming a protective structure on the sacrificial layer;
forming a light-emitting structure on the protective structure, wherein the light-emitting structure emits a first peak wavelength;
providing a carrier;
joining the carrier and the light-emitting structure; and
transforming the sacrificial layer by irradiating a laser beam from the rear side to separate the growth substrate from the light-emitting structure, wherein the laser beam emits a second peak wavelength, and wherein the protective structure reflects the second peak wavelength away from the light-emitting structure; wherein the protective structure comprises a first portion and a second portion, wherein the method further comprises removing the first portion, and forming an electrode on the second portion.

US Pat. No. 10,217,894

METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE

TOYODA GOSEI CO., LTD., ...

4. A method for producing a Group III nitride semiconductor light-emitting device, the method comprising:preparing a sapphire substrate;
forming an AlN buffer layer on the sapphire substrate; and
forming a Group III nitride semiconductor layer on the AlN buffer layer;
in the preparing a sapphire substrate, the sapphire substrate is prepared, of which a main surface has a c-plane base surface and a plurality of projections protruding from the base surface, and an area ratio of the base surface to the main surface is 8% to 32%;
in the forming an AlN buffer layer, an AlN buffer layer having a thickness in a range of 57 nm to 37 nm is formed by sputtering, the thickness of the AlN buffer layer is decreased as the area ratio of the base surface to the main surface of the substrate is increased,
wherein the thickness of the AlN buffer layer exists within a range of ±6 nm with respect to a line connecting a first point where the thickness of the buffer layer is 41 nm when the area ratio of the base surface to the main surface of the substrate is 25% and a second point where the thickness of the buffer layer is 38 nm when the area ratio of the base surface to the main surface of the substrate is 31%; and
in the forming a Group III nitride semiconductor layer, an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer are formed in this order on the AlN buffer layer.

US Pat. No. 10,217,893

METHODS, APPARATUS, AND SYSTEMS FOR PASSIVATION OF SOLAR CELLS AND OTHER SEMICONDUCTOR DEVICES

SPECIAL MATERIALS RESEARC...

1. A method of facilitating fabrication of a passivated emitter and rear solar cell (PERC) via a room temperature wet chemical growth (RTWCG) process using a junction isolation and phosphosilicate glass (PSG)/borosilicate glass (BSG) etch solar cell processing tool, the method comprising:(A) placing a first RTWCG solution in a first reservoir coupled to a junction isolation process tank through a first chemical dosing unit of the processing tool;
(B) placing at least a portion of a semiconductor substrate for the PERC in the junction isolation process tank and allowing contact in the junction isolation process tank between the portion of the semiconductor substrate and the first RTWCG solution so as to facilitate growth of a back side oxide passivation layer on a back side of the semiconductor substrate and thereby provide a back side passivated substrate, wherein the first RTWCG solution in the junction isolation process tank is delivered from the first reservoir by the first chemical dosing unit;
(C) rinsing the back side passivated substrate in a first rinse tank of the processing tool using de-ionized (DI) water so as to provide a rinsed back side passivated substrate;
(D) placing a second RTWCG solution in a second reservoir coupled to a PSG/BSG etch tank through a second chemical dosing unit of the processing tool;
(E) placing the rinsed back side passivated substrate in the PSG/BSG etch tank and allowing contact in the PSG/BSG etch tank between the rinsed back side passivated substrate and the second RTWCG solution so as to facilitate growth of a front side oxide passivation layer having a thickness of less than 50 nm on a front side of the substrate and thereby provide a front and back side passivated substrate, wherein the second RTWCG solution in the PSG/BSG etch tank is delivered from the second reservoir by the second chemical dosing unit; and
(F) rinsing and drying the front and back side passivated substrate using a rinse and dry station coupled to the PSG/BSG etch tank.

US Pat. No. 10,217,892

TANDEM SOLAR CELL

EPISTAR CORPORATION, Hsi...

1. A method of manufacturing a solar cell device, comprising:providing a substrate comprising Ge or GaAs;
forming a first tunnel junction on the substrate, comprising:
forming a first n-type layer, and
forming a first p-type layer comprising a first material and a first element comprising In, Tl, Sb, Bi, Sn, Pb, Te, Po, Cd or Hg;
forming a first p-n junction on the first tunnel junction;
forming a second tunnel junction on the first p-n junction, comprising:
forming a second n-type layer comprising InGaP:Te; and
forming a second p-type layer, the second p-type layer comprising a second material AlxGa(1?x)As and a second element comprising In, Tl, Sb, Bi, Sn, Pb, Te, Po or Hg; and
forming a second p-n junction on the second tunnel junction,
wherein a concentration of the second element is 1˜2%.

US Pat. No. 10,217,890

INTEGRATED MEASURING SYSTEM FOR THE SPECTRAL MEASURING TECHNIQUE

1. A measuring system, comprising:a substrate with a quantum dot layer which is arranged on the substrate and which comprises an emission segment with a first multitude of quantum dots, and the first multitude has an average first energy gap, wherein the first multitude is configured to emit a radiation corresponding to the average first energy gap, wherein
the quantum dot layer comprises at least one separate and distinct absorption segment with a second multitude of quantum dots, the second multitude of quantum dots of the absorption segment laterally displaced from the first multitude of quantum dots of the emission segment within the same plane, in a plan view looking toward the substrate from above, and the second multitude has an average second energy gap which is smaller than the average first energy gap, so that radiation emitted by the emission segment toward a separate external object via a first side with respect to the substrate, after interaction with the external object, able to be received via the first side and absorbed by the laterally displaced absorption segment.

US Pat. No. 10,217,889

CLAMPED AVALANCHE PHOTODIODE

LadarSystems, Inc., Beav...

16. An avalanche photodiode device operating in Geiger-mode, the device comprising:An array of individual P-N junctions formed on a substrate with a first semiconductor region and a second semiconductor region with an anode and a cathode;
a respective third semiconductor region, for each of the individual P-N junctions, the third semiconductor region in physical contact with the second region, not in physical contact with the first region, and being the same semiconductor-type as the first semiconductor region; and
a respective clamp diode for each of the individual P-N junctions, wherein each of the clamp diodes are on each of the respective individual second semiconductors region and in electrical communication with the third semiconductor regions and each of the clamp diodes have a voltage drop than the P-N junction.

US Pat. No. 10,217,888

SOLUTION-PHASE INCLUSION OF SILVER INTO CHALCOGENIDE SEMICONDUCTOR INKS

International Business Ma...

1. A method of forming an ink, the method comprising:mixing a silver halide and a solvent to form a first solution;
mixing a metal, sulfur, and the solvent to form a second solution;
combining the first solution and the second solution to form a precursor solution; and
adding constituent components for an absorber material to the precursor solution to form the ink.

US Pat. No. 10,217,887

CRYSTALLINE SILICON-BASED SOLAR CELL, CRYSTALLINE-SILICON SOLAR CELL MODULE, AND MANUFACTURING METHODS THEREFOR

KANEKA CORPORATION, Osak...

1. A method for manufacturing a crystalline silicon-based solar cell, the crystalline silicon-based solar cell comprising:an n-type crystalline silicon substrate having a first principal surface, a second principal surface and a side surface; a first intrinsic silicon-based thin-film, a p-type silicon-based thin-film, a first transparent electrode layer and a patterned collecting electrode which are sequentially formed on the first principal surface of the n-type crystalline silicon substrate; and a second intrinsic silicon-based thin-film, an n-type silicon-based thin-film, a second transparent electrode layer and a plated metal electrode which are sequentially formed on the second principal surface of the n-type crystalline silicon substrate,
the method comprising:
a first intrinsic silicon-based thin-film forming step of depositing the first intrinsic silicon-based thin-film on an entire region of the first principal surface and the side surface of the n-type crystalline silicon substrate;
a p-type silicon-based thin-film forming step of depositing the p-type silicon-based thin-film on the first intrinsic silicon-based thin-film;
a first transparent electrode layer forming step of depositing the first transparent electrode layer on the entire region of the first principal surface except for a peripheral edge thereof;
a second intrinsic silicon-based thin-film forming step of depositing the second intrinsic silicon-based thin-film on an entire region of the second principal surface and the side surface of the n-type crystalline silicon substrate;
an n-type silicon-based thin-film forming step of depositing the n-type silicon-based thin-film on the second intrinsic silicon-based thin-film; and
a second transparent electrode layer forming step of depositing the second transparent electrode layer on the n-type silicon-based thin-film, wherein
a plated metal electrode forming step is further carried out after each of the above steps is carried out and in a state in which an insulating region is provided on the peripheral edge of the first principal surface, the insulating region being freed either of the first transparent electrode layer and the second transparent electrode layer, wherein
in the plated metal electrode forming step, the plated metal electrode is formed on an entire surface of the second transparent electrode layer by an electroplating method,
in the first transparent electrode layer forming step, deposition is performed under a state in which the peripheral edge of the first principal surface is covered with a mask, thereby the first transparent electrode layer is formed on the entire region of the first principal surface except for the peripheral edge thereof, and
in the second transparent electrode layer forming step, deposition is performed without using the mask, thereby the second transparent electrode layer is formed on the entire region of the second principal surface and the side surface.

US Pat. No. 10,217,886

PHOTOELECTRIC CONVERSION DEVICE

Samsung Electronics Co., ...

1. A photoelectric conversion device comprising:a first electrode including a light-receiving surface;
a second electrode spaced apart from the first electrode and facing the first electrode, the first electrode on the second electrode; and
an auxiliary layer between the second electrode and an exciton producing layer,
the exciton producing layer between the first electrode and the second electrode, and
the exciton producing layer being spaced apart from the second electrode by a distance (D) corresponding to one of a crest and a trough of a standing wave of light to be converted into electricity, the distance D being 70 nm wherein
the exciton producing layer is in direct contact with the first electrode,
the auxiliary layer is an n layer,
the n layer is a single layer of a n-type fullerene,
the exciton producing layer is in direct contact with the auxiliary layer,
the auxiliary layer is in direct contact with the second electrode.

US Pat. No. 10,217,885

INTERCONNECTOR AND SOLAR PANEL

KABUSHIKI KAISHA TOYOTA J...

1. An interconnector configured to electrically connect a first photovoltaic cell and a second photovoltaic cell, wherein the first photovoltaic cell and the second photovoltaic cell are adjacent to each other in a first direction, the first photovoltaic cell is located at a first side in the first direction, and the second photovoltaic cell is located at a second side in the first direction, the interconnector comprising:a first electrode configured to be connected to the first photovoltaic cell;
a second electrode configured to be connected to the second photovoltaic cell; and
a connection body that connects the first electrode and the second electrode, wherein
the connection body includes
a first detour connected to the first electrode and extended toward a first side in a second direction that is orthogonal to the first direction,
a second detour connected to the second electrode and extended toward the first side in the second direction, and
a joint extended in the first direction to connect the first detour and the second detour, and
the first detour includes a first curved part that is curved toward the first side in the first direction and connected to the first electrode at an angle that is greater than a right angle, wherein
the first detour includes a first body part linearly extending between the first curved part and the joint, and
the first curved part extends from an end of the first body part toward the second side in the first direction, so that a portion of the first curved part is closer to the second electrode in the first direction compared to the end of the first body part, and then extends toward the first side in the first direction before connecting to the first electrode.

US Pat. No. 10,217,884

PROCESS FOR PRODUCING A SOLAR CELL HAVING AN AROMATIC POLYIMIDE FILM SUBSTRATE FOR HIGH PHOTOELECTRIC CONVERSION EFFICIENCY

Ube Industries, Ltd., Ub...

1. A process for producing a CIS solar cell, comprising:reacting an aromatic tetracarboxylic acid component comprising 3,3?,4,4?-biphenyltetracarboxylic dianhydride as the main component and an aromatic diamine component comprising p-phenylenediamine as the main component in a solvent to provide a polyimide precursor solution;
flow-casting the obtained polyimide precursor solution on a support, and heating the solution to form a self-supporting film having a weight loss within a range of from 36% to 39%, this weight loss being calculated by the following formula (A):
Weight loss (%)=(W1?W2)/W1×100  (A)wherein W1 represents the weight of the self-supporting film, and W2 represents the weight of the polyimide film after curing, whereinthe highest temperature (T1) is equal to or lower than the temperature (TM) at which the self-supporting film is thermally deformed;heating the obtained self-supporting film to conduct the imidization reaction thereby producing a polyimide film, whereinthe self-supporting film is heated at a temperature lower than the heat deformation temperature (TM), and then the temperature is increased and the film is heated at the highest heat treatment temperature (T2) of from 495° C. to 540° C.;forming a metal layer on the surface of the polyimide film;
forming a thin film containing a Group IB element, a Group IIIB element and a Group VIB element on or over the metal layer; and
forming a chalcopyrite semiconductor layer by subjecting the thin film to heat treatment at a temperature equal to or higher than 450° C.

US Pat. No. 10,217,883

FUNCTIONAL YARN EQUIPPED WITH SEMICONDUCTOR FUNCTIONAL ELEMENTS

Sphelar Power Corporation...

1. A functional yarn equipped with semiconductor functional elements, comprising a plurality of semiconductor functional elements formed as granules and having positive and negative electrodes at their opposite ends, and a pair of flexible conducting wires to which the plurality of semiconductor functional elements are connected in parallel, the plurality of semiconductor functional elements being arranged so that their electrically conductive directions defined by their positive and negative electrodes are aligned between the pair of conducting wires arranged in a parallel state, and being formed as a cord in which, along with the positive electrodes of the plurality of semiconductor functional elements being electrically connected to one of the conducting wires via electrically conductive joining material, the negative electrodes of the plurality of semiconductor functional elements are electrically connected to the other of the conducting wires via electrically conductive joining material, and further comprising:each flexible conductive wire comprises a plurality of conductive wire portions between adjacent electrodes;
wherein at least one conductive wire portion is defined as a conductive wire region and a surface of the conductive wire region is covered by an insulating member; and
wherein a surface of at least one conductive wire portion is not covered by the insulating member.

US Pat. No. 10,217,882

QUANTUM ROD, SYNTHESIS METHOD OF THE SAME AND QUANTUM ROD DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. A quantum rod, comprising:a core; and
a shell having a first portion and a second portion, the first portion entirely covering the core and the second portion extending from opposite sides of the first portion along an axis of the core and the shell,
wherein, in a direction crossing the axis, a first thickness of the first portion is greater than a second thickness of the second portion, and in a direction of the axis, a first length of the first portion is smaller than a second length of the second portion, and
wherein the first thickness is about 2.5 to 4 times a thickness of the core, and the first length is about 3 to 6 times a length of the core.

US Pat. No. 10,217,881

METAL-CONTACT-FREE PHOTODETECTOR

Elenion Technologies, LLC...

1. An optical device, comprising:a substrate;
a device layer, including a waveguide, on a surface of the substrate;
a first doped semiconductor contact in the device layer; and
a second doped semiconductor contact in the device layer;
a first metal terminal, in electrical communication with said first doped semiconductor contact; and
a second metal terminal, in electrical communication with said second doped semiconductor contact;
wherein the first and second metal terminals are in electrical communication with external circuitry;
wherein the first doped semiconductor contact comprising a first portion underneath the waveguide, a second portion underneath the first metal terminal, and a connecting slab extending in the device layer between the first and second portions; and
wherein the second doped semiconductor contact comprising a first portion underneath the waveguide, a second portion underneath the second metal terminal, and a connecting slab extending in the device layer between the first and second portions.

US Pat. No. 10,217,880

VOLTAGE BREAKDOWN DEVICE FOR SOLAR CELLS

SunPower Corporation, Sa...

1. A solar cell, comprising:a semiconductor substrate;
a plurality of alternating N-type and P-type semiconductor regions disposed in or above the substrate;
a plurality of conductive contacts coupled to the plurality of alternating N-type and P-type semiconductor regions; and
a voltage breakdown device disposed above the substrate, the voltage breakdown device comprising one of the plurality of conductive contacts in electrical contact with one of the N-type semiconductor regions and with one of the P-type semiconductor regions of the plurality of alternating N-type and P-type semiconductor regions disposed in or above the substrate to form a P/N junction of the voltage breakdown device, wherein the semiconductor substrate is an N-type semiconductor substrate, the one of the plurality of conductive contacts is in direct contact with the one of the N-type semiconductor regions and is not in direct contact with the one of the P-type semiconductor regions of the plurality of alternating N-type and P-type semiconductor regions.

US Pat. No. 10,217,879

OPTICAL SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. An optical semiconductor device comprising:a semiconductor substrate having a first surface and a second surface facing the first surface;
an electrode formed over the first surface of the semiconductor substrate; an optical element that is electrically coupled to the electrode and is formed in the semiconductor substrate; and
a lens arranged on the second surface side of the optical element, wherein a concave part is formed in the second surface of the semiconductor substrate, and the lens is arranged at the bottom of the concave part,
wherein a top part on the second surface side of the lens is located on the first surface side relative to the second surface located around the concave part, and
wherein, in a cross-sectional view, the concave part has a smoothly curved surface extending from the lens to the second surface of the semiconductor substrate.

US Pat. No. 10,217,878

TRI-LAYER SEMICONDUCTOR STACKS FOR PATTERNING FEATURES ON SOLAR CELLS

SunPower Corporation, Sa...

1. A back contact solar cell, comprising:a substrate;
a semiconductor structure disposed above the substrate, the semiconductor structure comprising a P-type semiconductor layer disposed directly on a first semiconductor layer, and a third semiconductor layer disposed directly on the P-type semiconductor layer, wherein an outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width, and wherein an outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the first semiconductor layer to the outermost edge of the third semiconductor layer; and
a conductive contact structure electrically connected to the semiconductor structure, wherein the semiconductor structure is vertically stacked with the first semiconductor layer between the P-type semiconductor layer and the substrate, the P-type semiconductor layer between the first and third semiconductor layers, and the third semiconductor layer between the P-type semiconductor layer and the conductive contact structure;
wherein the first semiconductor layer is a first intrinsic silicon layer, the P-type semiconductor layer is a boron-doped silicon layer, and the third semiconductor layer is a second intrinsic silicon layer.

US Pat. No. 10,217,877

SOLAR CELL

LG ELECTRONICS INC., Seo...

1. A solar cell comprising:a semiconductor substrate;
a conductive area including first and second conductive areas disposed on one surface of the semiconductor substrate; and
an electrode including a first electrode connected to the first conductive area and a second electrode connected to the second conductive area,
wherein the electrode includes an adhesive layer disposed on the semiconductor substrate or the conductive area, an electrode layer disposed on the adhesive layer and including a metal as a main component, and a barrier layer disposed on the electrode layer and including a metal that is different from the metal of the electrode layer as a main component,
wherein the electrode layer has a thickness greater than a thickness of each of the adhesive layer and the barrier layer,
wherein the barrier layer has a higher melting point than a melting point of the electrode layer,
wherein the entire adhesive layer is disposed between the conductive area and the electrode layer, and
wherein a width of the electrode layer is different from a width of the adhesive layer.

US Pat. No. 10,217,876

POLY-SILOXANE CONTAINING ORGANIC VEHICLE FOR ELECTROCONDUCTIVE PASTES

HERAEUS PRECIOUS METALS N...

1. A passivated emitter rear solar cell, comprising:a silicon substrate having a front and back surface;
a rear passivation layer on the back surface of the silicon substrate having a plurality of open holes formed therein;
an aluminum back contact layer formed in the open holes of the rear passivation layer; and
at least one backside soldering tab on the back surface of the silicon substrate,
wherein the backside soldering tab is formed from an electroconductive paste composition comprising conductive metallic particles, at least one lead-free glass frit, an adhesion promoting additive comprising MnO2, and an organic vehicle comprising at least one silicone oil.

US Pat. No. 10,217,875

BROADBAND GRAPHENE-BASED OPTICAL LIMITER FOR THE PROTECTION OF BACKSIDE ILLUMINATED CMOS DETECTORS

RAYTHEON COMPANY, Waltha...

1. A method of fabricating a sacrificial limiter filter for an optical device, the method comprising:depositing a first layer of graphene onto a surface of a silicon substrate of the optical device, wherein the optical device is a backside-illuminated focal plane array (FPA) or a backside-illuminated charge coupled device (CCD) camera;
depositing a first nano-layer of dielectric material onto the first layer of graphene;
depositing a second layer of graphene onto the first nano-layer of dielectric material, the first layer of graphene, the first nano-layer of dielectric material, and the second layer of graphene forming a first dipole conductive structure;
depositing a third layer of graphene onto the second layer of graphene;
depositing a second nano-layer of dielectric material onto the third layer of graphene; and
depositing a fourth layer of graphene onto the second nano-layer of dielectric material, the third layer of graphene, the second nano-layer of dielectric material, and the fourth layer of graphene forming a second dipole conductive structure, wherein the first, second, third, and fourth layers of graphene are configured to absorb and scatter at least a portion of electromagnetic radiation incident on the optical device and transmit at least 70% of electromagnetic radiation in a spectral range between about two and about eight microns.

US Pat. No. 10,217,874

SEMICONDUCTOR DEVICE HAVING A TRANSPARENT WINDOW FOR PASSING RADIATION

MELEXIS TECHNOLOGIES NV, ...

1. A method of manufacturing a packaged semiconductor device with a transparent window, comprising the steps of:a) providing a semiconductor structure comprising an opto-electric element located in a cavity formed between a substrate and a cap layer, the cap layer being made of quartz glass, sapphire glass or silicon, and having a substantially flat upper surface;
b) forming at least one protrusion extending on top of the cap layer;
c) bringing the at least one protrusion on top of the cap layer in contact with a tool having a substantially flat surface region, and applying an opaque material to the semiconductor structure at a portion thereof which is not in contact with the tool;
d) removing the tool thereby providing a packaged optical semiconductor device having a transparent window.

US Pat. No. 10,217,873

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DIE WITH ACTIVE REGION RESPONSIVE TO EXTERNAL STIMULUS

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a first semiconductor die including an active surface comprising a light-sensitive sensor;
disposing a second semiconductor die adjacent to the first semiconductor die;
depositing an encapsulant over the first semiconductor die and second semiconductor die including a first surface of the encapsulant coplanar with the active surface of the first semiconductor die;
forming a first conductive layer over the encapsulant after depositing the encapsulant with a surface of the first conductive layer on the active surface of the first semiconductor die and the first surface of the encapsulant, wherein a first portion of the first conductive layer extends from the first semiconductor die to the second semiconductor die;
forming a transmissive layer over the first conductive layer and light-sensitive sensor;
forming an opening through the encapsulant to expose the surface of the first conductive layer; and
forming a solder bump in the opening on the surface of the first conductive layer, wherein the solder bump extends through the encapsulant to above a second surface of the encapsulant opposite the first conductive layer.

US Pat. No. 10,217,872

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

RENESAS ELECTRONICS CORPO...

1. A semiconductor device having a memory cell comprising:in a first region of a first conductive type semiconductor substrate,
a plurality of first projection units, which are a part of the semiconductor substrate, and extend in a first direction along a main surface of the semiconductor substrate;
a first gate electrode, which is formed over an upper surface and a sidewall of the first projection units through a first insulating film, and extends in a second direction orthogonal to the first direction along the main surface of the semiconductor substrate;
a second gate electrode, which is formed adjacent to one side surface of the first gate electrode, and extends in the second direction;
a second insulating film, which is formed between the first gate electrode and the second gate electrode and between the first projection units and the second gate electrode, and includes a charge accumulation film; and
first source/drain regions, which are of a second conductive type different from the first conductive type, and are formed in the first projection units at a position on a side of the first gate electrode that is opposite the second gate electrode in the first direction and in the first projection units at a position on a side of the second gate electrode that is opposite the first gate electrode in the first direction,
wherein the first gate electrode and the second gate electrode are formed from polycrystalline silicon, which is of the second conductive type,
wherein a first metal film is provided between the first insulating film and the first gate electrode, and a second metal film is provided between the second insulating film and the second gate electrode,
wherein a first work function of the first metal film and a second work function of the second metal film are different from each other,
wherein the first conductive type is p-type, and the second conductive type is n-type,
wherein the first work function is greater than the second work function,
wherein the first metal film and the second metal film are formed of titanium nitride, and
wherein a thickness of the first metal film is greater than a thickness of the second metal film.

US Pat. No. 10,217,871

METHOD OF CONTROLLING ELECTRIC CONDUCTIVITY OF METAL OXIDE THIN FILM AND THIN FILM TRANSISTOR INCLUDING THE METAL OXIDE FILM HAVING THE CONTROLLED ELECTRIC CONDUCTIVITY

Industry-Academic Coopera...

1. A method of improving an electric conductivity of a metal oxide thin film for a large area application, the method comprising:forming a metal oxide thin film which is insulative;
applying thermal treatment to the metal oxide thin film so that the metal oxide thin film has a poly-crystalline structure; and
after the thermal treatment, irradiating UV-rays to the metal oxide thin film having the poly-crystalline structure in an atmosphere containing water molecules and oxygen molecules, forming a metal-OH composite film on a surface of the metal oxide thin film,
wherein the metal oxide thin film having the metal-OH composite film is conductive or semiconductive.

US Pat. No. 10,217,870

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A manufacturing method of a semiconductor device, comprising the steps of:forming a first oxide layer over a first insulating layer containing oxygen;
forming an oxide semiconductor layer over the first oxide layer;
forming a source electrode layer and a drain electrode layer over and in contact with the oxide semiconductor layer;
forming a second oxide layer over the source electrode layer and the drain electrode layer by a sputtering method, the second oxide layer being in contact with the oxide semiconductor layer;
forming a gate insulating layer over the second oxide layer;
forming a gate electrode layer over the gate insulating layer; and
forming a second insulating layer over the gate electrode layer,
wherein the second insulating layer is in contact with the first insulating layer, a side surface of the second oxide layer and a side surface of the gate insulating layer,
wherein the oxide semiconductor layer includes one or more metal elements,
wherein the first oxide layer and the second oxide layer include at least one of the metal elements included in the oxide semiconductor layer, and
wherein the second insulating layer has lower permeability to oxygen than the second oxide layer and the gate insulating layer.

US Pat. No. 10,217,869

SEMICONDUCTOR STRUCTURE INCLUDING LOW-K SPACER MATERIAL

International Business Ma...

1. A method comprising:forming a dummy gate stack on a substrate including a sacrificial spacer on a peripheral of the dummy gate stack;
etching down the sacrificial spacer using an over etch process, wherein the over etch process comprises:
partially recessing the dummy gate stack;
etching the sacrificial spacer down to the partially recessed dummy gate stack; and
etching remaining portions of the sacrificial spacer to form a dummy gate cavity that includes gaps around and above the partially recessed dummy gate stack;
filling a portion of the gaps with low-k spacer material that extends vertically along a sidewall of the dummy gate cavity; and
etching the low-k spacer material on the sidewall of the dummy gate cavity and below the partially recessed dummy gate stack to form a first low-k spacer portion and a second low-k spacer portion disposed above the first low-k spacer portion, wherein the first low-k spacer portion has a corresponding width that is constant as the first low-k spacer portion extends vertically along the sidewall of the dummy gate cavity, and the second low-k spacer portion has a corresponding width that tapers towards the sidewall of the dummy gate cavity as the second low-k spacer portion extends vertically along the sidewall of the dummy gate cavity.

US Pat. No. 10,217,868

AIRGAP SPACERS

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, comprising:forming one or more semiconductor fins on a substrate;
forming a first dummy gate across the one or more semiconductor fins;
forming a second dummy gate over the first dummy gate, wherein a material of the first dummy gate is different from a material of the second dummy gate;
etching away the second dummy gate;
forming a lower spacer that defines a gate region after etching away the second dummy gate;
forming a sacrificial upper spacer directly above the lower spacer;
forming a gate stack in the gate region;
etching away the sacrificial upper spacer to form an upper spacer opening; and
forming an airgap spacer in the upper spacer opening that comprises a dielectric material that encapsulates an internal void.

US Pat. No. 10,217,867

UNIFORM FIN DIMENSIONS USING FIN CUT HARDMASK

International Business Ma...

1. A method for forming fins, comprising:patterning a fin cut mask over a fin etch mask to protect the fin etch mask in a fin region;
etching a substrate using the fin cut mask to form fin cut regions;
forming first dielectric fill material in the fin cut regions;
after forming the first dielectric fill material in the fin cut regions, exposing the fin etch mask by removing the fin cut mask; and
after exposing the fin etch mask, etching fins in the substrate using the fin etch mask.

US Pat. No. 10,217,866

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a first fin shaped structure and a second fin shaped structure disposed on a substrate;
a first isolation structure disposed on the substrate, surrounded the first fin shaped structure and the second fin shaped structure;
a second isolation structure disposed in the first fin shaped structure;
a third isolation structure disposed in the second fin shaped structure, wherein a top surface of the third isolation structure and a top surface of the second isolation structure are in different heights, and the top surface of the third isolation structure is lower than a top surface of the second fin shaped structure; and
a first gate and a second gate, disposed on the second isolation structure and the third isolation structure, respectively; and
a fourth isolation structure disposed between the first fin shaped structure and the second fin shaped structure.

US Pat. No. 10,217,865

SGT-INCLUDING PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

UNISANTIS ELECTRONICS SIN...

1. An SGT-including pillar-shaped semiconductor device comprising:at least one surrounding gate transistor (SGT) including a semiconductor pillar on a substrate so as to be perpendicular to a surface of the substrate;
a gate insulating layer surrounding an outer periphery of the semiconductor pillar;
a gate conductor layer surrounding the gate insulating layer;
a first impurity region within the semiconductor pillar and functioning as a source; and
a second impurity region within the semiconductor pillar and functioning as a drain;
a first wiring conductor layer and at least one second wiring conductor layer above the first wiring conductor layer that individually connect to any one of the gate conductor layer, the first impurity region, and the second impurity region of the at least one SGT, and extending in a horizontal direction along the surface of the substrate, and at least partially overlapping in plan view;
an interlayer insulating layer between the first wiring conductor layer and the at least one second wiring conductor layer;
a first tubular insulating film having a bottom surface in contact with the first wiring conductor layer, and a side surface in contact with the at least one second wiring conductor layer and the interlayer insulating layer; and
a first lead-out conductor layer filling the tubular insulating film and connected to the first wiring conductor layer.

US Pat. No. 10,217,864

DOUBLE GATE VERTICAL FINFET SEMICONDUCTOR STRUCTURE

GLOBALFOUNDRIES Inc., Gr...

1. A semiconductor structure comprising:a substrate;
a vertical FinFET disposed over the substrate, the vertical FinFET including:
a bottom source/drain (S/D) region disposed over the substrate,
a fin extending vertically upwards from the bottom S/D region, the fin having a first (1st) sidewall, a second (2nd) sidewall and a top portion,
an upper S/D region disposed over the top portion of the fin, the fin defining a channel between the bottom S/D region and the upper S/D region,
a 1st gate structure having a 1st metal gate, the 1st gate structure disposed on the 1st sidewall of the fin, and
a 2nd gate structure having a 2nd metal gate, the 2nd gate structure disposed on the 2nd sidewall of the fin; and
wherein the 1st and 2nd metal gates are electrically isolated from each other by the fin.

US Pat. No. 10,217,863

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH AN ASYMMETRIC GATE STRUCTURE

International Business Ma...

1. A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, comprising:forming one or more tubular vertical fins on a substrate;
forming a first bottom spacer on the substrate surrounding at least one of the one or more tubular vertical fins;
forming a first gate structure on the first bottom spacer and around an outer wall of the at least one of the one or more tubular vertical fins;
forming a second bottom spacer within the at least one of the one or more tubular vertical fins; and
forming a second gate structure on the second bottom spacer within an inner wall of the at least one of the one or more tubular vertical fins having the first gate structure around the outer wall.

US Pat. No. 10,217,862

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device including:a semiconductor substrate having a primary surface;
a first-conductive-type first semiconductor layer that is formed over the primary surface of the semiconductor substrate;
a second-conductive-type drain region that is formed in the first semiconductor layer;
a second-conductive-type source region that is formed in the first semiconductor layer at a distance away from the drain region;
an isolation insulating film having a first thickness that is formed at a part of the first semiconductor layer located between the drain region and the source region;
a second-conductive-type drift layer that is formed from the surface of the first semiconductor layer up to a position deeper than the bottom of the isolation insulating film so as to surround the isolation insulating film and the drain region from the lateral and lower sides;
a gate electrode that is formed over a region located between the isolation insulating film and the source region and including a part serving as a channel;
an interlayer insulating film that is formed so as to cover the gate electrode; and
a contact plug that is formed to reach the inside of the isolation insulating film while penetrating the interlayer insulating film,
wherein the contact plug includes a buried part that is formed from the surface of the isolation insulating film up to a depth corresponding to a second thickness thinner than the first thickness.

US Pat. No. 10,217,861

HIGH VOLTAGE INTEGRATED CIRCUIT WITH HIGH VOLTAGE JUNCTION TERMINATION REGION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising: a first semiconductor region of a second conductivity type selectively provided in a surface layer of a semiconductor substrate;a second semiconductor region of the second conductivity type and surrounding a periphery of the first semiconductor region;
a third semiconductor region of a first conductivity type provided to be in contact with the second semiconductor region and to surround and to be away from the first semiconductor region;
a fourth semiconductor region of the second conductivity type, selectively provided in the third semiconductor region;
a fifth semiconductor region of the second conductivity type, selectively provided in the first semiconductor region or the second semiconductor region to face the fourth semiconductor region with no intervening second conductivity type semiconductor regions formed apart from the fifth semiconductor region other than the semiconductor region in which the fifth semiconductor region is selectively provided, the fifth semiconductor region having an impurity concentration that is higher than that of the second semiconductor region;
a gate electrode provided through a gate insulating film, on a surface of a portion of the third semiconductor region between the fourth semiconductor region and the second semiconductor region;
a sixth semiconductor region of the second conductivity type, selectively provided in the first semiconductor region or the second semiconductor region to be away from the fifth semiconductor region, the sixth semiconductor region having an impurity concentration that is higher than that of the second semiconductor region;
a seventh semiconductor region of the first conductivity type, selectively provided in the first semiconductor region to be away from the fifth semiconductor region;
an interlayer insulating film that covers the second semiconductor region;
a first electrode electrically connected to the fifth semiconductor region, and extending on the interlayer insulating film;
a second electrode electrically connected to the sixth semiconductor region or the seventh semiconductor region, and extending on the interlayer insulating film; and
a third electrode electrically connected to the third semiconductor region and the fourth semiconductor region, and extending on the interlayer insulating film to face the first electrode and the second electrode,
wherein on the interlayer insulating film, an interval across which the first electrode faces a first portion of the third electrode facing the fourth semiconductor region in a depth direction is larger than an interval between the second electrode and the third electrode.

US Pat. No. 10,217,860

PARTIALLY BIASED ISOLATION IN SEMICONDUCTOR DEVICES

NXP USA, Inc., Austin, T...

1. A device comprising:a semiconductor substrate having a first conductivity type;
a body region disposed in the semiconductor substrate within the core device area, having the first conductivity type, and in which a channel is formed during operation;
a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, the doped isolation barrier comprising an isolation well and a buried isolation layer, the isolation well and the buried isolation layer having a second conductivity type;
an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, wherein an entirety of the isolation well is spaced from the isolation contact region, the isolation contact region having the second conductivity type; and
a depleted well region disposed in the semiconductor substrate outside of the core device area between the isolation contact region and the isolation well, the depleted well region electrically coupling the isolation contact region and the doped isolation barrier such that the isolation well and the buried isolation layer of the doped isolation barrier are biased at a voltage level lower than the voltage applied to the isolation contact region,
wherein the depleted well region partially lifts a potential of the isolation well and the buried isolation layer of the doped isolation barrier to the voltage applied to the isolation contact region to lower voltage stress between the body region and the doped isolation barrier.

US Pat. No. 10,217,859

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate;
an insulating film that is provided on the semiconductor substrate, has a first opening through which the semiconductor substrate is exposed, and contains oxygen;
a first barrier metal portion that is provided at least on a bottom portion of the first opening and in which one or more kinds of films are laminated;
an upper electrode provided above the insulating film; and
a passivation film that is provided on the upper electrode, and has a second opening that exposes the upper electrode, wherein
the semiconductor device further comprises a second barrier metal portion between the upper surface of the insulating film and the upper electrode in which one or more kinds of films are laminated, and
the second barrier metal portion has a titanium nitride film contacting the insulating film and has a titanium nitride film contacting the upper electrode.

US Pat. No. 10,217,858

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a wide-bandgap semiconductor substrate of a first conductivity type made of a semiconductor having a wider bandgap than silicon;
a wide-bandgap semiconductor layer of the first conductivity type that is formed on a front surface of the wide-bandgap semiconductor substrate and that is made of the semiconductor having a wider bandgap than silicon, said wide-bandgap semiconductor layer having a lower impurity concentration than the wide-bandgap semiconductor substrate;
a first base region of a second conductivity type that is selectively formed in a surface layer of the wide-bandgap semiconductor layer of the first conductivity type on a side opposite to the wide-bandgap semiconductor substrate;
a second base region of the second conductivity type that is selectively formed inside the wide-bandgap semiconductor layer of the first conductivity type;
a first region of the first conductivity type that is selectively formed in the surface layer of the wide-bandgap semiconductor layer of the first conductivity type on the side opposite to the wide-bandgap semiconductor substrate and that has a higher impurity concentration than the wide-bandgap semiconductor layer of the first conductivity type, the first region being located between the first base region and the second base region;
a wide-bandgap semiconductor layer of the second conductivity type that is made of the semiconductor having a wider bandgap than silicon and that is formed on a surface of the wide-bandgap semiconductor layer of the first conductivity type opposite to the wide-bandgap semiconductor substrate;
a source region of the first conductivity type that is selectively formed in the surface of the wide-bandgap semiconductor layer of the second conductivity type;
a trench that goes through the source region and the wide-bandgap semiconductor layer of the second conductivity type, the trench reaching the first region and the second base region in the wide-bandgap semiconductor layer of the first conductivity type so that the second base region is at a bottom of the trench;
a gate electrode formed inside the trench with a gate insulating film interposed therebetween;
a source electrode that contacts the source region and the wide-bandgap semiconductor layer of the second conductivity type; and
a drain electrode formed on a rear surface of the wide-bandgap semiconductor substrate,
wherein the first base region is electrically connected to the second base region, and
wherein a second region of the first conductivity type and a third region of the first conductivity type, each having a higher impurity concentration than the first region, are selectively formed in the wide-bandgap semiconductor layer of the first conductivity type such that the second region partially surrounds the second base region, and the third region partially surrounds the first base region.

US Pat. No. 10,217,857

SUPER JUNCTION MOSFET AND METHOD OF MANUFACTURING THE SAME

DB Hitek Co., Ltd, Seoul...

1. A super junction MOSFET comprising:a substrate having a first conductive type;
an epitaxial layer formed on the substrate, the epitaxial layer having the first conductive type;
a set of pillars extending from the substrate through the epitaxial layer, the set of pillars being spaced apart from each other;
a set of first wells, each of the set of first wells having a second conductive type, the set of first wells formed in the epitaxial layer to extend to an upper face of the epitaxial layer, and each of the set of first wells connected to at least one corresponding pillar of the set of pillars;
a set of second wells of the first conductive type formed in the set of first wells; and
a plurality of gate structures formed on the epitaxial layer, each extending in a first direction to have a stripe shape such that the gate structures are spaced apart from each other,
wherein the set of pillars are spaced apart from one another along a second direction perpendicular to the first direction to have multiple rows such that the pillars are arranged to have a hexagonal array in a serpentine pattern along the second direction,
wherein the set of pillars includes a first group of the set of pillars arranged in a first row and a second group of the set of pillars arranged in a second row parallel and adjacent to the first row, and each of the gate structures extends between members of the first group of the set of pillars and over members of the second group of the set of pillars, and
wherein the second group of the set of pillars are formed in the epitaxial layer, and are spaced apart from the first wells and the gate structures.

US Pat. No. 10,217,856

SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION METAL OXIDE SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD FOR THE SAME

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a first base layer of a first conductivity type;
a drain layer of the first conductivity type formed on a back side surface of the first base layer;
a second base layer of a second conductivity type formed in a surface side of the first base layer;
a source layer of the first conductivity type formed in a surface side of the second base layer;
a gate insulating film disposed on a surface of both the source layer and the second base layer;
a gate electrode disposed on the gate insulating film;
a column layer of the second conductivity type formed in the first base layer directly below both the second base layer and the source layer by opposing the drain layer so that a long-side direction of the column layer is a direction vertical to a principal surface of the drain layer;
a drain electrode disposed on the drain layer; and
a source electrode disposed on both the source layer and the second base layer, wherein
the column layer and the first base layer are alternately-arranged repeatedly in a direction parallel to the principal surface of the drain layer, and a bottom surface of the column layer and a top surface of the drain layer are separated from each other, wherein
space is defined between a bottom surface of the column layer and the upper surface of the drain layer,
the bottom surface of the column layer or an upper portion of the space is subjected to a charged particle irradiation, and
a resistance value of the space is increased from the top surface of the drain layer toward the bottom surface of the column layer.

US Pat. No. 10,217,855

SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE

Nuvoton Technology Corpor...

1. A semiconductor substrate, comprising:a base layer;
a buffer layer, disposed on the base layer;
a channel layer, disposed on the buffer layer, wherein the channel layer comprises a two-dimensional electron gas (2DEG);
a barrier layer, disposed on the channel layer; and
a buried field plate region, embedded in the channel layer, wherein the buried field plate region is located below the two-dimensional electron gas and comprises a negatively charged region and a positively charged region aside the negatively charged region.

US Pat. No. 10,217,854

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

VANGUARD INTERNATIONAL SE...

1. A semiconductor device, comprising:a substrate;
a first III-V compound layer disposed over the substrate;
a second III-V compound layer disposed over the first III-V compound layer, wherein a first carrier channel is formed in an interface between the first III-V compound layer and the second III-V compound layer;
a third III-V compound layer disposed over the second III-V compound layer;
a fourth III-V compound layer disposed over the third III-V compound layer, wherein a second carrier channel is formed in an interface between the third III-V compound layer and the fourth III-V compound layer;
a gate structure disposed over the fourth III-V compound layer;
a source region and a drain region disposed on two opposite sides of the gate structure, wherein the first carrier channel and the second carrier channel are extended between the source region and the drain region; and
a first extended electrode disposed between the second III-V compound layer and the third III-V compound layer.

US Pat. No. 10,217,853

BIPOLAR JUNCTION TRANSISTOR AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A bipolar junction transistor (BJT), comprising:a substrate having an emitter region, a base region, and a collector region;
a shallow trench isolation (STI) between the emitter region and the base region;
a first well region disposed in the base region; and
a second well region disposed in the emitter region, wherein the first well region and the second well region comprise different concentration and same conductive type, the second well region is directly under part of the STI, and bottom surfaces of the first well region and the second region are coplanar.

US Pat. No. 10,217,852

HETEROJUNCTION BIPOLAR TRANSISTORS WITH A CONTROLLED UNDERCUT FORMED BENEATH THE EXTRINSIC BASE

GLOBALFOUNDRIES Inc., Gr...

1. A device structure for a heterojunction bipolar transistor, the device structure comprising:a trench isolation region surrounding an active region;
a collector in the active region;
a base layer including a first section that is arranged over the active region and a second section that is arranged over the trench isolation region, the first section of the base layer composed of a single-crystal semiconductor material, and the second section of the base layer composed of a polycrystalline semiconductor material; and
an emitter on the first section of the base layer,
wherein the second section of the base layer is spaced in a vertical direction from the trench isolation region to define a gap.

US Pat. No. 10,217,851

ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method of manufacturing an array substrate, comprising steps of:forming a semiconductor material film, a first insulation material film and a first conductive material film successively on a base substrate, and processing the semiconductor material film, the first insulation material film and the first conductive material film through a single patterning process so as to form an active pattern, a gate insulation pattern and a gate electrode;
forming a second insulation layer over the active pattern, the gate insulation pattern and the gate electrode, and forming a first contact hole and a second contact hole through a single patterning process, each of the first contact hole and the second contact hole penetrating through the gate insulation pattern and the second insulation layer so as to expose portions of the active pattern;
forming a second conductive material film with portions thereof being filled into the first contact hole and the second contact hole, and forming an electrically conductive first contact structure and an electrically conductive second contact structure from portions of the second conductive material film, the first contact structure comprising a portion located in the first contact hole and contacting the corresponding exposed portion of the active pattern, the second contact structure comprising a portion located in the second contact hole and contacting the corresponding exposed portion of the active pattern; and
forming a third conductive material film to directly cover the second conductive material film and the first contact structure and the second contact structure, and processing the third conductive material film and the second conductive material film through a single patterning process so as to form a pixel electrode, a source electrode and a drain electrode, the source electrode and the drain electrode being in direct contact with the first contact structure and the second contact structure respectively,
wherein the second conductive material film is formed from a transparent metal oxide, and the step of forming an electrically conductive first contact structure and an electrically conductive second contact structure from portions of the second conductive material film comprises:
forming a layer of photosensitive insulation film over the second conductive material film, and removing, through a single patterning process, portions of the layer of photosensitive insulation film corresponding to the first contact structure and the second contact structure to be formed, so as to expose portions of the second conductive material film for forming the first contact structure and the second contact structure; and
reducing the metal oxide of the portions of the second conductive material film exposed from the layer of photosensitive insulation film into a metal, such that the exposed portion of the second conductive material film corresponding to the first contact hole is formed into the first contact structure and the exposed portion of the second conductive material film corresponding to the second contact hole is formed into the second contact structure.

US Pat. No. 10,217,850

METHOD OF FORMING PAIRS OF THREE-GATE NON-VOLATILE FLASH MEMORY CELLS USING TWO POLYSILICON DEPOSITION STEPS

Silicon Storage Technolog...

1. A method of forming a pair of non-volatile memory cells comprising:forming a first insulation layer on a semiconductor substrate;
forming a first polysilicon layer on the first insulation layer in a first polysilicon deposition process;
forming a pair of spaced apart insulation blocks directly on the first polysilicon layer, each of the insulation blocks having first sides facing toward each other and second sides facing away from each other;
removing portions of the first polysilicon layer while maintaining portions of the first polysilicon layer disposed underneath the pair of insulation blocks and between the pair of insulation blocks;
forming a pair of spaced apart insulation spacers adjacent the first sides and over a portion of the first polysilicon layer disposed between the pair of insulation blocks, wherein the forming of the insulation spacers includes removing portions of the first insulation layer adjacent the second sides;
removing a portion of the first polysilicon layer disposed between the insulation spacers while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks and one of the pair of insulation spacers;
forming a source region in the substrate and between the pair of insulation blocks;
removing the pair of insulation spacers;
forming insulation material that at least extends along an end portion of each of the pair of polysilicon blocks and along portions of the semiconductor substrate adjacent the second sides;
forming a second polysilicon layer over the substrate and the pair of insulation blocks in a second polysilicon deposition process;
removing portions of the second polysilicon layer while maintaining a first polysilicon block, a second polysilicon block and a third polysilicon block of the second polysilicon layer, wherein:
the first polysilicon block is disposed between the pair of insulation blocks and over the source region,
the second polysilicon block is disposed adjacent the second side of one of the insulation blocks, and
the third polysilicon block is disposed adjacent the second side of another one of the insulation blocks,
wherein the removing of the portions of the second polysilicon layer includes performing a CMP using the pair of insulation blocks as an etch stop to planarize top surfaces of the first, second and third polysilicon blocks;
forming a first drain region in the substrate and adjacent the second polysilicon block; and
forming a second drain region in the substrate and adjacent the third polysilicon block.

US Pat. No. 10,217,849

METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH NANOWIRE AND ALIGNED EXTERNAL AND INTERNAL SPACERS

1. A method for making at least one semiconductor device, comprising at least:a) making, on a support, of a stack of layers comprising at least one first crystalline semiconductor layer and at least one second crystalline semiconductor layer capable of being selectively etched in relation to the semiconductor of the first layer, wherein the second layer is arranged between the first layer and the support;
b) etching of part of the stack of layers such that at least one portion of the first layer forms a nanowire arranged on a portion of the second layer;
c) selective etching of said portion of the second layer;
d) making, in at least one space formed beneath the nanowire by etching of said portion of the second layer, of at least one portion of sacrificial material, where the etching selectivity of the sacrificial material relative to the semiconductor of the first layer is greater than that of the semiconductor of the second layer relative to the semiconductor of the first layer;
e) making of at least one sacrificial gate and of at least one external spacer laterally surrounding the sacrificial gate;
f) etching of the stack of layers, revealing ends of the nanowire and of the portion of sacrificial material aligned with the external lateral faces of the external spacer;
g) selective etching of parts of the portion of sacrificial material, from the ends of the portion of sacrificial material, forming aligned cavities beneath the external spacer;
h) making of at least one internal spacer in the cavities, aligned with the external spacer.

US Pat. No. 10,217,848

THIN FILM TRANSISTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME

Wuhan China Star Optoelec...

1. A Thin Film Transistor (TFT) structure, comprising:a substrate;
a single-layered light-shielding resin, disposed on the substrate, wherein the single-layered light-shielding resin comprises an epoxy resin or polyurethane;
a polysilicon, disposed on the single-layered light-shielding resin;
a gate electrode insulator, disposed on the substrate and the polysilicon;
a gate electrode, disposed close to the gate electrode insulator;
an interlayer dielectric layer, disposed on the gate electrode insulator and the gate electrode;
a source electrode and a drain electrode, disposed on the interlayer dielectric layer;
wherein the source electrode and the drain electrode are respectively connected with the polysilicon via two through holes; the polysilicon comprises a channel-doping portion and two through-hole-doping portions; the through-hole-doping portions and the two through holes connect with each other; the source electrode and the drain electrode are connected with the through-hole-doping portions on two sides of the channel-doping portion by the two through holes, the channel-doping portion is directly disposed between the two through-hole-doping portions.

US Pat. No. 10,217,847

POWER TRANSISTOR WITH INCREASED AVALANCHE CURRENT AND ENERGY RATING

IXYS, LLC, Milpitas, CA ...

1. A method comprising:(a) forming a drift region;
(b) forming a body region which extends down into the drift region from a first upper semiconductor surface, wherein the first upper semiconductor surface extends in a first plane, wherein the body region meets the drift region at a body-to-drift boundary, wherein the body-to-drift boundary has a central portion, wherein the central portion of the body-to-drift boundary is non-planar, and wherein the drift region forms a central ridge that extends upward toward the first upper semiconductor surface; and
(c) forming a source region which extends down into the body region from a second upper semiconductor surface, wherein the second upper semiconductor surface extends in a second plane, wherein a maximum depth of the source region is not greater than a distance between the first plane and the second plane, and wherein the first upper semiconductor surface and the second upper semiconductor surface are not coplanar.

US Pat. No. 10,217,846

VERTICAL FIELD EFFECT TRANSISTOR FORMATION WITH CRITICAL DIMENSION CONTROL

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming multiple semiconductor layers on a semiconductor substrate, the multiple semiconductor layers comprising a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a fourth semiconductor layer on the third semiconductor layer, and a fifth semiconductor layer on the fourth semiconductor layer;
patterning the multiple semiconductor layers into a multi-layer semiconductor fin;
selectively etching exposed vertical surfaces of the second semiconductor layer and the fourth semiconductor layer to form a lower spacer cavity and an upper spacer cavity, respectively;
forming a lower spacer in the lower spacer cavity and an upper spacer in the upper spacer cavity;
selectively etching exposed vertical surfaces of the third semiconductor layer to form a gate cavity; and
forming a gate structure in the gate cavity.

US Pat. No. 10,217,845

VERTICAL FIELD EFFECT TRANSISTORS WITH BOTTOM SOURCE/DRAIN EPITAXY

International Business Ma...

16. A vertical fin field-effect-transistor comprising at least:a substrate;
a first source/drain layer comprising a plurality of pillar structures;
a plurality of fins each disposed on and in contact with a pillar structure in the plurality of pillar structures;
a doped epitaxy layer grown from the first source/drain layer in contact with the plurality of fins and the plurality of pillar structures;
a gate structure in contact with the plurality of fins;
a spacer layer in contact with at least the gate structure and the plurality of fins; and
a second source/drain layer disposed on at least the gate structure.

US Pat. No. 10,217,844

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING AN N TYPE SEMICONDUCTOR REGION FORMED IN A P TYPE SEMICONDUCTOR LAYER

TOYODA GOSEI CO., LTD, K...

1. A method of manufacturing a semiconductor device, comprising:a process of forming a p-type semiconductor layer that contains a p-type impurity and has a dislocation density of not higher than 1.0×107 cm?2, on an n-type semiconductor layer that contains an n-type impurity and has a dislocation density of not higher than 1.0×107 cm?2;
an n-type semiconductor region forming process of forming an n-type semiconductor region in at least part of the p-type semiconductor layer by ion-implanting an n-type impurity into the p-type semiconductor layer and performing heat treatment to activate the ion-implanted n-type impurity; and
a process of forming a trench that is recessed to pass through the p-type semiconductor layer and reach the n-type semiconductor layer, wherein
in the performing of the heat treatment of the n-type semiconductor region forming process, a p-type impurity diffusion region formed in the n-type semiconductor layer and below the n-type semiconductor region.

US Pat. No. 10,217,843

FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH STRAINED CHANNELS

International Business Ma...

1. A vertical fin field effect transistor (finFET), comprising;one or more vertical fins formed on a substrate, wherein the one or more vertical fins are a semiconductor material;
a first anchor wall at a first end of the one or more vertical fins, wherein the first anchor wall is in contact with a first endwall of each of the one or more vertical fins, and a second anchor wall at a second end of the one or more vertical fins opposite the first end, wherein the second anchor wall is in contact with a second endwall of each of the one or more vertical fins, and the first anchor wall and second anchor wall are silicon oxide, silicon nitride, or silicon oxynitride, that maintains the one or more vertical fins in a strained state;
a bottom spacer on the substrate and adjacent the sidewall of at least one of the one or more vertical fins; and
a gate dielectric layer on at least a portion of the sidewalls of at least one of the one or more vertical fins, a work function layer on the ate dielectric layer, and a gate metal layer on the work function layer, wherein the gate dielectric layer, work function layer, and gate metal layer are between the first anchor wall and the second anchor wall.

US Pat. No. 10,217,842

METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INNER SPACERS

1. A method for making a semiconductor device, including at least:a) making, on a substrate, a stack comprising at least one first semiconductor portion arranged between at least two second portions of at least one material able to be selectively etched relative to the semiconductor of the first portion, the first portion being able to form at least one active zone of the semiconductor device,
b) making, on a part of the stack, outer spacers and at least one dummy gate arranged between the outer spacers,
c) etching the second portions such that remaining parts of the second portions are arranged at least under the dummy gate,
d) partially oxidising the remaining parts of the second portions from outer faces of the remaining parts of the second portions which are revealed by etching the second portions, forming inner spacers,
e) removing the dummy gate and the non-oxidised parts of the remaining parts of the second portions arranged at least under the dummy gate,
f) making a gate between the outer spacers and between the inner spacers, covering the channel and able to be electrically insulated from source and drain regions by the outer spacers and the inner spacers.

US Pat. No. 10,217,841

FORMING AN UNIFORM L-SHAPED INNER SPACER FOR A VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTOR (VT FINFET)

International Business Ma...

1. A method of forming a vertical transport fin field effect transistor (VT FinFET), comprising:forming a plurality of vertical fins on a substrate;
forming a sacrificial liner on at least two of the plurality of vertical fins;
forming sidewall spacers on the vertical surfaces of the sacrificial liner, wherein the sidewall spacers are on opposite sides of the at least two of the plurality of vertical fins; and
removing a portion of the sacrificial liner to form an L-shaped channel adjacent to each of the at least two of the plurality of vertical fins.

US Pat. No. 10,217,840

REPLACEMENT METAL GATE STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A method comprising:forming a dummy gate structure with a first spacer;
forming a gate dielectric material on the first spacer;
removing a portion of the first spacer to form a space between an interlevel dielectric material and the gate dielectric material;
etching the gate dielectric material from within the space to form a recessed portion with exposure of sidewalls of the interlevel dielectric material above the first spacer;
depositing a second spacer on the exposed sidewalls of the interlevel dielectric material;
filling the recessed portion with a metal gate material; and
forming a self-aligned contact adjacent to the metal gate material.

US Pat. No. 10,217,839

FIELD EFFECT TRANSISTOR (FET) WITH A GATE HAVING A RECESSED WORK FUNCTION METAL LAYER AND METHOD OF FORMING THE FET

GLOBALFOUNDRIES INC., Gr...

1. A field effect transistor comprising:a gate adjacent to a semiconductor body at a channel region and comprising:
a conformal dielectric layer immediately adjacent to the semiconductor body; and,
a stack of gate conductor layers comprising:
a conformal metal layer on the conformal dielectric layer; and
a conductive fill material layer on the conformal metal layer, wherein the conductive fill material layer has a top surface and an outer sidewall, the outer sidewall has a lower portion and an upper portion above the lower portion, and the conformal metal layer has an essentially vertical portion positioned laterally immediately adjacent to the lower portion of the outer sidewall; and
a gate cap having a center portion and an edge portion, wherein the center portion is above and immediately adjacent to the top surface and the edge portion is positioned laterally immediately adjacent to the upper portion of the outer sidewall and is further above and immediately adjacent to a top of the vertical portion of the conformal metal layer.

US Pat. No. 10,217,838

SEMICONDUCTOR STRUCTURE WITH MULTIPLE TRANSISTORS HAVING VARIOUS THRESHOLD VOLTAGES

MIE FUJITSU SEMICONDUCTOR...

1. A method of fabricating a semiconductor structure, comprising:implanting in a substrate a first antipunchthrough region for a transistor element;
implanting in the substrate a second antipunchthrough region for the transistor element;
implanting in the substrate a first screening region for the transistor element with a first dopant species;
implanting in the substrate a second screening region for the transistor element with a second dopant species different from the first dopant species;
forming a substantially undoped epitaxial layer covering the first and the second screening regions to form a channel layer for the transistor element, and
wherein the first dopant species and the second dopant species are of same polarity;the second anitpunchthrough region is located under the first screening region and the second screening region, the first antipunchthrough region is located under the second antipunchthrough region.

US Pat. No. 10,217,837

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING ELECTRODE TRENCHES, ISOLATED SOURCE ZONES AND SEPARATION STRUCTURES

Infineon Technologies AG,...

1. A semiconductor device, comprising:a semiconductor mesa comprising source zones and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone;
electrode structures on opposite sides of the semiconductor mesa, at least one of the electrode structures comprising a gate electrode configured to control a charge carrier flow through the at least one body zone; and
a separation region arranged along an extension direction of the semiconductor mesa,
wherein in the separation region, the semiconductor mesa comprises a constricted portion that is partially or completely oxidized.

US Pat. No. 10,217,836

METHOD OF MANUFACTURING POWER SEMICONDUCTOR DEVICE

MagnaChip Semiconductor, ...

1. A method of manufacturing a power semiconductor device, comprising:forming trenches in a substrate, wherein the substrate comprises a first surface and a second surface opposite to the first surface;
forming a gate insulating layer and a gate electrode in each of the trenches;
forming a P-type base region between the trenches in the substrate;
performing a first implantation process using P-type dopants implanted onto the P-type base region;
forming an N+ source region in the substrate;
forming an interlayer insulating layer on the N+ source region;
performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region;
forming an emitter electrode in contact with the N+ source region and the P+ doped region;
forming a P-type collector region on the second surface of the substrate; and
forming a drain electrode on the P-type collector region.

US Pat. No. 10,217,835

BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a channel region of a semiconductor substrate composed of a type III-V semiconductor material;
a gate structure including an interlayer consisting of titanium aluminum oxynitride (TiAlON) present atop the channel region, wherein the gate structure further includes a high-k dielectric layer including hafnium directly atop the interlayer, and a layer of metal nitride directly atop the high-k dielectric layer, wherein the metal nitride is selected from the group consisting of TiN, AlN, TiAlN, TaN, NbN, Vn, WN and combinations thereof; and
source and drain regions on opposing sides of the channel region.

US Pat. No. 10,217,834

BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS

INTERNATIONAL BUSINESS MA...

1. A method of forming a binary alloy oxide based interlayer comprising:treating an aluminum containing III-V semiconductor substrate with a two stage treatment including a first surface treatment with ammonium hydroxide (NH4OH) followed by a second surface treatment with ammonium sulfide (NH4)2S to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer of arsenic oxide on the semiconductor substrate; and
converting the oxide containing interfacial layer to a binary alloy oxide comprising aluminum, titanium, oxygen and nitrogen using a plasma deposition sequence including alternating a metal gas precursor and a plasma selected from the group consisting of hydrogen, nitrogen or a combination thereof.

US Pat. No. 10,217,833

THIN FILM TRANSISTOR INCLUDING SCHOTTKY DIODE UNIT IN AN INSULATING MEDIUM LAYER

Tsinghua University, Bei...

1. A thin film transistor comprising:a gate electrode, an insulating medium layer and at least one Schottky diode unit, wherein the insulating medium layer is located on the gate electrode, the at least one Schottky diode unit is located on a surface of the insulating medium layer and insulated from the gate electrode via the insulating medium layer, the at least one Schottky diode unit comprises:
a first electrode located on the surface of the insulating medium layer, wherein the first electrode comprises a first metal layer and a second metal layer, the first metal layer covers the second metal layer, one end of the second metal layer is extended with respect to the first metal layer to form a step structure in the first electrode;
a second electrode located on the surface of the insulating medium layer and apart from the first electrode, wherein the second electrode comprises a third metal layer and a fourth metal layer, the third metal layer covers the fourth metal layer, one end of the third metal layer protrudes with respect to the fourth metal layer to form an inverted step structure in the second electrode; and
a semiconductor structure comprising a first end and a second end, wherein the first end of the semiconductor structure is sandwiched by the first metal layer and the second metal layer, the second end of the semiconductor structure is sandwiched by the third metal layer and the fourth metal layer, a portion of the semiconductor structure between the first end and the second end is defined as a middle portion, the step structure of the first electrode and the inverted step structure of the second electrode are both located between the first end and the second end of the semiconductor structure, and near the middle portion of the semiconductor structure, the semiconductor structure is a nano-scale semiconductor structure.

US Pat. No. 10,217,832

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate;
an insulating film that is provided on the semiconductor substrate, has an opening through which the semiconductor substrate is exposed, and contains oxygen;
a first barrier metal portion that is provided at least on a bottom portion of the opening and in which one or more kinds of films are laminated; and
an upper electrode that is provided above the insulating film, and contains Al as a main component, or Cu as a main component; wherein
a barrier metal is not provided between an upper surface of the insulating film and the upper electrode, or the semiconductor device further comprises a second barrier metal portion between the upper surface of the insulating film and the upper electrode, the second barrier metal portion having a configuration different from that of the first barrier metal portion.

US Pat. No. 10,217,831

HIGH ELECTRON MOBILITY TRANSISTOR DEVICES

VANGUARD INTERNATIONAL SE...

1. A HEMT device, comprising:a substrate;
a first epitaxial layer formed on the substrate;
a second epitaxial layer having a surface formed on the first epitaxial layer;
an insulating layer formed on the second epitaxial layer;
a gate formed in the insulating layer and extending into the second epitaxial layer, wherein the gate has a sidewall and a bottom; and
a source and a drain formed in the insulating layer and extending into the second epitaxial layer, wherein the source and the drain have a sidewall and a bottom, wherein the bottoms of the source and the drain are formed in the second epitaxial layer, and the source and the drain are located on both sides of the gate.

US Pat. No. 10,217,830

SEMICONDUCTOR DEVICE HAVING TRENCHES WITH ENLARGED WIDTH REGIONS

Infineon Technologies AG,...

1. A semiconductor device comprising:a plurality of trenches extending into a semiconductor substrate, wherein each trench of the plurality of trenches comprises a plurality of enlarged width regions distributed along the trench, and wherein at least one electrically conductive trench structure is located in each trench of the plurality of trenches;
an electrically insulating layer arranged between the semiconductor substrate and a first electrode structure; and
a first vertical electrically conductive structure extending through the electrically insulating layer, wherein the first vertical electrically conductive structure forms an electrical connection between the first electrode structure and an electrically conductive trench structure located in a first trench of the plurality of trenches at a first enlarged width region of the plurality of enlarged width regions of the first trench of the plurality of trenches, and
wherein the electrically insulating layer is arranged between a second enlarged width region of the plurality of enlarged width regions of the first trench and the first electrode structure or a second electrode structure above the second enlarged width region without any vertical electrical connections through the electrically insulating layer at the second enlarged width region.

US Pat. No. 10,217,829

COMPOUND SEMICONDUCTOR DEVICE INCLUDING DIFFUSION PREVENTING LAYER TO SUPPRESS CURRENT COLLAPSE PHENOMENON, METHOD OF MANUFACTURING COMPOUND SEMICONDUCTOR DEVICE, POWER SUPPLY UNIT, AND AMPLIFIER

FUJITSU LIMITED, Kawasak...

1. A compound semiconductor device comprising:a substrate;
an electron transit layer formed on the substrate;
a compound semiconductor layer containing gallium and formed on the electron transit layer;
a diffusion preventing layer containing gallium oxide and formed on the compound semiconductor layer;
an insulation layer formed on the diffusion preventing layer;
a source electrode, a drain electrode, and a gate electrode formed over the electron transit layer at a distance from one another; and
a barrier layer formed on the electron transit layer,
wherein the compound semiconductor layer is a cap layer of gallium nitride formed on the barrier layer, and
the cap layer includes:
an upper layer located close to the diffusion preventing layer; and
a lower layer located below the upper layer,
wherein a composition ratio of gallium in the upper layer is smaller than a composition ratio of gallium in the lower layer.

US Pat. No. 10,217,828

TRANSISTORS WITH FIELD PLATES ON FULLY DEPLETED SILICON-ON-INSULATOR PLATFORM AND METHOD OF MAKING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:forming a silicon-on-insulator (SOI) substrate as a field plate on a field plate oxide;
forming a high-voltage p-type well in a p-type substrate of a bulk transistor on which the SOI substrate is formed, the high-voltage p-type well formed between shallow trench isolation (STI) regions of the p-type substrate;
forming an n-drift region in the high-voltage p-type well;
forming a first gate on the high-voltage p-type well; and
implanting a first n-type region adjacent to the gate as a source region and a second n-type region adjacent to the SOI substrate as a drain region,
wherein the SOI substrate comprises a silicon wafer with a buried oxide insulator, wherein the silicon wafer is the field plate and the buried oxide insulator is the field plate oxide.

US Pat. No. 10,217,827

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)

RFHIC Corporation, Anyan...

1. A semiconductor transistor, comprising:an epitaxial layer;
a drain formed on the epitaxial layer;
an insulating layer formed on the epitaxial layer and covering the drain except a first contact open area on a top surface of the drain;
a drain field plate formed of an electrically conducting material and disposed on a portion of the insulating layer and on the first contact open area to thereby make a direct contact to the drain at the first contact open area, the drain field plate having a projection area that extends outside a projection area of the drain; and
a passivation layer formed of electrically insulating material and disposed between the insulating layer and the drain field plate and covering the drain except the first contact open area on the top surface of the drain.

US Pat. No. 10,217,826

APPARATUS OF A METAL-OXIDE-SEMICONDUCTOR (MOS) TRANSISTOR INCLUDING A MULTI-SPLIT GATE

TOWER SEMICONDUCTOR LTD.,...

1. An Integrated Circuit (IC) comprising at least one metal-oxide-semiconductor (MOS) transistor, the MOS transistor comprising:a source;
a drain;
a body; and
a multi-split gate comprising a control gate component configured to control conductivity of said MOS transistor, and at least first and second field plate gate components, said first field plate gate component is electrically isolated from said second field plate gate component, said first and second field plate gate components are electrically isolated from said control gate, the control gate component is configured to control the conductivity of said MOS transistor by creating a channel in an inversion region of said MOS transistor, the first field plate gate component is over an accumulation area of said MOS transistor, the second field plate gate component is over a depletion area of said MOS transistor.

US Pat. No. 10,217,825

METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTACTS AND METHOD OF FORMING

Toyko Electron Limited, ...

1. A method of forming a semiconductor device, the method comprising:providing a semiconductor substrate containing a contact region;
depositing an insulator film on the contact region, the insulator film including a mixed oxide material containing a mixture of titanium oxide (TiO2) and at least one additional metal oxide;
depositing a metal-containing electrode layer abutting the insulator film to form a metal-insulator-semiconductor (MIS) structure; and
heat-treating the MIS structure to scavenge oxygen from the TiO2 in the insulator film to the metal-containing electrode layer to form a MIS contact with oxygen vacancies in the TiO2.

US Pat. No. 10,217,824

CONTROLLED ION IMPLANTATION INTO SILICON CARBIDE USING CHANNELING AND DEVICES FABRICATED USING CONTROLLED ION IMPLANTATION INTO SILICON CARBIDE USING CHANNELING

Cree, Inc., Durham, NC (...

1. An electronic device, comprising:a silicon carbide drift region having a first conductivity type and a first doping concentration;
a well region in the drift region, the well region having a second conductivity type opposite the first conductivity type and having a second doping concentration; and
a deeply implanted region below the well region, wherein the deeply implanted region has a third doping concentration that is greater than the first doping concentration and less than the second doping concentration.

US Pat. No. 10,217,823

SEMICONDUCTOR DEVICE

SUMITOMO ELECTRIC INDUSTR...

1. A semiconductor device, comprising:a substrate;
a channel layer made of graphene and provided on the substrate;
a source electrode and a drain electrode provided on the channel layer;
an insulating film provided on the channel layer between the source electrode and the drain electrode;
a first gate electrode provided on the insulating film between the source electrode and the gate electrode; and
a second gate electrode provided within the substrate and between the first gate electrode and the drain electrode,
wherein the first gate electrode is closer to the source electrode than the second gate electrode and partially overlaps the second gate electrode.

US Pat. No. 10,217,822

SEMICONDUCTOR-ON-INSULATOR WITH BACK SIDE HEAT DISSIPATION

QUALCOMM Incorporated, S...

1. A singulated semiconductor-on-insulator (SOI) structure comprising:an active layer including a transistor having a source, a gate, and a drain;
a patterned layer formed on a back side of the active layer, wherein the patterned layer includes insulator material etched in a pattern, wherein the pattern includes a portion of insulator material formed below the gate, wherein a lateral dimension of the gate lies entirely within a lateral dimension of the portion of insulator material and the source and drain each lie only partially within the lateral dimension of the portion of insulator material; and
a strain layer deposited below the patterned layer and covering the portion of insulator material as well as an excavated region of the strain layer adjacent the portion of insulator material, wherein:
the excavated region extends laterally from below the source to beyond a periphery of the transistor;
wherein a lateral dimension of the excavated region is larger than a length of a channel of the transistor by at least a factor of ten.

US Pat. No. 10,217,821

POWER INTEGRATED DEVICES, ELECTRONIC DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME

SK HYNIX SYSTEM IC INC., ...

1. A power integrated device comprising:a channel region disposed in a first region of a semiconductor layer;
a source region disposed in a second region of the semiconductor layer;
a drift region disposed in a third region of the semiconductor layer, wherein the channel region is disposed between the source region and the drift region in a channel length direction;
a drain region disposed in the drift region;
a stacked gate including a gate insulation layer and a gate electrode and extending from over the channel region to over the drift region;
a plurality of deep trench field insulation layers each of which is disposed in the drift region, and between the stacked gate and the drain region in the channel length direction, sides of the each of the plurality of deep trench field insulation layers being surrounded by the drift region; and
a plurality of stacked gate extension portions which extend from the stacked gate to over the plurality of deep trench field insulation layers in the channel length direction, respectively, the plurality of stacked gate extension portions being spaced apart from each other in a channel width direction,
wherein the plurality of deep trench field insulation layers are separated from each other in the channel width direction,
wherein the drift region has a different conductivity from the first region of a semiconductor layer,
wherein each of the plurality of deep trench field insulation layers has a height greater than a width,
wherein the height is measured in a third direction and the width is measured in the channel length direction,
wherein the third direction is perpendicular to each of the channel length and the channel width directions,
wherein each of the plurality of stacked gate extension portions is entirely overlapped with each of the plurality of deep trench field insulation layers in a plane view, and
wherein each of the plurality of deep trench field insulation layers penetrates the drift region in the third direction and extends down to a level lower than a bottom of the drift region.

US Pat. No. 10,217,820

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

8. A semiconductor device, comprising:a diffusion prevention insulation pattern on a substrate, wherein the diffusion prevention insulation pattern comprises a lower surface facing the substrate and an upper surface opposite the lower surface;
a conductive pattern on the diffusion prevention insulation pattern, the conductive pattern having a sidewall that is not substantially vertical to a top surface of the substrate, wherein a portion of the diffusion prevention insulation pattern is between the substrate and the conductive pattern, and the conductive pattern comprises a lowermost surface facing the upper surface of the diffusion prevention insulation pattern, and wherein the lowermost surface of the conductive pattern contacts the upper surface of the diffusion prevention insulation pattern;
a barrier layer on an upper surface of the conductive pattern;
an insulating interlayer on the barrier layer and the conductive pattern; and
an air gap in the insulating interlayer, the air gap horizontally overlapping at least a portion of the sidewall of the conductive pattern.

US Pat. No. 10,217,819

SEMICONDUCTOR DEVICE INCLUDING METAL-2 DIMENSIONAL MATERIAL-SEMICONDUCTOR CONTACT

Samsung Electronics Co., ...

1. A semiconductor device comprising:a semiconductor layer including a well region doped to a first conductivity type and a source region and a drain region doped to a second conductivity type electrically opposite the first conductivity type;
a metal layer electrically contacting the semiconductor layer; and
a two-dimensional material layer between the semiconductor layer and the metal layer, the two-dimensional material layer having a two-dimensional crystal structure, the two-dimensional material layer being patterned in one of a plurality of nanowires, a plurality of nano-slits, and a plurality of nano-dots, the two-dimensional material layer including,
a first two-dimensional material layer on the source region, the metal layer including a source electrode on the first two-dimensional material layer, and
a second two-dimensional material layer on the drain region, the metal layer including a drain electrode on the second two-dimensional material layer,
wherein a part of the source region directly contacts the source electrode.

US Pat. No. 10,217,818

METHOD OF FORMATION OF GERMANIUM NANOWIRES ON BULK SUBSTRATES

International Business Ma...

1. A semiconductor structure comprising:a bulk substrate comprising a semiconductor material and having at least one notched surface portion and at least one recessed portion adjacent to the at least one notched surface portion of the substrate, wherein said at least one recessed portion has an uppermost horizontal surface below an uppermost surface of said at least once notched surface portion, and wherein said at least one notched surface portion of said bulk substrate has a pointed topmost surface;
a vertical stack of horizontal nanowires suspended directly above said at least one notched surface portion of said bulk substrate, wherein each horizontal nanowire of said vertical stack of horizontal nanowires consists of germanium and is of unitary construction, and wherein each horizontal nanowire has a horizontal planar topmost surface, a horizontal planar bottommost surface and faceted vertical sidewall surfaces, and wherein the planar topmost surface and the planar bottommost surface of each horizontal nanowire are parallel to a horizontal surface of said bulk substrate; and
a contiguous dielectric material layer located directly on an entire horizontal surface of said bulk substrate.

US Pat. No. 10,217,817

SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FORMATION IN STACKED-CHANNEL FETS

International Business Ma...

1. A method for forming a field effect transistor, comprising:forming a stack of nanosheets of alternating layers of channel material and sacrificial material, with a layer of sacrificial material forming a top layer of the stack;
forming a dummy gate over the stack;
etching away stack material outside of a region covered by the dummy gate;
selectively etching the sacrificial material to form recesses in the sacrificial material layers;
forming spacers in the recesses in the sacrificial material layers, with at least one pair of spacers being formed in recesses above an uppermost layer of channel material;
etching away the dummy gates with an anisotropic etch, where the top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch;
etching away the sacrificial material with an isotropic etch to expose the layers of channel material; and
forming a gate stack over and around the layers of channel material.

US Pat. No. 10,217,816

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a plurality of channels sequentially stacked on a substrate, the plurality of channels spaced apart from each other in a first direction perpendicular to a top surface of the substrate;
source/drain layers at opposite sides of the plurality of channels in a second direction parallel to the top surface of the substrate, the source/drain layers connected to the plurality of channels; and
a gate structure enclosing the plurality of channels, wherein the plurality of channels have different lengths in the second direction and different thicknesses in the first direction, wherein each of the source/drain layers includes:
an epitaxial layer on the substrate; and
extension portions extending from the epitaxial layer in the second direction and respectively connected to the plurality of channels.

US Pat. No. 10,217,815

INTEGRATED CIRCUIT DEVICE WITH SOURCE/DRAIN BARRIER

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:receiving a workpiece that includes:
a substrate; and
a device fin extending above the substrate, wherein the device fin includes a channel region;
etching a portion of the device fin adjacent the channel region, wherein the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess;
cleaning the workpiece to remove a first portion of the dielectric barrier from the source/drain recess such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess; and
forming a source/drain feature within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

US Pat. No. 10,217,814

SEMICONDUCTOR DEVICE

Nuvoton Technology Corpor...

1. A semiconductor device, comprising:a metal-oxide-semiconductor field-effect transistor (MOSFET), disposed on a substrate, wherein the MOSFET comprises a source region, a drain region, and a gate structure disposed between the source region and the drain region;
a plurality of junction gate field-effect transistors (JFETs) connected in parallel, being connected with the MOSFET in series, wherein each of the JFETs laterally extends between the source region and the drain region; and
a plurality of first isolation structures, respectively disposed among the JFETs, wherein each of the first isolation structures laterally extends between the source region and the drain region.

US Pat. No. 10,217,813

METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE

Sumitomo Electric Industr...

1. A silicon carbide semiconductor device comprising:a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to said first main surface;
an epitaxial layer formed on said first main surface, said epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which said silicon carbide substrate is located;
a trench which is formed in said epitaxial layer and includes side walls intersecting with said third main surface and a bottom portion connected to said side walls; and
an embedded region, which is formed in said trench and has a second conductivity type different from said first conductivity type, said trench being filled with said embedded region;
an opening of said trench being wider than said bottom portion, and said epitaxial layer adjacent to said embedded region and said embedded region constituting a superjunction structure, said silicon carbide semiconductor device further comprising:
an impurity region formed on said embedded region and having said second conductivity type;
a first electrode provided on said impurity region; and
a second electrode in contact with said second main surface.

US Pat. No. 10,217,812

SILICON-ON-INSULATOR CHIP HAVING MULTIPLE CRYSTAL ORIENTATIONS

Infineon Technologies AG,...

1. A silicon-on-insulator device having multiple crystal orientations comprising:a substrate layer;
an insulating layer disposed on the substrate layer;
a first strained silicon layer having a first crystal orientation disposed directly on a portion of the insulating layer;
a strain inducing layer comprising a strained material disposed on another portion of the insulation layer; and
a second strained silicon layer disposed directly on the strain inducing layer so as to be spaced from the insulating layer by the strain inducing layer and having a crystal orientation different from the first crystal orientation.

US Pat. No. 10,217,811

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a silicon carbide layer having a front surface inclined at 0° or more and 10° or less with respect to a (0001) face;
a silicon oxide layer; and
a region located between the front surface and the silicon oxide layer and having the number of carbon-carbon single bonds larger than the number of carbon-carbon double bonds.