US Pat. No. 10,142,039

INTEGRATED CIRCUIT CALIBRATION ARCHITECTURE

pSemi Corporation, San D...

1. A method for calibrating a radio frequency (RF) integrated circuit, including:(a) providing a primary RF transmission path and a primary RF reception path on an integrated circuit;
(b) selectively connecting at least one RF transceiver front-end circuit through a multi-way switch complex to the primary RF transmission path and the primary RF reception path;
(c) coupling at least one switchable internal calibration path to the at least one RF transceiver front-end circuit;
(d) configuring the at least one switchable internal calibration path to convey, in a calibration mode, an RF test signal from the primary RF transmission path through the multi-way switch complex and thence through at least a portion of the coupled at least one RF transceiver front-end circuit to the primary RF reception path; and
(e) providing at least one inter-chip switch for enabling selectable access from external to the integrated circuit to at least one of the primary RF transmission path, the primary RF reception path, and/or the at least one switchable internal calibration path; wherein at least one RF transceiver front-end circuit comprises a phase-attenuation core.

US Pat. No. 10,142,038

MIMO SIGNAL GENERATOR WITH FREQUENCY MULTIPLEXING

1. A MIMO signal generator, adapted to generate a MIMO signal, comprising:a signal generator, a signal divider, and a frequency shifter,
wherein the signal generator is adapted to generate a plurality of frequency shifted partial MIMO signals within a first signal generator output signal, the plurality of frequency shifted partial MIMO signals being arranged on a frequency axis in a non-overlapping manner,
wherein the signal divider is adapted to divide the first signal generator output signal onto a plurality of signal paths,
wherein the frequency shifter is adapted to shift frequencies of the plurality of frequency shifted partial MIMO signals to a joint carrier frequency, resulting in a plurality of partial MIMO signals, forming the MIMO signal, and
wherein the signal generator is adapted arrange the plurality of frequency shifted partial MIMO signals on the frequency axis in the non-overlapping manner, by placing a carrier frequency of all but one of the plurality of frequency shifted partial MIMO signals to different frequencies.

US Pat. No. 10,142,037

MEASUREMENT DEVICE AND MEASUREMENT METHOD

ANRITSU CORPORATION, Kan...

3. A measurement device, comprising:a plurality of measurement means that are respectively connected to a plurality of devices to be measured capable of using a plurality of communication frequency bands, and perform measurements of at least one of transmission characteristics and reception characteristics of the plurality of devices to be measured in parallel using different communication frequency bands,
wherein the communication frequency bands correspond to different channels and/or different communication protocols,
wherein each of the plurality of measurement means comprises:
signal input means for receiving a signal for measuring the transmission characteristics with a frequency in a communication frequency band from each of the plurality of measurement devices, respectively; and
signal output means for outputting a signal for measuring the reception characteristics with a frequency in a communication frequency band to each of the plurality of devices to be measured, respectively,
wherein the measurement device further comprises:
band information storage means for storing information on the communication frequency bands handled by the plurality of signal input means and the plurality of signal output means;
band setting means for setting a communication frequency band handled by the plurality of signal input means and the plurality of signal output means; and
band management means for executing a process of storing information on a communication frequency band handled by the plurality of signal input means and the plurality of signal output means in the band information storage means, and clearing the information on the used communication frequency band from the band information storage means when the plurality of signal input means and the plurality of signal output means end measurement,
wherein the band setting means outputs a use request for use of the signal input means or the signal output means, and a communication frequency band desired to be used, to the band management means,
wherein the band management means determines permission or refusal in response to the use request on the basis of the information on the communication frequency band stored in the band information storage means with respect to the band setting means, and
wherein in the plurality of measurement means:
the band information storage means is included in the plurality of measurement means, and includes a plurality of used band information storage means for storing information on a communication frequency band handled by the signal input means and the signal output means of the own measurement means; and
the band setting means is included in the plurality of measurement means, and includes used band setting means for setting the communication frequency band handled by the signal input means and the signal output means of the own measurement means on the basis of information on the communication frequency band stored in the used band information storage means of another measurement means.

US Pat. No. 10,142,036

CONFIGURATION SUB-SYSTEM FOR TELECOMMUNICATION SYSTEMS

Andrew Wireless Systems G...

1. A configuration sub-system comprising:an input communicatively coupleable to a base station;
a test signal generator integrated into the configuration sub-system, wherein the configuration sub-system is configured to switch between a first mode and a second mode, wherein in the first mode the configuration sub-system is configured to provide a test signal generated by the test signal generator to a downlink path, wherein in the second mode the configuration sub-system is configured to provide an RF downlink signal that is received via the input from the base station to the downlink path and deactivate the test signal generator, wherein the configuration sub-system is configured to provide the RF downlink signal to the downlink path only in the second mode;
a power measurement device integrated into the configuration sub-system, the power measurement device being configured to:
measure a test signal power of the test signal at a measurement point in the downlink path, and
measure a downlink signal power of the RF downlink signal at the measurement point; and
a controller configured to normalize signals transmitted using a distributed antenna system via the configuration sub-system by adjusting a downlink path gain for the downlink path based on the test signal power measured by the power measurement device, wherein the distributed antenna system is configured to transmit the RF downlink signal using the downlink path gain as adjusted by the controller.

US Pat. No. 10,142,035

INFORMATION TRANSMISSION METHOD, APPARATUS AND SYSTEM

Tencent Technology (Shenz...

1. An information transfer method, applied to a first terminal having one or more processors and a memory for storing program instructions that are executed by the one or more processors, the method comprising:acquiring to-be-transmitted information;
encoding the to-be-transmitted information at least once by using a preset encoding mode, to obtain vibration code information; and
determining, according to a preset rule, a vibration rhythm corresponding to the vibration code information, and causing the first terminal to vibrate according to the determined vibration rhythm, so as to transfer the to-be-transmitted information to a second terminal.

US Pat. No. 10,142,034

OPTICALLY TRANSMISSIVE ELECTRONIC DEVICE HAVING AN OPTICALLY TRANSMISSIVE LIGHT EMITTING DEVICE TO TRANSMIT OPTICAL SIGNAL TO A SECOND OPTICALLY TRANSMISSIVE LIGHT RECEIVING DEVICE THROUGH A FIRST OPTICALLY TRANSMISSIVE LIGHT RECEIVING DEVICE

PHILIPS LIGHTING HOLDING ...

1. An electronic device comprising:an optically transmissive light-emitting device;
first optically transmissive light-receiving device;
a second optically transmissive light-receiving device; and
arranged such that an optical signal transmitted from said light-emitting device propagates unguided from said light-emitting device, and is received by said first light-receiving device,
wherein said optically transmissive light-emitting device is configured to transmit said optical signal such that a portion of said optical signal is transmitted to said second optically transmissive light-receiving device through said first optically transmissive light-receiving device.

US Pat. No. 10,142,033

COMMUNICATION APPARATUS AND COMMUNICATION METHOD FOR SUCCESSIVE QUANTUM KEY DISTRIBUTION

Korea Institute of Scienc...

11. A communication method performed by a communication apparatus, the communication method comprising:receiving, from an other communication apparatus coupled to the communication apparatus, a synchronization signal and a first quantum signal generated by a first light source of the other communication apparatus;
detecting the synchronization signal received from the other communication apparatus;
generating, by a second light source, a decoy signal to be added to a second quantum signal, generated by reflecting the first quantum signal off a reflector, that is to be sent to the other communication apparatus in response to the first quantum signal being generated and received from the first light source of the other communication apparatus according to a result of the detecting of the synchronization signal; and
adding the generated decoy signal to pairs of photon pulses in second the quantum signal based on the result of the detecting of the synchronization signal, to monitor hacking of an eavesdropper in a plug and play quantum key distribution.

US Pat. No. 10,142,032

TEMPERATURE INSENSITIVE DELAY LINE INTERFEROMETER

INPHI CORPORATION, Santa...

1. A photonics optical system comprising:a photonics device with temperature insensitive characteristics comprising:
a first waveguide comprising a first length of a first material characterized by a first group index corresponding to a first phase delay for transferring a first light wave with a first peak frequency at an ambient temperature;
a second waveguide comprising a second length of a second material characterized by a second group index corresponding to a second phase delay for transferring a second light wave with a second peak frequency with a time-delay difference relative to the first light wave at the same ambient temperature;
wherein the first phase delay and the second phase delay are configured to change by a same amount upon any change of the ambient temperature, and the time-delay difference of the first light wave and the second light wave is equal to an inversed value of a free spectral range (FSR) configured to align the first peak frequency and the second peak frequency to two channels in a designated frequency grid; and
a network.

US Pat. No. 10,142,031

APPARATUS, METHOD AND COMPUTER PROGRAM FOR A RECEIVER OF AN OPTICAL SIGNAL

ALCATEL LUCENT, Boulogne...

1. An apparatus for a receiver of an optical signal being configured to:input digitized samples of the optical signal at a first sampling rate;
filter the digitized samples based on a plurality of filter coefficients to obtain filtered samples of the optical signal at a second sampling rate, the second sampling rate being different from the first sampling rate; and
output the filtered samples of the optical signal at the second sampling rate;
wherein the apparatus is further configured to:
filter, via an adaptive filter, the digitized samples at the first sampling rate;
base an updating of coefficients of the adaptive filter on a fraction of output samples of the adaptive filter;
select samples which are used to update the coefficients of the adaptive filter as samples of the filtered samples of the optical signal; and
determine other samples of the filtered samples of the optical signal.

US Pat. No. 10,142,030

M-ARY FREQUENCY PRESENCE MODULATION COMMUNICATION SYSTEM AND METHOD

BOOZ ALLEN HAMILTON INC.,...

1. An optical communication system, comprising:a data transmitter including:
at least one optical emission device configured to output light energy as an optical beam having an operating bandwidth,
a beam divider to receive and divide the operating bandwidth of the optical beam into bandwidth portions of plural communication bands,
a focusing grating, and
a digital mirror array having a plurality of digital mirrors,
wherein in an imaging mode, the optical communication system is configured to perform hyperspectral imaging by setting all of the plurality of digital mirrors to positions that transmit all wavelengths of a communication band among the plural communication bands to the focusing grating;
a frequency presence modulation unit that includes the digital mirror array, the focusing grating, a grating, a focusing mirror, and a detector; and
a controller for providing a control signal to the frequency presence modulation unit to control the positions of the plurality of digital mirrors.

US Pat. No. 10,142,029

DEVICE FOR MODULATING THE INTENSITY OF AN OPTICAL SIGNAL ON FOUR DIFFERENT LEVELS

1. Device for modulating the intensity of an optical signal on four different levels, wherein the device comprises:a power divider comprising an input to receive an initial optical signal to be modulated and first and second outputs which each deliver, respectively, first and second optical signals to be modulated, the intensity of each of these first and second optical signals to be modulated being equal to a non-zero fraction of the intensity of the initial optical signal received on the input of the power divider,
a first resonant ring modulator comprising:
an input port optically coupled to the first output of the power divider to receive the first optical signal to be modulated,
a first output port configured to deliver a first intensity-modulated optical signal, constructed by modulating the intensity of the optical signal received on the input port between only a high level and a low level,
a control port configured to receive a first binary control signal in response to which the first resonant ring modulator varies the intensity of the first optical signal to be modulated between the high and low levels to obtain the first modulated optical signal,
a second output configured to deliver an optical signal complementary to the first modulated optical signal, the intensity of the complementary optical signal being at the low level when the intensity of the first modulated optical signal is at the high level and vice versa,
second resonant ring modulator comprising:
an input port optically coupled to the second output of the power divider to receive the second optical signal to be modulated,
an output port configured to deliver a second modulated optical signal constructed by modulating the intensity of the optical signal received on its input port between only a high level and a low level,
a control port configured to receive a second binary control signal in response to which the second resonant ring modulator varies the intensity of the optical signal received on its input port between the high and low levels to obtain the second modulated optical signal,
a first optical assembler comprising:
a first input optically coupled to one of the first and second output ports of the first resonant ring modulator to receive the first modulated optical signal,
a second input optically coupled to the output port of the second resonant ring resonator modulator to receive the second modulated optical signal, and
an output configured to generate a first combined optical signal constructed by combining optical signals received on the first and second inputs of the first optical assembler,
a second optical assembler comprising:
a first input optically coupled to the output port of the first optical assembler
a second input optically coupled to the other of the first and second output ports of the first resonant ring modulator, and
an output configured to deliver the optical signal of which the intensity is modulated on at most four different levels constructed by combining optical signals received on its first and second inputs.

US Pat. No. 10,142,028

SIGNALING METHOD FOR LEVERAGING POWER ATTENUATION IN A MANDREL-WRAPPED OPTICAL FIBER

Dell Products L.P., Roun...

11. A non-transitory computer readable medium comprising processor executable program instructions that, when executed by the processor, cause operations including:monitoring a parameter of an optical signal transmitted between two endpoints via an optical fiber;
modifying a diameter of a mandrel around which a portion of the optical fiber is wrapped to modulate the parameter wherein the mandrel comprises a high order mode filter (HOMF); and
identifying data in accordance with the modulation of the monitored parameter;
wherein the optical signal is transmitted from a first endpoint to a second endpoint and wherein the monitored parameter comprises a received power parameter indicative of an average power of the optical signal as received at the second endpoint.

US Pat. No. 10,142,027

COMMUNICATION DEVICE AND COMMUNICATION SYSTEM

Sony Corporation, Tokyo ...

1. A communication device comprising:a first terminal that outputs a power supply voltage;
a second terminal coupled directly or indirectly to the first terminal;
a communication section that operates on a basis of the power supply voltage to communicate with a communication peer;
a communication controller that sets the communication section to be in an ON state or in an OFF state on a basis of a voltage on the second terminal; and
a switch inserted between the first terminal and the second terminal, the switch being turned into an ON state to cause the second terminal to be coupled to the first terminal.

US Pat. No. 10,142,026

RAMAN PUMPING ARRANGEMENT WITH IMPROVED OSC SENSITIVITY

Xieon Networks S.a.r.l., ...

1. A Raman pumping arrangement for amplifying a data optical signal transmitted in a fiber optic transmission system comprising:a Raman pump for generating a Raman pump signal wherein the Raman pump signal is used for amplifying the data optical signal in the fiber optic transmission system;
an optical supervisory channel receiver for receiving an optical supervisory channel signal transmitted through the fiber optic transmission system and copropagating with the data optical signal;
an amplification fiber arranged such that the data optical signal, the optical supervisory channel signal, and the Raman pump signal are transmitted therethrough; and
a control unit functionally connected to the Raman pump and to the optical supervisory channel receiver, the control unit being configured for controlling the operation of the Raman pump;
wherein the control unit is configured for setting the Raman pump in
an operation mode, when the optical supervisory channel receiver receives the optical supervisory channel signal; or
a start-up mode, when the optical supervisory channel receiver does not receive the optical supervisory channel signal;
wherein in the operation mode, the Raman pump provides an operation pumping power, and wherein in the start-up mode, the Raman pump provides a start-up pumping power, the start-up pumping power being smaller than the operation pumping power, said start-up pumping power being suitable for pumping the amplification fiber.

US Pat. No. 10,142,025

HIGH-DIRECTIVITY DIRECTIONAL COUPLER, AND RELATED METHODS AND SYSTEMS

Corning Optical Communica...

1. A high-directivity directional coupler, comprising:a substrate;
a ground plane disposed underneath the substrate;
an input port configured to receive an input signal;
an output port configured to output the received input signal as an output signal;
a coupled port configured to output a coupled signal proportional to the input signal;
an isolated port configured to provide isolation to the input signal and the coupled signal;
a first microstrip disposed above the substrate, the first microstrip configured to convey the input signal from the input port to the output port; and
a second microstrip disposed above the substrate parallel to the first microstrip, the second microstrip configured to:
provide a linear forward path for conveying an even mode current from the coupled port to the ground plane; and
provide a non-linear return path longer than the linear forward path for conveying an odd mode current in an opposite direction from the even mode current.

US Pat. No. 10,142,024

HIGHER-LEVEL CLOCK AND DATA RECOVERY (CDR) IN PASSIVE OPTICAL NETWORKS (PONS)

Futurewei Technologies, I...

1. An apparatus comprising:an optical-to-electrical (OE) component configured to convert an optical signal with a first modulation format to an analog electrical signal;
an analog-to-digital converter (ADC) coupled to the OE component and configured to convert the analog electrical signal to a first digital signal; and
a clock and data recovery (CDR) sub-system coupled to the ADC and configured to:
equalize the first digital signal into a second digital signal with a second modulation format, the second modulation format having more levels than the first modulation format; and
perform CDR on the second digital signal.

US Pat. No. 10,142,023

ANTENNA SYSTEM AND METHODS FOR WIRELESS OPTICAL NETWORK TERMINATION

CenturyLink Intellectual ...

1. An optical network termination system comprising:an optical fiber in communication with an external telecommunications information network;
a processor in communication with the optical fiber and providing for the processing of telecommunications information conveyed over the optical fiber to or from the external telecommunications information network said processor being housed outside of a premises;
an electrically conductive internal transport medium in communication with the processor, wherein the electrically conductive internal transport medium provides for the bidirectional conveyance of a first subset of the telecommunications information from the processor into the premises;
a wireless internal transport medium comprising a wireless access point in communication with the processor and housed with the processor outside of the premises:
a distributed antenna in communication with the wireless access point, the distributed antenna comprising a feed line attached to one or more walls of the customer premises and one or more radiating elements extending from the feed line, wherein the wireless internal transport medium provides for the bidirectional wireless conveyance of a second subset of the telecommunication information from the one or more radiating elements into the premises;
a signal detection circuit in communication with the distributed antenna providing for the detection of a signal received by the one or more radiating elements and further providing for the disabling or enabling of selected radiating elements based upon detected signal strength;
a port terminating the electrically conductive internal transport medium within the premises;
a power supply configured to be connected to an AC outlet within the premises; and
a back-power cable providing for the transmission of power from the power supply to the wireless access point over the electrically conductive internal transport medium upon connection of the back-power cable to the port, wherein the power is provided, over the electrically conductive internal transport medium, to the selected radiating elements.

US Pat. No. 10,142,022

ADJUSTMENT OF CONTROL PARAMETERS OF SECTION OF OPTICAL FIBER NETWORK

Ciena Corporation, Hanov...

1. A method for adjustment of one or more control parameters of a section of an optical fiber network, the method comprising:taking measurements of optical signals in the section;
deriving estimated data from the measurements and from knowledge of the section, where the estimated data is a function of optical nonlinearity and of amplified spontaneous emission;
evaluating gradients of an objective function using the measurements and the estimated data; and
applying one or more control algorithms using at least the gradients to adjust the one or more control parameters.

US Pat. No. 10,142,021

SATELLITE SYSTEM USING OPTICAL GATEWAYS AND GROUND BASED BEAMFORMING

1. A ground based subsystem for use in transmitting an optical feeder uplink beam to a satellite that includes a multiple element antenna feed array and that is configured to receive the optical feeder uplink beam and in dependence thereon use the multiple element antenna feed array to produce and transmit a plurality of RF service downlink beams to service terminals, the ground based subsystem comprising:a ground based beamformer (GBBF) configured to accept a plurality of spot beam signals, produce or otherwise obtain phase and amplitude beamforming coefficients, and output a plurality of feed element signals in dependence on the plurality of spot beam signals and the phase and amplitude beamforming coefficients;
a plurality of lasers, each of the lasers operable to emit an optical signal having a different peak wavelength within a specified optical wavelength range;
a plurality of electro-optical modulators (EOMs), each EOM of the plurality of EOMs configured to accept an optical carrier signal from a respective one of the plurality of lasers, accept a different one of the plurality of feed element signals from the GBBF, and output a respective optical feed element signal in dependence on the optical carrier signal and the feed element signal accepted by the EOM;
a wavelength-division multiplexing (WDM) multiplexer configured to accept the optical feed element signals output by the plurality of EOMs, and combine the plurality of optical feed element signals into a wavelength division multiplexed optical signal;
an optical amplifier configured to amplify the wavelength division multiplexed optical signal to thereby produce an optically amplified wavelength division multiplexed optical signal; and
transmitter optics configured to accept the optically amplified wavelength division multiplexed optical signal and transmit an optical feeder uplink beam to the satellite in dependence thereon.

US Pat. No. 10,142,020

REPRODUCTION METHOD FOR REPRODUCING CONTENTS

PANASONIC INTELLECTUAL PR...

1. A reproduction method comprising:receiving a visible light signal from a sensor of a terminal device from a transmitter which transmits the visible light signal by a light source changing in luminance;
transmitting a request signal for requesting a content associated with the visible light signal from the terminal device to a server;
receiving from the server, with the terminal device, the content including time points and pieces of data, each of which corresponds to one of the time points, to be reproduced; and
reproducing one of the pieces of data among the pieces of data of the content with the terminal device,
wherein the terminal device synchronizes one of the time points, corresponding to the one of the pieces of reproduced data, with a terminal device time point indicated by a clock included in the terminal device.

US Pat. No. 10,142,019

END USER DEVICE AND ASSOCIATED METHOD FOR SELECTING VISIBLE LIGHT COMMUNICATION PERSONAL AREA NETWORK COORDINATOR

WIPRO LIMITED, Bangalore...

10. An End User Device (EUD) in a Light Fidelity (Li-Fi) network, the EUD comprising:a network interface communicatively coupled to a current Visible light communication Personal Area Network Coordinator (VPANC);
a processor; and
a memory communicatively coupled to the processor, wherein the memory stores processor instructions, which, on execution, causes the processor to:
receive a set of customized channel scan parameters and a VPANC selection policy from the current VPANC the EUD is associated with, wherein the set of customized channel scan parameters and the VPANC selection policy are created by the current VPANC,
wherein the set of customized channel scan parameters and the VPANC selection policy are created by the current VPANC based on one or more channel scan parameters and VPANC controlling parameters associated with neighboring VPANCs of the current VPANC and EUD information received from a plurality of EUDs associated with the current VPANC, and
wherein the one or more channel scan parameters comprises a range of frequencies, a channel scan duration, and a time interval between channel scans, and wherein the VPANC control parameters comprises number of the neighboring VPANCs of the current VPANC, list of the neighboring VPANCs, geo-location of dead zones near the current VPANC, and VPANC measurement reports associated with each neighboring VPANC;
assess quality of an active channel currently used by the EUD, wherein the active channel is associated with the current VPANC; and
switch to a new VPANC from a plurality of VPANCs based on the set of customized channel scan parameters and the VPANC selection policy in response to the assessing, wherein the plurality of VPANCs comprise the current VPANC.

US Pat. No. 10,142,018

VISIBLE LIGHT COMMUNICATION VIA SOLID STATE LIGHTING DEVICES

Cree, Inc., Durham, NC (...

1. A solid-state lighting fixture comprising:a first plurality of solid-state light elements configured to emit visible light at a first wavelength;
a second plurality of solid-state light elements configured to emit the visible light at a second wavelength, which is different than the first wavelength; and
a light controller modulator configured to simultaneously:
modulate the visible light emitted from the first plurality of solid-state light elements, to emit a modulation pattern of the emitted visible light that communicates a first subset of data while being undetectable to a human eye; and
modulate the visible light emitted from the second plurality of solid-state light elements, to emit the modulation pattern of the emitted visible light that communicates a second subset of data while being undetectable to the human eye.

US Pat. No. 10,142,017

BEACON DEMODULATION WITH BACKGROUND SUBTRACTION

X Development LLC, Mount...

1. A method comprising:collecting, at a receiver of a first communication device, a plurality of frames, each frame being an image of a location and having a resolution including a plurality of pixels, each pixel having a pixel value corresponding to a color;
determining, by one or more processors of the first communication device, a static background of the location by averaging the pixel values of the plurality of frames collected at the receiver;
determining, by the one or more processors, pixel difference values for each frame by subtracting the determined static background from the pixel values of each frame;
identifying, by the one or more processors, a first subset of frames and a second subset of frames using the pixel difference values for each frame in the plurality of frames;
determining, by the one or more processors, an average pixel difference by averaging the pixel difference values of the first subset of frames and an inverse of the pixel difference values of the second subset of frames; and
determining, by the one or more processors, a position of a beacon of a second communication device at the location using the average pixel difference in order to align the first communication device and the second communication device for a communication link.

US Pat. No. 10,142,014

MULTI-FUNCTION DEVICE AND TERMINAL DEVICE

Brother Kogyo Kabushiki K...

1. A multi-function device configured to perform at least one of a printing function and scanning function, the multi-function device comprising:a short-range wireless interface configured to perform wireless communication with a terminal device using a short-range wireless communication protocol, the short-range wireless interface operable in a peer-to-peer mode and another mode which is one of a reader/writer mode and a card emulation mode;
a Wi-Fi interface configured to perform wireless communication with the terminal device using a Wi-Fi-compliant communication protocol;
a processor; and
a memory storing computer-readable instructions therein, the computer-readable instruction, when executed by the processor, causing the multi-function device to perform:
receiving, over a short-range wireless connection via the short-range wireless interface in the peer-to-peer mode, request information from the terminal device for causing the multi-function device to perform the at least one of the printing function and the scanning function;
in a case where a first determination process for causing only a permitted user to perform the at least one of the print function and the scanning function is to be executed,
transmitting, via the short-range wireless interface in the peer-to-peer mode, first response information to the terminal device in response to the receiving of the request information, wherein the first response information causes the terminal device to transmit authentication information for performing the at least one of the printing function and the scanning function via the short-range wireless interface in the another mode;
terminating the short-range wireless connection to the terminal device in the peer-to-peer mode after transmitting the first response information to the terminal device;
reactivating the short-range wireless connection to the terminal device in the another mode after terminating the short-range wireless connection to the terminal device;
receiving from the terminal device, via the short-range wireless interface in the another mode, the authentication information for performing the at least one of the printing function and the scanning function;
executing the first determination process in which the multi-function device determines whether performing the at least one of the printing function and the scanning function is permitted or not by determining whether the authentication information is correct in response to the receiving the authentication information;
when determined, in the first determination process, that performing the at least one of the printing function and the scanning function is permitted by determining that the authentication information is correct, performing, via the short-range wireless interface in the another mode, communication of network information to be used to connect with the Wi-Fi interface, otherwise, when determined, in the first determination process, that performing the at least one of the printing function and the scanning function is not permitted by determining that the authentication information is incorrect, not performing the communication of the network information; and
when the network information has been communicated, performing wireless communication with the terminal device using the Wi-Fi interface and performing the at least one of the printing function and the scanning function; and
in a case where the first determination process for causing only a permitted user to perform the at least one of the print function and the scanning function is not to be executed,
terminating the short-range wireless connection to the terminal device in the peer-to-peer mode without transmitting the first response information to the terminal device;
performing via the short-range wireless interface, communication of network information to be used to connect with the Wi-Fi interface;
performing wireless communication with the terminal device using the Wi-Fi interface; and
performing the at least one of the print function and the scanning function.

US Pat. No. 10,142,013

METHOD OF OPTIMIZING AN INTERPLANETARY COMMUNICATIONS NETWORK

The Boeing Company, Chic...

1. A method of optimizing a communications network, said method comprising:providing an initial network configuration for an interplanetary communications network, said interplanetary communications network having a plurality (k) of nodes;
providing forecasts of traffic demand in said interplanetary communications network;
determining objective functions by a computer responsive to said demands and characterizing communications over links between said nodes in said network;
determining by said computer at least one limit for each said objective function;
adjusting said initial network configuration, and thereby producing an adjusted network configuration, responsive to said at least one limit for each said objective function; and
deploying said interplanetary communications network with said adjusted network configuration.

US Pat. No. 10,142,012

CO-ORBITING LASER COMMUNICATIONS RELAY SATELLITE

THE AEROSPACE CORPORATION...

1. A relay satellite for relaying data from a client satellite to thereby reduce power and pointing accuracy requirements of the client satellite, said relay satellite comprising:a short-range communications link configured to receive data from the client satellite; and
a long-range communications link configured to retransmit the received data to a ground station or another satellite,
wherein the relay satellite is deployed in one of (a) a quasi-orbit with respect to the client satellite such that the relay satellite and the client satellite can be kept within a pre-determined distance or (b) the same orbit as the client satellite but with an in-track offset that keeps the relay satellite and the client satellite within a pre-determined distance;
wherein the short-range communications link can be used to receive data from the client satellite when the client satellite is within a pre-determined distance of the relay satellite;
wherein the relay satellite is deployable from the client satellite after the client satellite reaches orbit.

US Pat. No. 10,142,010

REPEATER AND METHODS FOR USE THEREWITH

1. A repeater device, comprising:an amplifier configured to amplify first channel signals to generate amplified first channel signals, wherein the first channel signals are extracted via a first coupler from a first transmission medium of a distributed antenna system as first guided electromagnetic waves, wherein the first guided electromagnetic waves propagate along the first transmission medium without requiring an electrical return path;
a channel selection filter configured to select one or more of the amplified first channel signals for wireless transmission to at least one device via a first antenna of the distributed antenna system; and
a channel duplexer configured to transfer to the distributed antenna system via a second coupler, at least a portion of the amplified first channel signals for use by an other repeater device of the distributed antenna system having a second antenna and further to transfer the first channel signals to the channel selection filter, wherein the second coupler launches second guided electromagnetic waves conveying the amplified first channel signals on a second transmission medium of the distributed antenna system and wherein the second guided electromagnetic waves propagate along the second transmission medium without requiring an electrical return path.

US Pat. No. 10,142,009

INTERFACE MODULE FOR A UNIT OF AN ANTENNA DISTRIBUTION SYSTEM, AND ANTENNA DISTRIBUTION SYSTEM

Andrew Wireless Systems G...

1. A distributed antenna system comprising:at least one master unit communicatively coupled to at least one base station; and
a plurality of remote units located remotely from the at least one master unit, wherein each of the plurality of remote units is communicatively coupled to the master unit over at least one transport communication link;
the system configured to distribute a first signal, received from the at least one base station, from the master unit to at least one remote unit in analog form, wherein the at least one remote unit radiates a second signal derived from the first signal from at least one antenna associated with the at least one remote unit;
a digital circuit configured to generate digital samples by digitally sampling the first signal;
a network interface for communicating with an external central control computer configured for central control of the distributed antenna system, wherein the external central control computer is distinct from the at least one base station;
the digital circuit configured to process the digital samples and communicate information about parameters of the first signal to the external central control computer via the network interface.

US Pat. No. 10,142,008

DATA COMPRESSION FOR WIRELESS RELAYS IN A DATA COMMUNICATION NETWORK

Sprint Communications Com...

1. A method of operating a wireless relay to serve User Equipment (UE) over a Radio Area Network (RAN) and a Wide Area Network (WAN), the method comprising:an evolved Node B (eNodeB) performing Tunneling Compression Multiplexing (TCM) on S1-MME signaling data and X2 signaling data and exchanging the compressed S1-MME signaling data and the compressed X2 signaling data with a data switch;
the eNodeB wirelessly exchanging user data with the UE and exchanging the user data with a Local Gateway (L-GW);
the L-GW separating the user data into RAN user data and WAN user data, performing TCM on the RAN user data, the WAN user data, and S11 signaling data, and exchanging the compressed RAN user data, the compressed WAN user data, and the compressed S11 signaling data with the data switch;
the data switch exchanging the compressed RAN user data, the S1-MME signaling data, the compressed X2 signaling data, and the compressed S11 signaling data with a Relay Equipment (RE) and exchanging the compressed WAN user data with an Internet Protocol Security (IPSec) agent;
the RE performing Robust Header Compression over Long Term Evolution (ROHCoLTE) for a RAN data tunnel and wirelessly exchanging the compressed RAN user data, the compressed S1-MME signaling data, the compressed X2 signaling data, and the compressed S11 signaling data over the compressed RAN data tunnel; and
the IPSec agent performing Robust Header Compression over IPSec (ROHCoIPSec) for a compressed WAN data tunnel and exchanging the compressed WAN user data over the compressed WAN data tunnel.

US Pat. No. 10,142,007

RADIO COMMUNICATION DEVICES AND METHODS FOR CONTROLLING A RADIO COMMUNICATION DEVICE

Intel Deutschland GmbH, ...

25. A radio communication device comprising:an antenna configured to operate in an operation mode of a plurality of operation modes that are respective radiation patterns;
a transmitter configured to transmit data using the antenna;
an evaluation circuit configured to evaluate a plurality of operation modes of the antenna in a plurality of cells;
a mode switching circuit configured to switch the operation mode of the antenna at least if the transmitter fulfils a predetermined transmitter criterion,
wherein the predetermined transmitter criterion is an indication of non-urgent uplink data;
a selection circuit configured to select the operation mode of the antenna based on a further predetermined criterion, wherein the further predetermined criterion is a highest acknowledgement rate of the plurality of operation modes evaluated by the evaluation circuit;
a memory configured to temporarily store the non-urgent uplink data until the selection circuit selects the operation mode of the antenna.

US Pat. No. 10,142,006

AMPLITUDE AND PHASE CALIBRATION AT A RECEIVER CHIP IN AN ANTENNA ARRAY

MOVANDI CORPORATION, New...

1. A system, comprising:an antenna array;
a receiver chip; and
one or more circuits in the receiver chip, wherein the one or more circuits are programmed with instructions to:
receive via a plurality of duplex filters, a plurality of receive signals at a plurality of receive paths, wherein the plurality of receive paths are associated with a plurality of antenna elements of the antenna array;
select, from the plurality of receive paths within the receiver chip, a first receive path for a first receive signal and a second receive path for a second receive signal;
adjust a first signal parameter of the second receive signal relative to the first signal parameter of the first receive signal so that one of a first signal strength value of an added signal is maximized, or a second signal strength value of a subtracted signal is minimized;
calibrate an offset of the first signal parameter based on the adjusted first signal parameter in the second receive path; and
independently activate the first receive path and the second receive path, and adjust a value of a second signal parameter so that the second signal parameter in the second receive path matches the second signal parameter in the first receive path.

US Pat. No. 10,142,005

BEAMFORMING TRAINING

LG ELECTRONICS INC., Seo...

1. A method for performing beamforming training in a wireless local area network (WLAN), the method performed by a responding device including a processor, a transceiver, a first array antenna and second array antenna, the method comprising:receiving a plurality of beacon frames from an initiating device through a plurality of sectors during a transmission (TX) beamforming (BF) interval,
wherein the plurality of sectors correspond to a plurality of transmit antenna patterns for the initiating device;
transmitting a first sector sweep feedback to the initiating device during a reception (RX) BF interval,
wherein the first sector sweep feedback includes a first antenna identifier (ID) indicating the first array antenna and a first TX ID indicating a first TX sector determined by the responding device for the first array antenna based on the plurality of beacon frames;
determining whether a first sector sweep acknowledgement (ACK) is received from the initiating device in response to the first sector sweep feedback; and
transmitting a second sector sweep feedback including a redundant feedback to the initiating device during the RX BF interval if the first sector sweep ACK is not received,
wherein the second sector sweep feedback includes a second antenna ID indicating the second array antenna and a second TX ID indicating a second TX sector determined by the responding device for the second array antenna based on the plurality of beacon frames, and
wherein the redundant feedback includes a third antenna ID indicating the first array antenna and a third TX ID indicating the first TX sector.

US Pat. No. 10,142,003

PRECODING INFORMATION OBTAINING APPARATUS, METHOD, AND SYSTEM

Huawei Technologies Co., ...

1. A precoding information obtaining method, comprising:determining a transformation matrix according to a steering vector of an antenna form and a departure-angle range;
sending information about the transformation matrix to a terminal for determining a precoding matrix indicator (PMI) according to the information about the transformation matrix, a codebook for obtaining channel information, and a pilot measurement result, wherein sending the information about the transformation matrix comprises:
sending a system information block to the terminal, wherein the system information block comprises the information about the transformation matrix, wherein the system information block comprises:
a horizontal transformation matrix indicator for indicating whether the transformation matrix is in a horizontal direction,
a horizontal transformation matrix dimension for indicating a dimension of the transformation matrix in the horizontal direction,
a horizontal transformation matrix nonzero quantity for indicating a quantity of nonzero elements of the transformation matrix in the horizontal direction, and
a horizontal transformation matrix element for indicating a value of the nonzero element of the transformation matrix in the horizontal direction; and
receiving the PMI reported by the terminal.

US Pat. No. 10,142,002

METHOD OF HANDLING MULTIUSER CQI FOR MU-MIMO AND RELATED COMMUNICATION DEVICE

Industrial Technology Res...

1. A method of handling at least one multiuser channel quality indicator (MU-CQI) set for a communication device, the method being utilized in a communication device and comprising:being indicated at least one companion precoding matrix index (PMI) set by a network via receiving information of the at least one companion PMI set from the network, wherein the at least one companion PMI set is determined by the network rather than the communication device, and the information of the at least one companion PMI set is transmitted by the network;
determining at least one MU-CQI set according to the at least one companion PMI set, respectively, wherein each MU-CQI of each MU-CQI set of the at least one MU-CQI set corresponds to each companion PMI of each companion PMI set of the at least one companion PMI set;
receiving a plurality of PMI sets via a higher layer signaling transmitted by the network:
selecting the at least one companion PMI set from the plurality of PMI sets according to the information: and
transmitting the at least one MU-CQI set to the network aperiodically.

US Pat. No. 10,142,001

METHOD AND SYSTEM FOR HYBRID RADIO FREQUENCY DIGITAL BEAMFORMING

Maxlinear, Inc., Carlsba...

1. An electronic device, the device comprising:one or more circuits coupled to an antenna array comprising antennas arranged along first and second directions, said one or more circuits being operable to:
beamform signals in an analog domain along the first direction of the antenna array; and
beamform signals in a digital domain along the second direction of the antenna array, with wider beam steering in the second direction as compared to narrower beam steering in the first direction.

US Pat. No. 10,142,000

ANTENNA APPARATUS

Mitsubishi Electric Corpo...

1. An antenna apparatus comprising:a plurality of sub-arrays (2-n: n=1, . . . , N) each of which is constituted by a plurality of element antennas (3-k: k=1, . . . , K);
a terminal position detector (32) to detect positions of a plurality of user terminals being communication objects;
a sub-array number determinator (41) to determine a number of sub-arrays to be allocated to each of the plurality of user terminals detected by the terminal position detector (32) on a basis of relation between the positions of the plurality of user terminals and a position of the antenna apparatus; and
an antenna selector (50) to select sub-arrays for the number determined by the sub-array number determinator (41) from among the plurality of sub-arrays (2-n) and allocate the selected sub-arrays for the determined number to each of the plurality of user terminals.

US Pat. No. 10,141,999

REFERENCE SIGNAL TRACKING IN A WIRELESS COMMUNICATION SYSTEM

TELEFONAKTIEBOLAGET LM ER...

1. A method performed by network equipment in a wireless communication system, the method comprising:transmitting a tracking process base signal to a wireless device;
responsive to receiving a report from the wireless device indicating reception of the tracking process base signal, configuring the wireless device with a tracking process for the wireless device to track a reference type signal by tuning a receiver configuration with which the wireless device received the tracking process base signal; and
transmitting a reference signal to the wireless device and identifying to the wireless device that the reference signal is to be tracked with the configured tracking process.

US Pat. No. 10,141,998

UTILIZATION OF ANTENNA BEAM INFORMATION

TELEFONAKTIEBOLAGET LM ER...

1. A method for utilizing antenna beam information, the method comprising a network node:acquiring antenna beam information indicative of a direction of a wireless device (WD) specific beam of the network node;
classifying the acquired antenna beam information into a cell-specific beam category based on an angular difference between the direction of the WD-specific beam and a direction of main lobe of a cell-specific beam of the network node; and
performing at least one of a load balancing action of the WD and a radiation beam pattern change related to the cell-specific beam category.

US Pat. No. 10,141,997

POWER AMPLIFIER ADJUSTMENT FOR TRANSMIT BEAMFORMING IN MULTI-ANTENNA WIRELESS SYSTEMS

Marvell World Trade Ltd.,...

1. A method, comprising:applying, at one or more integrated circuits, one or more beamsteering matrices to one or more signals to produce a plurality of signals to be transmitted via multiple antennas;
after applying the one or more beamsteering matrices to the one or more signals, providing the plurality of signals to a plurality of power amplifiers coupled to the multiple antennas;
determining, at the one or more integrated circuits, signal energies for the plurality of signals provided to the plurality of power amplifiers;
determining, at the one or more integrated circuits, a highest signal energy among the determined signal energies;
determining, at the one or more integrated circuits, respective measures of relative signal energies corresponding to one or more other signal energies among the determined signal energies relative to the determined highest signal energy; and
adjusting, based on the determined respective measures of relative signal energies, output power levels of the plurality of power amplifiers to make the output power levels of the plurality of power amplifiers equal.

US Pat. No. 10,141,994

TECHNIQUE FOR REDUCING RESPONDING SECTOR SWEEP TIME FOR MILLIMETER-WAVE DEVICES

QUALCOMM Incorporated, S...

1. An apparatus for wireless communications, comprising:a first interface for obtaining first frames from a wireless node during a sector sweep procedure;
a processing system configured to generate feedback regarding a transmit beamforming sector associated with one of the first frames, based on received signal qualities of the first frames as observed at the apparatus, and to generate second frames including the feedback, wherein the first frames have a first frame format and the second frames have a second frame format that is different from the first frame format; and
a second interface configured to output the second frames for transmission to the wireless node, wherein the second frame format has a frame control field having fewer bits than a frame control field of the first frame format.

US Pat. No. 10,141,993

MODULAR ANTENNA ARRAY BEAM FORMING

Intel Corporation, Santa...

1. A radio communication device comprising:a plurality of antenna arrays each configured to generate a steerable antenna beam according to a respective beamforming codeword, wherein each of the plurality of antenna arrays is configured to obtain the respective beamforming codeword from a single-antenna-array steering codebook that is common to each of the plurality of antenna arrays; and
a beamforming circuit configured to weight signals for the plurality of antenna arrays to coordinate the steerable antenna beams from a subset of the plurality of antenna arrays independently of the respective beamforming codewords assigned to the plurality of antenna arrays to form a combined antenna beam in a first steering direction.

US Pat. No. 10,141,992

CODEBOOK DESIGN AND STRUCTURE FOR ADVANCED WIRELESS COMMUNICATION SYSTEMS

Samsung Electronics Co., ...

1. A user equipment (UE) capable of communicating with a base station (BS), the UE comprising:a transceiver configured to:
receive, from the BS, downlink signals including precoding matrix indicator (PMI) codebook parameters comprising:
first and second quantities of antenna ports, N1 and N2, indicating respective quantities of antenna ports in first and second dimensions of a dual-polarized antenna array at the BS,
first and second oversampling factors, O1 and O2, indicating respective oversampling factors for Discrete Fourier Transform (DFT) beams in the first and second dimensions, and
a beam group configuration among a plurality of beam group configurations; and
a controller configured to:
determine a plurality of PMIs using a PMI codebook corresponding to the received PMI codebook parameters, wherein the plurality of PMIs comprises a first PMI (i1) indicating a plurality of DFT beams in a beam group, and a second PMI (i2) indicating one beam selection out of the plurality DFT beams and a co-phase value selection for the two polarizations of the antenna array the BS, and
cause the transceiver to transmit uplink signals containing the plurality of PMIs to the BS.

US Pat. No. 10,141,991

ADAPTIVE CODEWORD AND CODEBLOCK SELECTION IN WIRELESS COMMUNICATIONS

QUALCOMM Incorporated, S...

1. A method for wireless communication, comprising:identifying, for a carrier supporting a plurality of service types, resources for a first multiple-input multiple-output (MIMO) transmission;
identifying a first service type associated with the first MIMO transmission;
determining a first number of codewords to be received in the first MIMO transmission based at least in part on the first service type;
receiving the first MIMO transmission; and
decoding one or more codewords received in the first MIMO transmission, the one or more codewords corresponding to the first number of codewords.

US Pat. No. 10,141,990

METHOD FOR DETERMINING PRECODING MATRIX INDICATOR, USER EQUIPMENT, AND BASE STATION

HUAWEI TECHNOLOGIES CO., ...

1. A method for determining a precoding matrix indicator, comprising:receiving a first reference signal set sent by a base station, wherein the first reference signal set is associated with a user equipment-specific matrix set that includes at least two matrices;
selecting a precoding matrix based on the first reference signal set, wherein the precoding matrix w is a product of two matrices W1 and W2, wherein W=W1W2;
wherein the matrix W1 is a block diagonal matrix that comprises at least two block matrices, each block matrix X is a function of matrix A in the user equipment-specific matrix set or matrix B in the user equipment-specific matrix set, wherein the Matrix W2 is used for selection or weighted combination of column vectors in the matrix W1, wherein the precoding matrix w has the following matrix structure:

wherein []T is a matrix transpose, both M and N are positive integers, and ?, ? and ? are phase shifts; and
sending a precoding matrix indicator (PMI) to the base station, wherein the PMI corresponds to the selected precoding matrix.

US Pat. No. 10,141,989

SYSTEM AND METHOD FOR QUANTIZATION OF ANGLES FOR BEAMFORMING FEEDBACK

Huawei Technologies Co., ...

1. A method for beamforming feedback comprising:receiving a sounding packet for a beamforming transmission;
performing planar rotation in accordance with the sounding packet to generate phi and psi angle values;
quantizing the phi and psi angle values such that a quantized resolution of the phi angle value is different from a quantized resolution of the psi angle value; and
feeding back the quantized phi and psi angle values.

US Pat. No. 10,141,988

METHOD AND FIRST RADIO NODE FOR COMMUNICATING DATA USING PRECODERS

Telefonaktiebolaget LM Er...

1. A method performed by a first radio node for communicating data with a second radio node in a wireless network, the method comprising:communicating, with the second radio node, a first data transmission using a first set of precoders;
communicating, with the second radio node, a precoder indicator that is based on quality of the communicated first data transmission;
identifying a second set of precoders within the first set, based on the communicated precoder indicator; and
communicating, with the second radio node, a second data transmission using the second set of precoders.

US Pat. No. 10,141,987

METHOD FOR FEEDING BACK REFERENCE SIGNAL INFORMATION IN MULTI-ANTENNA WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR

LG ELECTRONICS INC., Seo...

1. A method for feeding back reference signal information by a user equipment (UE) in wireless communication using a two-dimensional active antenna system (2D-AAS) including multiple antennas, the method comprising:receiving, from a base station (BS), a reference signal configuration including identifiers (IDs) of a plurality of reference signals included in a first reference signal set and a second reference signal set;
receiving, from the BS, the plurality of reference signals, where a plurality of precoding is applied respectively;
determining a reference signal that is not successfully received based on the reference signal configuration;
measuring reference signal received power (RSRP) for each of the plurality of reference signals; and
transmitting, to the BS, information on at least part of the first reference signal set and information on at least part of the second reference signal set based on the measured RSRP, and an ID of the determined reference signal, which is not successfully received,
wherein precoding for the UE is determined based on the information on the at least part of the first reference signal set, and
wherein interference information on the UE is determined based on the information on the at least part of the second reference signal set.

US Pat. No. 10,141,986

METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING SIGNAL THROUGH BEAMFORMING IN COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A signal transmission and reception method of a terminal of a mobile communication system, the method comprising:receiving, from a base station, first information including a request associated with a beam of the terminal;
transmitting, to the base station, second information associated with the beam in response to the first information;
identifying at least one of a transmitting (Tx) beam or a receiving (Rx) beam of the terminal associated with the base station based on the first information and the second information; and
applying the identified at least one of the Tx beam or the Rx beam in response to the receiving of the first information or in response to the transmitting of the second information.

US Pat. No. 10,141,985

DETERMINING ACTUAL LOOP GAIN IN A DISTRIBUTED ANTENNA SYSTEM (DAS)

Corning Optical Communica...

1. A method for measuring actual loop gain in a wireless distribution system, comprising:disconnecting a downlink path into a first contact point and a second contact point;
providing at least one test signal having a first power level from the first contact point to at least one remote antenna unit (RAU) on the downlink path;
receiving at least one loopback test signal having a second power level from the second contact point;
determining a difference between the first power level of the at least one test signal at the first contact point and the second power level of the at least one loopback test signal at the second contact point;
determining an actual loop gain of the wireless distribution system based on the determined difference between the first power level and the second power level; and
recording the actual loop gain of the wireless distribution system in at least one storage medium.

US Pat. No. 10,141,984

MULTI-BAND TRANSMISSION SYSTEM

Marvell World Trade Ltd.,...

1. A system, comprising:a transmitter device configured to separate data into a plurality of frequency bands, wherein
each frequency band has an associated symbol time,
each associated symbol time is a whole multiple of one half of a smallest symbol time of all of the frequency bands to facilitate synchronized transmission of symbols over the plurality of frequency bands, and
the transmitter device includes:
i) a multiple input, multiple output (MIMO) processing block configured to multiplex the data into a plurality of spatial channels, and
ii) an analog front end configured to, for each spatial channel of the plurality of spatial channels,
combine data in the plurality of frequency bands, including combining data in a first frequency band with data in a second frequency band different from the first frequency band, into a respective combined signal for simultaneous transmission over the plurality of frequency bands, and
transmit the combined signal via a transmission medium, wherein transmission of symbols in the first frequency band is synchronized with transmission of symbols in the second frequency band.

US Pat. No. 10,141,983

METHOD FOR ACTIVATING PSCELL AND SCELL IN MOBILE COMMUNICATION SYSTEM SUPPORTING DUAL CONNECTIVITY

Samsung Electronics Co., ...

1. A method of a user equipment (UE), the method comprising:receiving, from a first base station, a first message for requesting UE capability information; and
transmitting, to the first base station, a second message including the UE capability information, the UE capability information including information on band combinations supported by the UE and information on each of at least one band combination among the band combinations including first information indicating that the UE supports a dual connectivity for each of the at least one band combination,
wherein the at least one band combination is used to configure a cell associated with a second base station and a cell associated with the first base station for the UE, and
wherein the first information includes second information indicating that the UE supports asynchronous dual connectivity.

US Pat. No. 10,141,982

RFID PROTOCOLS WITH NON-INTERACTING VARIANTS

RUIZHANG TECHNOLOGY LIMIT...

1. A method for operating an RFID reader, the method comprising:transmitting to a tag, a query command from a reader that is configured to store a first pair of keys including a first key and a second key, wherein the tag is configured to store a second pair of keys including a third key and a fourth key, and wherein the first pair of keys and the second pair of keys are used to create a sub-selection of a population of readers and tags;
transmitting to the tag, the first key from the reader;
receiving a first value from the tag if the first key from the reader matches the third key stored in the tag;
encrypting the first value using the second key stored in the reader to obtain a second value;
transmitting the second value to the tag that is configured to decrypt the second value using the fourth key to derive a challenge value;
receiving an identifier from the tag if a comparison of the first value to the challenge value indicates that the first value matches the challenge value.

US Pat. No. 10,141,981

METHODS AND APPARATUS FOR DETERMINING NEARFIELD LOCALIZATION USING PHASE AND RSSI DELIVERY

Texas Instruments Incorpo...

1. A receiver comprising:a receiver antenna to:
receive an electromagnetic signal; and
break the electromagnetic signal into an electric field signal and a magnetic field signal;
at least one processor coupled to the receiver antenna; and
a non-transitory computer readable storage medium storing a program for execution by the at least one processor, the program including instructions to:
determine an electric RSSI value of the electric field signal;
determine a magnetic RSSI value of the magnetic field signal;
determine an RSSI difference between the electric RSSI value and the magnetic RSSI value; and
determine a transmitter distance based on the RSSI difference.

US Pat. No. 10,141,980

WIRELESS POWER TRANSMISSION SYSTEM, AND COMMUNICATION AND PROTECTION METHODS FOR THE SAME

MINEBEA MITSUMI INC., Na...

1. A wireless power transmission system comprising a power supply device and a power receiving device,the power supply device comprising:
a power supply coil wirelessly transmitting electric power;
an inverter driving the power supply coil;
a first radio unit performing radio communication with the power receiving device; and
a first processor controlling the first radio unit and the inverter, and
the power receiving device comprising:
a resonant circuit including a power receiving coil wirelessly receiving electric power from the power supply coil of the power supply device and a capacitor to generate a resonant voltage;
a rectifying circuit rectifying the resonant voltage to output a rectified voltage;
a second radio unit performing radio communication with the first radio unit included in the power supply device; and
a second processor controlling the second radio unit,
wherein the second processor transmits a communication packet to the power supply device in a predetermined period of time, the communication packet including information about a rectified voltage value generated based on the rectified voltage and a circulation index value indicating transmission sequence and
the first processor outputs a signal according to the rectified voltage value included in the communication packet every time the first processor receives the communication packet without delay.

US Pat. No. 10,141,979

APPARATUS AND METHOD FOR USING NEAR FIELD COMMUNICATION AND WIRELESS POWER TRANSMISSION

Samsung Electronics Co., ...

1. A power receiving apparatus comprising:a resonator configured to receive a power and to output the power;
a near field communication (NFC) transceiver configured to perform wireless communication using the power output by the resonator;
a wireless power transmission (WPT) receiver configured to supply a voltage using the power output by the resonator;
a connecting unit configured to selectively connect the resonator to either the NFC transceiver or the WPT receiver;
a mode selector configured to control the connecting unit to selectively connect the resonator to either the NFC transceiver or the WPT receiver based on the power output by the resonator; and
an antenna/matching circuit configured to be connected to the NFC transceiver,
wherein the NFC transceiver transmits transmission (TX) data to the antenna/matching circuit and receives reception (RX) data from the antenna/matching circuit.

US Pat. No. 10,141,978

DATA ENCODER FOR POWER LINE COMMUNICATIONS

TEXAS INSTRUMENTS INCORPO...

1. A power line communication (PLC) transmitter comprising:a forward error correction (FEC) encoder to receive a physical layer (PHY) frame containing payload data and to create an encoded output of FEC code words;
a fragmenter to receive an FEC code word block that includes two or more of the FEC code words and to partition the FEC code word block into fragments;
a fragment repetition encoder to receive the fragments and to copy each of the fragments a selected number of times; and
an interleaver to receive the copies of fragments and to interleave the copies of the plurality of fragments for transmission on a power line.

US Pat. No. 10,141,977

SPECIAL OPERATIONS CHANNEL IN VECTORED SYSTEMS

Lantiq Deutschland GmbH, ...

1. A method, comprising:assigning an identification to each line associated with a provider equipment; and
transmitting a special operation channel (SOC) signal over at least one of the lines, wherein SOC symbols of the SOC signal transmitted over each of the at least one of the lines are modified by the identification of that line.

US Pat. No. 10,141,976

CROSSTALK MITIGATION

1. A method, comprising:estimating crosstalk from at least one first communication line not operating according to a vector standard to at least one second communication line operating according to a vector standard;
wherein estimating crosstalk comprises transmitting a probe signal from a central office device on the at least one first communication line, wherein communication via the at least one first communication line is a multitone communication; wherein transmitting the probe signal comprises transmitting a predetermined data sequence modulated on a predefined set of tones of a multitone modulation;
adapting a vectoring based on the estimated crosstalk; and
in order to prevent data communication on the predefined set of tones, at least one of: adding artificial noise to the tones of the predefined set of tones, excluding the predefined set of tones from a supported set of tones, excluding the tones of the predefined set of tones by a mask parameter, and excluding the predefined set of tones from communication by modifying a communication device coupled to the at least one first communication line.

US Pat. No. 10,141,975

METHOD AND APPARATUS FOR COMMUNICATING NETWORK MANAGEMENT TRAFFIC OVER A NETWORK

1. A first waveguide system comprising:a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, the operations comprising:
receiving network management data associated with a communication device; and
transmitting, to a second waveguide system, first electromagnetic waves to a physical interface of a transmission medium that propagate along an outer surface of the transmission medium without requiring an electrical return path, wherein the first electromagnetic waves are guided by the transmission medium, wherein the first electromagnetic waves convey the network management data without conveying data traffic associated with the communication device, and wherein the transmitting the first electromagnetic waves is over a virtual private network connection associated with the communication device and is responsive to a request from a management server for an out of band link with the communication device.

US Pat. No. 10,141,974

HIGH-CAPACITY FHSS-MA DEVICES AND METHODS

Shai Waxman, Sunnyvale, ...

1. A Frequency Hopped Spread Spectrum (FHSS) signals wireless receiver apparatus comprising:an antenna that receives a FHSS-MA signal comprising multiple FHSS signals, and
a radio frequency (RF) synthesizer that generates a synthesized radio frequency, and
a RF downconverter that down-converts the FHSS-MA signal using the synthesized radio frequency to an intermediate frequency (IF) signal, and
at least one wide band select filter with bandwidth greater-than at least 5 times the bandwidth of each of the FHSS signals, that filters the IF signal to reject out-of-band interference and outputs a filtered signal, and
at least one analog to digital converter that converts the filtered signal to a digitized signal, and
a I/Q imbalance correction circuit that inputs the digitized signal and outputs an array of multiple FHSS intermediate frequency (IF) I and Q signals, using an array of coefficients dynamically selected from a pre-populated coefficients memory as a function of the FHSS signals' center frequencies.

US Pat. No. 10,141,973

ENDPOINT PROXIMITY PAIRING USING ACOUSTIC SPREAD SPECTRUM TOKEN EXCHANGE AND RANGING INFORMATION

Cisco Technology, Inc., ...

16. A method comprising:at a first endpoint device: generating an acoustic spread spectrum signal including a pilot sequence and a spread data sequence synchronized with the pilot sequence, wherein the spread data sequence encodes a token and a future transmit time at which the acoustic spread spectrum signal will be transmitted; and transmitting the acoustic spread spectrum signal at the future transmit time;
at a second endpoint device: receiving the acoustic spread spectrum signal; determining from the received acoustic spread spectrum signal a receive time, a second token corresponding to the token, and the future transmit time; computing a separation distance between the first endpoint device and the second endpoint device based on a difference between the receive time and the future transmit time; and sending to the network the second token and the computed separation distance;
receiving from the second endpoint device over the network the second token and the computed separation distance; and
pairing the first endpoint device with the second endpoint device when the second token matches the token and the computed separation distance is less than a threshold distance.

US Pat. No. 10,141,972

TOUCH SCREEN CONTROLLER FOR INCREASING DATA PROCESSING SPEED AND TOUCH SYSTEM INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A touch screen controller (TSC) comprising:a front end circuit configured to send a control signal to a touch panel and to receive a touch signal from the touch panel;
an algorithm processing circuit configured to process source data generated based on the touch signal according to a predetermined algorithm;
a memory configured to store the source data and result data obtained as a result of processing the source data at the algorithm processing circuit; and
a bus configured to transfer data among the front end circuit, the algorithm processing circuit, and the memory,
wherein the algorithm processing circuit comprises:
a buffer configured to temporarily store the source data or the result data and shared by at least two circuits; and
a special function register (SFR) configured to store a setting value necessary for an operation of the algorithm processing circuit,
wherein the buffer comprises a source buffer configured to store the source data; and
wherein the algorithm processing circuit is configured to continuously read the source data from the memory during a plurality of cycles of an operating clock signal in a burst mode or a continuous single mode, and to store the source data in the source buffer.

US Pat. No. 10,141,971

TRANSCEIVER CIRCUIT HAVING A SINGLE IMPEDANCE MATCHING NETWORK

Silicon Laboratories Inc....

1. A transceiver circuit, comprising:a first amplifier coupled to receive signals from an antenna during a receive (RX) mode of the transceiver circuit;
a second amplifier coupled to transmit signals to the antenna during a transmit (TX) mode of the transceiver circuit, wherein the first and second amplifiers are directly connected to a shared node;
a single impedance matching network coupled to the antenna, directly connected to the shared node, and configured to transform an impedance of the antenna into a resistance at the shared node, wherein the single impedance matching network comprises a multiple stage inductor-capacitor (LC) network including at least a first stage and a second stage cascaded with the first stage, wherein the first stage and the second stage each comprise at least one variable capacitor having a capacitance that is reconfigurable; and
a control circuit coupled to the single impedance matching network, and configured to control the capacitance of the variable capacitors included within the first and second stages to provide a first resistance at the shared node during RX mode and a second resistance at the shared node during TX mode:
wherein the first resistance is a resistance at an input of the first amplifier that achieves a maximum voltage gain at the input of the first amplifier;
wherein the second resistance is a resistance at an output of the second amplifier that achieves a maximum output power at the output of the second amplifier; and
wherein the second resistance is different from the first resistance.

US Pat. No. 10,141,970

TRANSCEIVER CIRCUIT AND METHODS FOR TUNING A COMMUNICATION SYSTEM AND FOR COMMUNICATION BETWEEN TRANSCEIVERS

ams AG, Unterpremstaette...

1. A transceiver circuit with a front-end and a back-end, the front-end comprising:a first terminal and a second terminal for coupling to a first capacitor and to a second capacitor, respectively;
a tunable first resistor coupled between the first terminal and a reference terminal; and
a tunable second resistor coupled between the second terminal and the reference terminal,
wherein the front-end is configured to, during a tuning mode of operation,
receive receiver signals at the first and the second terminal utilizing a first setting for the first and the second resistor, and
generate a receiver data packet based on the receiver signals, wherein the back-end is configured to, during the tuning mode,
check the receiver data packet for errors with respect to a defined tuning data packet,
if an error is found with the checking, set the first and the second resistor to a default setting, and
if no error is found with the checking, set the first and the second resistor to a second setting,
wherein the tuning mode of operation is separate from a normal mode of operation for the transceiver circuit, and
wherein, during the tuning mode of operation, the first resistor and the second resistor are set to the default setting or to the second setting for operating the transceiver circuit in the normal mode of operation.

US Pat. No. 10,141,969

MOBILE ELECTRONIC DEVICE PROTECTION CASE

1. A mobile electronic device protection case comprising:a plurality of corner protectors;
each of the plurality of corner protectors comprising a first clip support, a second clip support, a lateral support, and a protective coating;
the first clip support and the second clip support each comprise a first securing arm, a second securing arm and a clip base;
the first securing arm being adjacently connected to the clip base;
the second securing arm being adjacently connected to the clip base;
the first securing arm being oppositely positioned to the second securing arm along the clip base;
the clip base of the first clip support being adjacently connected to the lateral support;
the clip base of the second clip support being adjacently connected to the lateral support;
the clip base of the first clip support being oppositely positioned to the clip base of the second clip support about the lateral support;
the protective coating being superimposed on the first clip support, the second clip support, and the lateral support;
a plurality of supporting struts;
each of the plurality of corner protectors being connected to another corner protector of the plurality of corner protectors through a supporting strut of the plurality of supporting struts;
a plurality of elastic strut ties;
each supporting strut of the plurality of supporting struts comprising a first strut portion and a second strut portion; and
the first strut portion being connected to the second strut portion through an elastic strut tie of the plurality of elastic strut ties.

US Pat. No. 10,141,968

DEVICE FOR REFLECTING, DEFLECTING, AND/OR ABSORBING ELECTROMAGENTIC RADIATION EMITTED FROM AN ELECTRONIC DEVICE AND METHOD THEREFOR

ROWTAN TECHNOLOGIES, LLC,...

1. A device for deflecting radio frequency (RF) radiation away from a user of a mobile phone comprising:a metallic plate configured to be positioned between the mobile phone and at least one of a decorative or protective cover, the metallic plate positioned over a rear surface of the mobile phone, wherein the metallic plate is removable and non-permanently attached to the mobile phone and the at least one of a decorative or protective cover and wherein the metallic plate includes:
a copper plate; and
a powder coating formed over the copper plate.

US Pat. No. 10,141,967

VIRTUAL NETWORK INTERFACE CONNECTIVITY

Ford Global Technologies,...

1. A system comprising:a mobile device programmed to
receive a message from a vehicle computing platform via remote process communication (RPC),
update an origin address of the message to indicate the mobile device,
send the message to a destination address of the message,
receive a response message from the destination,
update a destination address of the response message to indicate the computing platform, and
send the response message to the computing platform via the RPC.

US Pat. No. 10,141,966

UPDATE OF A TRUSTED NAME LIST

Apple Inc., Cupertino, C...

1. A method comprising:by a first electronic subscriber identity module (eSIM) server:
receiving, from a carrier server, a first request for an eSIM of a first type;
when the first eSIM server hosts eSIMs of the first type,
initiating an eSIM installation process with a device; and
when the first eSIM server does not host eSIMs of the first type:
sending, to a second eSIM server, a second request to reserve the eSIM on behalf of the device,
receiving, from the second eSIM server, a first identifier of the eSIM, and
sending, to the carrier server, the first identifier.

US Pat. No. 10,141,965

METHOD AND EQUIPMENT FOR CONFIGURING RADIO COMMUNICATIONS

Alcatel Lucent, Boulogne...

1. A method for configuring a radio communication channel between a first device and a second device wherein said first and second devices each include a physical data port and a radio communicator, said method comprising:providing a direct physical contact between the physical data ports of said first and second devices in order to establish communication between the physical data ports of said first and second devices;
exchanging configuration data through the direct physical contact; and
configuring a radio communication channel between the radio communicators of the first and second devices in accordance with the exchanged configuration data.

US Pat. No. 10,141,964

LOW-POWER CHANNEL SELECT FILTER USING TRANSRESISTANCE AMPLIFIER FOR DVB-H RECEIVERS

King Fahd University of P...

1. A channel select filter comprising:a fully differential transresistance amplifier (FDTRA) configured to change an input current at each differential input terminal to a voltage at each differential output terminal based on an impedance at a corresponding differential impedance terminal;
two first resistors, each having one end connected to a respective differential input terminal of the FDTRA and having another end connected to a node;
two feedback resistors, each having one end connected to a respective differential output terminal of the FDTRA and having another end connected to the node;
two first capacitors, each connected between ground and the node; and
two second capacitors, each connected between ground and a respective differential impedance terminal.

US Pat. No. 10,141,963

OPERATING METHOD OF RECEIVER, SOURCE DRIVER AND DISPLAY DRIVING CIRCUIT INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of operating a receiver, the method comprising:determining, by a controller of the receiver, whether a full initialization or a partial initialization of the receiver is needed;
adjusting, by the controller, alternating current (AC) characteristics and direct current (DC) characteristics of the receiver in a full initialization mode when the controller determines the full initialization is needed; and
adjusting, by the controller, the AC characteristics of the receiver in a partial initialization mode when the controller determines the partial initialization is needed,
wherein the adjusting of the AC characteristics comprises adjusting an equalization coefficient of an equalizer that is located in the receiver or causing a clock data recovery circuit of the receiver to enter a lock state.

US Pat. No. 10,141,962

DEMODULATOR

Asahi Kasei Microdevices ...

1. A demodulator comprising:a filter configured to reduce a high frequency component of a downconverted signal downconverted from a modulated signal;
a demodulation section configured to output a demodulated signal demodulated from the downconverted signal, in which the high frequency component is reduced; and
a noise remover configured to reduce a noise in the demodulated signal demodulated from the downconverted signal by using:
an integration section configured to integrate the demodulated signal;
a zone detection section configured to detect a replacement target zone in the demodulated signal based on an integrated signal output by the integration section; and
a replacement section configured to replace a signal of the replacement target zone in the demodulated signal with a replacement target signal.

US Pat. No. 10,141,961

PASSIVE INTERMODULATION CANCELLATION

NanoSemi, Inc., Waltham,...

1. A method for enhancing a received signal to remove distortion components of a concurrently transmitted signal, the method comprising:receiving a reference signal corresponding to a transmit signal transmitted in a radio frequency transmission band;
receiving via receiving circuitry a received signal acquired in a radio frequency reception band concurrently with transmission of the transmit signal in the transmit frequency band, wherein the received signal includes a distortion component of the transmit signal, and wherein the transmit frequency band and the receive frequency band are non-overlapping bands;
upsampling the reference signal to yield an upsampled transmit signal, and upsampling the received signal to yield an upsampled received signal, wherein the upsampled reference signal and the upsampled received signal have a same sampling rate, and wherein a relative frequency between the upsampled reference signal and the upsampled received signal matches a relative frequency between the transmit frequency band and the receive frequency band;
passing the upsampled reference signal to a configurable predictor configured with predictor parameters, the configurable predictor providing an upsampled distortion signal determined from the upsampled reference signal as input;
downsampling the upsampled distortion signal to yield a distortion signal;
enhancing the received signal using the distortion signal by removing components from the received signal corresponding to the distortion signal;
correlating the upsampled distortion signal and the upsampled received signal to determine a relative delay, wherein upsampling the reference signal includes synchronizing the upsampled reference signal and the upsampled received signal according to the relative delay; and
estimating the parameters for the predictor using the upsampled reference signal and the upsampled received signal.

US Pat. No. 10,141,959

RADIO-FREQUENCY INTEGRATED CIRCUIT (RFIC) CHIP(S) FOR PROVIDING DISTRIBUTED ANTENNA SYSTEM FUNCTIONALITIES, AND RELATED COMPONENTS, SYSTEMS, AND METHODS

Corning Optical Communica...

1. A central unit for providing communications signals in a wireless communications system, comprising:a radio-frequency (RF) communications interface configured to:
receive downlink RF communication signals at a RF communications frequency for a RF communications service; and
provide uplink RF communication signals at the RF communications frequency for the RF communications service;
at least one RF integrated circuit (IC) (RFIC) chip comprising at least one of:
a first frequency conversion circuitry configured to shift a frequency of the downlink RF communication signals to an intermediate frequency (IF) having a different frequency than the RF communications frequency, to provide downlink IF communications signals; and
a second frequency conversion circuitry configured to shift the frequency of uplink IF communication signals to the RF communications frequency to provide the uplink RF communications signals, wherein
the downlink RF communication signals are comprised of MIMO downlink RF communication signals,
the uplink RF communications signals are comprised of MIMO uplink RF communication signals,
the downlink IF communications signals are comprised of MIMO downlink IF communication signals,
the uplink IF communication signals are comprised of MIMO uplink IF communications signals; and
the RF communications interface is further configured to:
receive second MIMO downlink RF communication signals at the RF communications frequency for the RF communications service; and
receive second MIMO uplink RF communication signals at the RF communications frequency for the RF communications service, the central unit further comprising
at least one second RFIC chip comprising at least one of:
a third frequency conversion circuitry configured to shift the frequency of the second MIMO downlink RF communication signals to a second IF having a different frequency than the RF communications frequency, to provide second MIMO downlink IF communications signals; and
a fourth frequency conversion circuitry configured to shift the frequency of second MIMO uplink IF communication signals to the RF communications frequency to provide the second MIMO uplink RF communications signals.

US Pat. No. 10,141,958

ADAPTIVE TUNING NETWORK FOR COMBINABLE FILTERS

pSemi Corporation, San D...

1. A multi-path radio-frequency (RF) adaptive tuning network switch architecture configurable to operate in a carrier aggregation mode and in a non-carrier aggregation mode, including:(a) a multi-path tunable switch having (1) a plurality of signal ports each configured to be coupled to a corresponding RF band filter and (2) a common port, the multi-path tunable switch configured to concurrently connect at least two selected signal ports to the common port in at least one mode of operation;
(b) a single digitally-controlled tunable matching network coupled to the common port of the multi-path tunable switch and selectively controlled to counteract impedance mismatch conditions arising from coupling more than one selected RF band filter concurrently to the common port; and
(c) at least one digitally-controlled filter pre-match network for improving impedance matching and configured to be selectively coupled to or uncoupled from a corresponding signal port of the multi-path tunable switch, wherein at least one of the at least one digitally-controlled filter pre-match network is uncoupled from the corresponding signal port of the multi-path tunable switch when that corresponding signal port is operating in a non-carrier aggregation mode.

US Pat. No. 10,141,957

RADIO FREQUENCY FRONT END CIRCUITRY WITH REDUCED INSERTION LOSS

Qorvo US, Inc., Greensbo...

1. Circuitry comprising:a primary antenna node and a secondary antenna node;
a first set of input/output nodes, each associated with radio frequency (RF) signals within a first RF frequency band;
a second set of input/output nodes, each associated with RF signals within a second RF frequency band;
a first diplexer configured to separate RF signals within the first RF frequency band from RF signals within a first subset of the second RF frequency band;
a second diplexer configured to separate RF signals within the first RF frequency band from RF signals within a second subset of the second RF frequency band;
switching circuitry coupled between the primary antenna node, the secondary antenna node, the first set of input/output nodes, the second set of input/output nodes, the first diplexer, and the second diplexer; and
means for controlling the switching circuitry configured to cause the switching circuitry to:
in a carrier aggregation mode of operation between RF signals within the first RF frequency band and RF signals within the second RF frequency band, couple at least one of the first set of input/output nodes and at least one of the second set of input/output nodes to one of the primary antenna node and the secondary antenna node via one of the first diplexer and the second diplexer such that an insertion loss due to switching elements in the path between the at least one of the first set of input/output nodes and the primary antenna node is between 0.575 dB and 0.9 dB; and
in a non-carrier aggregation mode of operation, couple at least one of the first set of input/output nodes and the second set of input/output nodes to one of the primary antenna node and the secondary antenna node such that the first diplexer and the second diplexer are bypassed and an insertion loss due to switching elements in the path between the at least one of the first set of input/output nodes and the primary antenna node is between 0.625 dB and 0.9 dB.

US Pat. No. 10,141,956

DEVICE FOR BI-DIRECTIONAL AND MULTI-BAND RF COMMUNICATION OVER SINGLE RESONANT TRANSMISSION LINE AND METHOD OF ITS REALIZATION

14. A duplexing system comprising:a duplexer;
an antenna configured to transmit and receive electromagnetic signals;
a transmitter configured to couple electromagnetic signals to said antenna for transmission;
a receiver configured to receive electromagnetic signals;
wherein the duplexer comprises a first transmission line and a second transmission line, wherein a portion of said first transmission line is placed in a first proximity to a portion of said second transmission line, the first proximity causing electromagnetic coupling between said first transmission line and said second transmission line;
wherein a first end of said first transmission line is connected to a first duplexer port coupled to said antenna and a second end of said first transmission line is connected to a second duplexer port coupled to said transmitter; and
wherein both ends of said second transmission line are connected to loads;
wherein said second transmission line comprises a high directivity coupler comprising an interior transmission line connected at a first end to a third duplexer port coupled to the receiver and at a second end to ground;
wherein a portion of said interior transmission line is in a second proximity to a portion of said second transmission line, the second proximity causing electromagnetic coupling between said second transmission line and said interior transmission line.

US Pat. No. 10,141,955

METHOD AND APPARATUS FOR SELECTIVE AND POWER-AWARE MEMORY ERROR PROTECTION AND MEMORY MANAGEMENT

International Business Ma...

1. A method for providing selective error protection for a memory in a computing system, the method comprising:predicting a number of future errors likely to occur in at least one portion of the memory;
obtaining an active error correcting code (ECC) configuration for the at least one portion of the memory;
determining whether the active ECC configuration is sufficient to correct the number of predicted future errors in the at least one portion of the memory;
at least when the active ECC configuration is insufficient, determining whether data in the at least one portion of the memory is critical to an application running on the computing system;
when the data is not critical, tolerating corruption of the data; and
when the data is critical, determining whether a stronger ECC level is available and, when the stronger ECC level is available, increasing a strength of the active ECC configuration for the at least one portion of the memory.

US Pat. No. 10,141,953

LOW-DENSITY PARITY-CHECK APPARATUS AND MATRIX TRAPPING SET BREAKING METHOD

VIA Technologies, Inc., ...

1. A low-density parity-check (LDPC) apparatus, configured to perform an iteration operation to decode an original codeword, comprising:a log likelihood ratio (LLR) mapping circuit, configured to convert the original codeword into a LLR vector according to a mapping relationship;
a variable node (VN) calculation circuit, coupled to the LLR mapping circuit for receiving the LLR vector, and configured to calculate at least one original variable-node to check-node (V2C) information from at least one VN to at least one check node (CN) by using the LLR vector and at least one check-node to variable-node (C2V) information;
an adjustment circuit, coupled to the VN calculation circuit to receive the original V2C information, and configured to adjust the original V2C information to obtain at least one adjusted V2C information according to at least one factor, wherein the factor is multiplied to the original V2C information;
a check node calculation circuit, coupled to the adjustment circuit to receive the adjusted V2C information, and configured to calculate the at least one C2V information from the CN to the VN by using the adjusted V2C information, and providing the at least one C2V information to the VN calculation circuit; and
a controller, coupled to the adjustment circuit, and configured to determine whether to adjust the factor, wherein when the iteration operation falls into a matrix trapping set, the controller decides to adjust the factor to break the iteration operation away from the matrix trapping set.

US Pat. No. 10,141,952

MEMORY SYSTEM AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A memory system comprising:a memory device; and
a controller including an ECC circuit and coupled with the memory device, wherein the controller is configured to
receive a message in response to a request from a host,
generate a message matrix by the ECC circuit into at least one buffer of the ECC circuit, including predetermined row codes and predetermined column codes symmetrical to the predetermined row codes in accordance with the received message, wherein the message matrix includes a first triangular matrix and a second triangular matrix symmetrical to the first triangular matrix,
encode the message matrix by the ECC circuit using a block-wise concatenated Bose-Chadhuri-Hocquenghem (BCH) code with a symmetrical structure, and
store the encoded message by the ECC circuit into the memory device, and decode the encoded message by the ECC circuit using a block-wise concatenated BCH code with a symmetrical structure.

US Pat. No. 10,141,951

TRANSMITTER AND SHORTENING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...


where ?s(j) represents an index of a bit group area padded in the j-th order among the plurality of bit group areas, and Ninfo group represents a number of the plurality of bit group areas.

US Pat. No. 10,141,950

LOW DENSITY PARITY CHECK DECODER

1. A low density parity check (LDPC) code decoder, comprising:decoding circuitry configured to process blocks of an LDPC matrix, the decoding circuitry comprising:
a control unit that controls processing by the decoding circuitry, the control unit configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order,
wherein the control unit is configured to cause the decoding circuitry to process each block of the LDPC matrix in processing substeps comprising:
an R new update substep that provides an R new message, wherein the R new message is produced for a block of a different layer of the matrix from a layer containing a block currently being processed;
an R old update substep that selects an R old message, wherein the R old message is produced for a layer of the matrix currently being processed;
a P message substep that generates updated P messages;
a Q message substep that computes variable node messages (Q messages); and
a partial state substep that updates partial state of a block row based on Q messages computed for the block (check node unit (CNU) Partial state processing).

US Pat. No. 10,141,949

MODULAR SERIALIZER AND DESERIALIZER

Cavium, LLC, Santa Clara...

1. A deserializer circuit, comprising:an input buffer configured to receive a serial data signal; and
an array of cells, each cell comprising an input flip-flop and an output flip-flop, the array of cells including:
a bottom row of cells configured to receive a plurality of partial words in parallel from the input buffer to the input flip-flops of the bottom row of cells, the plurality of partial words corresponding to the serial data signal;
at least one intermediary row of cells configured to 1) receive the plurality of partial words from a preceding row of cells, and 2) transfer a subset of the plurality of partial words to a successive row of cells of the array of cells; and
a top row of cells configured to receive one of the plurality of partial words from a preceding row of cells of the array of cells;
the array of cells outputting a word in parallel via the output flip-flops, the word corresponding to the plurality of partial words.

US Pat. No. 10,141,948

DELTA-SIGMA MODULATOR, ANALOG-TO-DIGITAL CONVERTER AND ASSOCIATED SIGNAL CONVERSION METHOD BASED ON MULTI STAGE NOISE SHAPING STRUCTURE

MediaTek Inc., Hsin-Chu ...

1. A delta-sigma modulator, for digitizing a first stage input, comprising:a first signal converter, comprising:
a first input summer, for summing a first converted output and the first stage input to generate a first delta signal;
a first loop filter, coupled to the first input summer, for filtering the first delta signal to generate a first sigma signal;
a noise shaping quantizer, coupled to the first loop filter, for quantizing the first sigma signal to generate the first converted output, and shaping a first stage quantization error to generate a second stage input, wherein the first stage quantization error is inherent in quantization operation of the noise shaping quantizer, and the first stage input and the second stage input are analog signals;
a second signal converter, for converting the second stage input to a second converted output; and
a digital cancellation logic, coupled to the first input summer, the noise shaping quantizer and the second signal converter for generating a digital output according to the first converted output and the second converted output,
wherein the noise shaping quantizer comprises:
a first inner summer, coupled to the first loop filter, for summing the first converted output and the first sigma signal to generate a first inner summation signal, wherein the first inner summation signal is used as the second stage input;
a noise shaping filter, coupled to the first inner summer, for filtering the first inner summation signal to generate a noise shaped signal;
a second inner summer, coupled to the first loop filter, the noise shaping filter and the first inner summer, for summing the noise shaped signal and the first sigma signal to generate a second inner summation signal; and
a first noise shaping quantizer, coupled to the first inner summer, the second inner summer and the digital cancellation logic, for quantizing the second inner summation signal to generate the first converted output, wherein the first stage quantization error is generated by the first noise shaping quantizer.

US Pat. No. 10,141,947

SIGNAL GENERATING DEVICE

NIPPON TELEGRAPH AND TELE...

1. A signal generating device comprising:a digital signal processing unit;
two digital-to-analog converters (DACs); and
an analog multiplexer that alternatingly switches analog signals outputted from the two DACs with a frequency fc for outputting as analog signals, wherein
the digital signal processing unit includes:
when a signal, among desired output signals having an upper limit frequency of less than fc, made of a component having an absolute value of a frequency being substantially fc/2 or less is assumed as a low-frequency signal, and
when, for a positive frequency component and a negative frequency component which are made of a component having an absolute value of a frequency being substantially fc/2 or more among the desired output signals, a signal in which the positive frequency component is shifted by ?fc on a frequency axis and a signal in which the negative frequency component is shifted by +fc on the frequency axis are assumed as a folded signal,
means for generating a first signal that is equal to a signal obtained by multiplying the folded signal by a constant and adding a resultant to the low-frequency signal; and
means for generating a second signal that is equal to a signal obtained by multiplying the folded signal by the constant and subtracting a resultant from the low-frequency signal, and wherein:
a digital signal corresponding to the first signal generated in the digital signal processing unit is inputted into one of the two DACs; and
a digital signal corresponding to the second signal generated in the digital signal processing unit is inputted into the other one of the two DACs.

US Pat. No. 10,141,946

MULTI-PATH ANALOG SYSTEM WITH MULTI-MODE HIGH-PASS FILTER

Cirrus Logic, Inc., Aust...

1. A system comprising:an input for receiving an input signal;
an output for generating an output signal;
a capacitor coupled between the input and the output;
a variable resistor coupled to the output and having a plurality of modes including a first mode in which the variable resistor has a first resistance and a second mode in which the variable resistor has a second resistance; and
control circuitry configured to:
determine a difference between the input signal and the output signal; and
switch between modes of the plurality of modes when the difference is less than a predetermined threshold.

US Pat. No. 10,141,945

RADIO FREQUENCY FLASH ADC CIRCUITS

Maxlinear Asia Singapore ...

1. A system, the system comprising:a plurality of capacitors, a first port of each of the plurality of capacitors being operably coupled to a radio frequency (RF) input;
a plurality of resistors, a first port of each of the plurality of resistors being operably coupled to a reference level of a plurality of reference levels, a second port of each of the plurality of resistors being operably coupled to a second port of each of the plurality of capacitors; and
a sampling circuit operably coupled to the second port of each of the plurality of resistors, wherein the sampling circuit is operable to produce a plurality of digital outputs.

US Pat. No. 10,141,944

METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY

MAXLINEAR, INC., Carlsba...

1. A method, comprising:in an electronic device that performs analog-to-digital conversion:
generating a distorted digital signal by sampling an output from a non-linear analog frontend;
generating a corrected digital signal by applying a compensation signal to said distorted digital signal; and
generating said compensation signal according to a non-linearity estimation and a spectral analysis of said corrected digital signal.

US Pat. No. 10,141,943

HIGH SPEED ACQUISITION SYSTEM FOR PHASE LOCKED LOOPS

TELEDYNE DEFENSE ELECTRON...

1. A signal generator, comprising:a voltage window generator to receive an analog frequency select signal from a digital-to-analog converter (DAC) and to generate a first reference threshold voltage and a second reference threshold voltage based on the analog frequency select signal;
a window comparator coupled to the voltage window generator, the window comparator to receive a voltage controlled oscillator (VCO) tuning voltage from a phase locked loop (PLL), receive the first and second reference threshold voltages from the voltage window generator, and generate a first steering current control signal and a second steering current control signal; and
a steering current circuit coupled to the window comparator, the steering current circuit to receive the first and second steering current control signals to control a steering current coupled to a PLL and apply a phase comparator/detector signal to an PLL based on the first and second steering current control signals.

US Pat. No. 10,141,942

APPARATUSES AND METHODS FOR PROVIDING FREQUENCY DIVIDED CLOCKS

Micron Technology, Inc., ...

1. An apparatus, comprising:a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock;
a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock; and
a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks, wherein the third circuit comprises:
a delay circuit configured to delay the first intermediate clock to produce a delayed intermediate clock;
a phase detector configured to compare a phase of the delayed intermediate clock and the second intermediate clock; and
a multiplexer coupled to receive the second and third intermediate clocks, the multiplexer configured to select one of the second and third intermediate clocks responsive, at least in part, to an output from a phase detector, the multiplexer comprising:
a first logic gate including a first input coupled to receive the second intermediate clock;
a first inverter circuit including an output coupled to a second input of the first logic gate;
a second logic gate including a first input coupled to receive the third intermediate clock;
a second inverter circuit including an input coupled to an output of the first inverter circuit and further including an output coupled to a second input of the second logic gate; and
a third logic gate coupled to receive outputs of the first and second logic gates and including an output from which the output clock is provided.

US Pat. No. 10,141,941

DIFFERENTIAL PLL WITH CHARGE PUMP CHOPPING

HUAWEI TECHNOLOGIES CO., ...

1. A charge pump circuit comprising:an intake chopper circuit configured to switch input signals received at the first and second inputs of the intake chopper circuit between first and second outputs of the intake chopper circuit at a chopping frequency, wherein successive input signals at the first input are provided alternatively at the first and second outputs in successive cycles of the chopping frequency and successive input signals at the second input are provided alternatively at the second and first outputs in successive cycles of the chopping frequency;
a differential charge pump configured to receive the signals from the first and second outputs of the intake chopper circuit and produce corresponding first and second charge pumped signals; and
an output chopper circuit configured to receive the first and second charge pumped signals at respective first and second inputs, provide the first charge pumped signals alternatively at first and second outputs in successive cycles of the chopping frequency, and provide the second charge pumped signals alternatively at the second and first outputs in successive cycles of the chopping frequency.

US Pat. No. 10,141,940

FORWARDED CLOCK RECEIVER BASED ON DELAY-LOCKED LOOP

1. A delay-locked loop comprising:a voltage-controlled delay line generating a clock signal; and
a phase detector obtaining a first sample group by sampling a data signal in at least two positions at a unit interval based on the clock signal and a second sample group by sampling the data signal in at least two positions at the unit interval based on the clock signal, wherein a difference between the positions in which the second sample group is obtained and the positions in which the first sample group is obtained is a half of the unit interval,
selecting, for a first mode, the first sample group as an edge sample of the data signal and the second sample group as a data sample of the data signal, and for a second mode, the first sample group as the data sample of the data signal and the second sample group as the edge sample of the data signal, and
controlling the voltage-controlled delay line by toggling between the first mode and the second mode.

US Pat. No. 10,141,939

CONFIGURABLE COMPUTING ARRAY USING TWO-SIDED INTEGRATION

ChengDu HaiCun IP Technol...

1. A configurable computing-array die, comprising:a semiconductor substrate having a first side and a second side;
an array of configurable computing elements including first and second configurable computing elements disposed on said first side of said semiconductor substrate, wherein said first configurable computing element comprises a first memory for storing a first look-up table (LUT) for a first math function; and, said second configurable computing element comprises a second memory for storing a second LUT for a second math function;
an array of configurable logic elements including a configurable logic element disposed on said second side of said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library;
a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing elements and said configurable logic elements;
whereby said configurable computing-array die realizes a complex math function by programming said configurable computing elements and said configurable logic elements, wherein said complex math function is a combination of at least said first and second math functions.

US Pat. No. 10,141,938

STACKED COLUMNAR INTEGRATED CIRCUITS

XILINX, INC., San Jose, ...

1. A semiconductor device, comprising:a first integrated circuit (IC) die including a first column of cascade-coupled resource blocks;
a second IC die including a second column of cascade-coupled resource blocks, where an active side of the second IC die is mounted to an active side of the first IC die; and
a plurality of electrical connections between the active side of the first IC and the active side of the second IC, the plurality of electrical connections including at least one electrical connection between the first column of cascade-coupled resource blocks and the second column of cascade-coupled resource blocks.

US Pat. No. 10,141,937

PULSE-WIDTH MODULATION (PWM) CONTROL LOOP FOR POWER APPLICATION

ANDAPT, INC., San Jose, ...

1. A method comprising:receiving error signals from a signal wrapper of a programmable fabric, wherein the programmable fabric and the signal wrapper are integrated in a programmable logic device (PLD);
looking up one or more lookup tables storing rows of pre-calculated data and obtaining a matching pre-calculated data corresponding to the error signals; and
generating a compensated output signal using the matching pre-calculated data to drive a switch of a power regulator,
wherein the pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper, and
wherein the PLD comprises a high voltage power transistor, and the PLD is configured as the power regulator by configuring the high voltage power transistor, and wherein the compensated output signal is a pulse width of a pulse-width modulation (PWM) signal of a digital filter for driving a switch of the high voltage power transistor.

US Pat. No. 10,141,936

PIPELINED INTERCONNECT CIRCUITRY WITH DOUBLE DATA RATE INTERCONNECTIONS

Altera Corporation, San ...

1. An integrated circuit, comprising:a selection circuit configured to receive first and second signals;
control circuitry coupled to the selection circuit and configured to receive a clock signal and to control the selection circuit to generate a double data rate signal based on the clock signal by serializing the first and second signals, wherein the selection circuit is configured to generate the double data rate signal in a first mode of operation and to generate a single data rate signal in a second mode of operation; and
a storage element coupled to the selection circuit and configured to store the double data rate signal.

US Pat. No. 10,141,935

PROGRAMMABLE ON-DIE TERMINATION TIMING IN A MULTI-RANK SYSTEM

Intel Corporation, Santa...

1. A memory device with on-die termination (ODT) comprising:a hardware interface to couple to a memory bus shared by multiple memory devices;
an ODT circuit to selectively apply ODT to the hardware interface for a memory access operation in accordance with an ODT latency setting in response to receipt of a memory access command;
a first addressable register to store a dynamically programmable first ODT latency setting to control ODT turn on timing or turn off timing for a Read operation; and
a second addressable register separate from the first addressable register to store a dynamically programmable second ODT latency setting to control ODT turn on or turn off timing or turn off timing for a Write operation.

US Pat. No. 10,141,934

HIGH SPEED LEVEL-SHIFTER

Taiwan Semiconductor Manu...

1. A level shifter circuit, comprising:a latch with a first plurality of transistors and a second plurality of transistors, wherein drains of the second plurality of transistors are electrically connected to a logic low voltage pin;
a third plurality of transistors operatively connected to the latch;
a fourth plurality of transistors operatively connected between the third plurality of transistors and ground; and
a plurality of capacitors operatively connected between the latch and the gates of the fourth plurality of transistors.

US Pat. No. 10,141,933

SELF-REPAIRING DIGITAL DEVICE WITH REAL-TIME CIRCUIT SWITCHING INSPIRED BY ATTRACTOR-CONVERSION CHARACTERISTICS OF A CANCER CELL

KOREA ADVANCED INSTITUTE ...

1. An electric device, comprising:a first switch-unit providing a first internal circuit signal;
a first delay circuit unit outputting a second internal circuit signal which is generated by delaying the first internal circuit signal;
a first AND logic outputting a first repair-signal generated by a logical AND operation between the first internal circuit signal and the second internal circuit signal;
a first OR logic outputting a second repair-signal generated by a logical OR operation between the first internal circuit signal and the second internal circuit signal; and
a second switch-unit selecting one of the first repair-signal and the second repair-signal according to a third internal circuit signal generated by an operation including a logical AND operation between the first repair-signal and the second repair-signal and providing the selected one as an output signal through an output terminal;
wherein, the first switch-unit chooses one of the first repair-signal and the second repair-signal according to the output signal and provides the chosen one as first internal circuit signal.

US Pat. No. 10,141,932

WIRING WITH EXTERNAL TERMINAL

Micron Technology, Inc., ...

1. An apparatus comprising a semiconductor die, wherein the semiconductor die comprises:an area including a first side and a second side opposite to the first side;
a first via disposed on the first side of the area;
a second via disposed on the second side of the area;
a first pad disposed in a pad formation area and configured to receive a first voltage;
a first distribution conductor extending from the first pad to the first and second vias and configured to couple the first pad to the first and second vias;
a first conductive line coupled to the first via;
a second conductive line coupled to the second via;
a third conductive line configured to be coupled to the first conductive line;
a fourth conductive line configured to be coupled to the second conductive line;
a first switch disposed between the first and third conductive lines and configured to couple the first conductive line to the third conductive line; and
a second switch disposed between the second and fourth conductive lines and configured to couple the second conductive line to the fourth conductive line.

US Pat. No. 10,141,931

MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND SLEW RATE CALIBRATION METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A memory device comprising:a main driver configured to provide an output signal to a host based on a driving signal; and
a pre-driver configured to provide the main driver with the driving signal in order to calibrate a slew rate of the output signal based on an output resistance value of the main driver and a resistance value of an on-die termination circuit of the host.

US Pat. No. 10,141,930

THREE STATE LATCH

Nvidia Corporation, Sant...

1. An electronic circuit comprising a single latch having three stable states, said latch comprising three inputs and three outputs for indicating said three stable states, and wherein said latch is configured wherein all said three outputs reflect a change at any one of said inputs in not more than two gate delays.

US Pat. No. 10,141,928

QUANTUM LIMITED JOSEPHSON AMPLIFIER WITH SPATIAL SEPARATION BETWEEN SPECTRALLY DEGENERATE SIGNAL AND IDLER MODES

INTERNATIONAL BUSINESS MA...

1. A system for remotely entangling qubits via measurement, the system comprising:a Josephson parametric converter (JPC);
a first qubit-resonator system connected to the JPC, the first qubit-resonator system including a first qubit coupled to a first readout resonator; and
a second qubit-resonator system connected to the JPC, the second qubit-resonator system including a second qubit coupled to a second readout resonator, wherein the JPC is configured to remotely entangle the first qubit and the second qubit by reading out both the first and the second readout resonators at a frequency X.

US Pat. No. 10,141,926

ULTRA-LOW POWER CROSS-POINT ELECTRONIC SWITCH APPARATUS AND METHOD

Ciena Corporation, Hanov...

1. An electrical switch circuit adapted to switch digital, high-speed signals with low power, the electrical switch circuit comprising:a plurality of input buffers comprising a first set of digital inverters and each is coupled to an associated input transmission line of a plurality of input transmission lines;
a plurality of output buffers comprising a second set of digital inverters and each is coupled to an associated output transmission line of a plurality of output transmission lines; and
a plurality of switches each coupled to an associated input transmission line and an associated output transmission line and between the first set of digital inverters and the second set of digital inverters, wherein each of the input transmission line, the output transmission line, and the plurality of switches are in a single line configuration, wherein the plurality of input buffers, the plurality of output buffers, and the plurality of switches are arranged in a tile and comprise an N×N cross-point switch, wherein an M×M cross point switch, M>N, is formed by a plurality of tiles, and wherein each tile is sized smaller than a bit period length of the digital, high-speed signals.

US Pat. No. 10,141,925

CIRCUITS AND METHODS FOR STRENGTHENING LOAD TRANSIENT RESPONSE COMPENSATION

WISTRON CORP., New Taipe...

1. A circuit for strengthening load transient response compensation, comprising:a comparator, comparing a system voltage of an electronic device with a reference voltage;
a first MOSFET, coupled to the comparator and a first power supply;
a second MOSFET, coupled to the comparator and a second power supply of the electronic device;
wherein when an external device is connected to the electronic device such that the system voltage is lower than the reference voltage, the comparator outputs a low-level signal and the first MOSFET becomes conductive, so that the external device is powered by the first power supply;
wherein when the system voltage is higher than the reference voltage, the comparator outputs a high-level signal and the second MOSFET becomes conductive, so that the external device is powered by the second power supply; and
wherein the first power supply is a supercapacitor, and when the second MOSFET becomes conductive, the second power supply charges the supercapacitor at the same time.

US Pat. No. 10,141,923

SYSTEM AND METHOD FOR ELIMINATING GATE VOLTAGE OSCILLATION IN PARALLELED POWER SEMICONDUCTOR SWITCHES

1. A damping circuit for a semiconductor device, comprising:a switch having an input terminal and an output terminal for driving voltage;
a plurality of resistors connected to the output terminal of the switch including a first resistor and a second resistor;
a plurality of inductors that include a first inductor and a second inductor, an input of the first inductor connected to the first resistor and an input of the second inductor connected to the second resistor;
a plurality of capacitors that include a first capacitor and a second capacitor and configured to provide a capacitance for electrical storage, an input of the first capacitor connected to an output of the first inductor at a first gate terminal and an input of the second capacitor connected to an output of the second inductor at a second gate terminal;
a plurality of power semiconductor switches including a first power semiconductor switch and a second power semiconductor switch, the first power semiconductor switch being connected to the output of the first inductor at the first gate terminal and the second semiconductor switch being connected to the output of the second inductor at the second gate terminal;
a plurality of gate terminal switches including a first gate terminal switch and a second gate terminal switch; and
a plurality of gate terminal resistors including a first gate terminal resistor connected in series with the first gate terminal switch and a second gate terminal resistor connected in series with the second gate terminal switch, the first gate teiininal resistor and the first gate terminal switch being connected in between the first power semiconductor switch at the first gate terminal and a ground, the second gate terminal resistor and the second gate terminal switch being connected in between the second power semiconductor switch at the second gate terminal and the ground.

US Pat. No. 10,141,921

SIGNAL GENERATOR USING MULTI-SAMPLING AND EDGE COMBINING AND ASSOCIATED SIGNAL GENERATING METHOD

MEDIATEK INC., Hsin-Chu ...

1. A signal generator for generating an output signal having a waveform with transition edges according to an oscillating signal having a waveform, the signal generator comprising:a plurality of edge sampling circuits, each configured to receive the oscillating signal and a bias voltage, sample the waveform of the oscillating signal using the bias voltage to generate at least one of a rising edge and a falling edge in one cycle of the oscillating signal, and output a sampled signal using the at least one of the rising edge and the falling edge; and
an edge combining circuit, configured to combine a plurality of sampled signals generated by the edge sampling circuits, respectively, to generate the output signal;
wherein the edge sampling circuits comprise at least a first edge sampling circuit and a second edge sampling circuit, and the signal generator further comprises:
a voltage generator, configured to generate a first bias voltage to the first edge sampling circuit and generate a second bias voltage to the second edge sampling circuit;
wherein the first bias voltage is different from the second bias voltage, the first edge sampling circuit obtains a first set of a rising edge and a falling edge in a cycle of the oscillating signal according to the first bias voltage, the second edge sampling circuit obtains a second set of a rising edge and a falling edge in the cycle of the oscillating signal according to the second bias voltage, and the first set of the rising edge and the falling edge is different from the second set of the rising edge and the falling edge.

US Pat. No. 10,141,920

CLOCK SIGNAL CONTROLLER

INTERNATIONAL BUSINESS MA...

1. A clock signal controller, comprising:a first transistor being connected to a working level and a first connecting point, and a gate of the first transistor being connected to a first clock signal input end;
a second transistor being connected to a first connecting point and to a reference level, and a gate of the second transistor being connected to the first clock signal input end;
a third transistor being connected to the working level and to a second connecting point, and a gate of the third transistor being connected to a second clock signal input end; and
a fourth transistor being connected to the working level and the second connecting point, and a gate of the fourth transistor being connected to the second clock signal input end;
wherein the first connecting point and the second connecting point are connected to a first clock signal output end.

US Pat. No. 10,141,919

RESOLUTION-ENHANCING CMOS ALL-DIGITAL PULSE-MIXING METHOD AND DEVICE THEREOF

National Kaohsiung First ...

1. A CMOS all-digital pulse-mixing method comprising:providing a plurality of odd combination positions and a plurality of even combination positions on a basic element sequence which is formed from a series of basic elements;
providing a plurality of homogeneous logic elements, at least one first element parallel connection set and at least one second element parallel connection set for forming an all-digital pulse-mixing device;
arranging the at least one first element parallel connection set as an odd-positioned element parallel connection set, with the at least one first element parallel connection set having a first parallel connection number of first logic elements;
arranging the at least one second element parallel connection set as an even-positioned element parallel connection set, with the at least one second element parallel connection set having a second parallel connection number of second logic elements;
serially connecting the at least one first element parallel connection set with a first predetermined position of the plurality of odd combination positions and serially connecting the at least one second element parallel connection set with a second predetermined position of the plurality of even combination positions; and
utilizing the at least one first element parallel connection set and the at least one second element parallel connection set to stretch or shrink a pulse signal, with mixing a first degree of pulse stretching and a second degree of pulse shrinking to generate a stretched pulse signal or a shrunk pulse signal.

US Pat. No. 10,141,918

APPARATUS AND METHOD FOR SIGNAL PROCESSING BY CONVERTING AMPLIFIED DIFFERENCE SIGNAL

Samsung Electronics Co., ...

1. A signal processing apparatus, comprising:a difference signal acquirer configured to obtain a difference signal reflecting changes in an input signal at preset time intervals based on a reference signal;
a signal amplifier configured to amplify the difference signal; and
a signal restorer configured to generate an output signal reflecting the input signal by converting the amplified difference signal to a digital signal and incrementally summing the digital signal over the time intervals, wherein, for the incrementally summing over the time intervals, the signal restorer is configured to sum a digital signal of a current time to a summed digital signal of a previous time.

US Pat. No. 10,141,917

MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES

Lattice Semiconductor Cor...

1. A programmable logic device (PLD), comprising:a plurality of programmable logic blocks (PLBs); and
at least first and second logic cells within at least one of the plurality of PLBs, each logic cell comprising a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT, wherein:
the associated mode logic is configured to use a single physical output port to provide a logic cell output signal from its respective logic cell corresponding to an operational mode selected from a logic function operational mode, a ripple arithmetic operational mode, and an extended logic function operational mode;
when the selected operational mode for the first logic cell comprises the logic function operational mode, the associated mode logic for the first logic cell is configured to provide the LUT output signal of the first logic cell as the logic cell output signal on the single physical output port; and
when the selected operational mode for the first logic cell comprises the extended logic function operational mode, the associated mode logic for the first logic cell is configured to:
multiplex the LUT output signal of the first logic cell and the LUT output signal of the second logic cell, and
provide the multiplexed signal as a first logic cell output signal on the single physical output port of the first logic cell and to an input of the second logic cell.

US Pat. No. 10,141,916

HIGH-SPEED FLIP-FLOP SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A semiconductor circuit comprising:a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal;
a second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal; and
a third logic gate that receives inputs of a second input signal and a scan-enable signal and performs a third logical operation on the second input signal and the scan-enable signal to generate the first input signal.

US Pat. No. 10,141,915

SEQUENCED PULSE-WIDTH ADJUSTMENT IN A RESONANT CLOCKING CIRCUIT

INTERNATIONAL BUSINESS MA...

1. A method of operating an integrated circuit having a resonant clock distribution network, the method comprising:generating a distributed clock signal within the resonant clock distribution network by driving the resonant clock distribution network with a plurality of clock driver circuits that receive a clock input from a global clock signal and have outputs connected to corresponding locations within sectors of the resonant clock distribution network;
controlling pulse widths of individual ones of the plurality of clock drivers according to a plurality of control signals provided to corresponding ones of the plurality of clock driver circuits, wherein the pulse widths of the individual clock drivers differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network
from a first control logic, selecting an operating mode or frequency of the resonant clock distribution network; and
from a second control logic, generating the plurality of control signals such that, responsive to the selecting having selected a new operating mode or a new frequency, the pulse widths of the individual clock driver circuits are set to new pulse width values, wherein the individual clock driver circuits are operated at the new pulse width values, and wherein the new pulse width values differ for at least some of the sectors.

US Pat. No. 10,141,914

OSCILLATION CIRCUIT

Kabushiki Kaisha Toshiba,...

1. An oscillation circuit comprising:a delay circuit that includes a first inverter having an input terminal connected to a first node; and
a delay adjustment circuit including a first current supply path and a second current supply path through which the first node is charged in response to an output signal of the delay circuit, wherein,
during charging of the first node, a current with positive temperature characteristics is supplied to the first node through the first current supply path, and a current with negative temperature characteristics is supplied to the first node through the second current supply path, and
the second current supply path includes a source-drain path of an NMOS transistor having a gate to which a bias voltage with negative temperature characteristics is applied.

US Pat. No. 10,141,913

MULTIPLEXER, TRANSMISSION APPARATUS, AND RECEPTION APPARATUS

Murata Manufacturing Co.,...

1. A multiplexer that transmits and receives a plurality of high-frequency signals via an antenna element, the multiplexer comprising:a plurality of elastic wave filters that have pass bands different from one another; and
a common terminal that is connected to the antenna element by a connection path, a first inductance element being connected between the connection path and a reference terminal; wherein
each of the plurality of elastic wave filters includes at least one of a series resonator connected between an input terminal and an output terminal of each of the plurality of elastic wave filters, and a parallel resonator connected between the reference terminal and a connection path connecting the input terminal and the output terminal to each other;
a terminal closer to the antenna element among the input terminal and the output terminal of one elastic wave filter among the plurality of elastic wave filters is connected to the parallel resonator and is connected to the common terminal with a second inductance element interposed therebetween; and
a terminal closer to the antenna element among the input terminal and the output terminal of each of other elastic wave filters other than the one elastic wave filter among the plurality of elastic wave filters is connected to the common terminal and the series resonator.

US Pat. No. 10,141,912

RF RESONATORS AND FILTERS

ZHUHAI CRYSTAL RESONANCE ...

1. A filter package comprising an array of piezoelectric films sandwiched between an array of upper electrodes and lower electrodes:the individual piezoelectric films and the upper electrodes being separated by a passivation material; the lower electrode being coupled to an interposer with a first cavity between the lower electrodes and the interposer; the filter package further comprising a silicon wafer of known thickness attached over the upper electrodes with an array of upper cavities between the silicon wafer and a silicon cover; each upper cavity aligned with a piezoelectric film in the array of piezoelectric films, the upper cavities having side walls comprising the passivation material.

US Pat. No. 10,141,911

HIGH-FREQUENCY MODULE AND COMMUNICATION APPARATUS

MURATA MANUFACTURING CO.,...

1. A high-frequency module comprising:a plurality of filters including first and second filters and including respective pass bands which are different from one another;
a connection circuit that commonly connects a plurality of paths in which the plurality of filters are respectively provided; and
a low noise amplifier that is connected to the connection circuit; wherein
the connection circuit is connected between the plurality of filters and the low noise amplifier;
in paths in which the first and second filters are respectively provided among the plurality of paths, the respective filters and the connection circuit are connected without connecting impedance elements;
each of the first and second filters has a respective output impedance located in a matching region between a noise figure matching impedance at which a noise figure of the low noise amplifier is minimum and a gain matching impedance at which a gain of the low noise amplifier is maximum in the respective pass band of each of the first and second filters on a Smith chart.

US Pat. No. 10,141,910

INTEGRATED AND COMBINED PHASE SHIFTER AND ISOLATION SWITCH

pSemi Corporation, San D...

1. A digitally-controlled phase shifter, including:(a) at least two phase shift signal paths, each coupled to first and second ports, for providing a phase shift to a signal applied to at least one of the first and second ports and responsive to a corresponding independent path selection control signal for selectively independently enabling communication of the applied signal from the first port to the second port through the corresponding phase shift signal path when not in an isolation mode, and disabling communication of the applied signal from the first port to the second port through the corresponding phase shift signal path when in the isolation mode; and
(b) at least one selectable termination circuit, each operatively coupled to a corresponding one of the first or second ports, and responsive to a distinct isolation circuit control signal for isolating the first port from the second port in the isolation mode.

US Pat. No. 10,141,909

METHOD AND APPARATUS FOR DUAL NOTCH RIPPLE FILTERING

GENERAL ELECTRIC COMPANY,...

1. An apparatus comprising:a self-coupled transformer having first, second, and third windings that are operatively connected in series between higher and lower potential input terminals, with the second winding connected out-of-phase to the first and third windings;
a first band stop filter connected in series between the second and third windings of the self-coupled transformer;
a first tuning capacitor connected in parallel across the second winding of the self-coupled transformer; and
output terminals operatively connected between the first and second windings and between the second and third windings.

US Pat. No. 10,141,908

MULTI-DENSITY MIM CAPACITOR FOR IMPROVED PASSIVE ON GLASS (POG) MULTIPLEXER PERFORMANCE

QUALCOMM Incorporated, S...

1. A passive on glass (POG) device, comprising:a spiral inductor comprising a single layer of a plurality of interconnected trace segments; and
a plurality of parallel plate capacitors, each of the plurality of parallel plate capacitors having a dielectric layer between a pair of conductive plates, and each of the plurality of parallel plate capacitors is overlapped by only one of the plurality of interconnected trace segments of the single layer spiral inductor.

US Pat. No. 10,141,907

INTEGRATED BPF AND LNA INPUT MATCH

pSemi Corporation, San D...

1. An RF receiver comprising:a first shunt element;
a second shunt element;
a series element connected with the first shunt element and the second shunt element;
an LNA comprising a transistor being connected to a degenerative inductor at a source of said transistor and to the second shunt element at a gate of said transistor; and
a switch comprising a first end and a second end;
wherein:
the first shunt element and the second shunt element are configured to reject set out-of-band frequencies;
the series element is configured i) to pass set in-band frequencies and ii) as an impedance matching element, to match a first impedance to a second impedance;
a combination of the set in-band frequencies and the set out-of-band frequencies corresponds to one of a i) band-pass filtering mask or ii) low-pass filtering mask or iii) high-pass filtering mask;
the series element comprises a series resonator;
when the switch is in a closed state, the LNA is bypassed;
the first end is connected with a point of connection within or at the input of the series resonator, and
the second end is connected with an output of the LNA.

US Pat. No. 10,141,906

HIGH Q QUARTZ-BASED MEMS RESONATORS AND METHOD OF FABRICATING SAME

HRL Laboratories, LLC, M...

16. A method of fabricating a resonator, comprising:providing a quartz application-specific integrated circuit (ASIC) wafer comprising a first bond pad and a second bond pad;
providing a quartz resonator comprising a first side, a second side opposite said first side, a via, a first electrode, a second electrode and a third electrode, wherein said first electrode is on said first side and overlaps said via, wherein said second electrode is on said second side, extends into said via and is in electrical contact with said first electrode, wherein said second electrode is in electrical contact with said first bond pad, and wherein said third electrode is on said second side and is in electrical contact with said second bond pad, wherein said via is formed by a dry etching process; and
providing a first mesa located on said first side, said first mesa being defined by forming a first groove into said first side so that said first mesa is at least partially surrounded by material having the same thickness relative to said first groove as said first mesa but positioned laterally of said first mesa and separated therefrom by said first groove;
providing a second mesa located on said second side, said second mesa being defined by forming a second groove into said second side so that said second mesa is at least partially surrounded by material having the same thickness relative to said second groove as said second mesa but positioned laterally of said second mesa and separated therefrom by said first groove, the first and second groves increasing the quality factor (Q) of the resonator being fabricated; and
providing a first electrode on said first mesa and providing a second electrode on said second mesa, the first electrode filling a portion of said first groove.

US Pat. No. 10,141,905

AMPLIFIER WITH ADJUSTMENT OF THE AUTOMATIC SOUND LEVEL

DEVIALET, Paris (FR)

10. An amplifier for producing a volume gain to at least one audio signal, according to a desired volume gain selected by a user, comprising:a calculator for calculating a standardized total slow sound level from the-at least one audio signal;
a calculator for calculating a maximum slow volume gain and a minimum slow volume gain as the quotient of the product of the desired volume gain by a maximum slow gain, respectively by a minimum slow gain divided by the standardized total slow sound level;
a device for determining a first minimum volume gain out of the desired volume gain and the maximum slow volume gain;
a device for determining a second minimum volume gain out of the desired volume gain multiplied by a maximum volume gain and the minimum slow volume gain;
a device for determining, as a slow volume gain, the maximum of the first and second determined minimum volume gains: and
a calculator for calculating the volume gain according to the slow volume gain.

US Pat. No. 10,141,903

METHODS AND SYSTEMS FOR CONTROLLING AUDIO OUTPUT OF AN EXTERIOR VEHICLE AUDIO SYSTEM

Honda Motor Co., Ltd., T...

1. An audio system for a vehicle comprising an audio control computer device and an exterior audio assembly, said audio control computer device in communication with a memory device, said audio control computer device configured to:store, in the memory device, at least one limited volume level and a corresponding speed range;
receive a speed-related parameter indicative of an actual speed of the vehicle from a vehicle control system;
determine if the actual speed of the vehicle is within the stored speed range based on the speed-related parameter;
permit operation of the exterior audio assembly at the at least one limited volume level when the actual speed of the vehicle is within the speed range;
permit operation of the exterior audio assembly at a maximum volume level when the actual speed of the vehicle falls below a lower limit of the speed range; and
automatically deactivate operation of the exterior audio assembly when the actual speed of the vehicle exceeds the speed range.

US Pat. No. 10,141,902

APPARATUS FOR AND METHOD OF GENERATING OUTPUT SIGNAL BASED ON DETECTED LOAD RESISTANCE VALUE

MARVELL WORLD TRADE LTD.,...

1. An apparatus, comprising:a first connector configured to receive a second connector to couple a tip connecting terminal, a first ring connecting terminal, a second ring connecting terminal and a sleeve connecting terminal of the first connector with respective portions of the second connector; and
a signal processing circuit configured to, after an insertion determination that the first connector is coupled to the second connector:
measure a first current-voltage (I-V) characteristic of the second connector via the sleeve connecting terminal of the first connector, and a second I-V characteristic of the second connector via the second ring connecting terminal of the first connector;
determine a set of plural potential pole configurations for the second connector based on the first I-V characteristic and the second I-V characteristic;
detect a first load resistance value at a first connecting terminal of the second connector via the tip connecting terminal of the first connector and a second load resistance value at a second connecting terminal of the second connector via the first ring connecting terminal of the first connector;
select a pole configuration from the set of plural potential pole configurations based on the first load resistance value and the second load resistance value; and
set a first amplification gain for generating a first output signal based on the first load resistance value.

US Pat. No. 10,141,901

FLIP-CHIP AMPLIFIER WITH TERMINATION CIRCUIT

Skyworks Solutions, Inc.,...

1. A power amplifier module comprising:a flip-chip power amplifier die including a power amplifier configured to amplify a radio frequency signal;
a first circuit element included in a matching network that is configured to provide impedance matching at a fundamental frequency of the radio frequency signal; and
a second circuit element included in a harmonic termination circuit, the second circuit element and the first circuit element being electrically connected to an output of the power amplifier by way of different bumps.

US Pat. No. 10,141,900

OFFSET TRIMMING FOR DIFFERENTIAL AMPLIFIER

SANDISK TECHNOLOGIES LLC,...

1. An apparatus comprising:a differential amplifier comprising a non-inverting input, an inverting input, and an output coupled to the inverting input via a voltage divider;
a first variable current source coupled to the non-inverting input, such that increasing a current from the first variable current source increases a voltage at the non-inverting input; and
a second variable current source coupled to the inverting input, and to the output via the voltage divider, such that increasing a current from the second variable current source decreases a voltage at the output.

US Pat. No. 10,141,899

BROADBAND RADIO FREQUENCY POWER AMPLIFIERS, AND METHODS OF MANUFACTURE THEREOF

NXP USA, INC., Austin, T...

1. A packaged amplifier device having a bandwidth defined by a range of frequencies between a low cutoff frequency and an upper cutoff frequency, the amplifier device comprising:an input lead configured to receive an input radio frequency (RF) signal;
an output lead configured to produce an amplified RF signal;
a reference node;
a transistor die that includes
a first node,
a second node,
a transistor having a gate, a first current conducting terminal coupled to the output lead, and a second current conducting terminal coupled to the reference node,
a first integrated capacitance having a first terminal coupled to the first node, and a second terminal coupled to the reference node,
a first inductance having a first terminal coupled to the first node, and a second terminal coupled to the second node, and
a second integrated capacitance having a first terminal coupled to the second node, and a second terminal coupled to the reference node; and
a second inductance having a first terminal coupled to the input lead and a second terminal coupled to the first node of the transistor die,
wherein the first inductance, the first integrated capacitance, the second inductance, and the second integrated capacitance form a multiple pole filter of an input impedance matching circuit that is configured to filter the input RF signal to produce a filtered RF signal at the gate of the transistor, and wherein a first pole of the multiple pole filter is positioned at a first frequency within the bandwidth, and a second pole of the multiple pole filter is positioned at a second frequency outside the bandwidth.

US Pat. No. 10,141,898

HIGH CURRENT LOW-COST DC COUPLED DAC FOLLOWER LOW PASS FILTER HEADPHONE AMPLIFIER

TYMPHANY HK LIMITED, Hon...

1. A digital-to-analog converter (DAC) circuit comprising:a pair of output stages, each output stage comprising:
a DAC configured to convert a digital audio signal into an analog audio signal;
an low-pass filter circuit including an operational amplifier in signal communication with the DAC, the operation amplifier configured to generate a filtered analog signal based on the analog audio signal; and
an amplifier network in signal communication with the operational amplifier to generate an amplified audio signal based on the filtered analog signal,
wherein the operational amplifier includes a feedback circuit path including a first node connected to the output of the amplifier network and a second node connected to the input of the operational amplifier,
wherein the amplifier network is electrically nested in the feedback circuit path, and
wherein each output stage includes a DC servo circuit configured to equalize an impedance of the operational amplifier.

US Pat. No. 10,141,897

SOURCE FOLLOWER

SILICON INTERGRATED SYSTE...

1. A source follower, comprising:a first transistor having a first terminal, a second terminal and a control terminal, with the first terminal of the first transistor configured to receive a first base voltage, the second terminal of the first transistor electrically connected to a first output terminal, the control terminal of the first transistor configured to receive a first control voltage, and the first transistor configured to generate a first current according to the first control voltage;
a first output module electrically connected to the first output terminal and providing an output voltage to the first output terminal according to an input voltage signal and the first current;
a second transistor having a first terminal, a second terminal and a control terminal, with the first terminal of the second transistor configured to receive the first base voltage, the second terminal of the second transistor electrically connected to a second output terminal, the control terminal of the second transistor configured to receive the first control voltage and the second transistor configured to generate a second current according to the first control voltage;
a second output module electrically connected to the second output terminal and providing a common-mode voltage to the second output terminal according to a second base voltage and the second current; and
a feedback module electrically connected to the control terminal of the first transistor, the control terminal of the second transistor and a reference node in the second output module, the feedback module configured to regulate a voltage level of the reference node and a voltage level of the first control voltage according to a reference voltage, wherein the feedback module comprising:
an amplifier, with a first input terminal of the amplifier configured to receive the reference voltage, a second input terminal of the amplifier electrically connected to the reference node, an output terminal of the amplifier electrically connected to the control terminal of the first transistor and the control terminal of the second transistor, and the amplifier providing the first control voltage through the output terminal.

US Pat. No. 10,141,896

CURVE FITTING CIRCUIT, ANALOG PREDISTORTER, AND RADIO FREQUENCY SIGNAL TRANSMITTER

Huawei Technologies Co., ...

1. A curve fitting circuit, comprising:n segmentation processing circuits, wherein n is greater than or equal to 2; and
q first adder circuits, wherein q is a natural number;
wherein each segmentation processing circuit of the n segmentation processing circuits is configured to:
receive an input signal;
intercept a part of the input signal according to a preset rule;
generate a to-be-processed signal according to the intercepted part; and
generate q output signals according to the to-be-processed signal using a polynomial fitting method, wherein parts of the input signal intercepted by different segmentation processing circuits are not exactly the same; and
wherein each first adder circuit is configured to:
receive one signal in the q output signals of each segmentation processing circuit; and
obtain one output signal of the curve fitting circuit according to a sum of received n signals, wherein different first adder circuits receive different output signals in q output signals of a same segmentation processing circuit.

US Pat. No. 10,141,895

SYSTEMS AND METHODS FOR OPTIMIZING AMPLIFIER OPERATIONS

pSemi Corporation, San D...

3. A system for optimizing amplifier operations, including:an amplifier configured to receive an input signal and generate an output signal therefrom having a desired characteristic that includes at least one of a power level, a voltage range, or a current level; and
a feed-forward control circuit including a look-up table and configured to receive the input signal, analyze the input signal using a circuit element detector configured to measure component parameters of coupled circuit elements, apply the analyzed input signal to the look-up table to generate a control signal as a function of the analyzed input signal, and provide the control signal to the amplifier to modify at least one operating characteristic of the amplifier, thereby altering the desired characteristic of the output signal.

US Pat. No. 10,141,894

RADIO FREQUENCY (RF) AMPLIFIER

QUALCOMM Incorporated, S...

1. A circuit, comprising:a first amplifier path comprising a first amplifier, MA;
a second amplifier path comprising a cascode device and a second amplifier, MB;
a node defined by a source of the cascode device and a drain of the second amplifier, MB;
a capacitance coupled between the node and a source of the second amplifier, MB; and
an input configured to receive a radio frequency signal, the input being coupled to a gate of the first amplifier, MA, and to a gate of the second amplifier, MB.

US Pat. No. 10,141,893

INPUT STAGE OF AN AMPLIFIER AND CORRESPONDING AMPLIFIER

Devialet, Paris (FR)

1. An input stage of an amplifier comprising:an input for the digital signal to be converted;
a voltage output for the converted voltage;
a digital-to-analog converter, the input of which forms the input for the digital signal to be converted, the digital-to-analog converter comprising a signal terminal for generating a current;
a resistance for converting the current into a voltage, connected to said voltage output and to a reference potential; and
a current-voltage converter with a voltage output, connected to said signal terminal and to said voltage output, the current-voltage converter comprising a transistor such that the gate of the transistor is connected to a voltage source, the drain of the transistor is connected to a current source and the source of the transistor is connected to said digital-to-analog converter, the current source generating a continuous current,wherein the source of said transistor is exclusively connected to said signal terminal of said digital-to-analog converter and wherein said digital-to-analog converter is able to generate a current comprising a continuous component and a fixed component, the current source being able to provide a current equal to the continuous component of the current generated by said digital-to-analog converter, said digital-to-analog converter being connected between a fixed potential and the source of said transistor.

US Pat. No. 10,141,892

BIAS CIRCUIT FOR SUPPLYING A BIAS CURRENT TO A RF POWER AMPLIFIER

RAFAEL MICROELECTRONICS, ...

1. A bias circuit for supplying a bias current to an RF power amplifier, said bias circuit comprising:a first bipolar transistor having a base terminal, a collector terminal and an emitter terminal, wherein the emitter terminal is electrically coupled to the RF power amplifier;
a first voltage reference circuit for clamping a first terminal of first voltage reference circuit at a first reference voltage, wherein the first terminal of the first voltage reference circuit is electrically coupled to base terminal of the first bipolar transistor through a first resistive component, and a second terminal of the first voltage reference circuit is electrically coupled to a ground; and
a second voltage reference circuit for clamping a first terminal of second voltage reference circuit at a second reference voltage, wherein the first terminal of the second voltage reference circuit is electrically coupled to the first terminal of the first voltage reference circuit transistor through a second resistive component, and a second terminal of the second voltage reference circuit is electrically coupled to the ground;
wherein a first terminal of the second voltage reference circuit is electrically coupled to a voltage supply through a third resistive component so as to generate a bias current to the RF power amplifier through the emitter terminal of the first bipolar transistor;
wherein the first resistive component, the second resistive component and the third resistive component are connected in series one by one in a conductive path connecting the base terminal of the first bipolar transistor to the voltage supply, wherein the second resistive component is located between the first resistive component and the third resistive component in said conductive path.

US Pat. No. 10,141,891

POWER AMPLIFIER WITH SUPPLY SWITCHING

Avago Technologies Genera...

1. A power amplifier, comprising:a gain circuit;
a supply switch circuit configured to:
detect a magnitude of an outgoing broadband communication signal; and
determine whether the magnitude of the outgoing broadband communication signal exceeds a predetermined voltage threshold;
a first bias transformer coupled to a first voltage supply rail and configured to bias the gain circuit with the first voltage supply rail;
a second bias transformer coupled to a second voltage supply rail and configured to bias the gain circuit with the second voltage supply rail; and
a capacitive coupling combiner coupled to the first bias transformer and the second bias transformer and configured to reduce a residual flux change between the first bias transformer and the second bias transformer,
wherein the gain circuit is configured to:
apply a first gain to the outgoing broadband communication signal using a first voltage supply rail when it is determined that the magnitude exceeds the predetermined voltage threshold;
apply a second gain to the outgoing broadband communication signal using a second voltage supply rail when it is determined that the magnitude does not exceed the predetermined voltage threshold, the second voltage supply rail being smaller than the first voltage supply rail; and
produce an output signal from the outgoing broadband communication signal with the applied first gain or the applied second gain,
wherein a current of the outgoing broadband communication signal is switched between the first voltage supply rail and the second voltage supply rail in response to the magnitude being detected by the supply switch circuit.

US Pat. No. 10,141,890

POWER AMPLIFIER MODULE

MURATA MANUFACTURING CO.,...

1. A power amplifier module comprising:an amplifier transistor having a plurality of fingers and to which a first power supply voltage or a second power supply voltage is supplied based on a mode signal supplied to the power amplifier module, the amplifier transistor receiving a first signal and outputting a second signal obtained by amplifying the first signal; and
a bias circuit that supplies a bias current to the amplifier transistor, the bias circuit including:
a plurality of bias transistors connected in parallel, each of the plurality of bias transistors being turned ON by a bias control voltage based on a mode signal indicating an operation mode to be used to amplify the first signal;
a first resistor;
a common node, wherein the first resistor is connected at a first end to an emitter of a first of the plurality of bias transistors and at a second end to the common node, and wherein an emitter of a second of the plurality of bias transistors is connected to the common node; and
a plurality of resistors, wherein each one of the plurality of resistors is connected at a first end to the common node and at a second end to a respective one of the plurality of fingers of the amplifier transistor.

US Pat. No. 10,141,889

SEMICONDUCTOR INTEGRATED CIRCUIT, SENSOR READER, AND SENSOR READOUT METHOD

Mitsubishi Electric Corpo...

1. A semiconductor integrated circuit comprising:a plurality of first amplifiers, each first amplifier of the plurality of first amplifiers amplifying a sensor signal input from a corresponding sensor element of a plurality of sensor elements;
a plurality of first switches, each first switch of the plurality of first switches connecting to an output of a first amplifier to perform switching between conducting and blocking of the output;
a second switch to perform switching of a sensor amplification signal output via a first switch from the first amplifier, the switching of the second switch being between closing to conduct to, and opening to block, an external output terminal; and
a control circuit to cause:
when the second switch is closed, operating of the first switches so that sensor amplification signals output from the plurality of first amplifiers are output sequentially one at a time; and
when the second switch is open, setting a bias current and a gain of at least one first amplifier of the plurality of first amplifiers to second setting values that are lower than first setting values, the first setting values being the bias current and the gain when the second switch is closed.

US Pat. No. 10,141,888

DOUBLE BALANCED MIXER

pSemi Corporation, San D...

1. A double balanced mixer fabricated as an integrated circuit and configured to be coupled to both (1) a first balun having an unbalanced side configured to pass a local oscillator (LO) signal and a pair of ports on a balanced side and (2) a second balun having an unbalanced side configured to pass a radio frequency (RF) signal and a pair of ports on a balanced side, the double balanced mixer including:a four-node ring including four branches, each branch including at least one low threshold voltage field effect transistor (FET) having a close-to-zero turn-on voltage, each FET having a source, a drain, and a gate, wherein the source of each FET is connected to the drain of a next FET in the four-node FET ring and the gate and the drain of each FET are connected together as a diode,
wherein a first pair of opposing nodes of the four-node FET ring are configured to be connected to the pair of ports on the balanced side of the first balun, and a second pair of opposing nodes of the four-node FET ring are configured to be connected through corresponding capacitors to the pair of ports on the balanced side of the second balun.

US Pat. No. 10,141,887

OSCILLATOR FOR DETECTING TEMPERATURE OF ATMOSPHERE

NIHON DEMPA KOGYO CO., LT...

1. An oscillator that detects a temperature of an atmosphere where a crystal resonator providing an oscillation output is placed using a temperature detector to stabilize the temperature by controlling a temperature of a heater based on a temperature detection value, the oscillator comprising:a buffer amplifier interposed in a signal path of a control signal generated based on the temperature detection value;
a heater constituted of a transistor having a collector and an emitter positioned between a power source unit and a ground, and a base connected to an output port of the buffer amplifier; and
a first differential amplifier disposed to adjust a gain of the buffer amplifier so as to cancel a voltage fluctuation of the power source unit, the first differential amplifier amplifying a difference between a voltage corresponding to a voltage of the power source unit and a preliminarily set voltage to input to a gain adjustment port of the buffer amplifier.

US Pat. No. 10,141,886

METHOD AND APPARATUS FOR EXTRACTING ELECTRICAL ENERGY FROM PHOTOVOLTAIC MODULE

Techinvest-Eco, Limited L...

1. An apparatus for electrical energy take-off from a photovoltaic module (PVM), the apparatus comprising:one of
a DC/AC inverter having a maximum power not less than a nominal power of the PVM, and configured to connect an output of the DC/AC inverter to a local AC electrical power distribution system, or
a DC/DC converter having a maximum power not less than the nominal power of the PVM, and configured to connect to an input of an energy storage system;
a capacitor connected in parallel between the PVM and one of an input of the DC/AC inverter or an input of the DC/DC converter;
a means for voltage measurement on the capacitor; and
a control module connected to one of the DC/AC inverter or the DC/DC converter and further connected to the means for voltage measurement on the capacitor,
wherein the DC/AC inverter and the DC/DC converter are configured to switch between at least three power levels,
wherein the means for voltage measurement is configured to supply data to the control module regarding at least three predetermined fixed values of the capacitor voltage, the control module is configured to switch the at least three power levels of one of the DC/AC inverter or the DC/DC converter depending on the capacitor voltage,
wherein an internal resistance of the capacitor is at least half of an internal resistance of the PVM at a maximum power point (MPP) of the PVM, and
wherein capacity of the capacitor is defined as follows:
C?(k*PB)/(UB2?U12),
where
C is capacitance of the capacitor in Farads (F);
PB is maximal power of PVM under its maximal insolation in Watts (W);
UB is voltage of PVM at the maximum power point under maximal insolation in Volts (V);
U1 is an intermediate fixed voltage at the maximum power point under insolation that is less than maximal insolation closest to the UB in Volts (V); and
k is a factor with an absolute value of 0.3-0.5 seconds (sec).

US Pat. No. 10,141,885

FLOATING SOLAR PANEL SYSTEMS

1. A floating solar system, comprising:a border pontoon adapted to float on water defining a closed peripheral shape surrounding an interior space;
an array of interconnected photovoltaic panels distributed within the peripheral shape and structurally supported by support cables extending across between sides of the pontoon so as to span the interior space, each photovoltaic panel having a flotation device secured thereto so that the array is at least partially buoyant, the photovoltaic panels being electrically connected; and
a stabilizing skirt downwardly-depending from the border pontoon to surround a column of water underneath the array of photovoltaic panels, the skirt being weighted to remain substantially vertical in the water and forming a barrier around the column of water so as to create a more stable volume of water within the peripheral shape than outside of the border pontoon, wherein the skirt has a depth that is between about 10-40% of the width of the closed peripheral shape.

US Pat. No. 10,141,884

COOLING FAN FILTERING

Dell Products L.P., Roun...

5. An apparatus for cooling a system component of an information handling system, the apparatus comprising:at least one cooling fan configured to cool the system component; and
a controller coupled to the at least one cooling fan to apply a filtered first PWM control signal to the at least one cooling fan,
wherein the controller is configured to perform steps for controlling the at least one cooling fan comprising:
generating a first pulse width modulation (PWM) control signal for controlling the at least one cooling fan; and
filtering the first PWM control signal to generate the filtered first PWM control signal, the filtering comprising dampening the first PWM control signal such that a rate of change of the filtered first PWM control signal is decreased as a target process value is approached,
wherein the step of dampening the first PWM control signal comprises generating a new PWM control signal by adding the filtered first PWM control signal to a product of a gain parameter multiplied by a second parameter proportional to a difference between the first PWM control signal and the filtered first PWM control signal, and wherein the controller is further configured to apply the new PWM control signal to the at least one cooling fan.

US Pat. No. 10,141,883

INPUT STAGE FOR A MOTOR CONTROLLER, AND MOTOR CONTROLLER, ESPECIALLY FOR AN ELECTRIC MOTOR

ZIEHL-ABEGG SE, Kunzelsa...

1. An input stage for a motor controller, in particular a motor controller for an electric motor, wherein the input stage has an input for inputting an input signal, and an output for connecting to the motor controller, wherein the input stage is designed to generate a control signal from an input signal between a first voltage Uunten and a second voltage Uoben>Uunten, and to output the control signal as a target value parameter to the motor controller via the output, characterized by a first comparator for comparing the input signal with a first threshold voltage US1>oben, and a data output unit, wherein the data output unit generates a communication signal on the basis of at least a portion of the input signal, wherein the first comparator outputs an activation signal when the first threshold voltage US1 has been reached or exceeded by the input signal, which activates an outputting of the communication signal to the output by the data output unit.

US Pat. No. 10,141,882

MOTOR HEALTH MONITORING AND MEDICAL DEVICE INCORPORATING SAME

Medtronic MiniMed, Inc., ...

1. A method of detecting degradation in a drive system including a motor, the method comprising:applying a modulated voltage to the motor;
adjusting a duty cycle of the modulated voltage to achieve a commanded rotation of a rotor of the motor; and
identifying a degradation condition based on the duty cycle.

US Pat. No. 10,141,881

APPARATUS FOR CONTROLLING INVERTER

LSIS CO., LTD., Anyang-s...

1. An apparatus for controlling an inverter contained in an inverter system configured to drive a motor, comprising:a slip frequency decision unit configured to determine a first slip frequency to be used for compensation of a frequency of a first reference voltage, not only using a first reference voltage (including an amplitude and frequency) of the first reference voltage applied to the inverter, but also using an output current of the motor or a rotor speed of the motor; and
a reference voltage generation unit configured to determine not only a frequency of a second reference voltage achieved by compensation of the first slip frequency, but also an amplitude of the second reference voltage corresponding to the frequency of the second reference voltage, and apply the second reference voltage to the inverter,
wherein the slip frequency decision unit includes:
a closed-loop controller configured to determine a second slip frequency using the rotor speed of the motor; and
an open-loop controller configured to determine a third slip frequency, using an output current of the motor, the amplitude and frequency of the first reference voltage, and a nominal value of the motor.

US Pat. No. 10,141,880

DRIVING CIRCUIT FOR VOICE COIL MOTOR HAVING A FIRST DRIVER COUPLED TO A FIRST END OF A COIL AND A SECOND DRIVER COUPLED TO A SECOND END OF THE COIL

ROHM CO., LTD., Kyoto (J...

1. A driving circuit that supplies a bi-directional driving current to a voice coil motor, the driving circuit comprising:a current detection circuit structured to generate a detection voltage VS represented by VS=VREF+k×IDRV, with the driving current as IDRV, with a reference voltage as VREF, and with a gain as k;
an error amplifier structured to amplify a difference between the detection voltage VS and a control voltage that indicates a position of the voice coil motor so as to generate an error voltage;
a first driver having its output to be coupled to a first end of a coil of the voice coil motor, and structured to switch the driving current between a state in which the driving current flows as a source current and a state in which the driving current flows as a sink current according to the error voltage; and
a second driver having its output to be coupled to a second end of the coil of the voice coil motor, and structured to switch the driving current between a state in which the driving current flows as a sink current and a state in which the driving current flows as a source current according to the error voltage,
wherein a level of the reference voltage VREF is settable externally.

US Pat. No. 10,141,879

MOTOR CONTROL APPARATUS, SHEET CONVEYANCE APPARATUS, DOCUMENT FEEDING APPARATUS, DOCUMENT READING APPARATUS, AND IMAGE FORMING APPARATUS

Canon Kabushiki Kaisha, ...

1. A motor control apparatus to control a motor based on an instructed phase indicating a target phase of a rotor of the motor, the motor control apparatus comprising:a detector configured to detect a driving current flowing through a winding of the motor;
a phase determiner configured to determine a rotation phase of the rotor based on the driving current detected by the detector;
a converter configured to convert a current value in a stationary coordinate system which is detected by the detector into a current value in a rotational coordinate system based on the rotation phase determined by the phase determiner; and
a controller including a first control mode for controlling the driving current in a manner that a magnitude of the driving current detected by the detector becomes a target value set in a manner that a phase deviation between the instructed phase indicating the target phase of the rotor of the motor and the rotation phase determined by the phase determiner is decreased, and a second control mode for controlling the driving current based on a current having a previously determined magnitude,
wherein, in a case where the control mode for controlling the driving current is switched from the second control mode to the first control mode, the target value in the first control mode is set based on a value of a torque current component of the driving current detected by the detector during execution of the second control mode, and
wherein the torque current component corresponds to a current component represented by the rotational coordinate system of the driving current converted by the converter.

US Pat. No. 10,141,878

CONTROLLER FOR PERMANENT MAGNET SYNCHRONOUS MOTOR, AND CONTROL METHOD FOR ESTIMATING INITIAL POSITION OF ROTOR

KONICA MINOLTA, INC., To...

1. A controller for a sensorless permanent magnet synchronous motor having a rotor using a permanent magnet, the rotor rotating by a rotating magnetic field caused by a current flowing through an armature, the controller comprising:a drive portion configured to apply a voltage to the armature to drive the rotor;
an initial position estimating portion configured to estimate an initial position which is a position of magnetic poles of the rotor which is in a stop state; and
a control unit configured to control the drive portion; wherein
the initial position estimating portion gives instructions to the control unit to apply a pulse voltage for generating a magnetic field vector for searching for the initial position to each of search sections obtained by dividing a target range narrows down a target range in such a manner that a search section in which a largest amount of current flows through the armature by application of the pulse voltage is selected as a subsequent target range, and estimates the initial position.

US Pat. No. 10,141,877

CONTROLLER FOR PERMANENT MAGNET SYNCHRONOUS MOTOR, CONTROL METHOD, AND IMAGE FORMING APPARATUS

Konica Minolta, Inc., Ch...

1. A controller for a permanent magnet synchronous motor having a rotor using a permanent magnet, the rotor rotating by a rotating magnetic field caused by a current flowing through an armature, the controller comprising:a drive portion configured to feed a current to the armature to drive the rotor;
a speed estimating portion configured to estimate a rotational speed of the rotor based on the current flowing through the armature;
a magnetic pole position estimating portion configured to estimate a position of magnetic poles of the rotor based on an estimated speed that is the rotational speed estimated;
a control unit configured to control, based on an estimated angle that is an estimated value of the position of magnetic poles outputted by the magnetic pole position estimating portion, the drive portion to cause the rotating magnetic field rotating at a target speed indicated in an inputted speed command;
a step-out presuming portion configured to presume, based on the target speed and the estimated speed, whether or not a step-out occurs; and
a correction portion configured to correct the estimated angle when the step-out presuming portion presumes that a step-out occurs; wherein
when the correction portion corrects the estimated angle, the control unit controls, based on a post-correction estimated angle that is the estimated angle corrected by the correction portion, the drive portion to cause the rotating magnetic field depending on the target speed.

US Pat. No. 10,141,876

POWER GENERATOR SYSTEM, POWER GENERATOR CONTROL DEVICE, AND POWER-GENERATION BALANCE CONTROL METHOD FOR POWER GENERATOR SYSTEM

Mitsubishi Electric Corpo...

1. A generator system, comprising:a first generator control device comprising a first PWM signal generation part configured to generate a first PWM signal, the first generator control device being configured to control, based on the first PWM signal, a first field current to be supplied to a field coil of a first generator; and
a second generator control device comprising a second PWM signal generation part configured to generate a second PWM signal, the second generator control device being configured to control, based on the second PWM signal, a second field current to be supplied to a field coil of a second generator, wherein:
the first generator control device further comprises a duty restriction part configured to use a duty lower limit value that is more than 0% and a duty upper limit value that is less than 100% to perform, every X cycles, duty restriction processing on the first PWM signal generated by the first PWM signal generation part in continuous Y cycles out of the X cycles, and to transmit the first PWM signal after the restriction processing to the second generator control device;
the second generator control device further comprises a signal output control part configured to:
receive the first PWM signal after the restriction processing transmitted from the duty restriction part as a received PWM signal;
determine that a reception abnormality exists when the received PWM signal is received continuously in (X?Y+1) cycles as a signal representing a duty less than the duty lower limit value or a duty more than the duty upper limit value;
control the second field current based on the second PWM signal generated by the second PWM signal generation part in a cycle in which the reception abnormality is determined to exist; and
control the second field current based on the received PWM signal in a cycle in which the reception abnormality is not determined to exist; and
X and Y are integers satisfying X>Y>0.

US Pat. No. 10,141,873

SHOCK DETECTOR CIRCUIT AND METHOD FOR OPERATION THEREOF

1. An electronic device comprising:calculation circuitry configured to generate a signal representative of a physical magnitude, for a motor driving a display device, said motor comprising a rotor in a magnetic circuit, two terminals, one positive and one negative, via which the calculation circuitry controls the motor,
two shock detector circuits, each shock detector circuit being connected between the calculation circuitry and one of the two terminals for the detection of an external shock applied to the motor,
said motor having a first position of stable equilibrium placed at a reference angular position and a second position of stable equilibrium placed at 180° from the first stable angular position, for each direction of rotation, a maximum angular position from which the rotor is unable to return to a prior angular position, and
the calculation circuitry using an algorithm which, following a shock, detects the direction of rotation of the rotor by analysing an induced voltage detected by said shock detector circuit and sends a blocking pulse of reverse polarity to that of the induced voltage to stop and return the rotation,
wherein the blocking pulse has a maximum duration of 58.5 ms to stop and return the rotor to a predetermined angular position before the rotor reaches the maximum angular position.

US Pat. No. 10,141,871

METHOD AND SYSTEM FOR CONTROLLING A CONTROL INSTALLATION OF AN ELECTRIC MOTOR

SCHNEIDER TOSHIBA INVERTE...

10. A control system associated with a control installation, which includes:a number of input phases, which are designed for connection to an electric grid system for the delivery of an AC voltage,
a common mode filter connected on the input phases, comprising at least one inductance,
a DC supply bus, which is arranged for the delivery of a DC voltage,
a first converter connected to said DC supply bus, controlled for the application of the first voltage pulse edges to an electric motor by a first pulse width modulation, obtained by comparing a first carrier signal, described as the reference carrier signal, applied at a first chopping frequency, with a first modulating signal,
a second converter connected to said DC supply bus and controlled by a second pulse width modulation, obtained by comparing a second carrier signal, applied at a second chopping frequency, with a second modulating signal, and
said second carrier signal being designed to be out-of-phase with the reference carrier signal by a phase-shift angle, the control system comprising:
circuitry configured to determine an optimum phase-shift angle from the first chopping frequency and the second chopping frequency, wherein said optimum phase-shift angle corresponds to a phase-shift angle for which a maximum magnetic flux received by the inductance of the common mode filter is at a minimum.

US Pat. No. 10,141,870

AUTOMATED VERIFICATION TESTING FOR A MOTOR CAPACITOR

MJG INNOVATIONS, LLC, Fo...

1. A motor capacitor verification system comprising:a capacitor selection electrical circuit coupled to an electric motor, said electric motor employing a motor capacitor for its operation, said capacitor selection electrical circuit configured to connect said motor capacitor for verification testing;
a capacitor testing electrical circuit coupled to said capacitor selection electrical circuit and configured to evaluate said motor capacitor for operation with said electric motor; and
an AC power control electrical circuit coupled to said capacitor testing electrical circuit, said AC power control electrical circuit configured to only permit application of an AC operating voltage to said electric motor and said motor capacitor after a successful motor capacitor verification as required for operation of said electric motor.

US Pat. No. 10,141,869

IMPEDANCE COMPENSATION

DET International Holding...

1. Method for operating a power converter that delivers output current into a grid, including the steps ofa) determining the output current of the power converter,
b) monitoring an output voltage of the power converter;
c) controlling the output current in order to prevent the output voltage from exceeding an output voltage limit,
d) adjusting the output voltage limit to compensate for a voltage variation due to a line impedance of a line between the power converter and the grid, wherein the output voltage limit can be higher than a maximum voltage allowed at the grid without the output voltage exceeding the output voltage limit thereby allowing an efficient use of an available output power of the power converter in a wider operating range.

US Pat. No. 10,141,867

SWITCHING CONTROL CIRCUIT WITH SIGNAL PROCESS TO ACCOMMODATE THE SYNCHRONOUS RECTIFIER OF POWER CONVERTERS

SEMICONDUCTOR COMPONENTS ...

1. A switching control circuit for a power converter, comprising:an input circuit coupled to receive a feedback signal wherein the feedback signal is correlated to an output of the power converter; and
a clock generator configured to generate a clock signal having a frequency to control a switching frequency of a switching signal wherein the switching signal is configured to control switching of a transformer of the power converter for regulating the output of the power converter; and
the switching control circuit configured to reduce a pulse width of the switching signal without changing the frequency of the clock signal and thereafter increase the frequency of the clock signal.

US Pat. No. 10,141,866

MULTI-LEVEL INVERTER WITH FIRST AND SECOND SWITCH BANKS

THE UNIVERSITY OF NORTH C...

1. A system for converting direct current (DC) to alternating current (AC), the system comprising:a DC bus comprising a positive DC rail and a negative DC rail to receive a DC input voltage;
a first capacitor electrically coupled to the positive DC rail;
a second capacitor;
a third capacitor electrically coupled to the negative DC rail, wherein the first capacitor, the second capacitor and the third capacitor are electrically coupled in series between the positive DC rail and the negative DC rail,
a first pole switch bank comprising a plurality of first pole switches;
a first pole electrically coupled to the first pole switch bank;
a second pole switch bank comprising a plurality of second pole switches;
a second pole electrically coupled to the second pole switch bank; and
a control circuit comprising at least one processor programmed to alternately switch the first pole switch bank and the second pole switch bank to:
a first state of the first pole switch bank in which the first pole is electrically coupled to the positive DC rail;
a second state of the first pole switch bank in which the first pole is electrically coupled between the first capacitor and the second capacitor;
a third state of the first pole switch bank in which the first pole is electrically coupled to the negative DC rail;
a fourth state of the first pole switch bank in which the first pole is electrically coupled between the second capacitor and the third capacitor;
a first state of the second pole switch bank in which the second pole is electrically coupled to the positive DC rail;
a second state of the second pole switch bank in which the second pole is electrically coupled between the first capacitor and the second capacitor;
a third state of the second pole switch bank in which the second pole is electrically coupled between the second capacitor and the third capacitor; and
a fourth state of the second pole switch bank in which the second pole is electrically coupled to the negative DC rail,
wherein during a first period, cycle the first pole switch bank and the second pole switch bank sequentially back-and-forth-between:
(a) the first pole switch bank being in the first state of the first pole switch bank and the second pole switch bank being in the third state of the second pole switch bank;
(b) the first pole switch bank being in the first state of the first pole switch bank and the second pole switch bank being in the fourth state of the second pole switch bank; and
(c) the first pole switch bank being in the second state of the first pole switch bank and the second pole switch bank being in the fourth state of the second pole switch bank.

US Pat. No. 10,141,864

INVERTER APPARATUS INCLUDING CONTROL CIRCUIT EMPLOYING TWO-PHASE MODULATION CONTROL, AND INTERCONNECTION INVERTER SYSTEM INCLUDING THE INVERTER APPARATUS

DAUHEN Corporation, Osak...

1. A control circuit for controlling driving of a plurality of switches in a power conversion circuit related to three-phase alternating current power with use of PWM signals,the PWM signals being generated and output such that a waveform of an alternating current phase voltage output from or input to the power conversion circuit is a waveform that is continuously at a predetermined lower limit voltage value for a predetermined period of one cycle and is continuously at a predetermined upper limit voltage value for another predetermined period of the one cycle,
the control circuit comprising a command value signal generator and a PWM signal generator, wherein
the command value signal generator generates a first command value signal, a second command value signal and a third command value signal, each of the three command value signals having a one-cycle waveform that is at a predetermined upper limit value for a first period and is at a predetermined lower limit value for a second period, and
the PWM signal generator generates the PWM signals by comparing each command value signal with a predetermined carrier signal that has a frequency such that at least three cycles of waves of the carrier signal are contained within each of the first period and the second period, and three times a reciprocal of the frequency is smaller than said each of the first period and the second period,
wherein each of the first period and the second period is ? of one cycle of each of the three command value signals, the second command value signal being delayed in phase by 2?/3 relative to the first command value signal, the third command value signal being delayed in phase by 4?/3 relative to the first command value signal,
wherein the one-cycle waveform of the first command value signal is the lower limit value in a ? period,
a waveform obtained by shifting a waveform of a sine wave whose phase is in a section from 3?/2 to 11?/6 by a predetermined value in a next ? period,
a waveform obtained by shifting a waveform of a sine wave whose phase is in a section from ?/6 to ?/2 by a predetermined value in a next ? period,
the upper limit value in a next ? period,
a waveform obtained by shifting a waveform of a sine wave whose phase is in a section from ?/2 to 5?/6 by a predetermined value in a next ? period, and
a waveform obtained by shifting a waveform of a sine wave whose phase is in a section from 7?/6 to 3?/2 by a predetermined value in a next ? period;
wherein the command value signal generator generates, through the following method, the first to third command value signals using three phase voltage command value signals generated for specifying respective waveforms of three phases of phase voltages to be output from the power conversion circuit and using three line-to-line voltage command value signals that are difference signals between the phase voltage command value signals:
(a) hereinafter, the three phases are called a U phase, a V phase, and a W phase, the V phase being delayed by 2?/3 relative to the U phase, and the W phase being delayed by 4?/3 relative to the U phase; the phase voltage command value signals of the U phase, the V phase, and the W phase are called Xu, Xv, and Xw respectively; and a line-to-line voltage command value signal obtained by subtracting Xv from Xu is called Xuv, a line-to-line voltage command value signal obtained by subtracting Xw from Xv is called Xvw, and a line-to-line voltage command value signal obtained by subtracting Xu from Xw is called Xwu;
(b) in a case where an absolute value of Xu is greater than an absolute value of Xv and an absolute value of Xw, if Xu is a positive value, the first command value signal Xu3 is set to the upper limit value, the second command value signal Xv3 is set to a value obtained by subtracting Xuv from the upper limit value, and the third command value signal Xw3 is set to a value obtained by adding Xwu to the upper limit value;
(c) in a case where an absolute value of Xu is greater than an absolute value of Xv and an absolute value of Xw, if Xu is a negative value, Xu3 is set to the lower limit value, Xv3 is set to a value obtained by subtracting Xuv from the lower limit value, and Xw3 is set to a value obtained by adding Xwu to the lower limit value;
(d) in a case where an absolute value of Xv is greater than an absolute value of Xu and an absolute value of Xw, if Xv is a positive value, Xu3 is set to a value obtained by adding Xuv to the upper limit value, Xv3 is set to the upper limit value, and Xw3 is set to a value obtained by subtracting Xvw from the upper limit value;
(e) in a case where an absolute value of Xv is greater than an absolute value of Xu and an absolute value of Xw, if Xv is a negative value, Xu3 is set to a value obtained by adding Xuv to the lower limit value, Xv3 is set to the lower limit value, and Xw3 is set to a value obtained by subtracting Xvw from the lower limit value;
(f) in a case where an absolute value of Xw is greater than an absolute value of Xu and an absolute value of Xv, if Xw is a positive value, Xu3 is set to a value obtained by subtracting Xwu from the upper limit value, Xv3 is set to a value obtained by adding Xvw to the upper limit value, and Xw3 is set to the upper limit value; and
(g) in a case where an absolute value of Xw is greater than an absolute value of Xu and an absolute value of Xv, if Xw is a negative value, Xu3 is set to a value obtained by subtracting Xwu from the lower limit value, Xv3 is set to a value obtained by adding Xvw to the lower limit value, and Xw3 is set to the lower limit value.

US Pat. No. 10,141,863

POWER CONVERSION APPARATUS

TOSHIBA TEC KABUSHIKI KAI...

1. A power conversion apparatus, comprising:a first LC circuit directly connected in series with a power supply that supplies an input power having a current varying over time at an input frequency to a power output having at least periodic constant current;
a second LC circuit coupled in series with a load;
a first switch and a first diode coupled between ground and a node intermediate of the first LC circuit and the second LC circuit, the first LC circuit, the power supply, and the first diode forming a closed-loop;
a second switch and a second diode coupled between the node and a smoothing capacitance;
a controller that opens or closes the first and second switches at a frequency greater than the input frequency;
a first series circuit having the first LC circuit directly connected to the input power, the second diode, and a third capacitor.

US Pat. No. 10,141,862

POWER SUPPLY DEVICE

Ford Global Technologies,...

1. A vehicle comprising:an electric machine;
a power controller having inverting circuitry and an inductor and configured to deliver electrical power to the electric machine; and
a cooling system having first, second, and third substantially parallel cooling plates, and arranged such that the inverting circuitry and inductor are disposed on opposing sides of the second cooling plate, and the power controller is sandwiched between the first and third cooling plates.

US Pat. No. 10,141,861

POWER CONVERSION UNIT, POWER CONVERTER AND METHOD OF MANUFACTURING POWER CONVERTER

Hitachi, Ltd., Tokyo (JP...

1. A power conversion unit comprising:a circuit connection part including a plurality of conductors having different potentials, that is, at least a positive electrode conductor having an external positive terminal, at least a negative electrode conductor having an external negative terminal, and at least an AC conductor having an external AC terminal, wherein the circuit connection part has an approximately flat plate-like structure with a front side and a rear side;
a power semiconductor module connected to some of the plurality of conductors at the rear side of the circuit connection part; and
at least a capacitor connected to some of the plurality of conductors at the rear side of the circuit connection part,
wherein the positive electrode conductor is connectable to a different positive electrode conductor of a different power conversion unit through a unit connection part that is connected to the positive electrode conductor at the front side of the circuit connection part, and
wherein the negative electrode conductor is connectable to a different negative electrode conductor of the different power conversion unit through the unit connection part that is connected to the negative electrode conductor at the front side of the circuit connection part.

US Pat. No. 10,141,860

CONVERTER WITH DC LINK

SIEMENS AKTIENGESELLSCHAF...

1. A converter with a DC link for converting an input voltage into an alternating voltage with a pre-determined amplitude and frequency for driving a single or multiple-phase load, the converter comprising:a plurality of modules configured to be stackable over one another, wherein each module comprises a ceramic cooling body with a planar receiving surface having electronic components of one phase mounted thereon, wherein the ceramic cooling body has one or more channels passing through the planar receiving surface for carrying a coolant during an operation of the converter;
at least one DC link capacitor and input-side and output-side power connections arranged on a first carrier extending perpendicular to a plane of the plurality of receiving surfaces;
a control unit arranged on a second carrier extending parallel to the plane of the first carrier, the control unit configured to drive the electronic components of the phase;
a structural support arranged on each of two opposing sides of the receiving surface, wherein the structural supports protrude, in a direction perpendicular to the receiving surface, beyond the receiving surface, such that the electronic components lie in a depression formed between the receiving surface and the structural supports;
wherein the coolant is supplied to the one or more channels through a portion of the structural supports extending parallel to the planar receiving surface; and
a sealing plate on each side of the depression and configured to close the depression, each sealing plate comprising a passage for control connections or supply and load connections.

US Pat. No. 10,141,859

SERIES MODULE ASSEMBLY WITH A POWER BUS SYSTEM

1. A series module assembly adapted for mounting on a wall, comprising(a) a plurality of modules arranged in a row, each of said modules including at least one electronic component and a plug assembly connected with said at least one electronic component and extending from said module;
(b) a bus assembly for mounting said plurality of modules on the wall, said bus assembly including a mounting and bus rail having a plurality of busbars, said plug assemblies of said plurality of modules being connected with said busbars to electrically connect said electronic components of said modules with said busbars, said modules being pre-assembled with said mounting and bus rail with said modules being arranged parallel to the wall; and
c) a pair of adjustable anchoring assemblies which connect said mounting and bus rail with the wall at a selected distance, thereby to define a gap between said mounting and bus rail and the wall.

US Pat. No. 10,141,858

POWER CONVERTER FOR ELECTRIC LOCOMOTIVE

KABUSHIKI KAISHA TOSHIBA,...

1. A power converter for an electric locomotive comprising:an insulating transformer supplied with high-voltage AC power from an AC overhead wire to convert a high voltage to a low voltage and output low-voltage AC power;
an AC/DC converter that receives the low-voltage AC power and performs AC/DC conversion;
an inverter that receives an output from the AC/DC converter and performs DC/AC conversion for supply to a load;
a PWM controller that outputs a PWM control signal having a predetermined pattern for removing specific harmonic components from an output of the inverter or attenuating the specific harmonic components to a predetermined level or lower; and
a voltage controller that controls an output voltage of the inverter to be an intended output voltage by controlling a DC output voltage of the AC/DC converter.

US Pat. No. 10,141,857

ENERGY SUPPLY DEVICE FOR SUPPLYING ELECTRIC ENERGY AND METHOD OF OPERATING A CORRESPONDING ENERGY SUPPLY DEVICE

JENOPTIK Power Systems Gm...

1. An energy supply device for providing electric energy, the energy supply device comprising:at least one input interface for receiving electric energy;
an output interface for outputting electric energy; and
at least one supercapacitor connected between the input interface and the output interface,
wherein the at least one supercapacitor is connected to a control circuit for controlling and/or regulating charging the at least one supercapacitor with electric energy, and
wherein the control circuit is configured to read in a measured value relating to a physical parameter of the at least one supercapacitor and to control and/or regulate energy input via the input interface and/or energy output via the output interface in response to the at least one measured value.

US Pat. No. 10,141,856

INTEGRATED MAGNETIC AND COMPOSITE SUBSTRATE WITH INCORPORATED COMPONENTS

1. A magnetic device assembly, comprising:a substantially planar power converter substrate providing incorporated power components utilizing power input and output terminals, wherein the power converter substrate has an extent defined by a predetermined power converter device and associated power input and output terminals; and
a substantially planar integrated magnetic substrate providing at least one magnetic device utilizing integrated input and output terminals, wherein each integrated input and output terminal is co-located with a respective power input and output terminal,
wherein the integrated magnetic substrate is mounted adjacent the power converter substrate so as to be spaced apart by a standoff space in a stacked orientation,
wherein a portion of the incorporated power components reside within the standoff space, and
wherein at least one co-located power and integrated terminal is interconnected by a dual directed terminal,
whereby, a physical extent of the integrated magnetic substrate and the power converter substrate extent are generally coextensive with each other.

US Pat. No. 10,141,855

SYSTEM AND METHOD FOR POWER CONVERSION

Accion Systems, Inc., Mo...

1. A polarity-selectable high voltage (HV) direct current (DC) power supply comprising:a first drive assembly that transforms a first low voltage (LV) DC input into a first medium voltage (MV) alternating current (AC) output, wherein the first drive assembly defines a first output junction and a second output junction;
a first HV output assembly that transforms the first LV AC output into a first HV DC output, wherein the first HV output assembly defines a first input stage directly electrically connected to the first output junction, a second input stage directly electrically connected to the first output junction, and a first HV DC output junction;
a polarity selector coupled between the second output junction of the first drive assembly and the first and second input stages of the first HV output assembly, the polarity selector comprising a set of switches operable between a first configuration and a second configuration;
wherein in the first configuration: the set of switches directly electrically connects the second output junction to the first input stage and electrically isolates the second output junction from the second input stage, and the first HV DC output has a positive polarity; and
wherein in the second configuration: the set of switches directly electrically connects the second output junction to the second input stage and electrically isolates the second output junction from the first input stage, and the first HV DC output has a negative polarity.

US Pat. No. 10,141,853

POWER CONVERTER AND METHOD OF CONTROL THEREOF

DELTA ELECTRONICS, INC., ...

1. A flyback power converter receiving an input voltage and providing an output voltage and an output current to a load, comprising:a transformer having a primary winding and a secondary winding, the output voltage and the output current being provided to the load from the secondary winding;
a first switch coupled to the primary winding, the first switch coupling the input voltage across the primary winding when the first switch is turned on;
a clamp circuit comprising first and second parallel circuits coupled to each other in series, wherein the first parallel circuit comprises a second switch and a clamp diode, and wherein the second parallel circuit comprises a clamp capacitor and a clamp resistor, such that the clamp circuit to provide an active clamp or a passive clamp, according to whether the second switch is closed or open;
a controller for regulating the output voltage or the output current by periodically turning on and off the first switch; and
a power management unit for enabling or disabling switching of the second switch based on the flyback power converter's operating conditions.

US Pat. No. 10,141,852

LLC SECONDARY SIDE CONTROL WITH ADAPTIVE ON-TIME

TEXAS INSTRUMENTS INCORPO...

1. A circuit for use in an LLC converter with an LLC primary side and an LLC secondary side, the circuit comprising:a secondary side controller configured:
to monitor, on the secondary side of the LLC converter, a voltage;
to determine, based on the voltage, a diode conduction time for a first switch in the LLC converter;
the secondary side controller further configured:
to increase the on-time for the first switch in the LLC converter in response to determining that the diode conduction time for the first switch is greater than a target time; and
to decrease the on-time for the first switch in the LLC converter in response to determining that the diode conduction time for the first switch is less than a target time.

US Pat. No. 10,141,851

RESONANT DC TO DC POWER CONVERTER

GENERAL ELECTRIC COMPANY,...

1. A direct current (DC) to DC power converter, comprising:a first converter for converting a first DC bus voltage into a first high frequency alternating current (AC) voltage;
a second converter for converting a second high frequency AC voltage into a second DC bus voltage;
a resonant circuit for coupling the first convener and the second converter, wherein the resonant circuit comprises:
a high frequency transformer coupled between the first converter and the second converter;
an auxiliary converter coupled in series with a first resonant inductor and the high frequency transformer, wherein an auxiliary voltage generated by the auxiliary converter is added in series with an output voltage of the first converter;
a second resonant inductor coupled across a first winding of the high frequency transformer;
a controller for providing switching signals to the first converter, and the second converter and the auxiliary converter to operate the power converter in a soft switching mode,
wherein the controller controls the auxiliary voltage generated by the auxiliary converter to have a characteristics of a resonant capacitor voltage; and
wherein the controller controls the auxiliary converter such that the auxiliary voltage is equal in fundamental frequency magnitude and opposite in phase of a voltage drop across the first resonant inductor.

US Pat. No. 10,141,849

MULTI-PHASE CONVERTER

Google LLC, Mountain Vie...

1. An apparatus, comprising:first and second parallel converter branches, each parallel converter branch comprising:
an input node that receives a direct current (DC) input voltage;
N output nodes that each respectively output a DC output voltage, wherein the DC output voltage is less than the DC input voltage, wherein N is an integer with a value of two or more;
a plurality of switches that each operate at a magnitude limit of substantially the DC input voltage divided by N, wherein each switch comprises a first terminal, a second terminal, and a third terminal, and the third terminal of the first switch receives a control signal that places the first switch in either a closed state in which a conduction path is established between the first and second terminals, or an open state in which the conduction path is eliminated between the first and second terminals;
N?1 cascade stages, each having an ordinal position relative to the DC input voltage and beginning with a first cascade stage that is connected to the DC input voltage as a respective input voltage, and each subsequent cascade stage is connected to a previous cascade stage to receive a respective input voltage, wherein each of the N?1 cascade stages includes a stacking capacitor that is charged to approximately (N?Ord)/N of the DC input voltage, wherein the value of Ord is the ordinal position of the cascade stage relative to the DC input voltage; and
a final stage that is connected to a last cascade stage to receive a respective input voltage;
a converter output node that is connected to each of the N output nodes of the first and second parallel converter branches and provides the DC output voltage; and
control logic that generates a first set of switch signals to control the switches of the first parallel converter branch and a second set of switch signals to control the second parallel converter branch, the first set switch signals and the second set of switch signals having respective duty cycles to cause each of the first and second parallel converter branches to output the DC output voltage on each of the N output nodes.

US Pat. No. 10,141,848

INTERLEAVED POWER FACTOR CORRECTOR

MIDEA GROUP CO., LTD., F...

1. An interleaved power factor corrector, comprising:a first power factor correction (PFC) component comprising a first energy storage inductor, a first switch component and a first fast recovery diode;
a second PFC component, parallel to the first PFC component and comprising a second energy storage inductor, a second switch component and a second fast recovery diode, wherein the second switch component is connected to the first switch component and a first node is between the second switch component and the first switch component;
a current sampling resistor, wherein a first terminal of the current sampling resistor is connected to the first node and a second terminal of the current sampling resistor is grounded;
a current detection component, connected to the first node and configured to detect a current I1 flowing through the first switch component, to detect a current I2 flowing through the second switch component and to detect a current lin flowing through the first switch component and the second switch component, each detection is based on a sampling signal generated by the current sampling resistor;
a voltage detection component, configured to detect a voltage U1 inputted into the interleaved power factor corrector and an output voltage U2 of the interleaved power factor corrector; and
a control component, connected to the current detection component, the voltage detection component, a control terminal of the first switch component and a control terminal of the second switch component respectively and configured to generate a first pulse-width modulation (PWM) control signal for controlling the first switch component and a second PWM control signal for controlling the second switch component based on the current I1, the current I2, the current lin, the voltage U1, the voltage U2 and a preset target output voltage, wherein the first PWM control signal is different from the second PWM control signal by a half of a carrier period;
wherein the control component further comprises:
a PFC control unit, configured to generate a first duty ratio signal in each carrier cycle based on the current lin, the voltage U1, the voltage U2, and the preset target output voltage;
a duty ratio adjustment unit, configured to calculate a duty ratio adjustment value based on the current I1 and the current I2;
a first calculating unit, configured to calculate a duty ratio signal of the first switch component based on the first duty ratio signal and the duty ratio adjustment value;
a second calculating unit, configured to calculate a duty ratio signal of the second switch component based on the first duty ratio signal and the duty ratio adjustment value;
a first saw-tooth wave generating unit, configured to output a first saw-tooth wave signal;
a second saw-tooth wave generating unit, configured to output a second saw-tooth wave signal;
a first PWM control signal generating unit, configured to generate the first PWM control signal based on the duty ratio signal of the first switch component and the first saw-tooth wave signal; and
a second PWM control signal generating unit, configured to generate the second PWM control signal based on the duty ratio signal of the second switch component and the second saw-tooth signal.

US Pat. No. 10,141,846

METHODS AND APPARATUS FOR ADAPTIVE TIMING FOR ZERO VOLTAGE TRANSITION POWER CONVERTERS

TEXAS INSTRUMENTS INCORPO...

1. A method of controlling a power converter, the method comprising:executing a plurality of cycles, each cycle including:
turning on a first switch during a first period, the first switch having a first current handling terminal coupled to a first terminal of a power supply and a second current handling terminal coupled to a switch node; a terminal of a first inductor being coupled to the switch node, the first inductor having another terminal coupled to an output terminal for supplying current to a load;
turning on a second switch during a second period, the second period occurring after the first period such that the first switch and second switch are not on simultaneously, the second switch having a first current handling terminal coupled to the switch node and a second current handling terminal coupled to a second terminal of the power supply;
turning on a third switch at a first time during the second period, and turning the third switch off at a second time after the second period but before a beginning of the first period of a succeeding cycle, the third switch being turned off by a first open signal including a high discharge signal during a first open period followed by a lower discharge signal during a second open period, the third switch having a first current handling terminal coupled to the first terminal of the power supply and a second current handling terminal coupled to an auxiliary node and to a first terminal of a second inductor, a second terminal of the second inductor being coupled to the switch node; and
turning on a fourth switch at a third time after the second time, and turning the fourth switch off during the first period of the succeeding cycle, the fourth switch having a first current handling terminal coupled to the auxiliary node and a second current handling terminal coupled to the second terminal of the power supply.

US Pat. No. 10,141,845

DC-DC CONVERTER AND CONTROL CIRCUIT WITH LOW-POWER CLOCKED COMPARATOR REFERENCED TO SWITCHING NODE FOR ZERO VOLTAGE SWITCHING

TEXAS INSTRUMENTS INCORPO...

1. A DC-DC converter circuit to control an output voltage signal, the DC-DC converter circuit comprising:a first switching device coupled between an input voltage node and a switching node, the first switching device operative according to a first switching control signal;
a second switching device coupled between the switching node and a reference voltage node, the second switching device operative according to a second switching control signal;
a first supply voltage node to provide a first supply voltage relative to a reference voltage of the reference voltage node;
a second supply voltage node, connected to the first supply voltage node through a diode, to provide a second supply voltage relative to the switching node;
a first driver circuit, referenced to the switching node and powered by the second supply voltage, to provide the first switching control signal according to a first driver signal;
a second driver circuit, powered by the first supply voltage, to provide the second switching control signal according to a second driver signal;
a control circuit, referenced to the reference voltage node and powered by the first supply voltage, to provide the first and second driver signals to regulate an output voltage signal according to a feedback signal, and to adjust a delay time between the second switching device turning off and the first switching device turning on according to a level shifted comparator signal; and
a comparator circuit, referenced to the switching node and powered by the second supply voltage, to sample a switching node voltage of the switching node in response to a first edge of the first driver signal, and to generate a comparator signal having: a first state indicating that a threshold voltage is less than the switching node voltage; and a second state indicating that the threshold voltage is greater than the switching node voltage; the comparator circuit including: a clocked comparator circuit, including a clock input connected to the control circuit to receive the first driver signal, and an output to provide the comparator signal referenced to the switching node; and a level shift circuit, including an input connected to the clocked comparator circuit to receive the comparator signal, and an output to provide the level shifted comparator signal referenced to the reference voltage node.

US Pat. No. 10,141,844

RECONFIGURABLE POWER REGULATOR

Lion Semiconductor Inc., ...

1. A voltage regulator comprising:an input voltage terminal;
an output voltage terminal;
a ground terminal; and
a plurality of unit integrated voltage regulators (IVRs), wherein each of the plurality of unit IVRs comprises an IVR input voltage terminal, an IVR output voltage terminal, and an IVR ground terminal, wherein each of the plurality of unit IVRs is integrated on a unique die, and where in at least two of the plurality of unit IVRs are integrated on adjacent dies of a single wafer that are physically coupled to one another;
wherein the input voltage terminal of each of the plurality of unit IVRs is electrically connected to the input voltage terminal of the voltage regulator,
wherein the output voltage terminal of each of the plurality of unit IVRs is electrically connected to the output voltage terminal of the voltage regulator,
wherein the ground terminal of each of the plurality of unit IVRs is electrically connected to the ground terminal of the voltage regulator; and
wherein each of the plurality of unit IVRs has substantially identical performance characteristics.