US Pat. No. 10,892,442

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a substrate;
an organic light emitting diode unit in an emission space, the organic light emitting diode unit comprising:
an insulating layer on the substrate;
a first electrode on the insulating layer;
a pixel defining layer on the insulating layer and directly contacting the first electrode;
an organic emission layer; and
a second electrode;
a first barrier in a dead space; and
a thin film encapsulation layer on the organic light emitting diode unit,
wherein the thin film encapsulation layer comprises an organic layer disposed on the organic light emitting diode unit and a first inorganic layer disposed on the organic layer,
the organic layer is in an area defined by the first barrier,
the first inorganic layer overlaps with the first barrier, and
a height of the first barrier is equal to or lower than a height of the organic layer.

US Pat. No. 10,892,441

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a display panel which comprises a first area and a second area located around the first area;
a window which is disposed on the display panel and comprises a third area overlapping the display panel and a fourth area protruding outward from the display panel;
an under-panel sheet which is disposed under the display panel and overlaps the first area and the second area; and
a waterproof member which is disposed around the under-panel sheet,
wherein the waterproof member comprises a plurality of line-shaped waterproof tapes extending along sides of the under-panel sheet and a plurality of waterproof resins, each disposed in a space between the waterproof tapes.

US Pat. No. 10,892,440

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device, comprising:a flexible substrate including a first region including a display region, a second region including a curved region, and a third region including a terminal region, the flexible substrate having a first surface and a second surface opposite to the first surface;
an organic EL element located in the display region;
a resin layer provided on the first surface of the flexible substrate, and continuously extending from the first region to the third region, the resin layer being located on the organic EL element in the display region;
a first protective film provided on the resin layer;
a polarizing member on the first protective film, the polarizing member being smaller than the first protective film,
at least two second protective films, wherein one of the second protective films is provided on the second surface of the first region and other one of the second protective films is provided on the second surface of the third region, and
a spacer located between the first region and the third region, the spacer having a curved portion being in contact with the flexible substrate at the second region and conformed to the shape of the second region,
wherein
the resin layer is an adhesive bonding the first protective film to the organic EL element and thicker than the flexible substrate, and has a first portion having a high degree of polymerization in the curved region and a second portion in the display region having a lower degree of polymerization than the first portion,
a border between the first portion and the second portion is in the first region and inner to an end of the first protective film, and
an edge of the first protective film extending along and adjacent to the second region is arranged in the first region in a cross-sectional view.

US Pat. No. 10,892,439

DISPLAY PANEL HAVING FILLER LAYER AND HEAT DISSIPATION LAYER AND PACKAGING METHOD THEREOF, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A display panel, comprising:a substrate having a display region and a non-display region;
a cover plate;
a sealant between the substrate and the cover plate and in the non-display region for bonding the substrate and the cover plate;
a filler layer covered by the sealant to cause the sealant to have tight contact with the substrate and with the cover plate;
a heat dissipation layer between the substrate and the sealant; and
the filler layer between the sealant and the heat dissipation layer.

US Pat. No. 10,892,438

ORGANIC LIGHT-EMITTING DISPLAY DEVICE HAVING AN UPPER SUBSTRATE FORMED BY A METAL AND METHOD OF FABRICATING THE SAME

LG DISPLAY CO., LTD., Se...

1. An organic light-emitting display device comprising:an upper substrate and a lower substrate facing each other, the upper substrate including a metal; and
an encapsulating layer between the upper substrate and the lower substrate,
wherein the upper substrate includes an upper surface opposite to the encapsulating layer and a side inclined surface having a concavo-convex shape, and the side inclined surface is disposed between the upper surface and a side surface of the upper substrate, and
wherein the upper substrate further includes a corner inclined surface disposed at a corner of the upper surface, and wherein the corner inclined surface has a length greater than that of the side inclined surface.

US Pat. No. 10,892,437

DISPLAY DEVICE INCLUDING A SEALANT

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a first substrate including a display area that displays an image and a peripheral area surrounding the display area;
a first metal layer disposed above the first substrate in the peripheral area, and the first metal layer including a plurality of openings;
a sealant disposed above the first metal layer; and
a second metal layer disposed above the first substrate and below the first metal layer in the peripheral area, and overlapping the plurality of openings,
wherein a plurality of through-holes pass through one of the openings of the metal layer, and
wherein, a part of the sealant contacts the second, metal layer through the plurality of through-holes penetrate first and second insulation layers.

US Pat. No. 10,892,436

NARROW BEZEL ELECTROLUMINANCE LIGHTING DEVICE

LG DISPLAY CO., LTD., Se...

1. An electroluminescent lighting device comprising:a substrate including an emission area and a non-emission area surrounding the emission area;
an auxiliary line disposed at the emission area and defining a pixel area;
a lower pad extended from the auxiliary line and disposed at one side of the non-emission area;
an anode layer covering the auxiliary line and the lower pad;
an emission layer disposed on the anode layer in the emission area;
a cathode layer disposed on the emission layer;
a second pad extended from the cathode layer and disposed at another side of the non-emission area;
an encapsulation layer covering the emission area on the cathode layer;
a cover film attached on the encapsulation layer and having a first pad corresponding to the lower pad; and
a conductive adhesive electrically connecting the first pad and the lower pad.

US Pat. No. 10,892,435

ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An organic light-emitting diode (OLED) display device, comprising:a substrate having a light emitting area and a non-light emitting area;
a thin film transistor arranged on the substrate;
a protective layer that covers the light emitting area and the non-light emitting area and has a protruding pattern arranged only in the light emitting area;
an overcoat layer that covers the protective layer;
a first electrode that is arranged on the overcoat layer and is connected to the thin film transistor through a first contact hole to expose a part of the protective layer and the overcoat layer, and overlapped with the protruding pattern;
an organic light emitting layer that is arranged on the first electrode; and
a second electrode that is arranged on the organic light emitting layer,
wherein a top surface of the first electrode has a convex shape, and
wherein a top surface of the organic light emitting layer has a flat shape,
wherein the protective layer is formed of an inorganic layer,
wherein the overcoat layer is formed of an organic layer, and
wherein the protective layer arranged in the non-light emitting area of the substrate has a first thickness, and the protective layer arranged in the light emitting area of the substrate has a second thickness by the protruding pattern, and the second thickness is thicker than the first thickness.

US Pat. No. 10,892,434

LIGHT-EMITTING ELECTROCHEMICAL CELL

LUNALEC AB, Umea (SE)

1. A light-emitting electrochemical cell comprising:a first electrode;
a second electrode; and
at least one light-emitting active material separating the first and second electrodes, wherein the light-emitting active material comprises a combination of an electrolyte, a first constituent comprising a host compound and a second constituent comprising a guest compound,wherein:a quotient between a difference in LUMO energy level between the first and second constituent, Etrapn, and a difference in HOMO energy level between the second and first constituent, Etrapp, is 1/10 to 10;
a quotient between an electron mobility and a hole mobility on the first constituent is 1/100 to 100;
a quotient between a number of ions of the electrolyte and a number of molecules or repeat units of the second constituent is ? to 5; and
a LUMO energy level of the electrolyte is higher than the LUMO energy level of the first constituent and a HOMO energy level of the electrolyte is lower than the HOMO energy level of the first constituent.

US Pat. No. 10,892,433

QUANTUM DOT LIGHT EMITTING DEVICE INCLUDING LIGAND-SUBSTITUTED QUANTUM DOT LIGHT EMITTING LAYER WITH POLYMER HAVING AMINE GROUPS AND METHOD FOR FABRICATING THE SAME

Korea University Research...

1. A quantum dot light emitting device comprising:an electron transport layer;
a polymer layer having amine groups coated on the electron transport layer; and
a quantum dot light emitting layer formed by coating quantum dots on the polymer layer;
wherein the quantum dots have surface oleic acid ligands,
wherein at least part of the quantum dot surface oleic acid ligands in contact with the polymer are ligand-substituted with said amine groups,
wherein said polymer is a dendrimer,
wherein said amine groups are positioned at branch terminus of the dendrimer,
wherein said dendrimer is a generation 3 or 4 dendrimer, and
wherein the quantum dots are bonded to said amine groups of the dendrimer by ligand substitution.

US Pat. No. 10,892,432

ORGANIC EL DISPLAY DEVICE, MANUFACTURING METHOD THEREOF, AND LIGHT-EMISSION METHOD THEREOF

SHARP KABUSHIKI KAISHA, ...

1. An organic EL display device, comprising:a plurality of pixels including a first pixel configured to output blue light, and a second pixel configured to output light having a peak wavelength longer than that of the blue light; and
a first electrode, a second electrode, and an organic layer including a light-emitting layer, the organic layer being formed between the first electrode and the second electrode, in each of the pixels,
wherein the first pixel includes, as the light-emitting layer, a first phosphorescent luminescent material containing layer including a first phosphorescent luminescent material for emitting blue phosphorescent light, and a first fluorescent luminescent material containing layer including a first fluorescent luminescent material for emitting blue fluorescent light, the first fluorescent luminescent material containing layer being layered adjacently to the first phosphorescent luminescent material containing layer,
the first phosphorescent luminescent material containing layer and the first fluorescent luminescent material containing layer are common layers provided in common to the plurality of pixels,
the second pixel includes, as the light-emitting layer, a second phosphorescent luminescent material containing layer including a second phosphorescent luminescent material for emitting phosphorescent light having a peak wavelength longer than that of the blue light, the second phosphorescent luminescent material containing layer being provided in each of the second pixel adjacently to the common layers at a first electrode side from the common layers, and
while each of the first phosphorescent luminescent material containing layer and the first fluorescent luminescent material containing layer emits light in the first pixel, the second phosphorescent luminescent material containing layer emits light in the second pixel.

US Pat. No. 10,892,431

ORGANIC ELECTROLUMINESCENT ELEMENT

JOLED INC., Tokyo (JP)

1. An organic electroluminescent element comprising, in order:a first electrode;
an organic layer that includes an organic electroluminescent layer;
an electron injection layer doped with a metal and configured to facilitate injection of electrons to the organic electroluminescent layer,
an interface adjustment layer;
a resistive layer; and
a second electrode,
wherein the resistive layer includes a specific resistance higher than a specific resistance of the second electrode,
the interface adjustment layer includes a specific resistance higher than the specific resistance of the second electrode and lower than the specific resistance of the resistive layer, and
the interface adjustment layer is in direct contact with the electron injection layer.

US Pat. No. 10,892,430

INDUCTIVELY DOPED MIXED LAYERS FOR AN OPTOELECTRONIC COMPONENT, AND METHOD FOR THE PRODUCTION THEREOF

INURU GMBH, Berlin (DE)

1. A method for producing an optoelectronic component (1) with a cathode (3) and an anode (5) and with a layer system between the cathode (3) and the anode (5), comprising multiple electroactive layers and at least one optically active layer (15), wherein at least two layers between the cathode (3) and the anode (5) are produced by a method comprising:a) providing a first ink comprising a first semiconductor material dissolved in a first carrier means;
b) providing a second ink comprising a second semiconductor dissolved in a second carrier means;
c) generating a first layer by application of the first ink with the help of a printing method;
d) drying of the first layer;
e) applying the second ink with the help of a printing method onto the first layer for the generation of a second layer;
f) drying of the second layer;
wherein the second carrier means is selected in such a manner that when the second ink is applied, the first layer is at least partially superficially dissolved, so that between the first and second layer, at least one inductively doped mixed layer is generated, in which the first and second semiconductor materials are present mixed, wherein the second carrier means comprises a mixture of at least two different solvents, wherein a first solvent completely dissolves the first semiconductor material up to a concentration of at least 1 g/L, and a second solvent completely dissolves the first semiconductor material up to a concentration of at most 0.1 g/L, and wherein the thickness of the mixed layer (2) is between 1 nm and 20 nm.

US Pat. No. 10,892,429

ORGANIC EL ELEMENT AND DISPLAY DEVICE

JOLED INC., Tokyo (JP)

1. An organic electroluminescent (EL) element, comprising:a first electrode;
a second electrode;
an interlayer between the first electrode and the second electrode, the interlayer including at least one of a crosslinking group and an insolubilizing group and being formed via coating; and
an organic light-emitting layer between the interlayer and the second electrode, the organic light-emitting layer being a blue light-emitting layer and being formed via coating; wherein:
the organic light-emitting layer contains at least a host material and a dopant material, and a foundation of the organic light-emitting layer includes the interlayer;
the interlayer is formed of a material which has an energy gap larger than an energy gap of the dopant material and a highest occupied molecular orbital (HOMO) level deeper than a HOMO level of the dopant material; and
the interlayer includes arylamine, but does not include fluorene.

US Pat. No. 10,892,428

FLEXIBLE SUBSTRATE AND MANUFACTURING METHOD THEREOF

1. A flexible substrate, comprising a hard layer, an organic functional layer and a backplane layer which are stacked; whereinthe organic functional layer is attached to the backplane layer;
the flexible substrate further comprises a Polarizer layer and a Touch Panel layer disposed between the hard layer and the organic functional layer, and
the Touch Panel layer comprises a glass substrate and a conductive layer coated on a surface of the glass substrate;
wherein the Polarizer layer comprises a Polyvinyl Alcohol layer and a ¼ ? slide layer, the ¼ ? slide layer is coated to a surface of the glass substrate of the Touch Panel layer without the conductive layer coated, and the Polyvinyl Alcohol layer is disposed between the glass substrate and the hard layer or between the glass substrate and the organic functional layer.

US Pat. No. 10,892,427

ORGANOMETALLIC COMPOUND, ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE ORGANOMETALLIC COMPOUND, AND DIAGNOSTIC COMPOSITION INCLUDING THE ORGANOMETALLIC COMPOUND

SAMSUNG ELECTRONICS CO., ...

1. An organometallic compound represented by Formula 1:
wherein M in Formula 1 is beryllium (Be), magnesium (Mg), aluminum (Al), calcium (Ca), titanium (Ti), manganese (Mn), cobalt (Co), copper (Cu), zinc (Zn), gallium (Ga), germanium (Ge), zirconium (Zr), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), rhenium (Re), platinum (Pt), or gold (Au),
in Formula 1, two bonds selected from a bond between A1 and M, a bond between A2 and M, a bond between A3 and M, and a bond between A4 and M are each a covalent bond, and the others thereof are each a coordinate bond,
A1 is represented by one of Formulae CY1-1 to CY1-11, in Formulae CY1-1 to CY1-11, * indicates a binding site to M in Formula 1, and *? indicates a bind site to T1 in Formula 1,
A2 is represented by one of Formulae CY2-1 to CY2-5, and in Formulae CY2-1 to CY2-5, X21 is O, S, NR(R21), C(R21)(R22), or Si(R21)(R22), * indicates a binding site to M in Formula 1, *? indicates a binding site to T1 in Formula 1, and *? indicates a binding site to T2 in Formula 1,
A3 in Formula 1 is ring CY3 represented by one of Formulae A3-1 to A3-3, and in Formulae A3-1 to A3-3, * indicates a binding site to M in Formula 1, *? indicates a binding site to T2 in Formula 1, and *? indicates a binding site to T3 in Formula 1,
A4 in Formula 1 is a first atom linked to M, or a non-cyclic moiety comprising the first atom linked to M,
the first atom is B, P, Si, O, or S,
X2 to X3 and Y5 to Y6 in Formulae CY2-1 to CY2-5, and A3-1 to A3-3 are each independently C or N,
rings CY3 in Formulae A3-1 to A3-3 are each independently a C5-C30 carbocyclic group or a C1-C30 heterocyclic group,
in Formula 1, T1 to T3 are each independently selected from a single bond, a double bond, *—N(R7)—*?, *—B(R7)—*?, *—P(R7)—*?, *—C(R7)(R8)—*?, *—Si(R7)(R8)—*?, *—Ge(R7)(R8)—*?, *—S—*?, *—Se—*?, *—C(?O)—*?, *—S(?O)—*?, *—S(?O)2—*?, *—C(R7)?*?, *?C(R7)—*?, *—C(R7)?C(R8)—*?, *—C(?S)—*?, and *—C?C—*?, and * and *? each indicate a binding site to a neighboring atom,
R7 and R8 are optionally linked via a single bond, a double bond, or a first linking group to form a substituted or unsubstituted C5-C30 carbocyclic group or a substituted or unsubstituted C1-C30 heterocyclic group,
R1, R1a, R1b, R2, R2a, R2b, R3, R7, R8, R21, and R22 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, —SF5, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, —N(Q1)(Q2), —Si(Q3)(Q4)(Q5), —B(Q6)(Q7), and —P(?O)(Q8)(Q9),
a3 in Formulae A3-1 to A3-3 are each independently an integer from 0 to 20,
two of a plurality of neighboring groups R3 are optionally linked to form a substituted or unsubstituted C5-C30 carbocyclic group or a substituted or unsubstituted C1-C30 heterocyclic group,
two or more groups selected from R1, R1a, R1b, R2, R2a, R2b, and R3 are optionally linked to form a substituted or unsubstituted C5-C30 carbocyclic group or a substituted or unsubstituted C1-C30 heterocyclic group,
A1 and A4 in Formula 1 are not linked to each other,
at least one substituent of the substituted C5-C30 carbocyclic group, the substituted C1-C30 heterocyclic group, the substituted C1-C60 alkyl group, the substituted C2-C60 alkenyl group, the substituted C2-C60 alkynyl group, the substituted C1-C60 alkoxy group, the substituted C3-C10 cycloalkyl group, the substituted C1-C10 heterocycloalkyl group, the substituted C3-C10 cycloalkenyl group, the substituted C1-C10 heterocycloalkenyl group, the substituted C6-C60 aryl group, the substituted C6-C60 aryloxy group, the substituted C6-C60 arylthio group, the substituted C1-C60 heteroaryl group, the substituted monovalent non-aromatic condensed polycyclic group, and the substituted monovalent non-aromatic condensed heteropolycyclic group is selected from:
deuterium, —F, —Cl, —Br, —I, —CD3, —CD2H, —CDH2, —CF3, —CF2H, —CFH2, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group;
a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, —CD3, —CD2H, —CDH2, —CF3, —CF2H, —CFH2, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —N(Q11)(Q12), —Si(Q13)(Q14)(Q15), —B(Q16)(Q17), and —P(?O)(Q18)(Q19);
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group;
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, —CD3, —CD2H, —CDH2, —CF3, —CF2H, —CFH2, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —N(Q21)(Q22), —Si(Q23)(Q24)(Q25), —B(Q26)(Q27), and —P(?O)(Q28)(Q29); and
—N(Q31)(Q32), —Si(Q33)(Q34)(Q35), —B(Q36)(Q37), and —P(?O)(Q38)(Q39), and
Q1 to Q9, Q11 to Q19, Q21 to Q29, and Q31 to Q39 are each independently selected from hydrogen, deuterium, —F, —C1, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C1-C60 alkyl group substituted with at least one selected from deuterium, a C1-C60 alkyl group, and a C6-C60 aryl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryl group substituted with at least one selected from deuterium, a C1-C60 alkyl group, and a C6-C60 aryl group, a C6-C60 aryloxy group, a C6—C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group.

US Pat. No. 10,892,426

ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES

UNIVERSAL DISPLAY CORPORA...

1. An organic light emitting device (OLED), comprising:an anode;
a cathode; and
an emissive layer, disposed between the anode and the cathode, the emissive layer comprising a heteroleptic complex having the formula Ir(LA-B)2(LC-D),
wherein LA-B is

wherein LC-D is selected from the group consisting of
andwherein R1, R2, R3, R4 and R5 are each independently selected from the group consisting of hydrogen and alkyl;
wherein each of R1, R2, R3, R4 and R5 may represent mono, di, tri, tetra, or penta substitutions; and
wherein the emissive layer further comprises a host, wherein the host is an indolocarbazole derivative or an N-arylcarbazole derivative.

US Pat. No. 10,892,425

COMPOSITION OF MATTER FOR USE IN ORGANIC LIGHT-EMITTING DIODES

KYULUX, INC., Fukuoka (J...

1. A compound of Formula (I):
wherein
B is boron;
R is independently selected from

A is C1-4-alkyl;
L is independently selected from

D is independently selected from

m is 0, 1, or 2;
n is 1, 2, or 3;
n+m=3;
p is 1, or p is 2 if L is L-18 or L-19;
* indicates the point of attachment of an instance of L or R to B;
** indicates the point of attachment of an instance of L to an instance of D; and
*** indicates the point of attachment of an instance of D to an instance of L.

US Pat. No. 10,892,424

COMPOSITION FOR MANUFACTURING ORGANIC SEMICONDUCTOR DEVICE

DAICEL CORPORATION, Osak...

1. A composition for manufacturing an organic semiconductor device, comprising:2,3-dihydrobenzofuran as a solvent; and
an organic semiconductor material,
wherein a water content of the solvent is 0.25 wt % or less, and
wherein the organic semiconductor material comprises at least one compound selected from the group consisting of a compound represented by formula (1-1), a compound represented by formula (1-2), a compound represented by formula (1-3), a compound represented by formula (1-4), a compound represented by formula (1-5), and a compound represented by formula (1-6):

 wherein X1 and X2 are the same or different and each represent an oxygen atom, a sulfur atom, or a selenium atom, m is 0 or 1, n? and n2 are the same or different and each represent 0 or 1, and R1 and R2 are the same or different and each represent a fluorine atom, a C1-20 alkyl group, a C6-13 aryl group, a pyridyl group, a furyl group, a thienyl group, or a thiazolyl group, wherein 1 or 2 or more hydrogen atoms contained in the alkyl group may be substituted by a fluorine atom, and wherein 1 or 2 or more hydrogen atoms contained in the aryl group, the pyridyl group, the furyl group, the thienyl group, and the thiazolyl group may be substituted by a fluorine atom or an alkyl group having 1 to 10 carbon atoms.

US Pat. No. 10,892,423

CONDENSED CYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A condensed cyclic compound represented by Formula 1:
wherein, in Formulae 1 to 4,
X1 to X4 are each independently C(R1), N, or carbon linked to a group represented by Formula 2 or 3,
X5 to X8 are each independently C(R2), N, or carbon linked to a group represented by Formula 4,
X11 to X18 are each independently C(R3) or N,
X21 to X28 are each independently C(R4), N, or carbon linked to (L21)a21, and
at least one of X1 to X4 is carbon linked to a group represented by Formula 2 or 3, at least one of X5 to X8 is carbon linked to a group represented by Formula 4, and at least one of X21 to X28 is carbon linked to (L21)a21,
Y101 and Y102 are each independently selected from C(R11)(R12), Si(R11)(R12), O, S, and N(R11),
Y11, Y21, and Y22 are each independently selected from C(R21)(R22), Si(R21)(R22), O, S, and N(R21), provided that:
when Y101 is O, Y102 is C(R11)(R12), Si(R11)(R12), O or N(R11),
when Y11 is C(R21)(R22), Si(R21)(R22), O or N(R21) and Y101 is S, Y102 is C(R11)(R12), Si(R11)(R12), S or N(R11),
when Y11 and Y101 are each S, Y102 is C(R11)(R12), Si(R11)(R12), or S, and
when Y11 is S and Y101 is N(R11), Y102 is C(R11)(R12), Si(R11)(R12), O or N(R11);
L1, L11, and L21 are each independently a substituted or unsubstituted C3-C60 carbocyclic group or a substituted or unsubstituted C1-C60 heterocyclic group,
a1, a11, and a21 are each independently an integer from 0 to 3, wherein, when a1 is two or more, two or more L1(s) are identical to or different from each other, when a11 is two or more, two or more L11(s) are identical to or different from each other, and when a21 is two or more, two or more L21(s) are identical to or different from each other,
Ar1 is a substituted or unsubstituted C3-C60 carbocyclic group, a substituted or unsubstituted C1-C60 heterocyclic group, or *—S(?O)2(Q101),
R1 to R4, R11 to R12, and R21 to R22 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, —Si(Q1)(Q2)(Q3), —N(Q1)(Q2), —B(Q1)(Q2), —C(?O)(Q1), —S(?O)2(Q1), and —P(?O)(Q1)(Q2),
at least one substituent of the substituted C3-C60 carbocyclic group, the substituted C1-C60 heterocyclic group, the substituted C1-C60 alkyl group, the substituted C2-C60 alkenyl group, the substituted C2-C60 alkynyl group, the substituted C1-C60 alkoxy group, the substituted C3-C10 cycloalkyl group, the substituted C1-C10 heterocycloalkyl group, the substituted C3-C10 cycloalkenyl group, the substituted C1-C10 heterocycloalkenyl group, the substituted C6-C60 aryl group, the substituted C6-C60 aryloxy group, the substituted C6-C60 arylthio group, the substituted C1-C60 heteroaryl group, the substituted monovalent non-aromatic condensed polycyclic group, and the substituted monovalent non-aromatic condensed heteropolycyclic group is selected from:
deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazino group, a hydrazono group, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group;
a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazino group, a hydrazono group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —Si(Q11)(Q12)(Q13), —N(Q11)(Q12), —B(Q11)(Q12), —C(?O)(Q11), —S(?O)2(Q11), and —P(?O)(Q11)(Q12);
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, a biphenyl group, and a terphenyl group;
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, a biphenyl group, and a terphenyl group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazino group, a hydrazono group, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, a biphenyl group, a terphenyl group, —Si(Q21)(Q22)(Q23), —N(Q21)(Q22), —B(Q21)(Q22), —C(?O)(Q21), —S(?O)2(Q21), and —P(?O)(Q21)(Q22); and
—Si(Q31)(Q32)(Q33), —N(Q31)(Q32), —B(Q31)(Q32), —C(?O)(Q31), —S(?O)2(Q31), and —P(?O)(Q31)(Q32),
Q101, Q1 to Q3, Q11 to Q13, Q21 to Q23, and Q31 to Q33 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazino group, a hydrazono group, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, a biphenyl group, and a terphenyl group, and
* indicates a binding site to a neighboring atom.

US Pat. No. 10,892,422

COMPOUND FOR ORGANIC OPTOELECTRONIC DEVICE, ORGANIC LIGHT EMITTING DIODE INCLUDING THE SAME, AND DISPLAY INCLUDING THE ORGANIC LIGHT EMITTING DIODE

SAMSUNG ELECTRONICS CO., ...

1. A compound for an organic optoelectronic device represented by Chemical Formula 1:wherein, in Chemical Formula 1,Y1 is NR?, wherein R? is a substituted or unsubstituted C6 to C30 aryl group,
Y2 is —O—, —S—, or —S(O2)—,
X1 to X8 are independently —CR?— or —N—, any two adjacent X1 to X8 form a fused ring, wherein
R? are independently hydrogen, deuterium, a halogen, a cyano group, a hydroxyl group, an amino group, a substituted or unsubstituted C1 to C20 amine group, a nitro group, a carboxyl group, a ferrocenyl group, a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C2 to C30 heteroaryl group, a substituted or unsubstituted C1 to C20 alkoxy group, a substituted or unsubstituted C6 to C20 aryloxy group, a substituted or unsubstituted C3 to C40 silyloxy group, a substituted or unsubstituted C1 to C20 acyl group, a substituted or unsubstituted C2 to C20 alkoxycarbonyl group, a substituted or unsubstituted C2 to C20 acyloxy group, a substituted or unsubstituted C2 to C20 acylamino group, a substituted or unsubstituted C2 to C20 alkoxycarbonylamino group, a substituted or unsubstituted C7 to C20 aryloxycarbonylamino group, a substituted or unsubstituted C1 to C20 sulfamoylamino group, a substituted or unsubstituted C1 to C20 sulfonyl group, a substituted or unsubstituted C1 to C20 alkylthio group, a substituted or unsubstituted C6 to C20 arylthio group, a substituted or unsubstituted C1 to C20 heterocyclothio group, a substituted or unsubstituted C1 to C20 ureide group, a substituted or unsubstituted C3 to C40 silyl group, or a combination thereof,
one of X1 to X4 is —CR?—, wherein R? forms a bond with an adjacent substituent,
one of X5 to X8 is —CR?—, wherein the R? forms a bond with an adjacent substituent,
one of Ar1 and Ar2 is hydrogen and the other of Ar1 and Ar2 is a substituted or unsubstituted quinolinyl group, a substituted or unsubstituted isoquinolinyl group, a substituted or unsubstituted pyridyl group, a substituted or unsubstituted pyrimidinyl group, a substituted or unsubstituted triazinyl group, or a combination thereof, wherein a substituent of the substituted quinolinyl group, the substituted isoquinolinyl group, the substituted pyridyl group, the substituted pyrimidinyl group, and the substituted triazinyl group is a C1 to C30 alkyl group, a C6 to C30 aryl group, or a combination thereof,
L1 and L2 are independently a substituted or unsubstituted C2 to C20 alkenylene group, a substituted or unsubstituted C2 to C20 alkynylene group, a substituted or unsubstituted C6 to C30 arylene group, a substituted or unsubstituted C2 to C30 heteroarylene group, or a combination thereof,
n1 and n2 are independently integers ranging from 0 to 3,
m1 and m2 are independently integers ranging from 1 to 3.

US Pat. No. 10,892,421

ORGANIC SMALL MOLECULE SEMICONDUCTING CHROMOPHORES FOR USE IN ORGANIC ELECTRONIC DEVICES

The Regents of the Univer...

1. A compound of Formula IV-V:
where X1 and Y1 are selected from N and CH, where when X1 is N, Y1 is CH, and when X1 is CH, Y1 is N
M is selected from sulfur (S), oxygen (O), or N-R1, where R1 is H, C1-C30 alkyl or C6-C30 aryl;
K1 is independently selected from substituted or unsubstituted aryl or heteroaryl;
each E1 is independently either absent, or selected from substituted or unsubstituted aryl or heteroaryl groups;
each D1 is independently selected from substituted or unsubstituted aryl or heteroaryl groups; and
each D2 is independently selected from a nonentity, H, F, a C1-C16 alkyl group, or a substituted or unsubstituted aryl or heteroaryl group.

US Pat. No. 10,892,420

ORGANIC ELECTROLUMINESCENT DEVICE

Hodogaya Chemical Co., Lt...

1. An organic electroluminescent device comprising at least an anode, a hole transport layer, a light emitting layer, an electron transport layer and a cathode in this order,wherein the hole transport layer has a two-layer structure of a first hole transport layer and a second hole transport layer, and the second hole transport layer comprises an arylamine compound of general formula (1):

wherein Ar1 to Ar4 may be the same or different, and represent a substituted or unsubstituted aromatic hydrocarbon group, a substituted or unsubstituted aromatic heterocyclic group, or a substituted or unsubstituted condensed polycyclic aromatic group;
and the light emitting layer comprises an amine derivative of general formula (2a-a), (2a-b), (2b-a), (2b-b), (2b-c), (2b-d), (2c-a) or (2c-b), having a condensed ring structure:

wherein A1 represents a divalent group of a substituted or unsubstituted aromatic hydrocarbon, a divalent group of a substituted or unsubstituted aromatic heterocyclic ring, a divalent group of substituted or unsubstituted condensed polycyclic aromatics, or a single bond;
Ar5 and Ar6 may be the same or different, and represent a substituted or unsubstituted aromatic hydrocarbon group, a substituted or unsubstituted aromatic heterocyclic group, or a substituted or unsubstituted condensed polycyclic aromatic group, where Ar5 and Ar6 may bind to each other via a single bond, substituted or unsubstituted methylene, an oxygen atom, or a sulfur atom to form a ring;
X and Y may be the same or different, each representing an oxygen atom or a sulfur atom;
R1 to R4 may be the same or different, and represent a hydrogen atom, a deuterium atom, a fluorine atom, a chlorine atom, cyano, nitro, linear or branched alkyl of 1 to 6 carbon atoms that may have a substituent, cycloalkyl of 5 to 10 carbon atoms that may have a substituent, linear or branched alkenyl of 2 to 6 carbon atoms that may have a substituent, linear or branched alkyloxy of 1 to 6 carbon atoms that may have a substituent, cycloalkyloxy of 5 to 10 carbon atoms that may have a substituent, a substituted or unsubstituted aromatic hydrocarbon group, a substituted or unsubstituted aromatic heterocyclic group, a substituted or unsubstituted condensed polycyclic aromatic group, substituted or unsubstituted aryloxy, or a disubstituted amino group substituted with a group selected from an aromatic hydrocarbon group, an aromatic heterocyclic group, and a condensed polycyclic aromatic group, where R1 to R4 may bind to each other via a single bond, substituted or unsubstituted methylene, an oxygen atom, or a sulfur atom to form a ring, and R1 to R4 and the benzene ring binding with R1 to R4 may bind to each other via substituted or unsubstituted methylene, an oxygen atom, a sulfur atom, or a mono-substituted amino group;
R5 to R7 may be the same or different, represent a hydrogen atom, a deuterium atom, a fluorine atom, a chlorine atom, cyano, nitro, linear or branched alkyl of 1 to 6 carbon atoms that may have a substituent, cycloalkyl of 5 to 10 carbon atoms that may have a substituent, linear or branched alkenyl of 2 to 6 carbon atoms that may have a substituent, linear or branched alkyloxy of 1 to 6 carbon atoms that may have a substituent, cycloalkyloxy of 5 to 10 carbon atoms that may have a substituent, a substituted or unsubstituted aromatic hydrocarbon group, a substituted or unsubstituted aromatic heterocyclic group, a substituted or unsubstituted condensed polycyclic aromatic group, or substituted or unsubstituted aryloxy, wherein at least one of R5 to R7 is a substituted or unsubstituted aromatic hydrocarbon group, a substituted or unsubstituted aromatic heterocyclic group, or a substituted or unsubstituted condensed polycyclic aromatic group, and where R5 to R7 may bind to each other via a single bond, substituted or unsubstituted methylene, an oxygen atom, or a sulfur atom to form a ring, and R5 to R7 and the benzene ring binding with R5 to R7 may bind to each other via substituted or unsubstituted methylene, an oxygen atom, a sulfur atom, or a mono-substituted amino group; and
R8 and R9 may be the same or different, linear or branched alkyl of 1 to 6 carbon atoms that may have a substituent, cycloalkyl of 5 to 10 carbon atoms that may have a substituent, linear or branched alkenyl of 2 to 6 carbon atoms that may have a substituent, a substituted or unsubstituted aromatic hydrocarbon group, a substituted or unsubstituted aromatic heterocyclic group, a substituted or unsubstituted condensed polycyclic aromatic group, or substituted or unsubstituted aryloxy, where R8 and R9 may bind to each other via a single bond, substituted or unsubstituted methylene, an oxygen atom, a sulfur atom, or a mono-substituted amino group to form a ring.

US Pat. No. 10,892,419

SPACE-THROUGH CHARGE TRANSFER COMPOUND, AND ORGANIC LIGHT EMITTING DIODE AND DISPLAY DEVICE USING THE SAME

LG Display Co., Ltd., Se...

1. A delayed fluorescence compound, comprising:a naphthalene core;
an electron donor moiety; and
an electron acceptor moiety selected from the group consisting of pyridine, diazine, and triazole,
wherein the electron donor moiety is combined to a first position of the naphthalene core with a benzene linker and the electron acceptor moiety is combined to an eighth position of the naphthalene core with another benzene linker.

US Pat. No. 10,892,418

CHARGE INJECTION LAYER AND METHOD FOR ITS PRODUCTION AS WELL AS ORGANIC PHOTOELECTRONIC ELEMENT AND METHOD FOR ITS PRODUCTION

AGC Inc., Chiyoda-ku (JP...

1. A charge injection layer containing a fluorinated polymer and a semiconductor material, and having a refractive index in the wavelength range of from 450 nm to 800 nm of at most 1.60.

US Pat. No. 10,892,417

SUBSTRATE, DISPLAY DEVICE, CONDUCTIVE FILM WITH DOPANT AND METHOD FOR FABRICATING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A substrate, comprising a base substrate and a conductive pattern disposed on the base substrate, whereina material of the conductive pattern includes a second conductive polymer and a dopant, and the second conductive polymer is a conductive polymer transformed from a first conductive polymer under an action of the dopant; and
a conductivity of the second conductive polymer is greater than a conductivity of the first conductive polymer, wherein
the conductive pattern includes at least one layer of first sub-conductive pattern and at least one layer of second sub-conductive pattern, and each of the at least one layer of first sub-conductive pattern and each of the at least one layer of second sub-conductive pattern are alternately disposed;
a material of each of the at least one layer of first sub-conductive pattern is the same, and a material of each of the at least one layer of second sub-conductive pattern is the same;
a material of the first sub-conductive pattern and the material of the second sub-conductive pattern contain a same second conductive polymer and different dopants, wherein
a material of the first conductive polymer is selected from at least one of poly(3,4-ethylenedioxythiophene) (PEDOT), polythiophene, polypyrrole, polyaniline, and polyphenylene;
a material of the dopant is selected from at least one of polyvinyl alcohol (PVA) and dimethyl sulfoxide (DMSO); and
in a case where the dopant includes the polyvinyl alcohol (PVA), a ratio of PVA to the material of the conductive pattern is 0.01 wt % to 1 wt %.

US Pat. No. 10,892,416

SENSITIVE X-RAY AND GAMMA-RAY DETECTORS INCLUDING PEROVSKITE SINGLE CRYSTALS

NUtech Ventures, Lincoln...

1. A perovskite single crystal X-ray and gamma-ray radiation detector device, comprising:an X-ray and gamma-ray wavelength responsive active layer including a perovskite single crystal;
a first electrode disposed on a first surface of the perovskite single crystal; and
a second electrode disposed on the first surface or on a second surface of the perovskite single crystal opposite the first surface;
wherein the perovskite single crystal is a perovskite single crystal having a structure of APbBr3-xClx, wherein A is methylammonium (CH3NH3+) and
wherein x is a fractional number between 0 and 0.6.

US Pat. No. 10,892,415

DEPOSITION MASK, VAPOR DEPOSITION APPARATUS, VAPOR DEPOSITION METHOD, AND METHOD FOR MANUFACTURING ORGANIC EL DISPLAY APPARATUS

HON HAI PRECISION INDUSTR...

1. A vapor deposition method comprising:forming a deposition mask having at least partly a metal layer made of a ferromagnetic material;
magnetizing the metal layer of the deposition mask by applying a magnetic field to the metal layer;
aligning the deposition mask and a substrate for vapor deposition with each other, and then attracting and fixing the deposition mask to an electromagnet with the substrate for vapor deposition therebetween;
depositing a vapor deposition material on the substrate for vapor deposition by vaporizing the vapor deposition material in a vapor deposition source, the vapor deposition source being disposed so as to face the deposition mask; and
separating both the electromagnet and the substrate for vapor deposition from the deposition mask by generating a magnetic field to cause the deposition mask to repel from the electromagnet.

US Pat. No. 10,892,414

PROCESS FOR MAKING ELECTRONIC DEVICE

Merck Patent GmbH, Darms...

1. A process for the preparation of an electronic device comprising a first functional layer and a second functional layer which form an interface,wherein the process comprises the following process steps:
a1) depositing a first solution containing a first organic functional material and a first solvent on a support;
a2) drying said first solution and optionally annealing said first organic functional material to obtain a first functional layer;
b1) depositing a second solution containing a second organic functional material and a second solvent on the first functional layer; and
b2) drying said second solution and optionally annealing said second organic functional material to obtain a second functional layer;
characterized in that the absolute solubility of the first organic functional material in the second solvent is in the range from 0.1 to 200 g/L at 25° C. and in that the absolute solubility of the second organic functional material in the second solvent is >5.0 g/L and <500 g/L at 25° C.; and
wherein the dissolution rate of the first organic functional material in the second solvent is <0.116 g/(L·min) at 25° C.

US Pat. No. 10,892,413

INTEGRATION OF CONFINED PHASE CHANGE MEMORY WITH THRESHOLD SWITCHING MATERIAL

International Business Ma...

1. A phase change memory array comprising:a plurality of bottom electrodes;
a plurality of top electrodes positioned along a bit line direction;
a plurality of memory pillars, each of the memory pillars including phase change material surrounded by a dielectric casing, the dielectric casing including a casing lip in physical contact with the phase change material, the dielectric casing and casing lip forming an L-shaped cross section defining a space between the dielectric casing and the phase change material, the phase change material positioned between, and in series circuit with, a respective bottom electrode from the plurality of bottom electrodes and a respective top electrode from the plurality of top electrodes, and a metallic liner positioned over and in contact with the casing lip and inside the space between the dielectric casing and the phase change material extending vertically from the casing lip along an area defined by the dielectric casing and the phase change material; and
a continuous layer of unitary selector material positioned parallel lengthwise to the bit line direction and positioned between the memory pillars and the plurality of bottom electrodes, the selector material configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold; and
wherein each of the bottom electrodes is physically and electrically isolated from one another by a dielectric substrate and the continuous layer of selector material positioned between the memory pillars and the plurality of bottom electrodes.

US Pat. No. 10,892,412

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

SK hynix Inc., Icheon (K...

9. A method of fabricating an electronic device including a semiconductor memory, the method comprising:forming first stack structures extending in a first direction;
forming a first gap-fill layer between the first stack structures;
forming second stack structures extending in a second direction that intersects the first direction;
forming a second gap-fill layer between the second stack structures;
forming a first trench passing through the second gap-fill layer and exposing a first sidewall of the first stack structures;
forming a first protective layer in the first trench; and
forming a third gap-fill layer in the first trench in which the first protective layer is formed.

US Pat. No. 10,892,411

PHASE-CHANGE MATERIAL RF SWITCH

Newport Fab, LLC, Newpor...

1. A method of manufacturing a radio frequency (RF) switch, the method comprising:providing a heat spreader;
depositing a first dielectric over said heat spreader;
etching a trench in said first dielectric;
depositing a heating element in said trench and over at least a portion of said first dielectric;
depositing a thermally conductive and electrically insulating material at least in said trench over said heating element, wherein said thermally conductive and electrically insulating material is self-aligned with said heating element;
depositing a phase-change material over said first dielectric and said thermally conductive and electrically insulating material.

US Pat. No. 10,892,410

VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING VARIABLE RESISTANCE MEMORY DEVICES

Samsung Electronics Co., ...

1. A variable resistance memory device comprising:a plurality of insulating layers stacked on a substrate;
a first conductive line penetrating the plurality of insulating layers;
a plurality of switching patterns, each switching pattern between a respective pair of adjacent insulating layers of the plurality of insulating layers;
a phase change pattern between the first conductive line and each of the switching patterns; and
a capping pattern between the phase change pattern and the first conductive line and at least partially surrounded by the phase change pattern.

US Pat. No. 10,892,409

SWITCHING DEVICE, METHOD OF FABRICATING THE SAME, AND NON-VOLATILE MEMORY DEVICE HAVING THE SAME

SK hynix Inc., Icheon (K...

1. A switching device coupled in series to a variable resistor that stores logic values by changing a resistance state, the switching device being a selection element in which on-current flows when a voltage is applied in a set state and on-current does not flow when the voltage is applied in a reset state, the switching device comprising,a first electrode;
a second electrode; and
a switching film disposed between the first electrode and the second electrode, the switching film having an electrically insulating matrix and a conductive path formed in the electrically insulating matrix;
wherein the conductive path includes crystalline metal clusters dispersed in the electrically insulating matrix and a metal bridge connecting adjacent crystalline metal clusters, and the crystalline metal clusters have a crystal orientation plane.

US Pat. No. 10,892,408

MULTIVALENT OXIDE CAP FOR ANALOG SWITCHING RESISTIVE MEMORY

INTERNATIONAL BUSINESS MA...

1. A resistive random access memory (RRAM), comprising:a first electrode;
a base oxide being connected to the first electrode; and
a multivalent oxide being connected to the base oxide,
wherein the multivalent oxide switches oxidative states
wherein the oxidative states of the multivalent oxide is configured to be variable during a resistance switching cycle of the resistive random access memory structure,
wherein the base oxide is doped with the multivalent oxide to form a doped oxide layer,
wherein the doped oxide layer is provided on the first electrode, and
wherein the second electrode is provided on the doped oxide layer.

US Pat. No. 10,892,407

APPARATUS AND METHODS FOR ELECTRICAL SWITCHING

Massachusetts Institute o...

1. A method of actuating a device comprising a crystalline layer having at least one channel extending from a first side of the crystalline layer to a second side of the crystalline layer, a first electrode comprising an active material disposed on the first side of the crystalline layer, and a second electrode disposed on the second side of the crystalline layer, the method comprising:applying a first voltage, having a first sign, across the first electrode and the second electrode, the first voltage causing a plurality of metal ions of the active material to form a conductive filament extending between the first electrode and the second electrode along the at least one channel.

US Pat. No. 10,892,406

PHASE CHANGE MEMORY STRUCTURES AND DEVICES

Intel Corporation, Santa...

1. A phase change memory (PCM) cell, comprising:a PCM layer comprising a PCM material;
a first electrode and a second electrode disposed on opposite sides of the PCM layer;
wherein each of the first electrode and the second electrode includes an upper barrier layer, a lower barrier layer, and a metal ceramic composite material layer disposed between and in direct contact with the upper barrier layer and the lower barrier layer, wherein a composition of the upper barrier layer and a composition of the lower barrier layer are selected to provide thermal stability to the metal ceramic composite material layer,
wherein said each of the first electrode and the second electrode includes only layers superimposed on one another, and
wherein the metal ceramic composite material layer is made of a material different from a material of upper barrier layer and lower barrier layer; and
a first lamina layer disposed between the PCM layer and the first electrode.

US Pat. No. 10,892,405

HALL-EFFECT SENSOR PACKAGE WITH ADDED CURRENT PATH

TEXAS INSTRUMENTS INCORPO...

1. A Hall-effect sensor package, comprising:an integrated circuit (IC) die including at least one Hall-effect sensor element and signal processing circuitry including at least an amplifier coupled to an output node of the Hall-effect element;
a leadframe including:
a plurality of leads including a first plurality of leads on a first side of the package providing a first field generating current (FGC) path including at least one first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to at least one first FGC output pin and a second plurality of leads on a second side of the package that is opposite to the first side;
wherein at least some of the plurality of leads on the second side are attached to bond pads on the IC die including to an output of the Hall-effect sensor element, and
a clip attached at one end to a location on the first FGC input pin and at another end to a location on the first FGC output pin with a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first curved head for providing a parallel FGC path with respect to the first FGC path.

US Pat. No. 10,892,404

SACRIFICIAL BUFFER LAYER FOR METAL REMOVAL AT A BEVEL EDGE OF A SUBSTRATE

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming one or more contacts over a top surface of a substrate;
forming a dielectric layer surrounding the one or more contacts over the top surface and a bevel edge of the substrate;
forming a sacrificial buffer layer over the dielectric layer on the top surface and the bevel edge of the substrate;
removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate leaving the sacrificial buffer layer on the bevel edge of the substrate;
patterning one or more device structures comprising one or more metal layers over the one or more contacts, wherein patterning the one or more device structures comprises removing portions of the one or more metal layers formed over the dielectric layer on the top surface of the substrate leaving the one or more metal layers on the bevel edge of the substrate;
forming an encapsulation layer over the one or more device structures and the dielectric layer on the top surface of the substrate;
performing a bevel dry etch to remove the encapsulation layer and the one or more metal layers on the bevel edge of the substrate, the bevel dry etch damaging the sacrificial buffer layer on the bevel edge underneath the one or more metal layers; and
removing the damaged sacrificial buffer layer from the bevel edge of the substrate.

US Pat. No. 10,892,403

STRUCTURED BOTTOM ELECTRODE FOR MTJ CONTAINING DEVICES

International Business Ma...

1. A magnetic tunnel junction (MTJ) containing device comprising:a bottom electrode structure comprising a mesa portion and a laterally adjacent recessed region;
a dielectric material located laterally adjacent to the recessed region of the bottom electrode structure;
a MTJ pillar located on a topmost surface of the mesa portion of the bottom electrode structure;
a top electrode located on the MTJ pillar; and
a passivation material spacer located on a sidewall of each of the top electrode and the MTJ pillar, wherein a bottommost surface of the passivation material spacer is in direct physical contact with the topmost surface of the mesa portion of the bottom electrode structure.

US Pat. No. 10,892,402

MAGNETORESISTIVE ELEMENT, AND PRODUCTION METHOD FOR MAGNETORESISTIVE ELEMENT

KONICA MINOLTA, INC., To...

1. A production method for a magnetoresistive element, comprising:treating a stacked layer into a predetermined shape, the stacked layer including a magnetoresistive layer whose resistance changes depending on a magnetic field and a cap layer which is above the magnetoresistive layer and which has a layer thickness in a range of 10 nm to 60 nm;
covering and protecting the stacked layer with an insulating layer;
forming an opening in the insulating layer by reactive etching and exposing a surface of the cap layer at the opening;
etching the cap layer in a range less than a total layer thickness of the cap layer by ion milling of the surface of the cap layer which is exposed at the opening in the exposing; and
depositing an upper layer to be a part of the magnetoresistive element, the upper layer being in contact with the surface of the cap layer which is left after the etching.

US Pat. No. 10,892,401

SPIN CURRENT MAGNETIZATION ROTATIONAL ELEMENT, MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY

TDK CORPORATION, Tokyo (...

1. A magnetoresistance effect element comprising:a spin current magnetization rotational element containing a ferromagnetic metal layer and spin-orbit torque wiring;
another ferromagnetic metal layer having a fixed magnetization orientation; and
a non-magnetic layer sandwiched between the another ferromagnetic metal layer and the ferromagnetic metal layer, wherein
the ferromagnetic metal layer has a variable magnetization direction,
the spin-orbit torque wiring extends in a direction that intersects a direction perpendicular to a surface of the ferromagnetic metal layer and is connected to the ferromagnetic metal layer,
a spin resistance of a connection portion of the spin-orbit torque wiring that is connected to the ferromagnetic metal layer is larger than a spin resistance of the ferromagnetic metal layer, and
the spin-orbit torque wiring has a side wall connection portion that contacts a portion of a side wall of the ferromagnetic metal layer.

US Pat. No. 10,892,400

MAGNETIC MEMORY DEVICE

Samsung Electronics Co., ...

1. A magnetic memory device comprising:a buffer layer on a substrate;
a magnetic tunnel junction structure on the buffer layer, the magnetic tunnel junction structure comprising a fixed layer structure, a tunnel barrier, and a free layer that are sequentially stacked on the buffer layer; and
a spin-orbit torque (SOT) structure on the magnetic tunnel junction structure, the SOT structure comprising a topological insulator material,
wherein the free layer comprises a Heusler material.

US Pat. No. 10,892,399

POWERLESS MAGNETIC FIELD SENSING USING MAGNETOELECTRIC NANOWIRES

University of Florida Res...

1. A magnetic field sensor device comprising:a first electrode positioned across a second electrode, wherein an electrode gap separates the first electrode and the second electrode;
a magnetoelectric nanowire connected to the first electrode and the second electrode across the electrode gap without substrate clamping;
wherein the magnetoelectric nanowire generates a voltage response in a presence of a magnetic field.

US Pat. No. 10,892,398

QUBIT HARDWARE FOR ELECTRONS ON HELIUM

1. A system comprising:a substrate to support a film of liquid helium, wherein the film of liquid helium is to support an electron subsystem comprising electrons that are confined, in a direction perpendicular to a surface of the film of liquid helium, by image forces of electrostatic attraction to the film of liquid helium;
a side gate to receive a side gate voltage to electrostatically define a boundary of the electron subsystem;
a trap gate to receive a trap voltage to electrostatically define an electron trap located outside the boundary of the electron subsystem; and
a load gate to selectively open and close access from the electron subsystem to the electron trap, wherein to open access of the electron subsystem to the electron trap is to apply a first load gate voltage to the load gate to allow the electrons of the electron subsystem to access the electron trap, and wherein to close access of the electron subsystem to the electron trap is to apply a second load gate voltage to the load gate to prevent the electrons of the electron subsystem from accessing the electron trap.

US Pat. No. 10,892,397

SELF-MONITORING SUPERCONDUCTING TAPE VIA INTEGRATED OPTICAL FIBERS

NORTH CAROLINA STATE UNIV...

1. A high-temperature superconductor (HTS) laminate structure, comprising:an HTS-based insert extending from a first end to a second end;
one or more optical fibers coupled to the HTS-based insert and extending along a length of the HTS-based insert from the first end to the second end of the HTS-based insert for the HTS laminate structure;
an encapsulate surrounding the HTS-based insert and the one or more optical fibers, wherein the encapsulate is in contact with the HTS-based insert and the one or more optical fibers, wherein the encapsulate comprises a metal stabilizer; and
an optical distributed sensor interrogator coupled to the one or more optical fibers of the HTS laminate structure to receive an optical signal that is Rayleigh backscattered from the one or more optical fibers along the length of the HTS-based insert for the HTS laminate structure.

US Pat. No. 10,892,396

STABILIZED COPPER SELENIDE THERMOELECTRIC MATERIALS AND METHODS OF FABRICATION THEREOF

THE REGENTS OF THE UNIVER...

1. A thermoelectric composition comprising:a nanocomposite comprising a copper selenide (Cu2Se) matrix having a plurality of nanoinclusions comprising copper metal selenide (CuMSe2) distributed therein, wherein M is selected from the group consisting of: indium (In), aluminum (Al), gallium (Ga), antimony (Sb), bismuth (Bi), and combinations thereof and the thermoelectric composition has an average figure of merit (ZT) of greater than or equal to about 1.5 at a temperature of less than or equal to about 850K (about 577° C.).

US Pat. No. 10,892,395

THERMOELECTRIC CONVERSION MATERIAL AND PRODUCTION METHOD THEREOF

TOYOTA JIDOSHA KABUSHIKI ...

1. A thermoelectric conversion material comprising a matrix and a barrier material, wherein:the matrix contains Mg2Si1-xSnx (x is from 0.50 to 0.80) and an n-type dopant,
the barrier material contains Mg2Si1-ySny (y is from 0 to 0.30),
the matrix is divided into a high-temperature-side matrix and a low-temperature-side matrix by the barrier material,
a high-temperature-side interface is present between the high-temperature-side matrix and the barrier material,
a low-temperature-side interface is present between the barrier material and the low-temperature-side matrix,
a band offset ?Ec is formed on a conduction band side in the high-temperature-side interface and the low-temperature-side interface,
a band offset ?Ev is formed on a valence band side in the high-temperature-side interface and the low-temperature-side interface, and
the band offset ?Ec is 0.1 eV or less and the band offset ?Ev is 0.10 eV or more.

US Pat. No. 10,892,394

HIGHER MANGANESE SILICIDE BASED TELLURIDE COMPOSITE FOR THERMOELECTRIC CONVERSION AND PREPARATION METHOD THEREOF

TOYOTA JIDOSHA KABUSHIKI ...

1. A higher manganese silicide based telluride composite for thermoelectric conversion represented by the following general formula (1):(MnSi1.740±0.015)1?x(MnTe)x  (1)
wherein
x is the molar fraction of manganese telluride in the higher manganese silicide based telluride composite for thermoelectric conversion and satisfies the relation 0 a maximum ZT value of the higher manganese silicide based telluride composite for thermoelectric conversion is 0.40 or more.

US Pat. No. 10,892,393

LIGHT EMITTING DEVICE HAVING EXTERNAL CONNECTION WITH DIFFERENT WIDTH

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a substrate including
an insulating base material having a first main surface, a second main surface that is opposite from the first main surface, and a mounting surface that is adjacent to at least the second main surface,
a pair of connection terminals disposed on the first main surface, and
a pair of external connection sections disposed on the second main surface, each of the external connection sections having a narrow-width region and a wide-width region with a width of the wide-width region being wider than a width of the narrow-width region;
a light emitting element having a pair of electrodes connected to element connection sections of the pair of connection terminals;
a light transmissive member disposed on an upper surface of the light emitting element; and
a sealing member covering at least a part of a side surface of the light emitting element and at least a part of the light transmissive member.

US Pat. No. 10,892,392

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

NICHIA CORPORATION, Anan...

1. A method for manufacturing a semiconductor device, the method comprising:preparing a structure body comprising a semiconductor stacked body, wherein a first surface of the structure body comprises a concave portion;
forming a first metal portion on a substrate, the first metal portion comprising a plurality of pores; and
after forming the first metal portion on the substrate, bonding the first metal portion to the structure body, such that:
the first metal portion is located between the structure body and the substrate,
a first part of the first metal portion is bonded to the concave portion of the first surface, and a second part of the first metal portion is bonded to a part of the first surface other than the concave portion,
the first metal portion is bonded to the first surface such that at least a portion of the concave portion is filled with the first metal portion, and
an average diameter of a plurality of the pores in the second part of the first metal portion is smaller than an average diameter of a plurality of the pores in the first part of the first metal portion.

US Pat. No. 10,892,391

LIGHT-EMITTING DEVICE PACKAGE INCLUDING A LEAD FRAME

SAMSUNG ELECTRONICS CO., ...

1. A light-emitting device package, comprising:a lead frame comprising a first metallic lead and a second metallic lead that are spaced apart from each other in a first direction;
a light-emitting device chip mounted on a first area of the lead frame, the first area of the lead frame including a part of the first metallic lead and a part of the second metallic lead; and
a molding structure comprising:
an outer barrier surrounding at least a part of the lead frame, and
an electrode separator disposed between the first metallic lead and the second metallic lead and filling space between the first metallic lead and the second metallic lead, the electrode separator extending in a second direction intersecting the first direction,
wherein each of the first metallic lead and the second metallic lead comprises at least two inner slots formed to extend in the first direction, the at least two inner slots of the first metallic lead penetrating through the first metallic lead from an upper surface to a lower surface of the first metallic lead, the at least two inner slots of the second metallic lead penetrating through the second metallic lead from an upper surface to a lower surface of the second metallic lead, and,
wherein the molding structure comprises inner slot molding parts integrally connected to the electrode separator and filling the at least two inner slots of each of the first metallic lead and the second metallic lead.

US Pat. No. 10,892,390

LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING ELEMENT PACKAGE INCLUDING THE SAME

LG INNOTEK CO., LTD., Se...

1. A light-emitting element comprising:a light-emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer in a first direction;
a reflective layer disposed on the second conductive type semiconductor layer;
a capping layer disposed on the reflective layer;
a first electrode electrically connected to the first conductive type semiconductor layer;
an insulating layer disposed on the first electrode and the capping layer;
a first bonding pad penetrating the insulating layer and electrically connected to the first electrode; and
a second bonding pad penetrating the insulating layer and electrically connected to the capping layer, the second bonding pad spaced from the first bonding pad in a second direction different from the first direction,
wherein the light-emitting structure includes a recess extending to a partial region of the first conductive type semiconductor layer through the second conductive type semiconductor layer and the active layer,
wherein the first electrode is disposed in the recess and electrically connected to the first conductive type semiconductor layer,
wherein the first electrode includes a portion spaced from the second bonding pad in a third direction different from the first direction and the second direction,
wherein the reflective layer is disposed to be spaced apart from the recess,
and
wherein an entirety of the first electrode and the second bonding pad are disposed not to overlap each other in the first direction.

US Pat. No. 10,892,389

PACKAGING LEADFRAME AND PACKAGING STRUCTURE

KAISTAR LIGHTING (XIAMEN)...

1. A packaging lead frame, comprising:a substrate layer, disposed with a circuit layer wherein the circuit layer has a cathode and an anode arranged on an upper surface of the substrate layer, and the cathode and the anode are configured for electrically connecting with a light emitting diode (LED) chip and whereby the cathode as well as the anode are located between the upper surface and the LED chip; and
a sidewall structure disposed on the substrate layer, wherein the materials of sidewall structure comprises a halocarbon polymer and a plurality of light reflective particles uniformly mixed together, the sidewall structure is ring-shaped to expose the cathode and the anode and further is configured for reflecting light emitted from the LED chip, and the plurality of light reflective particles are configured for increasing a reflectivity of the halocarbon polymer to the light.

US Pat. No. 10,892,388

GESN NANOBEAM LIGHT-EMITTING DIODE

United States of America ...

1. An LED structure comprising:a thick Si substrate having a thickness of greater than 50 nm and less than 1000 nm;
a thin Si layer having a thickness of about 50 nm formed on the thick silicon substrate;
a relaxed Ge buffer layer having a thickness of about 50 nm formed on the thin Si layer;
a nanobeam formed on the Ge buffer layer having a left nanobeam section, a central nanobeam section and a right nanobeam section;
the central nanobeam section including:
1) a bottom germanium rib layer having a length of about 1.0 to 1.4 micrometers a thickness of about 50 nanometers and a width of about 1600 nanometers formed on the relaxed germanium buffer layer and being N doped,
2) a middle germanium-tin layer having a length of about 1.0 to 1.4 micrometers, a thickness of about 200 nm having a width of about 420 nm formed on the bottom germanium rib layer, the middle germanium-tin layer being formed in the mid-region of the bottom germanium rib layer such that the bottom germanium rib layer includes wing extensions extending outwardly from either side of the middle germanium-tin layer, the wing extensions having a width of about 590 nm on each side of the middle germanium-tin layer,
3) a top germanium layer having a length of about 1.0 to 1.4 micrometers, a thickness of about 50 nm and a width of about 420 nm formed on the middle germanium-tin layer and being P doped;
4) a first metal contact having a length of about 100 nm, a width of about 420 nm and a thickness of about 100 nm and being formed on the top germanium layer, and
5) a second metal contact having a length of about 100 nm, a width of 200 nm and thickness of about 100 nm, and being formed on the wing extension of the N doped bottom germanium rib layer and being spaced apart from the middle germanium-tin layer by a distance of about 390 nanometers;
the left nanobeam section including:
1) a left germanium rib layer having a length of about 4.0 micrometers, a thickness of about 50 nanometers and a width of about 1600 nanometers formed on the relaxed germanium buffer layer, the left germanium rib layer extending from the bottom germanium rib layer, and
2) a left germanium nanobeam having a length of about 4.0 micrometers, a thickness of about 250 nm and a width of about 420 nm, the left germanium nanobeam extending from the middle germanium-tin layer and the top germanium layer;
the right nanobeam section including:
1) a right germanium rib layer having a length of about 4.0 micrometers, a thickness of about 50 nanometers and a width of about 1600 nanometers formed on the relaxed germanium buffer layer, the left germanium rib layer extending from the bottom germanium rib layer, and
2) a right germanium nanobeam having a length of about 4.0 micrometers, a thickness of about 250 nm and a width of about 420 nm, the right germanium nanobeam extending from the middle germanium-tin layer and the top germanium layer;
a plurality of cylindrical holes extending through the first metal contact, the nanobeam, the relaxed Ge buffer layer, and the thin Si layer and into the thick Si substrate, the plurality of holes being arranged in a row along the nanobeam and being sized and spaced apart to form a zero point-defect resonator, the diameters of the holes being reduced as the position of the hole moves away from the center of the nanobeam towards the ends of the left and right sections of the nanobeam in accordance with a Gaussian taper with the holes nearest the center of the nanobeam having a diameter of 0.34a and the holes at the end of the left and right sections of the nanobeam having a diameter of 0.25a, where a is the lattice constant and is about 350 nanometers; and
an electrical circuit connected between the first and second metal contacts to supply an electrical signal that energizes the middle section of the nanobeam to emit light as a light emitting diode and transmit light down both the left and right sections of the nanobeam which functions as a resonance enhanced lightguide.

US Pat. No. 10,892,387

LIGHTING DEVICE WITH SWITCHING MATERIAL

Lumileds, LLC, San Jose,...

1. A lighting device, comprising:a light-emitting module having independently-addressable adjacent light-emitting elements without a reflective barrier disposed therebetween, the light-emitting elements being configured to emit light towards a light-emitting side; and
a top layer disposed on the light-emitting module at the light-emitting side, the top layer comprising a switching material capable of a reversible change in transmittance for the light emitted by the light-emitting elements, the top layer being controllable to individually change to a higher transmittance in regions of the top layer situated on each of light-emitting elements in a switched-on state compared to a transmittance in regions of the top layer situated on each of light-emitting elements in a switched-off state, the switching material having a porous structure that comprises:
a non-light absorbing material structure having a plurality of sub-micron pores, and
a polymer matrix filling the sub-micron pores, a difference between a refractive index of the non-light absorbing material structure and a refractive index of the polymer matrix changeable with temperature.

US Pat. No. 10,892,386

WAFER-LEVEL LIGHT EMITTING DIODE PACKAGE AND METHOD OF FABRICATING THE SAME

SEOUL SEMICONDUCTOR CO., ...

1. A light emitting diode (LED) package, comprising one or more light emitting diodes to emit light, wherein each single light emitting diode includes:a semiconductor stack comprising a first conductive type semiconductor layer, a second conductive type semiconductor layer and an active layer that is interposed between the first and second semiconductor layers to generate light under an electrical signal applied to the first and second type semiconductor layers, the first conductive type semiconductor layer shaped to include an inclined side wall;
means in the second conductive type semiconductor layer and the active layer for exposing the first conductive type semiconductor layer;
a first bump arranged on a first side of the semiconductor stack and electrically coupled to an exposed part of the first conductive type semiconductor layer;
a second bump arranged on the first side of the semiconductor stack and electrically coupled to the second conductive type semiconductor layer;
a protective insulation layer covering an entire sidewall of the semiconductor stack of each light emitting diode; and
an electrically conductive material on the first side of the semiconductor stack between, and electrically insulated from, the first and second bumps to dissipate heat from the LED package.

US Pat. No. 10,892,385

LED FABRICATION USING HIGH-REFRACTIVE-INDEX ADHESIVES

LUMILEDS LLC, San Jose, ...

1. An apparatus comprising:a sapphire substrate having a first surface and an oppositely positioned second surface;
an epitaxial layer disposed on the first surface of the sapphire substrate, the epitaxial layer
forming an active region of a light-emitting diode that emits visible blue light in a wavelength range of about 450 to about 470 nm;
a wavelength converting member disposed adjacent the second surface of the sapphire substrate; and
a silicone-containing adhesive layer disposed between the second surface of the sapphire substrate and the wavelength-converting member, in direct contact with the second surface of the sapphire substrate, in direct contact with the wavelength converting member, formed by a cyclic ring-opening polymerization of the silicone, comprising amounts of at least one organic base, and exhibiting a crosslink density gradient between the second surface of the sapphire substrate and the wavelength converting member.

US Pat. No. 10,892,384

ETCHED TRENCHES IN BOND MATERIALS FOR DIE SINGULATION, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

11. A method of singulating SST dies on a substrate, comprising:bonding a carrier substrate and a semiconductor die material by forming intermetallic compounds between the die material and the carrier substrate, with the intermetallic compounds forming a bond material, the die material including a plurality of unsingulated SST dies;
forming a plurality of dicing streets between neighboring SST dies by exposing the bond material between neighboring SST dies;
etching through the exposed bond material at the dicing streets to form a plurality of trenches in the substrate, wherein individual trenches have lateral side portions at least partially extending through the bond material and a bottom portion at least partially extending into the carrier substrate;
at least partially encapsulating the SST dies and the side portions of the trenches with a protective material;
forming a plurality of openings in the protective material to partially expose a first side of the SST dies;
forming a plurality of contacts at the corresponding openings; and
singulating the carrier substrate along the trenches using a mechanical saw.

US Pat. No. 10,892,383

LIGHT EMITTING DIODE PACKAGE AND METHOD FOR FABRICATING SAME

Cree, Inc., Durham, NC (...

1. A method for fabricating a plurality of surface mount Light Emitting Diode (LED) packages, comprising:sizing a submount panel to accommodate formation of a plurality of LED packages;
forming sets of attach pads and contact pads on a first surface of said submount panel, each of said sets of attach pads and contact pads corresponding to one of said LED packages formed from said submount panel;
attaching a plurality of LEDs to said submount panel, each of said plurality of LEDs attached to an electrically connected to one of said sets of attach pads and contact pads;
molding a plurality of hemispherical lenses on said submount panel, each hemispherical lens in said plurality of hemispherical lenses coupled to the first surface of said submount panel and coupled over one LED in said plurality of said LEDs, such that at least a portion of said hemispherical lenses is directly coupled to the first surface of said submount panel, said hemispherical lenses comprising a protective layer on and covering the first surface of said submount panel between said hemispherical lens and an edge of said submount panel;
forming sets of surface mount contacts on the surface of said submount panel opposite said sets of attach pads and contact pads, each of said sets of said surface mount contacts corresponding to a respective one of said sets of attach pads and contact pads; and
singulating said submount panel into a plurality of LED packages, wherein each of said plurality of said singulated LED packages comprises at least one of said attach pads and at least one of said contact pads that in combination cover at least 75% of said first surface of the portion of said submount panel in said singulated LED package.

US Pat. No. 10,892,382

SEMICONDUCTOR LIGHT-EMITTING ELEMENT

NICHIA CORPORATION, Anan...

15. A semiconductor light-emitting element comprising:a sapphire substrate;
a first semiconductor layer formed on the sapphire substrate;
a second semiconductor layer;
a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer;
a first electrode connected to the first semiconductor layer; and
a second electrode connected to the second semiconductor layer,
wherein the second electrode comprises:
a light-transmissive connection electrode in contact with the second semiconductor layer,
a light-transmissive semiconductor electrode in contact with the connection electrode, the light-transmissive semiconductor electrode being made of a semiconductor layer, and
a pad electrode in contact with a first portion of the uppermost surface of the light-transmissive semiconductor electrode, such that a second portion of the uppermost surface of the light-transmissive semiconductor electrode is exposed from the pad electrode; and
wherein the light-transmissive connection electrode is an ohmic electrode that includes:
a first ohmic electrode ohmically contacting the second semiconductor layer, and
a second ohmic electrode bonded to the first ohmic electrode by surface activation bonding or atomic diffusion bonding, and ohmically contacting the semiconductor electrode,
wherein both the first ohmic electrode and the second ohmic electrode are made of indium tin oxide.

US Pat. No. 10,892,381

SEMICONDUCTOR STRUCTURE WITH LAYER HAVING PROTRUSIONS

Sensor Electronic Technol...

1. A heterostructure for an optoelectronic device, the heterostructure comprising:an active region configured to operate in conjunction with radiation having an operating wavelength;
a substrate having a growth surface; and
a growth layer located between the active region and the growth surface of the substrate, wherein the growth layer is formed of a first material and includes a plurality of protruding domains extending away from the growth surface of the substrate toward the active region, wherein the first material comprises aluminum oxide, and wherein at least some of the plurality of protruding domains include internal regions comprising a second material different from the first material, wherein an index of refraction of the second material for radiation having the operating wavelength is lower than an index of refraction of the first material for radiation having the operating wavelength.

US Pat. No. 10,892,380

LIGHT-EMITTING DEVICE

EPISTAR CORPORATION, Hsi...

1. A light-emitting device, comprising:a substrate;
a bonding layer on the substrate;
a light-emitting stack on the bonding layer and having a first-type semiconductor layer, a second-type semiconductor layer, and an active layer between the first-type semiconductor layer and the second-type semiconductor layer;
a reflective structure between the first-type semiconductor layer and the substrate;
a void between the substrate and the light-emitting stack;
a first interface between the substrate and the light-emitting stack; and
a second interface on the void;
wherein the void is enclosed and embedded within the light-emitting device and directly contacts the bonding layer, the reflective structure electrically connects to the first-type semiconductor layer at the first interface, and a critical angle at the first interface for a light emitted from the light-emitting stack is larger than that at the second interface.

US Pat. No. 10,892,379

HIGH EFFICIENCY VISIBLE AND ULTRAVIOLET NANOWIRE EMITTERS

1. A device, comprising:a substrate; and
a light-emitting diode (LED) comprising a plurality of nanowires disposed on the substrate, wherein the nanowires have a filling factor greater than 30 percent,
wherein the plurality of nanowires comprise a nanowire that has a core-shell structure comprising a shell region and a core region inside the shell region, wherein the nanowire comprises a quaternary compound comprising Group III elements and a Group V element, wherein the shell region has a concentration of a first Group III element higher than a concentration of the first Group III element in the core region.

US Pat. No. 10,892,378

METHOD OF MAKING A SEMI-POLAR NITRIDE LAYER ON A CRYSTALLINE SUBSTRATE

CENTRE NATIONAL DE LA REC...

1. A method for obtaining at least one semi-polar nitride layer obtained from a gallium and nitrogen based material on an upper surface of a crystalline substrate of cubic symmetry, the method comprising:(i) etching a plurality of parallel grooves from the upper surface of the crystalline substrate, each groove comprising at least two opposed inclined facets, at least one of the two opposed facets having a crystalline orientation <111>;
(ii) forming a mask above the upper surface of the crystalline substrate such that the facets opposite to the facets having the crystalline orientation <111> are masked and that the facets having the crystalline orientation <111> are not masked; and
(iii) after forming the mask in (ii), forming the semi-polar nitride layer by epitaxial growth from the non-masked facets having the crystalline orientation <111>;
wherein forming the semi-polar nitride layer in (iii) comprises:
at least one first epitaxial growth phase, carried out from the non-masked facets having the crystalline orientation <111> so as to form a seed in a plurality at least of parallel grooves;
interrupting of the first epitaxial growth phase when the seed has an inclined facet having a crystalline orientation 0001 and an upper facet having a crystalline semi-polar orientation 1011;
a surface treatment comprising a modification of an upper portion of the seed by placing the seed in presence with at least one gas comprising silicon so as to form on the surface of the seed a modified portion comprising silicon; and
at least one second epitaxial growth phase of the material, carried out from the inclined facet having the crystalline orientation 0001, the second epitaxial growth phase being continued until coalescence of seeds of adjacent parallel grooves.

US Pat. No. 10,892,377

SELECTIVE DEPOSITION FOR INTERDIGITATED PATTERNS IN SOLAR CELLS

IMEC VZW, Leuven (BE)

1. A method for creating an interdigitated pattern for a solar cell, comprising:providing a substrate of the solar cell, wherein a surface of the substrate includes one or more exposed regions and one or more regions covered by a patterned first passivation layer stack protected by a hard mask; and
selectively depositing a second passivation layer stack comprising at least a first layer of amorphous silicon (a-Si) on the one or more exposed regions such that the first passivation layer stack and the second passivation layer stack form the interdigitated pattern,
wherein selectively depositing the second passivation layer stack comprises:
1a) adding, using a plasma deposition process, a sublayer of the first layer on the hard mask and in the one or more exposed regions of the surface;
1b) etching, using a plasma etch process, the added sublayer on the hard mask and in the one or more exposed regions, wherein an etch rate of the added sublayer on the hard mask is higher than an etch rate of the added sublayer in the one or more exposed regions, thereby substantially removing the added sublayer from the hard mask and leaving a finite thickness of the added sublayer in the one or more exposed regions; and
1c) cleaning, using a plasma cleaning process, a surface of the remaining added sublayer in the one or more exposed regions from contaminants remaining from the plasma etch process, and adding a further sublayer of the first layer in the one or more exposed regions by repeating steps 1a) and 1b),
wherein step 1c) is repeated until a desired thickness of the first layer in the one or more exposed regions is obtained.

US Pat. No. 10,892,376

METHOD AND DEVICE FOR PRODUCING A PHOTOVOLTAIC ELEMENT WITH STABILISED EFFICIENCY

1. A method for producing a photovoltaic element with stabilised efficiency, comprising the following steps:providing a silicon substrate;
forming an emitter layer at a surface of the silicon substrate;
forming electrical contacts on the silicon substrate;
wherein the method further comprises a stabilising treatment step comprising:
introducing hydrogen into the silicon substrate from a hydrogen-containing dielectric layer applied onto the silicon substrate, wherein the hydrogen is introduced at temperatures of the substrate above 650° C. and subsequent cooling the substrate to 450° C. is carried out with a ramp at a cooling rate of at least 10° C./s, preferably at least 20° C./s, more preferably at least 30° C./s, yet more preferably at least 60° C./s, while the substrate is at a temperature above 550° C. during the cooling of the substrate; and
generating excess minority charge carriers in the silicon substrate while the silicon substrate is at a temperature above 230° C., wherein the excess minority charge carriers are generated by illumination with an illumination intensity greater than 1 kW/m2 with light having wavelengths less than 1180 nm.

US Pat. No. 10,892,375

PHOTONIC ENERGY STORAGE DEVICE

Quantum Photonics Corpora...

1. A photonic energy storage device, comprising:a storage device body, the storage device body surrounding a sealed environment in which is provided a set of at least three thin layers of reactive material, the set of layers comprising:
a plurality of reflective coatings;
a plurality of photovoltaic layers each coupled to one of the plurality of reflective coatings; and
a plurality of optical amplification layers each coupled to one of the plurality of photovoltaic layers;
wherein the plurality of reflective coatings, the plurality of photovoltaic cell layers, and the plurality of optical amplification layers are arranged in a pattern whereby every second element in the pattern is a photovoltaic cell layer; and
at least one integrated LED wafer comprising one or more LEDs disposed in a first direction from the plurality of optical amplification layers, configured to direct light emitted by the one or more LEDs of the integrated LED wafer against at least one of the plurality of reflective coatings.

US Pat. No. 10,892,374

METHOD FOR FABRICATION OF GERMANIUM PHOTODIODE WITH SILICON CAP

Newport Fab, LLC, Newpor...

1. A method for fabricating a photodiode, said method comprising:opening a photodiode window in a hard mask disposed over a silicon substrate;
forming a germanium structure in said photodiode window;
forming a blanket silicon layer over said germanium structure and said hard mask;
forming an N type germanium region in said germanium structure, said N type germanium region being a cathode of said photodiode;
implanting with P type dopants to form a P type germanium region in said germanium structure over said N type germanium region, and a P type silicon cap in said blanket silicon layer over said P type germanium region, said P type germanium region being an anode of said photodiode;
forming an anode contact and a cathode contact of said photodiode.

US Pat. No. 10,892,373

GERMANIUM PHOTODIODE WITH SILICON CAP

Newport Fab, LLC, Newpor...

1. A photodiode comprising:a top silicon layer in a silicon-on-insulator (SOI) device;
an N type germanium region situated over said top silicon layer, said N type germanium region being a cathode of said photodiode;
a P type germanium region situated over said N type germanium region, said P type germanium region being an anode of said photodiode;
a P type silicon cap over said P type germanium region;
a cathode contact of said photodiode being situated on an N type region of said top silicon layer that is electrically connected to said N type germanium region of said photodiode.

US Pat. No. 10,892,372

HIGH PERFORMANCE SOLAR CELLS, ARRAYS AND MANUFACTURING PROCESSES THEREFOR

mPower Technology, Inc., ...

1. A solar cell array assembly comprising interconnected photovoltaic cells, the solar cell array assembly comprising:a flexible substrate;
a first string of first non-overlapping singulated photovoltaic cells electrically connected in series; and
a second string of second non-overlapping singulated photovoltaic cells electrically connected in series, said second string electrically connected in parallel with said first string;
wherein each of said first non-overlapping singulated photovoltaic cells have a first shape and a first area and each of said second non-overlapping singulated photovoltaic cells have a second shape different from said first shape and a second area different from said first area;
wherein said first non-overlapping singulated photovoltaic cells are intermingled with said second non-overlapping singulated photovoltaic cells on said flexible substrate; and
wherein said different shapes and said intermingling enable the solar cell array assembly to be flexible in more than two directions.

US Pat. No. 10,892,371

SOLAR MODULE CONSTRUCTION

S. E. TRACK AG, Zug (CH)...

1. A solar module array constructed from a multiplicity of adjacently disposed solar module constructions,wherein each of the solar module constructions comprises:
a support unit with a triangular base and a plurality of triangular lateral planes,
wherein the support unit forms a pyramidal supporting frame,
wherein the triangular base is spanned by base struts and the triangular lateral planes are spanned by lateral struts;
a first flexible material is stretched over a first of the triangular lateral planes,
a second flexible material is stretched over a second of the triangular lateral planes,
wherein each of the first and second flexible material has at least one feature of transparency, reflectivity, structure, sound absorbency, and tint,
wherein the at least one feature of the first flexible material differs from the at least one feature of the second flexible material,
and photovoltaic units provided on at least one of the triangular lateral planes of the support unit,
wherein the photovoltaic units comprise flexible solar modules attached on an outside surface of the first and/or second flexible material of at least one of the triangular lateral planes,
wherein two adjacently disposed solar module constructions within the solar module array form a solar module pair, in which the bases of the two adjacently disposed solar module constructions within the pair abut one another to form a parallelogram.

US Pat. No. 10,892,370

PHOTOELECTRIC CONVERSION DEVICE AND METHOD OF MANUFACTURING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A method of manufacturing a photoelectric conversion device, the method comprising:forming a first transparent electrode and a second transparent electrode on a transparent substrate, the second transparent electrode being adjacent to the first transparent electrode and separated from the first transparent electrode;
forming a conductive layer containing noble metal as a main component, on a partial region adjacent to the first transparent electrode on the second transparent electrode;
forming a fine particle layer having a stack of fine particles, on at least the conductive layer;
forming an active layer above the transparent substrate so as to cover the first transparent electrode, the second transparent electrode, and the fine particle layer;
scribing the active layer and the fine particle layer along a formation region of the conductive layer to form a scribe groove penetrating through the active layer and the fine particle layer and exposing a surface of the conductive layer; and
forming a first counter electrode and a second counter electrode corresponding to the first transparent electrode and the second transparent electrode, on the active layer divided by the scribe groove,
wherein the first counter electrode is electrically connected with the second transparent electrode via the conductive layer and a conductive layer having a part of the first counter electrode filled in the scribe groove.

US Pat. No. 10,892,369

PHOTODIODE HAVING AN ALUMINUM METAL OHMIC CONTACT AND A SPINEL OXIDE LAYER

King Abdulaziz University...

1. A photodiode, comprising:an aluminum metal ohmic contact having a first work function;
an inorganic substrate layer in continuous contact with the ohmic contact;
a photoactive layer in continuous contact with the inorganic substrate layer;
a light absorption layer in continuous contact with the photoactive layer; and
a top electrode in contact with the light absorption layer, the top electrode having a second work function;
wherein the inorganic substrate layer comprises a semiconductor;
wherein the photoactive layer consists of ZnFe2O4 nanowires in N2, the ZnFe2O4 nanowires present at 80-90 vol % relative to a total volume of the photoactive layer;
wherein the ZnFe2O4 nanowires have widths of 35-45 nm and lengths of 170-350 nm;
wherein all ZnFe2O4 nanowires are physically adsorbed to the inorganic substrate layer and to the light absorption layer;
wherein the inorganic substrate layer and the photoactive layer are both p-type semiconductors forming an isotype junction between each other;
wherein the light absorption layer comprises at least one material selected from the group consisting of quantum dots, quantum rods, and quantum wires; and
wherein the second work function is higher than the first work function.

US Pat. No. 10,892,368

NANOSHEET TRANSISTOR HAVING ABRUPT JUNCTIONS BETWEEN THE CHANNEL NANOSHEETS AND THE SOURCE/DRAIN EXTENSION REGIONS

INTERNATIONAL BUSINESS MA...

1. A method of performing fabrication operations to form a nanosheet field effect transistor (FET) device, wherein the fabrication operations include:forming a nanosheet stack over a substrate;
wherein the nanosheet stack comprises a plurality of channel nanosheets;
wherein the plurality of channel nanosheets includes a first channel nanosheet having a first end region, a second end region, and a central region positioned between the first end region and the second end region;
wherein the first end region, the second end region, and the central region each comprises a first type of semiconductor material;
wherein, when the first type of semiconductor material is at a first temperature, the first type of semiconductor material has a first diffusion coefficient for a dopant; and
converting the central region to a second type of semiconductor material;
wherein, when the second type of semiconductor material is at the first temperature, the second type of semiconductor material has a second diffusion coefficient for the dopant.

US Pat. No. 10,892,367

METAL OXIDE FILM, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A manufacturing method of a semiconductor device, characterized by comprising:forming a first conductor containing oxygen and aluminum, over a first insulator;
forming a second insulator containing oxygen and silicon, over the first conductor;
forming an oxide over the second insulator by a sputtering method at an oxygen flow rate ratio lower than or equal to 20%;
performing a heat treatment;
forming a third insulator containing oxygen and silicon, over the oxide;
forming a second conductor over the third insulator;
forming a fourth insulator containing oxygen and silicon, over the third insulator and the second conductor; and
forming a fifth insulator containing oxygen and silicon, over the fourth insulator by a sputtering method.

US Pat. No. 10,892,366

THIN FILM TRANSISTOR AND VERTICAL NON-VOLATILE MEMORY DEVICE INCLUDING TRANSITION METAL-INDUCED POLYCRYSTALLINE METAL OXIDE CHANNEL LAYER

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a substrate;
a liner pattern including a transition metal on the substrate;
a polycrystalline metal oxide pattern on the liner pattern;
an insulating film extending along a sidewall of the liner pattern, a sidewall of the polycrystalline metal oxide pattern, and an upper surface of the polycrystalline metal oxide pattern; and
a gate electrode on the insulating film.

US Pat. No. 10,892,365

FIN FIELD EFFECT TRANSISTOR HAVING CRYSTALLINE TITANIUM GERMANOSILICIDE STRESSOR LAYER

UNITED MICROELECTRONICS C...

1. A fin field effect transistor, comprising:a semiconductor substrate comprising at least one fin structure extending along a first direction;
a metal gate disposed on the semiconductor substrate and traversing the at least one fin structure along a second direction, wherein the first direction is not parallel to the second direction;
at least a silicon germanium (SiGe) epitaxial region disposed on the fin structure and adjacent to the metal gate;
a contact structure disposed on the SiGe epitaxial region, wherein the contact structure comprises a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier;
a crystalline titanium germanosilicide stressor layer disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region; and
an amorphous titanium germanosilicide layer between the TiN barrier layer and the crystalline titanium germanosilicide stressor layer.

US Pat. No. 10,892,364

DIELECTRIC ISOLATED FIN WITH IMPROVED FIN PROFILE

INTERNATIONAL BUSINESS MA...

1. A fin field effect transistor (finFET) comprising:a semiconductor portion of a fin structure that is present on a dielectric base portion of the fin structure, wherein at least two peak uniform tail region portions each having a triangular cross section that are present at an interface of the semiconductor portion of the fin structure and the dielectric base portion of the fin structure one of each of the at least two peak uniform tail regions portions on opposing sidewalls of the fin structure, the at least two peak uniform tail regions connected by a centrally positioned planar upper surface of the dielectric base portion of the fin structure;
a gate structure present on a portion of the fin structure including a gate dielectric in contact with a channel portion of the fin structure; and
a source region and a drain region on opposing sides of the channel portion of the fin structure.

US Pat. No. 10,892,363

SEMICONDUCTOR DEVICE HAVING TERMINATION REGION WITH INSULATOR FILMS HAVING DIFFERENT COEFFICIENTS OF MOISTURE ABSORPTION

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a cell region in which a device is provided, and a termination region provided around the cell region;
a first insulating film provided on the semiconductor substrate in the termination region and having a plurality of openings;
a plurality of metal electrodes provided in the termination region and connected to the semiconductor substrate via the plurality of openings;
a second insulating film having lower coefficient of moisture absorption than that of the first insulating film and covering the first insulating film and the plurality of metal electrodes; and
a third insulating film having higher coefficient of moisture absorption than that of the first insulating film,
wherein the third insulating film has a first portion provided on the second insulating film and a second portion, and
the second portion is provided in a region from the outermost electrode of the plurality of metal electrodes to an end part of the semiconductor substrate, separated from the first portion, and in direct contact with the first insulating film without the second insulating film serving as an intermediary layer.

US Pat. No. 10,892,362

DEVICES FOR LDMOS AND OTHER MOS TRANSISTORS WITH HYBRID CONTACT

Silicet, LLC, Durham, NC...

1. A lateral DMOS transistor structure, comprising:(a) a substrate of a first dopant polarity;
(b) a body region of a first dopant polarity;
(d) a source region on or within the body region;
(e) a drift region of a second dopant polarity;
(f) a drain region on or within the drift region;
(g) a channel region between the source region and the drift region;
(h) a gate structure over the channel region;
(i) a hybrid contact implant, of the second dopant polarity, in the source region; and
(j) a respective metal contact on or within each of the source region, the gate structure, and the drain region;
(k) wherein the hybrid contact implant and the metal contact that is on or within the source region combine to form a hybrid contact that defines first, second, and third electrical junctions, wherein the first electrical junction is a Schottky junction formed vertically between the source metal contact and the body, wherein the second electrical junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant, and wherein the third electrical junction is a rectifying PN junction between the hybrid contact implant and the channel region; and
(l) wherein the hybrid contact implant has an as-implanted depth that defines a first depth, wherein the metal contact of the hybrid contact has a second depth, and wherein the first depth is less than that of the second depth.

US Pat. No. 10,892,361

LATERAL INSULATED-GATE BIPOLAR TRANSISTOR AND METHOD THEREFOR

NXP USA, INC., Austin, T...

1. A method of forming a lateral insulated-gate bipolar transistor formed as a Darlington configuration, the method comprising:forming an epitaxial layer of a first conductivity type at a top surface of a substrate;
implanting a first region to form a first body region of the first conductivity type in the epitaxial layer;
implanting a second region to form a second body region of a second conductivity type in the epitaxial layer adjacent to the first body region, the second conductivity type opposite of the first conductivity type;
implanting a third region to form a source region of the second conductivity type in the first body region, a portion of the first body region forming a channel region between the source region and the second body region;
forming an emitter region of the first conductivity type in the second body region;
forming a gate dielectric over the channel region; and
depositing a conductive material on the gate dielectric to form a gate electrode, the gate electrode overlapping at least a portion of second body region and the source region.

US Pat. No. 10,892,360

SEMICONDUCTOR DEVICE STRUCTURE WITH HIGH VOLTAGE DEVICE

Taiwan Semiconductor Manu...

1. A high-voltage semiconductor device structure, comprising:a semiconductor substrate;
a source ring in the semiconductor substrate;
a drain region in the semiconductor substrate;
a doped ring surrounding sides and a bottom of the source ring;
a well region surrounding sides and bottoms of the drain region and the doped ring, wherein the well region has a conductivity type opposite to that of the doped ring;
a conductor electrically connected to the drain region and extending over and across a periphery of the well region; and
a shielding element ring between the conductor and the semiconductor substrate, wherein the shielding element ring extends over and across the periphery of the well region, and wherein the shielding element ring laterally surrounds the well region, the source ring, and the drain region.

US Pat. No. 10,892,359

SEMICONDUCTOR DEVICE

SANKEN ELECTRIC CO., LTD....

1. A semiconductor device, comprising:a semiconductor base in which a first trench is formed in a mesh-like shape in a plan view and a second trench is formed in a mesh opening surrounded by the first trench;
a first semiconductor element which is formed in the semiconductor base and includes a first gate electrode provided within the first trench; and
a second semiconductor element which is formed in the semiconductor base and includes a second gate electrode provided within the second trench surrounded by the first gate electrode,
wherein a distance between an upper surface of the semiconductor base in which openings of the first and second trenches are formed and a bottom surface of the second trench is shorter than a distance between the upper surface of the semiconductor base and a bottom surface of the first trench.

US Pat. No. 10,892,358

INSULATING STRUCTURE OF HIGH ELECTRON MOBILITY TRANSISTOR AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. An insulating structure of a high electron mobility transistor (HEMT), comprising:a gallium nitride layer;
a buffer layer located below the gallium nitride layer;
an aluminum gallium nitride layer on the gallium nitride layer;
an insulating doped region located in the gallium nitride layer and the aluminum gallium nitride layer, wherein the range of the insulating doped region comprises part of the gallium nitride layer, part of the aluminum gallium nitride layer and part of the buffer layer; and
two sidewall insulating structures positioned at two sides of the insulating doped region respectively.

US Pat. No. 10,892,357

DOUBLE-CHANNEL HEMT DEVICE AND MANUFACTURING METHOD THEREOF

STMICROELECTRONICS S.r.l....

1. A device, comprising:a semiconductor body including a first layer of a first III-V compound semiconductor material, a second layer of a second III-V compound semiconductor material over the first layer, and a third layer of a third III-V compound semiconductor material over the second layer;
a gate structure, which contacts the first layer in a first direction, contacts the second layer in a second direction that is different from the first direction, and is separated from a first portion of the third layer in the second direction, a distance between a gate electrode of the gate structure and the first portion of the third layer being substantially equal to or larger than 5 ?m; and
a source structure that contacts the first layer in the first direction, contacts the second layer in the second direction, and contacts a second portion of the third layer in the second direction, wherein the second portion of the third layer contacts the gate structure in the second direction.

US Pat. No. 10,892,356

GROUP III-NITRIDE HIGH-ELECTRON MOBILITY TRANSISTORS WITH BURIED P-TYPE LAYERS AND PROCESS FOR MAKING THE SAME

CREE, INC., Durham, NC (...

1. An apparatus, comprising:a substrate;
a group III-Nitride buffer layer on the substrate;
a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride buffer layer;
a source electrically coupled to the group III-Nitride barrier layer;
a gate electrically coupled to the group III-Nitride barrier layer;
a drain electrically coupled to the group III-Nitride barrier layer;
a p-region being at least one of the following: in the substrate or on the substrate below said group III-Nitride barrier layer; and
a contact pad electrically coupled to said p-region and the contact pad being implemented electrically separate from the source.

US Pat. No. 10,892,355

LATERAL FIN STATIC INDUCTION TRANSISTOR

HRL Laboratories, LLC, M...

1. A lateral transistor device with a fin-like channel, the device comprising:a gated channel and a drift region, the gated channel located in the fin-like channel near the drift region, the drift region located in the fin-like channel, wherein the current transport through the drift region is space charge limited, the drift region determining the breakdown voltage of the transistor;
a source; a drain, and a substrate;
the source and the drain being electrically connected by the fin-like channel;
the source, the drain, and fin-like channel being on the substrate;
the source, drain, and fin-like channel being of a first conductivity type.

US Pat. No. 10,892,354

FIELD PLATES ON TWO OPPOSED SURFACES OF DOUBLE-BASE BIDIRECTIONAL BIPOLAR TRANSISTOR: DEVICES, METHODS, AND SYSTEMS

Ideal Power Inc., Austin...

1. A power semiconductor device, comprising:first and second first-conductivity-type emitter/collector regions, located respectively on first and second surfaces of a second-conductivity-type semiconductor die;
first and second second-conductivity-type base contact regions, located respectively on the first and second surface of the semiconductor die;
first and second entrenched field plate structures, located respectively on the first and second surface of the semiconductor die; wherein the entrenched field plate structures are conductive, and are insulated from the bulk of the semiconductor die, and are vertically extended, and laterally adjoin the emitter/collector regions, and also laterally adjoin the base contact regions;
wherein, on each of the surfaces, an emitter/collector region and a base contact region are separated by an entrenched field plate structure, the entrenched field plate structure adjoining both the emitter/collector region and also the base contact region;
wherein the first and second emitter/collector regions, and also the first and second base contact regions, are each connected to a respectively corresponding external connection; and
first and second field-limiting ring structures, located respectively on the first and second surfaces of the die; wherein the first field-limiting ring structure laterally surrounds the first emitter/collector region, the first entrenched field plate structure, and the first base contact region; and wherein the second field-limiting ring structure laterally surrounds the second emitter/collector region, the second entrenched field plate structure, and the second base contact region;
whereby the breakdown voltage is improved under either polarity of applied voltage.

US Pat. No. 10,892,353

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a first trench and a second trench formed in a semiconductor substrate, the first trench and the second trench extending in a first direction in a plan view and facing each other in a second direction perpendicular to the first direction in the plan view;
a first base region of a first conductivity type formed in the semiconductor substrate and located between the first trench and the second trench;
a first emitter region of a second conductivity type opposed to the first conductivity type being formed in the first base region;
a first contact hole formed on the first base region; and
an emitter potential electrode formed in the first contact hole and in contact with the first emitter region and the first base region,
wherein a first gate electrode electrically connected to a gate potential is formed in the first trench,
wherein an insulating film is formed in the second trench,
wherein the first contact hole is formed at a position overlapping the second trench in the plan view, and
wherein a bottom portion of the first contact hole is located on a first insulating layer in the second trench and is located on the first base region.

US Pat. No. 10,892,352

POWER SEMICONDUCTOR DEVICE

MITSUBISHI ELECTRIC CORPO...

1. A manufacturing method for a semiconductor device, the method comprising:providing a first-conductive-type silicon substrate having a first principal surface and a second principal surface opposite to the first principal surface;
forming a second-conductive-type base region disposed on the first principal surface of the silicon substrate;
selectively forming a first-conductive-type emitter region disposed in the base region from the first principal surface side, the emitter region being shallower than the base region;
forming a first groove part, a plurality of second groove parts, and a plurality of third groove parts in stripes,whereinthe first groove part is formed from the first principal surface side to the second principal surface side through the emitter region and the base region,
the plurality of second groove parts are formed at both sides of the first groove part from the first principal surface side to the second principal surface side through the base region, and
the plurality of third groove parts are formed at each side away from the emitter region and of the plurality of second groove parts from the first principal surface side to the second principal surface side through the base region, and are formed directly adjacent to each other;
forming gate insulating films covering inner walls of the first groove part, the second groove parts, and the third groove parts;
forming trench gates by filling the first groove part, the second groove parts, and the third groove parts with polysilicon over the gate insulating films;
forming gate electrodes electrically connected to the trench gates embedded in the first groove part and the trench gates embedded in the third groove parts; and
forming emitter electrodes electrically connected to the trench gates embedded in the second groove parts.

US Pat. No. 10,892,351

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor device comprising:a first semiconductor region of a first conductivity type having a lower surface comprising a first portion and a second portion;
a second semiconductor region of a second conductivity type, the second semiconductor region below the first portion of the first semiconductor region;
a third semiconductor region of the second conductivity type below the second portion of the first semiconductor region, the third semiconductor region having a second conductivity type carrier concentration that is lower than that of the second semiconductor region;
a first electrode below, and directly adjacent, the second semiconductor region and the third semiconductor region;
a fourth semiconductor region of the second conductivity type above the first portion of the first semiconductor region;
a fifth semiconductor region of the first conductivity type on a portion of the fourth semiconductor region;
a gate insulating layer;
a gate electrode extending alongside the fourth semiconductor region with the gate insulating layer therebetween;
a sixth semiconductor region of the second conductivity type above the first portion and the second portion of the first semiconductor region;
a first insulating layer;
a second electrode extending alongside the sixth semiconductor region with the first insulating layer interposed therebetween; and
a third electrode above the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region and electrically connected to the fourth semiconductor region, the fifth semiconductor region, the sixth semiconductor region, and the second electrode.

US Pat. No. 10,892,350

SEMICONDUCTOR DEVICE

MURATA MANUFACTURING CO.,...

1. A semiconductor device comprising:a semiconductor element including a bipolar transistor disposed on a compound semiconductor substrate, a collector electrode, a base electrode, and at least one emitter electrode, the bipolar transistor including a collector layer, a base layer, and at least one emitter layer, the collector electrode being in contact with the collector layer, the base electrode being in contact with the base layer, the at least one emitter electrode being in contact with the at least one emitter layer;
a protective layer disposed on one surface of the semiconductor element;
an emitter redistribution layer electrically connected to the at least one emitter electrode via a contact hole in the protective layer; and
a stress-relieving layer disposed between the emitter redistribution layer and the at least one emitter layer in a direction perpendicular to a surface of the compound semiconductor substrate.

US Pat. No. 10,892,349

FINFETS WITH DEPOSITED FIN BODIES

Micron Technology, Inc., ...

1. A method of fabricating a device having a fin field effect transistor, the method comprising:forming a fin field effect transistor including;
forming a structure extending from a base on a substrate, including forming the structure having a first dielectric with a dielectric surface extending from the base, the structure having a first conductive region within the first dielectric with the first dielectric having a portion of the first dielectric on top of the first conductive region;
depositing material on the dielectric surface and on the portion of the first dielectric on top of the first conductive region, and maintaining at least a portion of the deposited material to form a fin body of the fin field effect transistor;
forming a second dielectric contacting the fin body on a surface of e fin body opposite the dielectric surface of the first dielectric;
forming a second conductive region on the second dielectric, the second conductive region separated from the fin body by the second dielectric; and
forming a doped region to the fin body.

US Pat. No. 10,892,347

VERTICAL TUNNELING FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A vertical field effect transistor (VFET) comprising:a first fin structure protruding from a substrate, the first fin structure acting as a first channel of the VFET, the substrate including a source/drain region;
a second fin structure protruding from the substrate, the second fin structure acting as a second channel of the VFET;
a first source/drain structure on a top surface of the first fin structure;
a second source/drain structure on a top surface of the second fin structure;
a cap including a first pillar portion and a second pillar portion, the first pillar portion covering a side surface of the first source/drain structure and partially covering a top portion of a side surface of the first fin structure, the second pillar portion covering a top portion of a side surface of the second source/drain structure and partially covering a top portion of a side surface of the second fin structure;
a gate insulator extending along a remaining portion of the side surface of the first fin structure under the first pillar portion of the cap, extending along a remaining portion of the side surface of the second fin structure under the second pillar portion of the cap, and extending along bottom surfaces of the first and second pillar portions of the cap; and
a work function metal gate on the gate insulator,
wherein the cap further includes a roof portion covering an upper surface of the work function metal gate and connecting the first pillar portion and the second pillar portion.

US Pat. No. 10,892,346

BIPOLAR JUNCTION TRANSISTOR (BJT) FOR LIQUID FLOW BIOSENSING APPLICATIONS WITHOUT A REFERENCE ELECTRODE AND LARGE SENSING AREA

INTERNATIONAL BUSINESS MA...

1. A bipolar junction transistor containing sensor comprising:a vertically oriented stack of a collector atop a base region;
a first extrinsic base region in contact with a first sidewall of the base region, wherein the first extrinsic base region is electrically contacted to provide a bias current of the bipolar junction transistor during sensor operation;
a second extrinsic base region in contact with a second sidewall of the base region, the second extrinsic base region including a sensing element; and
a sample trench having a trench sidewall provided by the sensing element.

US Pat. No. 10,892,345

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a bottom electrode disposed on a substrate;
a top electrode disposed on the bottom electrode; and
a conductive seed layer; and
a dielectric layer including:
a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure having a vertical lattice constant and a horizontal lattice constant; and
an oxidation seed layer including an oxidation seed material,
wherein the hafnium oxide layer is disposed between the conductive seed layer and the oxidation seed layer,
wherein the oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of the horizontal lattice constant and the vertical lattice constant of the hafnium oxide, and
wherein the conductive seed layer comprises a conductive seed material including a lattice constant having a lattice mismatch of 2% or less with one of the horizontal lattice constant and the vertical lattice constant of the hafnium oxide.

US Pat. No. 10,892,344

ATOMIC LAYER DEPOSITION OF SELECTED MOLECULAR CLUSTERS

STMICROELECTRONICS, INC.,...

1. A method comprising:forming a source region;
forming a drain region;
forming a channel region extending between the source region and the drain region; and
forming a gate structure on the channel region, the gate structure including a gate electrode and a first molecular cluster thin film having ionic clusters including at least two bonded atoms that are different, the first molecular cluster thin film being between the gate electrode and the channel region.

US Pat. No. 10,892,343

DISPLAY DEVICE INCLUDING CAPPING LAYER COVERED SOURCE AND DRAIN ELECTRODES

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a thin-film transistor on a substrate, the thin-film transistor comprising on the substrate:
an active layer;
a gate electrode overlapping the active layer;
a source electrode and a drain electrode electrically connected to the active layer, the source electrode and the drain electrode including a first metal material; and
a first capping layer which covers the gate electrode, the first capping layer including a second metal material having a Young's modulus greater than that of the first metal material.

US Pat. No. 10,892,342

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

16. A method of manufacturing semiconductor device, comprising:stacking sacrificial layers and semiconductor layers on a substrate alternately;
patterning the sacrificial layers and the semiconductor layers to form a first active pattern and a second active pattern;
forming a first sacrificial gate pattern and a second sacrificial gate pattern on the first and second active patterns, respectively;
removing the first and second sacrificial gate patterns to form a first space and a second space, respectively;
sequentially forming, in the first space, a first metal nitride layer, and a second metal nitride layer containing silicon; and
forming a third metal nitride layer containing silicon in the second space,
wherein a silicon concentration of the second metal nitride layer is greater than that of the third metal nitride layer.

US Pat. No. 10,892,341

FLASH MEMORY WITH ASSISTANT GATE AND METHOD OF FABRICATING THE SAME

Powerchip Semiconductor M...

1. A flash memory, comprising:a substrate;
two floating gates disposed on said substrate;
an insulating layer conformally formed on said two floating gates and said substrate;
an assistant gate disposed on said insulating layer between said two floating gates, wherein a portion of said assistant gate wraps around said two floating gates;
two select gates disposed respectively on said insulating layer at outsides of said two floating gates and partly overlap said floating gate, wherein said floating gate has a point portion protruding upwardly at corner overlapping said select gate; and
in the erase operation, said assistant gate is applied with a negative voltage and said select gate is applied with a positive voltage, and said point portion of said floating gate enhances electrons tunneling through said insulating layer between said floating gate and said select gate.

US Pat. No. 10,892,340

MEMORY CELL STRUCTURES

Micron Technology, Inc., ...

1. A memory cell, comprising:an interface dielectric on a semiconductor;
a first storage dielectric on the interface dielectric;
a tunnel dielectric on the first storage dielectric such that the interface dielectric is between the semiconductor and the tunnel dielectric and in contact with the first storage dielectric;
a charge trap on the tunnel dielectric, such that the tunnel dielectric is beneath the charge trap and between and in direct contact with the first storage dielectric and the charge trap;
a second storage dielectric on the charge trap;
a blocking dielectric on the second storage dielectric; and
a control gate on the blocking dielectric.

US Pat. No. 10,892,339

GATE FIRST TECHNIQUE IN VERTICAL TRANSPORT FET USING DOPED SILICON GATES WITH SILICIDE

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming a gate stack on a fin, the gate stack being formed to have a vertical gate length in a vertical direction; and
forming a gate contact adjacent to the gate stack and corresponding to the vertical gate length of the gate stack in the vertical direction.

US Pat. No. 10,892,338

SCALED GATE CONTACT AND SOURCE/DRAIN CAP

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a gate structure comprising an active region;
source and drain contacts adjacent to the gate structure;
a capping material over the source and drain contacts;
a gate contact formed directly above the active region of the gate structure and over the capping material;
a U-shape dielectric material around the gate contact, above the source and drain contacts, the U-shape dielectric material being formed from the capping material and a liner material; and
a contact in electrical contact to at least one of the source and drain contacts,
wherein the source and drain contacts include a lower contact and an upper contact and the capping material is over the lower contact, wherein:
the upper contact is above and in direct contact with the lower contact, and below the gate contact that extends over the source and drain regions, and
the U-shape dielectric material formed from the capping material and the liner material comprises a source/drain cap underneath a portion of the gate contact, wherein:
the liner material of the U-shape dielectric material extends on sidewalls of the gate contact above the upper contact and above the gate structure;
the source/drain cap comprises a lower surface that is above the gate structure and over the lower contact; and
the source/drain cap extends to within a portion of the upper contact; and
the contact is to the upper contact and is remote from the gate contact that extends above the source and drain regions of the gate structure.

US Pat. No. 10,892,337

BACKSIDE SOURCE/DRAIN REPLACEMENT FOR SEMICONDUCTOR DEVICES WITH METALLIZATION ON BOTH SIDES

INTEL Corporation, Santa...

1. An integrated circuit (IC) comprising:a substrate;
a transistor above the substrate and including:
a gate;
a semiconductor region above the gate;
a source region and a drain region adjacent to the semiconductor region;
first and second contacts above the source and drain regions, respectively; and
a seed layer below the source and drain regions, wherein the seed layer includes semiconductor material and has doping levels of at least 1E19 atoms per cubic centimeter (cm) less than doping levels of the source and drain regions;
at least one metallization layer below the transistor and between the transistor and the substrate; and
at least one metallization layer above the transistor.

US Pat. No. 10,892,336

WRAP-AROUND-CONTACT STRUCTURE FOR TOP SOURCE/DRAIN IN VERTICAL FETS

International Business Ma...

1. A method for forming a wrap-around-contact, the method comprising:forming top spacers adjacent top portions of a plurality of fins;
recessing the top spacers;
forming top source/drain regions over the top portions of the plurality of fins;
forming trenches adjacent the top source/drain regions; and
depositing a metal liner within the trenches and over the top source/drain regions such that the wrap-around-contact is defined to cover an upper area of the top source/drain regions.

US Pat. No. 10,892,335

DEVICE ISOLATION BY FIXED CHARGE

Intel Corporation, Santa...

1. A transistor arrangement, comprising:a channel material over a substrate;
a gate electrode of a first transistor over a first portion of the channel material;
a gate electrode of a second transistor over a second portion of the channel material; and
an isolation structure over a third portion of the channel material, the third portion being between the first portion and the second portion of the channel material, the isolation structure comprising a fixed charge dielectric material,
wherein:
the fixed charge dielectric material includes a dielectric material having fixed charges,
the fixed charges are positive fixed charges when the channel material is a P-type material, and
the fixed charges are negative fixed charges when the channel material is an N-type material.

US Pat. No. 10,892,334

N-TYPE SIC SINGLE CRYSTAL SUBSTRATE, METHOD FOR PRODUCING SAME AND SIC EPITAXIAL WAFER

SHOWA DENKO K.K., Tokyo ...

1. An n-type SiC single crystal substrate which is doped with both a donor and an acceptor, whereina difference between a donor concentration and an acceptor concentration in an outer peripheral portion of the substrate is smaller than a difference between a donor concentration and an acceptor concentration in a central portion, and
the difference between the donor concentration and the acceptor concentration in said outer peripheral portion is smaller than 3.0×1019/cm3.

US Pat. No. 10,892,333

METHOD OF MAKING A GALLIUM NITRIDE DEVICE

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a stressed layer;
a conductive metal layer positioned on the stressed layer;
contacts separately positioned on the conductive metal layer, the conductive metal layer being on at least a portion of sides of the contacts;
a substrate positioned on the contacts such that an insulating layer is arranged on portions of the substrate proximate to the contacts; and
an oxide region arranged adjacent to the contacts so as to provide a separation between the contacts.

US Pat. No. 10,892,332

GATE INSULATING LAYER HAVING A PLURALITY OF SILICON OXIDE LAYER WITH VARYING THICKNESS

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a silicon carbide layer;
a gate electrode; and
a gate insulating layer provided between the silicon carbide layer and the gate electrode, the gate insulating layer including a first silicon oxide layer and a second silicon oxide layer, the second silicon oxide layer being provided between the first silicon oxide layer and the gate electrode, the first silicon oxide layer having a first nitrogen concentration and a first thickness, the second silicon oxide layer having a second nitrogen concentration lower than the first nitrogen concentration and a second thickness,
wherein the second thickness between an end portion of the gate electrode and the silicon carbide layer is greater than the second thickness between a central portion of the gate electrode and the silicon carbide layer.

US Pat. No. 10,892,331

CHANNEL ORIENTATION OF CMOS GATE-ALL-AROUND FIELD-EFFECT TRANSISTOR DEVICES FOR ENHANCED CARRIER MOBILITY

International Business Ma...

1. A semiconductor integrated circuit device, comprising:a first-type nanosheet field-effect transistor device and a second-type nanosheet field-effect transistor device disposed on a semiconductor substrate;
wherein the first-type nanosheet field-effect transistor device comprises a first nanosheet stack structure comprising a stack of nanosheet channel layers, wherein each nanosheet channel layer of the first nanosheet stack structure comprises a first channel width;
wherein the second-type nanosheet field-effect transistor device comprises a second nanosheet stack structure comprising at least a first stack of nanosheet channel layers and a second stack of nanosheet channel layers, wherein the first and second stacks of nanosheet channel layers are disposed adjacent to and spaced apart from each other, and wherein each nanosheet channel layer of the first and second stacks of nanosheet channel layers comprises a second channel width, which is less than the first channel width;
wherein horizontal surfaces of the nanosheet channel layers of the first and second nanosheet stack structures are aligned with a first crystal plane of the nanosheet channel layers, which provides a greater carrier mobility of a first type of carrier over a second type of carrier; and
wherein vertical surfaces of the nanosheet channel layers of the first and second nanosheet stack structures are aligned with a second crystal plane of the nanosheet channel layers, which provides a greater carrier mobility of the second type of carrier over the first type of carrier.

US Pat. No. 10,892,330

FET BASED SYNAPSE NETWORK

INTERNATIONAL BUSINESS MA...

1. A synapse network device, comprising:an array of field effect transistor (FET) devices having controllable channel resistance;
pre-neurons coupled to the array to provide input pulses to the array on first terminals of the FET devices; and
post-neurons coupled to the array to receive outputs from the array on second terminals of the FET devices and provide feedback to the array on third terminals of the FET devices, wherein a state of the FET devices is indicated based upon the input pulses and the feedback of the FET devices.

US Pat. No. 10,892,329

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND POWER CONVERSION DEVICE

Mitsubishi Electric Corpo...

1. A method for manufacturing a semiconductor device, the semiconductor device including:a semiconductor substrate of a first conductivity type;
an epitaxial layer of the first conductivity type, the epitaxial layer being formed on a first principal surface of the semiconductor substrate;
a first semiconductor region of the first conductivity type, the first semiconductor region being formed from an outermost surface to an inner portion of the epitaxial layer;
a second semiconductor region of a second conductivity type, the second semiconductor region being formed in contact with a side surface of the first semiconductor region;
a source region and a drain region of the second conductivity type, the source region and the drain region being selectively formed in an upper layer portion of the first semiconductor region;
a gate electrode formed on the first semiconductor region between the source region and the drain region through a gate insulating film; and
a third semiconductor region of the second conductivity type, the third semiconductor region being formed from a bottom surface of the first semiconductor region to an inner portion of the semiconductor substrate, the method comprising the steps of:
(a) polishing a second principal surface opposite to the first principal surface of the semiconductor substrate above which at least the source region, the drain region, and the gate electrode are formed to thin the semiconductor substrate; and
(b) ion-implanting impurities of the second conductivity type from the second principal surface of the polished semiconductor substrate to form the third semiconductor region,
wherein step (b) includes (b-1) ion-implanting the impurities of the second conductivity type so that the third semiconductor region is higher in impurity concentration than the second semiconductor region.

US Pat. No. 10,892,328

SOURCE/DRAIN EXTENSION REGIONS AND AIR SPACERS FOR NANOSHEET FIELD-EFFECT TRANSISTOR STRUCTURES

International Business Ma...

1. A method of forming a semiconductor structure, comprising:forming a nanosheet stack over a substrate, the nanosheet stack comprising alternating sacrificial layers and channel layers, the channel layers providing nanosheet channels for one or more nanosheet field-effect transistors;
forming one or more vertical fins in the nanosheet stack and at least a portion of the substrate;
forming indents in sidewalls of the sacrificial layers at vertical sidewalls of the one or more vertical fins;
forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the vertical sidewalls of the one or more vertical fins, the nanosheet extension regions increasing in thickness from a first thickness proximate the indented sidewalls of the sacrificial layers to a second thickness proximate the vertical sidewalls of the one or more vertical fins; and
forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers;
wherein the nanosheet extension regions have a curved thickness profile that gradually increases from the first thickness proximate the indented sidewalls of the sacrificial layers to the second thickness proximate the vertical sidewalls of the one or more vertical fins.

US Pat. No. 10,892,327

SEMI-METAL RECTIFYING JUNCTION

University College Cork, ...

1. A rectifying Schottky barrier junction formed in a conduction path provided in a material that behaves as a semimetal in the bulk, wherein:the material has a length along which the conduction path extends, and a thickness or diameter;
the thickness or diameter is smaller than a threshold size, the threshold size being the size at or below which the material exhibits quantum confinement such that the length of material forms a bandgap and behaves as a semiconductor, wherein the threshold size is the same as or less than a Fermi wavelength of charge carriers in the material;
bonds at a surface of a first region of the length of material are arranged to decrease the bandgap of the first region such that the first region reverts to semimetallic behaviour; and
bonds at a surface of a second region of the length of material are arranged to preserve the bandgap of the second region such that the second region maintains semiconducting behaviour,
wherein the second region is contiguous to the first region, such that a rectifying junction is formed at a boundary between the first region and the second region.

US Pat. No. 10,892,326

REMOVAL OF A BOTTOM-MOST NANOWIRE FROM A NANOWIRE DEVICE STACK

Intel Corporation, Santa...

1. A method comprising:forming a substrate;
forming a stack of nanowires, the stack of nanowires comprising an attached nanowire that is attached to the substrate, and one or more nanowires that are not attached to the substrate;
forming a gate stack, wherein the gate stack fully encircles at least a corresponding section of each nanowire of the one or more nanowires, and partially encircles the attached nanowire; and
removing the attached nanowire that is attached to the substrate, without removing any nanowire of the one or more nanowires.

US Pat. No. 10,892,325

VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED GATE TO SOURCE/DRAIN CAPACITANCE

INTERNATIONAL BUSINESS MA...

1. A method of forming a fin field effect transistor device, comprising:forming a vertical fin on a bottom source/drain layer;
reducing the width of the vertical fin to form a thinned vertical fin; and
depositing a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness with at least a portion of a top surface that tapers towards the bottom source/drain layer in a direction towards the thinned vertical fin.

US Pat. No. 10,892,324

VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED GATE TO SOURCE/DRAIN CAPACITANCE

INTERNATIONAL BUSINESS MA...

1. A fin field effect transistor device, comprising:a bottom source/drain layer on a substrate;
one or more thinned vertical fins on the source/drain layer;
a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness with a top surface that tapers towards the bottom source/drain layer in a direction towards each of the one or more thinned vertical fins; and
a gate dielectric layer on the bottom spacer layer and sidewalls of each of the one or more thinned vertical fins.

US Pat. No. 10,892,323

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Winbond Electronics Corp....

1. A buried word line structure, comprising:a substrate;
an isolation structure located in the substrate to define active regions separated from each other, wherein the active regions extend in a first direction; and
a buried word line located in the substrate and extending through the isolation structure and the active regions in a second direction, wherein the first direction intersects the second direction, the buried word line and the substrate are isolated from each other, and
the same word line comprises a first portion and a second portion, wherein the first portion is located in the active regions, the second portion is located in the isolation structure between two adjacent active regions in the first direction, and a width of the first portion is greater than a width of the second portion.

US Pat. No. 10,892,322

CIRCUITS EMPLOYING A DOUBLE DIFFUSION BREAK (DDB) AND SINGLE DIFFUSION BREAK (SDB) IN DIFFERENT TYPE DIFFUSION REGION(S), AND RELATED FABRICATION METHODS

QUALCOMM Incorporated, S...

1. A circuit, comprising:a substrate comprising a top surface;
a first diffusion region comprising either an N-type diffusion region or a P-type diffusion region disposed in the substrate,
the first diffusion region comprising at least one first semiconductor channel each having a first longitudinal axis in a first direction;
a second diffusion region comprising either a P-type diffusion region or an N-type diffusion region opposite of a diffusion type of the first diffusion region,
the second diffusion region disposed in the substrate and comprising at least one second semiconductor channel each having a second longitudinal axis parallel to the first longitudinal axis;
a first dummy gate extending along a third longitudinal axis orthogonal to the first longitudinal axis, the first dummy gate comprising a first dielectric material disposed above the first diffusion region and the second diffusion region, the first dielectric material extending from the top surface of the substrate to a first depth into the substrate;
a second dummy gate extending along a fourth longitudinal axis parallel to the third longitudinal axis, the second dummy gate comprising a second dielectric material disposed above the first diffusion region and the second diffusion region, the second dielectric material extending from the top surface of the substrate to a second depth into the substrate, the second dummy gate adjacent to the first dummy gate by a gate pitch;
a double diffusion break (DDB) in the first diffusion region, the DDB comprising:
a trench isolation structure between the first dummy gate and the second dummy gate in the first direction;
a portion of the first dummy gate in the first diffusion region; and
a portion of the second dummy gate in the first diffusion region; and
a single diffusion break (SDB) in the second diffusion region, the SDB comprising:
a portion of the first dummy gate in the second diffusion region; and
a portion of the second dummy gate in the second diffusion region.

US Pat. No. 10,892,321

MOS TRANSISTORS IN PARALLEL

STMicroelectronics (Rouss...

1. An electronic chip comprising:a plurality of first transistors connected in parallel so that gates of the first transistors are interconnected, drain areas of the first transistors are interconnected, and source areas of the first transistors are interconnected;
a plurality of first isolating trenches, the first transistors being separated from one another by the first isolating trenches;
a plurality of second transistors; and
a plurality of second isolating trenches, the second transistors separated from one another by the second isolating trenches, wherein the first isolating trenches have a maximum width that is smaller than a maximum width of all the second isolating trenches.

US Pat. No. 10,892,320

SEMICONDUCTOR DEVICES HAVING STACKED TRENCH GATE ELECTRODES OVERLAPPING A WELL REGION

Vanguard International Se...

1. A semiconductor device, comprising:a substrate having a first conductivity type;
an epitaxial layer having the first conductivity type disposed on the substrate, and a trench is in the epitaxial layer;
a first well region disposed in the epitaxial layer under the trench, and the first well region has a second conductivity type that is different from the first conductivity type;
a first gate electrode disposed in the trench and having the second conductivity type, wherein a doping concentration of the first gate electrode is greater than a doping concentration of the first well region; and
a second gate electrode disposed in the trench on the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer.

US Pat. No. 10,892,319

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor layer having a front surface, a back surface on a side opposite thereto and an end surface;
an MIS transistor structure which is formed on a front surface portion of the semiconductor layer;
a first conductivity type portion and a second conductivity type portion which are formed adjacent to each other on a side of the back surface of the semiconductor layer; and
a first electrode which is formed on the back surface of the semiconductor layer, which forms a Schottky junction with the first conductivity type portion and which is in ohmic contact with the second conductivity type portion, wherein
the first electrode includes a peripheral edge in a position separated inward from the end surface of the semiconductor layer.

US Pat. No. 10,892,318

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:an insulating structure defining a first trench on a substrate;
a first conductive layer in the insulating structure, a first portion of an upper surface of the first conductive layer exposed by the first trench;
a capacitor structure including a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, the first electrode pattern extending along sidewalls and a bottom surface of the first trench and an upper surface of the insulating structure; and
a first wiring pattern on the capacitor structure,
wherein a first distance from the first trench to a distal end of the first electrode pattern is shorter than a second distance from the first trench to a distal end of the dielectric pattern.

US Pat. No. 10,892,317

POWER TRENCH CAPACITOR COMPATIBLE WITH DEEP TRENCH ISOLATION PROCESS

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:a buried implant layer over a substrate;
an epitaxial (EPI) layer over the buried implant layer;
an oxide layer over the EPI layer;
a nitride layer over the oxide layer;
a deep trench isolation (DTI) and a DTI-capacitor (DTI-CAP) in the nitride layer, the oxide layer, the EPI layer, the buried implant layer and the substrate, the DTI being wider and deeper than the DTI-CAP;
a dielectric layer on sidewalls of the DTI and on side and bottom surfaces of the DTI-CAP below an upper surface of the EPI layer;
a first polysilicon layer over the dielectric layer in the DTI and DTI-CAP; and
a second polysilicon layer filling the DTI and above the upper surface of the EPI layer in the DTI-CAP,
wherein the EPI layer is a bottom plate of the DTI-CAP and the first and second polysilicon layers are a top plate of the DTI-CAP.

US Pat. No. 10,892,316

HIGH DENSITY BALL GRID ARRAY (BGA) PACKAGE CAPACITOR DESIGN

Google LLC, Mountain Vie...

1. An integrated circuit package, comprising:a substrate having a first side and a second side opposite the first side;
an integrated circuit component coupled to the second side of the substrate;
a ball grid array formed on the first side of the substrate, the ball grid array comprising multiple contact balls arranged in a pattern, wherein each of a first subset of the contact balls is electrically coupled to a first voltage input of the integrated circuit component, and each of a second subset of the contact balls is electrically coupled to a second voltage input of the integrated circuit component; and
a capacitor mounted to the first side and having a first terminal coupled to a first contact ball in the first subset of the contact balls and a second terminal coupled to a second contact ball in the second subset of the contact balls,
wherein the first voltage input is a drain voltage input of a complementary, metal-oxide-semiconductor circuit, and the second voltage input is a sink voltage input of the complementary, metal-oxide-semiconductor circuit.

US Pat. No. 10,892,315

DISPLAY DEVICE

Japan Display Inc., Mina...

1. An electronic device comprising:a flexible substrate;
a first insulating film provided on the flexible substrate;
a switching element provided on the first insulating film;
a second insulating film provided on a semiconductor layer of the switching element;
a third insulating film provided on a gate electrode of the switching element;
a first organic film provided on the third insulating film;
a wiring electrically connected with the switching element; and
a pad electrode electrically connected with the wiring,
wherein
the wiring is in a first portion, a second portion, and a third portion,
the second portion is between the first portion and the third portion,
the pad electrode is in the third portion,
in the first portion and the third portion, the first insulating film, the second insulating film, and the first organic film are between the flexible substrate and the wiring,
in the second portion, the first organic film is between the flexible substrate and the wiring and in contact with a surface of the flexible substrate, and
a thickness of the first organic film located in the second portion is larger than a thickness of the first organic film located in the first portion and the third portion.

US Pat. No. 10,892,314

STRETCHABLE DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. A stretchable display device comprising:a lower substrate;
a plurality of island substrates spaced apart from each other and disposed on the lower substrate;
a plurality of pixels defined on the plurality of island substrates;
a plurality of base polymers disposed between adjacent island substrates of the plurality of island substrates; and
a plurality of conductive particles distributed in the base polymer and electrically connecting a plurality of pads disposed on the adjacent island substrates,
wherein the plurality of base polymers include a first area overlapping with the island substrate and a second area disposed between the plurality of island substrates, and
wherein a density of the conductive particles decreases downward from an upper portion of the base polymer.

US Pat. No. 10,892,313

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate comprising a pad area;
a plurality of first conductive pads disposed in a matrix form in the pad area in a first direction and in a second direction intersecting the first direction;
protrusions disposed on the plurality of first conductive pads; and
a plurality of second conductive pads disposed on the plurality of first conductive pads and the protrusions;
wherein the plurality of second conductive pads comprises:
contact portions in contact with the first conductive pads; and
raised portions extending from the contact portions, wherein the raised portions cover the protrusions, and have a height greater than a height of the contact portions; and
wherein the plurality of second conductive pads comprise an ultrasonic bondable material.

US Pat. No. 10,892,312

FLEXIBLE DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. A flexible display device comprising:a flexible display panel including a flexible substrate and back plates, the flexible substrate including a display area, a signal line area, a panel pad area and a bending area between the signal line area and the panel pad area;
a plurality of pixels disposed at the display area of the flexible substrate;
a plurality of signal lines disposed at the signal line area of the flexible substrate and extending to the panel pad area of the flexible substrate for transmitting driving signals to the plurality of pixels;
a plurality of panel pads disposed at the panel pad area of the flexible substrate for receiving the driving signals from outside,
wherein the back plates includes a first back plate disposed under the flexible substrate corresponding to the display area and the signal line area of the flexible substrate and a second back plate disposed under the flexible substrate corresponding to the panel pad area of the flexible substrate, and
wherein the second back plate is disposed under the first back plate to face the first back plate; and
a flexible film transmitting the driving signals inputted from the outside to the flexible display panel and including a film pad area in which a plurality of film pads corresponds to the plurality of panel pad,
wherein the plurality of panel pads of the flexible display panel and the plurality of film pads of the flexible film are arranged to correspond to each other in a fan shape and have different pitches and slopes from each other.

US Pat. No. 10,892,311

DISPLAY DEVICE AND DISPLAY TERMINAL

Wuhan China Star Optoelec...

1. A display assembly, comprising:a flexible substrate comprising, along a horizontally arranged direction, a first section, a connecting section and a second section in sequence;
a first display device disposed on the first section of the flexible substrate;
a second display device disposed on the second section of the flexible substrate, the second display device comprising a first display section, a foldable section and a second display section, which connect with one another in sequence; and
a metal wire disposed at the connecting section of the flexible substrate and electrically connected to the first display section and the first display device;
when in a folded state, an area of a rear surface of the flexible substrate corresponding to the first display device is over another area of the rear surface of the flexible substrate corresponding to the first display section, and a front surface of the first display section is over a front surface of the second display section; and
wherein the first display device comprises a first display layer, a first optical glue connection layer and a first transparent protection layer, and the first transparent protection layer is mounted on a front surface of the first display layer through the first optical glue connection layer.

US Pat. No. 10,892,310

DISPLAY DEVICE INCLUDING A PASSIVATION LAYER HAVING AN UNEVEN SURFACE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a substrate including a display area and a peripheral area disposed at an edge of the display area;
a transistor disposed on the display area of the substrate and comprising an interlayer insulating layer for electrical insulation between at least two electrodes of the transistor;
a passivation layer disposed on the transistor;
a first electrode disposed on the passivation layer;
a pixel definition layer disposed on the passivation layer having an opening overlapping the first electrode;
a light-emitting member disposed on the first electrode and inside the pixel definition layer;
a second electrode disposed on the light-emitting member and the pixel definition layer; and
a pad portion disposed on the peripheral area of the substrate,
wherein the pad portion includes:
a first pad electrode;
a second pad electrode disposed adjacent to the first pad electrode; and
an auxiliary electrode disposed between the first pad electrode and the second pad electrode,
wherein the interlayer insulating layer having an opening disposed between the first pad electrode and the second pad electrode in a plan view, and the auxiliary electrode is disposed in the opening in the plan view, and
wherein a plurality of first electrode particles are disposed on the auxiliary electrode and the plurality of first electrode particles include substantially the same material as the first electrode.

US Pat. No. 10,892,309

DISPLAY APPARATUS INCLUDING A PLURALITY OF BANKS AND A METHOD OF MANUFACTURING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus, comprising:a first substrate on which a plurality of organic light-emitting diodes are arranged; and
a second substrate bonded to the first substrate, wherein the second substrate comprises a plurality of light control units respectively corresponding to the plurality of organic light-emitting diodes and a plurality of banks arranged between the plurality of light control units,
wherein the plurality of banks comprise:
a first bank having a deflection arrangement structure in which a fluorine-containing polymer is concentrated on a surface of a side of the first bank; and
a second bank that does not have a deflection arrangement structure in which the fluorine-containing polymer is deflectively arranged.

US Pat. No. 10,892,308

DISPLAY PANEL AND METHOD OF FABRICATING THE SAME

Samsung Display Co., Ltd....

1. A display panel, comprising:a base layer including a first region and a second region that is bent from the first region along a predetermined bending axis;
a first thin-film transistor provided in the first region, the first thin-film transistor comprising a crystalline silicon semiconductor pattern, a first control electrode, and a first input electrode and a first output electrode that are coupled to the crystalline silicon semiconductor pattern and are spaced apart from each other with the first control electrode interposed therebetween;
a second thin-film transistor disposed in the first region, the second thin-film transistor comprising a second control electrode, an oxide semiconductor pattern disposed on the second control electrode, and a second input electrode and a second output electrode that are in contact with the oxide semiconductor pattern and are spaced apart from each other;
a first inorganic layer disposed to overlap the first thin-film transistor and the second thin-film transistor in a thickness direction, and to include a first groove that overlaps the second region;
a second inorganic layer disposed between first thin-film transistor and the second thin-film transistor and the base layer, to include a second groove that overlaps the first groove:
an organic layer disposed in the first region and the second region to cover inner surfaces of the first and second grooves; and
an organic light emitting diode disposed on the organic layer and in the first region and electrically connected to the first thin-film transistor,
wherein the second inorganic layer is disposed to expose a portion of a top surface of the base layer, and the organic layer is disposed to be in contact with the portion of the top surface of the base layer.

US Pat. No. 10,892,307

FINGERPRINT SENSOR, DISPLAY DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a pixel circuit;
a pixel electrode electrically connected to the pixel circuit;
a light-emitting layer overlapping the pixel electrode in a plan view;
a sensor circuit comprising a capacitor electrode;
a sensor electrode electrically connected to the sensor circuit, the sensor electrode overlapping the capacitor electrode in the plan view; and
a common electrode overlapping the pixel electrode in the plan view;
wherein:
the common electrode comprises an opening corresponding to at least a portion of the sensor electrode;
the sensor electrode and pixel electrode comprise a same material; and
the pixel electrode, the light-emitting layer, and the common electrode overlap to form an light-emitting element in the plan view.

US Pat. No. 10,892,306

DISPLAY PANEL AND DISPLAY DEVICE

Shanghai Tianma AM-OLED C...

18. A display device, comprising a display panel, wherein the display panel comprises:a pixel defining layer comprising a plurality of aperture regions and a non-aperture region;
a light-emitting unit comprising a first electrode, a light-emitting layer, and a second electrode that are stacked, wherein the light-emitting layer is arranged in the aperture region, the first electrode is located at a side of the light-emitting layer facing away from the pixel defining layer, the second electrode is located at a side of the light-emitting layer close to the pixel defining layer, and the first electrode covers a display region over its entire surface;
a first support post located between the pixel defining layer and the first electrode in a direction perpendicular to a plane of the display panel, wherein an orthographic projection of the first support post on the plane of the display panel is within the non-aperture region, and the first electrode completely covers the light-emitting layer and the first support post; and
a touch layer located at a side of the first electrode facing away from the pixel defining layer, and comprising a hollow portion, a first portion and a second portion connected to the first portion, wherein both the first portion and the hollow portion overlap the first support post in a direction perpendicular to the plane of the display panel, the second portion does not overlap the first support post in the direction perpendicular to the plane of the display panel, and an area of an overlapping portion of the first portion and the first support post is smaller than an area of the first support post in the direction perpendicular to the plane of the display panel.

US Pat. No. 10,892,305

TOUCH STRUCTURE, ORGANIC LIGHT EMITTING DIODE (OLED) DISPLAY TOUCH PANEL AND TOUCH DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...

6. A touch display device, comprising:a touch structure for OLED, the touch structure comprising an electrode layer, an insulation layer, and a bridge layer stacked in sequence, the electrode layer being of a metal mesh structure comprising a plurality of driving electrodes along a first direction and a plurality of sensing electrodes along a second direction, the driving electrodes and the sensing electrodes being disposed within gaps of an emission layer of the OLED, the first direction and the second direction forming a first angle, two adjacent driving electrodes along the first direction being connected, the bridge layer being configured with bridge wires, the insulation layer being configured with openings, the bridge wires connecting to two adjacent sensing electrodes along the second direction via the openings; wherein the driving electrodes and the sensing electrodes comprises a plurality of first metal lines extending in the third direction and a plurality of second metal lines extending in the fourth direction, the third direction and the fourth direction are at a second angle ?, the bridge lines comprises at least one third metal line extending along the third direction, and at least one fourth metal line extending along the fourth direction, the plurality of the first metal lines are spaced apart from each other by a first interval, and the plurality of the second metal lines are spaced apart from each other by a second interval.

US Pat. No. 10,892,304

DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. A display device comprising:a light-emitting element disposed on a substrate having an active area and a non-active area;
an encapsulation unit disposed on the light-emitting element, wherein the encapsulation unit comprises a plurality of inorganic encapsulation layers and at least one organic encapsulation layer;
a plurality of touch sensors disposed on the encapsulation unit; and
a plurality of routing lines connected to the plurality of touch sensors,
wherein each of the plurality of routing lines comprises a first routing line disposed on the encapsulation unit and a second routing line overlapping the first routing line with a touch insulation layer interposed therebetween, the second routing line is electrically connected to the first routing line through a plurality of routing contact holes in the non-active area, which are formed in the touch insulation layer covering the first routing line, and
wherein the first and second routing lines are extended along a side surface of the encapsulation unit.

US Pat. No. 10,892,303

ELECTRONIC DEVICE AND MANUFACTURING METHOD FOR SAME

GUANGDONG OPPO MOBILE TEL...

1. An electronic device, comprising:a housing;
a light-permeable display screen received in the housing and comprising a display area and a black matrix area surrounding the display area, the black matrix area comprising a first window region;
an emitter arranged at a side of the light-permeable display screen and opposite to the first window region of the black matrix area, the emitter being configured to emit an infrared light through the first window region; and
a receiver arranged at the side of the light-permeable display screen and configured to receive the infrared light through the light-permeable display screen,
wherein the electronic device further comprises a coating layer coated at the first window region and shielding the emitter, the coating layer is configured to allow the infrared light to pass through and to block a visible light, and the emitter is configured to emit the infrared light through the coating layer and the first window region,
wherein the coating layer comprises an infrared ink, the infrared ink has a light transmittance for the infrared light larger than 85% and a light transmittance for the visible light less than 6%, and the infrared ink allows the infrared light whose wave length ranges from 850 nm to 940 nm to pass through.

US Pat. No. 10,892,302

PHOTOELECTRIC CONVERSION ELEMENT, IMAGING ELEMENT, STACKED-TYPE IMAGING ELEMENT, AND SOLID-STATE IMAGING APPARATUS

SONY CORPORATION, Tokyo ...

1. An imaging element, comprising:a stacked structure of a first electrode, an organic photoelectric conversion layer, and a second electrode, wherein
the organic photoelectric conversion layer comprises a material that has a bulk heterostructure, and
the bulk heterostructure includes a hole transport material, an electron transport material, and an optical absorption organic semiconductor material;
a first organic material layer; and
a second organic material layer, wherein the first organic material layer and the second organic material layer between the first electrode and the organic photoelectric conversion layer from a side of the first electrode.

US Pat. No. 10,892,301

PHOTO-ELECTRIC CONVERSION ELEMENT, SOLID-STATE IMAGING ELEMENT, AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...

1. A photo-electric conversion element comprising:an organic photo-electric conversion layer sandwiched by a first electrode and a second electrode,
wherein the organic photo-electric conversion layer contains organic molecules of a quinacridone derivative and a subphthalocyanine derivative,
wherein at least the quinacridone derivative out of the organic molecules is in random orientation, and
wherein a crystal grain size of the quinacridone derivative is 2 to 5 nm.

US Pat. No. 10,892,300

STORAGE DEVICE

Toshiba Memory Corporatio...

15. A storage device comprising:a plurality of first wires;
a plurality of second wires intersecting the plurality of first wires; and
memory cells provided in regions where the first wires and the second wires intersect each other,
wherein one of the memory cells includes a resistance change element and a switching element, the switching element provided in any one of a position between the resistance change element and the one of the first wires and a position between the resistance change element and the one of the second wires, the switching element containing at least one element of silicon (Si) and germanium (Ge), tellurium (Te), and aluminum (Al), and
an atomic concentration of the at least one element in the switching element is higher than an atomic concentration of aluminum (Al) in the switching element.

US Pat. No. 10,892,299

MAGNETIC FIELD CONTROLLED TRANSISTOR

International Business Ma...

10. A method for operating a magneto-resistive material, the channel being arranged between the first and the second electrode;a third electrode;
a fourth electrode;
a control layer comprising an electrically conductive material, the control layer being arranged between the third and the fourth electrode; and
an insulating layer comprising an insulating material, the insulating layer being arranged between the channel comprising the magneto-resistive material and the control layer;
wherein the magneto-resistive material is a colossal magneto-resistive material;
the method comprising:
driving a control current between the third and the fourth electrode through the control layer, thereby applying a magnetic field on the channel and controlling the resistivity of the channel by the magnetic field being induced by the control current.

US Pat. No. 10,892,298

LIGHT EMITTING DIODE DISPLAY DEVICE WITH SEPARATION FILM AND PARTITION ALIGNING TO EACH OTHER

SAMSUNG ELECTRONICS CO., ...

1. A light emitting diode display device comprising:a first light emitting diode pixel including a first light emitting diode layer and a first color conversion material on the first light emitting diode layer;
a second light emitting diode pixel including a second light emitting diode layer and a second color conversion material on the second light emitting diode layer;
a separation film disposed between the first light emitting diode layer and the second light emitting diode layer; and
a partition disposed between the first color conversion material and the second color conversion material and including a partition material,
wherein the first and second light emitting diode pixels are divided by the separation film and the partition,
the partition is disposed on the separation film in alignment with the separation film such that the partition includes linear portions that extend in a first direction and the separation film includes linear portions that also extend in the first direction and vertically overlap the linear portions of the partition, and
the partition material includes an insulating material different from silicon,
wherein the partition includes:
a first liner which contacts the first color conversion material;
a second liner which is spaced from the first liner in a horizontal direction and contacts the second color conversion material;
a third liner which connects an upper part of the first liner and an upper part of the second liner; and
a gap fill layer disposed under the third liner and disposed between the first liner and the second liner.

US Pat. No. 10,892,297

LIGHT EMITTING DIODE (LED) STACK FOR A DISPLAY

Seoul Viosys Co., Ltd., ...

1. A light emitting diode (LED) stack for a display, comprising:a first LED sub-unit having a first surface and a second surface;
a second LED sub-unit disposed on the first surface of the first LED sub-unit;
a third LED sub-unit disposed on the second LED sub-unit;
a reflective electrode disposed on the second surface of the first LED sub-unit and forming ohmic contact with the first LED sub-unit; and
an ohmic electrode interposed between the first LED sub-unit and the second LED sub-unit and forming ohmic contact with the first LED sub-unit,
wherein:
the second LED sub-unit and the third LED sub-unit are configured to transmit light generated from the first LED sub-unit; and
the third LED sub-unit is configured to transmit light generated from the second LED sub-unit.

US Pat. No. 10,892,296

LIGHT EMITTING DEVICE HAVING COMMONLY CONNECTED LED SUB-UNITS

Seoul Viosys Co., Ltd., ...

1. A light emitting device for a display, comprising:a first LED sub-unit;
a second LED sub-unit disposed adjacent to the first LED sub-unit;
a third LED sub-unit disposed adjacent to the second LED sub-unit; and
electrode pads disposed on the first LED sub-unit and electrically connected to the first, second, and third LED sub-units, the electrode pads comprising a common electrode pad electrically connected to each of the first, second, and third LED sub-units, and first, second, and third electrode pads connected to a respective one of the first, second, and third LED sub-units,
wherein:
the common electrode pad, the second electrode pad, and the third electrode pad are electrically connected to the second LED sub-unit and the third LED sub-unit through holes that pass through the first LED sub-unit;
the first LED sub-unit, the second LED sub-unit, and the third LED sub-unit are configured to be independently driven;
light generated in the first LED sub-unit is configured to be emitted to the outside of the light emitting device through the second LED sub-unit and the third LED sub-unit; and
light generated in the second LED sub-unit is configured to be emitted to the outside of the light emitting device through the third LED sub-unit.

US Pat. No. 10,892,295

GERMANIUM-MODIFIED, BACK-SIDE ILLUMINATED OPTICAL SENSOR

Microsoft Technology Lice...

1. An imaging sensor array comprising:an electrically biased photoelectron collector formed on a silicon transport layer;
an epitaxial germanium layer grown on the silicon transport layer, on a side opposite the photoelectron collector;
a silicon passivation layer grown on the epitaxial germanium layer, on a side opposite the silicon transport layer; and
a light-shaping structure formed on the photoelectron collector, on the side opposite the epitaxial germanium layer, the light-shaping structure being configured to cause light incident on the epitaxial germanium layer to reflect repeatedly through the epitaxial germanium layer, thereby increasing absorption.

US Pat. No. 10,892,294

RADIATION DETECTOR ELEMENT AND IMAGER COMPRISING AN ASSEMBLY OF RADIATION DETECTOR ELEMENTS

THALES, Courbevoie (FR)

1. A radiation detector element comprising:a stack of layers superimposed in a stacking direction, the stack having a first face and a second face and comprising a radiation-absorbing layer consisting of a first semiconductor material having a first band gap value and at least one barrier layer consisting of a second semiconductor material having a second band gap value, the second band gap value being strictly greater than the first band gap value; and
a reading circuit delimited in the stacking direction by the first face;
the absorbing layer comprising a first portion having a doping of a first type chosen from among n-type doping and p-type doping, and a second portion having a doping of a second type chosen from among n-type doping and p-type doping, the second type of doping being different from the first type of doping, the first portion and the second portion forming a first p-n junction;
further delimiting a primary hole traversing each of the layers of the stack, the primary hole receiving at least part of a primary electrode electrically connecting the second portion to the reading circuit and traversing the first face, the first p-n junction surrounding the primary electrode in a plane orthogonal to the stacking direction, and
the second face carrying at least one band delimited in the stacking direction by the barrier layer, the band being made from the second semiconductor material and having a doping of the first type and a free carrier density greater than or equal to 1.1017 cm?3.

US Pat. No. 10,892,293

SOLID-STATE IMAGING ELEMENT, IMAGING DEVICE, AND ELECTRONIC DEVICE

SONY CORPORATION, Tokyo ...

1. A solid-state imaging element, comprising:a pixel array comprising a plurality of pixels, wherein each pixel of the plurality of pixels comprises:
a photoelectric conversion region configured to generate a charge by photoelectric conversion based on an amount of incident light;
a charge accumulation region configured to accumulate the charge generated by the photoelectric conversion region,
wherein, in a specific direction, a pitch of the photoelectric conversion region is shifted from a pitch of the charge accumulation region by a substantially half pitch;
a plurality of electrodes configured to form a transfer gradient to transfer the charge accumulated in the charge accumulation region; and
a charge voltage conversion region configured to convert the transferred accumulated charge into a voltage.

US Pat. No. 10,892,292

BACK-SIDE ILLUMINATED IMAGE SENSOR

STMicroelectronics (Croll...

1. A back-side illuminated image sensor, comprising memory regions formed in a semiconductor wafer, each memory region being located between two opaque walls which extend into the semiconductor wafer from a rear surface of the semiconductor wafer and are in contact with an opaque screen arranged at the rear surface of the semiconductor wafer to cover the memory region, wherein each opaque wall is separated from the memory region by a polysilicon layer.

US Pat. No. 10,892,291

BONDING PAD ARCHITECTURE USING CAPACITIVE DEEP TRENCH ISOLATION (CDTI) STRUCTURES FOR ELECTRICAL CONNECTION

STMicroelectronics (Croll...

1. A method, comprising:forming a plurality of capacitive deep trench isolation structures extending completely through a semiconductor substrate from a front side surface to a back side surface, each capacitive deep trench isolation structure comprising a conductive region insulated from the semiconductor substrate by an insulating liner;
providing a metallization structure at the front side surface of the semiconductor substrate that is electrically connected to first ends of the plurality of capacitive deep trench isolation structures;
recessing the back side surface of the semiconductor substrate to expose second ends of the plurality of capacitive deep trench isolation structures; and
forming a bonding pad structure adjacent the recessed back side surface of the semiconductor substrate, wherein the bonding pad structure is directly physically and electrically connected to the conductive regions at the second ends of the plurality of capacitive deep trench isolation structures and electrically insulated from the semiconductor substrate, wherein forming the bonding pad structure comprises:
depositing a conformal layer of a dielectric material on the recessed back side surface and exposed second ends of the plurality of capacitive deep trench isolation structures;
depositing a conformal layer of an oxide material on the layer of the dielectric material;
planarizing the layer of the oxide material;
opening an aperture extending through at least the layer of the dielectric material which extends on end surfaces of the plurality of capacitive deep trench isolation structures to expose the conductive regions at the second ends of the plurality of capacitive deep trench isolation structures; and
depositing one or more metal materials forming the bonding pad structure within said aperture.

US Pat. No. 10,892,290

INTERCONNECT LAYER CONTACT AND METHOD FOR IMPROVED PACKAGED INTEGRATED CIRCUIT RELIABILITY

OmniVision Technologies, ...

1. A method of forming a packaged photosensor array comprising:fabricating a first integrated circuit having a plurality of bondpads;
forming vias through a semiconductor substrate and a dielectric layer of the first integrated circuit to expose a first layer metal of the plurality of the plurality of bondpads;
mechanically reinforcing the first layer metal of the plurality of bondpads by depositing a single-layer conductive metal plug conformal to a shape of each via and in contact with the first layer metal of the plurality of bondpads in the vias;
after depositing the conductive metal plugs in the vias, depositing and masking an interconnect metal conformal to walls of each via and in contact with the associated conductive metal plug in each via, the interconnect metal extending beyond each via;
depositing a solder-mask dielectric over the interconnect metal and forming openings therethrough;
forming solder bumps on the interconnect metal at the openings in the solder-mask dielectric; and
bonding the solder bumps to conductors of an integrated circuit package;
wherein the only metal in contact with the metal plugs are the interconnect metal and the first layer metal,
and wherein the metal plugs chemically isolate the interconnect metal from the first layer metal.

US Pat. No. 10,892,289

OPTICAL SENSORS INCLUDING A LIGHT-IMPEDING PATTERN

Samsung Electronics Co., ...

1. An optical sensor of an optical scanner, the optical sensor comprising:a plurality of photoelectric conversion regions;
a plurality of lenses on the plurality of photoelectric conversion regions;
a light-impeding layer extending between the plurality of photoelectric conversion regions and the plurality of lenses, the light-impeding layer comprising an opening between a first one of the plurality of photoelectric conversion regions and a first one of the plurality of lenses; and
a planarization layer on the light-impeding layer,
wherein the opening of the light-impeding layer overlaps the first one of the plurality of photoelectric conversion regions, and the first one of the plurality of photoelectric conversion regions is configured to generate charges in response to light that is incident on the first one of the plurality of photoelectric conversion regions,
wherein the plurality of lenses are arranged along a first direction,
wherein the first one of the plurality of lenses is spaced apart from the light-impeding layer in a second direction that is perpendicular to the first direction,
wherein a shortest distance between the first one of the plurality of lenses and the light-impeding layer in the second direction is equal to or less than a width of the first one of the plurality of lenses in the first direction, and
wherein a ratio of a width of the opening in the first direction to the width of the first one of the plurality of lenses in the first direction is greater than 0 and less than 0.7.

US Pat. No. 10,892,288

SOLID STATE IMAGING DEVICE

Kabushiki Kaisha Toshiba,...

1. A solid state imaging device, comprising a first pixel and a second pixel adjacent to each other in a first direction, structures of the first pixel and the second pixel being mutually mirror-symmetric,each of the first pixel and the second pixel including an opening region where light enters,
the opening region of the first pixel being disposed over an entire width in the first direction of the first pixel,
the opening region of the second pixel being disposed over an entire width in the first direction of the second pixel,
the first pixel being driven as one imaging element and the second pixel being driven as another one imaging element in a high-resolution imaging mode, and
a total amount of a signal charge stored in the opening region of the first pixel and a signal charge stored in the opening region of the second pixel being detected such that the first pixel and the second pixel are driven as one imaging element in a high-sensitivity imaging mode.

US Pat. No. 10,892,287

IMAGE SENSOR WITH IMAGE RECEIVER AND AUTOMATIC IMAGE SWITCHING

Cista System Corp., San ...

1. An imaging system comprising:an image sensor comprising
a first image sensor array to generate first image data for a first image,
a receiver to receive, into the image sensor, second image data for a second image, wherein the first image and the second image are captured substantially concurrently, wherein the first image includes a scene, and wherein the second image includes the scene,
an image selection circuit coupled to the first image sensor array and the receiver to receive the first image data and the second image data and select one of the first image data and the second image data according to one or more image selection criteria, and at least one of the first image data and the second image data, and
a transmitter coupled to the image selection circuit to transmit the selected one of the first image data and the second image data from the image sensor; and
a second image sensor array coupled to the image sensor to generate the second image data for the second image, wherein the second image sensor array is external to the image sensor.

US Pat. No. 10,892,286

IMAGING DEVICE

PANASONIC INTELLECTUAL PR...

1. An imaging device, comprising:a photoelectric converter that generates a signal charge by photoelectric conversion of light;
a semiconductor substrate that includes a first semiconductor layer on a surface of the semiconductor substrate;
a charge accumulation region that is an impurity region of a first conductivity type in the first semiconductor layer, the charge accumulation region being configured to accumulate the signal charge;
a first transistor that includes, as a source or a drain, a first impurity region of the first conductivity type in the first semiconductor layer; and
a blocking structure that is located between the charge accumulation region and the first transistor, wherein
the blocking structure includes
a second impurity region of a second conductivity type in the first semiconductor layer, the second impurity region being located between the charge accumulation region and the first impurity region, the second conductivity type being different from the first conductivity type, and
a first electrode that is located above the first semiconductor layer, the first electrode overlapping at least a part of the second impurity region in a plan view, the first electrode being configured to be applied with a first voltage in a period when the charge accumulation region accumulates the signal charge, the first voltage being a constant voltage.

US Pat. No. 10,892,285

DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

Au Optronics Corporation,...

1. A display panel, comprising:a substrate, having a first surface and a second surface opposite to the first surface;
a light-shielding positioning layer, disposed on the first surface, wherein the light-shielding positioning layer has at least one first alignment pattern; and
a transparent positioning layer, disposed on the second surface, wherein the transparent positioning layer has at least one second alignment pattern, and in a direction perpendicular to the substrate, the at least one first alignment pattern overlaps with the at least one second alignment pattern.

US Pat. No. 10,892,284

DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A manufacturing method of a display substrate, comprising:fabricating a gate electrode, a gate electrode insulating layer, and a semiconductor active layer sequentially on a base substrate;
fabricating a first etching stopping layer and a second etching stopping layer on the base substrate with the semiconductor active layer fabricated thereon, wherein the first etching stopping layer is disposed in a display area of the display substrate, the second etching stopping layer is disposed in a peripheral area of the display substrate, and the second etching stopping layer is a non-transparent layer; and
fabricating source/drain electrodes by a patterning process, on the base substrate with the first etching stopping layer and the second etching stopping layer fabricated thereon, wherein the second etching stopping layer is used as an alignment marker in fabricating the source/drain electrodes.

US Pat. No. 10,892,283

FLEXIBLE DISPLAY PANEL

Wuhan China Star Optoelec...

1. A flexible display panel, defined with a special-shaped cutout area and a display area, comprising a substrate, and a plurality of pixel structures, a scan line layer, and a data line layer disposed above the substrate, wherein:each of the plurality of the pixel structures comprises three sub-pixels, and the scan line layer comprises a plurality of scan lines, and the data line layer comprises a plurality of data lines;
the sub-pixels are arranged in an array over the substrate, and the scan lines and the data lines are disposed in the array of the sub-pixels;
a scan line is disposed between every two rows of the sub-pixels and two data lines are disposed between every column of the sub-pixels in the special-shaped cutout area, and the sub-pixels are connected to the scan lines adjacent thereto, the sub-pixels in the odd rows are connected to the data lines on the left side thereof, and the sub-pixels in the even rows are connected to the data lines on the right side thereof;
wherein a distance between two rows of sub-pixels disposed with the scan line is defined as a first distance; and
wherein a distance between two columns of sub-pixels disposed with no scan line is defined as a second distance, and a length of the second distance is less than a length of the first distance.

US Pat. No. 10,892,282

METAL OXIDE FILM AND METHOD FOR FORMING METAL OXIDE FILM

Semiconductor Energy Labo...

1. A transistor comprising:an oxide semiconductor layer comprising a channel formation region including a region where a plurality of circumferentially distributed spots are observable in a nanobeam electron diffraction pattern of the oxide semiconductor layer.

US Pat. No. 10,892,281

METHOD FOR MANUFACTURING A TRANSISTOR HAVING A SHARP JUNCTION BY FORMING RAISED SOURCE-DRAIN REGIONS BEFORE FORMING GATE REGIONS AND CORRESPONDING TRANSISTOR PRODUCED BY SAID METHOD

STMicroelectronics, Inc.,...

1. A method, comprising:on a bulk substrate, repeating epitaxial processes to grow a first stack of alternating semiconductor stress release buffer and semiconductor defect cap layers;
epitaxially growing a defect free and fully stress released semiconductor layer on top of an uppermost one of the semiconductor defect cap layers in the first stack, the defect free and fully stress released semiconductor layer having a first thickness;
bonding a wafer to an upper surface of the defect free and fully stress released semiconductor layer, said wafer comprising a second stack of an insulator layer and a semiconductor layer, wherein the insulator layer is bonded to the defect free and fully stress released semiconductor layer;
epitaxially growing a doped semiconductor layer on the semiconductor layer of said wafer; and
removing at least the insulator layer to form a cavity underneath the semiconductor layer of said wafer and the doped semiconductor layer.

US Pat. No. 10,892,280

INTER-DECK PLUG IN THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME

YANGTZE MEMORY TECHNOLOGI...

1. A method for forming a three-dimensional (3D) memory device, comprising: forming a first dielectric deck comprising a first plurality of interleaved sacrificial layers and dielectric layers above a substrate; forming a first channel structure extending vertically through the first dielectric deck and comprising a first memory film and a first semiconductor channel; forming (i) an inter-deck plug in an upper portion of the first channel structure and in contact with the first semiconductor channel and (ii) a recess with a stepped portion between a top surface of the inter-deck plug and a top surface of the first dielectric deck; forming an etch stop plug in the recess to cover the top surface of the inter-deck plug; forming a second dielectric deck comprising a second plurality of interleaved sacrificial layers and dielectric layers above the first dielectric deck; forming a first opening extending vertically through the second dielectric deck and ending at the etch stop plug; removing the etch stop plug from the recess to form a channel hole comprising the first opening and the recess; forming a second memory film along a sidewall of the first opening and in the recess of the channel hole; and forming a second semiconductor channel over the second memory film and extending vertically through part of the second memory film in the recess to contact the inter-deck plug.

US Pat. No. 10,892,279

NAND STRING CONTAINING SEPARATE HOLE AND ELECTRON TUNNELING DIELECTRIC LAYERS AND METHODS FOR FORMING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory openings extending through the alternating stack;
memory opening fill structures located within a respective one of the memory openings; and
a gate dielectric located between the memory opening fill structures and the electrically conductive layers,
wherein:
each of the memory opening fill structures comprises a vertical semiconductor channel, a conductive core electrode, and a memory film located between the vertical semiconductor channel and the conductive core electrode; and
the memory film comprises a layer stack including a first tunneling dielectric contacting the vertical semiconductor channel, a second tunneling dielectric contacting the conductive core electrode, and a charge storage layer located between the first tunneling dielectric and the second tunneling dielectric.

US Pat. No. 10,892,278

THREE-DIMENSIONAL SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A three-dimensional semiconductor device comprising:a stack of layers comprising gate electrodes disposed one over another on a substrate;
a channel structure extending through the gate electrodes and connected to the substrate;
an insulating gap-fill pattern disposed within the channel structure and surrounded by the channel structure as viewed in a plan view; and
a conductive pattern on the insulating gap-fill pattern, wherein:
a portion of the insulating gap-fill pattern extends into the conductive pattern,
at least a portion of the conductive pattern is interposed between the portion of the insulating gap-fill pattern and the channel structure, and
the portion of the insulating gap-fill pattern is spaced apart from the channel structure by the at least a portion of the conductive pattern.

US Pat. No. 10,892,277

HIGH-? DIELECTRIC LAYER IN THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

YANGTZE MEMORY TECHNOLOGI...

1. A three-dimensional (3D) memory device, comprising:a substrate;
a memory stack comprising:
a first high-? dielectric layer above the substrate, and
a plurality of interleaved conductor layers and dielectric layers above the first high-? dielectric layer; and
a semiconductor plug disposed with a lowest surface of the semiconductor plug directly contacting a highest surface of the substrate and in an opening of the first high-? dielectric layer.

US Pat. No. 10,892,276

THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATION METHODS THEREOF

YANGTZE MEMORY TECHNOLOGI...

1. A method for forming a three-dimensional (3D) memory device, comprising:forming an initial channel hole in a structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate, the first layers comprising at least one of polysilicon or carbon;
removing a portion of each of the first layers to form an offset between the side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole, wherein the offset creates a recess region in each of the first layers between adjacent second layers along a vertical direction such that there is an open space between second layers in direct contact with the first layer;
forming, in the channel hole, a semiconductor channel comprising a blocking layer in direct contact with the first layers;
forming a plurality of gate electrodes based on the plurality of second layers;
removing the first layers; and
removing a portion of the blocking layer directly after removal of the first layers to form a disconnected blocking layer.

US Pat. No. 10,892,275

STACKED CONNECTIONS IN 3D MEMORY AND METHODS OF MAKING THE SAME

Yangtze Memory Technologi...

1. A memory device, comprising:a substrate;
a first layer stack above the substrate and having first alternating conductor and insulator layers;
a second layer stack, disposed over the first layer stack and having second alternating conductor and insulator layers;
one or more first vertical structures extending through the first layer stack;
one or more second vertical structures extending through the second layer stack; and
a conductive material sandwiched between the one or more first vertical structures and the one or more second vertical structures, wherein
the conductive material projects outward from the one or more first vertical structures and the one or more second vertical structures; and
the one or more second vertical structures extend through a portion of the conductive material.

US Pat. No. 10,892,274

THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

Yangtze Memory Technologi...

1. A method for forming a three-dimensional (3D) memory device, comprising:forming an alternating dielectric stack on a substrate;
forming a channel hole penetrating the alternating dielectric stack to expose a surface of the substrate;
forming an epitaxial layer on a bottom of the channel hole;
forming a functional layer covering a sidewall of the channel hole and a top surface of the epitaxial layer;
forming a protecting layer covering the functional layer on the sidewall and the bottom of the channel hole;
removing portions of the functional layer and the protecting layer on the top surface of the epitaxial layer to form an opening to expose a surface of the epitaxial layer;
expanding the opening laterally, by removing portions of the functional layer on the top surface of the epitaxial layer and the protecting layer on the sidewall of the channel hole, to increase an exposed area of the epitaxial layer at the bottom of the channel hole, wherein an axial section of the remaining protecting layer includes two L-shaped portions; and
forming a channel structure on the sidewall of the channel hole and being in electrical contact with the epitaxial layer through the expanded opening.

US Pat. No. 10,892,273

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a stacked body having a stepped portion in which a plurality of metal layers is stacked via an insulating layer, and end portions of the plurality of metal layers are formed in a stepwise manner;
a plurality of pillars extending in a stacking direction of the stacked body to penetrate the stacked body from an uppermost metal layer to a lowermost metal layer of the stacked body, and forming a plurality of memory cells at respective intersections with at least metal layers arranged near a center of the stacked body, of the plurality of metal layers;
a plurality of columnar portions arranged in steps of the stepped portion and penetrating the stepped portion; and
a band portion provided near a leading end portion of the metal layer of a lowermost step of the stepped portion, the band portion extending in a first direction along the leading end portion and dividing the stacked body and a peripheral region of the stacked body, wherein
a coverage of the columnar portions arranged in the lowermost step is larger than a coverage of the columnar portions arranged in an upper step adjacent to the lowermost step only in a second direction toward a region where the memory cells are arranged.

US Pat. No. 10,892,272

SEMICONDUCTOR MEMORY DEVICES INCLUDING A STRESS RELIEF REGION

Samsung Electronics Co., ...

16. A semiconductor memory device comprising:a semiconductor layer on a substrate including a chip region and a stress relaxation region that are adjacent to each other in a first direction;
a peripheral circuit structure between the substrate and the semiconductor layer;
a stack structure including vertically stacked electrodes on the chip region;
a vertical semiconductor structure in the stack structure;
an interlayer insulating layer on the stacked structure;
first contact plugs connected to the electrodes through the interlayer insulating layer on the chip region; and
a stress relief structure penetrating the interlayer insulating layer on the stress relaxation region,
wherein the stress relief structure has a width in the first direction that decreases with increasing distance from an upper surface of one of the first contact plugs, and
wherein the width of the stress relief structure is greater than a width of the vertical semiconductor structure in the first direction.

US Pat. No. 10,892,271

INTERCONNECT STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE

Yangtze Memory Technologi...

1. A three-dimensional (3D) NAND memory device, comprising:a substrate;
an alternating layer stack on the substrate, the alternating layer stack comprising a staircase structure;
a barrier structure extending vertically through the alternating layer stack, wherein the alternating layer stack comprises (i) an alternating dielectric stack comprising a plurality of dielectric layer pairs enclosed laterally by at least the barrier structure, and (ii) an alternating conductor/dielectric stack comprising a plurality of conductor/dielectric layer pairs;
a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack;
an etch stop layer on an end of the channel structure;
a plurality of first contacts, an interconnect conductor layer, and a contact layer comprising a plurality of second contacts, wherein each of (i) a conductor layer of the alternating conductor/dielectric stack in the staircase structure, (ii) the etch stop layer, and (iii) the slit structure is electrically connected to the interconnect conductor layer by a corresponding first contact and a respective one of the plurality of second contacts.

US Pat. No. 10,892,270

SEMICONDUCTOR MEMORY DEVICE HAVING AN ARRAY CHIP BONDED TO A CIRCUIT CHIP BY A BONDING METAL

Toshiba Memory Corporatio...

9. A semiconductor memory device comprising:an array chip including
a three-dimensionally disposed plurality of memory cells,
a memory-side interconnection layer provided below the memory cells and connected to the memory cells,
a stacked body including a plurality of electrode layers stacked via an insulating layer,
a semiconductor body extending in a stacking direction of the stacked body in the stacked body,
a charge storage film provided between the semiconductor body and the electrode layers,
a bit line connected to an end portion of the semiconductor body, and
a source line connected to another end portion of the semiconductor body;
a circuit chip including a substrate, a MOS transistor provided on the substrate, and a circuit-side interconnection layer provided above the MOS transistor and connected to the MOS transistor, the circuit chip provided below the array chip and stuck to the array chip, the circuit-side interconnection layer provided below the memory-side interconnection layer of the array chip;
a bonding metal provided between the memory-side interconnection layer and the circuit-side interconnection layer, and bonded to the memory-side interconnection layer and the circuit-side interconnection layer;
a pad included in the memory-side interconnection layer of the array chip, wherein
the pad is provided in a same layer as the source line and formed of a same material as the source line; and
an external connection electrode provided on the array chip, the external connection electrode electrically connected to the pad.

US Pat. No. 10,892,269

SEMICONDUCTOR MEMORY DEVICE HAVING A BONDED CIRCUIT CHIP INCLUDING A SOLID STATE DRIVE CONTROLLER CONNECTED TO A CONTROL CIRCUIT

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a circuit chip including a substrate, a control circuit provided on the substrate, a solid state drive controller provided on the substrate, and a circuit-side interconnection layer;
an array chip being bonded to the circuit chip, the array chip including a memory-side interconnection layer and a three-dimensionally disposed plurality of memory cells above the memory-side interconnection layer, the memory cells connected to the memory-side interconnection layer; and
a bonding metal provided between the circuit-side interconnection layer and the memory-side interconnection layer, and bonded to the memory-side interconnection layer and the circuit-side interconnection layer; wherein
the control circuit is connected to the memory-side interconnection layer through the circuit-side interconnection layer and the bonding metal,
the control circuit is connected to the solid state drive controller through the circuit-side interconnection layer.

US Pat. No. 10,892,268

INTEGRATED STRUCTURES CONTAINING VERTICALLY-STACKED MEMORY CELLS

Micron Technology, Inc., ...

1. An integrated structure comprising:a stack of alternating dielectric levels comprising a dielectric material and conductive levels that comprise a conductive material that physically contacts the dielectric material;
vertically-stacked memory cells within the conductive levels, each of the vertically stacked memory cells comprising a charge trapping region, the dielectric material of the dielectric levels extending over and beneath the charge trapping region across an entirety of a width of the charge trapping region;
an opening extending through the stack, the opening having a sidewall extending vertically continuously from top to bottom of the opening; and
a channel liner material within the opening and along the memory cells and directly against the dielectric material of the dielectric levels; and
a germanium-comprising channel material within the opening and spaced from the sidewall by the channel liner material, the germanium-comprising channel material having a horizontally-extending gradient of germanium, and comprising at least one dopant; the dopant being p-type, n-type or i-type and being present in a horizontally-extending dopant gradient.

US Pat. No. 10,892,267

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING THROUGH-MEMORY-LEVEL CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A device structure comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate and including stepped surfaces in a staircase region;
a dielectric liner located on the stepped surfaces;
a retro-stepped dielectric material portion overlying the dielectric liner;
a flanged conductive via structure including a conductive pillar portion extending through the retro-stepped dielectric material portion, the dielectric liner, a horizontal surface among the stepped surfaces, and a subset of layers within the alternating stack, and a conductive flange portion laterally protruding from the conductive pillar portion and contacting a top surface of a topmost electrically conductive layer in the subset of layers within the alternating stack; and
annular insulating spacers located at each level of the electrically conductive layers in the subset of layers within the alternating stack and laterally surrounding the conductive pillar portion,wherein:the insulating layers comprise a first silicon oxide material;
the dielectric liner comprises a second silicon oxide material; and
the retro-stepped dielectric material portion comprises a third silicon oxide material,wherein:an etch rate of the second silicon oxide material in a 100:1 dilute HF solution is greater than an etch rate of the first silicon oxide material in the 100:1 dilute HF solution by a factor of at least 3; and
the etch rate of the second silicon oxide material in the 100:1 dilute HF solution is greater than an etch rate of the third silicon oxide material in the 100:1 dilute HF solution by a factor of at least 3.