US Pat. No. 10,693,603

METHOD FOR TRANSMITTING AND RECEIVING SIGNAL IN A WIRELESS LOCAL AREA NETWORK AND DEVICE FOR SAME

LG Electronics Inc., Seo...

1. A method of transmitting, by a first station (STA), a signal to a second STA through a plurality of channels in a wireless LAN (WLAN) system, the method comprising:transmitting a beam refinement protocol (BRP) packet to the second STA, wherein the BRP packet is generated based on a lowest modulation and coding scheme (MCS) to perform a beamforming training procedure on the plurality of channels, wherein the plurality of channels is generated based on a channel bonding scheme or a channel aggregation scheme; and
transmitting the signal to the second STA through the plurality of channels based on the beamforming training procedure,
wherein the BRP packet is configured in an order of a Legacy Short Training Field (L-STF) field, a Legacy Channel Estimation (L-CE) field, a Legacy Header (L-Header) field, an Enhanced Directional Multi Gigabit Header A (EDMG Header A) field, a Beam Refinement Protocol (BRP) data frame, and a Training (TRN) field,
wherein the BRP data frame is duplicated for the plurality of channels,
wherein the TRN field is transmitted through bonded channels based on the channel bonding scheme according to information in the EDMG Header A field.

US Pat. No. 10,693,602

SYSTEM AND METHOD FOR A LONG-TERM EVOLUTION (LTE)-COMPATIBLE SUBFRAME STRUCTURE FOR WIDEBAND LTE

Futurewei Technologies, I...

1. A method for scheduling transmissions, the method comprising:selecting, by a base station, a wideband micro-frame from a plurality of wideband micro-frames in a subframe of a wideband carrier for a wideband transmission, wherein the selected wideband micro-frame having a time duration that covers a first symbol of the subframe in the time-domain; and
scheduling, by the base station, the wideband transmission in the time duration of the selected wideband micro-frame for uplink or downlink transmissions in accordance with whether narrowband signaling carried in the first symbol is uplink narrowband signaling or downlink narrowband signaling, wherein a downlink wideband transmission is scheduled in the time duration of the selected wideband micro-frame when the downlink narrowband signaling is carried in the first symbol, and wherein an uplink wideband transmission is scheduled in the time duration of the selected wideband micro-frame when the uplink narrowband signaling is carried in the first symbol; and
signaling the wideband transmission scheduling to a user equipment (UE).

US Pat. No. 10,693,601

TERMINAL, BASE STATION, TRANSMISSION METHOD, AND RECEPTION METHOD

Panasonic Intellectual Pr...

1. A terminal comprising:a receiver which, in operation, receives information indicating a first subframe at which repetition transmission of a Scheduling Request (SR) starts and a second subframe at which repetition transmission of an Acknowledgement/Negative Acknowledgement (ACK/NACK) for a downlink data signal starts; and
a transmitter which, in operation, repeatedly transmits the SR using a defined number of consecutive subframes starting at the first subframe and the ACK/NACK using at least the defined number of consecutive subframes starting at the second subframe,
wherein the first subframe is set to the same time resource as the second subframe such that start positions of the SR repetition transmission and the ACK/NACK repetition transmission are the same, and a number of repetitions of the ACK/NACK is the same as a number of repetitions of the SR.

US Pat. No. 10,693,600

METHODS AND SYSTEMS FOR TRANSMITTING ERROR CORRECTION PACKETS

PISMO LABS TECHNOLOGY LIM...

1. A method carried out at a first communications router for transmitting data packets to a second communications router through a plurality of WAN interfaces:a. receiving a first data packet from a first host through a local area network (LAN) Interface, wherein the first data packet is destined to a second host reachable through the second communications router;
b. transmitting the first data packet to the second communications router through a first WAN interface;
c. storing the first data packet in a local storage medium;
d. retransmitting the first data packet to the second communications router through a second WAN interface;
e. transmitting an error correction packet corresponding to the first data packet through a third WAN interface;wherein at least two of the first WAN interface, the second WAN interface and the third WAN interface are two different WAN interfaces.

US Pat. No. 10,693,598

CONFIGURATION METHOD FOR SENDING AND RECEIVING DATA AND AN APPARATUS THEREOF

YULONG COMPUTER TELECOMMU...

1. A configuration method for sending and receiving data, wherein, the method comprises:receiving a second configuration signal sent by a network device, wherein, the second configuration signal is for instructing a terminal device to simultaneously detect at least one of the following four types of downlink control information (DCI) information:
a first DCI information which contains a Code Block Group indicator and a Code Block Group decoding manner;
a second DCI information which contains a Code Block Group indicator and does not contain a Code Block Group decoding manner;
a third DCI information which contains a Code Block Group decoding manner and does not contain a Code Block Group indicator;
a fourth DCI information which does not contain a Code Block Group indicator or a Code Block Group decoding manner;
wherein the Code Block Group indicator is for indicating which Code Block Groups are contained in the Transport Block corresponding to the DCI information, and the Code Block Group decoding manner is for indicating a decoding manner for the respective Code Block Groups in the Transport Block corresponding to the DCI information;
receiving a first configuration signal sent by the network device, wherein, the first configuration signal is for indicating whether a first Transport Block to be sent by the network device is a retransmitted Transport Block, and the first configuration signal contains DCI information of the first Transport Block;
receiving the first Transport Block sent by the network device, wherein, the first Transport Block comprises at least one Code Block Group;
decoding the Code Block Group in the first Transport Block according to the DCI information of the first Transport Block.

US Pat. No. 10,693,597

METHOD AND APPARATUS FOR TRANSMITTING STATUS REPORT FOR RECEIVER

SPREADTRUM COMMUNICATIONS...

1. A method for transmitting status report at a receiver, comprising:determining a format of a Radio Link Control (RLC) status report;
transmitting the RLC status report to a sender, according to the format of the RLC status report; and
wherein the receiver is a receiver of a service data, and the sender is a sender of a service data,
wherein determining the format of the RLC status report comprises: identifying the format of the RLC status report configured by the sender, or configuring the format of the RLC status report by the receiver,
wherein if the format of the RLC status report is configured by the receiver, the method further comprises indicating the format of the RLC status report to the sender, and
wherein if the format of the RLC status report is configured by the receiver, determining the format of the RLC status report comprises: receiving a selection criterion configured for the RLC status report from the sender and selecting and configuring the format of the RLC status report from pre-configured formats according to the selection criterion including any one of the following: selecting the format of the RLC status report according to a rate threshold of the data radio bearer or data stream; selecting the format of the RLC status report according to the number of bits required to transmit the RLC status report in different pre-configured formats; selecting the format of the RLC status report according to the number of RLC data packets transmitted in a single transmission time interval (TTI); or selecting the format of the RLC status report according to the number of RLC data packets consecutively not received; or, if the format of the RLC status report is configured by the receiver, the format of the RLC status report is configured according to any one of the following: a rate of a data radio bearer, bit number of RLC status reports in different formats, the number of RLC data packets transmitted within a single TTI, the number of RLC data packets consecutively not received, or a device type of the receiver.

US Pat. No. 10,693,596

DOWNLINK HARQ FEEDBACK TRANSMISSION

TELEFONAKTIEBOLAGET LM ER...

11. An access node in a wireless network, the access node comprising:a transmitter;
a memory storing instructions; and
a processing system configured to execute the instructions, wherein the access node is configured to:
generate a HARQ feedback table; and
transmit the HARQ feedback table toward a plurality of communication devices, wherein the HARQ feedback table comprising a HARQ feedback entry for each communication device included in a set of two or more communication devices, wherein the set of communication devices comprises the first communication device and a second communication device, wherein the HARQ feedback entry for the first communication device comprises a first communication device identifier identifying the first communication device and at least two HARQ feedbacks, and wherein said at least two HARQ feedbacks include a first HARQ feedback for a first HARQ process of the first communication device and a second HARQ feedback for a second HARQ process of the first communication device.

US Pat. No. 10,693,595

ACK CLOCK COMPENSATION FOR HIGH-SPEED SERIAL COMMUNICATION INTERFACES

International Business Ma...

1. A transceiver for sending and receiving network packets, the transceiver comprising:packet processing logic that receives the network packets, the packet processing logic comprising an acknowledge (ACK) receive queue that includes a plurality of single-bit entries, wherein the packet processing logic generates an ACK bit for each received network packet, stores each ACK bit in the ACK receive queue, and wafts until multiple of the plurality of entries in the ACK receive queue contain valid ACK bits before transmitting one of the valid ACK bits from the ACK receive queue; and
an ACK compensation mechanism that monitors the ACK receive queue, and when a number of valid ACK bits in the ACK receive queue is less than a predetermined lower threshold, the ACK compensation mechanism sends at least one network packet that increases the number of valid ACK bits in the ACK receive queue, wherein the at least one network packet that increases the number of valid ACK bits in the ACK queue comprises a deleted ACK control block that indicates the next transmitted packet does not have a valid ACK bit, and when the number of valid ACK bits in the ACK receive queue is greater than a predetermined upper threshold, the ACK compensation mechanism sends at least one network packet that decreases the number of valid ACK bits in the ACK receive queue, wherein the at least one network packet that decreases the number of valid ACK bits in the ACK queue comprises an extra ACK control block.

US Pat. No. 10,693,594

COMMUNICATION DEVICE AND METHOD FOR STORING DATA

Apple Inc., Cupertino, C...

1. A communication device comprising:a chip including an on-chip memory, and implementing, at least partially, a receiver, wherein the receiver is configured to:
receive data via a communication channel; and
store the received data in the on-chip memory;
an off-chip memory; and
one or more processors configured to:
determine whether the communication device is to request a retransmission for the received data,
store the received data, from the on-chip memory, into the off-chip memory in response to determining the communication device is to request the retransmission for the received data, and
prevent storing of the received data in the off-chip memory in response to determining the communication device is to omit the request for the retransmission for the received data,
wherein the receiver is configured to receive the data via a retransmission protocol, and
wherein the on-chip memory has a size that is larger than a retransmission protocol process size of the retransmission protocol but smaller than two times the retransmission protocol process size of the retransmission protocol.

US Pat. No. 10,693,593

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

LG ELECTRONICS INC., Seo...

1. An apparatus for receiving a broadcast signal, the apparatus comprising:a tuner configured to receive the broadcast signal carrying broadcast data and signaling information for time deinterleaving;
a demodulator configured to demodulate the broadcast signal by an Orthogonal Frequency Division Multiplex (OFDM) scheme;
a time deinterleaver configured to deinterleave data in one or more signal frames in the demodulated broadcast signal based on the signaling information for time deinterleaving, the time deinterleaver including:
a convolutional deinterleaver configured to deinterleave the data; and
a block deinterleaver configured to deinterleave the deinterleaved data based on a Time Interleaving (TI) block; and
a decoder to decode the time deinterleaved data,
the signaling information for time deinterleaving including:
first information representing a number of TI blocks to which a time interleaving operation is applied and
second information related to a maximum number of Forward Error Correction (FEC) blocks per an interleaving frame including one or more TI blocks,
wherein a maximum number of FEC blocks for time deinterleaving TI block is obtained based on the first information and the second information, and
the maximum number of FEC blocks is greater than or equal to a number of FEC blocks of the TI block.

US Pat. No. 10,693,592

METHOD OF TRANSMITTING AND RECEIVING SYSTEM INFORMATION AND DEVICE THEREFOR

LG Electronics Inc., Seo...

4. An apparatus for receiving system information in a wireless communication system, the apparatus comprising:at least one processor; and
at least one computer memory operably connectable to the at least one processor and storing instructions that, when executed by the at least one processor, performs operations comprising:
receiving a Physical Downlink Control Channel (PDCCH) including Downlink Control Information (DCI) for scheduling the system information;
obtaining the DCI based on a System Information-Radio Network Temporary Identifier (SI-RNTI);
obtaining a bit in the DCI for determining the system information type from;
determining the system information type as Remaining Minimum System Information (RMSI) based on the bit being a first value or the system information type as Other System Information (OSI) based on the bit being a second value; and
receiving the system information based on the determined system information type.

US Pat. No. 10,693,591

DATA MAPPING METHOD AND APPARATUS IN WIRELESS COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method, performed by a base station, of transmitting and receiving data in a wireless communication system, the method comprising:determining whether a code block (CB), one of a plurality of CBs included in a transport block (TB), is scheduled for a transmission based on code block group transmission information (CBGTI);
in response to the CB being scheduled for the transmission, determining a length of a sequence for the CB based on a number of CBs of the TB or a number of scheduled CBs of the TB;
generating the sequence for the CB according to the determined length of the sequence; and
transmitting a signal including the generated sequence.

US Pat. No. 10,693,590

METHOD FOR POLAR CODING AND APPARATUS

Huawei Technologies Co., ...

1. A method for coding, performed by a device in a wireless communication network, comprising:inputting a first bit sequence, wherein the first bit sequence comprises bits for indicating timing, wherein the bits for indicating timing comprises a set of bits for indicating synchronization signal block index (SSBI);
interleaving the first bit sequence to obtain a first interleaved sequence having sequence number starting with a sequence number of 0, wherein the set of bits for indicating SSBI are placed in positions indicated by sequence numbers of 2, 3 and 5 in the first interleaved sequence;
adding a number of Cyclic Redundancy Check (CRC) bits on the first interleaved sequence to obtain a second bit sequence;
interleaving on the second bit sequence according to an interleave pattern to obtain a second interleaved sequence;
polar encoding the second interleaved sequence to obtain the encoded sequence; and
outputting the encoded sequence.

US Pat. No. 10,693,588

TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, RECEPTION METHOD, INTEGRATED CIRCUIT, AND PROGRAM

SUN PATENT TRUST, New Yo...

1. A transmission device comprising:a split circuit configured to split baseband frames into first frames and second frames;
a first processor connected to the split circuit to perform error correction coding and mapping on the first frames to generate first cells consisting of a first initial cell and first remaining cells following the first initial cell;
a second processor connected to the split circuit to perform error correction coding and mapping on the second frames to generate second cells consisting of a second initial cell and second remaining cells following the second initial cell;
an exchange circuit connected to the first processor and the second processor to exchange a first subset of the first cells with a second subset of the second cells to generate a first exchanged cell stream and a second exchanged cell stream; and
a transmission circuit connected to the exchange circuit to transmit the first exchanged cell stream and the second exchanged cell stream in a first frequency band and a second frequency band, respectively,
wherein the first subset includes the first initial cell and the second subset includes the second initial cell.

US Pat. No. 10,693,587

MULTI-WIRE PERMUTED FORWARD ERROR CORRECTION

KANDOU LABS, S.A., Lausa...

1. An apparatus comprising:a plurality of forward error-correction (FEC) encoders configured to generate a plurality of streams of FEC-encoded bits, each FEC encoder configured to receive a respective subset of a plurality of subsets of information bits, and to responsively generate a corresponding stream of FEC-encoded bits of the plurality of streams of FEC-encoded bits; and
a permuter configured to receive the plurality of streams of FEC-encoded bits, and to responsively provide each stream of FEC-encoded bits of the plurality of streams of FEC-encoded bits to a respective sub-channel encoder of a plurality of sub-channel encoders, wherein the permuter is configured to provide sequential streams of FEC-encoded bits received from a given FEC encoder in a cyclically varying order to each sub-channel encoder of the plurality of sub-channel encoders; and
the plurality of sub-channel encoders configured to generate a set of codewords of a vector signaling code for transmission over a multi-wire bus, each codeword of the set of codewords generated by summing a plurality of weighted sub-channel vectors, each weighted sub-channel vector generated by a respective sub-channel encoder modulating a corresponding sub-channel vector of a plurality of mutually orthogonal sub-channel vectors according to a bit in the received stream of FEC-encoded bits.

US Pat. No. 10,693,586

METHOD FOR RECEIVING REFERENCE SIGNAL RESOURCES IN A WIRELESS COMMUNICATION SYSTEM AND APPARATUS

LG Electronics Inc., Seo...

1. A method for performing a Channel State Information-Reference Signal (CSI-RS) based reporting in a wireless communication system, the method performed by a User Equipment (UE) and comprising:receiving, from a base station, a configuration for a (i) first CSI-RS resource set that is based on a time unit and (ii) a second CSI-RS resource set that is based on a sub-time unit, wherein the time unit includes a plurality of sub-time units;
receiving a plurality of CSI-RS resources included in the second CSI-RS resource set; and
based on the plurality of CSI-RS resources being configured to be transmitted via different transmission beams, reporting a CSI-RS Resource Indicator (CRI) for the plurality of CSI-RS resources to the base station,
wherein, based on the plurality of CSI-RS resources being configured to be transmitted via the same transmission beam, the UE does not report any information including the CRI to the base station.

US Pat. No. 10,693,585

SYSTEM AND METHOD FOR MULTI-USER FULL DUPLEX LINK ADAPTATION

Futurewei Technologies, I...

1. A method comprising:providing, by a user device, a multi-user full duplex mode enabling a first link direction from a first wireless device to the user device, and a second link direction from the user device to a second wireless device;
requesting, by the user device from the second wireless device, a first channel quality indicator indicating channel quality between the user device and the second wireless device in a full duplex time period and a second channel quality indicator indicating channel quality between the user device and the second wireless device in a non-full duplex time period; and
providing, by the user device, a signal to at least one of the first or second wireless devices to adjust at least one parameter of the full duplex mode based on an evaluation of the full duplex mode using the first and second channel quality indicators.

US Pat. No. 10,693,584

SYSTEM AND METHOD FOR ADAPTIVE MODULATION

InterDigital Patent Holdi...

1. A method implemented by a wireless transmit/receive unit (WTRU), the method comprising:the WTRU receiving information indicating that the WTRU is to use a plurality of modulation and coding scheme (MCS) tables for MCS selection, wherein a first MCS table of the plurality of MCS tables comprises MCS values mapped to a modulation order of QPSK (Quadrature Phase Shift Keying), 16QAM (Quadrature Amplitude Modulation), or 64QAM, and wherein a second MCS table of the plurality of MCS tables comprises at least one MCS value mapped to a modulation order of 256QAM;
the WTRU receiving a physical downlink control channel (PDCCH) transmission comprising scheduling information for a downlink shared channel transmission; and
the WTRU determining an MCS for the downlink shared channel transmission based on the first MCS table or the second MCS table, wherein the WTRU determines which of the first MCS table or the second MCS table is to be used to determine the MCS used for the downlink shared channel transmission based on at least an identity used to scramble the PDCCH transmission.

US Pat. No. 10,693,583

APPARATUS, SYSTEM AND METHOD OF COMMUNICATING A CHANNEL ESTIMATION FIELD WITH GOLAY SEQUENCES

INTEL CORPORATION, Santa...

1. An apparatus comprising:memory circuitry; and
a processor comprising logic and circuitry configured to cause an Enhanced Directional Multi-Gigabit (EDMG) wireless communication station (STA) to:
generate an EDMG Channel Estimation Field (EDMG-CEF) based on a first sequence having a length of 1536 and a second sequence having a length of 1536, the first sequence comprising a first combination of a pair of Golay complementary sequences of length 384, the second sequence comprising a second combination, different from the first combination, of the pair of Golay complementary sequences of length 384; and
transmit an EDMG Physical Layer (PHY) Protocol Data Unit (PPDU) comprising the EDMG-CEF over a channel bandwidth of 6.48 Gigahertz (GHz).

US Pat. No. 10,693,582

LOCALIZATION OF REFERENCE SYMBOLS IN COMMUNICATIONS SYSTEMS

The Johns Hopkins Univers...

1. A method comprising:receiving a first signal capture from a first wireless, cellular communication signal transmitted by a base station, the first signal capture being a portion of a first radio frame;
aligning the first signal capture with a frame structure to determine a location of a start of a first symbol in the first signal capture;
decoding data within the first signal capture to generate a first capture grid based on the location of the start of the first symbol in the first signal capture;
receiving a second signal capture from a second wireless, cellular communication signal transmitted by the base station, the second signal capture being one or more radio frame durations after the first signal capture, the second signal capture being a portion of a second radio frame;
aligning the second signal capture with the frame structure to determine a location of a start of a second symbol in the second signal capture;
decoding data within the second signal capture to generate a second capture grid based on the location of the start of the second symbol in the second signal capture;
combining the first capture grid with the second capture grid to generate a resultant grid, the resultant grid indicating positions of reference symbols that are commonly located within both the first capture grid and the second capture grid;
determining a subset of possible physical cell identifiers based on a position of a selected reference symbol within the resultant grid; and
performing a search of the subset of possible physical cell identifiers to identify a current cell identifier corresponding to the base station for a mobile communications device.

US Pat. No. 10,693,581

ORTHOGONAL TIME FREQUENCY SPACE MODULATION OVER A PLURALITY OF NARROW BAND SUBCARRIERS

Cohere Technologies, Inc....

1. A method of transmitting, on a per-frame basis, a plurality of data symbols over an impaired wireless channel comprising a plurality of narrow-band subcarriers, the method comprising:for each frame, distributing the plurality of data symbols over a two-dimensional (2D) orthogonal time frequency space (OTFS) delay-Doppler frame by assigning each data symbol to its own unique 2D OTFS delay-Doppler frame location, wherein the 2D OTFS delay-Doppler frame comprises a 2D delay-Doppler grid, and wherein the 2D OTFS delay-Doppler frame location is a 2D delay-Doppler grid coordinate;
OTFS transforming, using an OTFS transform operation, the plurality of data symbols on the 2D OTFS delay-Doppler frame by using each data symbol and frame location to modulate a unique, location specific, 2D basis wave function selected from a set of mutually orthogonal 2D basis wave functions operating over a 2D OTFS time-frequency frame, wherein the OTFS transforming spreads each data symbol, in a lossless and invertible manner, throughout the 2D OTFS time-frequency frame, and wherein the OTFS transforming creates a 2D OTFS time-frequency frame based wave aggregate;
scrambling the 2D OTFS time-frequency frame based wave aggregate with a scrambling operation to generate a scrambled 2D OTFS time-frequency frame based wave aggregate; and
modulating and transmitting portions of the scrambled 2D OTFS time-frequency frame based wave aggregate, over the plurality of narrow-band subcarriers, over a plurality of time intervals,
wherein a granularity and extent of the portions, the plurality of narrow-band subcarriers, and the plurality of time intervals are chosen so that the sum of the transmitted portions characterizes the scrambled 2D OTFS time-frequency frame based wave aggregate, and
wherein the impaired wireless channel distorts the transmitted portions into channel distorted portions.

US Pat. No. 10,693,580

SYSTEMS AND METHODS TO SYNCHRONIZE WIRELESS DEVICES IN THE PRESENCE OF A FMCW RADIO ALTIMETER

Honeywell International I...

10. A system for synchronizing a wireless network sharing a radio spectrum with a radio altimeter, the system comprising:a memory storing instructions; and
a processor executing the instructions to execute a process, the process including:
receiving information regarding a radio altimeter signal;
in response to receiving the information regarding the radio altimeter signal, allocating a timeslot for a first frequency channel, the first frequency channel periodically sharing a frequency spectrum with the radio altimeter signal, the allocated timeslot being calculated not to conflict with the radio altimeter signal; and
in response to allocating the timeslot, transmitting, to a plurality of device nodes, an arbitrary timing synchronization beacon (ATSB) during the allocated timeslot delinked from any periodicity so that the ATSB and the radio altimeter signal do not concurrently occupy a same channel at a same time.

US Pat. No. 10,693,579

TRANSPARENT CLOCKING IN CROSS CONNECT SYSTEM

IPG PHOTONICS CORPORATION...

1. A method for providing transparent clocking between a plurality of ingress ports and a plurality of egress ports in a cross-connect system, the method comprising:receiving a data signal at a first ingress port of the plurality of ingress ports and recovering a clock signal from the data signal;
generating a synthesized clock signal based on the recovered clock signal, the synthesized clock signal being adjusted to match the recovered clock signal;
passing data representing the received data signal from the first ingress port to a selected one of the egress ports; and
wherein passing the data representing the received data signal includes clocking the data at the selected one of the egress ports in order to transmit a signal based on the synthesized clock signal such that the clock frequency of the signal transmitted by the selected one of the egress ports substantially matches the clock frequency of the data signal received at the first ingress port.

US Pat. No. 10,693,578

PREDICTIVE RADIO TUNING SYSTEMS AND METHODS FOR AIRCRAFT

Rockwell Collins, Inc., ...

1. A predictive radio tuning system for an aircraft, the predictive radio tuning system comprising:a processor configured to:
receive flight information from avionics of the aircraft and radio frequency information from an internet-based system wide information management system (SWIM); and
provide a list of predicted frequencies in response to the flight information and the radio frequency information when the aircraft is under prior conditions using previous selections of frequencies received via a virtual radio tuning panel under the prior conditions, wherein the list of predicted frequencies is displayed on the virtual radio tuning panel for selection by a user.

US Pat. No. 10,693,577

REQUEST TO SEND (RTS) TO GROUP WITHIN WIRELESS COMMUNICATIONS

Avago Technologies Intern...

1. A wireless communication device comprising:a communication interface; and
processing circuitry that is coupled to the communication interface, wherein at least one of the communication interface or the processing circuitry configured to:
receive, from a first other wireless communication device, a request to send (RTS) to group (RTG) frame that includes a first RTS intended for the wireless communication device that is modulated within a first sub-channel that includes a first subset of orthogonal frequency division multiple access (OFDMA) sub-carriers of a communication channel and a second RTS intended for a second other wireless communication device that is modulated within a second sub-channel that includes a second subset of OFDMA sub-carriers of the communication channel;
generate a clear to send (CTS);
transmit, in response to the RTG frame, the CTS to the first other wireless communication device; and
receive, from the first other wireless communication device, an OFDMA data frame that includes first data intended for the wireless communication device or second data intended for the second other wireless communication device.

US Pat. No. 10,693,576

CARRIER FREQUENCY OFFSET MODELING FOR RADIO FREQUENCY FINGERPRINTING

LEVL TECHNOLOGIES, INC., ...

1. A method comprising operating at least one hardware processor for:receiving, by a radio frequency (RF) receiver, a plurality of training RF transmissions from an RF device, wherein each of said training RF transmissions is temporally associated with operational parameters and ambient parameters of said RF receiver and said RF device;
at a training stage, training a machine learning classifier based, at least in part, on a training set comprising:
(i) a Carrier Frequency Offset (CFO) value calculated for each of said training RF transmissions, and
(ii) labels associated with said operational parameters and said ambient parameters; and
at an inference stage, applying said trained machine learning classifier to determine whether one or more runtime RF transmissions originate from said RF device.

US Pat. No. 10,693,575

SYSTEM AND METHOD FOR THROUGHPUT PREDICTION FOR CELLULAR NETWORKS

1. A method, comprising:identifying, by a processing system including a processor, a plurality of performance indicators regarding a cellular network;
obtaining, by the processing system, historical data regarding the plurality of performance indicators for each of a series of time points during a past time period having a predetermined length, the historical data for each of the plurality of performance indicators forming an array of values for that performance indicator;
generating, by the processing system from each array, a set of inputs to an algorithm for predicting a throughput of the cellular network during a future time period having a predetermined length, the set of inputs comprising a statistical summarization of the array, the algorithm comprising a machine learning algorithm; and
obtaining, by the processing system, a predicted throughput for the cellular network based on the algorithm.

US Pat. No. 10,693,574

METHOD AND APPARATUS FOR EFFICIENT DATA TRANSMISSIONS IN HALF-DUPLEX COMMUNICATION SYSTEMS WITH LARGE PROPAGATION DELAYS

QUALCOMM Incorporated, S...

1. A method of determining a time lag of a return link time reference relative to a forward link time reference in a satellite communication system, the method comprising:determining a minimum round-trip propagation delay of signals between a ground station and a satellite;
determining a transition time for a half-duplex transceiver of the ground station to switch between a transmit mode and a receive mode;
determining a system parameter based on the transition time for the half-duplex transceiver to switch between the transmit mode and the receive mode;
determining the time lag of the return link time reference relative to the forward link time reference by offsetting the system parameter from the minimum round-trip propagation delay; and
scheduling at least one of one or more transmission operations by the satellite or one or more reception operations by the satellite in accordance with the determined time lag,
wherein the scheduling schedules the one or more transmission operations by the satellite on a first of n+k frames and the scheduling schedules the one or more reception operations by the satellite on a second set of n+k frames, where n is greater than or equal to zero,
wherein a leading edge of a frame k in the second set of n+k frames is skewed by the determined time lag at the satellite from a leading edge of a frame k in the first set of n+k frames,
wherein the return link time reference is a return link receiver time reference of the satellite, and
wherein the forward link time reference is a forward link transmitter time reference of the satellite.

US Pat. No. 10,693,573

METHOD FOR LOCATING A TERRESTRIAL TRANSMITTING SOURCE OF AN UNKNOWN SIGNAL

ATOS CONVERGENCE CREATORS...

1. A method for locating a terrestrial transmitting source of a signal which is transmitted from an unknown location of the terrestrial transmitting source via satellite to a terrestrial receiver to resolve satellite interference problems, the method comprising:acquiring data of the signal transmitted from the unknown location of the terrestrial transmitting source and at least one known signal;
comparing a power fluctuation of the signal transmitted from the unknown location of the terrestrial transmitting source with a power fluctuation of the at least one known signal allocated to a known terrestrial transmitting source;
determining a degree of similarity between the power fluctuation of the signal transmitted from the unknown location of the terrestrial transmitting source and the power fluctuation of the at least one known signal;
calculating an estimate of a distance between the terrestrial transmitting source of the signal and the terrestrial transmitting source of the at least one known signal based on the degree of similarity between the power fluctuations of the signal transmitted from the unknown location of the terrestrial transmitting source and the at least one known signal; and
estimating the location of the terrestrial transmitting source of the signal based on positions of the terrestrial transmitting source of the at least one known signal having a highest degree of similarity between the power fluctuations of the signal and the at least one known signal to resolve the satellite interference problems.

US Pat. No. 10,693,572

MEASURING SYSTEM FOR OVER-THE-AIR POWER MEASUREMENTS WITH ACTIVE TRANSMISSION

1. A measuring system for performing over the air power measurements, comprising:a detector module, comprising a detector input,
a transmitter module, comprising a transmitter output, and
an antenna,
wherein the detector input and the transmitter output are within a single housing and are at least temporarily connected,
wherein at least the transmitter output or the detector input are at least temporarily connected to the antenna,
wherein the detector module comprises detector diodes adapted to rectify a signal received by the antenna,
wherein the transmitter module comprises a signal source,
wherein the signal source is adapted to be regulated in a digital manner,
wherein the detector input and the transmitter output are connected by an electrical power coupler,
wherein the antenna is connected to a direct path of the power coupler, and
wherein the power coupler comprises a first coupling path and a second coupling path and whereby the first coupling path and the second coupling path are connected to the detector module.

US Pat. No. 10,693,571

IMAGE GENERATING APPARATUS, COMMUNICATION APPARATUS, ANTENNA ADJUSTMENT METHOD AND IMAGE GENERATING METHOD

NEC CORPORATION, Tokyo (...

1. An image generating apparatus, comprising:hardware, including a processor and memory;
a first image generating unit implemented at least by the hardware and configured to generate a first image showing, in a two-dimensional coordinate system having coordinate axes respectively corresponding to angles of an antenna in two axial directions, reception quality information indicating a quality of a received signal received by the antenna at each of antenna angles, the antenna angles being the angles of the antenna in the two axial directions; and
a second image generating unit implemented at least by the hardware and configured to generate a second image, the second image being a photographed image of a direction in which the antenna faces at the antenna angles, wherein
the first image is used to adjust the antenna angles,
the image generating apparatus further comprises a determination unit implemented at least by the hardware and configured to determine validity of the adjusted antenna angle by using at least the second image, and
when a highest quality indicated in the first image is equal to or larger than a first value, the determination unit determines that the adjusted antenna angles are valid, the first value being determined in advance based on a theoretical value of a quality of a received signal in the antenna.

US Pat. No. 10,693,570

DEVICE AND METHOD OF ANALYZING A RADIO FREQUENCY SIGNAL

1. A device for analyzing a radio frequency signal, comprising:an analyzing module that is configured to analyze input data relating to a multicarrier radio frequency signal with at least two carrier frequencies, said multicarrier analyzing module being further configured to calculate at least one of an optimized intermediate frequency or an optimized local oscillator frequency based on said input data, said multicarrier analyzing module being configured to calculate at least one of said optimized intermediate frequency or said optimized local oscillator frequency automatically.

US Pat. No. 10,693,569

METHOD OF PROVIDING A PHASE REFERENCE, METHOD FOR ESTABLISHING KNOWN PHASE RELATIONSHIPS AS WELL AS PHASE REFERENCE SYSTEM

1. A method of providing a phase reference for a phase-sensitive receiver, with the following steps:generating, by using a first frequency generator, a first generator signal with a first generator frequency;
generating, by using a second frequency generator, a second generator signal with a second generator frequency;
feeding the first generator signal and the second generator signal into a multiplier; and
outputting a first spectral line with a first frequency, a second spectral line with a second frequency and a third spectral line with a third frequency,
the first frequency being equal to a first integer multiple of the first generator frequency, the second frequency being equal to a second integer multiple of the second generator frequency and the third frequency being equal to the sum or the difference of the first frequency and the second frequency.

US Pat. No. 10,693,568

ADAPTING SERDES RECEIVERS TO A UFS RECEIVER PROTOCOL

ADVANTEST CORPORATION, T...

1. An automated test equipment (ATE) system comprising:a computer system comprising a system controller communicatively coupled to a tester processor and a Field Programmable Gate Array (FPGA);
wherein the FPGA is communicatively coupled to the tester processor, and is configured to internally generate commands and data transparently from the tester processor for testing a Device Under Test (DUT); and
wherein the FPGA comprises a transceiver circuit configured to:
receive payload data from the DUT using a first rate of a plurality of line rates during a first burst;
transition to a power saving state at an end of the first burst;
receive synchronization data from the DUT using a second rate of a plurality of line rates during a second burst;
establish synchronization with a clock data recovery (CDR) circuit of the transceiver at the second rate; and
receive payload data from the DUT at the second rate.

US Pat. No. 10,693,567

VEHICLE COMMUNICATION SYSTEM AND METHOD

The Boeing Company, Chic...

1. A spacecraft comprising:a frame including a joint coupling a first frame portion to a second frame portion, wherein the joint is configured to provide relative movement between the first frame portion and the second frame portion; and
an acoustic communication system configured to transfer acoustic data signals across the joint between the first frame portion and the second frame portion;
wherein the joint includes a forced coupling system configured to bias the first frame portion against the second frame portion in a zero gravity environment so as to form an acoustic data transmission conduit from the first frame portion to the second frame portion.

US Pat. No. 10,693,566

WIRELESS JOSEPHSON PARAMETRIC CONVERTER

Yale University, New Hav...

1. A wireless converter for microwave signals comprising:a substrate;
a plurality of first Josephson junctions formed on the substrate and connected in a ring;
a ground plane formed on the substrate adjacent to the ring;
a first antenna formed on the substrate and connected to the plurality of first Josephson junctions; and
a second antenna formed on the substrate, oriented perpendicular to the first antenna, and connected to the plurality of first Josephson junctions,
wherein:
a first half of the first antenna is connected to a first node between two Josephson junctions on a first side of the ring and a second half of the first antenna is connected to a second node between two Josephson junctions on a second side of the ring; and
a first half of the second antenna is connected to a third node between two Josephson junctions on a third side of the ring and a second half of the second antenna is connected to a fourth node between two Josephson junctions on a fourth side of the ring.

US Pat. No. 10,693,565

COMPENSATING FOR ENTANGLEMENT LOSS IN COMMUNICATION LINES

The United States of Amer...

1. A method for compensating for entanglement loss in communication channels in a communication system comprising at least one entangled photon source and at least a first transmission channel and a second transmission channel, the first transmission channel exhibiting a first entanglement loss, the method comprising:providing a compensating loss element in the second transmission channel; and
selecting a compensating polarization dependent loss (PDLcomp) for being provided in the second transmission channel,
wherein the PDLcomp is selected to compensate for at least a portion of the first entanglement loss.

US Pat. No. 10,693,564

PHOTONICS INTERFERENCE CANCELER

Raytheon Company, Waltha...

1. A photonic integrated circuit for performing interference cancellation, comprising:a substrate;
a first terminal for receiving an RF signal;
a second terminal for receiving a reference signal;
a third terminal for outputting an output signal;
a first electro-optic (EO) modulator formed on the substrate, the first EO modulator being coupled to the first terminal, the first EO modulator being configured to modulate the RF signal onto a first optical carrier signal to generate a first modulated signal;
an optical combiner formed on the substrate, the optical combiner being configured to combine a plurality of base signals into a second optical carrier signal, each one of the plurality of base signals having a respective wavelength that is different from the respective wavelengths of the remaining base signals in the plurality, the second optical carrier signal having a different spectral content than the first optical carrier signal;
a second EO modulator that is formed on the substrate, the second EO modulator being coupled to the second terminal and the optical combiner, the second EO modulator being configured to modulate the reference signal onto the second optical carrier signal to generate a second modulated signal, the second modulated signal including a plurality of modulated signal components, each modulated signal component corresponding to a different one of the base signals;
a dispersive element that is formed on the substrate, the dispersive element being coupled to the second EO modulator, the dispersive element being configured to generate a tapped delay line signal by imparting a different respective delay on each of the modulated signal components of the second modulated signal; and
a subtraction element that is formed on the substrate, the subtraction element being coupled to the first EO modulator, the dispersive element, and the third terminal, the subtraction element being configured to subtract the tapped delay line signal from the first modulated signal to generate the output signal.

US Pat. No. 10,693,563

COHERENT OPTICAL RECEIVER

Elenion Technologies, LLC...

1. An apparatus for coherent demodulation of quadrature-modulated (QM) light, the QM light comprising two transmitter signals optically combined in quadrature, the apparatus comprising:an optical quadrature heterodyne receiver configured to receive the QM light and to obtain therefrom two electrical signals;
a phase-sensitive filter circuit configured to detect a heterodyne frequency (HF) tone in each of the two electrical signals so as to preserve a relative phase therebetween; and,
a demodulator circuit configured to decompose the two transmitter signals from the two electrical signals based at least in part on the HF tones to obtain two decomposed transmitter signals.

US Pat. No. 10,693,562

ENCODING DEVICE AND DECODING DEVICE

NIPPON TELEGRAPH AND TELE...

2. An encoding device, comprising:an encoding unit configured to perform an encoding process of inputting N intensity signals (N is an integer greater than or equal to 2) of (M+1) values (M is an integer greater than or equal to 1) and adding (2LM/2) (L is an integer less than or equal to 1 and 2L is less than or equal to N) to an encoded signal having a negative minimum value in a range of the encoded signal among encoded signals of 2L channels of (2LM+1) values obtained by calculating an inner product of a Hadamard matrix of 2L rows and 2L columns and a matrix having elements of 2L intensity signals included in a set for each set of 2L intensity signals and generate encoded signals of N channels;
N digital-to-analog conversion units corresponding to the N channels and configured to convert the encoded signals of the N channels from digital signals into electrical analog signals;
N light sources corresponding to the N channels and configured to output light of wavelengths for use in the N channels;
N light intensity modulation units corresponding to the N channels and configured to intensity-modulate the light output from the N light sources with the encoded signals converted into the electrical analog signals by the N digital-to-analog conversion units; and
a wavelength multiplexing unit configured to output a wavelength-multiplexed signal obtained by wavelength-multiplexing the light intensity-modulated by the N light intensity modulation units.

US Pat. No. 10,693,561

APPARATUS AND METHOD FOR BEAMFORMING COMMUNICATION

Electronics and Telecommu...

1. A transmitting apparatus for beamforming communication, including elements manufactured in a wafer level through a silicon or compound-based photonics process, the transmitting apparatus comprising:an optical modulator configured to modulate polarized or unpolarized input light into a light signal including a carrier signal and a sideband signal based on a radio frequency (RF) signal, having polarization characteristics crossing each other;
an optical power splitter configured to split the light signal into a plurality of light signals obtained by splitting power at an arbitrary splitting rate;
a plurality of light phase shifters configured to respectively shift phases of the plurality of light signals;
a plurality of polarization controllers configured to perform control so that a phase-shifted carrier signal and a phase-shifted sideband signal included in each of the phase-shifted plurality of light signals have the same polarization characteristic;
a plurality of photodetectors configured to convert the plurality of light signals, each including the phase-shifted carrier signal and the phase-shifted sideband signal which are controlled to have the same polarization characteristic, into a plurality of electrical signals; and
a plurality of antenna elements configured to radially transmit the plurality of electrical signals in an RF signal form, respectively.

US Pat. No. 10,693,560

OPTICAL TRANSMITTER, OPTICAL COMMUNICATION SYSTEM, AND OPTICAL COMMUNICATION METHOD

NEC Corporation, Tokyo (...

1. A digital signal processor, comprising:an encoder configured to encode input digital signals by one of a plurality of encoding methods, the one of the plurality of encoding methods corresponding to optical transmission attributes of an optical carrier wave, and output encoded digital signals;
a mapper configured to map the encoded digital signals and output mapped signals; and
a digital analog converter configured to output drive signals to modulate the optical carrier wave based on the mapped signals.

US Pat. No. 10,693,559

SYSTEM AND METHODS FOR CENTRALIZED NETWORK NODE DIGITIZATION

Cable Television Laborato...

1. An access network, comprising:a first local network node configured to serve one or more first client devices according to a first network protocol;
a second local network node configured to serve one or more second client devices according to a second network protocol different than the first network protocol; and
a hub in operable communication with the first and second local network nodes over respective transport media, the hub containing a centralized network node configured to generate a first digitized radio frequency (RF) stream to the first local network node and a second digitized RF stream to the second local network node,
wherein the first digitized RF stream corresponds to the first network protocol and the second digitized RF stream corresponds to the second network protocol.

US Pat. No. 10,693,557

DUAL FIDELITY CONNECTIVITY ON-BOARD A VEHICLE

GOGO LLC, Chicago, IL (U...

13. A dual fidelity access point disposed within a vehicle that includes a plurality of seats having corresponding seatback devices installed thereat, the dual fidelity access point including:one or more transceivers configured to communicate with the plurality of devices via a radio frequency (RF) communication protocol, one or more light emitting diodes (LEDs) configured to emit light in accordance with a light fidelity (LiFi) communication protocol, wherein the emitted light is detected by photo-detectors operatively connected to respective seatback devices;
a bus interface communicatively coupled to a network controller; and
a controller configured to:
obtain, via the bus interface, data packets addressed to devices within a footprint of the dual fidelity access point;
identify data streams associated with the data packets, wherein one or more of the data streams are associated with seatback devices on-board the vehicle; analyze the data streams to determine a metric associated with the one or more data streams; and
based on the metric for a particular data stream associated with a particular seatback device, communicate the data packets that form the particular data stream to the particular seatback device via one of the one or more transceivers or the one or more LEDs.

US Pat. No. 10,693,556

METHOD AND APPARATUS FOR THE DETECTION OF DISTORTION OR CORRUPTION OF CELLULAR COMMUNICATION SIGNALS

Viavi Solutions Inc., Sa...

1. A method for determining the cause of distortion or corruption of signals in a cellular communications network, the cellular communications network including radio equipment and at least one radio equipment controller, and an uplink signal transmission medium and a downlink signal transmission medium interconnecting the radio equipment and the radio equipment controller, the uplink and downlink signal transmission media carrying transport digital data signals, including I (in phase) and Q (quadrature phase) digital data signals relating to cellular communications signals, the cellular communications network further including an equipment monitoring system which generates alarm signals or indicator signals representing abnormal conditions relating to the radio equipment, the method comprising the steps of:receiving one of the alarm or indicator signals from the network equipment monitoring system;
determining from the received one of the alarm or indicator signals a particular radio equipment to monitor;
operatively coupling to selected uplink and downlink signal transmission media relating to the particular radio equipment, and providing the transport digital data signals of the selected uplink and downlink signal transmission media, including the I and Q digital data signals, carried thereby;
extracting the I and Q digital data signals from the transport digital data signals carried by the selected uplink and downlink signal transmission media;
processing the extracted I and Q digital data signals using a Fourier Transform algorithm, and generating therefrom signal spectrum data relating thereto; and
analyzing the signal spectrum data to detect if a signal distortion event has occurred or whether the received one of the alarm or indicator signals was a false alarm.

US Pat. No. 10,693,555

OPTICAL NETWORK FAULTED IDENTIFICATION

BRITISH TELECOMMUNICATION...

1. An optical network node capable of being powered, comprisinga transceiver,
a retro-reflective reflector arranged to reflect an optical signal back to an optical transmitter that is the source of the optical signal, the optical transmitter being located at a head end of a network to which the optical network node belongs, and
a switch arranged to direct the optical signal to the transceiver or the reflector in dependence on whether the optical network node is powered,
wherein the switch is arranged to direct the optical signal to the retro-reflective reflector when the optical network node is unpowered such that the optical signal is reflected back to the optical transmitter that is the source of the optical signal; and
wherein the optical network node is arranged to transmit a power down indication signal, indicating power loss to the optical network node, to the head end to initiate transmission of a test optical signal from the optical transmitter to the optical network node.

US Pat. No. 10,693,554

METHOD FOR COMMUNICATION BETWEEN A GROUND TERMINAL ON THE EARTH'S SURFACE AND A SATELLITE

Airbus Defence and Space ...

1. A method for communication between a ground terminal on Earth's surface and a satellite, wherein the ground terminal and a radio terminal of the satellite are configured for Internet Protocol-based (IP-based) communication, the method comprising:via one or more IP-based protocols, with interposition of a space-based Internet system:
transmitting control commands for one or more modules of the satellite from the ground terminal to the radio terminal, which receives the control commands by radio from the space-based Internet system and forwards the control commands to the one or more modules; and
transmitting module data coming from one or more modules of the satellite from the radio terminal to the ground terminal, wherein the radio terminal transmits the module data by radio to the space-based Internet system;
wherein a flying altitude of the satellite is lower than that of the space-based Internet system;
wherein the satellite comprises a payload comprising a camera system configured for recording images of the Earth's surface;
wherein in the ground terminal a user interface is provided by which a user can affect transmission of the control commands and transmission of the module data; and
wherein the user interface comprises a web browser by which the radio terminal of the satellite is addressable.

US Pat. No. 10,693,553

HYBRID SATELLITE COMMUNICATION SYSTEM FOR COCKPIT, CABIN, AND CREW CONNECTIVITY

Rockwell Collins, Inc., ...

1. A hybrid satellite communication system for cockpit, cabin, and crew connectivity, comprising:a hybrid antenna mountable on an exterior surface of an aircraft, the hybrid antenna comprising:
an L-band antenna; and
a high-throughput antenna configured to operate on at least one of a ku-band or a ka-band; and
a multi-constellation modem manager in communication with the hybrid antenna, the multi-constellation modem manager comprising:
an L-band antenna modem card configured to communicate with the L-band antenna; and
a high-throughput modem card configured to communicate with the high-throughput antenna,
the multi-constellation modem manager being configured for simultaneous operation on multiple satellite constellations by simultaneously communicating via the L-band antenna and the high-throughput antenna.

US Pat. No. 10,693,552

BEAM TRAINING OF A RADIO TRANSCEIVER DEVICE

Telefonaktiebolaget LM Er...

1. A method for beam training of a radio transceiver device, the method being performed by the radio transceiver device, the radio transceiver device comprising at least two antenna arrays, the method comprising:receiving, during the beam training, a first set of occurrences of a reference signal using all the antenna arrays and such that one respective occurrence of the reference signal is received in one single wide beam at each of all the antenna arrays; and
receiving, during the beam training, a second set of occurrences of the reference signal using less than all antenna arrays and such that one respective occurrence of the reference signal is received in each respective narrow beam at each of the less than all antenna arrays,
wherein which of the less than all antenna arrays to receive the second set of occurrences of the reference signal is determined based on evaluation of reception of the first set of occurrences of the reference signal at each of all the antenna arrays,
wherein only a single one of the antenna arrays is used when receiving the second set of occurrences of the reference signal.

US Pat. No. 10,693,551

COMMUNICATION DEVICE AND METHOD USING VIRTUAL SECTOR FORMING

SONY CORPORATION, Tokyo ...

1. A communication device for RF-based communication with another communication device, said communication device comprising:antenna circuitry configured to transmit and receive RF signals, and
beamforming circuitry configured to perform beamforming and to carry out a beam training procedure for finding a beam for use in transmitting and/or receiving RF signals and/or for channel estimation, said beamforming training procedure comprising at least two stages during which training signals are transmitted using different beams, wherein first beams used in a first stage have a larger beam sector than second beams used in a second stage and wherein the second beams are selected by forming a virtual best sector based on an evaluation of a predetermined metric obtained for the first beams in the first stage.

US Pat. No. 10,693,550

ENHANCED CUSTOMER PREMISE EQUIPMENT

RF DSP Inc., Irving, CA ...

1. An enhanced millimeter wave (mmWave) Customer Premise Equipment (EmmCPE) comprisingone or more Base Station (BS) facing antennas (BS-facing antennas) and RF processing circuits to establish a network connection via one or more mmWave wireless links with one or more Base Station (BS);
a local mmWave Customer Premise Equipment module (mmCPE) that uses part of the one or more mmWave wireless links with the one or more Base Station (BS) to provide network services to one or more user equipment (UEs) within the local customer premise where the mmCPE is located;
a Forward Processing Equipment module (FPE) that uses one or more antennas and RF processing circuits to direct one or more mmWave beams to establish mmWave wireless links with other mmCPE(s) or EmmCPE(s) not located at the local customer premise and uses another part of the one or more mmWave wireless links with the one or more Base Station (BS) to provide network connection to the other mmCPE(s) or EmmCPE(s) not located at the local customer premise, and,
a Controller that routes some of the data from the one or more BS to the local mmCPE and some of the data from the one or more BS to the FPE, routes the data from the local UEs via the local mmCPE to the one or more BS, and routes the data from the other mmCPE(s) or EmmCPE(s) not located at the local customer premise via the FPE to the one or more BS, wherein the routing of the data is by the Controller is controlled by the one or more BS.

US Pat. No. 10,693,549

MULTI-FREQUENCY HIGH FREQUENCY DATA LINK

Rockwell Collins, Inc., ...

1. A ground station radio device comprising:a transmitter configured to transmit uplink data to a plurality of aircraft over a first frequency; and
a receiver configured to receive downlink packets from the plurality of aircraft over a plurality of second frequencies that are different from the first frequency, wherein the transmitter transmits an acknowledge, first information and first uplink packets over the first frequency, wherein the first information comprises list of available downlink frequencies for the second frequencies over the first frequency, wherein the acknowledge is provided when a downlink packet successfully received from one of the aircraft.

US Pat. No. 10,693,548

TWO REFERENCE SIGNAL BEAM REPORTING AND IDENTIFICATION

1. A user equipment device, comprising:a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
generating a beam index comprising a first group of signal measurements of a first type of reference signal, and a second group of signal measurements of a second type of reference signal; and
transmitting a report associated with the beam index to a network node device based on a signal measurement of a beam of the first group of signal measurements.

US Pat. No. 10,693,547

SYSTEM AND METHOD FOR BEAM MANAGEMENT

QUALCOMM Incorporated, S...

1. A method of wireless communication by a user equipment (UE), the method comprising:receiving, from a base station, a plurality of first signals, each first signal being associated with synchronization with the base station and each first signal being received on a respective one of a first plurality of beams, wherein the first signals are swept through transmit directions of the first plurality of beams according to a sequence;
determining, before synchronization with the base station, a selected first signal of the plurality of first signals based on the sequence;
synchronizing with the base station based on the selected first signal of the plurality of first signals, wherein other first signals of the plurality of first signals are unused for the synchronization with the base station;
receiving, after the synchronizing with the base station, a plurality of second signals, each second signal comprising a reference signal and each second signal being received on a respective one of a second plurality of beams;
measuring a first value based on at least one second signal of the plurality of second signals;
sending, to the base station, a report indicating the first value; and
communicating with the base station based on the report indicating the first value.

US Pat. No. 10,693,546

APPARATUS AND METHOD FOR SPARSIFYING CHANNEL USING BEAMFORMING

1. A method of sparsifying a channel using beamforming at a transmitting end of a wireless communication system, the method comprising:inserting pilot symbols into resources allocated among resource elements constituting a time-frequency grid;
calculating beamforming weights for sparsifying a beamformed time-domain channel; and
beamforming frequency-domain channels of a plurality of antennas mapping the pilot symbols by using the beamforming weights,
wherein the calculating of the beamforming weights comprises:
performing a discrete Fourier transform on time-domain channel vectors and then applying a relationship between channel gains and antenna indices;
deriving a result of the application as computed values for the time-domain channel vectors and a first matrix; and
deriving the beamforming weights as computed values for a pseudo inverse matrix of the first matrix.

US Pat. No. 10,693,545

DIFFERENT SECTOR ROTATION SPEEDS FOR POST-AMBLE PROCESSING OF A BEAM FORMING PACKET

Apple inc., Cupertino, C...

1. A system, comprising:a first and second wireless communication device, respectively comprising a broadband processor and one or more antenna arrays;
the first wireless communication device, configured to:
provide an indication of a first rotation speed between a plurality of transmission sectors of the one or more antenna arrays at the first wireless communication device of the first wireless communication device as part establishing communications with the second wireless communication device;
transmit a packet to the second wireless communication device, wherein the transmission of a post-amble portion of the packet is performed according to the first rotation speed provided to the second wireless communication device;
the second wireless communication device, configured to:
determine a second rotation speed between reception sectors of the one or more antenna arrays at the second wireless communication device according based on the provided first rotation speed to capture power measurements between individual ones of the reception sectors and the transmission sectors based on the receipt of the post-amble portion of the packet from the first wireless communication device;
rotate between the reception sectors of the one or more antenna arrays at the second wireless communication device according to the second rotation speed;
compare the power measurements to identify one of the reception sectors at one of the one or more antenna arrays at the second wireless communication device with a greatest power measurement; and
transmit a second packet to the first wireless communication device using a transmission sector at one of the one or more antenna arrays at the second antenna array selected according to the identified reception sector.

US Pat. No. 10,693,544

METHODS AND APPARATUS FOR MULTI-FREQUENCY BEAMFORMING

Massachusetts Institute o...

1. A system comprising a beamformer, wherein:(a) the beamformer includes a first set of antennas; and
(b) the beamformer is configured to transmit a first set of wireless signals from the first set of antennas during a period of time, in such a way that
(i) each antenna in the first set of antennas transmits a specific signal in the first set of signals, which specific signal is different than that transmitted by any other antenna in the first set of antennas, at least because the specific signal has a carrier frequency that is different than that of each other signal in the first set of signals;
(ii) the first set of signals has a distribution of carrier frequencies; and
(iii) the distribution of carrier frequencies maximizes peak power received at a spatial position external to the beamformer, which peak power occurs during a subperiod of the period of time, which subperiod occurs while constructive interference of the signals at the spatial position is at a global maximum for the period of time.

US Pat. No. 10,693,543

BEAMFORMING-BASED TRANSMISSION METHOD AND APPARATUS

HUAWEI TECHNOLOGIES CO., ...

1. A beamforming-based transmission method by a terminal, the method comprising:obtaining, from a base station, a first reference signal and a message indicating a quantity M of beamforming vectors needing to be reported by the terminal, wherein the first reference signal is received from N dual-polarized antenna ports of the base station, and wherein M and N each are an integer greater than zero;
estimating downlink channel states on the N dual-polarized antenna ports based on the first reference signal;
selecting m first beamforming codewords based on the downlink channel states and the quantity M of beamforming vectors needing to he reported, wherein m?M; and
feeding back to the base station the m first beamforming codewords and ranks of the downlink channel states.

US Pat. No. 10,693,542

COMMUNICATION APPARATUS, COMMUNICATION METHOD, AND PROGRAM

SONY CORPORATION, Tokyo ...

1. A communication apparatus comprising:a controller configured to measure a terminal-specific reference signal transmitted in a radio resource allocated for a terminal apparatus in units of the radio resource, and transmit information indicating a measurement result of the terminal-specific reference signal,
wherein the controller transmits the information indicating the measurement result in units of the radio resource as information indicating the measurement result in units of a sub-band,
wherein the information indicating the measurement result is a channel state report, and
wherein the controller is configured to transmit the channel state report along with a hybrid automatic repeat-request (HARQ) response to data transmitted in the radio resource including the reference signal.

US Pat. No. 10,693,541

SECTOR SWEEPS FOR ESTABLISHING TWO-WAY DATA COMMUNICATIONS WITH DIRECTIONAL ANTENNAS

APPLE INC., Cupertino, C...

1. One or more non-transitory computer-readable media having instructions that, when executed, cause a User Equipment (UE) to:receive a sequence of base station transmit sector sweep signals from a base station (BS) at the UE, each signal being transmitted to a different transmit sector from a multiple antenna array of the BS;
measure the received base station transmit sector sweep signals;
select a best transmitted signal at the UE based on comparing the measured base station transmit sector sweep signals;
send a sequence of UE transmit sector sweep signals to the base station from the UE, each signal being transmitted to a different transmit sector from a multiple antenna array of the UE;
send an identification of the selected best base station transmit sector sweep signal to the base station;
receive an identification of a selected best UE transmit sector sweep signal from the base station; and
send data to the BS using the identified best UE transmit sector, wherein a defined number of slots are allocated in a superframe for sending the sequence of UE transmit sector sweep signals and wherein sending the sequence of UE transmit sector sweep signals comprises sending the signals in less than all of the defined number of slots.

US Pat. No. 10,693,540

METHOD FOR PERIODICALLY TRANSMITTING UPLINK CONTROL INFORMATION IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS FOR SAME

LG Electronics Inc., Seo...

1. A method for periodically reporting channel state information to a base station based on a linear combination codebook in a wireless communication system, the method comprising:receiving a reference signal from the base station; and
reporting, to the base station, channel state information calculated based on the reference signal,
wherein the channel state information comprises information about a channel quality indicator and a precoding matrix index,
wherein, when a rank calculated based on the reference signal is 2, the precoding matrix index is selected from a subsampled codebook,
wherein a precoding matrix constituting the subsampled codebook comprises a first column vector for a first layer and a second column vector for a second layer, the second column vector being orthogonal to the first column vector,
wherein the information about the precoding matrix index has a 4-bit size and indicates three co-phase coefficients defining the first column vector, and
wherein three co-phase coefficients defining the second column vector are identical to the three co-phase coefficients defining the first column vector.

US Pat. No. 10,693,539

LAYER MAPPING METHOD AND DATA TRANSMISSION METHOD FOR MIMO SYSTEM

LG Electronics Inc., Seo...

1. A method for receiving one or more codewords by a first device supporting Multi-Input Multi-Output (MIMO) scheme, the method comprising:receiving, from a second device, the one or more codewords mapped to one or more layers according to one of first layer mapping combinations and second layer mapping combinations, wherein the first layer mapping combinations are for mapping two codewords, and wherein the second layer mapping combinations are for mapping a single codeword; and
processing the one or more codewords,
wherein the second layer mapping combinations comprise 4 layer mapping combinations for respectively mapping the one of the two codewords to 1 layer, 2 layers, 3 layers, or 4 layers such that all possible layer mapping combinations for transmission of one of the two codewords mapped according to the first layer mapping combinations is included in the second layer mapping combinations.

US Pat. No. 10,693,538

APPARATUS, METHOD AND COMPUTER PROGRAM FOR GENERATING BROADCAST BEAMS

Huawei Technologies Co., ...

1. A method of operating an antenna element array to generate a first broadcast beam and a second broadcast beam, the method comprising:selecting from the antenna element array a first set of dual polarized antenna elements and a third set of dual polarized antenna elements, wherein the antenna element array comprises a plurality of dual polarized antenna elements, each dual polarized antenna element having a first input for a first polarization and a second input for a second polarization, and wherein each of the first set of dual polarized antenna elements and the third set of dual polarized antenna elements is arranged in a different half of the antenna element array;
selecting from the antenna element array a second set of dual polarized antenna elements and a fourth set of dual polarized antenna elements, wherein each of the second set of dual polarized antenna elements and the fourth set of dual polarized antenna elements is arranged in a different half of the antenna element array;
generating the first broadcast beam by feeding a first broadcast beam signal to the first input of each dual polarized antenna element of the first set and to the second input of each dual polarized antenna element of the second set; and
generating the second broadcast beam by feeding a second broadcast beam signal to the first input of each dual polarized antenna element of the third set and to the second input of each dual polarized antenna element of the fourth set, wherein the second polarization is orthogonal to the first polarization.

US Pat. No. 10,693,537

CODEBOOK SUBSET RESTRICTION METHOD

Huawei Technologies Co., ...

1. A field notification method, wherein the method comprises:receiving, by a user equipment, a first field, wherein the first field comprises T1 bits, the first field indicates one or more vectors that are allowed to be used to construct a precoding matrix W in a vector set, the precoding matrix W comprises N rows and R columns, N is greater than R;
determining, by the user equipment and based on the first field, the one or more vectors that are allowed to be used to construct the precoding matrix W in the vector set; wherein
R is equal to 3 or 4, an lth column of the precoding matrix W satisfies:
andl is a non-negative integer smaller than R?1, i is an integer, mi is a non-negative integer smaller than N2O2?1, li is a non-negative integer smaller than ½N1O1?1, N1 and N2 are positive integers and separately represent numbers of antenna ports in different dimensions, O1 and O2 are positive integers separately representing Discrete Fourier Transform (DFT) vector oversampling factors in different dimensions, ?pl is an element of set ?={?0, ?1, . . . , ?S?1}, S is a predefined positive integer, ?l is a complex number of a unit amplitude, T1=N1O1N2O2, the vector set is vector set B, B={b0, b1, . . . , bT2?1}, T2=½N1O1N2O2, a length of each vector in the vector set B is N/4, bit x of the T1 bits corresponds to a vector of vector set B, bit x indicates whether the corresponding vector is allowed to be used to construct the precoding matrix W, bit y of the T1 bits is corresponding to two vectors of vector set B, used to indicate whether the corresponding two vectors can construct the precoding matrix W, x satisfies a condition:
is an even number, y satisfies a condition:is an odd number, x and y are non-negative integers smaller or equal to T1?1, K2=N2O2, bk1 is selected from the one or more vectors that are indicated by the first field.

US Pat. No. 10,693,536

APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING PHASE COMPENSATION REFERENCE SIGNAL

Samsung Electronics Co., ...

1. A method performed by a terminal in a wireless communication system, the method comprising:receiving, from a base station, downlink control information (DCI) including information indicating an association between at least one demodulation reference signal (DMRS) antenna port and at least one phase tracking reference signal (PTRS) antenna port;
identifying a number of a-PTRS antenna port associated with uplink based on the DCI;
identifying a DMRS antenna port associated with uplink based on the DCI;
identifying a PTRS antenna port associated with uplink based on the DCI and the number of PTRS antenna port; and
transmitting, to the base station, a DMRS and a PTRS based on the DMRS antenna port associated with uplink and the PTRS antenna port associated with uplink.

US Pat. No. 10,693,535

PRECODING IN HIGH-ORDER MIMO

Apple Inc., Cupertino, C...

1. An apparatus, comprising:one or more processing elements, coupled to a wireless interface, wherein the one or more processing elements are configured to:
determine rank information specifying a number of layers;
transmit the rank information specifying the number of layers;
determine long-term feedback, wherein the long-term feedback comprises a reference to a first element of a data structure associated with the rank information wherein the long-term feedback relates to a long-term transmit channel correlation between a high-order multiple-input multiple-output (MIMO) transmitter and the apparatus; and
transmit the long-term feedback, wherein the long-term feedback is transmitted substantially less frequently than fast feedback associated with MIMO precoding, wherein the fast feedback is a reference to a precoding matrix based on an estimate of an instance of the transmit channel between the high-order MIMO transmitter and the apparatus.

US Pat. No. 10,693,534

WIRELESS COMMUNICATION DEVICE, WIRELESS COMMUNICATION SYSTEM, WIRELESS COMMUNICATION METHOD, AND COMPUTER-READABLE MEDIUM FOR TRANSMISSION OF TRANSMISSION WEIGHT INFORMATION

SONY CORPORATION, Tokyo ...

1. An electronic device comprisingcircuitry configured to:
control receiving a first reference signal or a second reference signal, the second reference signal being formed by weighting the first reference signal;
determine first transmission weight information and second transmission weight information based on reception of the first reference signal and the second reference signal; and
control transmitting of the first transmission weight information according to a first period and the second transmission weight information according to a second period, the first period being different from the second period,
wherein the second transmission weight information is determined and transmitted after the first transmission weight information is transmitted.

US Pat. No. 10,693,533

GENERATING AND PROCESSING MULTI-USER DATA UNITS FOR WLAN

Huawei Technologies Co., ...

1. A method for generating a multi-user data unit for transmission via a multiple input, multiple output (MIMO) communication channel, the method comprising:generating, at a communication device, a multi-user data unit having a preamble and a data portion, wherein the preamble of the multi-user data unit includes a plurality of training sequences, a first field, and a second field, wherein the preamble of the multi-user data unit is structured such that i) the first field of the preamble precedes the plurality of training sequences, and ii) the plurality of training sequences precedes the second field of the preamble, wherein the plurality of training sequences are to be used by multiple receivers for channel estimation, wherein the first field of the preamble includes a plurality of indications of respective numbers of spatial or space-time streams for respective receivers of the multiple receivers to enable each respective receiver of the multiple receivers to determine a respective set of one or more training sequences, in the plurality of training sequences, that corresponds to the respective receiver, wherein the second field of the preamble includes respective modulation and coding scheme information for the respective receivers of the multiple receivers, and wherein the data portion of the multi-user data unit is to be transmitted using respective modulation and coding schemes for the respective receivers of the multiple receivers; and
transmitting, with the communication device, the multi-user data unit.

US Pat. No. 10,693,532

OPERATION METHOD OF STATION IN WIRELESS LOCAL AREA NETWORK

NEWRACOM, INC., Lake For...

1. An operation method performed in a first station, the method comprising:generating a high efficiency (HE) preamble including first scheduling information of a first plurality of reception stations and second scheduling information of a second plurality of reception stations different from the first plurality of reception stations;
generating a physical layer protocol data unit (PPDU) including a legacy preamble, the HE preamble, and a payload, the payload being after the HE preamble and including a plurality of time domains, the plurality of time domains including a first time domain having a first plurality of data units to be transmitted to the first plurality of reception stations and a second time domain having a second plurality of data units to be transmitted to the second plurality of reception stations; and
transmitting the PPDU using one or more frequency bands,
wherein the first scheduling information includes 1) first resource allocation information indicating a resource in the first time domain allocated to the first plurality of reception stations, and 2) a first station identifier list including identification information for each of the first plurality of reception stations,
wherein the second scheduling information includes 1) second resource allocation information indicating a resource in the second time domain allocated to the second plurality of reception stations, and 2) a second station identifier list including identification information for each of the second plurality of reception stations, and
wherein the first resource allocation information includes a first allocation pattern of the one or more frequency bands, and the second resource allocation information includes a second allocation pattern of the one or more frequency bands.

US Pat. No. 10,693,531

SECURE END-TO-END TRANSPORT THROUGH INTERMEDIARY NODES

Seven Networks, LLC, Mar...

1. A non-transitory computer-readable storage medium storing instructions to be implemented by a first computer having a processor, wherein the instructions, when executed by the processor, cause the first computer to perform steps comprising:receiving a token from an intermediary server; and
transmitting a transaction message comprising payload data to the intermediary server, wherein the payload data is transmitted to a second computer by the intermediary server based on the token and the intermediary server is coupled to the second computer over a mobile network.

US Pat. No. 10,693,530

WIRELESS WIDE AREA NETWORK RADIO FOR A MOBILE TELECOMMUNICATION CELLULAR NETWORK

1. A wireless wide area network (WWAN) radio for a mobile telecommunication cellular network, the WWAN radio comprising:a first WWAN MODEM configured to communicate over the mobile telecommunication cellular network;
a first WWAN transceiver configured to communicate over the mobile telecommunication cellular network, said first WWAN transceiver functionally coupled to the first WWAN MODEM, said first WWAN transceiver including a transmit port and a receive port;
a multi-mode amplifier functionally coupled to the transmit port of the first WWAN transceiver, said multi-mode amplifier configured to communicate standard mode WWAN communications over the mobile telecommunication cellular network; and
a high power port including a high power amplifier, a frequency duplexer, and a high power antenna together configured as a high power duplex chain, the high power amplifier functionally coupled to the multi-mode amplifier, the high power port configured to communicate high power mode WWAN communications over the mobile telecommunication cellular network, the high power mode WWAN communications being at greater transmission power than the standard mode WWAN communications.

US Pat. No. 10,693,528

ANTENNA ARRAY SHARING IN A MULTI-OPERATOR RADIO NODE IN A COMMUNICATIONS SYSTEM

1. A radio node for distributing communications signals in a communications system, comprising:a first signal processing circuit, comprising:
a first downlink input port configured to receive a first downlink communications signal from a first signal source associated with a first service provider; and
a first modem coupled to the first downlink input port, the first modem configured to form a plurality of first downlink signal streams in an individual spectrum of the first service provider and distribute each of the plurality of first downlink signal streams to a respective downlink signal processing output port among a plurality of first downlink signal processing output ports;
a second signal processing circuit, comprising:
a second downlink input port configured to receive a second downlink communications signal from a second signal source associated with a second service provider having a spectrum different than the spectrum of the first service provider;
a second modem coupled to the second downlink input port, the second modem configured to form a plurality of second downlink signal streams in an individual spectrum of the second service provider and distribute each of the plurality of second downlink signal streams to a respective downlink signal processing output port among a plurality of second downlink signal processing output ports; and
a plurality of downlink combiner circuits each comprising a first downlink combiner input port coupled to a first downlink signal processing output port among the plurality of first downlink signal processing output ports, a second downlink combiner input port coupled to a second downlink signal processing output port among the plurality of second downlink signal processing output ports, and a downlink combiner output port coupled to a respective radio-frequency (RF) chain circuit among a plurality of RF chain circuits;
each downlink combiner circuit among the plurality of downlink combiner circuits configured to combine a downlink signal stream among the plurality of first downlink signal streams on the first downlink combiner input port and a downlink signal stream among the plurality of second downlink signal streams on the second downlink combiner input port to generate a combined downlink signal stream on the downlink combiner output port;
the plurality of RF chain circuits each coupled to a downlink combiner output port of a respective downlink combiner circuit among the plurality of downlink combiner circuits and a respective antenna element among a plurality of antenna elements in an antenna array;
each RF chain circuit among the plurality of RF chain circuits configured to receive a respective combined downlink signal stream on the coupled downlink combiner output port, process the combined downlink signal stream into a combined RF downlink signal stream, and distribute the processed combined RF downlink signal stream to the coupled antenna element among the plurality of antenna elements in the antenna array.

US Pat. No. 10,693,527

DISTRIBUTED ANTENNA SYSTEM INCLUDING CREST FACTOR REDUCTION MODULE DISPOSED AT OPTIMUM POSITION

SOLiD, INC., Seongnam-si...

17. A distributed antenna system, comprisingat least one head-end device configured to receive mobile communication signals from a plurality of base stations; and
at least one remote device communicatively coupled to the at least one head-end device,
wherein the at least one remote device is configured to receive the mobile communication signals from the at least one head-end device,
wherein the at least one remote device is remotely disposed and configured to transmit the mobile communication signals to a terminal in service coverage,
wherein the at least one remote device includes:
an equalizer configured to perform an equalizing process of at least one of group delay, ripple, phase and amplitude of the mobile communication signals received from the at least one head-end device, and
a crest factor reduction (CFR) processor that is disposed posterior to the equalizer and performs CFR processing on the equalized signals output from the equalizer.

US Pat. No. 10,693,526

DEVICE AND METHOD FOR WIRELESS COMMUNCATION

ORANGE, Paris (FR)

1. A communication method on a first device, called a terminal, capable of receiving a first message in a radio carrier wave by using electromagnetic wave conduction capacities of a first channel whose medium is the body of a user carrying the terminal and of communicating with a second device over a second wireless channel having a medium distinct from the body of the user, wherein the method comprises the following acts on the terminal:receiving, on the first channel, the first message including at least one first pairing datum originating from the second device when the user enters a proximity of the second device;
establishing a communication session on the second channel with said second device, using said pairing datum;
communicating with said second device only on the second radio channel, independently of reception of data on the first channel.

US Pat. No. 10,693,525

RESONANT CIRCUIT DYNAMIC OPTIMIZATION SYSTEM AND METHOD

TRIUNE IP LLC, Plano, TX...

1. A resonant circuit dynamic optimization system, said system comprising:at least one first antenna configured to receive or transmit at least one electromagnetic signal from or to a second antenna;
at least one variable circuit having at least one non-variable circuit component operatively coupled to said antenna, wherein said variable circuit is configured to modify the power transfer efficiency of said electromagnetic signal by modifying a resonant frequency of the first antenna; and
at least one dynamic adjustment circuit operatively coupled to said circuit component, wherein said variable circuit is configured to adjust an impedance value in response to the dynamic adjustment circuit, and the dynamic adjustment circuit is configured to determine a power transfer efficiency of the first antenna with the second antenna by measuring a signal across the at least one non-variable circuit component.

US Pat. No. 10,693,524

SYSTEM AND METHOD FOR MECHANICALLY-BASED MAGNETIC-FIELD TRANSMITTER

UNIVERSITY OF ILLINOIS, ...

1. A low-frequency magnetic field transmitter, comprising:at least one rotor magnet mounted on an axle, the axle configured to rotate the at least one rotor magnet, wherein the axle being connected to a restoring spring that is configured to return the axle to a default position; and
wherein in response to rotation of the axle, at least one rotor magnet rotates and undergoes angular motion, creating time-periodic oscillation of a magnetic dipole and modulation of a magnetic field.

US Pat. No. 10,693,523

METHOD AND DEVICE FOR TRANSMITTING AND RECEIVING PHYSICAL UPLINK CONTROL CHANNEL BETWEEN USER EQUIPMENT AND BASE STATION IN WIRELESS COMMUNICATION SYSTEM

LG Electronics Inc., Seo...

1. A method for transmitting an uplink control signal by a user equipment (UE) in a wireless communication system, the method comprising:receiving, from a base station, configuration information regarding presence or absence of frequency hopping for transmission of a physical uplink control channel (PUCCH);
determining resource locations of a demodulation reference signal (DM-RS) and uplink control information (UCI), which are included in the PUCCH according to symbol duration of the PUCCH and the presence or absence of the frequency hopping; and
transmitting the PUCCH based on the determined resource locations of the DM-RS and UCI,
wherein based on the symbol duration of the PUCCH being equal to or less than X-symbol duration (where X is a natural number), the resource locations to which the DM-RS and UCI are mapped are configured to vary according to the presence or absence of the frequency hopping, and
wherein based on the symbol duration of the PUCCH being greater than the X-symbol duration (where X is the natural number), the resource locations to which the DM-RS and UCI are mapped are configured to be fixed regardless of the presence or absence of the frequency hopping.

US Pat. No. 10,693,522

METHOD AND DEVICE FOR PERFORMING PUCCH FEEDBACK ON BASIS OF BEAMFORMED CSI RS RESOURCE IN WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method performed by a wireless device in a wireless communication system, the method comprising:receiving, from a base station, a plurality of beamformed channel state information reference signals (CSI-RSs) transmitted through a plurality of beams;
transmitting, to the base station, information for a set of candidate beams which are part of the plurality of beams, on a data channel; and
transmitting, to the base station, a precoding type indicator (PTI) informing a preferred beam among the candidate beams, on a physical uplink control channel (PUCCH),
wherein the preferred beam is determined based on a result of a measurement on the plurality of beamformed CSI-RSs,
wherein a size of the PTI is determined based on a number of the candidate beams, and
wherein each possible bit value of the PTI is mapped to each element of the set of the candidate beams.

US Pat. No. 10,693,521

DEVICES AND METHODS FOR BACKSCATTER COMMUNICATION USING ONE OR MORE WIRELESS COMMUNICATION PROTOCOLS INCLUDING BLUETOOTH LOW ENERGY EXAMPLES

University of Washington,...

1. A device comprising:an antenna configured to receive an incident signal having a carrier frequency;
a modulator; and
a waveform generator, wherein the waveform generator is configured to provide a subcarrier frequency, and wherein the waveform generator is further configured to control the modulator to backscatter the incident signal having the carrier frequency using the subcarrier frequency to provide a backscattered signal to the antenna, the backscattered signal including a bandpass signal in a frequency range associated with a Bluetooth standard, wherein the backscattered signal comprises a packet formatted in accordance with a Bluetooth standard.

US Pat. No. 10,693,520

TRANSMIT ENERGY LEAKAGE CONTROL IN A RECEIVER

Entropic Communications, ...

1. A system, comprising:one or more signal processing circuits comprising a receive path and a transmit path; and
a control circuit that:
generates a receive control signal based on:
leakage between the transmit path and the receive path,
at least one signal applied or generated in the transmit path, and
at least one signal applied or generated in the receive path; and
applies the receive control signal into the receive path to adjust or control processing of received signals.

US Pat. No. 10,693,519

INTERFACE CIRCUIT

NXP USA, Inc., Austin, T...

22. An interface circuit, comprising:an inductive coil having a first, second and third terminal;
wherein the first terminal is coupled to an external interface port;
wherein the second terminal is coupled to a first communication port;
wherein the third terminal is coupled to a second communication port;
wherein the inductive coil is configured to attenuate an equivalent capacitance from at least one of the terminals; and
wherein the inductive coil is configured to extend a bandwidth of at least one of the ports.

US Pat. No. 10,693,518

DEVICE AND METHOD OF VERIFYING PROTECTIVE CASE USAGE

CaseFax Inc., Roseville,...

1. A method, comprising:receiving, by one or more processors over a timeframe, verification information indicating whether a protective case accessory is mounted on a device, wherein the verification information is based on a test output signal generated by one or more sensors of the device in response to an input force generated by an electromechanical transducer of the device;
determining, by the one or more processors, protective case usage information based on the verification information, wherein the protective case usage information indicates whether the protective case accessory protected the device from damage over the timeframe; and
storing, in a memory, the protective case usage information.

US Pat. No. 10,693,517

MOBILE DEVICE CONNECTION APPARATUS

Nite Ize, Inc., Boulder,...

1. A mobile device connection apparatus, comprising:a plate-like piece of material, the plate-like piece of material having electrostatic cling properties, the plate-like piece of material folded onto itself;
a connector, the connector sandwiched between the plate-like piece of material;
wherein the plate-like piece of material is shaped to fit on a back of an electronic device, such that the plate-like piece of material is sandwiched between the back of the electronic device and a case, the plate-like piece shaped and having the electrostatic cling properties, to resist lateral movement in relation to the electronic device while being held to the back of the electronic device from moving in an orthogonal direction in relation to the electronic device.

US Pat. No. 10,693,516

ELECTRONIC DEVICE HAVING ADJUSTABLE ANTENNA SETTINGS

Apple Inc., Cupertino, C...

1. An electronic device having opposing first and second faces, comprising:a housing;
a touch-sensitive display at the first face;
an image sensor at the first face;
a plurality of microphones in the housing that are configured to receive sound and to generate audio signals in response to the sound;
wireless communications circuitry configured to convey radio-frequency signals over a plurality of antennas using antenna settings; and
control circuitry configured to adjust the antenna settings based on sensor data, wherein the sensor data comprises data selected from the group consisting of:
a grip map generated by the touch-sensitive display, and
an angle of arrival of the sound received by the plurality of microphones.

US Pat. No. 10,693,515

METHODS AND APPARATUS FOR REDUCING CELLULAR TELEPHONE RADIATION EXPOSURE

Dugan Patents, LLC, Slee...

1. A system comprising:a mobile telephone operative to communicate directly with a cellular network; and
an application executable on the mobile telephone, the application including computer program code operative to direct the mobile telephone to:
detect the presence of a WiFi network; and
in response to detecting the presence of the WiFi network:
switch the mobile telephone to a low radiation mode by communicating using low radiation emitting communications circuitry and a WiFi communications protocol;
stop communicating directly with a cellular network; and
allow voice communication from the mobile telephone over the WiFi network without communicating directly over a cellular network and using a radiation level that is less than is used to communicate directly over a cellular network using the mobile telephone;
wherein a user of the mobile telephone is not exposed to higher radiation levels used to communicate directly with a cellular tower during voice communication over the WiFi network.

US Pat. No. 10,693,514

WIRELESS AUDIO TRANSMISSION SYSTEM

SHENZHEN FZONE TECHNOLOGY...

1. A wireless audio transmission system, comprising a wireless audio transmitter matched with an audio input device in a plug-in manner and configured to transmit an audio signal, a wireless audio receiver matched with an audio output device in a plug-in manner and configured to receive the audio signal, wherein the audio output device is provided with a first plug-in hole matched with the wireless audio receiver in a plug-in manner, and the audio input device is provided with a second plug-in hole matched with the wireless audio transmitter in a plug-in manner, wherein the wireless audio receiver includes a signal receiving component configured to receive the audio signal and a first plug-in connector signally connected with the signal receiving component and configured to match with the first plug-in hole in plug-in manner so as to transmit the audio signal received by the signal receiving component to the audio input device, and a first housing connected with the first plug-in connector; wherein the first housing is encircled to form a first accommodation cavity which has an opening and is configured to accommodate the signal receiving component, wherein the first plug-in connector is connected with the opening of the first housing.

US Pat. No. 10,693,513

IQ IMBALANCE ESTIMATOR

Imagination Technologies ...

1. An apparatus comprising:an input arranged to receive a signal;
a mixer arranged to mix the received signal with a local oscillator signal and to generate both a first mixer output and a second mixer output; and
correlation logic arranged to generate an IQ amplitude imbalance metric by calculating a correlation of the first and second mixer outputs generated by the mixer;
wherein the mixer is arranged to generate four partial products from the received signal and the local oscillator signal; and
wherein the first and second mixer outputs are generated by combining the four partial products in two different ways.

US Pat. No. 10,693,512

DISTORTION CANCELLATION

Cisco Technology, Inc., ...

1. A method, comprising:receiving a collided signal that includes a first component signal carrying a first packet and a second component signal carrying a second packet;
amplifying and digitizing the collided signal according to a first gain to produce a first digital signal;
extracting a nonlinear interference component of the first packet on the second packet in the collided signal from the first digital signal;
extracting a linear interference component of the first packet on the second packet in the collided signal from the first digital signal;
amplifying the collided signal according to a second gain greater than the first gain to produce a second signal;
removing the nonlinear interference component and the linear component interference from the second signal to produce a de-interfered signal; and
decoding the second packet from the de-interfered signal.

US Pat. No. 10,693,511

WIRELESS USER SIGNAL RECEPTION BASED ON MULTIPLE DIRECTIONS-OF-ARRIVAL

Sprint Communications Com...

1. A method of operating radio circuitry to wirelessly serve User Equipment (UE) with dynamic direction-of-arrival reception, the method comprising:control circuitry determining a primary direction-of-arrival for a user signal and responsively configuring a digital filter for the primary direction-of-arrival;
detection circuitry filtering the user signal with the digital filter configured for the primary direction-of-arrival and recovering user data from the user signal;
the control circuitry determining increased radio noise and responsively reconfiguring the digital filter for multiple directions-of-arrival; and
the detection circuitry filtering a subsequent user signal with the digital filter configured for the multiple directions-of-arrival and recovering additional user data from the subsequent user signal.

US Pat. No. 10,693,510

METHODS AND APPARATUS TO MEASURE EXPOSURE TO BROADCAST SIGNALS HAVING EMBEDDED DATA

The Nielsen Company (US),...

1. An apparatus comprising:a watermark decoder to:
decode a watermark from a media signal, the watermark including a station identifier; and
obtain a transmission frequency of a broadcast signal in response to a query that includes the station identifier;
a receiver to tune to the broadcast signal based on the transmission frequency;
a data decoder to decode data from the broadcast signal tuned by the receiver;
a communication interface to transmit the decoded data to at least one of a remote server or an external device; and
a location detector to determine a location of the apparatus, wherein the query is to include the station identifier and the location of the apparatus.

US Pat. No. 10,693,509

DIGITAL PREDISTORTION WITH POWER-SPECIFIC CAPTURE SELECTION

ANALOG DEVICES INTERNATIO...

1. An apparatus for applying predistortion to an input signal, the apparatus comprising:a capture selector circuit configured to establish boundaries of K ranges of powers in a feedback signal indicative of an output of an electronic component by:
acquiring N trial captures of the feedback signal, where each trial capture includes L samples of the feedback signal, and where each of K, N, and L is an integer equal to or greater than 2,
for each of the N trial captures, determining a power characteristic, and
establishing the boundaries of the K ranges of powers based on the power characteristics determined for the N trial captures, where one of the K ranges includes a highest value of the power characteristics determined for the N trial captures, and one of the K ranges includes a lowest value of the power characteristics determined for the N trial captures; and
an actuator circuit configured to apply a predistortion to at least a portion of the input signal prior to providing the input signal to the electronic component, where the predistortion is based on the boundaries of the K ranges of powers.

US Pat. No. 10,693,508

LOW COMPLEXITY TRANSMITTER STRUCTURE FOR ACTIVE ANTENNA SYSTEMS

1. A first amplifier device, comprising:a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
sending a first output to a measurement component for a first determination, based on the first output, of a first amplification nonlinearity associated with the first amplifier device;
receiving a first pre-distortion signal from a pre-distorter component, wherein the pre-distorter component determined the first pre-distortion signal based on the first amplification nonlinearity; and
applying the first pre-distortion signal to the first amplifier device, wherein the first pre-distortion signal is further applied to a second amplifier device for a second determination of a second amplification nonlinearity associated with the second amplifier device.

US Pat. No. 10,693,507

RECONFIGURABLE RADAR TRANSMITTER

INTERNATIONAL BUSINESS MA...

1. A method, comprising:providing, a device operatively coupled to a processor, a radar waveform signal from a set of radar waveform signals; and
dividing, by the device, a local oscillator signal associated with a first frequency and a first amplitude into a first local oscillator signal and a second local oscillator signal; and
generating, by the device, a radio frequency (RF) signal associated with a second frequency and a second amplitude based on the radar waveform signal, the first local oscillator signal and the second local oscillator signal, wherein a first pulse control waveform is provided to a first RF mixer circuit and a second pulse control waveform is provided to a second RF mixer circuit, wherein the first local oscillator signal comprises an opposite polarity than the second local oscillator signal, and wherein a time span of the RF signal is approximately equal to a difference between a first pulse control width of the first pulse control waveform and a second pulse control width of the second pulse control waveform.

US Pat. No. 10,693,506

ELECTRONIC DEVICE COMPRISING ANTENNA

Samsung Electronics Co., ...

1. An electronic device comprising:a housing;
a communication circuit positioned inside the housing and including a first port for a first frequency band and a second port for a second frequency band;
a first antenna positioned inside the housing or forming a part of the housing;
a second antenna positioned inside the housing or forming a part of the housing;
a test port positioned inside the housing or at least partially exposed through the housing; and
a switching circuit configured to:
vary a connection between the first port and the first antenna, the second antenna, and the test port, and
vary a connection between the second port and the first antenna, the second antenna, and the test port,
wherein switching circuit varies the connections by selectively connecting one or more of the first port or the second port to one or more of the first antenna, the second antenna, or the test port,
wherein the switching circuit includes an opened terminal and the switching circuit is configured to connect the test port to the first antenna or the second antenna through a path extending from the opened terminal.

US Pat. No. 10,693,505

SIGNAL TRANSMISSION APPARATUS

MITSUBISHI ELECTRIC CORPO...

1. A signal transmission apparatus comprising:a sender including a processor to execute a program; and a memory to store the program which, when executed by the processor, performs processes of performing numerical value computation of data signals of a plurality of sequences; and DA converters to convert the signals outputted from the processor to analog signals and to send out the analog signals to a transmission path formed of a plurality of conductors, the number of the DA converters being equal to the number of the data signals of the plurality of sequences; and
a receiver including AD converters to convert the signals received through the transmission path to digital signals, the number of the AD converters being equal to the number of the data signals of the plurality of sequences in the sender; a processor to execute a program; and a memory to store the program which, when executed by the processor, performs processes of reconstructing the data signals of the plurality of sequences from the signals outputted from the AD converters, wherein
the processor of the sender is configured to calculate output signals using a matrix formed of eigenvectors corresponding to transmission eigenmodes in which the signals propagate through the transmission path, and the processor of the receiver is configured to calculate the data signals of the plurality of sequences by inverse of the matrix used by the processor of the sender,
the processor of the sender is configured to multiply a result of adding together two-sequence data signals by a weight coefficient (1??) and allow a resultant as one output data, and to multiply a result of subtracting the data signals from each other by a weight coefficient ? and allow a resultant as other output data, and
the processor of the receiver is configured to multiply the received one output data by a weight coefficient 1/(1??) and multiply the other output data by a weight coefficient 1/?, and to add together the one output data and the other output data and allows a resultant to serve as one data signal out of the two-sequence data signals, and to subtract the one output data and the other output data from each other and allow a resultant to serve as an other data signal.

US Pat. No. 10,693,504

APPARATUSES AND METHODS FOR STAIRCASE CODE ENCODING AND DECODING FOR STORAGE DEVICES

Micron Technology, Inc., ...

1. A method comprising:receiving a codeword at a first syndrome computation circuit and at a second syndrome computation circuit, the codeword comprising a portion of a staircase code;
computing, via the first syndrome computation circuit, a first syndrome for at least a portion of a first component codeword of the codeword and computing, via a second syndrome computation circuit, a second syndrome for at least a portion of a second component codeword of the codeword, wherein responsive to completion of computing the first syndrome for a horizontal step of the staircase code, partially computing the second syndrome of a subsequent step in the staircase code; and
determining a location of one or more erroneous bits in at least one of the first or second component codewords based on the first and second syndromes, respectively.

US Pat. No. 10,693,503

POLAR CODE DECODING APPARATUS AND METHOD

SAMSUNG ELECTRONICS CO., ...

1. A polar code encoding and decoding method comprising:generating a first sub-codeword by polar-encoding a first pre-codeword, the first pre-codeword including first unfrozen bits and first frozen bits, wherein the first unfrozen bits include first data bits and second data bits;
generating a second sub-codeword by polar-encoding a second pre-codeword, the second pre-codeword including second unfrozen bits and second frozen bits, wherein the second unfrozen bits include third data bits and the second data bits;
decoding the first sub-codeword;
decoding the second sub-codeword without reference to the decoding the first sub-codeword; and
only if the decoding of the first sub-codeword is successful and the decoding of the second sub-codeword without reference to the decoding the first sub-codeword is not successful, decoding the second sub-codeword a second time, using the second data bits recovered from the decoding of the first sub-codeword.

US Pat. No. 10,693,502

TRANSMISSION APPARATUS AND METHOD, AND RECEPTION APPARATUS AND METHOD

Panasonic Intellectual Pr...

1. A transmission method comprising:receiving information data blocks to be transmitted;
adding, by a signal processing circuit, at least one known information data block to the information data blocks to generate first data blocks;
error-correction coding, by the signal processing circuit, the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate;
removing, by the signal processing circuit, the at least one known information data block from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate;
modulating, by the signal processing circuit, the second coded data blocks using a modulation scheme to generate a modulated signal, and;
transmitting, from an antenna, the modulated signal, wherein
a number of data blocks included in the at least one known information data block depends on a number of the information data blocks such that the first code rate is fixed regardless of the number of the information data blocks.

US Pat. No. 10,693,501

METHOD AND APPARATUS FOR CONTROLLING INTERLEAVING DEPTH

Samsung Electronics Co., ...

6. A digital communication apparatus with interleaving depth control, comprising:one or more processors configured to:
perform a modulo operation on an initial interleaving depth and a total number of codewords,
in response to a result of the modulo operation excluding “0” and the initial interleaving depth being less than the total number of the codewords,
determine whether a sum of the result of the modulo operation and the initial interleaving depth is less than or equal to a maximum interleaving depth,
apply a first interleaving for (NB?2) interleaving blocks and a second interleaving on codewords for (NB?1)th interleaving block and (NB)th interleaving block when the sum is less than or equal to the maximum interleaving depth, wherein an interleaving depth of the first interleaving is different from an interleaving depth of the second interleaving, and
apply the first interleaving for the (NB?2) interleaving blocks, a third interleaving for (NB?1)th interleaving block, and fourth interleaving for (NB)th interleaving block when the sum is greater than the maximum interleaving depth.

US Pat. No. 10,693,500

SYSTEMS AND METHODS FOR DECODING FORWARD ERROR CORRECTION CODES BASED ON COMPONENT CODES

Duke University, Durham,...

1. A method for decoding forward error correction codes, the method comprising:decoding a plurality of component codes, the plurality of component codes comprising code symbols, for which at least one code symbol is involved in multiple component codes; and
analyzing the decoding of each of the plurality of component codes to generate an outcome, wherein analyzing the decoding of each of the plurality of component codes comprises:
estimating at least one possible error location;
storing information related to the at least one possible error location;
storing state information; and
updating the state information based on: information related to the generated outcome; and a previous version of the state information.

US Pat. No. 10,693,499

APPARATUS AND METHOD FOR LDPC ENCODING SUITABLE FOR HIGHLY RELIABLE AND LOW LATENCY COMMUNICATION

INDUSTRY-ACADEMIC COOPERA...

1. An apparatus for LDPC encoding, the apparatus comprising:a first outer encoding module configured to output a pre-coding bit string by using a portion of information bit strings that are to be encoded;
a second outer encoding module configured to perform repetition and permutation operations for the pre-coding bit string and a remainder of the information bit strings;
a first inner encoding module configured to output a portion of parity bit strings by way of a single parity check operation on bit strings outputted from the second outer encoding module; and
a second inner encoding module configured to output parity bit strings by way of an accumulator operation with the bit strings outputted from the second outer encoding module and the portion of parity bit strings outputted from the first inner encoding module used as input,
wherein the first inner encoding module uses a portion of parity bits outputted from the second inner encoding module as additional input in outputting a remainder of parity bit strings by way of an accumulator operation.

US Pat. No. 10,693,498

PARITY CHECK MATRIX GENERATOR, OPERATING METHOD THEREOF AND ERROR CORRECTION CIRCUIT USING PARITY CHECK MATRIX GENERATED BY THE SAME

SK hynix Inc., Gyeonggi-...

12. An error correction circuit comprising:a parity check matrix generator configured to generate a parity check matrix of a Quasi Cyclic Low Density Parity Check (QC-LDPC); and
a decoder configured to perform a decoding operation on a codeword based on the parity check matrix,
wherein the parity check matrix generator:
stores matrix characteristics of binary cyclic permutation matrices included in a binary parity check matrix of the QC-LDPC code,
generates non-binary cyclic permutation matrices based on the matrix characteristics, and
provides the parity check matrix including the non-binary cyclic permutation matrices to the decoder.

US Pat. No. 10,693,497

DECODING APPARATUS, RECEPTION APPARATUS, ENCODING METHOD AND RECEPTION METHOD

Panasonic Intellectual Pr...

1. A decoding apparatus comprising:input circuitry configured to receive coded data; and
decoding circuitry configured to decode the coded data to obtain decoded data; wherein
the coded data are generated by using an encoding process at an encoding apparatus,
the encoding process includes:
(i) repeatedly-selecting and collecting first packets included in the decoded data to generate at least one second packet;
(ii) dividing at least one third packet included in the decoded data into fourth packets; and
(iii) allocating fifth packets included in the decoded data to respective sixth packets without collecting the first packets or dividing the at least one third packet, and
performing an error correcting encoding on the second packets, the fourth packets, and the sixth packets in accordance with a coding rate selected from a plurality of coding rates to generate parity data.

US Pat. No. 10,693,496

MEMORY SYSTEM WITH LDPC DECODER AND METHOD OF OPERATING SUCH MEMORY SYSTEM AND LDPC DECODER

SK hynix Inc., Gyeonggi-...

13. A method of operating a memory system, comprisinginputting training data from a storage into a trained neural network assembly of a decoder of the memory system;
performing multiple iterations of decoding in the trained neural network assembly, and outputting unsuccessfully decoded data of a last of the multiple iterations;
separating the unsuccessfully decoded data output from the trained neural network assembly into multiple clusters of variable nodes of different degrees in parity and data regions of the unsuccessfully decoded data, the variable nodes in each cluster having one or more degrees unique to that cluster; and
training a plurality of neural networks, each receiving the unsuccessfully decoded data of a corresponding cluster of variable nodes.

US Pat. No. 10,693,495

DATA COLLECTION DEVICE WITH EFFICIENT DATA COMPRESSION

THE BOEING COMPANY, Chic...

1. A method comprising:generating data at a first device;
determining one or more parameters corresponding to a statistical distribution of values based on the data;
generating a frequency-based code using the one or more parameters;
encoding the data based on the frequency-based code to generate compressed data; and
sending the one or more parameters and the compressed data from the first device to a second device, the second device configured to generate the frequency-based code using the one or more parameters in order to decode the compressed data.

US Pat. No. 10,693,494

REDUCING A SIZE OF MULTIPLE DATA SETS

Dell Products L.P., Roun...

1. A method comprising:selecting, by one or more processors, a plurality of data sets;
determining, by the one or more processors, a set of strings that are included in at least two data sets of the plurality of data sets;
selecting, by the one or more processors, a particular string of the set of strings based in part on:
a frequency of occurrence of the particular string; and
a length of the particular string;
associating, by the one or more processors, a reference with the particular string;
replacing, by the one or more processors, each occurrence of the particular string in the plurality of data sets with the reference to create a plurality of modified data sets, wherein the plurality of modified data sets is smaller in size than the plurality of data sets; and
storing, by the one or more processors, the particular string and the associated reference in a table.

US Pat. No. 10,693,493

REDUCING LATCH COUNT TO SAVE HARDWARE AREA FOR DYNAMIC HUFFMAN TABLE GENERATION

INTERNATIONAL BUSINESS MA...

1. An accelerator comprising:an input buffer;
a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer;
a Huffman encoder communicatively coupled to the LZ77 compressor, the Huffman encoder comprising a bit translator; and
an output buffer communicatively coupled to the Huffman encoder.

US Pat. No. 10,693,492

CONTEXT DETERMINATION FOR PLANAR MODE IN OCTREE-BASED POINT CLOUD CODING

BlackBerry Limited, Wate...

1. A method of encoding a point cloud to generate a bitstream of compressed point cloud data representing a three-dimensional location of an object, the point cloud being located within a volumetric space recursively split into sub-volumes and containing points of the point cloud, wherein a volume is partitioned into a first set of child sub-volumes and a second set of child sub-volumes, the first set of child sub-volumes being positioned in a first plane and the second set of child sub-volumes being positioned in a second plane parallel to the first plane, and wherein an occupancy bit associated with each respective child sub-volume indicates whether that respective child sub-volume contains at least one of the points, both the first plane and the second plane being orthogonal to an axis, the method comprising:determining whether the volume is planar based on whether all child sub-volumes containing at least one point are positioned in either the first set or the second set;
entropy encoding in the bitstream a planar mode flag to signal whether the volume is planar, wherein entropy encoding includes determining a context for coding the planar mode flag based, in part, on one or more of:
(a) whether a parent volume containing the volume is planar in occupancy,
(b) occupancy of a neighbouring volume at a parent depth, the neighbouring volume being adjacent the volume and having a face in common with the parent volume, or
(c) a distance between the volume and a closest already-coded occupied volume at a same depth as the volume and having a same position on the axis as the volume;
encoding occupancy bits for at least some of the child sub-volumes; and
outputting the bitstream of compressed point cloud data.

US Pat. No. 10,693,491

RECEIVER FOR A TELECOMMUNICATION SYSTEM

HUAWEI TECHNOLOGIES CO., ...

1. A receiver, comprising:an analog baseband (ABB) filter stage including an ABB filter stage input configured to receive an analog baseband (BB) signal and an ABB filter stage output configured to provide a filtered analog BB signal;
an analog-to-digital converter (ADC) stage, including:
an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal;
an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital (A/D) conversion of the ADC input signal to derive the digital BB signal; and
a summation node at the ADC stage input;
a first feedback path configured to feedback the ADC input signal to the ABB filter stage;
a second feedback path configured to feedback the digital BB signal to the ABB filter stage comprises a first feedback digital to analog (D/A) converter; and
a third feedback path configured to feedback the digital BB signal to the summation node at the ADC stage input, wherein the third feedback path comprises a second feedback D/A converter.

US Pat. No. 10,693,490

SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER AND OPERATION METHOD THEREOF

Faraday Technology Corp.,...

1. A Sigma-Delta (?-?) analog-to-digital converter, comprising:a ?-? modulator, having an input terminal for receiving an analog signal, and configured to convert the analog signal into a digital signal according to a feedback signal;
a dynamic element matching circuit, coupled to the ?-? modulator to receive the digital signal, and configured to perform at least one dynamic element matching algorithm on the digital signal to generate the feedback signal, and provide the feedback signal to the ?-? modulator; and
a control circuit, coupled to the ?-? modulator to receive the digital signal, wherein the control circuit listens to the digital signal to detect a mute period, and the control circuit disables the dynamic element matching circuit during the mute period to suspend a progress of the at least one dynamic element matching algorithm.

US Pat. No. 10,693,489

CIRCUIT AND METHOD FOR DIGITAL-TO-ANALOG CONVERSION USING THREE-LEVEL CELLS

Samsung Electronics Co., ...

1. A circuit for digital-to-analog conversion using a plurality of 3-level cells mutually independently providing positive electricity, negative electricity or floating, the circuit comprising:a preprocess circuit configured to receive thermometer code data generated from signed binary data and generate, from the thermometer code data, a shift count for shifting a cell pointer pointing to one of the plurality of 3-level cells for dynamic element matching (DEM); and
a shift circuit configured to store the cell pointer and shift the cell pointer according to the shift count, wherein
the cell pointer is shifted in proportion to an absolute value of the signed binary data in a direction depending on a sign of the signed binary data.

US Pat. No. 10,693,488

DIGITALIZATION DEVICE

DENSO CORPORATION, Kariy...

1. A digitalization device configured to output predetermined analog information as a digital value, the digitalization device comprising:a first pulse delay unit that includes a plurality (2n?(2m?1)) of first delay units connected in series, and outputs a first signal corresponding to a numerical number of the first delay units through which a first pulse signal passes;
a second pulse delay unit that includes a plurality (2n+(2m?1)) of second delay units connected in series, and outputs a second signal corresponding to a numerical number of the second delay units through which a second pulse signal passes; and
an addition output unit that outputs, as the digital value, an addition value obtained by adding a first numerical value based on a first output from the first pulse delay unit and a second numerical value based on a second output from the second pulse delay unit, wherein:
n and m are natural numbers; and
n?m.

US Pat. No. 10,693,487

SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND OPERATION METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A successive approximation register (SAR) analog-to-digital converter (ADC) operating in a sampling phase or in a comparison and switching phase to convert an analog input signal into a digital code, comprising:a switch-capacitor digital-to-analog converter (DAC) comprising a plurality of capacitors, and configured to sample the analog input signal in the sampling phase;
a comparator, coupled to the switch-capacitor DAC, and configured to compare outputs of the switch-capacitor DAC in the comparison and switching phase to generate a plurality of comparison results;
a successive approximating register (SAR), coupled to the comparator, and configured to store the comparison results, wherein the digital code is made up of the comparison results; and
a control circuit, coupled to the SAR, and configured to switch terminal voltages of a part of the capacitors according to the comparison results in the comparison and switching phase, and to switch terminal voltage(s) of at least one target capacitor among the capacitors according to a data in the sampling phase.

US Pat. No. 10,693,486

ASYNCHRONOUS SAR ADC WITH ADAPTIVE TUNING COMPARATOR

AVAGO TECHNOLOGIES INTERN...

1. A successive approximation analog-to-digital converter for converting an analog input signal to a digital output, the successive approximation analog-to-digital converter comprising:a digital-to-analog converter;
a comparator with adjustable integration time electrically coupled to the digital-to-analog converter; and
control circuitry electrically coupled to the digital-to-analog converter and the comparator, the control circuitry configured to adjust an integration time of the comparator, one or more times during a conversion cycle, to be longer for a least significant bit than for a most significant bit.

US Pat. No. 10,693,485

ADAPTIVE BACKGROUND ADC CALIBRATION

AVAGO TECHNOLOGIES INTERN...

1. An electronic device comprising:an analog-to-digital converter circuit configured to receive an input signal;
an adaptive filter circuit coupled to a digital output of the analog-to-digital converter circuit, the adaptive filter circuit configurable to correct one or more circuit impairments in the analog-to-digital converter circuit;
a training signal generator circuit coupled to the analog-to-digital converter circuit and the adaptive filter circuit, the training signal generator circuit configured to generate at least one training signal, the analog-to-digital converter circuit configured to add one of the at least one training signals to the input signal, and the adaptive filter circuit configured to use one of the at least one training signals to adjust one or more adaptive filter coefficients; and
an amplitude detector circuit coupled to the training signal generator circuit and the adaptive filter circuit and configured to receive the input signal and cause the training signal generator circuit to suspend generation of the at least one training signal and cause the adaptive filter circuit to suspend adaptation of the one or more adaptive filter coefficients when the input signal is above a predetermined threshold.

US Pat. No. 10,693,484

PIPELINED ANALOG-TO-DIGITAL CONVERTER CALIBRATION

AVAGO TECHNOLOGIES INTERN...

1. A method for calibrating a pipelined analog-to-digital converter (ADC) comprising:reading a first output level from a first sub-ADC;
reading one or more additional output levels from one or more additional sub-ADCs;
combining the one or more additional output levels from the one or more additional sub-ADCs into a combined output level; and
adjusting a comparator threshold of the first sub-ADC when the first output level and the combined output level meet a set of predetermined conditions,
wherein the comparator threshold of the first sub-ADC is reduced when the combined output level is above a first predetermined level and the first output level is below a second predetermined level and wherein the comparator threshold of the first sub-ADC is increased when the combined output level is below a third predetermined level and the first output level is above a fourth predetermined level.

US Pat. No. 10,693,483

ADAPTIVE TOGGLE NUMBER COMPENSATION FOR REDUCING DATA DEPENDENT SUPPLY NOISE IN DIGITAL-TO-ANALOG CONVERTERS

ANALOG DEVICES INTERNATIO...

1. A digital-to-analog converter (DAC) system, comprising:a first plurality of DAC units;
a second plurality of DAC units, where each DAC unit of the first plurality of DAC units and the second plurality of DAC units is configured to operate in one of two states to convert digital samples to analog values; and
a controller configured to:
select one or more DAC units of the first plurality of DAC units and the second plurality of DAC units to operate in a first state of the two states during conversion of a second digital sample to a second analog value,
operate the one or more DAC units in the first state during conversion of the second digital sample, and
operate unselected DAC units of the first plurality of DAC units and the second plurality of DAC units in a second state of the two states during conversion of the second digital sample;
wherein the one or more DAC units are selected so that a number of DAC units of the first plurality of DAC units and the second plurality of DAC units that switch from operating in the first state during conversion of a first digital sample to a first analog value to operating in the second state during conversion of the second digital sample and that switch from operating in the second state during conversion of the first digital sample to operating in the first state during conversion of the second digital sample is equal to a target toggle number, where the first digital sample and the second digital sample are consecutive digital samples of an input signal to the DAC system.

US Pat. No. 10,693,482

TIME-TO-VOLTAGE CONVERTER WITH EXTENDED OUTPUT RANGE

Silicon Laboratories Inc....

1. An apparatus comprising:a first voltage reference node;
a second voltage reference node; and
a time-to-voltage converter comprising:
a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period,
wherein the shifted reset voltage level is outside a voltage range of the voltage on the output node defined by a first power supply voltage level on the first voltage reference node and a second power supply voltage level on the second voltage reference node.

US Pat. No. 10,693,481

TIME-TO-DIGITAL CONVERTER AND DIGITAL PHASE LOCKED LOOP

Huawei Technologies Co., ...

1. A time-to-digital converter, comprising:N stages of converting circuits connected in series, wherein N2, and N is an integer;
each stage of the converting circuits includes a first delayer and an arbiter, wherein
a first delayer in a first stage of the converting circuits is configured to receive a reference signal, an input end of the first delayer in each stage of the converting circuits other than the first stage of the converting circuits is coupled to an output end of a first delayer in a previous stage of the converting circuits, and an output end of the first delayer in each stage of the converting circuits is configured to output a delayed signal of each stage of the converting circuits;
the arbiter in each stage of the converting circuits is configured to:
receive a sampling clock of each stage of the converting circuits and the delayed signal of each stage of the converting circuits, and
compare the sampling clock with the delayed signal to obtain an output signal of each stage of the converting circuits, wherein the sampling clock of each stage of the converting circuits is derived from a clock signal; and
the first delayer in each stage of the converting circuits includes at least one first delay cell circuit, wherein a quantity of the first delay cell circuits included in the first delayer in the first stage of the converting circuits is 1, and wherein a quantity of the first delay cell circuits included in the first delayer in a jth stage of the converting circuits is 2j-2, wherein j=2, 3 . . . N, and wherein a delay time of each first delay cell circuit is a first time unit.

US Pat. No. 10,693,480

PLL WITH LOCK-IN FREQUENCY CONTROLLER

1. A phase-locked loop (PLL), comprising:a phase predictor;
a phase subtractor; and
a frequency comparator configured to output a signal related to a difference between a target frequency and an oscillator frequency by capturing an initial phase and observing a change in phase difference relative to a difference between a measured phase and a predicted phase based on the initial phase;
wherein the frequency comparator is active during a lock-in period.

US Pat. No. 10,693,479

PHASE ACCUMULATOR WITH IMPROVED ACCURACY

1. A phase-locked loop (PLL) including a phase accumulator, comprising:a counter configured to count cycles of a controlled-oscillator clock signal, wherein a counter output sequence changes in only one bit per counted controlled-oscillator clock signal cycle; and
first latches coupled with a counter output and configured to sample and store a counter output value upon receiving a reference clock signal, the counter value representing an integer output phase.

US Pat. No. 10,693,478

CLOCK GENERATION SYSTEM AND METHOD HAVING TIME AND FREQUENCY DIVISION ACTIVATION MECHANISM

REALTEK SEMICONDUCTOR COR...

1. A clock generation system having a time and frequency division activation mechanism comprising:a clock source processing circuit configured to generate a primary clock signal; and
a plurality of clock-branching circuits that perform a clock-branching generation procedure respectively in an order each comprising:
a frequency division unit, during the clock-branching generation procedure, configured to receive the primary clock signal to divide a frequency of the primary clock signal according to a divisor number and output a branch clock signal; and
a processing unit configured to control the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over the time period from an initial divisor number larger than one to a final divisor number after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.

US Pat. No. 10,693,477

VOLTAGE-TO-CURRENT CONVERTER CIRCUIT

Apple Inc., Cupertino, C...

1. An apparatus, comprising:a coarse-tuning circuit configured to generate, based on a reference voltage level, a coarse-tuning current;
a fine-tuning circuit that includes:
a first current mirror circuit coupled to a power supply signal and configured to mirror a first initial current to generate a first current, wherein the first initial current is generated using a voltage level of a control signal and a first value of a first variable resistor; and
a second current mirror circuit coupled to a ground signal and configured to mirror a second initial current to generate a second current, wherein the second initial current is generated using the voltage level of the control signal and a second value of a second variable resistor;
wherein the fine-tuning circuit is configured to generate a fine-tuning current using the first current and the second current; and
an oscillator circuit configured to generate a clock signal whose frequency is based on a combination of the coarse-tuning current and the fine-tuning current.

US Pat. No. 10,693,476

SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a crystal resonator;
an oscillation circuit that oscillates the crystal resonator and outputs a frequency signal;
a variable load capacity circuit including 1) a plurality of load capacity elements coupled in parallel with each other and coupled to one end of the crystal resonator and 2) a plurality of switches that are respectively serially coupled to the load capacity elements;
a temperature sensor that detects a temperature of the crystal resonator and generates temperature information based on the detected temperature of the crystal resonator; and
a switch control unit that controls ON/OFF of the switches based on the temperature information,
wherein, when the temperature information that is used as an index of frequency deviation of the frequency signal due to a change in the temperature of the crystal resonator falls outside a predetermined allowable range, the switch control unit changes a number of switches to be turned ON among the plurality of switches to allow an absolute value of the frequency deviation to be small.

US Pat. No. 10,693,475

GRADUAL FREQUENCY TRANSITION WITH A FREQUENCY STEP

Silicon Laboratories Inc....

1. A method for generating a clock signal by a phase-locked loop comprising:generating a phase difference signal based on an input clock signal and a feedback clock signal; and
generating a loop filter output signal, wherein in a first mode of operation, the loop filter output signal is generated based on the phase difference signal and a predetermined frequency slope limit, the clock signal being generated based on the loop filter output signal.

US Pat. No. 10,693,474

PLL FILTER HAVING A CAPACITIVE VOLTAGE DIVIDER

Infineon Technologies AG,...

1. A phase-locked loop (PLL), comprising:a detector configured to generate an error signal based on a difference between a reference signal and an output signal;
a charge pump configured to generate current pulses based on the error signal;
a loop filter configured to generate a control voltage based on the current pulses; and
a voltage-controlled oscillator (VCO) configured to generate the output signal at a frequency which is a function of the control voltage,
wherein the loop filter comprises a capacitive voltage divider configured to reduce the control voltage from a range that falls within a voltage domain of the charge pump to a range that falls within a voltage domain of the VCO,
wherein the voltage domain of the charge pump is greater than the voltage domain of the VCO.

US Pat. No. 10,693,473

MULTI-MODAL DATA-DRIVEN CLOCK RECOVERY CIRCUIT

KANDOU LABS, S.A., Lausa...

11. A method comprising:configuring at least one local oscillator of a plurality of local oscillators using a respective local oscillator control signal formed based on outputs of a plurality of multi-input comparators (MICs) connected to a plurality of wires of a multi-wire bus;
selectively configuring the plurality of MICs to (i) generate a plurality of orthogonal sub-channel outputs in a first mode by configuring at least one MIC to compare a set of at least three signals received via respective wires of the multi-wire bus, and (ii) to generate a set of non-return-to-zero (NRZ) outputs in a second mode by configuring a subset of the plurality of MICs to compare signals received on respective pairs of wires of the multi-wire bus;
generating, in the first mode, a plurality of data-driven phase-error signals based on the plurality of orthogonal sub-channel outputs and forming a composite phase-error signal by combining the plurality of data-driven phase-error signals, the composite phase-error signal provided to a local oscillator of the plurality of local oscillators; and
generating, in the second mode, a respective local oscillator control signal for each NRZ output of the set of NRZ outputs, and providing each respective local oscillator control signal to a respective local oscillator of the plurality of local oscillators.

US Pat. No. 10,693,472

METHOD AND APPARATUS FOR GENERATING CLOCK

SAMSUNG ELECTRONICS CO., ...

1. A clock generation apparatus comprising:a pulse generator configured to generate a pulse signal and a selection signal using a reference clock signal;
a delay line circuit configured to select, as an input signal to a delay path, the pulse signal or a fed back portion of a delay clock signal at an output of the delay path, the selection being based on the selection signal, and thereby generate the delay clock signal;
a switch configured to switch, based on a switch control signal, a first voltage or a second voltage to the delay line circuit for operation thereof, wherein the first voltage further provides power to the pulse generator, and the second voltage is generated based on a phase difference between the reference clock signal and the delay clock signal; and
a controller configured to generate the switch control signal based on a frequency of the delay clock signal.

US Pat. No. 10,693,471

DIGITAL PHASE LOCKED LOOP FOR LOW JITTER APPLICATIONS

INTERNATIONAL BUSINESS MA...

1. A phase locked loop circuit, comprising:a feedback path connecting an output of an oscillator to a digital path and an analog path, wherein the oscillator includes oscillator elements configured in rows and columns;
a plurality of varactors in connection with each other and with each row of the plurality of rows, wherein each column of the oscillator elements is connected to a respective varactor of the varactors, wherein a digital tuning signal and an analog tuning signal modify a frequency of the output of the oscillator simultaneously by increasing a voltage of the analog tuning signal which provides a corresponding shift in the frequency of the output of the oscillator by selectively activating the varactors, and increasing the frequency of the output of the oscillator linearly at any voltage of the digital tuning signal, and a capacitance of the varactors increases due to the voltage of the analog tuning signal, thereby decreasing the frequency of the oscillator;
a linear phase detector which receives a reference signal that provides a periodic input for the oscillator and a feedback signal from the feedback path and outputs up and down pulses in response to the reference signal and the feedback signal; and
a gain device comprising a resistor and at least one capacitor in series with the resistor, the at least one capacitor being directly charged and discharged by the up and down pulses to generate the analog tuning signal,
wherein the digital tuning signal selectively activates and deactivates the rows of the oscillator elements to dynamically control a fill factor of the oscillator.

US Pat. No. 10,693,470

DUAL MODE POWER SUPPLY FOR VOLTAGE CONTROLLED OSCILLATORS

Futurewei Technologies, I...

1. An oscillator system, comprising:a voltage controller oscillator (VCO) configured to generate an output waveform having an amplitude based on an input voltage;
a reference generator configured to provide a reference value;
an automatic gain control loop configured to receive the output waveform, determine an indication of the amplitude of the output waveform, and generate a difference between the reference value and the indication of the amplitude of the output waveform, the automatic gain control loop comprising:
a source follower circuit configured to supply the input voltage to the VCO; and
a low pass filter configured to filter the input voltage before the input voltage is supplied to the source follower circuit; and
a controller configured to operate the oscillator system in both a first mode and a second mode:
the controller, when operating in the oscillator system in the first mode, configures the automatic gain control loop to provide the input voltage based on the difference and is configured to determine a second mode input voltage value based on monitoring the provided input voltage; and
the controller, when operating in the oscillator system in the second mode, is configured to provide the second mode input voltage value as the input voltage.

US Pat. No. 10,693,469

MULTIPLIER-ACCUMULATOR CIRCUIT, LOGIC TILE ARCHITECTURE FOR MULTIPLY-ACCUMULATE, AND IC INCLUDING LOGIC TILE ARRAY

Flex Logic Technologies, ...

1. An integrated circuit comprising:a plurality of multiply-accumulator circuitry, connected in a concatenation architecture, to perform a plurality of multiply and accumulate operations, wherein each multiply-accumulator circuitry includes:
memory to store a plurality of multiplier weight data;
a first MAC circuit, connected to the memory to receive first multiplier weight data, including:
a multiplier to multiply first data by a first multiplier weight data and generate a first product data, and
an accumulator, coupled to the multiplier of the first MAC circuit, to add first input data and the first product data to generate first sum data, and
a second MAC circuit, connected to the memory to receive second multiplier weight data, including:
a multiplier to multiply second data by a second multiplier weight data and generate a second product data, and
an accumulator, coupled to the multiplier of the second MAC circuit and the accumulator of the first MAC circuit, to add the first sum data and the second product data to generate second sum data; and
a first load-store register, coupled to an output of the accumulator of the second MAC circuit, to temporarily store the second sum data.

US Pat. No. 10,693,468

INTEGRATED CIRCUIT AND PROCESS FOR FAMILY OF DIGITAL LOGIC FUNCTIONS

Texas Instruments Incorpo...

1. A digital logic integrated circuit comprising:(a) a substrate of semiconductor material having a core area and a peripheral area;
(b) bond pads, including an output bond pad, formed in the peripheral area;
(c) leads formed on the substrate, the leads including an output lead coupled to the output bond pad;
(d) a first independent digital logic circuit having a first logical function, the first independent digital logic circuit having a functional output;
(e) a second independent digital logic circuit having a second logical function different than the first logical function, the second independent digital logic circuit having a functional output; and
(e) conductive material coupling the functional output of the first independent digital logic circuit to the output lead, and the conductive material not coupling the functional output of the second independent digital logic circuit to the output lead.

US Pat. No. 10,693,467

SWITCH CIRCUIT, SEMICONDUCTOR DEVICE USING SAME, AND SWITCHING METHOD

NEC CORPORATION, Tokyo (...

1. A switch circuit comprising:a plurality of four-terminal switches in each of which two switches each including a variable-resistance element and a rectifier element being connected in series, each of the variable-resistance element and the rectifier element including two terminals, are connected at the terminals on the series connections;
an input line and an output line each connected to the terminal of the variable-resistance element in the two switches, the terminal being separate from the terminal on the series connection, a number of at least one of the input line and the output line being more than one; and
a control line each connected to the terminal of the rectifier element in the two switches, the terminal being separate from the terminal on the series connection, wherein,
out of the variable-resistance elements in a plurality of the four-terminal switches out of the four-terminal switches connected to one of the input line and the output line, the control line turns on or off, with the input line and the output line, a group of the variable-resistance elements connected to the input line and a group of the variable-resistance elements connected to the output line, sequentially for each group.

US Pat. No. 10,693,466

SELF-ADAPTIVE CHIP AND CONFIGURATION METHOD

1. A self-adaptive chip, comprising:a plurality of dynamically reconfigurable cells arranged in an array, each of the plurality of dynamically reconfigurable cells being capable of being dynamically reconfigured as needed to execute different operating functions and/or input-output control functions,
wherein each of the plurality of dynamically reconfigurable cells is connected to multiple neighboring dynamically reconfigurable cells to directly acquire data from one or more of the multiple neighboring dynamically reconfigurable cells and to output an operation result, generated from the data, directly to at least one neighboring dynamically reconfigurable cell;
wherein each of the plurality of dynamically reconfigurable cells comprises an arithmetic logic time cell, the arithmetic logic time cell being configured to perform operations comprising an arithmetic operation, a logical operation, an empty operation, and counting, and
wherein each of the plurality of dynamically reconfigurable cells is connected to six to eight neighboring dynamically reconfigurable cells.

US Pat. No. 10,693,465

COUNT VALUE GENERATION CIRCUIT, PHYSICAL QUANTITY SENSOR MODULE, AND STRUCTURE MONITORING DEVICE

Seiko Epson Corporation, ...

1. A count value generation circuit comprising:a first counter that counts edges of a reference signal in synchronization with an input signal to generate a first reference signal count value, the input signal being input to the first counter as a frequency modulation signal;
a time digital value generator that generates a time digital value corresponding to a phase difference between the reference signal and the input signal;
a count integrated value combiner that combines an integer multiple of the first reference signal count value and the time digital value; and
a count value generator that generates a count value in response to a difference between a first output value and a second output value, the first and second output values being temporally continuously output from the count integrated value combiner, the first output value being output prior to the second output value from the count integrated value combiner.

US Pat. No. 10,693,464

CONFIGURABLE LINEAR ACCELERATOR

Varex Imaging Corporation...

1. A system, comprising:a particle power source configured to generate a particle power signal including a particle power pulse having a particle power pulse timing;
a radio frequency (RF) power source configured to generate an RF power signal including an RF power pulse having an RF power pulse timing;
a particle source configured to generate a particle beam pulse in response to the particle power pulse;
a RF source configured to generate an RF signal pulse in response to the RF power pulse;
an accelerator structure configured to accelerate the particle beam pulse in response to the RF signal pulse; and
control logic coupled to the particle power source and the RF power source, wherein the control logic is configured to:
receive a pulse message;
activate the particle power source to generate the particle power pulse in response to the pulse message; and
activate the RF power source to generate the RF power pulse in response to the pulse message;
wherein the control logic is configured to activate the particle power source and the RF power source such that a difference between the particle power pulse timing and the RF power pulse timing is based on the pulse message.

US Pat. No. 10,693,463

LINE DRIVER APPARATUS WITH COMBINED FEED-THROUGH CAPACITANCE AND FEED-FORWARD EQUALIZATION

LATTICE SEMICONDUCTOR COR...

1. An apparatus comprising:a capacitive feed-through module including
a first pre-driver operable to receive input differential signals and delayed signals of the input differential signals, generate first drive signals from the input differential signals and the delayed signals, and equalize the first drive signals, wherein the first pre-driver comprises:
a first transistor; and
a first pulse generator configured to receive one of the input differential signals and generate a first pulse signal to drive the first transistor, and
a capacitance reducing module arranged between the first pre-driver and transmission lines and operable to reduce parasitic capacitance at the transmission lines in response to the first drive signals, wherein the capacitance reducing module is connected to the first transistor; and
a driving module coupled to the transmission lines and operable to generate output differential signals from the input differential signals for transmission on the transmission lines.

US Pat. No. 10,693,462

GROUND INTERMEDIATION FOR INTER-DOMAIN BUFFER STAGES

SHENZHEN GOODIX TECHNOLOG...

1. A ground intermediating buffer circuit comprising:a ground input node configured to couple with a first ground signal, the first ground signal being at a ground reference of a first circuit domain and comprising a input quantity of ground noise during operation of the first circuit domain;
a ground output node configured to couple with a second ground signal, the second ground signal being at a ground reference of a second circuit domain and comprising a output quantity of ground noise during operation of the second circuit domain;
a buffer input node configured to couple with a data signal output of the first circuit domain;
a buffer output node configured to couple with a data signal output of the second circuit domain;
a ground intermediator circuit configured to generate an intermediated ground, responsive to the ground input node and the ground output node, to have a third quantity of ground noise between the input and output quantities of ground noise; and
a signal buffer circuit configured, responsive to receiving an input data signal at the buffer input node, to generate an output data signal on the buffer output node referenced to the intermediated ground.

US Pat. No. 10,693,461

POWER SWITCH CIRCUIT CAPABLE OF REDUCING LEAKAGE CURRENT

eMemory Technology Inc., ...

1. A power switch circuit comprising:an output terminal configured to output an output voltage;
a voltage selection unit configured to receive a first variable voltage and a second variable voltage, and output a greater one of the first variable voltage and the second variable voltage as an operation voltage;
a first level shift circuit coupled to the voltage selection unit, and configured to output a first control signal according to a first input signal;
a second level shift circuit coupled to the voltage selection unit, and configured to output a second control signal according a second input signal;
a first transistor having a first terminal configured to receive the first variable voltage, a second terminal coupled to the output terminal of the power switch circuit, and a control terminal coupled to the first level shift circuit for receiving the first control signal;
a second transistor having a first terminal configured to receive the second variable voltage, a second terminal coupled to the output terminal of the power switch circuit, and a control terminal coupled to the second level shift circuit for receiving the second control signal; and
a first leakage control unit having a first terminal coupled to the first terminal of the first transistor and/or the first terminal of the second transistor, a second terminal coupled to the control terminal of the second transistor, and a control terminal configured to receive the operation voltage, the first leakage control unit being configured to establish an electrical connection between the first terminal and the second terminal of the first leakage control unit according to the operation voltage.

US Pat. No. 10,693,460

FUSE ADJUSTABLE OUTPUT DRIVER

Micron Technology, Inc., ...

1. An apparatus comprising:an output node;
pull-up circuitry comprising a pull-up transistor coupled between a first voltage node and a first intermediate node and a first resistor coupled between the first intermediate node and the output node;
pull-down circuitry comprising a pull-down transistor coupled between a second voltage node and a second intermediate node and a second resistor coupled between the second intermediate node and the output node;
a first configurable resistor coupled between the output node and one of either the first intermediate node or the second intermediate node, wherein the first configurable resistor comprises a plurality of parallel branches, wherein each respective branch comprises a respective transistor and a respective branch resistor, and couples to the output node and the one of either the first intermediate node or the second intermediate node; and
a fuse circuit configured to provide a plurality of fuse signals to configure the first configurable resistor, wherein each respective fuse signal of the plurality of fuse signals is provided to a respective gate of the respective transistor of the respective parallel branch.

US Pat. No. 10,693,458

SWITCH CIRCUIT AND METHOD OF OPERATING THE SAME

SUPER MICRO COMPUTER, INC...

1. A switch circuit, comprising:a first conductive terminal configured to receive a first signal from a first pin of a connector;
a second conductive terminal configured to receive a second signal from a second pin of the connector;
a third conductive terminal electrically connected to a third pin of the connector; and
a fourth conductive terminal electrically connected to a fourth pin of the connector,
wherein the third conductive terminal outputs a first power signal of a first voltage level to the third pin of the connector upon receiving the first signal from the first pin of the connector, and wherein the fourth conductive terminal outputs a second power signal of a second voltage level to the fourth pin of the connector upon receiving the second signal from the second pin of the connector, wherein the second voltage level is different from the first voltage level.

US Pat. No. 10,693,457

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

SOCIONEXT INC., Kanagawa...

1. A semiconductor integrated circuit device, comprising:a global power supply line; and
a power domain,
the power domain including:
a local power supply line;
a plurality of standard cells connected to the local power supply line; and
a plurality of power switch cells,
wherein each of the plurality of power switch cells includes a power switch capable of performing switching between electrical connection and disconnection between the global power supply line and the local power supply line in accordance with a control signal,
the power switches of the plurality of power switch cells are connected in a chain state to form a chain connection through which the control signal is sequentially transmitted, the power switches including a starting point switch which is positioned at the beginning of the chain connection and to which the control signal is given from outside of the power domain, and at least one ending point switch positioned at the end of the chain connection, and
a distance between the starting point switch and a first edge of a region occupied by the power domain is greater than a distance between the at least one ending point switch and a second edge of the region occupied by the power domain, wherein the first edge is the nearest to the starting point switch among edges of the region occupied by the power domain and the second edge is the nearest to the at least one ending point switch among edges of the region occupied by the power domain.

US Pat. No. 10,693,456

METHOD AND ELECTRONIC CIRCUIT FOR DRIVING A TRANSISTOR DEVICE

Infineon Technologies AG,...

14. An electronic circuit comprising a drive circuit, wherein the drive circuit is configured to:generate a drive voltage at a drive output configured to have a drive input of the transistor device connected thereto, wherein a voltage level of the drive voltage is higher than a threshold voltage level of the transistor device;
adjust the voltage level of the drive voltage based on a load signal that represents a current level of a load current through the transistor device; and
determine that the current level of the load current exceeds a threshold current level,
wherein the drive circuit is configured to adjust the voltage level of the drive voltage by increasing the voltage level of the drive voltage in the on-state causing a reduction in conduction losses in the transistor device in response to determining that the current level of the load current exceeds the threshold current level, and
wherein the current level is an actual current level or an expected current level of the load current.

US Pat. No. 10,693,455

THYRISTOR OR TRIAC CONTROL CIRCUIT

STMicroelectronics (Tours...

12. A circuit, comprising:a capacitive element coupled between a first output terminal and a second output terminal;
a first thyristor having:
a gate;
a first conduction terminal coupled to the first output terminal;
a second thyristor having
a gate;
a first conduction terminal coupled to the first output terminal;
a first control circuit and a second control circuit, each control circuit including:
a first diode element coupled between a first node and a second node, the second node of the first control circuit coupled to the gate of the first thyristor and the second node of the second control circuit coupled to the gate of the second thyristor;
a first capacitive element coupled between a first control terminal and the first node;
a second capacitive element coupled between the second node and the first output terminal;
a second diode coupled between the first output terminal and the first node; and
a transistor having a first output terminal coupled to the first output terminal, a second output terminal coupled to the first node, and a second control terminal, the second control terminal of the transistor of the first control circuit being coupled to the first node of the second control circuit, and the second control terminal of the transistor of the second control circuit coupled to the second node of the first control circuit; and
a pulse generation circuit coupled to the first control terminal of each of the first and second control circuit, the pulse generation circuit configured to provide a plurality of pulses on the first control terminal, an amplitude of the plurality of pulses being less than an amplitude of an alternating voltage signal across the first conduction node and a second conduction node of the thyristor, and a frequency of the plurality of pulses being greater than a frequency of the alternating voltage signal across the first and second conduction nodes of the thyristor.

US Pat. No. 10,693,454

SIGNALS FOR THE CONTROL OF POWER DEVICES

Infineon Technologies Aus...

1. A device comprising:a gate driver circuit; and
a control circuit configured to:
generate a first signal including a duty cycle equal to a duration of a high pulse of the first signal divided by a duration of a period of the first signal, the duty cycle of the first signal encoding an amplitude of an electrical current having a sinusoidal shape,
generate a second signal including a duty cycle equal to a duration of a high pulse of the second signal divided by a duration of a period of the second signal, the duty cycle of the second signal encoding a phase angle of the electrical current, and
deliver the first signal and the second signal to the gate driver circuit, wherein the gate driver circuit is configured to:
determine a duty cycle of a driver signal as a function of the first signal and of the second signal, and
deliver the driver signal to a switch to cause the electrical current having the sinusoidal shape to be delivered to an electrical load,
wherein the driver signal is a pulse-width modulation (PWM) signal,
wherein at least one of the first signal or the second signal has a frequency that is N times a frequency of the PWM signal, and
wherein N is an integer greater than or equal to two.

US Pat. No. 10,693,453

POWER SWITCH CIRCUIT

Excelliance MOS Corporati...

1. A power switch circuit, comprising:a first transistor, having a first end, a second end and a control end, wherein the first end of the first transistor is configured to serve as an input terminal of the power switch circuit, the second end of the first transistor is coupled to a node, and a control end of the first transistor is configured to receive a first control voltage;
a second transistor, having a first end, a second end and a control end, wherein the first end of the second transistor is configured to serve as an output terminal of the power switch circuit, the second end of the second transistor is coupled to the node, and a control end of the second transistor is configured to receive a second control voltage; and
a control circuit, coupled to the node, the control end of the first transistor and the control end of the second transistor, wherein the control circuit detects a voltage of the node, determines a type of series connection between the first transistor and the second transistor according to the voltage of the node, and generates the first control voltage and the second control voltage according to the type of series connection, so as to start controlling a turned-on state of another of the first transistor and the second transistor after completely turning on one of the first transistor and the second transistor.

US Pat. No. 10,693,452

ULTRA LOW EMISSION SOLID STATE RELAY

Sensata Technologies, Inc...

1. A solid state switch comprising:an output circuit comprising a first plurality of semiconductor switching devices including a plurality of silicon controlled rectifiers, wherein the first plurality of semiconductor switching devices selectively provide power to a load from a voltage source when enabled; and
an input circuit comprising a second plurality of semiconductor switching devices, wherein each of the second plurality of semiconductor switching devices is electrically coupled to a gate of a corresponding semiconductor switching device of the first plurality of semiconductor switching devices; and
wherein the second plurality of semiconductor switching devices comprise a plurality of optocoupler devices with zero crossing detection functionality;
wherein the second plurality of semiconductor switching devices are configured to turn on the output circuit upon the zero crossing of a control signal applied to the second plurality of semiconductor switching devices.

US Pat. No. 10,693,451

RINGING SUPPRESSOR CIRCUIT

SOKEN, INC., Nisshin (JP...

1. A ringing suppressor circuit connected to a transmission line for transmitting a differential signal that switches between a high level and a low level via a high potential and low potential pair of signal lines, and for suppressing a ringing in the differential signal, the ringing suppressor circuit comprising:a ringing suppressor configured to lower an impedance between the pair of signal lines when the differential signal switches from the low level to the high level; and
a stopper configured to
stop the ringing suppressor from lowering the impedance between the pair of signal lines when the stopper determines that a voltage of the differential signal drops below a voltage lowering determination voltage, wherein
the stopper is further configured to set the voltage lowering determination voltage lower than a differential voltage of the differential signal when the transmission line is transmitting the differential signal at the high level.

US Pat. No. 10,693,450

APPARATUS AND METHOD FOR OVER-VOLTAGE PROTECTION

Intel IP Corporation, Sa...

1. An apparatus comprising:a first power supply rail to provide a first power supply;
a second power supply rail to provide a second power supply, wherein the first power supply is higher than the second power supply, wherein a voltage level of the first power supply and a voltage level of the second power supply are higher than a ground voltage on a ground power supply rail;
a first stack of transistors of a same conductivity type, the first stack including a first transistor and a second transistor coupled in series and having a first common node, wherein the first transistor is coupled to the first power supply rail;
a second stack of transistors of an opposite conductivity type to the first stack of transistors, the second stack including a third transistor and a fourth transistor coupled in series and having a second common node, wherein the second stack of transistor is coupled in series to the first stack of transistors and having a third common node, wherein a gate terminal of the third transistor is coupled to a circuitry which is coupled to the second power supply rail; and
a feedback transistor of a same conductivity type of the third transistor coupled to the second common node and a gate terminal of the third transistor of the second stack, wherein the feedback transistor includes a gate terminal which is coupled to the third common node.

US Pat. No. 10,693,449

SWITCHING CIRCUIT DEVICE, STEP-DOWN DC-DC CONVERTER, AND ELEMENT UNIT

TOHOKU UNIVERSITY, Miyag...

1. A switching circuit device comprising:a high-side switching element circuit including first and second high-side switching elements connected in series between an output terminal and a high-voltage terminal of a high voltage source, the first high-side switching element being closer to the high-voltage terminal and the second high-side switching element being closer to the output terminal, each of the first and second high-side switching elements having an n-type metal-oxide-semiconductor field-effect transistor;
a low-side switching element circuit including first and second low-side switching elements connected in series between the output terminal and a reference potential terminal, each of the first and second low-side switching elements having an n-type metal-oxide-semiconductor field-effect transistor;
a high-side drive circuit configured to turn on and off the second high-side switching element;
a low-side drive circuit configured to turn on and off the first and second low-side switching elements; and
a bootstrap circuit provided in the high-side drive circuit and having a bootstrap capacitor, the bootstrap capacitor having:
a first terminal connected only to a gate terminal of the first high-side switching element regarding the high-side switching element circuit; and
a second terminal connected to the output terminal,
the bootstrap capacitor being configured to:
be connected to a drive power source and charged while the first and second low-side switching elements are ON; and
apply a gate voltage to the gate terminal of the first high-side switching element while the first and second low-side switching elements are OFF, the gate voltage being defined by adding a voltage of the output terminal to a voltage between the first and second terminals of the bootstrap capacitor.

US Pat. No. 10,693,448

SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. An operation method for driving a semiconductor device,wherein the semiconductor device comprises:
a first transistor comprising a backgate;
a second transistor comprising a backgate;
a third transistor;
a fourth transistor;
a first load comprising a fifth transistor;
a second load comprising a sixth transistor;
a first terminal;
a second terminal;
a third terminal;
a fourth terminal;
a fifth terminal;
a sixth terminal; and
a seventh terminal;
wherein a drain of the third transistor is electrically connected to a source of the first transistor and a source of the second transistor,
wherein a drain of the first transistor is electrically connected to the source of the fifth transistor,
wherein a drain of the second transistor is electrically connected to the source of the sixth transistor,
wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor is an n-channel transistor,
wherein a drain of the first transistor is electrically connected to the first load,
wherein a drain of the second transistor is electrically connected to the second load,
wherein the first terminal is electrically connected to a gate of the first transistor;
wherein the second terminal is electrically connected to a gate of the second transistor;
wherein the third terminal is electrically connected to a drain of the second transistor;
wherein the fourth terminal is electrically connected to a source of the third transistor;
wherein the fifth terminal is electrically connected to the backgate of the first transistor and the backgate of the second transistor;
wherein one of a drain and a source of the fourth transistor is electrically connected to the second terminal,
wherein the other of the drain and the source of the fourth transistor is electrically connected to the sixth terminal; and
wherein the seventh terminal is electrically connected to a gate of the fourth transistor;
wherein the operation method comprises:
supplying a first potential to the fifth terminal,
supplying a second potential to the sixth terminal,
supplying a third potential to the seventh terminal and resetting the potential of the second terminal,
supplying a fourth potential to the fourth terminal,
supplying a fifth potential to the first terminal and supplying a sixth potential to the second terminal, and
generating a seventh potential based on the comparison of the fifth potential and the sixth potential and supplying the seventh potential to the third terminal.

US Pat. No. 10,693,447

COMPARATOR CIRCUIT

Artery Technology Co., Lt...

1. A comparator circuit, comprising:a comparator, coupled between a power voltage and a ground voltage, configured to perform a comparison according to a set of input signals to generate at least one comparison signal, wherein the comparator comprises:
a set of input terminals, configured to receive the set of input signals;
a first set of transistors, coupled between the power voltage and a node, wherein a first terminal, a second terminal and a control terminal of a transistor within the first set of transistors are respectively coupled to a second terminal of another transistor within the first set of transistors, the node and an input terminal within the set of input terminals, and a first terminal of the other transistor within the first set of transistors is coupled to the power voltage;
a second set of transistors, coupled between the power voltage and the node, wherein a first terminal, a second terminal and a control terminal of a transistor within the second set of transistors are respectively coupled to a second terminal of another transistor within the second set of transistors, the node and another input terminal within the set of input terminals, and a first terminal of the other transistor within the second set of transistors is coupled to the power voltage;
a third set of transistors, coupled between the power voltage and the ground voltage, wherein a first terminal, a second terminal and a control terminal of a transistor within the third set of transistors are respectively coupled to a second terminal of another transistor within the third set of transistors, the ground voltage and an output stage of the comparator, and a first terminal and a control terminal of the other transistor within the third set of transistors are respectively coupled to the power voltage and a control terminal of the other transistor within the first set of transistors; and
a fourth set of transistors, coupled between the power voltage and the ground voltage and positioned in the output stage, wherein a first terminal, a second terminal and a control terminal of a transistor within the fourth set of transistors are respectively coupled to a second terminal of another transistor within the fourth set of transistors, the ground voltage and the control terminal of the transistor within the third set of transistors, and a first terminal and a control terminal of the other transistor within the fourth set of transistors are respectively coupled to the power voltage and a control terminal of the other transistor within the second set of transistors;
a current source, coupled between the node and the ground voltage, configured to provide current; and
a plurality of positive feedback circuits, coupled between the power voltage and the ground voltage and coupled to the node, configured to perform a plurality of positive feedback operations on the node to generate a plurality of instant currents on the node, respectively, to make the comparator switch said at least one comparison signal in response to a transition of the set of input signals in real time, wherein any positive feedback circuit within the positive feedback circuits comprises:
a first switch, coupled to the node, configured to enable or disable said any positive feedback circuit in response to a transition of said at least one comparison signal, wherein when said any positive feedback circuit is enabled, a first current flows through the first switch; and
a set of transistors, coupled between the power voltage and the ground voltage, configured to generate the first current and a second current corresponding to each other, wherein an instant current within the instant currents corresponds to the second current.

US Pat. No. 10,693,446

CLOCK ADJUSTMENT CIRCUIT AND CLOCK ADJUSTMENT METHOD

REALTEK SEMICONDUCTOR COR...

1. A clock adjustment circuit configured to generate an output clock, comprising:a phase interpolator configured to generate by interpolation an intermediate clock according to a first reference clock, a second reference clock, and a control signal, wherein the frequency of the first reference clock, the frequency of the second reference clock, and the frequency of the intermediate clock are substantially the same;
a logic circuit coupled to the phase interpolator and configured to generate the output clock according to the intermediate clock and one of the first reference clock and the second reference clock; and
an integrator coupled to the phase interpolator and the logic circuit and configured to generate the control signal according to the output clock, wherein the control signal varies with an average based on a duty cycle of the output clock;
wherein the phase interpolator comprises:
a first transistor having a first gate, a first drain, and a first source, wherein the first gate receives the first reference clock, and the intermediate clock is outputted through the first drain;
a second transistor having a second gate, a second drain, and a second source, wherein the second gate receives the second reference clock, and the second drain is electrically connected to the first drain;
a third transistor having a third gate, a third drain, and a third source, wherein the third gate receives a reference signal, the third drain is electrically connected to the first source, and the third source is coupled to a first reference voltage;
a fourth transistor having a fourth gate, a fourth drain, and a fourth source, wherein the fourth gate receives the control signal, the fourth drain is electrically connected to the second source, and the fourth source is coupled to the first reference voltage;
a capacitor with one end of which coupled to the first drain and the other end of which coupled to a second reference voltage; and
a resistor with one end of which coupled to the first drain and the other end of which coupled to the second reference voltage.

US Pat. No. 10,693,445

MAGNETIC TUNNEL JUNCTION RING OSCILLATOR WITH TUNABLE FREQUENCY AND METHODS FOR OPERATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising:a ring oscillator, wherein the ring oscillator comprises:
an input voltage terminal;
an output voltage terminal; and
an odd number of at least three inverters disposed electrically in series with one another between the input voltage terminal and the output voltage terminal, each of the at least three inverters comprising a first N-type metal oxide semiconductor transistor, a second N-type metal oxide semiconductor transistor, and one or more magnetic tunnel junctions disposed electrically in series with the first N-type metal oxide semiconductor transistor and electrically in series with the second N-type metal oxide semiconductor transistor,
wherein the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor of each of the at least three inverters are selectively tunable with regard to either or both of a threshold voltage and an effective channel width.

US Pat. No. 10,693,444

MIXED SIGNAL CIRCUIT SPUR CANCELLATION

TEXAS INSTRUMENTS INCORPO...

1. A mixed signal circuit, comprising:an analog circuit; and
a digital circuit, comprising:
a spur cancellation circuit, comprising:
a clock generation circuit; and
a flip-flop bank coupled to the clock generation circuit, and comprising:
a plurality of flip-flops, each of the flip-flops comprising a clock input coupled to a clock output of the clock generation circuit;
a control circuit coupled to the clock generation circuit and the flip-flop bank and comprising:
a plurality of clock enable outputs, each of the clock enable outputs coupled to a clock enable input of one of the flip-flops; and
a data output coupled to a data input of one of the flip-flops;
wherein the clock generation circuit comprises:
a ring counter comprising:
a plurality of flip-flops; and
a plurality of selection circuits, each of the selection circuits coupled to an output of a first of the flip-flops of the ring counter and an input of a second of the flip-flops of the ring counter;
clock gating circuitry coupled to the ring counter, and comprising a logic gate coupled to:
an output of the ring counter; and
an input clock selector.

US Pat. No. 10,693,442

UNIVERSAL AUTOMATIC FREQUENCY CONTROL FOR MULTI-CHANNEL RECEIVERS

Sirius XM Radio Inc., Ne...

1. A data receiver, comprising:a tuner for receiving a first signal and a second signal;
a first demodulator coupled to the tuner, the first demodulator being configured to demodulate the first signal;
a second demodulator coupled to the tuner, the second demodulator being configured to demodulate the second signal; and
at least one processor coupled to the first and second demodulators, the at least one processor being configured to determine a first frequency offset for the first demodulator,
wherein, when the second demodulator is unable to lock to the second signal, the at least one processor applies the first frequency offset to the second demodulator.

US Pat. No. 10,693,441

ACOUSTIC WAVE FILTER

TAIYO YUDEN CO., LTD., T...

1. An acoustic wave filter comprising:a piezoelectric substrate;
a first multimode filter that includes at least three first IDTs located on the piezoelectric substrate, has a first passband, and is connected between an input terminal and an output terminal; and
a second multimode filter that includes at least three second IDTs located on the piezoelectric substrate, has a second passband, and is connected in series with the first multimode filter between the input terminal and the output terminal, a part of the second passband overlapping with the first passband, a remaining part of the second passband not overlapping with the first passband,
wherein:
0.01?2×If1-f2I/(f1+f2)<0.02
where f1 represents a center frequency of the first passband and f2 represents a center frequency of the second passband,
each of a center first IDT of the at least three first IDTs and adjacent first IDTs to the center first IDT includes a pair of first comb-shaped electrodes, electrode fingers of one of the pair of first comb-shaped electrodes and electrode fingers of another of the pair of first comb-shaped electrodes are alternately arranged, and no electrode is located between the center first IDT and the adjacent first IDTs, and
each of a center second IDT of the at least three second IDTs and adjacent second IDTs to the center second IDT includes a pair of second comb-shaped electrodes, electrode fingers of one of the pair of second comb-shaped electrodes and electrode fingers of another of the pair of second comb-shaped electrodes are alternately arranged, and no electrode is located between the center second IDT and the adjacent second IDTs.

US Pat. No. 10,693,440

ACOUSTIC WAVE DEVICE

TAIYO YUDEN CO., LTD., T...

14. An acoustic wave device comprising:a first substrate having a first surface;
an acoustic wave element located on the first surface;
a second substrate having a second surface;
a functional element located on the second surface;
a third substrate having a third surface and a fourth surface, the third surface facing the first surface and the second surface across an air gap, the fourth surface being an opposite surface of the third substrate from the third surface;
a first metal layer that is separated from the acoustic wave element and a wiring line connected to the acoustic wave element in the first substrate and connects the first surface and the third surface;
a second metal layer that is separated from the functional element and a wiring line connected to the functional element in the second substrate and connects the second surface and the third surface;
a first metal pattern that is located on the third surface, is in contact with the first metal layer and the second metal layer, and connects the first metal layer and the second metal layer;
a terminal that is located on the fourth surface and is electrically connectable to the first metal pattern;
a first insulating layer included in the third substrate and having the third surface;
a first via wiring being in contact with the first metal pattern between the first metal layer and the second metal layer and penetrating through the first insulating layer;
a second via wiring being in contact with the first metal pattern and penetrating through the first insulating layer;
a second insulating layer included in the third substrate, located between the first insulating layer and the fourth surface, and having a fifth surface; and
a second metal pattern located on the fifth surface, connected to the terminal, and connected to the first metal pattern through the first via wiring and the second via wiring, the first via wiring and the second via wiring being connected in parallel to each other between the first metal pattern and the second metal pattern,
wherein the first metal pattern is electrically connected to the terminal through the first via wiring.

US Pat. No. 10,693,439

CRYSTAL VIBRATOR AND CRYSTAL VIBRATION DEVICE

KYOCERA CORPORATION, Kyo...

1. A crystal vibrator comprising:a plate-shaped crystal blank generating thickness shear vibration, the crystal blank comprising a pair of major surfaces,
a pair of excitation electrodes, each excitation electrode located on a respective one of the major surfaces of the crystal blank, and
a pair of extraction electrodes respectively extracted from the excitation electrodes, wherein
the crystal blank comprises a plurality of hill parts which are covered by an excitation electrode, and
heights of the hill parts are larger than a standard deviation of a thickness of the crystal blank and are not more than 0.1% of an average thickness of the crystal blank.

US Pat. No. 10,693,438

ACOUSTIC WAVE RESONATOR AND METHOD FOR MANUFACTURING THE SAME

Samsung Electro-Mechanics...

1. An acoustic wave resonator, comprising:a substrate;
a resonating portion formed on a first surface of the substrate;
a metal pad connected to the resonating portion through a via hole formed in the substrate; and
a protective layer disposed on a second surface of the substrate and comprising a plurality of layers,
wherein the metal pad comprises an internal pad connected to the resonating portion, and comprising an inner surface disposed on the second surface of the substrate, and
wherein the plurality of layers comprises:
an internal protective layer directly in contact with the second surface of the substrate and an outer surface of the internal pad, and formed of a first insulating material; and
an external protective layer disposed on an outer surface of the internal protective layer.

US Pat. No. 10,693,437

HIGH GAMMA ON-WAFER LOAD PULL TEST SYSTEM

1. A high GAMMA on-wafer load-pull test system, comprisingat least one automated tuner,
a manual, low profile pre-matching module,
a wafer-probe-station, input and output wafer-probes and associated test instruments,
at least one 3-axis tuner positioner,
a control computer, calibration and test software;
wherein
the at least one tuner has an extended bent slabline (bend-line) directly connected to a wafer-probe,
and wherein
the low-profile module is mounted on the bend-line between the bend and the wafer-probe;
and wherein
the wafer-probe connects to a DUT, and
the tuner position is controlled by the 3-axis positioner.

US Pat. No. 10,693,436

IMPEDANCE ADJUSTING CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME

SK hynix Inc., Gyeonggi-...

1. An impedance adjusting circuit, comprising:a first node coupled to a resistor;
a first impedance unit having an impedance value determined based on a first impedance code and coupled between a first voltage terminal and a second node;
a first switching unit suitable for electrically connecting the first node and the second node to each other in response to a clock;
a first average voltage unit suitable for generating an average voltage of the first node;
a first comparison unit suitable for comparing the average voltage of the first node with a first reference voltage to produce a comparison result of the first comparison unit; and
a first code generation unit suitable for generating the first impedance code in response to the comparison result of the first comparison unit.

US Pat. No. 10,693,435

INTEGRATED AND COMBINED PHASE SHIFTER AND ISOLATION SWITCH

pSemi Corporation, San D...

1. A digitally-controlled attenuation/phase shifter circuit having a circuit path for communicating an applied signal between a first circuit port and a second circuit port, including:(a) at least one variable attenuator serially coupled to the circuit path;
(b) one or more variable phase shifters serially coupled to the circuit path and to the at least one variable attenuator, at least one of the one or more variable phase shifters responsive to independent path selection control signals for selectively independently enabling communication of the applied signal from the first circuit port to the second circuit port through the at least one variable phase shifter when not in an isolation mode, and for disabling communication of the applied signal from the first circuit port to the second circuit port through the at least one variable phase shifter when in the isolation mode; and
(c) at least one selectable termination circuit coupled to the circuit path, each operatively coupled through the circuit path to a corresponding one of the first or second circuit ports and responsive to a distinct isolation circuit control signal for isolating the first circuit port from the second circuit port in the isolation mode.

US Pat. No. 10,693,434

RC TIME CONSTANT MEASUREMENT

Teledyne LeCroy, Inc., T...

1. An electronic-implemented method to characterize a device under test, comprising:receiving, by an electronic test instrument, an electrical waveform from the device under test;
sampling, by the electronic test instrument, the electrical waveform to generate an array of data values that represent a magnitude of an electrical characteristic of the electrical waveform at corresponding points in time;
presenting, by the electronic test instrument, a representation of the electrical waveform on a display of the electronic test instrument;
receiving, by the electronic test instrument, user input that selects an arbitrary, user-selected position of the electrical waveform that is presented on the display of the electronic test instrument;
identifying, by the electronic test instrument, a starting time that corresponds to the usr-selected position that was selected by user input;
identifying, by the electronic test instrument, a starting data value in the array of data values that corresponds to the user-selected position that was selected by user input;
identifying, by the electronic test instrument, a decayed value that identifies a level of the starting data value decayed by a pre-determined amount;
analyzing, by the electronic test instrument, the array of data values to identify multiple data values in the array of data values that correspond to the decayed value;
determining, by the electronic test instrument, an ending time using the multiple data values in the array of data values that correspond to the decayed value;
determining, by the electronic test instrument after the decayed value has been identified, a decay time between the starting time and the ending time; and
presenting, by the electronic test instrument and on a display device, the determined decay time.

US Pat. No. 10,693,433

ELECTROSTATIC CHUCK FILTER BOX AND MOUNTING BRACKET

Lam Research Corporation,...

1. An electrostatic chuck RF filter box for mounting on a bracket of a pedestal lift to make a plurality of electrical connections, the RF filter box comprising:at least one contact block including a plurality of self-aligning electrical connectors on a mating surface of the RF filter box, wherein the mating surface is an outer surface of the RF filter box; and
at least one alignment feature on the mating surface of the RF filter box, wherein the at least one alignment feature is configured for aligning the plurality of self-aligning electrical connectors with corresponding electrical connectors on the bracket of the pedestal lift such that the plurality of self-aligning electrical connectors and the corresponding electrical connectors on the bracket of the pedestal lift automatically mate when the at least one contact block is mounted to the bracket of the pedestal lift.

US Pat. No. 10,693,432

SOLENOID STRUCTURE WITH CONDUCTIVE PILLAR TECHNOLOGY

QUALCOMMM Incorporated, ...

1. A three-dimensional solenoid structure, comprising:a first inductor portion including a first surface and a second surface opposite the first surface;
a first capacitor portion;
a first inductor pillar coupled to the first surface of the first inductor portion, the first inductor pillar having a first bonding material at an end away from the first surface;
at least one capacitor pillar coupled to the first capacitor portion;
a second inductor portion including a third surface and a fourth surface opposite the third surface;
a second inductor pillar coupled to the third surface of the second inductor portion, the second inductor pillar having a second bonding material at an end near the first bonding material; and
a first inductor bonding interface between the first inductor pillar and the second inductor pillar to couple the first inductor portion and the second inductor portion, the first inductor bonding interface comprising the first bonding material and the second bonding material.

US Pat. No. 10,693,431

MANUFACTURING OF THIN-FILM BULK ACOUSTIC RESONATOR AND SEMICONDUCTOR APPARATUS COMPRISING THE SAME

Semiconductor Manufacturi...

1. A method for manufacturing a semiconductor apparatus, comprising:providing a base substrate;
forming an isolation trench layer on a first side of the base substrate;
forming a first dielectric layer on the isolation trench layer, wherein the isolation trench layer being positioned between the base substrate and the first dielectric layer;
forming a lower electrode layer on a part of the first dielectric layer, the lower electrode layer is also above the isolation trench layer;
forming a second dielectric layer to cover the lower electrode layer;
forming an opening in the second dielectric layer, the opening exposing a part of the lower electrode layer and having a plan view in the shape of a polygon;
forming a piezoelectric film to cover an upper surface of the second dielectric layer and bottom and side surfaces of the opening;
forming an upper electrode layer on the piezoelectric film;
patternizing the piezoelectric film and the upper electrode layer, retaining a portion of the piezoelectric film and the upper electrode layer in the opening;
forming a third dielectric layer to cover the upper electrode layer and the second dielectric layer;
forming a first cavity in the third dielectric layer, the first cavity exposing at least part of the upper electrode layer and having a plan view in the shape of a first polygon;
providing a first assistant substrate;
forming a first bonding layer on the first assistant substrate;
bonding the first bonding layer with the third dielectric layer to seal the first cavity;
removing a part of the base substrate to expose the isolation trench layer;
forming a fourth dielectric layer on a side of the isolation trench layer that is opposing to a side of the isolation trench layer that contacts the first dielectric layer, so that the isolation trench layer is positioned between the fourth dielectric layer and the first dielectric layer;
etching through the fourth dielectric layer, the isolation trench layer, the first dielectric layer to expose a part of the lower electrode layer and form a second cavity beneath the lower electrode layer, wherein the second cavity is facing the first cavity and has a plan view of a second polygon, the plan views of the first and second cavities have an overlapped region that forms a shape of a third polygon that does not have any parallel sides; and
sealing the second cavity.

US Pat. No. 10,693,430

AUDIO SIGNAL PROCESSING METHOD AND AUDIO EQUALIZER

REALTEK SEMICONDUCTOR COR...

1. An audio signal processing method adapted for an audio equalizer, comprising:reading a time domain audio signal;
windowing the time domain audio signal to produce a plurality of sampling blocks, wherein each of the sampling blocks has a plurality of samples, and each of any adjacent two of the sampling blocks has an overlap portion with a predetermined proportion;
applying a Kaiser-Bessel-derived (KBD) window to each of the sampling blocks to produce a plurality of result values corresponding to each sample of each of the sampling blocks;
converting the sampling blocks into a plurality of frequency bands of a frequency domain through a Modified Discrete Cosine Transform (MDCT), wherein each of the frequency bands has a frequency point corresponding to a frequency value;
equalizing the frequency bands to produce a plurality of adjusted frequency bands, wherein each of the adjusted frequency bands has a frequency point corresponding to an adjusted frequency value;
converting the adjusted frequency bands to a plurality of new sampling blocks in a time domain through an Inverse Modified Discrete Cosine Transform (IMDCT), wherein each sample of each of the new sampling blocks corresponds to a new result value;
applying a KBD restore window to each of the new sampling blocks to compensate for the new result value corresponding to each sample of each of the new sampling blocks; and
aliasing each of the new sampling blocks based on the overlap portion through an Overlap-and-Add (OLA) processing to produce a new time domain audio signal.

US Pat. No. 10,693,429

DYNAMIC PHASED ARRAY TAPERING WITHOUT PHASE RECALIBRATION

INTERNATIONAL BUSINESS MA...

1. A method for phased array tapering, comprising:setting a gain at a phase-invariant variable gain amplifier in each of a plurality of front-ends of a phased array transceiver, to perform tapering of beam pattern side lobes, by:
setting a first gain at a first stage of the phase-invariant variable gain amplifier; and
setting a second gain at a second stage of the phase-invariant variable gain amplifier, wherein a dependency of a phase shift of the first stage on the gain of the first stage is equal to and opposite a dependency of a phase shift of the second stage on the gain of the second stage.

US Pat. No. 10,693,428

SYSTEM AND METHOD FOR CONTROL OF AN ANALOG DEVICE

1. An analog device control system, comprising:an analog device control module, comprising computer-executable code stored in non-volatile memory;
a processor; and
an analog device;
wherein the analog device control module, the processor, and the analog device are operably connected and configured to:
use the analog device to receive an analog audio signal in the form of a live performance;
digitally control the analog device using the analog device control module; and
vary the analog audio signal using the analog device control module;
wherein varying the analog signal is based on digitally controlling the analog device using the analog device control module,
wherein said varying of the analog audio signal comprises digitally changing parameter values of the analog audio signal in substantially real time, wherein said changed parameter values are stored in said memory for later retrieval and application to a subsequent performance.

US Pat. No. 10,693,427

HIGH-EFFICIENCY AMPLIFIER

Airbus Defence and Space ...

1. An electronic amplification apparatus comprising:a travelling wave tube amplifier (TWTA); and
a limiter;
wherein the TWTA is designed for optimised RF-to-DC efficiency at an operating point below saturation within the linear region of the amplifier, such that the peak RF-to-DC efficiency of the TWTA is within the linear region, and the limiter is arranged to prevent the output power of the amplifier from going beyond a predetermined limit.

US Pat. No. 10,693,426

INTEGRATED AMPLIFIER DEVICES AND METHODS OF USE THEREOF

INTRINSIX CORP., Marlbor...

1. An integrated amplifier device comprising:a main amplifier configured to be coupled to an input source;
a replica amplifier coupled to the main amplifier to provide a bias to the main amplifier;
a transconductance biasing cell coupled to the main amplifier and the replica amplifier, wherein the transconductance biasing cell is configured to bias both the main amplifier and the replica amplifier; and
a differential voltage source coupled to the replica amplifier to provide a differential voltage and a differential current source coupled to the replica amplifier to provide a differential current.

US Pat. No. 10,693,425

POWER AMPLIFIER TIME-DELAY INVARIANT PREDISTORTION METHODS AND APPARATUS

Dali Wireless, Inc., Men...

1. A predistortion system for linearizing the output of a power amplifier, the predistortion system comprising: a feedback receiver configured to receive a feedback signal representative of at least one nonlinear characteristic of the power amplifier, the power amplifier configured to amplify an input signal comprising a radio frequency (RF) modulated signal in digital form; anda predistortion processor communicatively coupled with the feedback receiver, the predistortion processor comprising a lookup table of a predetermined size configured to receive the input signal, wherein an output of the lookup table includes a time delay correction element.

US Pat. No. 10,693,424

POWER AMPLIFYING APPARATUS WITH WIDEBAND LINEARITY

Samsung Electro-Mechanics...

1. A power amplifying apparatus comprising:a first bias circuit configured to generate a first bias current;
a first amplification circuit configured to receive the first bias current from the first bias circuit and an input signal input through a first node, amplify the input signal, and output a first amplified signal to a second node;
a second bias circuit configured to generate a second bias current having a magnitude different from a magnitude of the first bias current; and
a second amplification circuit connected in parallel with the first amplification circuit and configured to receive the second bias current from the second bias circuit and the input signal input through the first node, amplify the input signal, and output a second amplified signal to the second node,
wherein the second amplification circuit is further configured so that the second bias current causes the second amplified signal to comprise a third-order intermodulation distortion (IM3) component having a phase offsetting a third-order intermodulation distortion (IM3) component included in the first amplified signal.

US Pat. No. 10,693,423

DYNAMIC AMPLIFICATION CIRCUIT

SHENZHEN GOODIX TECHNOLOG...

1. A dynamic amplification circuit, comprising:a first drive circuit, configured to generate a first driving voltage according to a first control signal and a first driving current, wherein the first driving current is generated by a first reference voltage, and the first reference voltage is a constant voltage;
a second drive circuit, configured to generate a first driving signal according to the first driving voltage and a second driving voltage, wherein the first driving voltage varies with time, and the second driving voltage is a multiple of the first reference voltage;
a third drive circuit, configured to generate a second control signal according to the first control signal and the first driving signal; and
a dynamic amplifier DA comprising a first branch and a second branch, wherein the first branch comprises a first capacitor, the second branch comprises a second capacitor, the first capacitor and the second capacitor are identical capacitors, the first branch and the second branch are connected through a first resistor and a second resistor, and the first resistor and the second resistor are identical resistors,
wherein the DA is configured to receive the first control signal and the second control signal, and an operation state of the DA is controlled through the first control signal and the second control signal, wherein a duration of the DA in an amplification phase is proportional to a product of a resistance value of the first resistor and a capacitance value of the first capacitor.