US Pat. No. 10,659,130

TERMINAL, BASE STATION, AND CHANNEL INFORMATION OBTAINING METHOD

HUAWEI TECHNOLOGIES CO., ...

1. A channel information obtaining method, comprising:sending, by a base station, a downlink reference signal to a terminal, wherein the downlink reference signal is used to obtain second channel information using feedback of the terminal to the downlink reference signal, and the second channel information is used to indicate channel state matrix information of a second subset of channels between the base station and the terminal;
receiving, by the base station, an uplink reference signal from the terminal, wherein the uplink reference signal is used to obtain first channel information using the uplink reference signal, and the first channel information is used to indicate channel state matrix information of a first subset of the channels between the base station and the terminal; and
receiving, by the base station, the second channel information from the terminal, wherein the first channel information and the second channel information are combined by the base station to obtain channel state matrix information of the channels between the base station and the terminal.

US Pat. No. 10,659,129

METHOD AND APPARATUS FOR FEEDING BACK CHANNEL STATE INFORMATION, AND A METHOD AND APPARATUS FOR TRANSMITTING DATA

China Academy of Telecomm...

1. A method for providing feedback channel state information, the method comprising:calculating channel state information according to a first codebook, wherein the first codebook includes a set of elements and each of the elements includes a set of pre-coding matrixes; and
providing feedback of the channel state information;
wherein the channel state information is a channel quality indicator (CQI), a set of pre-coding matrixes corresponding to the CQI is one of the sets of pre-coding matrixes in the first codebook, and data is assumed to be preprocessed by using all or a part of the pre-coding matrixes in the set of pre-coding matrixes over resources for transmitting the data.

US Pat. No. 10,659,128

RADIO NETWORK NODE, WIRELESS DEVICE AND METHODS PERFORMED THEREIN

Telefonaktiebolaget LM Er...

1. A method performed by a user equipment, the method comprising:determining a recommended CSI filtering based on measurements of one or more received reference signals from a base station;
transmitting, to the base station, a first indication of the determined recommended CSI filtering;
receiving, from the base station or another base station, a first configuration of CSI filtering; and
using the received first configuration for applying CSI filtering.

US Pat. No. 10,659,127

METHOD AND DEVICE FOR PERFORMING BEAM SCANNING IN WIRELESS ACCESS SYSTEM SUPPORTING MILLIMETER WAVE

LG ELECTRONICS INC., Seo...

1. A method of scanning transmission and reception beams by a millimeter Wave (mmWave) user equipment in a wireless access system supportive of mmWave, the method comprising:performing a long term beam scanning in a period N, wherein performing the long term beam scanning comprises receiving a first preamble and obtaining first Channel Quality Information (CQI) based on the first preamble;
transmitting feedback information containing a first transmission beam Identifier (Tx beam ID) obtained through the long term beam scanning to an mmWave base station;
receiving a higher layer signal containing reception beam scanning configuration information assigned for a short term beam scanning;
performing the short term beam scanning in a reception beam scanning region based on the reception beam scanning configuration information, wherein performing the short term beam scanning comprises receiving a second preamble and obtaining second CQI based on the second preamble; and
comparing the first CQI and the second CQI with each other,
wherein based on the first CQI being equal to or greater than the second CQI, the mmWave user equipment feeds back the second CQI to the mmWave base station, and
wherein based on the first CQI being smaller than the second CQI, the mmWave user equipment feeds back a second Tx beam ID mapped to the second preamble and a Temporary User Equipment Identifier (TUEID) of the mmWave user equipment to the mmWave base station.

US Pat. No. 10,659,126

METHOD FOR FEEDING BACK CSI INFORMATION IN WIRELESS COMMUNICATION SYSTEM AND DEVICE THEREFOR

LG ELECTRONICS INC., Seo...

1. A method of feeding back channel state information (CSI) by a user equipment (UE) in a wireless communication system applied three-dimensional (3D) beamforming, the method comprising:receiving a pilot signal (reference signal) from a base station;
configuring a CSI transmission mode in one of a first transmission mode or a second transmission mode;
feeding back a set of antenna index for vertical beamforming and a set of antenna index for horizontal beamforming; and
feeding back a CSI based on the configured CSI transmission mode,
wherein the first transmission mode includes precoding matrix index (PMI) information for any one of the vertical beamforming or the horizontal beamforming,
wherein the second transmission mode includes PMI information for both the vertical beamforming and the horizontal beamforming, and
wherein the set of antenna index for a beamforming requesting an open loop transmission is an empty set.

US Pat. No. 10,659,125

SYSTEM AND METHOD FOR ANTENNA ARRAY CONTROL AND COVERAGE MAPPING

Verizon Patent and Licens...

1. A method comprising:identifying, by a computer device, a location for a user equipment (UE) device serviced by a base station sector associated with a base station;
performing, by the computer device, modeling of radio frequency signal propagation for the identified location;
determining, by the computer device, settings for an antenna array associated with the base station sector based on the performed modeling; and
instructing, by the computer device, the base station sector to apply the determined settings to the antenna array.

US Pat. No. 10,659,124

MULTIANTENNA COMMUNICATION DEVICE AND COEFFICIENT UPDATE METHOD

FUJITSU LIMITED, Kawasak...

1. A multiantenna communication device that forms a directional beam by adding an antenna weight to respective signals of a plurality of antenna elements, the multiantenna communication device comprising:a processor that executes performing distortion compensation on a transmission signal by using a distortion compensation coefficient;
a plurality of power amplifiers that are provided corresponding to the antenna elements, and that amplify the transmission signal subjected to the distortion compensation by the processor;
a multiplexer that multiplexes signals output from the power amplifiers to feed back; and
an analog/digital (A/D) converter that A/D converts a multiplex feedback signal that is obtained by the multiplexer, wherein
the processor executes:
generating demultiplex signals as many as number of the antenna elements by demultiplexing the transmission signal;
adding a weight same as an antenna weight per antenna element to each of the generated demultiplex signals;
generating a multiplex signal by multiplexing the demultiplex signals to which the weight is added; and
updating the distortion compensation coefficient by using the multiplex feedback signal A/D converted by the A/D converter and the multiplex signal.

US Pat. No. 10,659,123

APPARATUS AND METHOD FOR BEAM MANAGEMENT IN WIRELESS COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method for operating a base station (BS) in a wireless communication system, the method comprising:receiving, from a terminal, capability information of a number of receive beams of the terminal;
transmitting, to the terminal, configuration information regarding channel state information-reference signal (CSI-RS); and
transmitting, to the terminal, reference signals based on the configuration information of the CSI-RS,
wherein the configuration information includes:
resource information for indicating a plurality of CSI-RS resources, and
repetition information for indicating that the reference signals on the plurality of CSI-RS resources are transmitted with a same transmit beam of the BS, and
wherein the reference signals on the plurality of CSI-RS resources are transmitted in different orthogonal frequency division multiplexing (OFDM) symbols, and
wherein the capability information is associated with a number of repetitions associated with the plurality of CSI-RS resources.

US Pat. No. 10,659,122

COMMUNICATION DEVICE AND ANTENNA SELECTION METHOD

WISTRON NEWEB CORP., Hsi...

1. A communication device for communicating with an external device, comprising:a smart antenna, wherein the smart antenna is capable of switching between a plurality of antenna modes;
a storage device; and
a processor;
wherein in each of the antenna modes during a training stage, the smart antenna transmits a first test datum and receives a first feedback datum in response to the first test datum, the processor calculates a reward indicator according to the first feedback datum, and the storage device stores the reward indicator;
wherein during a first working stage, the processor compares all of the reward indicators with each other and controls the smart antenna to select a specific mode of the antenna modes according to a comparison between all of the reward indicators;
wherein in the specific mode during the first working stage, the smart antenna transmits a second test datum and receives a second feedback datum in response to the second test datum, the processor determines a weight function of the first feedback datum and the second feedback datum of the specific mode, and the processor updates the reward indicator of the specific mode according to the weight function.

US Pat. No. 10,659,121

APPARATUS AND METHODS FOR RADIO FREQUENCY FRONT-ENDS

Skyworks Solutions, Inc.,...

1. A wireless device comprising:a plurality of antennas including a first primary antenna, a second primary antenna, a first diversity antenna, and a second diversity antenna;
a transceiver; and
a radio frequency front end system electrically coupled between the transceiver and the plurality of antennas, the radio frequency front end system including a shared power management circuit configured to output a common power amplifier supply voltage, and a plurality of ultrahigh band modules each configured to output an ultrahigh band transmit signal having a frequency content greater than about 3 gigahertz, the plurality of ultrahigh band modules including a first ultrahigh band module electrically coupled to the first primary antenna, a second ultrahigh band module electrically coupled to the second primary antenna, a third ultrahigh band module electrically coupled to the first diversity antenna, and a fourth ultrahigh band module electrically coupled to the second diversity antenna, each of the plurality of ultrahigh band modules including a power amplifier configured to receive power from the common power amplifier supply voltage.

US Pat. No. 10,659,120

COMMUNICATION APPARATUS AND COMMUNICATION METHOD

Panasonic Intellectual Pr...

1. A communication apparatus comprising:a frame generating circuit, which, in operation, generates a frame including a Header and a Short Sector Sweep Payload (Short SSW Payload) field, wherein the Header includes a Scrambler Initialization field; and
a transmitter which, in operation, transmits the generated frame, wherein
in a case of a Transmission Sector Sweep by an Initiator, the Short SSW Payload field includes a Short Scrambled Basic Service Set ID (Short Scrambled BSSID) subfield, in which a Short Scrambled BSSID is set, wherein the Short Scrambled BSSID is generated by dividing a plurality of bits that form a BSSID into a plurality of words, scrambling each of the plurality of words by using a value of the Scrambler Initialization field as a seed, applying Cyclic Redundancy Check (CRC) encoding to a consecutive concatenation of the plurality of scrambled words, and taking upper bits of a bit sequence generated by the CRC encoding.

US Pat. No. 10,659,119

METHOD FOR TRANSMITTING A REFERENCE SIGNAL, METHOD FOR DETERMINING PHASE NOISE AND RELATED APPARATUSES

China Academy of Telecomm...

1. A method for transmitting a reference signal, comprising:pre-coding, by a transmitter, each data stream, and transmitting each data stream over its corresponding one or more antenna groups, wherein antenna elements or antenna ports in a same antenna group have a same phase noise, and all antenna groups corresponding to one data stream have a same phase noise;
pre-coding, by the transmitter, a Demodulation Reference Signal (DMRS) of each DMRS port, and transmitting each DMRS over its corresponding one or more antenna groups, wherein all antenna groups corresponding to one DMRS port have a same phase noise, and one data stream corresponds to one DMRS port; and
pre-coding, by the transmitter, a Phase-Tracking Reference Signal (PTRS) of each PTRS port, and transmitting each PTRS over its corresponding one or more antenna groups, wherein all antenna groups corresponding to one PTRS port have a same phase noise, and one PTRS port corresponds to at least one DMRS port.

US Pat. No. 10,659,118

METHOD AND APPARATUS FOR EXPLICIT CSI REPORTING IN ADVANCED WIRELESS COMMUNICATION SYSTEMS

Samsung Electronics Co., ...

1. A user equipment (UE) for a channel state information (CSI) feedback in an advanced communication system, the UE comprising:a transceiver configured to receive, via a higher layer signaling from a base station (BS), CSI feedback configuration information for the CSI feedback including a spatial channel information indicator; and
at least one processor configured to determine the spatial channel information indicator using a codebook that indicates a sum of a plurality of matrices by calculating the sum as a linear combination of the plurality of matrices, wherein each matrix is a product of a coefficient and an n-dimensional basis matrix as a representation of a downlink channel matrix, where n>1,
wherein, the transceiver is further configured to transmit, to the BS, over an uplink channel, the CSI feedback including the spatial channel information indicator.

US Pat. No. 10,659,117

CODEBOOK RESTRICTION AND SUB-SAMPLING FOR CHANNEL STATE INFORMATION REPORTING

QUALCOMM Incorporated, S...

1. A method for wireless communication at a user equipment (UE), comprising:receiving, from a base station, an indication of a plurality of codebook sets, each codebook set including one or more precoding matrices for precoding downlink transmissions to the UE;
receiving, from the base station, an indication of at least one codebook set of the plurality of codebook sets to be evaluated for determining one or more preferred precoding matrices;
identifying, based at least in part on the indication of the at least one codebook set of the plurality of codebook sets, at least one set of the plurality of codebook sets to be evaluated for determining one or more preferred precoding matrices;
evaluating the one or more precoding matrices in the at least one set to determine the one or more preferred precoding matrices; and
transmitting, to the base station, a precoding matrix indicator (PMI) of the one or more preferred precoding matrices in a channel state information (CSI) report.

US Pat. No. 10,659,116

ENABLING UL-MU-MIMO WITH UL-OFDMA

CISCO TECHNOLOGY, INC., ...

1. A method by a wireless network apparatus, comprising:identifying a plurality of wireless devices associated with the wireless network apparatus;
identifying a subset of the plurality of wireless devices based on:
whether the wireless devices in the subset have a probability above a threshold to yield to each other via a clear channel assessment (CCA); and
whether the wireless network apparatus can decode uplink signals simultaneously transmitted by the wireless devices in the subset over a common uplink resource;
assigning the subset to an uplink resource, wherein the uplink resource comprises one or more sub-carriers;
separating each wireless device in the subset to each of a plurality of groups, wherein a group comprises wireless devices that are able to receive data on a common steered downlink message from the wireless network apparatus; and
transmitting, for each group, a steered downlink message indicating the assigned uplink resource for each wireless device in the group, wherein the wireless devices in each group are assigned to different uplink resources.

US Pat. No. 10,659,115

DYNAMIC ANTENNA CALIBRATION SCHEDULING

Sprint Communications Com...

1. One or more non-transitory computer-readable media having computer-executable instructions embodied thereon that, when executed, perform a method for dynamically delaying a calibration of an antenna, the method comprising:determining that there is a quantity of user devices above a predetermined threshold in a multiple user multiple input multiple output (MU-MIMO) group on the particular sector of the antenna of a base station;
determining that there is an upcoming scheduled calibration event of the antenna; and
based on the upcoming scheduled calibration event and the quantity of user devices being above a predetermined threshold in a MU-MIMO group, delaying the upcoming scheduled calibration event of the antenna.

US Pat. No. 10,659,114

MULTI-LAYERED PRECODING

Facebook, Inc., Menlo Pa...

1. A method of precoding multi-carrier signals, comprising:obtaining a transmission channel matrix of a transmission channel between a plurality of antennas of a terminal and a plurality of spatially separate users, wherein the transmission channel matrix includes channel estimates for a plurality of subcarriers of the multi-carrier signals;
wherein the terminal is one of a plurality of terminals interfaced with a central processing unit;
wherein the terminal communicates with the plurality of spatially separate user with the multi-carrier signals;
determining a precoding for the terminal based on a distribution of user signal power across the transmission channel between the terminal and the plurality of spatially separate users; and
determining a precoding for the central processing unit based on the precoding for the terminal and based on the transmission channel matrix, wherein a precoding matrix for the central processing unit is multi-carrier signal dependent.

US Pat. No. 10,659,113

MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) CONTROL IN A WIRELESS ACCESS NODE

Sprint Communications Com...

1. A method of operating a source wireless access node to serve User Equipment (UEs) over a Three-Dimensional (3D) Multiple Input Multiple Output (MIMO) antenna array and over a Two-Dimensional (2D) MIMO antenna array, the method comprising:network circuitry exchanging user data with radio circuitry;
the radio circuitry wirelessly exchanging the user data with the UEs over the 3D MIMO antenna array;
the network circuitry detecting a loss-of-synchronization for the source wireless access node;
the network circuitry detecting an interference condition at neighbor wireless access nodes;
when the interference condition at the neighbor wireless access nodes and the loss-of-synchronization at the source wireless access node occur simultaneously, the network circuitry responsively disabling the 3D MIMO antenna array and exchanging additional user data with the radio circuitry; and
the radio circuitry wirelessly exchanging the additional user data with the UEs over the 2D MIMO antenna array when the interference condition at the neighbor wireless access nodes and the loss-of-synchronization at the source wireless access node occur simultaneously.

US Pat. No. 10,659,112

USER EQUIPMENT ASSISTED MULTIPLE-INPUT MULTIPLE-OUTPUT DOWNLINK CONFIGURATION

XCOM Labs, Inc., San Die...

1. A user equipment comprising:antenna elements comprising a first antenna element; and
a processor configured to:
receive, from a base station, information identifying an active set of one or more serving nodes to provide transmission service to the user equipment;
determine a selected mode of wirelessly receiving data using the first antenna element, the selected mode being either a coordinated multipoint mode or an alternate downlink data transmission mode, wherein the processor is configured to determine that the selected mode is the coordinated multipoint mode based on a mobility measurement being less than a first threshold and channel state information variation being less than a second threshold; and
cause transmission, via at least one of the antenna elements, of a request to receive data at the first antenna element in the selected mode.

US Pat. No. 10,659,111

METHOD AND APPARATUS FOR TRANSMITTING DATA

HUAWEI TECHNOLOGIES CO., ...

1. A method for receiving data, comprising:receiving two streams and reference signals associated with the two streams, wherein at least two second resource groups are comprised in each first resource group of at least one first resource group, wherein each of the second resource groups comprises one or more time and frequency resource and is capable of bearing at least two reference signals, wherein the at least two reference signals correspond to different antenna ports, wherein the two streams are respectively mapped onto resource elements (REs) on two different antenna ports, and the reference signals associated with the streams correspond to the two different antenna ports and are respectively borne on two different second resource groups of the first resource group; and
decoding the received streams,
wherein the reference signals comprise demodulation reference signals (DMRS).

US Pat. No. 10,659,110

POSITIONAL TRACKING ASSISTED BEAM FORMING IN WIRELESS VIRTUAL REALITY SYSTEMS

Facebook Technologies, LL...

1. A head-mounted display (HMD) comprising:a transceiver configured to communicate directly with a console via a wireless channel, in accordance with a communication instruction, the communication instruction causing the transceiver to communicate a first packet with the console over a first directional beam of a plurality of directional beams; and
a controller configured to:
determine a change in a position of the HMD relative to a reference point of the console based on tracked positional information of the HMD relative to the console,
translate, by a conversion unit of the controller, the tracked positional information of the HMD and the change in the position of the HMD into a beam pointing direction of the HMD corresponding to a second directional beam different from the first directional beam by selecting the second directional beam from the plurality of directional beams covering a region in space comprising the reference point of the console,
update the communication instruction identifying the second directional beam, and
provide the updated communication instruction to the transceiver causing the transceiver switching from the first directional beam to the second directional beam for communication of a second packet with the console, wherein a latency of the beam switching is less than a time period between the change in the position of the HMD and a start of the second packet following the first packet.

US Pat. No. 10,659,109

METHOD AND APPARATUS FOR EXPANDING QUASI-COLOCATION (QCL) SIGNALING TO COVER VARIED SCENARIOS

Qualcomm Incorporated, S...

1. A method for wireless communications by a user equipment (UE), comprising:obtaining quasi-colocation (QCL) information indicating QCL assumptions for one or more types of reference signals (RS) and channels associated with different cell identifications (IDs) including at least one non-serving cell ID;
measuring the one or more types of RS; and
processing one or more of the channels, based on the RS measurements and the QCL information.

US Pat. No. 10,659,108

DIGITAL TRANSPORT OF DATA OVER DISTRIBUTED ANTENNA NETWORK

DALI WIRELESS, INC., Men...

1. A method of serializing RF data and IP data, the method comprising:receiving the RF data;
receiving the IP data at an Ethernet port;
processing the RF data to provide digital payload I & Q data;
allocating a first priority to the digital payload I & Q data;
allocating a second priority to the IP data;
transmitting the digital payload I & Q data and the IP data to a framer according to the first priority and the second priority;
framing the digital payload I & Q data and the IP data to provide framed data;
encoding the framed data;
scrambling the encoded data;
serializing the scrambled data; and
converting the serialized data to one or more optical signals.

US Pat. No. 10,659,107

SYSTEM AND METHOD FOR COMPENSATING THE EFFECTS OF DOPPLER

TOTUM LABS, INC., San Di...

1. A method comprising:estimating, by an endpoint, a first rate of change of a Doppler frequency offset during a downlink reception from a satellite associated with the Doppler frequency offset; and
applying, by the endpoint, a second rate of change of the Doppler frequency offset to an uplink transmission to the satellite, wherein the second rate of change of the Doppler frequency offset compensates the first rate of change of the Doppler frequency offset.

US Pat. No. 10,659,105

METHOD AND APPARATUS FOR ARRANGING COMMUNICATION SESSIONS IN A COMMUNICATION SYSTEM

1. A method, comprising:determining, by a processing system comprising a processor, a channel reuse pattern for adjusting characteristics of electromagnetic waves transmitted along surfaces of a plurality of transmission mediums, wherein the determining is according to an electromagnetic wave interference analysis; and
providing, by the processing system, instructions to a plurality of waveguide systems coupled to the plurality of transmission mediums to utilize the channel reuse pattern to transmit the electromagnetic waves along respective ones of the surfaces of the plurality of transmission mediums, wherein each channel of the channel reuse pattern is used for transporting data via the electromagnetic waves transmitted by the plurality of waveguide systems.

US Pat. No. 10,659,104

METHOD FOR DIAGNOSING A COMMUNICATION LINK IN A MOTOR VEHICLE

Continental Automotive Fr...

1. A method for diagnosing a status of a communication link between an interior relay antenna mounted in the passenger compartment of a motor vehicle and an exterior relay antenna mounted on a body of said motor vehicle, the status of said communication link being determined by a value of a voltage defined across terminals of a variable resistor that is connected both to an intermediate point of the communication link, located between the interior relay antenna and the exterior relay antenna, and to a first ground, said method being implemented by a diagnostic module comprising an electrical circuit including a midpoint that is connected to the interior relay antenna, a first resistor that is connected both to a voltage source and to said midpoint, and a capacitor that is connected both to the midpoint and to a second ground that is different from the first ground, the diagnostic module further comprising a second resistor that is linked to the midpoint of the electrical circuit and connected in series with a switch linked to the voltage source, the method comprising:measuring a first voltage value defined between the midpoint of the electrical circuit and the second ground when the switch is in the open position;
measuring a second voltage value defined between the midpoint of the electrical circuit and the second ground when the switch is in a closed position;
calculating a value of the variable resistor from the first measured voltage value, from the second measured voltage value, from the value of a voltage defined across terminals of the voltage source and from the values of the first resistor and of the second resistor; and
diagnosing the status of the communication link on the basis of the calculated value of the variable resistor.

US Pat. No. 10,659,103

SYNCHRONIZED MULTI-CHANNEL ACCESS SYSTEM

Entropic Communications, ...

1. A synchronized multi-channel access platform, comprising:a host processor; and
a plurality of network controllers, where each of the plurality of network controllers is associated with a communication channel,
wherein the host processor is operable to synchronize upstream and downstream operation of each of the communication channels, the communication channels occupying neighboring non-guard band separated frequency bands, by communicating control messages with the plurality of network controllers through an Ethernet switch operatively connected to the host processor via an Ethernet interface and/or through a Media Independent Interface Management Interface (MMI),
wherein each of the plurality of network controllers is operable to simultaneously send an error vector magnitude (EVM) probe in accordance with an EVM probe cycle defined by a predetermined number of beacon signal cycles encountered by each of the plurality of network controllers.

US Pat. No. 10,659,102

SYNCHRONIZATION TECHNIQUES USING FREQUENCY HOPPING IN UNLICENSED RADIO FREQUENCY SPECTRUM

QUALCOMM Incorporated, S...

1. A method for wireless communication, comprising:receiving, on a first hop frequency of a plurality of available hop frequencies in an unlicensed radio frequency spectrum band, two or more synchronization signals from a first base station;
identifying a first synchronization signal of the first base station based at least in part on the received two or more synchronization signals;
identifying, on the first hop frequency, a second synchronization signal of the first base station based at least in part on a periodicity of synchronization signal transmissions on one or more hop frequencies of the plurality of available hop frequencies; and
identifying a hopping pattern of the first base station based at least in part on the received first synchronization signal and a physical channel signal of the first base station.

US Pat. No. 10,659,101

INFORMATION PROCESSING DEVICE AND METHOD, TRANSMITTING DEVICE AND METHOD, AND RECEIVING DEVICE AND METHOD

Sony Semiconductor Soluti...

1. An information processing device, comprising:a supplying unit configured to supply identification information of a transmitting device to a plurality of receiving devices that receive a plurality of transmission signals that are transmitted from the transmitting device,
wherein the plurality of transmission signals are multiplexed and generated by the transmitting device performing chirp modulation on transmission data in the same transmission channel and shifting a transmission timing at predetermined time intervals,
wherein a selection of the transmission channel and the transmission timing is based on the identification information of the transmitting device, and
wherein the identification information of the transmitting device is a setting for receiving the plurality of transmission signals at each of the plurality of receiving devices; and
a receiving unit configured to receive the transmission data from the plurality of receiving devices,
wherein, to supply the identification information to the plurality of receiving devices, the supplying unit is further configured to supply the identification information of the transmitting device serving as a transmission source of the plurality of transmission signals that are received by the each of the plurality of receiving devices.

US Pat. No. 10,659,100

CHANNEL HOPPING BASED ON CHANNEL PERFORMANCE STATISTICS

TEXAS INSTRUMENTS INCORPO...

1. A method of generating a channel hopping sequence for a link in a wireless sensor network, the method comprising:receiving performance quality data for respective frequency channels of a plurality of frequency channels in the link in a monitoring system;
determining a channel quality indicator (CQI) by the monitoring system for each frequency channel based on the respective performance quality data; and
determining a repetition factor by the monitoring system for each frequency channel based on the respective CQI, wherein a repetition factor for a frequency channel indicates a number of times the frequency channel is repeated in the channel hopping sequence.

US Pat. No. 10,659,099

PAGE SCANNING DEVICES, COMPUTER-READABLE MEDIA, AND METHODS FOR BLUETOOTH PAGE SCANNING USING A WIDEBAND RECEIVER

Samsung Electronics Co., ...

1. A page scanning device, comprising:a memory storing computer-readable instructions; and
at least one processor communicably coupled to the memory and configured to execute the computer-readable instructions to,
select a first tone among a plurality of detected tones,
first determine whether the first tone is included within an expected hop sequence to generate a first determination result,
generate a first tone template in response to the first determination result indicating that the first tone is included within the expected hop sequence,
align the first tone template with the plurality of detected tones based on the first tone,
second determine whether the first tone template matches the plurality of detected tones to generate a second determination result, and
detect a valid frequency hopping sequence in response to the second determination result indicating that the first tone template matches the plurality of detected tones.

US Pat. No. 10,659,098

DUPLEXING APPARATUS, TRANSCEIVER APPARATUS AND METHOD OF COMPENSATING FOR SIGNAL LEAKAGE

u-blox AG, Thalwil (CH)

1. A duplexing apparatus comprising:a hybrid junction module having an antenna port, a transmit port, a receive port and a balance port;
a feedforward circuit configured to be responsive to a first transmit band of frequencies and a second transmit band of frequencies, the feedforward circuit having an input operably coupled to the transmit port of the hybrid junction module and having an output for outputting a compensation signal;
wherein the hybrid junction module is configured to substantially isolate the receive port from the transmit port with respect to the first transmit band of frequencies and substantially not isolate the receive port from the transmit port with respect to the second transmit band of frequencies; and
the feedforward circuit is configured to generate the compensation signal by propagating signal frequencies in the second transmit band over propagation of signal frequencies in the first transmit band.

US Pat. No. 10,659,097

TESTING SYSTEM

1. A testing system, comprising:a bilinear polarized antenna configured for receiving and dividing a circularly polarized radio wave associating with a horizontal polarization path and a vertical polarization path of an object-to-be-tested into a first high frequency signal and a second high frequency signal;
a first power splitter and a second power splitter electrically connected to the bilinear polarized antenna and configured for receiving from the bilinear polarized antenna the first high frequency signal and the second high frequency signal, respectively;
a first phase retarder electrically connected to the first power splitter and configured for delaying a phase of the first high frequency signal from the first power splitter by 90 degrees to form a first high frequency signal with a phase delay of 90 degrees;
a third power splitter electrically connected to the first phase retarder and the second power splitter and configured for receiving or synthesizing the first high frequency signal with the phase delay of 90 degrees from the first phase retarder and the second high frequency signal from the second power splitter; and
a first power meter electrically connected to the third power splitter and configured for measuring power of the first high frequency signal with the phase delay of 90 degrees and the second high frequency signal received or synthesized by the third power splitter and determining states of the horizontal polarization path and the vertical polarization path of the object-to-be-tested based on the power.

US Pat. No. 10,659,096

FREQUENCY SCAN WITH RADIO MAINTAINED IN ACTIVE STATE

NXP USA, Inc., Austin, T...

1. A method comprising:placing a radio of a device in an active mode, the radio comprising a phase locked loop (PLL), which in turn comprises a voltage-controlled oscillator (VCO) and a divider; and
while maintaining the radio in the active mode:
determining a first coarse frequency tuning value based on a first target frequency;
determining a first fractional divider value based on the first target frequency;
placing the PLL in an open-loop configuration;
while the PLL is in the open-loop configuration, programming the VCO with the first coarse frequency tuning value, and programming the divider with the first fractional divider value;
placing the PLL in a closed-loop configuration with the VCO programmed with the first coarse frequency tuning value and the divider programmed with the first fractional divider value;
with the VCO programmed with the first coarse frequency tuning value and the divider programmed with the first fractional divider value, performing a first operation at the radio based on an output signal of the PLL while it is in the closed-loop configuration;
determining a second coarse frequency tuning value based on a second target frequency;
determining a second fractional divider value based on the second target frequency;
placing the PLL in the open-loop configuration after performing the first operation;
while the PLL is in the open-loop configuration, programming the VCO with the second coarse frequency tuning value, and programming the divider with the second fractional divider value;
placing the PLL in the closed-loop configuration with the VCO programmed with the second coarse frequency tuning value and the divider programmed with the second fractional divider value; and
with the VCO programmed with the second coarse frequency tuning value and the divider programmed with the second fractional divider value, performing a second operation at the radio based on an output signal of the PLL while it is in the closed-loop configuration.

US Pat. No. 10,659,095

DENSITY FUNCTION CENTRIC SIGNAL PROCESSING

Alarm.com Incorporated, ...

1. An apparatus for classifying a signal as one of noise and a predetermined type of event comprising a plurality of symbols subjected to predetermined channel noise regimes, each regime represented by one or more of a plurality of temporal attributes, the apparatus comprising:a receiver configured to estimate a density function of the signal and sample the density function at a plurality of points; and
a signal processor connected to the receiver and configured to
determine a maximum number of the regimes and a minimum number of the regimes through a clustering technique,
initialize a plurality of clusters corresponding to the plurality of sampled points, based upon the maximum and minimum numbers,
process, through a clustering technique, a signal value corresponding to each of the regimes by updating parameters maintained for a cluster of the plurality of clusters,
calculate a plurality of statistical values from the updated parameters, and
classify the signal based upon the plurality of statistical values and the updated parameters.

US Pat. No. 10,659,094

ULTRA-BROADBAND MICROWAVE RADIOMETER OPTIMIZED FOR MICROSATELLITE APPLICATIONS

United States of America ...

1. A microwave radiometer with reduced volume, mass, phase noise, and power requirements and increased harmonic rejection, comprising:a fixed number of frequency banks configured to provide signals within separate, non-overlapping local oscillation frequency bands;
a detection circuit configured to receive and detect one or more microwave RF signals;
an RF downconverter connected to said detection circuit and said frequency banks, said RF downconverter configured to mix the signals within the separate, non-overlapping local oscillation frequency bands with the one or more of said microwave RF signals to provide a continuous range of down converted frequencies; and
a switched power circuit for selectively powering amplifiers of individual ones of the frequency banks.

US Pat. No. 10,659,093

MANAGING INTERFERENCE IN CONTROL CHANNELS AND METHODS THEREOF

ISCO International, LLC, ...

1. A method, comprising:obtaining, by a system comprising a processor, uplink information that describes a configuration for uplink wireless communications by a communication device, wherein the uplink information comprises a first assignment of a first resource block to the communication device for transport of control information as a physical uplink control channel (PUCCH);
performing, by the system, a first Signal to Interference plus Noise Ratio (SINR) measurement of the PUCCH;
initiating, by the system, a first corrective action responsive to detecting the first SINR measurement being below a first SINR threshold; and
initiating a second SINR measurement of the PUCCH to confirm the second SINR measurement is above the first SINR measurement;
wherein the first SINR threshold is associated with the PUCCH,
wherein the first corrective action comprises filtering adjacent signals, adjusting gain of the uplink wireless communications, filtering interference signals, utilizing diversity signal paths, adjusting a pilot signal, adjusting a modulation scheme, adjusting a coding scheme, adjusting a position of an antenna to reshape a coverage, adjusting a configuration of a device adversely affecting the first SINR measurement, or any combination thereof, and
wherein the uplink information comprises a second assignment of a second resource block for transport of data as a physical uplink shared channel (PUSCH), wherein a second SINR threshold is associated with the PUSCH, and wherein the first SINR threshold is higher than the second SINR threshold,
performing, by the system, a third SINR measurement of the PUSCH;
initiating, by the system, a second corrective action responsive to detecting the third SINR measurement being below the second SINR threshold; and
initiating a fourth SINR measurement of the PUSCH to confirm the fourth SINR measurement is above the third SINR measurement, wherein the second corrective action comprises filtering adjacent signals, adjusting gain of the uplink wireless communications, filtering interference signals, utilizing diversity signal paths, adjusting a pilot signal, adjusting a modulation scheme, adjusting a coding scheme, adjusting a position of an antenna to reshape a coverage, adjusting a configuration of a device adversely affecting the third SINR measurement, or any combination thereof.

US Pat. No. 10,659,092

CHANNEL LOSS COMPENSATION CIRCUITS

TAIWAN SEMICONDUCTOR MANU...

1. A receiver circuit, comprising:a plurality of receivers, each receiver of the plurality of receivers being associated with a carrier of a plurality of carriers;
a decoupler configured to receive a transmission signal from a transmission channel and output a plurality of divided transmission signals to the plurality of receivers; and
an equalizer configured to modify one of the transmission signal or a divided transmission signal of the plurality of divided transmission signals,
wherein the equalizer modification is based on a frequency-dependent loss of the transmission signal introduced by the transmission channel.

US Pat. No. 10,659,091

INTRINSICALLY LINEAR, DIGITAL POWER AMPLIFIER EMPLOYING NONLINEARLY-SIZED RF-DAC, MULTIPHASE DRIVER, AND OVERDRIVE VOLTAGE CONTROL

Technische Universiteit D...

1. A digitally-controlled power amplifier (DPA), comprising:a radio frequency digital-to-analog converter (RF-DAC) comprising a plurality of nonlinearly-weighted PA segments, each PA segment including one or more power transistors;
control logic configured to selectively and digitally enable and disable power transistors in the plurality of PA segments depending on a time-varying value of an input amplitude code word (ACW); and
an RF drive signal generator configured to generate one or more RF drive signals that drive those power transistors in the PA segments that have been selectively and digitally enabled by the control logic,
wherein the nonlinear weighting of the PA segments and the enabling and disabling of power transistors by the control logic are controlled in a manner that results in an amplitude of an RF output produced by the DPA being a substantially linear function of the input ACW.

US Pat. No. 10,659,090

ANALOG CIRCUIT TIME CONSTANT COMPENSATION METHOD FOR A DIGITAL TRANSMITTER USING AN ANALOG OUTPUT

ROSEMOUNT INC., Shakopee...

1. A process transmitter comprising:a circuit producing a plurality of digital values representing magnitudes for an analog signal;
a filter receiving the plurality of digital values and producing a plurality of filtered digital values;
output analog circuitry configured to receive the plurality of filtered digital values and output an analog signal on a communication channel of the process transmitter, wherein the output analog circuitry has a transfer function and wherein the filter has a transfer function that at least partially offsets the transfer function of the output analog circuitry; and
wherein the filter comprises a clipping function to limit magnitudes of the filtered digital values to a range of magnitude values supported by the output analog circuitry and an analog circuitry output emulator that estimates a latest output of the output analog circuitry based on a previous output of the clipping function.

US Pat. No. 10,659,089

DIFFERENTIAL DATA TRANSMITTER WITH PRE-EMPHASIS

1. A differential data transmitter with pre-emphasis, comprising:a single-ended input node adapted to receive an input stream of serialized data bits;
a first main driver directly coupled to said input node and arranged to produce a main differential output stream which varies with said input stream;
circuitry coupled to said single-ended input node which provides a delayed and inverted version of said input stream at a single-ended output;
a first pre-emphasis driver directly coupled to the single-ended output of said circuitry and arranged to produce a pre-emphasis differential output stream which varies with said delayed and inverted version of said input stream, said pre-emphasis differential output stream coupled to said main differential output stream to produce differential data transmitter output signals data_P and data_N at a differential data transmitter output node, said differential data transmitter output signals having associated full signal swings;
said first main and first pre-emphasis drivers operating in parallel and arranged such that said first pre-emphasis driver boosts said differential data transmitter output signals such that they provide said full signal swings when consecutive bits in said input stream change state, and to attenuate said differential data transmitter output signals such that they provide signal swings less than said full signal swings when consecutive bits in said input stream do not change state;
wherein said delayed and inverted input stream is delayed by an amount Z?1,
said first main driver comprising:
a pre-driver having a single-ended input coupled to said single-ended input node and which provides differential signals DRV_P and DRV_N at a differential output;
first cross-coupled transistors coupled to receive differential signals DRV_P and DRV_N at respective inputs and to provide differential signals main_data_P and main_data_N at respective outputs; and
first and second main output resistors Rm1 and Rm2 coupled between said first cross-coupled transistor outputs and said differential data transmitter output node;
said first pre-emphasis driver comprising:
a pre-driver having a single-ended input coupled to the single-ended output of said circuitry and which provides differential signals DRV_N*Z?1 and DRV_P*Z?1 at a differential output, said first pre-emphasis driver and said circuitry being distinct from each other;
second cross-coupled transistors coupled to receive differential signals DRV_N*Z?1 and DRV_P*Z?1 at respective inputs and to provide differential signals pre_data_N and pre_data_P at respective outputs; and
first and second pre-emphasis output resistors Rp1 and Rp2 coupled between said second cross-coupled transistor outputs and said differential data transmitter output node, such that said signal pre_data_N is coupled to said output signal data_P and said signal pre_data_P is coupled to said output signal data_N;
wherein said differential data transmitter has an associated characteristic impedance Z0 and an output impedance Zt, said differential data transmitter arranged such that said output impedance Zt matches said characteristic impedance Z0.

US Pat. No. 10,659,088

METHOD AND APPARATUS FOR MANAGING OPERATIONS OF A COMMUNICATION DEVICE

NXP USA, INC., Austin, T...

1. A method, comprising:receiving, by a wireless communication device, network condition information from a communication element that is remote from the wireless communication device, wherein the network condition information does not include settings for a variable reactance element of a matching network of the wireless communication device;
selecting, by the wireless communication device, a profile from among a plurality of profiles based on an identification of the communication element, wherein each profile of the plurality of profiles includes tuning information for the matching network;
determining, by the wireless communication device, a desired operational metric according to the network condition information;
determining, by the wireless communication device, a relative position of a body part of a user and the wireless communication device;
determining, by the wireless communication device, a use case for the wireless communication device according to relative position of the body part of the user;
determining, by the wireless communication device, a tuning state for the matching network via the tuning information of the profile according to the desired operational metric and the use case; and
adjusting, by the wireless communication device, the variable reactance element according to the tuning state to perform impedance matching.

US Pat. No. 10,659,087

COMMUNICATION CIRCUIT WITH SINGLE ELEMENT ANTENNA FOR MULTI-FREQUENCY APPLICATIONS

Schlage Lock Company LLC,...

1. A communication circuit, comprising:a single element antenna;
a plurality of signal-limiting circuits;
a high-frequency transceiver circuit adapted to be selectively coupled to the single element antenna via the plurality of signal-limiting circuits and tuned to operate at a high frequency carrier frequency; and
a low-frequency transceiver circuit adapted to be selectively coupled to the single element antenna via the plurality of signal-limiting circuits and tuned to operate at a low frequency carrier frequency;
wherein the single element antenna includes a resonant stub when the high-frequency transceiver circuit is coupled to the single element antenna and the low-frequency transceiver circuit is decoupled from the single element antenna; and
wherein one or more electromagnetic characteristics of the resonant stub are filtered by the high-frequency transceiver circuit when the high-frequency transceiver circuit is coupled to the single element antenna and the low-frequency transceiver circuit is decoupled from the single element antenna.

US Pat. No. 10,659,086

MULTI-MODE RADIO FREQUENCY CIRCUIT

Qorvo US, Inc., Greensbo...

1. A multi-mode radio frequency (RF) circuit comprising:a switchable filter circuit configured to:
pass an RF signal in a first frequency band and present a first inherent impedance outside the first frequency band at a first signal node; and
pass the RF signal in a second frequency band and present a second inherent impedance outside the second frequency band at a second signal node;
wherein the first inherent impedance is different from the second inherent impedance when the first frequency band is identical to the second frequency band;
a switching circuit coupled to an RF front-end circuit via at least one output node and comprising:
a first input node coupled to the first signal node; and
a second input node coupled to the second signal node; and
a control circuit configured to:
in a first mode, couple the first input node to the at least one output node to communicate the RF signal in the first frequency band via the at least one output node and present the first inherent impedance at the at least one output node; and
in a second mode, couple the second input node to the at least one output node to communicate the RF signal in the second frequency band via the at least one output node and present the second inherent impedance at the at least one output node.

US Pat. No. 10,659,084

SOFT DECODING FOR FLASH MEMORY

Kabushiki Kaisha Toshiba,...

1. A method of soft decoding received signals, the method comprising:defining quantisation intervals for a signal value range;
determining a number of bits detected in each quantisation interval, a number of bits in each quantisation interval that are connected to unsatisfied constraints and a probability that an error correction code is unsatisfied;
determining an overall bit error rate based on the probability that the error correction code is unsatisfied;
determining a log likelihood ratio for each quantisation interval based on the overall bit error rate, the number of bits detected in each quantisation interval and the number of bits in each quantisation interval that are connected to unsatisfied constraints; and
performing soft decoding using the log likelihood ratios.

US Pat. No. 10,659,083

SORT SYSTEM INCLUDING NORMALIZATION

XILINX, INC., San Jose, ...

1. A sort system for list decoding of a Polar codeword, comprising:a sorter circuit configured to receive and sort path metrics for coded bits of the Polar codeword, the path metrics obtained from log-likelihood ratios associated with the coded bits;
a limiter circuit configured to cull the sorted path metrics to provide a list having a subset of the path metrics to limit output paths of a list decoder; and
a normalizer circuit configured to subtract a path metric of the path metrics or a threshold metric representing a minimum metric respectively from entries in the list to provide normalized path metrics to decode the Polar codeword.

US Pat. No. 10,659,082

RECEIVING DEVICE AND RECEIVING METHOD

SONY CORPORATION, Tokyo ...

1. A decoding device, comprising:a central processing unit (CPU) configured to:
arrange a plurality of media packets of data in a first direction and a second direction, based on a forward error correction (FEC) block size of an FEC block, wherein the FEC block includes at least four media packets of the plurality of media packets in each of the first direction and the second direction;
determine, based on a packet missing pattern, a first recovery process from a plurality of recovery processes for a missing packet in the data, wherein
the data further includes a plurality of redundant packets, and
generation of the plurality of redundant packets is based on a two-dimensional XOR-based FEC encoding process;
calculate a number of rows and a number of columns associated with the plurality of media packets, wherein each row of the calculated number of rows and each column of the calculated number of columns include the missing packet of the data;
compare the calculated number of rows with the calculated number of columns;
execute, based on the comparison, the first recovery process in one of the first direction or the second direction, wherein
the first recovery process is executed in the first direction based on the calculated number of rows that is larger than the calculated number of columns, and
the first recovery process is executed in the second direction based on the calculated number of columns that is larger than the calculated number of rows; and
control a display device to display the data after the execution of the first recovery process.

US Pat. No. 10,659,081

PREPROGRAMMED DATA RECOVERY

Everspin Technologies, In...

1. A method for recovering data stored in magnetic memory cells, comprising:retrieving a first data group from the magnetic memory cells, wherein the first data group includes a first plurality of data bits and a first set of error correction code information;
retrieving a second data group from the magnetic memory cells, wherein the second data group includes a second plurality of data bits and a second set of error correction code information;
reading a third data group from the magnetic memory cells, wherein the third data group includes a third plurality of data bits and a third set of error correction code information;
after reading the first, second, and third data groups, generating a majority data group that includes a plurality of data bits and a set of error correction code information, wherein generating the majority data group includes:
for each bit in the plurality of data bits in the majority data group, determining the bit based on a majority voting scheme using a corresponding bit from each of the first, second, and third pluralities of data bits; and
for each bit in the set of error correction code information in the majority data group, determining the bit based on the majority voting scheme using a corresponding bit from each of the first, second, and third sets of error correction code information, wherein each of the first, second, and third sets of error correction code information includes at least one parity bit, wherein each of the at least one parity bit represents at least one of an even or odd parity of the respective first, second, and third plurality of data bits; and
regenerating a recovered data set using the majority data group, wherein regenerating includes correcting any existing errors detected by applying the set of error correction code information in the majority data group to the plurality of data bits in the majority data group.

US Pat. No. 10,659,080

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

Saturn Licensing LLC, Ne...

1. A method for generating a terrestrial digital television broadcast signal, the method decreasing a signal-to-noise power ratio per symbol for a selected bit error rate of the generated terrestrial digital television broadcast signal and/or expanding reception range of the terrestrial digital television broadcast signal at which the data is decodable by a receiving device for presentation to a user, the method comprising:receiving data to be transmitted in a terrestrial digital television broadcast signal;
performing low density parity check (LDPC) encoding, in an LDPC encoding circuitry, on input bits of the received data according to a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 to generate an LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the terrestrial digital television broadcast signal;
wherein the LDPC code word includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors,
the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,
the information matrix portion is represented by a parity check matrix initial value table, and
the parity check matrix initial value table, having each row indicating positions of elements ‘1’ in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity hits in the LDPC encoding, is as follows
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509 8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544 8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598
105 381 1574 4351 5452 560 3 5943 7467 7788 7933 8362 8513 8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578 8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
10 4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
10 22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 740 3 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979;
group-wise interleaving, by interleaving circuitry, the LDPC code word in units of bit groups of 360 bits to generate a group-wise interleaved LDPC code word;
wherein, in the group-wise interleaving, when an (i+1)-th bit group from a head of the generated LDPC code word is indicated b a bit group i, a sequence of bit groups 0 to 179 of the generated LDPC code word of 64800 bits is interleaved into a following sequence of bit groups49, 2, 57, 47, 31, 35, 24, 39, 59, 0, 45, 41, 55, 53, 51, 37, 33, 43, 56, 38, 48, 32, 50, 23, 34, 54, 1, 36, 44, 52, 40, 58, 122, 46, 42, 30, 3, 7, 73, 65, 145, 71, 79, 67, 69, 83, 85, 147, 63, 81, 77, 61, 5, 26, 62, 64, 74, 70, 82, 149, 76, 4, 78, 84, 80, 86, 66, 68, 72, 6, 60, 154, 103, 95, 101, 143, 9, 89, 141, 128, 97, 137, 133, 7, 13, 99, 91, 93, 87, 11, 136, 90, 88, 94, 10, 8, 14, 96, 104, 92, 132, 142, 100, 98, 12, 102, 152, 139, 150, 106, 146, 130, 27, 108, 153, 112, 114, 9, 110, 134, 116, 15, 127, 125, 123, 120, 148, 151, 113, 126, 124, 135, 129, 109, 5, 28, 158, 117, 105, 115, 111, 131, 107, 121, 18, 170, 164, 20, 140, 160, 166, 162, 119, 155, 168, 178, 22, 174, 172, 176, 16, 157, 159, 171, 161, 118, 17, 163, 21, 165, 19, 179, 177, 167, 138, 173, 156, 144, 169, and 175;mapping the group-wise interleaved LDPC code word to any one of 1024 signal points in a modulation scheme in units of 10 bits; and
transmitting, by a terrestrial broadcast transmitter, the digital television broadcast signal including the mapped group-wise interleaved LDPC code word in units of 10 bits.

US Pat. No. 10,659,079

QC-LDPC CODES

MEDIATEK INC., Hsin-Chu ...

1. A method of wireless communication of a user equipment (UE) or a base station, comprising:determining a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding;
comparing the CBS with at least one threshold;
determining, based on a result of the comparison, a Kb number that is an integer, wherein the Kb number is a first value when the CBS is greater than the at least one threshold and the Kb number is a second value when the CBS is less than or equal to the at least one threshold, the first value being different from the second value;
determining a Kp number that is an integer based on a code rate and the Kb number;
selecting a first section of a base matrix when the Kb number is the first value or a second section of the base matrix when the Kb number is the second value to generate a parity check matrix of the LDPC coding, an information portion of the parity check matrix being a first matrix formed by M number of second square matrices, M being equal to Kp multiplied by Kb, a total number of columns in the Kb number of second square matrices being equal to a total number of bits of the CBS, one or more matrices of the M number of second square matrices being circular permutation matrices;
generating the parity check matrix; and
operating an LDPC encoder or an LDPC decoder based on the parity check matrix.

US Pat. No. 10,659,078

TIMING FOR IC CHIP

TEXAS INTRUMENTS INCORPOR...

1. An integrated circuit (IC) chip comprising:an input configured to receive a first synchronization signal;
a root timer that includes an input coupled to receive a start trigger signal and an output, wherein the root timer is configured to generate a frame pulse at the output based on the start trigger signal;
a clock control unit that includes:
a first input coupled to the input of the IC chip to receive the first synchronization signal;
a second input coupled to the output of the root timer to receive the frame pulse; and
an output to provide a clock signal, wherein the clock control unit is configured to select between providing the clock signal based on the frame pulse and based on the first synchronization signal; and
a plurality of analog to digital converters (ADCs) coupled to the output of the clock control unit, each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.

US Pat. No. 10,659,077

AMENDING CIRCUIT OF CORRECTING BOUNCING MISJUDGMENT OF A KEYSWITCH

PixArt Imaging Inc., Hsi...

1. An amending circuit for correcting bouncing misjudgment of a keyswitch, the amending circuit comprising:a comparator having a first input terminal, a second input terminal and an output terminal, the first input terminal being adapted to receive a plurality of triggering signals generated by the keyswitch;
a predetermined voltage generator electrically connected to the second input terminal and adapted to generate a first predetermined voltage and a second predetermined voltage, the first predetermined voltage being larger than the second predetermined voltage, and a critical region being defined between the first predetermined voltage and the second predetermined voltage; and
a controller electrically connected to the output terminal, the controller being adapted to determine the triggering signals are generated by an actual triggering of the keyswitch when the triggering signals are higher than the critical region and further determine the keyswitch is bounced when the triggering signals are at the critical region and further determine the keyswitch is not triggered when the triggering signals are lower than the critical region, and to generate a confirming signal according to variation in an operation frequency of a polling application while a polling result of the polling application is kept at a specific level, wherein the confirming signal is used by an external processor to perform a function related to the keyswitch, variation of the triggering signals generated by the actual triggering of the keyswitch is larger than variation of the triggering signals generated by bouncing of the keyswitch due to environmental vibration.

US Pat. No. 10,659,076

REDUCING THE AMOUNT OF DATA STORED IN A SEQUENCE OF DATA BLOCKS BY COMBINING DEDUPLICATION AND COMPRESSION

EMC IP HOLDING COMPANY LL...

1. A system, comprising:a memory that stores computer executable components; and
a processor that executes the computer executable components stored in the memory, wherein the computer executable components comprise:
a data block identifier to identify, for a sequence of data blocks, a first data block in the sequence of data blocks that corresponds to first data, resulting in a first identified data block;
a deduplication component to identify, for the sequence of data blocks, a second data block in the sequence of data blocks that corresponds to the first data, resulting in a second identified data block, wherein the deduplication component replaces the second identified data block with a key value corresponding to the first identified data block; and
a compression component to compress the first identified data block, resulting in a compressed data block.

US Pat. No. 10,659,075

SUPERCONDUCTOR ANALOG TO DIGITAL CONVERTER

Hypres Inc., Elmsford, N...

1. An analog to digital converter system, comprising:an input configured to receive a signal;
a converter, configured to produce a stream of magnetic flux quanta, representing the signal as a set of parallel pulses, with an associated quantization error;
the converter being further configured to produce a residue signal representing the associated quantization error, amplified by a fluxon amplifier comprising an integral low pass filter;
a digitizer, configured to receive the residue signal representing the associated quantization error, and to produce therefrom a stream of quantized information, representing associated quantization error.

US Pat. No. 10,659,074

DELTA-SIGMA MODULATOR, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING DELTA-SIGMA MODULATOR

SONY SEMICONDUCTOR SOLUTI...

1. A delta-sigma modulator, comprising:a filter configured to:
integrate a difference between an input analog signal and a feedback signal; and
output the integrated difference as an integrated signal;
a preceding-stage quantizer configured to:
quantize the integrated signal into a first digital signal; and
output the first digital signal as a preceding-stage output signal;
an adder configured to:
add a determined dithering signal to the preceding-stage output signal; and
output a resulting signal based on the addition as a subsequent-stage input signal;
a subsequent-stage quantizer configured to:
re-quantize the subsequent-stage input signal into a second digital signal of a shorter number of bits than the preceding-stage output signal; and
output the second digital signal as a subsequent-stage output signal; and
a digital-to-analog converter configured to:
convert the subsequent-stage output signal into a resulting analog signal; and
output the resulting analog signal to the filter as the feedback signal.

US Pat. No. 10,659,073

SEMICONDUCTOR INTEGRATED CIRCUITRY

SOCIONEXT INC., Yokohama...

1. Semiconductor integrated circuitry, comprising:a global reference node;
a distribution circuit;
a plurality of operating units each comprising a local regulation circuit, a local reference node and operating circuitry, and each operating unit being operable to carry out an operation dependent on a reference signal provided at its local reference node; and
reference regulation circuitry which comprises the local regulation circuits and is connected to provide respective reference signals at the local reference nodes, the reference regulation circuitry generating a control signal,
wherein, for each of the operating units, the local regulation circuit has an input terminal connected to receive the control signal from the reference regulation circuitry and is configured to regulate a voltage level of a reference signal at the local reference node based on the received control signal;
the input terminal of the local regulation circuit has a high input impedance so that a relatively low amount of current is drawn from the reference regulation circuitry by the input terminal; and
the local regulation circuit is configured to draw a relatively high amount of current from a voltage supply and provide that current to the operating circuitry concerned at the local reference node,
and wherein:
the distribution circuit comprises signal paths which connect the local reference nodes of the operating circuits to the global reference node to enable current drawn at the local reference nodes by the operating circuitry of the operating units to be drawn from the global reference node; and
for each operating unit, the local regulation circuit is configured to draw said relatively high amount of current from the voltage supply and provide that current to the operating circuitry concerned at the local reference node so that a part of a current drawn by the operating circuitry from the local reference node is provided from the voltage supply by the local regulation circuit rather than from the global reference node.

US Pat. No. 10,659,072

TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER WITH CALIBRATION

Intel Corporation, Santa...

1. An apparatus comprising:an analog-to-digital converter (ADC) having an input to receive an analog signal and an output to provide a digital representation of the analog signal;
a multiplexer coupled to the output of the ADC, wherein the multiplexer is to select between a first and second calibration mode;
a first circuitry coupled to an output of the multiplexer, wherein the first circuitry is to determine a maximum value of the output of the multiplexer; and
a second circuitry coupled to an output of the multiplexer, wherein the second circuitry is to determine a minimum value of the output of the multiplexer.

US Pat. No. 10,659,071

HIGH BANDWIDTH OSCILLOSCOPE

TELEDYNE LECROY, INC., T...

1. An electronic instrument for signal acquisition, comprising:a first input adapted to receive a first input signal;
a first digitizer that has a first bandwidth;
a second input adapted to receive a second input signal;
a second digitizer that has a second bandwidth and that is connected to the second input;
a switch adapted to change the first digitizer from:
(a) connecting to the first input, to
(b) connecting to the second input;
a user-selectable button adapted to activate the switch and change the first digitizer from connecting to the first input to connecting to the second input, resulting in the second input signal being provided to both the first digitizer and the second digitizer; and
a combiner adapted to combine an output of the first digitizer and an output of the second digitizer, when the second input signal is provided to both the first digitizer and the second digitizer, to generate an output signal that has been digitized using the first digitizer and the second digitizer, the output signal having a bandwidth that exceeds the first bandwidth of the first digitizer and that exceeds the second bandwidth of the second digitizer.

US Pat. No. 10,659,070

DIGITAL TO ANALOG CONVERTER DEVICE AND CURRENT CONTROL METHOD

REALTEK SEMICONDUCTOR COR...

1. A digital-to-analog converter (DAC) device, comprising:a DAC circuitry, comprising:
a first DAC circuit configured to generate a first signal according to a plurality of least significant bits of an input signal, wherein the input signal is generated by processing digital data according to a system clock signal; and
a second DAC circuit configured to output a second signal according to a plurality of most significant bits of the input signal,
wherein a ratio is present between a first turn-on time of at least one current source circuit in the first DAC circuit and the system clock signal, and the ratio is configured to set the first signal.

US Pat. No. 10,659,069

BACKGROUND CALIBRATION OF NON-LINEARITY OF SAMPLERS AND AMPLIFIERS IN ADCS

ANALOG DEVICES, INC., No...

1. A calibration system with efficient error estimation, comprising:dither circuitry to inject a dither at an input of a circuit and to remove the dither at an output of the circuit;
counting circuitry to count a first number of samples of the output corresponding to a first value of the dither falling within a range defined by an inspection point of the output, and count a second number of samples of the output corresponding to a second, different value of the dither falling within the range defined by the inspection point of the output;
error circuitry to compare the first number and the second number, and determine an error estimate based on the comparison; and
calibration circuitry to drive the error estimate towards zero.

US Pat. No. 10,659,068

DA CONVERTER, DA CONVERTING METHOD, ADJUSTING APPARATUS, AND ADJUSTING METHOD

Asahi Kasei Microdevices ...

1. A DA converter comprising:a DA converting unit to input a reference voltage and a digital value and output an analog signal according to the digital value based on the reference voltage; and
a superimposing unit to superimpose, on the reference voltage, a superimposing signal having a basic wave component of the analog signal.

US Pat. No. 10,659,067

ALKALI-METAL VAPOR CELL ATOMIC CLOCK SYSTEM

TSINGHUA UNIVERSITY, Bei...

1. An alkali-metal vapor cell atomic clock system, comprising:a crystal oscillator;
a frequency synthesizer connected with the crystal oscillator;
a proportional-integral-derivative controller connected with the crystal oscillator;
a laser generating device, wherein a frequency signal emitted by the crystal oscillator is converted into a microwave signal by the frequency synthesizer, and the microwave signal is input into the laser generating device, to modulate a laser beam emitted by the laser generating device;
a first atomic vapor cell and a second atomic vapor cell, wherein the laser beam emitted by the laser generating device is divided into a first laser signal entering the first atomic vapor cell and a second laser signal entering the second atomic vapor cell, and the first atomic vapor cell and the second atomic vapor cell are both alkali-metal atomic vapor cells;
a digital signal processor connected with the laser generating device and the proportional-integral-derivative controller respectively, wherein the digital signal processor outputs a first time sequence to control the first laser signal, and the digital signal processor outputs a second time sequence to control the second laser signal; and
a photoelectric sensing device connected with the digital signal processor, wherein the photoelectric sensing device is configured to receive optical signals respectively output from the first atomic vapor cell and the second atomic vapor cell, convert the optical signals into electrical signals, and transmit the electrical signals to the digital signal processor, the digital signal processor calculates a correction signal according to the electrical signals; the proportional-integral-derivative controller adjusts an output frequency signal of the crystal oscillator according to the correction signal.

US Pat. No. 10,659,066

ATOMIC OSCILLATOR

Seiko Epson Corporation, ...

1. An atomic oscillator comprising:an atom cell that accommodates an alkali metal atom therein;
a container that accommodates the atom cell therein;
a heating device that is disposed adjacent the container and is configured to heat the atom cell;
a substrate on which the container is disposed; and
a positioning member that is disposed on the substrate and positions the container relative to the substrate,
wherein the atom cell is pressed against the container toward the heating device, and
the heating device is pressed against the container toward the atom cell, and the container is in turn pressed against the positioning member.

US Pat. No. 10,659,065

APPARATUS AND METHODS FOR PHASE SYNCHRONIZATION OF PHASE-LOCKED LOOPS

ANALOG DEVICES, INC., No...

1. A frequency synthesizer system with phase synchronization, the frequency synthesizer system comprising:a fractional-N phase-locked loop (PLL) configured to receive a reference clock signal at an input and to generate an output clock signal at an output, the fractional-N PLL including an input phase detector configured to compare the reference clock signal to a feedback clock signal; and
a phase synchronization circuit comprising:
an output phase detector configured to generate an output phase detection signal based on comparing the output clock signal to the reference clock signal used by the input phase detector of the fractional-N PLL; and
a phase adjustment control circuit configured to generate a phase adjustment signal based on accumulating the output phase detection signal,
wherein the phase synchronization circuit is configured to provide a phase adjustment to the fractional-N PLL based on the phase adjustment signal so as to synchronize the fractional-N PLL.

US Pat. No. 10,659,064

PHASE LOCK LOOP CIRCUITS AND METHODS INCLUDING MULTIPLEXED SELECTION OF FEEDBACK LOOP OUTPUTS OF MULTIPLE PHASE INTERPOLATORS

Marvell Asia Pte, Ltd., ...

1. A phase lock loop circuit comprising:a phase frequency detector to (i) compare a phase of a reference clock signal to a phase of a frequency divided output signal, and (ii) generate an error signal based on the comparison;
a voltage controlled oscillator to, based on the error signal, generate a phase lock loop output signal and a plurality of output clock signals;
a phase interpolator to phase interpolate the plurality of output clock signals to generate an interpolator output signal;
a clock signal selector to select one of the plurality of output clock signals;
a selection module to
receive the interpolator output signal and the one of the plurality of output clock signals, and
generate a selection signal based on (i) a state of the interpolator output signal, and (ii) a state of the selected one of the plurality of output clock signals;
a multiplexer to, based on the selection signal, select the interpolator output signal or the selected one of the plurality of output clock signals; and
a divider to frequency divide an output of the multiplexer to provide the frequency divided output signal.

US Pat. No. 10,659,063

ADAPTIVE VOLTAGE FREQUENCY SCALING FOR OPTIMAL POWER EFFICIENCY

NVIDIA CORPORATION, Sant...

1. An adaptive voltage and frequency scaling (AVFS) system comprising:a clock signal generator configured to generate a frequency in an integrated circuit (IC);
a voltage regulator configured to control a current voltage level in the IC;
a look-up-table (LUT) configured to determine a maximum frequency available under the current voltage level in the IC; and
a voltage requestor configured to compare a software-requested frequency and the maximum frequency, to determine a difference between the software-requested frequency and the maximum frequency, and to generate a new voltage request based on the difference,
wherein the voltage regulator is further configured to adjust the current voltage level to substantially approximate the new voltage request in response to the new voltage request,
further wherein, the clock signal generator is configured to adjust the frequency in the IC to substantially approximate the software-requested frequency in response to an adjustment in the current voltage level,
wherein the LUT is configured to determine the maximum frequency based on a plurality of current operating conditions, the plurality of current operating conditions being measured using plurality of sensors; and
a plurality of pulse skippers configured to modulate a frequency of the clock signal, wherein the frequency generated by the clock signal generator is adjusted by controlling an operation of the plurality of pulse skippers.

US Pat. No. 10,659,062

PLL CIRCUIT

MITSUBISHI ELECTRIC CORPO...

1. A PLL circuit comprising:a voltage-controlled oscillator to transmit a frequency signal corresponding to a voltage of a supplied signal;
a frequency divider to perform frequency dividing on an output of the voltage-controlled oscillator;
a phase frequency comparator to compare an output of the frequency divider with a reference signal;
a first charge pump to output a signal corresponding to a result of the comparison performed by the phase frequency comparator;
a loop filter to supply a signal obtained by smoothing the output signal of the first charge pump to the voltage-controlled oscillator;
a lock detector to detect a locked state and an unlocked state from an output of the phase frequency comparator;
a counter to be reset when an output of the lock detector switches from the locked state to the unlocked state, and to count the reference signal while the unlocked state is being detected;
a D/A converter to generate a signal to be added to an output of the loop filter;
a switch to switch whether to supply an output signal of the D/A converter; and
a parameter controlling circuit to acquire a count value of the counter, and control switching on and off of the switch and an output voltage of the D/A converter so that the count value of the counter is restricted within a set value.

US Pat. No. 10,659,061

DIVIDER-LESS FRACTIONAL PLL ARCHITECTURE

Intel Corporation, Santa...

1. A fractional digital phase locked loop (PLL), comprising:a time-to-digital converter (TDC) to receive a reference clock signal and a digitally controlled oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal;
a counter coupled in parallel to the TDC, the counter to receive the DCO clock signal and count an output frequency of the DCO clock signal to detect reference noise within the reference clock signal that is above a threshold level;
a sampler to sample an output of the counter using a replica of the reference clock signal, and generate a plurality of samples;
a sample selector to select one of the plurality of samples based on the phase difference signal output from the TDC; and
a digital phase detector (DPD) to generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.

US Pat. No. 10,659,060

SPUR CANCELLATION WITH ADAPTIVE FREQUENCY TRACKING

Silicon Laboratories Inc....

1. A method for tracking spur frequency comprising:generating a spur cancellation signal with a first phase using a target spur frequency;
determining the first phase of the spur cancellation signal with the first phase from a first sample of parameters used in generating the spur cancellation signal with the first phase;
generating the spur cancellation signal with a second phase;
determining the second phase from a second sample of parameters used in determining the spur cancellation signal with the second phase;
determining a phase difference between the first phase and the second phase;
updating the target spur frequency to an updated target spur frequency based on the phase difference; and
generating an updated spur cancellation signal using the updated target spur frequency.

US Pat. No. 10,659,059

MULTI-PHASE CLOCK GENERATION CIRCUIT

TEXAS INSTRUMENTS INCORPO...

1. A multi-phase clock generation circuit, comprising:a first delay circuit including first and second delay outputs, a second delay circuit including third and fourth delay outputs, and a third delay circuit including a fifth delay output, in which the first, second and third delay circuits are coupled in series;
a first clock mixer circuit including:
a first differential amplifier including first and second input terminals and first and second output terminals, the first input terminal coupled to the first delay output, and the second input terminal coupled to the second delay output; and
a second differential amplifier including third and fourth input terminals and third and fourth output terminals, the third input terminal coupled to the third delay output, the fourth input terminal coupled to the fourth delay output, the third output terminal coupled to the first output terminal, and the fourth output terminal coupled to the second output terminal; and
a second clock mixer circuit including fifth and sixth input terminals, the fifth input terminal coupled to the third delay output or to the fourth delay output, and the sixth input terminal coupled to the fifth delay output.

US Pat. No. 10,659,058

SYSTEMS AND METHODS INVOLVING LOCK LOOP CIRCUITS, DISTRIBUTED DUTY CYCLE CORRECTION LOOP CIRCUITRY

GSI TECHNOLOGY, INC., Su...

1. A locked loop circuitry, comprising:a main loop comprising:
a first lock loop circuit that generates a signal;
a duty cycle adjust circuit coupled to the first lock loop circuit that receives two control signals to adjust a duty cycle of the signal from the first lock loop and output a clock signal; and
a clock tree coupled to the duty cycle adjust circuit that outputs a clock signal fed back to the first lock loop circuit;
a duty cycle detection circuit outside of the main loop coupled to the clock signal output from the clock tree that generates a signal proportional to a duration of a high pulse of the clock signal and a signal portional to a duration of a low pulse of the clock signal and generates the two control signals in response to a detected duty cycle of the clock signal, wherein a first of the two control signals increases when the signal proportional to the duration of a high pulse of the clock signal is larger than the signal portional to a duration of a low pulse of the clock signal and a second of the two control signal decreases; and
wherein the duty cycle adjust circuit adjusts the duty cycle of the signal from the first lock loop in response to the first and second control signals.

US Pat. No. 10,659,057

COMPENSATION TECHNIQUE FOR THE NONLINEAR BEHAVIOR OF DIGITALLY-CONTROLLED OSCILLATOR (DCO) GAIN

Taiwan Semiconductor Manu...

1. A method for controlling a digitally controlled oscillator (DCO), the method comprising:generating a first normalized tuning word (NTW) corresponding to a first channel of a plurality of channels;
generating a plurality of normalizing gain multipliers, including a first normalizing gain multiplier X, using a multiplexer, based on a reference frequency fR and a nonlinear function of frequency of a digitally controlled oscillator or an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel;
multiplying the first NTW by the first normalizing gain multiplier X to obtain a first oscillator tuning word (OTW); and
inputting the first OTW to the DCO to cause the DCO to hop to the first channel.

US Pat. No. 10,659,056

GRAY CODE COUNTING SIGNAL DISTRIBUTION SYSTEM

OmniVision Technologies, ...

1. A counter distribution system, comprising:an N bit counter to receive a first counting clock, wherein N bit counter is coupled to generate a plurality of data bits including a plurality of lower data bits and a plurality of upper data bits, wherein upper data bits include at least one redundant bit to provide error correction for the counter distribution system, wherein the N bit counter is coupled to generate the plurality of lower data bits on a plurality of lower data bit lines, wherein the N bit counter is further coupled to generate the plurality of upper data bits on a plurality of upper data bit lines; and
a plurality of latches coupled to the N bit counter, wherein each one of the plurality of lower bit data lines and each one of the plurality of upper bit data lines is coupled to at least one of a plurality of latches, wherein the plurality of latches is arranged into a plurality of groupings of latches, wherein each grouping of latches is coupled to a respective one of a plurality of latch enable signals, wherein each latch in each grouping of latches is coupled to latch a respective one of the plurality of data bits in response to the respective latch enable signal.

US Pat. No. 10,659,055

TWO STAGE GRAY CODE COUNTER WITH A REDUNDANT BIT

OmniVision Technologies, ...

1. An N bit counter having lower bits and upper bits, the N bit counter comprising:a lower counter having a first output, wherein the first output has M bits, wherein N is greater than M, wherein the lower counter operates at a first counting frequency;
an upper counter having a second output, wherein the second output has N?M+L bits, wherein L is greater than or equal to one, wherein the second output has N?M most significant bits (MSBs) and L least significant bits (LSBs), wherein the upper counter operates at a second counting frequency, wherein the second counting frequency is equal to the first counting frequency divided by 2(M-L); and
an error correction controller coupled to receive the first output and the second output after a counting operation of the lower counter and the upper counter, wherein the error correction controller includes logic that when executed causes the error controller to perform operations, including:
comparing the L LSBs of the second output and at least one most significant bit (MSB) of the first output; and
correcting the N?M MSBs of the second output in response to the comparison of the L LSBs of the second output and the at least one MSB of the first output, wherein the lower bits of the N bit counter are the M bits of the first output, and wherein the upper bits of the N bit counter are the corrected N?M MSBs of the second output.

US Pat. No. 10,659,054

TRUSTED MONOTONIC COUNTER USING INTERNAL AND EXTERNAL NON-VOLATILE MEMORY

NXP B.V., Eindhoven (NL)...

1. A device, comprising:an unsecure non-volatile memory;
a secure device including:
a processor; and
a secure non-volatile memory;
wherein the secure device is configured to:
calculate a trusted monotonic counter (TMC) value from an offset and a base value;
store a TMC version value in the secure non-volatile memory and the unsecure non-volatile memory, wherein the TMC version value is updated when the TMC value is incremented the first time after the secure device is powered up;
store the base value in the unsecure non-volatile memory;
store the offset value in the unsecure non-volatile memory when the secure device is in a system power down state;
store the offset value in the secure non-volatile memory when the secure device is in a rescue state, wherein the rescue state is reached in response to secure device being in the system power down state; and
store a TMC link value in the unsecure memory, wherein the TMC link value is based upon the base value and TMC version value stored in the unsecure memory, wherein the secure non-volatile memory is more efficiently used and rollback protection is provided.

US Pat. No. 10,659,053

LIVE POWER ON SEQUENCE FOR PROGRAMMABLE DEVICES ON BOARDS

Honeywell International I...

1. A method of controlling a power-on sequence for an electronic system on a board, comprising:providing a system comprising a printed circuit board (PCB) including at least one programmable logic device (PLD), a memory, and a live power ON sequence algorithm stored in said memory, and other electronics, wherein said PLD is connected to a primary DC power supply that beginning at a first time receives power from primary DC power supply wiring for providing DC power to said PLD, comprising:
configuring said PLD using a configuration memory device having stored PLD configuration information, wherein upon completion of said configuring, said PLD generates a PLD control signal at its output to indicate said configuration of said PLD is complete and said PLD is in its active operation mode;
at a second time after said configuration of said PLD is complete power coupling comprising coupling said primary DC power supply to a power input of an electronic switch,
wherein said PLD control signal is used as an enable signal that controls power initially arriving through said electronic switch to all of said other electronics, and
wherein said primary DC power supply comprises a plurality of primary DC power supplies each having a plurality of DC levels to said PLD and to said other electronics using a plurality of said electronic switches,
wherein coupling said primary DC power supply wiring to a power input of a second DC power supply and said second power supply comprises a plurality of said second power supplies for supplying power with a plurality of DC levels to said other electronics.

US Pat. No. 10,659,052

REGIONAL PARTIAL RECONFIGURATION OF A PROGRAMMABLE DEVICE

Intel Corporation, Santa...

1. A method for configuring a programmable device, comprising:identifying a resource in a programmable fabric of the programmable device as belonging to a partition;
creating an indication of which portion of the partition the identified resource belongs; and
reconfiguring the identified resource, via a configuration controller, in the programmable fabric based at least in part on the indication without changing an additional resource associated with another partition in the programmable fabric, wherein the identified resource is reconfigured at runtime of the programmable device after configuration data is received by the programmable device.

US Pat. No. 10,659,051

BIDIRECTIONAL VOLTAGE TRANSLATOR WITH PULSE WIDTH CONTROL

NXP USA, Inc., Eindhoven...

1. A bidirectional voltage translator, comprising:a first one-shot circuit that receives a first voltage signal V1 and
(i) generates a first pulse signal P1 when the first voltage signal V1 transitions from a first low state to a first high state, and
(ii) generates a first driver signal D1 based on the first pulse signal P1 and a duration of the first voltage signal (Tv1),
wherein the duration of the first voltage signal (Tv1) is a time duration for which the first voltage signal V1 remains in the first high state, and
wherein a second voltage signal V2 is generated based on the first driver signal D1; and
a second one-shot circuit that receives the second voltage signal V2 and
(i) generates a second pulse signal P2 when the second voltage signal V2 transitions from a second low state to a second high state, and
(ii) generates a second driver signal D2 based on the second pulse signal P2 and a duration of the second voltage signal (Tv2),
wherein the duration of the second voltage signal (Tv2) is a time duration for which the second voltage signal V2 remains in the second high state, and
wherein the first voltage signal V1 is generated based on the second driver signal D2;
wherein the first one-shot circuit comprises:
a first monostable multi-vibrator that receives the first voltage signal V1 and generates the first pulse signal P1 when the first voltage signal V1 transitions from the first low state to the first high state;
a first feedforward signal generator that receives the first voltage signal V1 and generates a first feedforward signal F1 based on the duration of the first voltage signal duration (Tv1); and
a first driver circuit connected to the first multi-vibrator and the first feedforward signal generator for receiving the first pulse signal P1 and the first feedforward signal F1, respectively, and generating the first driver signal D1.

US Pat. No. 10,659,050

LEVEL SHIFTER AND SEMICONDUCTOR DEVICE

WINBOND ELECTRONICS CORP....

1. A level shifter, comprising:a first PMOS transistor, wherein an electrode of the first PMOS transistor is provided with a voltage having a first voltage level, another electrode of the first PMOS transistor is coupled to a first node and a gate of the first PMOS transistor is coupled to a second node;
a second PMOS transistor, wherein an electrode of the second PMOS transistor is provided with the voltage having the first voltage level, another electrode of the second PMOS transistor is coupled to the second node, and a gate of the second PMOS transistor is coupled to the first node;
a first NMOS transistor, which is an intrinsic-type transistor, wherein an electrode of the first NMOS transistor is coupled to the first node, another electrode of the first NMOS transistor is provided with a first enable signal, and a gate of the first NMOS transistor is coupled to a first control signal;
a second NMOS transistor, which is an intrinsic-type transistor, wherein an electrode of the second NMOS transistor is coupled to the second node, another electrode of the second NMOS transistor is provided with a second enable signal having a logic level that is an inverse of that of the first enable signal, and a gate of the second NMOS transistor is coupled to a second control signal;
an input node, configured to receive an input signal having a second voltage level or a third voltage level;
a control circuit, driven by the second voltage level and configured to generate the first control signal and the second control signal according to the input signal; and
an output node, configured to output an output signal having the first voltage level or the third voltage level in response to the input signal,
wherein when the first NMOS transistor is turned on to charge the first node and after a first predetermined period of time, the first NMOS transistor is turned off in response to the first control signal, and when the second NMOS transistor is turned on to charge the second node and after a second predetermined period of time, the second NMOS transistor is turned off in response to the second control signal, and
wherein the control circuit comprises a delay circuit configured to generate the first control signal and the second control signal according to the input signal, and wherein the delay circuit generates the first control signal and the second control signal according to the charge time of the first node and the second node for being charged via the first NMOS transistor and the second NMOS transistor.

US Pat. No. 10,659,049

LEVEL SHIFTING CIRCUIT

BOE TECHNOLOGY GROUP CO.,...

1. A level shifting circuit, comprising a boost subcircuit and a first phase-inverting subcircuit, whereinthe boost subcircuit has a first terminal being coupled to an input terminal of the level shifting circuit, a second terminal being coupled to a first high level signal terminal, a third terminal being coupled to a low level signal terminal, a fourth terminal being directly coupled to a first terminal of the first phase-inverting subcircuit; the boost subcircuit is configured to electrically connect the second terminal and the fourth terminal of the boost subcircuit when the input terminal of the level shifting circuit receives one of a high level signal and a low level signal, and to electrically connect the third terminal and the fourth terminal of the boost subcircuit when the input terminal of the level shifting circuit receives the other of the high level signal and the low level signal; a voltage of the high level signal received by the input terminal of the level shifting circuit is smaller than a voltage of a signal at the first high level signal terminal;
the first phase-inverting subcircuit has a second terminal being coupled to the first high level signal terminal, a third terminal being coupled to the low level signal terminal, and a fourth terminal being coupled to a first output terminal of the level shifting circuit; the first phase-inverting subcircuit is configured to electrically connect the third terminal and the fourth terminal of the first phase-inverting subcircuit when the first terminal of the first phase-inverting subcircuit receives a high level signal, and to electrically connect the second terminal and the fourth terminal of the first phase-inverting subcircuit when the first terminal of the first phase-inverting subcircuit receives a low level signal;
a first current limiting subcircuit is provided between the second terminal and the fourth terminal of the first phase-inverting subcircuit, or between the third terminal and the fourth terminal of the first phase-inverting subcircuit, and the first current limiting subcircuit is configured to limit a current flowing therethrough such that a maximum value of the current does not exceed a first predetermined value,
wherein the first phase-inverting subcircuit comprises:
a first P-type transistor having a gate electrode being coupled to the first terminal of the first phase-inverting subcircuit, a first electrode being coupled to the second terminal of the first phase-inverting subcircuit, and a second electrode being coupled to the fourth terminal of the first phase-inverting subcircuit; and
a first N-type transistor having a gate electrode being coupled to the first terminal of the first phase-inverting subcircuit, a first electrode being coupled to the fourth terminal of the first phase-inverting subcircuit, and a second electrode being coupled to the third terminal of the first phase-inverting subcircuit,
wherein the boost subcircuit is configured to electrically connect the second terminal and the fourth terminal of the boost subcircuit when the first terminal thereof receives a high level signal;
the first current limiting subcircuit comprises a second N-type transistor, the second N-type transistor has a gate electrode being coupled to a first current limiting control terminal, a first electrode being coupled to the fourth terminal of the first phase-inverting subcircuit, and a second electrode being coupled to the first electrode of the first N-type transistor; the first current limiting control terminal is configured to provide a low level signal to turn off the second N-type transistor when the input terminal of the level shifting circuit receives a low level signal, and to provide a high level signal enabling the second N-type transistor to be in a saturation region when the input terminal of the level shifting circuit receives a high level signal; and the first predetermined value is a magnitude of a driving current between the first electrode and the second electrode of the second N-type transistor when the second N-type transistor is in the saturation region.

US Pat. No. 10,659,048

MIXED SIGNAL SYSTEM

InvenSense, Inc., San Jo...

1. A mixed signal system comprising:a digital domain; and
an analog domain comprising a plurality of block of addressable registers (BARs), wherein each BAR of the plurality of BARs comprises at least one or more addressable registers,
wherein the digital domain comprises an interface configured to communicate with the analog domain, wherein the interface is configured to write data to an addressable register within a BAR of the plurality of BARs in the analog domain by transmitting a first select signal configured to select a first BAR of the plurality of BARs, and wherein the interface is further configured to transmit an address of the addressable register of the first BAR and wherein the interface is further configured to broadcast the write data to the first BAR and further to at least one BAR other than the first BAR of the plurality of BARs, and
wherein the analog domain is configured to transmit data from a second BAR of the plurality of BARs to the digital domain by gating a select BAR signal associated with each BAR of the plurality of BARs with its corresponding content stored therein to form a respective BAR output and further by gating the respective BAR outputs with one another, wherein gating the select BAR signal associated with the second BAR and its content generates a non-zero respective BAR output and wherein gating the select BAR signal associated with BARs of the plurality of BARs other than the second BAR generates a zero output.

US Pat. No. 10,659,047

OUTPUT DRIVING CIRCUIT

SK hynix Inc., Gyeonggi-...

1. An output driving circuit, comprising:a pad coupled to at least two resistors, a voltage of the pad changing based on a clock signal;
a pull-down driver including at least two transistors sequentially coupled in series between the pad and a ground node, a first transistor of the at least two transistors being adjacent to the ground node, and a second transistor of the at least two transistors being adjacent to the pad;
an input/output control logic configured to receive the clock signal and an enable signal, and transfer a control signal to a gate electrode of the first transistor;
a gate control logic configured to receive a voltage of the pad and output a feedback voltage to a gate electrode of the second transistor; and
an inverter configured to invert the enable signal and transfer an inverted enable signal to the gate control logic,
wherein the gate control logic includes at least two transistors including third and fourth transistors coupled in series between a first resistor and a first supply voltage node, the first resistor is one of the at least two resistors, the third transistor of the at least two transistors is adjacent to the pad and receives the first supply voltage, and the fourth transistor of the at least two transistors is adjacent to the first supply voltage node and receives the inverted enable signal.

US Pat. No. 10,659,046

LOCAL CELL-LEVEL POWER GATING SWITCH

Intel Corporation, Santa...

1. An apparatus comprising:a plurality of logic cells of an integrated circuit die, each logic cell having a data input line and a data output line and a power supply input to receive power to drive circuits of the logic cell; and
a power switch for each logic cell coupled between a power supply and the power supply input of the respective logic cell to control power being connected from the power supply to the respective logic cell, wherein the power switch switches between allowing or preventing power flow to the respective logic cell, wherein the power switch is a back end transistor formed in one or more interconnect layers of the integrated circuit die over the respective logic cell, and wherein the power switch is vertically integrated within a cell layout footprint of the respective logic cell.

US Pat. No. 10,659,045

APPARATUS WITH ELECTRONIC CIRCUITRY HAVING REDUCED LEAKAGE CURRENT AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An apparatus, comprising:an integrated circuit (IC), comprising:
complementary metal oxide semiconductor (CMOS) circuitry comprising a p-channel transistor network comprising at least one p-channel transistor having a gate-induced drain leakage (GIDL) current; and
a first native metal oxide semiconductor (MOS) transistor coupled to supply a first bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

US Pat. No. 10,659,044

ON-DISPLAY-SENSOR STACK

BOE Technology Group Co.,...

9. An electronic display comprising:a display stack comprising a plurality of layers, the plurality of layers comprising a cover layer; and
a plurality of electrodes of a touch sensor disposed on one or more of the plurality of layers of the display stack other than the cover layer of the display stack, wherein:
the one or more of the plurality of layers of the display stack on which the plurality of electrodes are disposed comprises a first layer within the display stack;
the plurality of electrodes comprise first electrodes disposed on the first layer within the display stack on a first side of the first layer and second electrodes disposed on the first layer within the display stack on a second side of the first layer such that the first electrodes and the second electrodes directly contact the first layer, the first layer being a single substrate made of a same material;
the first electrodes disposed on the first layer within the display stack on the first side of the first layer are positioned nearer to the cover layer of the display stack than the first layer within the display stack on which the first electrodes are disposed; and
the second electrodes disposed on the second side of the first layer within the display stack comprise one or more electrodes configurable to operate as sense electrodes.

US Pat. No. 10,659,043

PROXIMITY SENSOR

Hitachi Metals, Ltd., To...

1. A proximity sensor, comprising:a sensor cable that comprises a first electrode wire and a second electrode wire arranged parallel to each other, an insulation covering both the first electrode wire and the second electrode wire, and a shield partially covering a surface of the insulation so as to form an opening, the shield comprising a composite tape formed by laminating a base comprising an insulating resin and a metal layer comprising a conductive metal, the first electrode wire and the second electrode wire being arranged to have different distances to the opening; and
a detector circuit that comprises a first capacitance detecting portion for detecting a first capacitance to be detected by the first electrode wire, a second capacitance detecting portion for detecting a second capacitance to be detected by the second electrode wire, and a differential output portion for outputting a difference between the first capacitance and the second capacitance;
wherein a plurality of slits are formed on the metal layer of the composite tape at predetermined intervals, and the composite tape is spirally wound around the sensor cable so that the plurality of slits are lined up along the longitudinal direction of the sensor cable and form an opening.

US Pat. No. 10,659,042

DEVICE HAVING AN OPTICALLY SENSITIVE INPUT ELEMENT

Biovotion AG, Zurich (CH...

1. A device comprising a housing (1) and a user-operatable input element (14), wherein said input element (14) comprises at least one photodiode (D1, D2a, D2b), characterized in that said input element (14) comprisesa sensing circuit (15) comprising at least one first photodiode (D1) and at least one second photo-diode (D2a, D2b), wherein said first photodiode (D1) is arranged in series to said second photodiode (D2a, D2b), a voltage source (12) generating a voltage, wherein said voltage is applied over said sensing circuit (15),
an amplifier (A1) having an input connected to an intermediate voltage potential at a location (16) between said first photodiode (D1) and said second photodiode (D2a, D2b),
wherein said first photodiode (D1) and said second photodiode (D2a, D2b) are spaced apart and are arranged to receive ambient light at least in part through first and second separate areas (6, 7) of said housing (1); andwherein the input of said amplifier is connected via a low-pass filter (17) to a location (16) between the first photodiode (DI) and the second photodiode (D2a, D2b), said low-pass filter (17) comprising a capacitor (CI) and an asymmetric resistor (R1, D3), wherein said asymmetric resister (R1,D3) is arranged between said capacitor (CI) and said location (16) and is oriented to have a higher conductivity for current flowing through said second photodiode (D2a, D2b) than for current flowing through said first photodiode (DI).

US Pat. No. 10,659,041

CONTROL OF AN ANODE-GATE THYRISTOR

STMicroelectronics (Tours...

1. A circuit for controlling an anode-gate thyristor for rectification of an AC voltage signal, comprising:a first transistor coupling a gate of the anode-gate thyristor to a first terminal which is at a first potential;
wherein the first potential is lower than a second potential at a second terminal, wherein the second terminal is connected to an anode of the anode-gate thyristor;
a second transistor coupling a control terminal of the first transistor to a third terminal to receive a third potential which is positive with respect to the second potential of the second terminal;
a voltage regulator coupled between the third terminal and a fourth terminal;
a diode having an anode directly electrically connected to the first terminal and a cathode directly electrically connected to the second terminal; and
a resistor directly electrically connected between the second terminal and the fourth terminal.

US Pat. No. 10,659,040

CLOCK VOLTAGE STEP-UP CIRCUIT

CSMC TECHNOLOGIES FAB2 CO...

1. A clock voltage step-up circuit comprising:a first inverter, an input end of the first inverter being configured to input a first clock signal;
a second inverter, an input end of the second inverter being connected to an output end of the first inverter, an output end of the second inverter outputting a first control signal used for controlling a sampling switch, and after the first clock signal passes through a fourth inverter, a fifth inverter and a sixth inverter, a second control signal used for controlling the sampling switch being generated;
a third inverter, an input end of the third inverter being configured to input a second clock signal, and the first clock signal and the second clock signal being a set of two-phase non-overlapping clock signals;
a PMOS transistor, a gate end of the PMOS transistor being connected to a drain end of the PMOS transistor, and a source end of the PMOS transistor being configured to be connected to a power supply; and
a bootstrap capacitor, an end of the bootstrap capacitor being connected to an output end of the third inverter, and another end of the bootstrap capacitor being connected to the drain end of the PMOS transistor and being connected to the second inverter, to step up a voltage of the first control signal.

US Pat. No. 10,659,039

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a first transistor including, one end of a current path connected to a first node, another end of the current path connected to a second node, and a gate connected to a third node;
a second transistor including, one end of a current path connected to the second node, another end of the current path connected to a fourth node, and a gate connected to the third node;
a switch configured to connect the second node and the third node; and
a first control circuit configured to control the switch,
wherein the first control circuit turns on the switch in a period in which the first transistor and the second transistor are turned off,
wherein the first control circuit comprises:
a first current supply circuit including a third transistor that supplies a first current; and
a first voltage generation circuit that generates and outputs a first voltage based on the first current, wherein
the switch is controlled based on a gate potential of the third transistor,
the switch comprises a fifth transistor connected between the second node and the third node, and
the third transistor and the fifth transistor form a current mirror.

US Pat. No. 10,659,038

POWER ON RESET LATCH CIRCUIT

NXP USA, Inc., Austin, T...

1. A circuit comprising:a latch circuit that powers up to a known latch state and includes a second latch state, the latch circuit comprising:
a latch including a first latch node and a second latch node, the first latch node and the second latch node are at first complementary node states in the known latch state and are at second complementary node states in the second latch state, the latch including power supply terminals for being powered at a first power supply voltage differential of a first voltage domain;
a current path between the first latch node and a power supply terminal;
a latch resetting device located in the current path, the latch resetting device including a control input to receive a signal to place the latch resetting device in a conductive state to pull the first latch node towards a power supply voltage of the power supply terminal coupled to the current path to place the latch circuit in the second latch state;
a diode located in the current path, the diode inhibiting current flow in the first current path between the first latch node and the power supply terminal when the power supply voltage differential is below a threshold voltage during power up; and
a level shifter including a first stage and a second stage, the first stage for being powered at the first power supply voltage differential of the first voltage domain, the second stage being power by a second supply voltage differential of a second voltage domain, wherein the first stage includes an output to provide the signal.

US Pat. No. 10,659,037

AUDIO SWITCHING CIRCUIT

MOTOROLA SOLUTIONS, INC.,...

1. An audio switching circuit comprising:a first P-channel transistor including a first source terminal, a first gate terminal, and a first drain terminal, the first P-channel transistor configured to receive a first audio signal at the first source terminal;
a first resistor coupled to the first source terminal and the first gate terminal;
a second P-channel transistor including a second source terminal, a second gate terminal, and a second drain terminal, the second drain terminal coupled to the first drain terminal;
a second resistor coupled to the second source terminal and the second gate terminal; and
a control circuit coupled to the first gate terminal and the second gate terminal, the control circuit configured to disconnect the first gate terminal from a ground reference, and
in response to the presence of the first audio signal, cause, via the first resistor, a first voltage between the first gate terminal and the first source terminal to be approximately zero, and prevent the first audio signal from passing through the first drain terminal.

US Pat. No. 10,659,036

RADIO-FREQUENCY ISOLATED GATE DRIVER FOR POWER SEMICONDUCTORS

The Florida State Univers...

1. A radio frequency (RF) isolated gate driver, comprisingan RF modulator that receives a control signal from a controller and outputs a carrier frequency that is modulated by the control signal from the controller, wherein the carrier frequency is higher than frequencies corresponding to conducted electromagnetic interference (EMI);
an RF transformer tuned to the carrier frequency and connected at a primary side to the RF modulator, wherein the RF transformer spatially couples energy from the primary side to a secondary side, and wherein the RF transformer filters the frequencies corresponding to conducted EMI, and wherein the RF transformer provides galvanic isolation between the primary side and the secondary side;
an RF demodulator connected to the secondary side of the RF transformer that receives the modulated carrier frequency and outputs a demodulated control signal; and
an unfolder circuit connected to the RF demodulator that receives the demodulated control signal and outputs a gate signal for driving a gate of a power semiconductor.

US Pat. No. 10,659,035

POWER MODULE WITH A UNIPOLAR SEMICONDUCTOR COMPONENT FOR A LONG SERVICE LIFE

FRAUNHOFER-GESELLSCHAFT Z...

1. A power module, which has a carrier substrate on which at least one unipolar semiconductor component is arranged as a power switch,characterised in that,
the unipolar semiconductor component is designed such that a temperature rise of the semiconductor component, from a first temperature up to which the semiconductor component heats during operation at 50% of full load, to a second temperature up to which the semiconductor component heats during operation at full load, is less than a temperature rise of the semiconductor component from an initial temperature at zero load to the first temperature.

US Pat. No. 10,659,034

INTEGRATED ELECTRONIC DEVICE SUITABLE FOR OPERATION IN VARIABLE-TEMPERATURE ENVIRONMENTS

STMicroelectronics SA, M...

1. An integrated electronic device, comprising:a silicon-on-insulator substrate;
at least one MOS transistor formed in and on said silicon-on-insulator substrate;
wherein the at least one MOS transistor comprises:
a gate region configured to receive a control voltage,
a back gate configured to receive an adjustment voltage;
a source or drain region having a resistive portion;
a first terminal configured to be coupled to a first voltage and formed in the source or drain region and on a first side of the resistive portion of the source or drain region; and
a second terminal configured to generate a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source or drain region and on a second side of the resistive portion of the source or drain region; and
adjustment circuitry configured to generate the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.

US Pat. No. 10,659,033

HIGH VOLTAGE GATE DRIVER CURRENT SOURCE

TEXAS INSTRUMENTS INCORPO...

1. A circuit comprising:a power terminal;
a bus terminal;
a power field-effect transistor (FET) having a FET gate and a FET drain and a FET source, in which the FET drain is coupled to the power terminal, and the FET source is coupled to the bus terminal;
a charge pump voltage terminal;
a current mirror including first and second transistors, in which the first transistor has a first gate and a first drain and a first source, the second transistor has a second gate and a second drain and a second source, the first and second sources are coupled to the charge pump voltage terminal, and the second gate is coupled to the first gate and to the second drain;
a biasing current source coupled to the second drain;
a cascode transistor having a third gate and a third drain and a third source, in which the third drain is coupled to the FET gate, and the third source is coupled to the first drain;
a feedback transistor having a fourth gate and a fourth drain and a fourth source, in which the fourth gate is coupled to the first drain, and the fourth drain is coupled to the charge pump voltage terminal;
first and second feedback resistors, in which the first feedback resistor is coupled between the fourth source and the third gate, and the second feedback resistor is coupled between the third gate and the FET drain; and
a current limit circuit including a non-inverting input, an inverting input and an output, in which the output of the current limit circuit is coupled to the FET gate, the non-inverting input is adapted to be coupled to a reference current source, and the inverting input is adapted to be coupled to a power current source.

US Pat. No. 10,659,032

GAN-ON-SAPPHIRE MONOLITHICALLY INTEGRATED POWER CONVERTER

HRL Laboratories, LLC, M...

1. A method for fabricating a half bridge circuit comprising:growing GaN epitaxy on a sapphire wafer;
fabricating an upper switch and a lower switch in the GaN epitaxy;
forming a first gate driver in the GaN epitaxy;
forming a second gate driver in the GaN epitaxy;
forming a first metal post;
forming a second metal post;
forming a first conductor coupled to the upper switch, wherein a portion of the first conductor is supported by the first and second metal posts on a plane vertically separated from the upper switch and the lower switch by a height;
forming a second conductor coupled to the lower switch, wherein a portion of the second conductor is supported by the first and second metal posts on a plane vertically separated from the upper switch and the lower switch by the height;
providing a capacitor coupled between the portion of the first conductor and the portion of the second conductor; and
forming interconnects between the first gate driver, the upper switch, the second gate driver, the lower switch, the first metal post, the second metal post, the first conductor, and the second conductor to form one or more half bridge integrated circuits.

US Pat. No. 10,659,031

RADIO FREQUENCY SWITCH

Qorvo US, Inc., Greensbo...

1. A radio frequency switch comprising a first node, a second node, and a plurality of switch cells that is coupled in series between the first node and the second node, wherein each of the plurality of switch cells comprises:a switch field-effect transistor (FET) comprising a switch drain terminal, a switch source terminal, a switch gate terminal, and a switch body terminal; and
a body bias network comprising:
a first body bias FET having a first drain terminal coupled to the switch body terminal, a first gate terminal, and a first source terminal;
a first cross-FET having a second drain terminal coupled to the first source terminal, a second source terminal coupled to the switch gate terminal, and a second gate terminal;
a second body bias FET having a third drain terminal coupled to the switch body terminal, a third gate terminal, and a third source terminal; and
a second cross-FET having a fourth drain terminal coupled to the third source terminal, a fourth source terminal coupled to the switch gate terminal, and a fourth gate terminal, wherein the first gate terminal of the first body bias FET is coupled to the fourth gate terminal of the second cross-FET, and the third gate terminal of the second body bias FET is coupled to the second gate terminal of the first cross-FET.

US Pat. No. 10,659,030

TRANSACTIONAL MEMORY THAT PERFORMS A STATISTICS ADD-AND-UPDATE OPERATION

Netronome Systems, Inc., ...

1. A transactional memory, comprising:a memory unit, wherein a plurality of first values is stored in a plurality of memory locations in the memory unit; and
a hardware engine that receives an Add-and-Update (AU) command from a bus, wherein the Add-and-Update command includes a second value, and wherein the hardware engine executes the Add-and-Update command thereby: 1) causing each of the memory locations to be read, 2) causing the same second value to be added to each of the first values thereby generating a corresponding set of updated first values, and 3) causing the set of updated first values to be written into the plurality of memory locations.

US Pat. No. 10,659,029

CHOPPED TRIANGULAR WAVE PWM QUANTIZER

CIRRUS LOGIC, INC., Aust...

1. An apparatus in a pulse width modulation (PWM) modulator, comprising:a triangular wave generator that generates a triangular wave;
a comparator that is responsive to a signal input to generate a signal output, wherein an output of the PWM modulator is responsive to the comparator signal output;
a polarity inversion circuit coupled to the comparator;
wherein the polarity inversion circuit is configured in one of the following ways:
to provide the triangular wave to the comparator when the triangular wave has a first slope polarity and to provide a polarity-inverted version of the triangular wave to the comparator when the triangular wave has a second slope polarity opposite the first slope polarity; and
to provide the signal input to the comparator when the triangular wave has the first slope polarity and to provide a polarity-inverted version of the signal input to the comparator when the triangular wave has the second slope polarity; and
wherein the polarity-inversion circuit comprises a de-chopping switch.

US Pat. No. 10,659,028

DIGITAL AUDIO CONVERTER AND AMPLIFIER CONTROLLER

AXIGN B.V., Enschede (NL...

1. A programmable pulse width modulating (PWM) controller comprising in series(i) at least two parallel loop filters for loop-gain and signal processing, each loop filter comprising multiple inputs and at least one output, wherein a loop filter is adapted to perform at least one of interpolation of the pulse code modulated (PCM) input signal, common mode control, differential mode control, audio processing, audio filtering, audio emphasizing, and LC compensation,
wherein each single output being in electrical connection with
(ii) at least one butterfly mixer, the butterfly mixer being capable of mixing at least two inputs and of providing at least two mixed outputs to
(iii) at least two parallel pulse width modulators (PWM's), wherein a pulse width modulator comprises a carrier signal with an adaptable and programmable shape, phase and frequency, wherein the carrier signal is compared by the pulse width modulator with the input signal to create an output signal,
wherein (iv) loop filters, butterfly mixer, and PWM's are individually and independently programmable and adaptable,
wherein loop filter input is adapted to receive at least one of a local digital PWM processed output signal, and an ADC output, and
comprising at least one setting data storage for loading, adapting and storing programmable and adaptable settings.

US Pat. No. 10,659,027

COMPARATOR CIRCUITRY

SOCIONEXT INC., Yokohama...

1. Comparator circuitry for use in a comparator to capture differences between magnitudes of first and second comparator input signals in a series of capture operations defined by a clock signal, the circuitry comprising:a biasing current source configured to provide a bias current which flows independently of the clock signal;
a tail node connected to receive the bias current;
first and second nodes conductively connectable to said tail node along respective first and second paths; and
switching circuitry configured during each capture operation to control connections between the tail node and the first and second nodes based on the first and second comparator input signals such that said bias current is divided between said first and second paths in dependence upon the difference between magnitudes of the first and second comparator input signals,
wherein:
the switching circuitry comprises a first transistor whose channel forms part of the first path and a second transistor whose channel forms part of the second path;
gate or base terminals of the first and second transistors are controlled by the first and second comparator input signals, respectively, such that the conductivity of the connections between the tail node and the first and second nodes is controlled by the magnitudes of the first and second comparator input signals;
the switching circuitry further comprises a third transistor whose channel forms part of the first path and a fourth transistor whose channel forms part of the second path;
the third and fourth transistors are located along their respective paths between the first and second transistors and the first and second nodes, respectively;
the third and fourth transistors are non-clocked transistors whose gate or base terminals are controlled by a gate or base bias signal which is also independent of the clock signal;
the comparator circuitry further comprises first and second gain-stage buffers each having a buffer input terminal and a buffer output terminal;
the buffer input terminals are connected to the first and second nodes, respectively;
the first and second gain-stage buffers are operable to output first and second buffer output signals at their respective buffer output terminals based on first and second buffer input signals received at their respective buffer input terminals from the respective first and second nodes, respectively;
the comparator circuitry further comprises first and second controllable resistances;
the first controllable resistance is connected between the first node and a first reference voltage supply and the second controllable resistance is connected between the second node and the first reference voltage supply;
the first and second controllable resistances are configured to limit a voltage level change at the first and second nodes, respectively, during each capture operation; and
the first and second controllable resistances are connected to be controlled by the first and second buffer output signals, respectively.

US Pat. No. 10,659,026

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a resistive subdivision circuit generating a first comparison voltage and a second comparison voltage different from the first comparison voltage based on subdividing an input voltage with different resistive subdivision ratios;
a first voltage detection circuit outputting a result of a comparison between a reference voltage and the first comparison voltage to an output node of the first voltage detection circuit;
a second voltage detection circuit outputting a result of a comparison between the reference voltage and the second comparison voltage to an output node of the second voltage detection circuit;
wherein the first voltage detection circuit includes:
a first transistor of a first conductive type coupled between the output node and a first power supply; and
a first transistor of a second conductive type having a gate supplied with the first comparison voltage, and coupled between the output node and a second power supply,
wherein the second voltage detection circuit includes:
a second transistor of the first conductive type coupled between the output node and the first power supply; and
a second transistor of the second conductive type having a gate supplied with the second comparison voltage, and coupled between the output node and the second power supply,
wherein a mirror current flows through each of the first and second transistors of the first conductivity type, the mirror current caused by a third transistor of the first conductivity type having a gate and a drain commonly coupled to a gate of the first transistor of the first conductivity type and a gate of the second transistor of the first conductivity type, and
wherein the third transistor is supplied with a bias current by a bias current generating circuit.

US Pat. No. 10,659,025

ADAPTIVE BIAS CIRCUIT FOR POWER EVENT DETECTION COMPARATOR

Synaptics Incorporated, ...

1. A system, comprising:a power supply;
an adaptively biased power event detection comparator; and
an adaptive bias circuit for the adaptively biased power event detection comparator;
wherein the adaptively biased power event detection comparator is configured to compare a first input corresponding to a voltage level of the power supply with a second input corresponding to a reference voltage;
wherein the adaptive bias circuit is configured to increase a bias current for the adaptively biased power event detection comparator based on the voltage level of the power supply decreasing to be closer to the reference voltage;
wherein the adaptive bias circuit comprises a first transistor and a second transistor, wherein the voltage level of the power supply is input to a gate of the first transistor and the reference voltage is input to a gate of the second transistor; and
wherein the bias current is a sum of a first current across a source and a drain of the first transistor and a second current across a source and a drain of the second transistor.

US Pat. No. 10,659,024

INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO CHANGE A CLOCK SIGNAL FREQUENCY WHILE A DATA SIGNAL IS VALID

Rambus Inc., Sunnyvale, ...

1. A memory controller, comprising:clock output circuitry to output a clock signal;
data output circuitry to output a data signal that is timed using the clock signal;
first circuitry to maintain a temporal correspondence between the clock signal and the data signal until information encoded in the data signal is interpreted using the clock signal; and
second circuitry to gaplessly change a clock frequency of the clock signal while the data output outputs the data signal that is timed using the clock signal.

US Pat. No. 10,659,023

APPARATUS AND METHOD FOR MULTIPLYING FREQUENCY

Electronics and Telecommu...

1. An apparatus for multiplying a frequency of an input signal, comprising:a main differential device for converting the input signal into a first differential signal and a second differential signal;
a first multiplying device for outputting a first signal obtained by multiplying a frequency of the first differential signal;
a second multiplying device for outputting a second signal obtained by multiplying a frequency of the second differential signal; and
a compositing device for outputting a third signal obtained by combining the first signal and the second signal to remove a fundamental frequency component,
wherein the main differential device is a balun or a transformer.

US Pat. No. 10,659,022

COMPARATOR, ANALOG-TO-DIGITAL CONVERTER, SOLID-STATE IMAGE PICKUP DEVICE, AND IMAGE PICKUP APPARATUS

Sony Corporation, Toyko ...

1. A comparator, comprising:a plurality of signal input transistors each having a control terminal to which an input signal is input;
a reference input transistor configuring, together with each of the plurality of signal input transistors, a differential pair, and having a control terminal to which a reference signal is input;
a signal input transistor selection section selecting any one of the plurality of signal input transistors, and generating a current in response to a difference between the input signal and the reference signal to flow in the differential pair configured with the selected signal input transistor and the reference input transistor; and
a load section converting, at a time of a change of a current flowing in any one of the plurality of signal input transistors and the reference input transistor in response to the difference, the change of the current into a change of a voltage, and outputting the change of the voltage as a result of comparison between the input signal and the reference signal,
wherein the signal input transistor selection section selects the one signal input transistor by applying, to the control terminals of unselected signal input transistors among the plurality of signal input transistors, a voltage for turning the unselected signal input transistors into a non-conductive state.

US Pat. No. 10,659,021

VECTOR SUM CIRCUIT AND PHASE CONTROLLER USING THE SAME

Samsung Electronics Co., ...

1. A vector sum circuit comprising:an amplifier configured to amplify an orthogonal signal by using a first metal oxide semiconductor field effect transistor (MOSFET);
a self body-biasing circuit comprising a resistor
configured to connect a drain and a body of the first MOSFET to reduce a voltage applied to the body as a current at the drain increases; and
an amplification controller configured to control a tail current of the amplifier,
wherein the amplifier controller comprises a second MOSFET and a switch, and
wherein the switch is configured to provide an output of a current mirror circuit interlocked with an output of a digital-to-analog converter (DAC) to a gate of the second MOSFET.

US Pat. No. 10,659,020

PULSE COUNTING CIRCUIT

STMicroelectronics (Rouss...

1. A circuit, comprising:a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs, respectively;
a first counter coupled to the first RONG output and configured to generate a first count at a first counter output;
a second counter coupled to the second RONG output and configured to generate a second count at a second counter output; and
a selection circuit coupled to the first and second counter outputs and to the first and second RONG outputs and configured to select one of the first and second counts.

US Pat. No. 10,659,019

NANOSECOND PULSER ADC SYSTEM

Eagle Harbor Technologies...

1. A nanosecond pulser system comprising:a nanosecond pulser comprising:
a pulser input;
a high voltage DC power supply;
one or more solid-state switches coupled with the high voltage DC power supply and the pulser input, the one or more solid-state switches switching the high voltage DC power supply based on input pulses provided by the pulser input;
one or more transformers coupled with the one or more switches; and
a pulser output coupled with the one or more transformers that outputs a high voltage waveform with an amplitude greater than about 2 kV and a pulse repetition frequency greater than about 1 kHz based on the pulser input; and
a control system coupled with the nanosecond pulser at a measurement point, the control system providing the input pulses to the pulser input.

US Pat. No. 10,659,018

QUANTUM CONTROLLER WITH MULTIPLE PULSE MODES

Quantum Machines, (IL)

1. A method comprising:receiving, in a pulse modification circuit of an electromagnetic pulse generation system, a first pulse and a second pulse;
making, by the pulse modification circuit, a decision whether to process the first pulse and the second pulse as a multi-pulse pair or as two independent pulses;
when the decision is to process the first pulse and the second pulse as a multi-pulse pair:
processing the first pulse and the second pulse to generate a single output pulse; and
outputting the single output pulse on a first signal path; and
when the decision is to process the first pulse and second pulse as independent pulses:
processing the first pulse to generate a first output pulse;
processing the second pulse to generate a second output pulse;
outputting the first output pulse on a second signal path; and
outputting the second output pulse on a third signal path.

US Pat. No. 10,659,017

LOW-POWER SCAN FLIP-FLOP

Marvell International Ltd...

14. A flip-flop comprising:a first latch comprising:
a multi-stage, single clock phase-dependent, first driver comprising:
a multiplexor stage having a multiplexor output node; and
a tristate output stage having a first driver output node, wherein a first driver output signal at the first driver output node is dependent, in part, on a multiplexor output signal at the multiplexor output node;
a first feed-forward path; and
a first feedback path;
a second latch comprising: a second driver having a second driver input node and a second driver output node; a second feed-forward path; and a second feedback path;
a third driver comprising a third driver input node and a third driver output node,
wherein the first feed-forward path connects the first driver output node to the second driver input node,
wherein the first feedback path is connected to at least one first node on the first feed-forward path,
wherein the second feed-forward path connects the second driver output node to the third driver input node, and
wherein the second feedback path is connected to at least one second node on the second feed-forward path; and
an n-type shared clock-gated power supply transistor comprising a first source/drain terminal connected to a ground voltage rail and a second source/drain terminal connected to the second driver and the first feedback path,
wherein the n-type shared clock-gated power supply transistor is controlled by a clock signal.

US Pat. No. 10,659,016

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a level shifter,
wherein the level shifter includes:
a latch circuit including a pair of first-conductivity-type cross-coupled transistors each coupled to a first power supply node to which a high power supply voltage is input;
an input circuit including a pair of second-conductivity-type transistors each coupled to a second power supply node to which a reference voltage is input and having respective gates that receive complementary input signals to the level shifter; and
an exceeded-breakdown-voltage prevention circuit coupled between the latch circuit and the input circuit,
wherein the exceeded-breakdown-voltage prevention circuit includes:
a first-conductivity-type first exceeded-breakdown-voltage prevention transistor having a gate that receives a first intermediate voltage which is between the high power supply voltage and the reference voltage;
a second-conductivity-type second exceeded-breakdown-voltage prevention transistor having a gate that receives a second intermediate voltage which is between the high power supply voltage and the reference voltage and coupled in series to the first exceeded-breakdown-voltage prevention transistor; and
a first-conductivity-type third exceeded-breakdown-voltage prevention transistor coupled in series to the first and second exceeded-breakdown-voltage prevention transistors between the first and second exceeded-breakdown-voltage prevention transistors and the latch circuit, and
wherein the level shifter further includes a first-conductivity-type clamp transistor coupled between a coupling node between the third exceeded-breakdown-voltage prevention transistor and the latch circuit and the first power supply node.

US Pat. No. 10,659,015

METHOD, APPARATUS, AND SYSTEM FOR A LEVEL SHIFTING LATCH WITH EMBEDDED LOGIC

QUALCOMM Incorporated, S...

1. An apparatus, comprising:a latching element having a data input, a first feedback input, a second feedback input, and an output;
a pull-up input block coupled to the data input of the latching element and having at least a first pull-up input;
a pull-down input block coupled to the data input of the latching element and having at least a first pull-down input;
a feedback pull-down block coupled to a feedback pull-down control device, the feedback pull-down block responsive to the first pull-up input and implementing an opposite logic function to the pull-up input block;
a feedback pull-up block coupled to a feedback pull-up control device, the feedback pull-up block responsive to the first pull-down input and implementing an opposite logic function to the pull-down input block; and
a set-reset latch, wherein:
the pull-up input block and the pull-down input block are configured not to be enabled concurrently,
the feedback pull-down control device and the feedback pull-up control device are controlled by the output,
the pull-up input block further has a second pull-up input and the feedback pull-down block is further responsive to the second pull-up input,
the pull-down input block further has a second pull-down input and the feedback pull-up block is further responsive to the second pull-down input,
the first pull-up input of the pull-up input block is a not_reset input, the first pull-down input of the pull-down input block is a set input, and
the second pull-up input and the second pull-down input are coupled together as a select input.

US Pat. No. 10,659,014

CLOCK CONTROL IN SEMICONDUCTOR SYSTEM

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a first ring oscillator disposed at a first location and configured to generate a first oscillating signal;
a second ring oscillator disposed at a second location and configured to generate a second oscillating signal, the first location being closer than the second location to a first logic circuit of an operation circuit, and the second location being closer than the first location to a second logic circuit of the operation circuit;
a detecting circuit configured to generate a first clock signal by performing a predetermined logic operation on the first oscillating signal and the second oscillating signal; and
a calibration circuit configured to generate a second clock signal for operating the operation circuit by receiving the first clock signal from the detecting circuit and performing a delay control on each of the first ring oscillator and the second ring oscillator.

US Pat. No. 10,659,013

CURRENT-CONTROLLED OSCILLATOR WITH START-UP CIRCUIT

NXP USA, Inc., Austin, T...

1. A start-up circuit for a ring current-controlled oscillator (CCO), wherein the ring CCO receives a CCO current, the startup circuit comprising:a replica CCO current generator that receives a reference voltage and a supply voltage, and generates a replica CCO current;
a replica ring CCO connected to the replica CCO current generator for receiving the replica CCO current, wherein the replica ring CCO generates a replica CCO output voltage at a first oscillating frequency that is less than a second oscillating frequency of a CCO output voltage of the ring CCO; and
a buffer, connected to the ring CCO and the replica ring CCO, wherein the buffer provides a first current to the ring CCO when the second oscillating frequency is lower than a desired oscillating frequency of the CCO output voltage, and drains a second current from the ring CCO when the second oscillating frequency is greater than the desired oscillating frequency.

US Pat. No. 10,659,012

OSCILLATOR AND METHOD FOR OPERATING AN OSCILLATOR

NXP B.V., Eindhoven (NL)...

1. An oscillator, comprising:an output;
a ring oscillator core configured to generate an output clock signal on the output;
a control circuit coupled between the output and the ring oscillator core; and
a timer that disables the control circuit until oscillation of the ring oscillator core begins;
wherein the timer is released by a reset signal; and
wherein after a release of the timer by the reset signal, the timer expires and activates the control circuit after a startup time of the ring oscillator core.

US Pat. No. 10,659,011

LOW NOISE AMPLIFIER

1. A low noise amplifier, comprising:an input port;
an output port;
an inverter electrically connected between the input port and the output port;
a plurality of switched-capacitor units, wherein each of the plural switched-capacitor units is electrically connected with the inverter in parallel and comprises a switch and a capacitor connected in series, the plural switches are turned on at different times separately, the sum of a plurality of duty ratios of the plural switches is 100%, wherein the low noise amplifier has a work frequency, and the plural switched-capacitor units have a center frequency;
a plurality of parasitic capacitors causing a decrease of the work frequency; and
a feedback inductor electrically connected with the inverter in parallel, wherein the feedback inductor causes an increase of the work frequency, and the increase and the decrease are equal in magnitude so as to make the work frequency equal to the center frequency.

US Pat. No. 10,659,010

RF OUTPUT DRIVER

QUALCOMM Incorporated, S...

1. A radio frequency (RF) driver circuit having a driver circuit input and a driver circuit output, comprising:a first transistor having a source terminal coupled to the driver circuit input and a drain terminal coupled to the driver circuit output;
a second transistor having a source terminal coupled to the driver circuit output and a gate terminal coupled to the driver circuit input; and
an RF current source coupled to the source terminal of the first transistor, the RF current source comprising an inductor,
wherein the source terminal of the first transistor is coupled to the inductor, and the gate terminal of the first transistor is coupled to ground via a first capacitor, and
wherein the drain terminal of the second transistor is coupled to a supply voltage or to ground, and the gate terminal of the second transistor is coupled to the driver circuit input via a second capacitor.

US Pat. No. 10,659,009

METHOD AND SYSTEM FOR ATTENUATOR PHASE COMPENSATION

NXP B.V., San Jose, CA (...

1. A method for attenuator phase compensation, the method comprising:determining a phase compensation value for an attenuator based on a function of a received attenuation configuration of the attenuator, wherein the received attenuation configuration of the attenuator comprises an adjustable impedance value of the attenuator; and
performing phase compensation according to the phase compensation value to maintain a constant phase response.

US Pat. No. 10,659,006

RESONATOR ELEMENT, RESONATOR, ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND MOVING OBJECT

SEIKO EPSON CORPORATION, ...

1. A resonator element comprising:a base portion including a first end surface and a second end surface which is provided on a rear side of the first end surface; and
a pair of vibrating arms that protrude from the first end surface of the base portion in a first direction and are arranged in a line extending in a second direction perpendicular to the first direction, the vibrating arms each including a weight portion and an arm portion, the arm portion disposed between the weight portion and the base portion in plan view,
a shortest distance Wb between the first end surface of the base portion and the second end surface of the base portion is selected so that the following are satisfied:
Q={(?×Cp)/(c×?2×?)}×[{1+(2×?×Cp×We2×f/(?×k))2}/(2×?×Cp×We2×f/(?·k))]
0.81?Wb/We?1.70,
where Q is a Q-value of the resonator element, f is a vibration frequency [Hz] of the resonator element, We is an effective width [m], ? is mass density [kg/m3], Cp is heat capacity per unit mass at constant pressure [J/(kg×K)], c is an elastic constant [N/m2] related to a direction perpendicular to a direction of Wb in a plane, ? is a thermal expansion coefficient [1/K] related to a direction perpendicular to the direction of Wb in the plane, ? is an environmental temperature [K], and k is thermal conductivity [W/(m×K)] related to the direction of Wb.

US Pat. No. 10,659,005

AT-CUT CRYSTAL ELEMENT, CRYSTAL RESONATOR AND CRYSTAL UNIT

NIHON DEMPA KOGYO CO., LT...

1. An AT-cut crystal element, comprising:side surfaces intersecting with a Z?-axis of a crystallographic axis of a crystal, and
at least one side surface of the side surfaces being constituted of three surfaces of a first surface, a second surface and a third surface,
wherein
the first surface, the second surface, and the third surface intersect in this order, and
the first surface is a surface corresponding to a surface where a principal surface is rotated around an X-axis of the crystal by 4°±3.5°, wherein the principal surface is an X-Z? surface of the AT-cut crystal element and the X-Z? surface is represented by the crystallographic axes of the crystal,
the second surface is a surface corresponding to a surface where the principal surface is rotated around the X-axis of the crystal by ?57°±5°, and
the third surface is a surface corresponding to a surface where the principal surface is rotated around the X-axis of the crystal by ?42°±5°.

US Pat. No. 10,659,003

ELECTRONIC COMPONENT WITH TWO SUBSTRATES ENCLOSING FUNCTIONAL ELEMENT AND INSULATING FILM THEREIN

TAIYO YUDEN CO., LTD., T...

1. An electronic component comprising:a first substrate;
a second substrate that includes a functional element formed on a lower surface of the second substrate, the second substrate being mounted on the first substrate so that the functional element faces an upper surface of the first substrate across an air gap; and
an insulating film that is located on the upper surface of the first substrate, overlaps with at least a part of the functional element in plan view, faces the functional element across the air gap, that has a film thickness that is more than half of a distance between a lower surface of the functional element and the upper surface of the first substrate, and that is made of an organic insulating material, a thermal conductivity of the insulating film being more than five times a thermal conductivity of air.

US Pat. No. 10,659,001

ELASTIC WAVE DEVICE

MURATA MANUFACTURING CO.,...

1. An elastic wave device comprising:a support substrate;
a lamination layer film provided on the support substrate and including a plurality of films including a piezoelectric thin film;
an interdigital transducer (IDT) electrode provided on one surface of the piezoelectric thin film;
a first insulation layer provided in a region located at an outer side portion of a region where the IDT electrode is provided and extending from at least a portion of a region where the lamination layer film is not present to an upper portion of the piezoelectric thin film in a plan view; and
a wiring electrode electrically connected to the IDT electrode, extending from the upper portion of the piezoelectric thin film to an upper portion of the first insulation layer, and extending onto a section of the first insulation layer positioned in the region where the lamination layer film is not present.

US Pat. No. 10,659,000

FLUIDIC SENSOR DEVICE HAVING UV-BLOCKING COVER

Qorvo Biotechnologies, LL...

1. A fluidic sensing device comprising:a fluidic channel having a first side, a second side, a top, and a bottom;
a first sidewall defining the first side of the fluidic channel;
a second sidewall spaced apart from the first sidewall and defining the second side of the fluidic channel;
a bulk acoustic resonator structure having a surface defining at least a portion of the bottom of the channel, wherein the bulk acoustic resonator structure comprises piezoelectric material arranged between a first electrode and a second electrode;
a biomolecule attached to the surface of the bulk acoustic resonator;
a cover disposed over the first and second sidewalls and attached to the first and second sidewalls, wherein the cover defines at least a portion of the top of the fluidic channel and wherein a portion of the cover disposed over the channel blocks transmission of ultraviolet (UV) radiation configured, wherein a first portion of the cover disposed over the first sidewall is transparent to UV radiation, and wherein a second portion of the cover disposed over the second sidewall is transparent to UV radiation.

US Pat. No. 10,658,999

ON-CHIP HARMONIC FILTERING FOR RADIO FREQUENCY (RF) COMMUNICATIONS

Silicon Laboratories Inc....

1. An integrated circuit, comprising:a circuit coupled between a first node and a connection pad for the integrated circuit, the circuit comprising:
a first inductance coupled between the first node and a second node;
a first capacitance coupled between the first node and the second node in parallel with the first inductance, the first capacitance being a fixed capacitance;
a variable second capacitance coupled between the second node and ground; and
a second inductance coupled between the second node and the connection pad; and
a controller coupled to control a capacitance amount for the variable second capacitance to determine filtering with respect to a radio frequency (RF) signal passing through the circuit and to determine impedance matching with respect to a load coupled to the connection pad,
wherein the variable second capacitance comprises:
a first variable capacitor circuit having a coarse-tune control signal as an input from the controller; and
a second variable capacitor circuit having a fine-tune control signal as an input from the controller.

US Pat. No. 10,658,998

PIEZOELECTRIC FILM TRANSFER FOR ACOUSTIC RESONATORS AND FILTERS

OEPIC SEMICONDUCTORS, INC...

1. A method for forming an acoustic resonator comprising;forming a piezoelectric material on a first substrate, wherein forming the piezoelectric material comprises:
growing a single crystal aluminum nitride film directly on a sapphire substrate; and
depositing an electrode material on a first surface of the single crystal aluminum nitride film forming a first electrode;
forming a reflector device on a semiconductor substrate separate from the sapphire substrate;
bonding the first electrodes to the reflector device formed on the semiconductor substrate so that the first electrode formed on the single crystal aluminum nitride film on the sapphire substrate attaches to the reflector device; and
removing the sapphire substrate.

US Pat. No. 10,658,997

ENERGY EFFICIENT CLIP LIMITING VOLTAGE CONTROLLED AMPLIFIER

RGB Systems, Inc., Anahe...

1. A voltage controlled amplifier, comprising:a power amplifier in a primary signal path, the power amplifier configured to receive an input signal transmitted along the primary signal path and to amplify the input signal; and
an amplitude limiting circuit in a secondary signal path that is configured to limit the gain of the power amplifier when active, wherein the amplitude limiting circuit comprises:
a first differential transistor pair of a first type;
a second differential transistor pair of a second type, wherein the first differential transistor pair and the second differential transistor pair are configured to attenuate the input signal provided to the power amplifier; and
a control circuit configured to control operation of the first differential transistor pair and the second differential transistor pair based at least in part on a control signal, wherein the control signal indicates whether to attenuate the input signal, wherein the control circuit comprises an operational amplifier.

US Pat. No. 10,658,996

RENDERING WIDEBAND ULTRASONIC SIGNALS AUDIBLE

SONOTEC Ultraschallsensor...

1. Method for rendering an ultrasonic signal audible while retaining a temporal dynamic range of the ultrasonic signal which method comprisesdigitally sampling a portion of an ultrasonic signal to obtain a digital signal sample;
separating the digital signal sample into narrowband octaves using a digital filter bank;
obtaining separate time-dependent amplitude level values for the digital signal sample within each of the narrowband octaves;
defining a scaled frequency band for each of the narrowband octaves;
generating in substantially real time a bandpass-limited noise signal in an audible range for each amplitude level value within each defined scaled frequency band; and
outputting an audible noise signal for each narrowband octave within each defined scaled frequency band simultaneously.

US Pat. No. 10,658,995

CALIBRATION OF BONE CONDUCTION TRANSDUCER ASSEMBLY

Facebook Technologies, LL...

1. A method comprising:presenting, via an air conduction (AC) transducer to a wearer of a headset, a plurality of tones that are at different frequencies;
presenting, via a bone conduction (BC) transducer of the headset to the wearer, each tone corresponding to each of the plurality of tones, the each corresponding tone having a same frequency as each of the plurality of tones;
adjusting the each corresponding tone such that a level of loudness of the each corresponding tone is within a threshold range of a level of loudness of each of the plurality of tones;
recording a plurality of ear-canal sound pressures (ECSPs) resulting from the plurality of tones;
recording each voltage of a plurality of voltages applied to the BC transducer for generating each adjusted corresponding tone such that the level of loudness of the each adjusted corresponding tone is within the threshold range of the level of loudness of each of the plurality of tones;
while presenting the plurality of tones, generating an equalization filter based on the ECSPs and the voltages;
after the plurality of tones are presented, measuring, via an accelerometer coupled to the BC transducer, acceleration data while presenting an audio signal via the BC transducer; and
adjusting the audio signal for presentation via the BC transducer based on the acceleration data and an equalization curve of the generated equalization filter.

US Pat. No. 10,658,994

METHOD TO DISCOVER AND CONTROL AN AMPLIFIER'S AUTOMATIC GAIN CONTROL (AGC) LOOP BANDWIDTH

Ciena Corporation, Hanov...

1. An amplifier circuit, the amplifier circuit comprising:an amplifier configured to receive at least one input signal and generate an output voltage in response to the at least one input signal and a gain control voltage;
a voltage detector configured to generate a detector voltage based on the output voltage;
a gain control summation circuit configured to generate an error signal by subtracting the detector voltage from a reference voltage;
a loop filter configured to generate the gain control voltage based on the error signal and adjust the loop bandwidth in response to a loop filter adjust signal; and
an analog automatic gain control bandwidth controller configured to monitor the detector voltage and the gain control voltage, to provide the reference voltage and the loop filter adjust signal, and to control a loop bandwidth of the output signal.

US Pat. No. 10,658,993

CHARGE-SCALING MULTIPLIER CIRCUIT WITH DIGITAL-TO-ANALOG CONVERTER

International Business Ma...

1. A multiplier circuit fabricated within an integrated circuit (IC), the multiplier circuit configured to draw a product output node to a voltage proportional to a product of two received N-bit binary numbers, the multiplier circuit comprising:a first set of N inputs configured to receive a first N-bit binary number, each input of the first set of N inputs indexed by an integer bit number “n” corresponding to each input's respective significance, where n is in a range between and including 0 and N?1;
a second set of N inputs configured to receive a second N-bit binary number, each input of the second set of N inputs indexed by the integer bit number “n” corresponding to each input's respective significance;
a local reset device configured to draw, in response to receiving a reset signal, a local product node to ground;
a unity gain amplifier configured to drive a product output node to a voltage equivalent to a voltage on the local product node;
a digital-to-analog converter (DAC) configured to drive, to a DAC output node, an analog voltage that represents a value of the first N-bit binary number, the DAC including:
a voltage divider circuit configured to generate a set of 2N analog voltages; and
a first analog multiplexer (mux) configured to:
receive, through 2N analog inputs electrically connected to the voltage divider circuit, the set of 2N analog voltages;
receive, through a set of N select inputs, the first N-bit binary number; and
drive, to the DAC output node, a DAC output voltage that represents the value of the first N-bit binary number, the DAC output voltage selected, in response to the value of the first N-bit binary number, from the set of 2N analog voltages; and
a set of N analog muxes, each analog mux of the set of N analog muxes configured to drive, in response to a respective input of the second set of N inputs, to a corresponding analog mux output node, the DAC output voltage;
a set of N scaled capacitors, each capacitor of the set of N scaled capacitors electrically connected to a respective analog mux output node and further electrically connected to the local product node, each capacitor of the set of N scaled capacitors having a capacitance value equal to 2n* a unit capacitance value (CUNIT); and
a reference capacitor electrically connected to GND and further electrically connected to the local product node, a value of the reference capacitor equal to CUNIT.

US Pat. No. 10,658,992

OPERATIONAL TRANSCONDUCTANCE AMPLIFIER

Rafael Microelectronics, ...

1. A circuit for implementing an operational transconductance amplifier (OTA), said circuit comprising:a first pair of transistors, comprising a first transistor having a first terminal, a second terminal and a third terminal and a second transistor having a fourth terminal, a fifth terminal and a sixth terminal, wherein the second terminal and the fourth terminal are connected at a first node, and the third terminal and the sixth terminal are connected at a second node;
a second pair of transistors, comprising a third transistor having a seventh terminal, an eighth terminal and a ninth terminal and a fourth transistor having a tenth terminal, an eleventh terminal and a twelfth terminal, wherein the eighth terminal and the eleventh terminal are connected at a third node, and the ninth terminal and the twelfth terminal are connected at a fourth node;
a third pair of transistors, comprising a fifth transistor having a thirteenth terminal, a fourteenth terminal and a fifteenth terminal and a sixth transistor having a sixteenth terminal, a seventeenth terminal and an eighteenth terminal, wherein the fourteenth terminal and the seventeenth terminal are connected to the second node, and the fifteenth terminal and the eighteenth terminal are connected at a fifth node;
a fourth pair of transistors, comprising a seventh transistor having a nineteenth terminal, a twentieth terminal and a twenty-first terminal and an eighth transistor having a twenty-second terminal, a twenty-third terminal and a twenty-fourth terminal, wherein the twentieth terminal and the twenty-third terminal are connected to the fourth node, and the twenty-first terminal and the twenty-fourth terminal are connected at a sixth node;
a fifth pair of transistors, comprising a ninth transistor having a twenty-fifth terminal, a twenty-sixth terminal and a twenty-seventh terminal and a tenth transistor having a twenty-eighth terminal, a twenty-ninth terminal and a thirtieth terminal, wherein the twenty-sixth terminal is connected to the fifth node that is connected to the fifth terminal of the second transistor and the seventh terminal of the third transistor, and the thirtieth terminal is connected to the first node that is connected to the thirteenth terminal of the fifth transistor and the twenty-second terminal of the eighth transistor, wherein the twenty-fifth terminal and the twenty-eighth terminal are connected at a seventh node; and
a sixth pair of transistors, comprising an eleventh transistor having a thirty-first terminal, a thirty-second terminal and a thirty-third terminal and a twelfth transistor having a thirty-fourth terminal, a thirty-fifth terminal and a thirty-sixth terminal, wherein the thirty-third terminal is connected to the sixth node that is connected to the first terminal and the tenth terminal, and the thirty-sixth terminal is connected to the third node that is connected to the sixteenth terminal and the nineteenth terminal, wherein, the thirty-first terminal and the thirty-fourth terminal are connected at an eighth node;
wherein the fourth node and the second node are capable of outputting a first pair of differential signals according to a second pair of differential signals inputted to the seventh node and the eighth node.

US Pat. No. 10,658,991

COMMON BASE PRE-AMPLIFIER

Skyworks Solutions, Inc.,...

1. An amplification system comprising:a pre-amplifier having an input and an output, and configured to amplify a signal received at the input node to generate an intermediate signal at the output;
a power amplifier configured to receive and amplify the intermediate signal from the output of the pre-amplifier to generate an output signal; and
an LC tank circuit including a parallel combination of an inductance and a capacitance implemented to couple the input of the pre-amplifier and a ground.

US Pat. No. 10,658,990

HIGH FREQUENCY AMPLIFIER UNIT HAVING AMPLIFIER MODULES ARRANGED ON OUTER CONDUCTORS

Cryoelectra GmbH, Wupper...

1. A high frequency amplifier unit, comprising:several amplifier modules to amplify high frequency input signals into high frequency output signals; and
a coaxial combiner having an outer conductor and an inner conductor arranged coaxially to this to combine the high frequency output signals of the amplifier modules;
wherein the amplifier modules are arranged on the outside of the outer conductor of the coaxial combiner; and
wherein the amplifier modules are connected to the coaxial inner conductor of the coaxial combiner to transmit the high frequency output signals to the coaxial combiner.

US Pat. No. 10,658,989

SYSTEMS AND METHODS FOR FULL DUPLEX AMPLIFICATION

Cable Television Laborato...

1. An amplification subsystem for a communication system including a first transceiver in communication with a second transceiver over a transmission medium, comprising:a first amplifier configured to transmit a first signal, from the first transceiver to the second transceiver, within a first frequency range;
a second amplifier configured to transmit a second signal, from the second transceiver to the first transceiver, within a second frequency range different from the first frequency range;
a first diplexer disposed along the transmission medium between the first transceiver and the first amplifier;
a second diplexer disposed along the transmission medium between the second transceiver and the second amplifier;
a first bypass circuit in parallel with the first diplexer, and including a first switched bandpass filter configured to transmit the first signal within a third frequency range between the first and second frequency ranges; and
a second bypass circuit in parallel with the second diplexer, and including a second switched bandpass filter configured to transmit the second signal within the third frequency range.

US Pat. No. 10,658,988

OPEN-LOOP CLASS-D AMPLIFIER SYSTEM WITH ANALOG SUPPLY RAMPING

Cirrus Logic, Inc., Aust...

1. A signal processing system, comprising:a modulation stage configured to generate a modulated input signal;
an open-loop switched mode driver coupled to the modulation stage and configured to generate an output signal from the modulated input signal;
a voltage regulator configured to generate a supply voltage that supplies electrical energy to the open-loop switched mode driver; and
a control subsystem configured to, when a magnitude of the modulated input signal falls below a threshold magnitude, control the voltage regulator to control the supply voltage such that the output signal varies non-linearly with the modulated input signal for magnitudes of the modulated input signal below the threshold magnitude.

US Pat. No. 10,658,987

AMPLIFIER CIRCUIT FOR CRYOGENIC APPLICATIONS

Rambus Inc., Sunnyvale, ...

1. An amplifier circuit comprising:a current source;
a first complementary transistor pair coupled between a first source node and a second source node, the first source node being coupled to the current source and the first complementary transistor pair comprising a first input terminal and a first output terminal;
a second complementary transistor pair coupled between the first source node and the second source node, the second complementary transistor pair comprising a second input terminal and a second output terminal;
a first shunt resistor coupled between the first input terminal and the first output terminal; and
a second shunt resistor coupled between the second input terminal and the second output terminal, wherein an input impedance between the first input terminal and the second input terminal is controlled by a transconductance of the first complementary transistor pair and the second complementary transistor pair, wherein the transconductance of the first complementary transistor pair and the second complementary transistor pair is adjusted by a first magnitude of a first well body bias voltage applied to a first well of the first complementary transistor pair and by a second magnitude of a second well body bias voltage applied to a second well of the first complementary transistor pair.

US Pat. No. 10,658,986

METHODS AND APPARATUS FOR DRIVER CALIBRATION

SEMICONDUCTOR COMPONENTS ...

15. An imaging system, comprising:a generator circuit configured to generate a bias voltage;
a current comparator circuit connected to the generator circuit and configured to generate a threshold current;
a controller configured to:
store a plurality of calibration codes; and
transmit one calibration code of the plurality of calibration codes;
a digital-to-analog converter (DAC) connected to the generator circuit and configured to:
receive the calibration code;
generate a DAC voltage; and
generate a calibration voltage according to the calibration code;
a differential operational amplifier (DOA) connected to the DAC and comprising:
a first input terminal and a second input terminal, wherein the DOA is configured to:
receive the DAC voltage at the first input terminal;
receive a feedback voltage at the second input terminal; and
generate an op-amp output voltage at an output terminal;
a driver connected to the output terminal of the DOA and comprising a drive transistor; wherein:
a gate terminal of the drive transistor is connected to the output terminal of the DOA; and
a source terminal of the drive transistor is connected to the second input terminal of the DOA;
a feedback circuit connected to the DAC, the driver, and the DOA, and configured to generate the feedback voltage according to the calibration voltage; and
a replica circuit comprising a replica transistor, wherein:
a gate terminal of the replica transistor is connected to the output terminal of the DOA;
a drain terminal is of the replica transistor is connected to the current comparator circuit; and
a source terminal of the replica circuit is connected to a source terminal of the drive transistor.

US Pat. No. 10,658,985

TRANS-IMPEDANCE AMPLIFIER

HANGZHOU HONGXIN MICROELE...

1. A trans-impedance amplifier, comprising:an inverting amplifier circuit, having an input end and an output end, the input end being coupled to an optical diode and used for accessing an input voltage signal, the output end being used for outputting an amplified voltage signal, the inverting amplifier circuit comprising at least three sequentially-connected amplifier units, the at least three amplifier units are identical, each of the at least three amplifier units comprising two mutually-coupled N-type transistors, one N-type transistor being used for receiving an input voltage, the other N-type transistor being used for receiving a DC voltage signal, a common connection end of the two N-type transistors being used for outputting an amplified voltage signal, wherein the N-type transistor used for receiving a DC voltage signal adopts a native NFET, wherein the inverting amplifier circuit comprises:
a primary amplifier unit, having an input end and an output end, the input end being coupled to an optical diode and used for accessing an input voltage signal, the output end being used for outputting a primarily amplified first voltage signal, wherein the primary amplifier unit comprises:
a first N-type transistor, a second end thereof being coupled to an output end of the optical diode and used for receiving the input voltage signal, a first end thereof being used for outputting the first voltage signal, and a third end thereof being grounded; and
a second N-type transistor, both a first end and a second end thereof being used for receiving the DC voltage signal, and a third end thereof being coupled to the first end of the first N-type transistor;
a secondary amplifier unit, having an input end and an output end, the input end being coupled to the output end of the primary amplifier unit and used for accessing a first voltage, the output end being used for outputting a secondarily amplified second voltage signal; and
a tertiary amplifier unit, having an input end and an output end, the input end being coupled to the output end of the secondary amplifier unit and used for accessing a second voltage, and the output end being used for outputting a tertiarily amplified voltage signal; and
a feedback resistor, coupled to the input end and the output end of the inverting amplifier circuit.

US Pat. No. 10,658,983

AMPLIFIER AND TRANSMITTER

KABUSHIKI KAISHA TOSHIBA,...

1. An amplifier comprising:a first amplifier to amplify an inputted first signal;
at least two second amplifiers to amplify at least two of inputted second signals;
a first output network connected to an output node of the first amplifier and a node connected to a load;
at least two second output networks which are connected to output nodes of the at least two of second amplifiers and which are electrically connected to the node connected to the load; and
at least two first bias networks, wherein one of the first bias networks is connected to the first output network and at least one of the first bias networks is connected to at least one of the second output networks to supply D.C. voltages to at least one of the first output network or the second output networks;
wherein an electrical length of the first bias networks is less than 90 degrees,
the D.C. voltages supplied by the first bias networks have a same voltage level, and
an electrical length of at least one of the first output network, the second output networks, or the first bias networks are reconfigurable.

US Pat. No. 10,658,982

DYNAMICALLY LINEARIZING MULTI-CARRIER POWER AMPLIFIERS

MOTOROLA SOLUTIONS, INC.,...

1. A host controller for a radio frequency (RF) power amplifier linearizer of a radio frequency (RF) transmitter, the host controller comprising:a memory storing a correction set including a plurality of correction solutions, each one of the plurality of correction solutions corresponding to one of a plurality of carrier configurations; and
an electronic processor coupled to the memory and configured to
load the correction set into the RF power amplifier linearizer,
determine a first carrier configuration of the RF transmitter during a first timeslot of operation of the RF transmitter,
send a first correction solution index to the RF power amplifier linearizer, the first correction solution index corresponding to a first correction solution of the plurality of correction solutions,
determine that a carrier configuration change is initiated to operate the RF transmitter with a second carrier configuration during a second timeslot of operation of the RF transmitter, the second timeslot being subsequent to the first timeslot, and
send a second correction solution index to the RF power amplifier linearizer, the second correction solution index corresponding to a second correction solution of the plurality of correction solutions.

US Pat. No. 10,658,981

LINEARIZATION CIRCUITS AND METHODS FOR MULTILEVEL POWER AMPLIFIER SYSTEMS

Eta Devices, Inc., Cambr...

1. An amplifier system having one or more inputs and one or more RF outputs, the system comprising:one or more RF amplifiers each having one or more RF inputs, one or more RF outputs, and a power supply input;
a voltage control unit coupled to provide a power supply voltage to the power supply input of at least one of the one or more RF amplifiers wherein said voltage control unit dynamically selects the power supply voltage from among a discrete set of voltages based in part upon one or more signal characteristics of one or more signals to be transmitted; and
a controller configured to generate (i) control signals for the voltage control unit and (ii) one or more predistorted signals for at least one of the RF amplifiers, wherein the one or more predistorted signals are generated based, at least in part, on selected power supply voltages.

US Pat. No. 10,658,980

MODULATING INPUT DEVICE HAVING A FULL WAVE RECTIFIER

Honeywell International I...

1. An actuator circuit comprising:a rectifier having a supply ground input and a supply voltage input and a device ground output and a device voltage output;
a control signal source output;
an operational amplifier having a first input for a first voltage between the supply ground input and the device ground output, and a second input for a second voltage between the control signal source output and the device ground output; and
a linearization circuit having an input connected to an output of the operational amplifier and having an output that can go to zero.

US Pat. No. 10,658,979

POWER AMPLIFIER WITH SUPPLY SWITCHING

Avago Technologies Intern...

1. A power amplifier, comprising:a gain circuit;
a supply switch circuit configured to determine whether a magnitude of an outgoing broadband communication signal exceeds a predetermined voltage threshold;
a first bias transformer coupled to a first voltage supply rail and configured to bias the gain circuit with the first voltage supply rail; and
a second bias transformer coupled to a second voltage supply rail smaller than the first voltage supply rail and configured to bias the gain circuit with the second voltage supply rail,
wherein the gain circuit is configured to:
apply a first gain to the outgoing broadband communication signal using the first voltage supply rail when the magnitude exceeds the predetermined voltage threshold;
apply a second gain to the outgoing broadband communication signal using the second voltage supply rail when the magnitude does not exceed the predetermined voltage threshold; and
produce an output signal from the outgoing broadband communication signal with the applied first gain or the applied second gain.

US Pat. No. 10,658,978

METHOD FOR CONFIGURING POWER IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREOF

Samsung Electronics Co., ...

1. An electronic device, comprising:an antenna array comprising a plurality of antenna elements;
a communication circuit comprising a receive path and a transmit path, the receive path comprising a plurality of first power amplifiers connected with the plurality of antenna elements and a plurality of first phase shifters and the transmit path comprising a plurality of second power amplifiers connected with the plurality of antenna elements and a plurality of second phase shifters;
at least one processor operatively connected to the communication circuit; and
a memory operatively connected to the at least one processor and stores instructions,
wherein the instructions, when executed by the at least one processor, cause the at least one processor to:
transmit, via the plurality of antenna elements, a first signal using the plurality of second power amplifiers with initial power gain configuration,
obtain a transmit power of a specified power amplifier among the plurality of second power amplifiers, the transmit power being associated with transmission of the first signal,
determine a calibration value to calibrate a power gain of at least one second power amplifier among the plurality of second power amplifiers based on the transmit power,
store the calibration value in the memory, and
change a parameter associated with at least one of the plurality of second phase shifters in a state where the power gain is changed based on the calibration value.

US Pat. No. 10,658,977

POWER AMPLIFIERS ISOLATED BY DIFFERENTIAL GROUND

Skyworks Solutions, Inc.,...

1. A mobile device comprising:a transceiver configured to generate a plurality of radio frequency input signals including a first radio frequency input signal and a second radio frequency input signal, the transceiver configured to control the plurality of radio frequency input signals to provide beam forming; and
a plurality of differential power amplifiers including a first differential power amplifier configured to provide amplification to the first radio frequency input signal and a second differential power amplifier configured to provide amplification to the second radio frequency input signal, the first differential power amplifier and the second differential power amplifier each configured to operate with differential ground so as to provide isolation between the first differential power amplifier and the second differential power amplifier.

US Pat. No. 10,658,976

LOW POWER CRYSTAL OSCILLATOR

UNITED MICROELECTRONICS C...

1. A crystal oscillator comprising:a first transistor comprising a first terminal coupled to a first reference terminal, a second terminal, and a control terminal coupled to a first bias terminal;
a second transistor comprising a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to a second bias terminal, and a control terminal coupled to an output terminal of the crystal oscillator;
a third transistor comprising a first terminal coupled to the first reference terminal, a second terminal, and a control terminal;
a fourth transistor comprising a first terminal coupled to the first reference terminal, a second terminal, and a control terminal coupled to the control terminal of the third transistor;
a fifth transistor comprising a first terminal coupled to the second bias terminal, a second terminal coupled to a second reference terminal, and a control terminal coupled to the second bias terminal;
a sixth transistor comprising a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the second reference terminal, and a control terminal coupled to the second bias terminal;
a seventh transistor comprising a first terminal coupled to the second terminal of the fourth transistor, a second terminal coupled to the second reference terminal, and a control terminal;
an eighth transistor comprising a first terminal coupled to the first reference terminal, a second terminal coupled to the output terminal of the crystal oscillator, and a control terminal coupled to the control terminal of the third transistor;
a ninth transistor comprising a first terminal coupled to the output terminal of the crystal oscillator, a second terminal coupled to the second reference terminal, and a control terminal coupled to the control terminal of the seventh transistor; and
a crystal element comprising a first terminal coupled to the control terminal of the seventh transistor, and a second terminal coupled to the first terminal of the seventh transistor.

US Pat. No. 10,658,975

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. An integrated circuit device comprising:a first digital controlled oscillator, wherein the first digital controlled oscillator comprises:
a first set of inductors, each one of the first set of inductors having a first inductance;
a second set of inductors, each one of the second set of inductors having a second inductance different from the first inductance, wherein individual ones of the first set of inductors are in series with individual ones of the second set of inductors;
a switched capacitor array connected between the first set of inductors and the second set of inductors;
a first active feedback device connected to the first set of inductors;
a second active feedback device connected to the first set of inductors; and
a capacitor connected between a first inductor of the first set of inductors and a second inductor of the first set of inductors, the capacitor having a constant capacitance; and
a second digital controlled oscillator coupled to the first digital controlled oscillator.

US Pat. No. 10,658,974

QUADRATURE OSCILLATOR, FSK MODULATOR, AND OPTICAL MODULE

FUJITSU LIMITED, Kawasak...

1. A quadrature oscillator comprising:a first oscillator that outputs a first differential signal; and
a second oscillator that outputs a second differential signal having phases that are different from those of the first differential signal,
wherein the first oscillator includes a first LC resonator having an inductor and a capacitor coupled in parallel, a first cross-coupled circuit having a first pair of cross-coupled transistors coupled to the first LC resonator, a first tail current source coupled to the first pair of transistors, first input differential pair transistors to which the second differential signal is to be input, and a first pair of harmonic resonators disposed in input sections of the first input differential pair transistors,
the second oscillator includes a second LC resonator having an inductor and a capacitor coupled in parallel, a second cross-coupled circuit having a second pair of cross-coupled transistors coupled to the second LC resonator, a second tail current source coupled to the second pair of transistors, second input differential pair transistors to which the first differential signal is to be input, and a second pair of harmonic resonators disposed in input sections of the second input differential pair transistors,
the first pair of the harmonic resonators have a resonance frequency of an odd multiple of a resonance frequency of the first oscillator, and
the second pair of the harmonic resonators have a resonance frequency of an odd multiple of a resonance frequency of the second oscillator.

US Pat. No. 10,658,973

RECONFIGURABLE ALLOCATION OF VNCAP INTER-LAYER VIAS FOR CO-TUNING OF L AND C IN LC TANK

International Business Ma...

1. An inductor-capacitor (LC) tank oscillator, comprising:a capacitor comprising at least two metal layers, each metal layer having metal fingers that are interdigitated, wherein an orientation of the metal fingers alternates amongst the at least two metal layers;
an inductor on the capacitor,
wherein an inductance and a capacitance in the LC tank oscillator are tuneable, and wherein the LC tank oscillator further comprises:
inter-layer vias interconnecting the at least two metal layers, wherein an arrangement of the inter-layer vias in an area between the at least two metal layers is configured to co-tune both the inductance and the capacitance in the LC tank oscillator.

US Pat. No. 10,658,971

PHOTOVOLTAIC MODULE AND PHOTOVOLTAIC SYSTEM INCLUDING THE SAME

LG ELECTRONICS INC., Seo...

1. A photovoltaic module comprising:a solar cell module;
a converter to convert a direct current (DC) voltage from the solar cell module;
an inverter to convert the DC voltage from the converter into an alternating current (AC) voltage;
a plug to outwardly output the AC voltage from the inverter, the plug having a ground terminal;
a first interface unit to receive an AC voltage from an adjacent photovoltaic module;
a second interface unit to output the AC voltage from the first interface unit and the AC voltage from the inverter to the plug; and
a cable provided in order to electrically connect the first interface unit and the second interface unit to each other,
wherein a first connector for coupling with the first interface unit is connected to one end of the cable, and the other end of the cable is electrically connected to the second interface unit,
wherein the ground terminal of the plug is electrically connected to a ground terminal of the inverter,
wherein the ground terminal of the inverter is electrically connected to a ground line of the solar cell module,
wherein the plug is connected to an outlet including a ground terminal or a connector including a ground terminal, and
wherein the ground terminal of the plug is connected to the ground terminal of the outlet or the ground terminal of the connector.

US Pat. No. 10,658,970

MAINTAINING A SOLAR POWER MODULE

Saudi Arabian Oil Company...

1. A method for cleaning a solar power system, comprising:operating a solar power system that comprises a plurality of solar power cells mounted on a spherical frame, where the plurality of solar power cells are mounted on an upper hemispherical portion of the spherical frame;
rotating the spherical frame to move the plurality of solar power cells into a volume of a hemispherical reservoir that is mounted to the spherical frame, the hemispherical reservoir mounted to the spherical frame to enclose a lower hemispherical portion of the spherical frame;
rotating the spherical frame to move the plurality of solar power cells mounted on the upper hemispherical portion of the spherical frame into a solar cell cleaning solution fluid enclosed within the volume of the hemispherical reservoir defined between an interior surface of the reservoir and the spherical frame;
rotating the spherical frame to move another plurality of solar power cells mounted to the lower hemispherical portion of the spherical frame out of the solar cell cleaning solution; and
removing, with the solar cell cleaning solution, a plurality of particulates attached to the plurality of solar power cells.

US Pat. No. 10,658,969

PHOTOVOLTAIC SOLAR ROOF TILE ASSEMBLY

SOLARMASS ENERGY GROUP LT...

1. A photovoltaic solar roof tile assembly comprising:a roof tile having a front side and a rear side and a hole extending through the tile;
a circuit board having a front side and a rear side, the rear side of the circuit board facing the front side of the roof tile,
a photovoltaic solar panel having a front side and a rear side, the rear side of the photovoltaic solar panel facing the front side of the circuit board,
a junction located in the hole extending through the tile, wherein the junction comprises a first DC connector and a second DC connector,
a female plug located in the hole in the roof tile, the female plug including a positive conductor and a negative conductor extending from both a first end and second end of the female plug, the positive and negative conductors extending from the first end comprising the second DC connector,
wherein the first DC connector further comprises a positive conductor and a negative conductor, the positive conductor electrically connected to the positive output of the photovoltaic solar panel and the negative conductor electrically connected to the negative output of the photovoltaic solar panel, and
wherein the positive conductor of the first DC connector is electrically connected to the positive conductor of the second DC connector extending from the first end of the female plug and the negative conductor of the first DC connector is electrically connected to the negative conductor extending from the first end of the second DC connector, the positive conductor and negative conductor extending from the second end of the female plug for connection to an electrical circuit,
wherein the photovoltaic solar panel, circuit board and the first DC connector form a laminated structure, with the first DC connector sealed to the laminated structure, the first DC connector being accessible from the rear side of the roof tile and attachable and detachable from the second DC connector, and wherein one of the first DC connector and second DC connector include a diode.

US Pat. No. 10,658,968

NEAR-FIELD BASED THERMORADIATIVE DEVICE

Mitsubishi Electric Resea...

17. A method for generating power, comprising:providing a thermoradiative element having a top surface and a bottom surface, wherein the thermoradiative element is a semiconductor material having a bandgap energy; and
placing a thermal conductive element having a first surface and a second surface in parallel to the thermoradiative element, wherein the first surface is arranged to face the bottom surface of the thermoradiative element, wherein the first surface is a structured surface having a periodic structure, wherein the structured surface is separated from the bottom surface with a distance d to establish near-field resonance between the bottom surface and the structured surface.

US Pat. No. 10,658,967

MOTOR DRIVE APPARATUS AND AIR CONDITIONER

Mitsubishi Electric Corpo...

1. A motor drive apparatus driving a motor, comprising:inverter modules equivalent in number to phases of the motor; and
a control unit generating a PWM signal used to drive the inverter modules with PWM, wherein
the inverter modules each include a plurality of switching element pairs connected in parallel, each of the switching element pairs including two switching elements connected in series,
at least one of the inverter modules includes:
a first drive control unit configured to generate first PWM signals for controlling the switching elements provided in an upper arm of the switching element pairs; and
a second drive control unit configured to generate second PWM signals for controlling the switching elements provided in a lower arm of the switching element pairs, and
a pulse width of at least one of the first PWM signals or the second PWM signals is increased/decreased by an amount according to a temperature difference between the switching elements provided within the upper arm or within the lower arm.

US Pat. No. 10,658,966

MOTOR DRIVING APPARATUS, REFRIGERATOR, AND AIR CONDITIONER

Mitsubishi Electric Corpo...

1. A motor driving apparatus used for driving a motor comprising a plurality of winding groups, each of the winding groups comprising three winding portions to which a three-phase alternating-current voltage is applied, each of the winding groups forming an electrically independent circuit, the motor driving apparatus comprising:at least one inverter applying the alternating-current voltage to at least one of the winding groups; and
an induced voltage detector detecting an induced voltage induced by at least one of the winding portions of at least one of the winding groups
wherein when stopping any of the plurality of inverters, an inverter including the induced voltage detector is stopped.

US Pat. No. 10,658,965

MOTOR VEHICLE

TOYOTA JIDOSHA KABUSHIKI ...

1. A motor vehicle comprising:a first motor connected with one wheels out of front wheels and rear wheels;
a first inverter configured to drive the first motor by switching of a plurality of first switching elements;
a second motor connected with the other wheels out of the front wheels and the rear wheels;
a second inverter configured to drive the second motor by switching of a plurality of second switching elements;
a power storage device connected with the first inverter and the second inverter via a power line;
a control device configured to control the first inverter and the second inverter; and
an overcurrent detector configured to detect overcurrent in each of the plurality of second switching elements,
wherein when the motor vehicle has an abnormality and is driven by emergency drive with output of a torque from the first motor to the one wheels, the control device performs zero torque control that controls the second inverter such that a torque of the second motor becomes equal to zero, and
wherein when temperature of a coil of the second motor is monitored during the emergency drive, the control device performs gate shutoff of the second inverter and determines whether an on-failure occurs in any of the plurality of second switching elements, based on the temperature of the coil.

US Pat. No. 10,658,964

MOTOR DRIVING APPARATUS, VACUUM CLEANER, AND HAND DRYER

Mitsubishi Electric Corpo...

1. A motor driving apparatus driving an electric blower including a single-phase permanent magnet synchronous motor, the motor driving apparatus comprising:a single-phase inverter applying an alternating-current voltage to the single-phase permanent magnet synchronous motor, the inverter including switching elements;
a position detecting unit outputting a position detecting signal that is a signal corresponding to a rotational position of a rotor of the single-phase permanent magnet synchronous motor;
a current detecting unit outputting a signal corresponding to a motor current flowing to the single-phase permanent magnet synchronous motor; and
an inverter control unit receiving the position detecting signal and the motor current and outputting a driving signal to corresponding one of the switching elements of the single-phase inverter, wherein
the single-phase inverter individually increases or reduces reactive power and effective electric power supplied to the single-phase permanent magnet synchronous motor,
the electric blower changes an air volume by the individual increase or reduce in the reactive power and the effective electric power, and
the reactive power is changed only when a rotational speed of the single-phase permanent magnet synchronous motor reaches a specific rotational speed.

US Pat. No. 10,658,963

FLUX OBSERVER-BASED CONTROL STRATEGY FOR AN INDUCTION MOTOR

GM Global Technology Oper...

10. An electrical system comprising:an induction motor having a rotor and a stator;
a rotary position sensor configured to output a position signal indicative of a measured angular position of the rotor; and
a controller programmed to regulate operation of the induction motor via execution of instructions, wherein execution of the instructions causes the controller to:
calculate a rotor flux angle error value, via a flux observer, using an estimated d-axis flux value and an estimated q-axis flux value of the rotor, wherein the flux observer operates in a synchronous frame of reference of the induction motor;
estimate a position of the rotor, using the position signal and a position observer, to thereby generate an estimated rotor position, wherein the position observer operates in a stationary frame of reference of the induction motor;
calculate a slip position of the rotor, via the position observer, using a d-axis current and a q-axis current of the stator;
estimate a flux angle of the rotor as a function of the slip position and the estimated rotor position to thereby generate an estimated rotor flux angle;
calculate a corrected rotor flux angle by selectively adding the rotor flux angle error value to the estimated rotor flux angle; and
control output torque of the induction motor using the corrected rotor flux angle.

US Pat. No. 10,658,962

METHOD, ANGLE DETERMINATION APPARATUS AND CONTROL APPARATUS

Robert Bosch GmbH, Stutt...

1. A method for determining a rotor angle (1) of a rotor (2) of an electric machine (3), having the following steps:generating (S1) a torque-dependent test signal (5) that depends on the torque (4) of the electric machine (3) and has a higher frequency than a supply signal (6) for the electric machine (3),
driving the electric machine (3) with the supply signal (6) and with the test signal (5) which is superimposed on the supply signal (6),
capturing phase currents (13, 14, 15) of the electric machine (3), and
determining the rotor angle (1) of the rotor (2) of the electric machine (3) on the basis of the effects of the test signal (5) on the phase currents (13, 14, 15);
wherein a direction of the test signal (5) is selected in accordance with the current torque (4) of the electric machine (3) such that a resulting high-frequency oscillation of the motor current indicator only minimally affects the torque (4) of the electric machine (3).

US Pat. No. 10,658,961

METHOD FOR IDENTIFYING THE DISCRETE INSTANTANEOUS ANGULAR SPEED OF AN ELECTROMECHANICAL SYSTEM

ABB Schweiz AG, Baden (C...

1. A method for identifying a discrete instantaneous angular speed ?d of a motor or generator of an electromechanical system, by measuring analog stator current signals IsA, IsB, IsC for at least one phase A, B, C, and analog stator voltage signals UsA, UsB, Usc signals for at least one phase A, B, C and by converting said measurements into a digital discrete form to obtain discrete stator current signals and discrete stator voltage signals, the method comprising:transmitting said digital discrete signals to a computer device wherein data analysis is performed in a processor unit, on the basis of a simplified mathematical model of the dynamics of the motor or generator, said simplified mathematical model being based upon manipulations of a stator voltage equation for a smooth-air-gap machine and a rotor voltage equation for a smooth-air-gap machine, said manipulations involving simplifying assumptions that a complex rotor flux-linkage space phasor in the stationary reference frame changes slowly in comparison to a complex stator flux-linkage space phasor, that ohmic losses in the motor or generator are negligible and that leakage inductances of the motor or generators are low,
identifying an average supply frequency value, ?L, from one or more of the discrete stator current signals or discrete stator voltage signals,
identifying an average angular speed, ? from one or more of the discrete stator current signals or discrete stator voltage signals,
identifying an instantaneous phase difference between the discrete stator current signals and the discrete stator voltage signals, ØUI,d from one or more of the discrete stator current signals and one or more of the discrete stator voltage signals,
determining an average rotor time constant, ?r on the basis of the simplified mathematical model of the dynamics of the motor or generator using one or more of the discrete stator current signals and one or more of the discrete stator voltage signals,
identifying a discrete instantaneous angular speed ?d according to the formula:

where:
p is a number of pole pairs of the electric motor
wL is an average supply frequency value,
tr is an average rotor time constant
fUI,d is an instantaneous phase difference between the discrete stator current signals and the discrete stator voltage signals,
storing the result of combining said data in a memory of the processor unit.

US Pat. No. 10,658,960

MOTOR CONTROL SYSTEM AND MOTOR CONTROL METHOD

Hitachi, Ltd., Tokyo (JP...

14. A motor control method for applying AC voltage to a motor in response to a voltage command, comprising:estimating a plurality of evaluation values of the motor or an object to be driven by the motor from at least one state quantity of the motor by using a plurality of regression formulas, in which the state quantity is an input variable and the plurality of evaluation values are output variables;
calculating an evaluation function with the estimated plurality of evaluation values as arguments; and
changing the voltage command based on a calculation value resulting from the evaluation function.

US Pat. No. 10,658,959

POWER SUPPLY SYSTEM WITH FIRST AND SECOND AC VOLTAGE GENERATORS AND RESPECTIVE 6-PULSE RECTIFIER UNITS

HAMILTON SUNSTRAND CORPOR...

1. A power supply comprising:first and second ac voltage generators, wherein both the first and second ac voltage generators are connected to one or more loads and wherein the first and second ac voltage generators are connected to respective first and second 6-pulse rectifier units for rectifying ac voltage from each of the first and second ac voltage generators to a dc voltage output for the loads,
wherein each of the first and second ac voltage generators comprises two 3-phase voltage sources separated by a phase shift,
wherein the voltage output from each rectifier unit is coupled to the loads via a respective interphase inductor; and
a third ac voltage generator connected to the one or more loads and having a further two 3-phase voltage sources separated by a phase shift and further comprising a respective further rectifier unit for each of the further two 3-phase voltage sources;
wherein:
a first rectifier unit receives inputs from a first 3-phase source (a,c) of each of the first and second ac voltage generators and a second rectifier unit receives inputs from a second 3-phase source (b,d) of each ac voltage generator;
wherein the first rectifier unit provides a first dc output (e) and the second rectifier unit provides a second dc output (f);
wherein the first dc output (e) is connected to the loads and to the second rectifier unit via a first interphase inductor, and the second dc output (f) is connected to the loads and to the first rectifier unit via a second interphase inductor; and
wherein the two sources for the third ac voltage generator are connected into the output via two further rectifier units, which are also connected in parallel via respective interphase inductors to output the loads;
wherein the power supply is in combination with a geared turbofan engine, wherein the second ac voltage generator is associated with a high spool side of the engine and the third ac voltage generator is associated with a low spool side of the generator.

US Pat. No. 10,658,958

GENSET

1. A genset with at least one generator for generating electrical energy, driven by a drive device, comprising:a detection device for detecting a presence of a grid fault in at least one phase of a power grid;
a device for determining an operating state of the at least one generator immediately before or upon detection of the grid fault;
a regulating device to which signals from the detection device and the device for determining the operating state can be fed, wherein the regulating device is designed to regulate power of the drive device upon detection of the grid fault, in dependence on a specific operating state of the at least one generator determined by the device for determining the operating state, which occurred immediately before or during detection of the grid fault; and
a load angle device for calculating a current load angle of the at least one generator, whose signals can be fed to the regulating device, wherein the regulating device is designed to maintain and reinforce measures to reduce power of the drive device upon reaching or exceeding a predetermined threshold value by using a Moment of inertia of the genset and the load angle and to terminate or reduce measures to reduce power of the drive device upon falling below the predetermined threshold value.

US Pat. No. 10,658,957

POWER TOOL

Koki Holdings Co., Ltd., ...

1. A power tool comprising:a brushless motor configured to drive and rotate when a voltage applied to the brushless motor is larger than or equal to an induced voltage;
a supplying circuit configured to apply a driving voltage to the brushless motor; and
a controller configured to control the supplying circuit,
wherein the supplying circuit includes:
a rectifying circuit configured to rectify an alternating voltage and output a rectified voltage;
a capacitor configured to smooth the voltage inputted via the rectifying circuit; and
a switching circuit configured to perform a switching operation based on a PWM signal to adjust a period during which the driving voltage is applied,
wherein the controller is configured to set a duty ratio within a prescribed range, and output the PWM signal of the set duty ratio to the switching circuit to control the switching operation,
wherein the controller is configured to perform a constant-number-of-rotation control (constant rotational speed control) for controlling the brushless motor to rotate at a constant target rotation number by changing the duty ratio,
wherein the capacitor has a capacitance allowing a smoothed voltage to be always larger than or equal to the induced voltage during the constant-number-of-rotation control (constant rotational speed control),
wherein the controller is capable of maintaining the constant speed control when a load of the motor is smaller than or equal to a first load and incapable of maintaining the constant speed control when the load of the motor is larger than the first load,
wherein the capacitor has the capacitance which allows the smoothed voltage to be always larger than the pulsating induced voltage in a case where the load of the motor is smaller than or equal to the first load, and allows a minimum of the smoothed voltage to be smaller than the pulsating induced voltage in a case where the load of the motor exceeds a second load larger than the first load.

US Pat. No. 10,658,956

PROCESS OF OPERATING A HYBRID CONTROLLER FOR BRUSHLESS DC MOTOR

Texas Instruments Incorpo...

1. A process of operating a motor comprising:receiving in a processor a feedback signal associated with the motor, the feedback signal indicating a voltage pattern across a phase winding and a center tap connection of the motor;
detecting in the processor a transition from a mutual inductance zero crossing (MIZO) condition to a back electromotive force zero crossing (BEMFZO) condition based on the feedback signal;
commutating the motor before the transition is detected by the processor with a mutual inductance controller coupled to the processor;
commutating the motor upon and after the transition is detected by the processor with a BEMF controller coupled to the processor; and
determining the transition in the processor when the voltage pattern includes a number of successive pulses with a constant polarity before a zero crossing event, and when the number exceeds a predetermined threshold.

US Pat. No. 10,658,955

SENSORLESS CONTROL SYSTEM FOR PERMANENT MAGNET SYNCHRONOUS MACHINE

LSIS CO., LTD., Anyang-s...

1. A sensorless control system for a permanent magnet synchronous machine, comprising:a counter electromotive force estimation unit configured to estimate a counter electromotive force of the permanent magnet synchronous machine using a current and a first voltage reference, wherein the first voltage reference is converted, by a conversion unit, into a second voltage reference, the second voltage reference is converted, by a control unit, into a third voltage reference, and the third voltage reference is applied from the control unit to an inverter, wherein the third voltage reference is synthesized by the inverter to be applied to the permanent magnet synchronous machine; and
a speed estimation unit configured to estimate an angular velocity and an electrical angle of a rotor of the permanent magnet synchronous machine using the estimated counter electromotive force that is estimated in the counter electromotive force estimation unit,
wherein the counter electromotive force estimation unit is configured to:
determine a state variable based on the current and inductances in a synchronous reference frame, and
estimate the counter electromotive force based on a weighted value, the current, and the first voltage reference, wherein the weighted value is determined by comparing the estimated angular velocity with a reference angular velocity,
wherein the weighted value is a value in a range of 0 to 1,
wherein the speed estimation unit includes a proportional controller configured to apply a proportional gain to an error between an actual angle and an estimated angle using the estimated counter electromotive force,
wherein the counter electromotive force estimation unit includes a first integration unit configured to integrate an output of a first adding unit to output the estimated counter electromotive force.

US Pat. No. 10,658,954

CALIBRATION OF 3-PHASE MOTOR CURRENT SENSING FOR SURGICAL ROBOTIC ACTUATORS

VERB SURGICAL INC., Sant...

1. A method for calibration of 3-phase motor current sensing, comprising:monitoring an output of a first phase current sensor while adjusting one or more of a first phase voltage, a second phase voltage, and a third phase voltage, until the monitored output reaches a zero reference;
capturing an output of a second phase current sensor while the monitored output of the first phase current sensor is at the zero reference; and
storing in memory calibration data that is based on the captured output of the second phase current sensor.

US Pat. No. 10,658,953

METHODS AND DEVICES FOR UNIVERSAL BRAKING, SAFE START PROTECTION, AND OTHER MOTOR CONTROL FOR ALTERNATING CURRENT DEVICES

1. A circuit for a smart braking system, the circuit comprising:an electricity input connector;
an electricity output connector configured to connect with an electrical connection of a user device having an AC motor; and
a motor brake sub-system connected to receive electricity from the electricity input connector and to output electricity to the electricity output connector, the motor brake sub-system including a sub-circuit including switches, which when triggered, activate the motor brake sub-system to output DC power to the user device, thereby applying a counter-rotational stopping torque to the AC motor and decelerating rotation of a rotating component of the user device,
wherein the circuit has a plurality of functional states including:
a first state, activated via manual actuation of an on switch, in which electricity is supplied to the user device to allow rotation of the rotating component,
a second state, activated via manual actuation of a braking switch, in which the motor brake sub-system is activated to decelerate the rotation of the rotating component, and
a third state, activated once the rotating component has ceased rotation, in which no electricity is supplied to the user device to prevent unintentional rotation of the rotating component.

US Pat. No. 10,658,952

DRIVE SYSTEM

1. A drive system, comprising:a power converter;
a motor powered from the power converter via supply leads;
an electromagnetically actuatable brake disposed on the motor;
an AC/DC converter adapted to supply and control the brake; and
a DC/AC converter powered and/or controlled by signal electronics of the power converter, the DC/AC converter adapted to power the AC/DC converter via lines connected between the DC/AC converter and the AC/DC converter.

US Pat. No. 10,658,951

ELECTRIC WORKING MACHINE AND METHOD FOR SMOOTHING AC POWER SUPPLIED THERETO

MAKITA CORPORATION, Anjo...

1. An electric working machine comprising:a motor;
a rectifier circuit configured to rectify an AC power inputted from an AC power supply and to output a rectified power, the AC power fluctuating periodically;
a capacitor including a first electrode and a second electrode, the first electrode being electrically coupled with the rectifier circuit, the capacitor being configured to be charged by the rectified power outputted from the rectifier circuit and to smooth the rectified power;
a first switching element, which is a switching element electrically coupled with the second electrode;
a resistive element including a first terminal electrically coupled with the second electrode;
a drive circuit configured to drive the motor based on a power smoothed by the capacitor;
a peak voltage value acquirer configured to acquire a peak voltage value, which is a maximum absolute value of a voltage of the AC power; and
a controller configured to bring the first switching element into conduction in a case where the AC power is inputted to the rectifier circuit and where a specified conducting condition based on the peak voltage value acquired by the peak voltage value acquirer is satisfied,
wherein the first switching element and/or the resistive element are/is arranged so as to allow a charging current to flow from the rectifier circuit to the capacitor and a discharging current to flow from the capacitor to the drive circuit,
wherein the resistive element includes a second terminal,
wherein the electric working machine further comprises a second switching element, which is a switching element electrically coupled with the second terminal, and
wherein the controller is configured to bring the second switching element into conduction when the AC power is inputted to the rectifier circuit, and to subsequently bring the first switching element into conduction when the conducting condition is satisfied.

US Pat. No. 10,658,950

PIEZOELECTRIC ACTUATOR, PIEZOELECTRIC MOTOR, ROBOT, AND ELECTRONIC COMPONENT CONVEYANCE APPARATUS

Seiko Epson Corporation, ...

1. A piezoelectric actuator comprising:a vibrating plate having a piezoelectric material extending along a first direction in a plan view, the vibrating plate being rectangular-shaped having four sides including a first side, the first side extending along a second direction perpendicular to the first direction in the plan view, a concave being provided in the first side of the vibrating plate; and
a contact member provided at the first side of the vibrating plate, the contact member being configured with first and second members connected to each other, a side of the first member directly contacting a driven part, an end of the second member being inserted into the concave provided in the first side of the vibrating plate,
wherein a length of the first member along the second direction in the plan view is longer than a width of the second member along the second direction in the plan view, and
a width of the first member along the first direction in the plan view is shorter than a length of the second member along the first direction in the plan view.

US Pat. No. 10,658,949

ELECTRICAL ARCHITECTURE FOR CONVERTING DC VOLTAGE INTO AC VOLTAGE, AND VICE VERSA

Valeo Systemes de Control...

1. An electrical architecture comprising:a DC/AC voltage converter for converting a DC voltage into an AC voltage and for converting an AC voltage into a DC voltage, comprising a plurality of arms assembled in parallel, each arm comprising two controllable switching cells, in series and separated by a midpoint, the arms being paired according to H-bridges; and
for each H-bridge, a dedicated control block, such that all the switching cells of said H-bridge can be controlled by the dedicated control block, each dedicated control block being configured to communicate with a same remote control unit through a potential barrier,
wherein the each dedicated control block includes at least one selected from the group consisting of:
a digital processing unit configured to communicate with the remote control unit,
a device for measuring at least one electrical quantity in the H-bridge, and
a device for measuring the temperature in the H-bridge.

US Pat. No. 10,658,948

DC/AC ELECTRICAL POWER CONVERTER DEVICE FOR A VARIABLE-SPEED MOTOR AND A HIGH-SPEED MOTOR

1. A DC/AC electrical power converter device comprising:inlet terminals for electrically connecting to a DC electricity power supply network,
outlet terminals for electrically connecting to an electric motor,
a chopper electrical converter coupled to said inlet terminals,
an electrical inverter coupled between the chopper electrical converter and said outlet terminals, and
a control unit for controlling the electrical inverter and that is configured to operate using pre-calculated pulse width modulation with pre-calculated unchanging switching instants for controlled switches of the electrical inverter regardless of a frequency of rotation of the motor and of a voltage of the electricity network for connection to said device,
wherein the switching instants are angles at which additional switching takes place to eliminate predetermined harmonics from a spectrum of voltage supplied to the motor, and the switching instants are pre-calculated to eliminate the predetermined harmonics.