US Pat. No. 10,510,799

ABSORPTION ENHANCEMENT STRUCTURE FOR IMAGE SENSOR

Taiwan Semiconductor Manu...

15. An integrated chip, comprising:a substrate comprising a plurality of sidewalls defining a first protrusion and a second protrusion disposed along a first side of the substrate;
an image sensing element arranged within the substrate; and
wherein the first protrusion comprises a first sidewall having a first flat segment and the second protrusion comprises a second sidewall having a second flat segment, the first flat segment is coupled to the second flat segment by a horizontally extending surface of the substrate that is between the first protrusion and the second protrusion.

US Pat. No. 10,510,797

SEMICONDUCTOR IMAGE SENSOR

TAIWAN SEMICONDUCTOR MANU...

1. A back side illumination (BSI) image sensor comprising:a substrate comprising a front side and a back side opposite to the front side;
a plurality of pixel sensors disposed in the substrate, and each of the pixel sensors comprising a photo-sensing device and a plurality of micro structures disposed over the photo-sensing device on the back side of the substrate;
an isolation structure disposed in the substrate;
a plurality of color filters comprising a side wall disposed over the pixel sensors on the back side of the substrate;
a grid disposed over the backside of the substrate comprising a side wall in contact with the side wall of the color filter; and
a plurality of micro-lenses disposed over the color filter,wherein the micro structures and the photo-sensing device of one of the pixel sensors are isolated from the micro structures and the photo-sensing device of an adjacent pixel sensor by the isolation structure.

US Pat. No. 10,510,792

3DIC SEAL RING STRUCTURE AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate;
a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip comprising a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate;
a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, the first conductive feature having a first width in the plurality of first dielectric layers;
a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip, the first seal ring structure having the first width in the plurality of first dielectric layers, the first seal ring structure being electrically isolated from the first conductive feature, wherein a bottom surface of the first seal ring is disposed in the second semiconductor chip, and wherein a distance between a top surface of the first seal ring and the second semiconductor chip is less than a distance between a top surface of the first substrate and the second semiconductor chip; and
a second seal ring structure extending through the plurality of first dielectric layers, wherein the second seal ring structure is spaced apart from and electrically isolated from the first seal ring structure.

US Pat. No. 10,510,790

HIGH-K DIELECTRIC LINERS IN SHALLOW TRENCH ISOLATIONS

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, the method comprising:forming an opening extending from a top surface of a semiconductor substrate into the semiconductor substrate, the opening being entirely within a p-well of the semiconductor substrate;
depositing a metal oxide layer on sidewalls and a bottom of the opening, the metal oxide layer directly contacting the p-well;
after depositing the metal oxide layer, annealing the metal oxide layer;
after annealing the metal oxide layer, depositing a dielectric material over the metal oxide layer in the opening;
performing a planarization to remove excess portions of the dielectric material; and
forming a photo image sensor completely within the p-well of the semiconductor substrate, wherein the photo image sensor is configured to receive light, and convert the light to an electrical signal, wherein a sidewall of the metal oxide layer extends continuously from a top surface of the semiconductor substrate to a top surface of the dielectric material above the top surface of the semiconductor substrate.

US Pat. No. 10,510,788

SEMICONDUCTOR IMAGE SENSOR

TAIWAN SEMICONDUCTOR MANU...

9. A back side illumination (BSI) image sensor comprising:a substrate;
a pixel sensor; and
a hybrid isolation surrounding the pixel sensor in the substrate, and the hybrid isolation comprising:
a conductive structure;
a dielectric layer covering at least sidewalls of the conductive structure; and
a first insulating structure disposed in the substrate,
wherein the dielectric layer covers sidewalls and a bottom surface of the first insulating structure.

US Pat. No. 10,510,787

STRUCTURES AND METHODS OF CREATING CLEAR PIXELS

SEMICONDUCTOR COMPONENTS ...

1. A pixel array comprising:an array of photodiodes;
a first dielectric layer;
a second dielectric layer; and
a color filter layer that overlaps the array of photodiodes, the color filter layer comprising:
a grid of color filter container material that forms an array of openings over the photodiodes in the array of photodiodes, wherein the grid of color filter container material has a refractive index, wherein the grid of color filter container material extends from the first dielectric layer to the second dielectric layer, and wherein the first dielectric layer is formed from the color filter container material;
organic color filter material in a first set of the openings, wherein the organic color filter layer extends from the first dielectric layer to the second dielectric layer; and
transparent dielectric material in a second set of the openings, the transparent dielectric material forming clear color filter elements, wherein the clear color filter elements extend from the first dielectric layer to the second dielectric layer and wherein the transparent dielectric material has a refractive index that is greater than the refractive index of the color filter container material.

US Pat. No. 10,510,786

APPARATUS AND METHOD FOR IMPROVED PRECISION OF PHASE DIFFERENCE DETECTION

Sony Corporation, Tokyo ...

1. A solid-state imaging device, comprising:a pixel array unit comprising a plurality of imaging pixels for generation of a captured image and a plurality of phase difference detection pixels for phase difference detection,
wherein each of a first imaging pixel of the plurality of imaging pixels and a first phase difference detection pixel of the plurality of phase difference detection pixels comprise an on-chip lens, a first photoelectric conversion unit, and a charge accumulation unit; and
a driving control unit configured to drive the plurality of imaging pixels and the plurality of phase difference detection pixels,
wherein the charge accumulation unit of the first imaging pixel is shielded from light,
wherein at least one of a part of the first photoelectric conversion unit or a part of the charge accumulation unit of the first phase difference detection pixel is unshielded from the light,
wherein the first phase difference detection pixel shares a constituent element with another pixel of the pixel array unit,
wherein the constituent element includes at least one of a floating diffusion region, a reset transistor, an amplifier transistor, or a selection transistor,
wherein the charge accumulation unit is configured to retain charge from the first photoelectric conversion unit,
wherein the first phase difference detection pixel includes a transfer electrode,
wherein the transfer electrode is configured to transfer charge from the first photoelectric conversion unit to the charge accumulation unit,
wherein the transfer electrode is above the charge accumulation unit, and
wherein the transfer electrode comprise a transparent conductive film.

US Pat. No. 10,510,785

METHOD FOR MANUFACTURING TFT SUBSTRATE AND METHOD FOR MANUFACTURING TFT DISPLAY APPARATUS

WUHAN CHINA STAR OPTOELEC...

1. A method for manufacturing a thin film transistor (TFT) substrate, comprising:a step S10 of providing a base substrate;
a step S20 of forming a source/drain metal layer on the base substrate;
a step S30 of depositing a photoresist layer on the source/drain metal layer and patterning the photoresist layer to form a desired pattern of the photoresist layer;
a step S40 of using an etching gas to etch the source/drain metal layer, wherein all etched areas in the source/drain metal layer are etched at a same etching rate; and
a step S50 of stripping the photoresist layer;
wherein the step S40 of using the etching gas to etch the source/drain metal layer includes:
a step S401 of using a BCl3 gas to remove metal oxides generated due to contact of the source/drain metal layer with air; and
a step S402 of using a mixing gas including a Cl2 gas and the BCl3 gas to etch the source/drain metal layer.

US Pat. No. 10,510,784

ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A method of manufacturing an array substrate, the method comprising steps of:forming a first electrode layer, a metal gate layer and a first layer of non-oxide insulation material, the first layer of non-oxide insulation material being formed on an upper surface of the metal gate layer; and
forming, by using a first patterning process, patterns including a common electrode and triple layers of a first sub-electrode and a gate and a first non-oxide insulation layer, wherein,
the common electrode and the first sub-electrode are formed from the first electrode layer and the gate is formed from the metal gate layer, the first non-oxide insulation layer is formed from the first layer of non-oxide insulation material; and
the gate is formed between the first sub-electrode and the first non-oxide insulation layer, a material for the metal gate layer includes copper or copper alloy; and
the common electrode is a single layer, and a surface of the common electrode is free of the metal gate layer and the first layer of non-oxide insulation material after completion of the first patterning process.

US Pat. No. 10,510,783

TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A TFT array substrate having a bottom gate structure, comprising:a bearing substrate,
a gate line and a data line arranged across each other on the bearing substrate,
a pixel region defined by the gate line and the data line, and
a thin film transistor, a pixel electrode and an active layer disposed in the pixel region, a gate of the thin film transistor being connected to the gate line, a source thereof being connected to the data line and a drain thereof being connected to the pixel electrode, wherein
an insulating layer is also formed above the source of the thin film transistor, and a drain trench is formed in said insulating layer,
the drain of the thin film transistor is in said drain trench and is connected to the source through the active layer, and
wherein common electrode wires are further provided on the TFT array substrate, the insulating layer also forms a common electrode insulating layer above the common electrode wires, and common electrode via holes are formed in said common electrode insulating layer, which are filled with a drain material.

US Pat. No. 10,510,782

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A manufacturing method for an array substrate, comprising:forming a first signal line and a second signal line which have a same extension direction and are separated from each other on a base substrate;
forming an initial pixel electrode on the base substrate, wherein the initial pixel electrode includes a first extension portion, the initial pixel electrode is connected to the first signal line by the first extension portion, and the initial pixel electrode is separated from the second signal line; and
removing at least part of the first extension portion of the initial pixel electrode to form a pixel electrode separated from the first signal line,
wherein
the method further comprises: forming a common electrode on the base substrate after forming the first signal line, the second signal line and the initial pixel electrode;
the forming the common electrode on the base substrate includes: forming a common electrode film on the base substrate; and performing a patterning treatment on the common electrode film to form the common electrode; and
in the patterning treatment, the at least part of the first extension portion of the initial pixel electrode is removed.

US Pat. No. 10,510,781

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A method of producing a semiconductor device which includes a substrate, a plurality of first thin film transistors supported on the substrate, an interlevel dielectric layer covering the plurality of first thin film transistors, and a plurality of terminal portions electrically connecting the plurality of first thin film transistors to corresponding external wiring lines, each of the plurality of terminal portions including an upper conductive portion provided on the interlevel dielectric layer, the semiconductor device including an active region in which the plurality of first thin film transistors are provided, and a peripheral region being located around the active region and including the plurality of terminal portions provided therein, the method comprising:step (A) of forming gate electrodes of the plurality of first thin film transistors on the substrate;
step (B) of forming a gate dielectric layer covering the gate electrodes;
step (C) of forming an oxide semiconductor layer of the plurality of thin film transistors on the gate dielectric layer;
step (D) of forming source electrodes and drain electrodes of the plurality of thin film transistors;
step (E) of forming the interlevel dielectric layer to cover the plurality of thin film transistors;
step (F) of forming an aperture in the interlevel dielectric layer, the aperture being located between the active region and the plurality of terminal portions and extending through the interlevel dielectric layer; and
step (G) of, after the step (F), forming the upper conductive portion on the interlevel dielectric layer, wherein,
in the step (C), above a region of the gate dielectric layer that is located between the active region and the plurality of terminal portions, a protection layer is formed from a same oxide semiconductor film as the oxide semiconductor layer,
in the step (F), the aperture is formed so as to overlap the protection layer,
the aperture does not extend through the gate dielectric layer, and
in the step (C), the protection layer and the oxide semiconductor layer are formed simultaneously.

US Pat. No. 10,510,777

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a gate electrode;
a gate insulating layer over the gate electrode;
an oxide semiconductor layer over the gate insulating layer;
a metal oxide layer over the oxide semiconductor layer;
a first insulating layer over the metal oxide layer;
a source electrode over the first insulating layer;
a drain electrode over the first insulating layer; and
a second insulating layer over the source electrode and the drain electrode,
wherein the gate insulating layer contains silicon and oxygen,
wherein the second insulating layer contains silicon and oxygen,
wherein the source electrode is in contact with the oxide semiconductor layer through a first opening of the metal oxide layer and the first insulating layer,
wherein the drain electrode is in contact with the oxide semiconductor layer through a second opening of the metal oxide layer and the first insulating layer, and
wherein the metal oxide layer contains at least one of metal elements selected from constituent elements of the oxide semiconductor layer.

US Pat. No. 10,510,776

SEMICONDUCTOR DEVICE WITH COMMON ACTIVE AREA AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate;
a pair of transistor devices over the substrate, wherein each of the pair of the transistor devices comprises a channel, a gate electrode over the channel, and a source/drain region alongside the gate electrode;
an isolation region between the source/drain regions of the pair of the transistor devices, wherein the isolation region has a first doping type opposite to a second doping type of the source/drain regions; and
a pair of second isolation regions on two opposing sides of the isolation region, wherein the pair of the second isolation regions has the first doping type, and a doping concentration of the pair of the second isolation regions is lower than that of the isolation region.

US Pat. No. 10,510,774

INTEGRATED CIRCUIT POWER DISTRIBUTION NETWORK

IMEC vzw, Leuven (BE)

1. An integrated circuit device comprising:a semiconductor substrate;
a plurality of standard cells, each standard cell comprising:
a plurality of integrated transistors and interconnecting structures for locally interconnecting the transistors so as to provide a predetermined function of the standard cell, wherein each of the integrated transistors comprises at least one gate structure and wherein each gate structure is oriented in a first direction parallel to the substrate; and
at least one internal power pin for supplying a reference voltage to contacts of the integrated transistors in accordance with the predetermined function of the standard cell,
wherein a spatial dimension of each standard cell measured in a second direction orthogonal to the first direction and parallel to the substrate defines a standard cell width;
a stack of layers comprising a plurality of metal layers in which conductive metal lines are formed to route signals between the standard cells, the metal lines in each metal layer having a preferred orientation, wherein each metal layer has a preferred orientation that is orthogonal to the preferred orientation of the metal lines in an adjacent metal layer of the plurality of metal layers,
wherein a first vertical metal layer of the plurality of metal layers is the lowest metal layer in the stack that has the first direction as preferred orientation and that provides routing resources for signal routing between the standard cells, and wherein a second horizontal metal layer of the plurality of metal layers is the nearest metal layer above the first vertical metal layer in the stack,
wherein the semiconductor substrate forms a bottom level of the stack; and
a power distribution network for delivering the reference voltage to the at least one internal power pin, wherein for any conductive path in the power distribution network that electrically connects a further metal layer above the second horizontal metal layer to the at least one internal power pin, any portion of the conductive path that is contained within the second horizontal metal layer covers less than the width of the standard cell in the second direction, such that the power distribution network does not include any conductive path within the second horizontal metal layer spanning across more than any two adjacent standard cells in the second direction.

US Pat. No. 10,510,773

APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD

Micron Technology, Inc., ...

1. A memory device, comprising:a first vertical string of memory cells, wherein each memory cell of the first vertical string is formed at an intersection between a respective access line and a first vertical structure of ferroelectric material that is common to the first vertical string.

US Pat. No. 10,510,772

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A method of manufacturing a semiconductor device, the method comprising:alternately stacking first material layers and second material layers;
forming a hole passing through the first material layers and the second material layers;
forming cell blocking insulating layers arranged on side walls of the second material layers and dummy blocking insulating layers arranged on side walls of the first material layers, the dummy blocking insulating layers having side walls protruding further toward the hole than the cell blocking insulating layers; and
forming a data storage layer along the side walls of the cell blocking insulating layers and the dummy blocking insulating layers,
wherein forming the cell blocking insulating layers and the dummy blocking insulating layers comprises:
forming third material layers having side walls protruding further toward the hole than the side walls of the second material layers on the side walls of the first material layers; and
oxidizing the third material layers and portions of the side walls of the second material layers.

US Pat. No. 10,510,771

THREE-DIMENSIONAL MEMORY DEVICES HAVING PLURALITY OF VERTICAL CHANNEL STRUCTURES

Samsung Electronics Co., ...

1. A three-dimensional (3D) memory device, comprising:a first memory block including a plurality of first vertical channel structures, each first vertical channel structure of the plurality of first vertical channel structures extending in a vertical direction that is substantially perpendicular with respect to a surface of a substrate;
a second memory block including a plurality of second vertical channel structures, a first string selection line, and a second string selection line, each second vertical channel structure of the plurality of second vertical channel structures offset above the plurality of first vertical channel structures in the vertical direction, the first string selection line and the second string selection line extending in a first horizontal direction and being offset from each other in the vertical direction, the first horizontal direction being substantially parallel with respect to the surface of the substrate; and
a bit line extending in the first horizontal direction between the first memory block and the second memory block and configured to be shared by the first and second memory blocks,
wherein the second memory block further includes a first string selection transistor and a second string selection transistor, the first string selection transistor and the second string selection transistor each connected to the bit line and the first string selection line, the first string selection transistor and the second string selection transistor having different threshold voltages from each other.

US Pat. No. 10,510,770

THREE-DIMENSIONAL MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a base body portion including a first layer and a second layer, the first layer being provided on a substrate with at least a first insulating film interposed, the first layer including a first portion and a second portion arranged along a first direction, the first portion being of a semiconductor, the second portion being of a semiconductor, the second layer including a first region and a second region, the first region being positioned on the first portion, the second region being positioned on the second portion, a portion of a source being formed of the first region;
a stacked body provided above the base body portion, the stacked body alternately including a conductive layer and an insulating layer;
a first pedestal portion provided inside at least the second layer, the first pedestal portion including a portion extending in the first direction in the second region of the second layer;
a plate portion including at least a first insulator, being provided from an upper end of the stacked body to the second layer, extending in the first direction, and contacting the first region of the second layer and the portion of the first pedestal portion extending in the first direction;
a plurality of first columnar portions, the plurality of first columnar portions each including a semiconductor layer and a memory film, being provided from the upper end of the stacked body to the second layer, and being adjacent to the plate portion in a second direction with the stacked body interposed, the second direction crossing the first direction, the semiconductor layer contacting the first region of the second layer, the memory film including a charge trapping portion between the semiconductor layer and the conductive layer; and
a plurality of second columnar portions including at least a second insulator, being provided from the upper end of the stacked body to the second layer, being adjacent to the plate portion in the second direction with the stacked body interposed, and being adjacent to the first pedestal portion in the second direction with the second region of the second layer interposed.

US Pat. No. 10,510,769

THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME

Micron Technology, Inc., ...

1. A method comprising:forming conductive regions over a substrate;
forming conductive materials and dielectric materials over the conductive regions, the conductive materials being electrically isolated from each other by the dielectric materials;
forming holes through the conductive materials and dielectric materials to create initial cavities in each of the conductive materials;
enlarging a size of each of the initial cavities to form enlarged cavities;
forming memory elements in the enlarged cavities, each of the memory elements formed in a respective enlarged cavity of the enlarged cavities; and
forming conductive paths through the memory elements, each of the conductive paths formed to electrically couple to a respective conductive region of the conductive regions.

US Pat. No. 10,510,767

INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A method for manufacturing an integrated circuit (IC), the method comprising:forming a charge trapping layer on a semiconductor substrate;
forming a sacrificial gate layer covering the charge trapping layer;
patterning the sacrificial gate layer to form a sacrificial control gate overlying the charge trapping layer, and to further form a sacrificial select gate neighboring the charge trapping layer and the sacrificial control gate;
forming a common source/drain in the semiconductor substrate, between the sacrificial control and select gates, wherein the common source/drain has a first doping type; and
replacing the sacrificial control gate with a control gate electrode, wherein the replacing of the sacrificial control gate is performed independent of the sacrificial select gate, wherein the control gate electrode comprises a first metal, wherein a work function of the first metal is within about 0.4 electron volts of a work function of doped polysilicon having a second doping type, and wherein the second doping type is opposite the first doping type.

US Pat. No. 10,510,766

FLASH MEMORY STRUCTURE WITH REDUCED DIMENSION OF GATE STRUCTURE AND METHODS OF FORMING THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device structure, the method comprising:forming a first gate electrode layer on a substrate;
forming a first charge trapping dielectric on the first gate electrode layer;
forming a patterned hardmask layer over the first charge trapping dielectric;
etching the first charge trapping dielectric exposed by the patterned hardmask layer to form a patterned first charge trapping dielectric, wherein etching the first charge trapping dielectric forms a recess extending partially through the first gate electrode layer;
forming a dielectric layer on the substrate covering the patterned first charge trapping dielectric and sidewalls of the recess in the first gate electrode layer, wherein a portion of the first gate electrode layer at a bottom of the recess is exposed; and
forming a select gate structure by etching through the portion of the first gate electrode layer at the bottom of the recess using the dielectric layer as sidewall protection for an upper sidewall portion of the first gate electrode layer.

US Pat. No. 10,510,764

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a stacked body including a plurality of conductive layers and a plurality of insulating layers, the conductive layers and the insulating layers being stacked alternately along a first direction, the conductive layers including a first conductive layer and a second conductive layer disposed above the first conductive layer;
a first insulating body extending in a second direction and being provided inside the stacked body along the first direction and dividing the first conductive layer and the second conductive layer, the second direction crossing the first direction;
a second insulating body extending in the second direction and being provided inside the stacked body along the first direction and dividing the first conductive layer and the second conductive layer, the second insulating body being at a position different from the first insulating body in a third direction, the third direction crossing the first direction and the second direction;
a third insulating body provided inside the stacked body along the first direction and dividing the first conductive layer and the second conductive layer, the third insulating body being between the first insulating body and the second insulating body;
a fourth insulating body provided inside the stacked body along the first direction, dividing the second conductive layer, and not dividing the first conductive layer, the fourth insulating body being between the first insulating body and the second insulating body, the fourth insulating body including a plurality of portions extending in the second direction, the plurality of portions contacting the third insulating body and being separated from each other in the second direction with the third insulating body interposed;
a first columnar portion provided inside the stacked body along the first direction and penetrating the first conductive layer and the second conductive layer, the first columnar portion being between the first insulating body and the fourth insulating body and including a semiconductor layer; and
a second columnar portion provided inside the stacked body along the first direction and penetrating the first conductive layer and the second conductive layer, the second columnar portion being between the second insulating body and the fourth insulating body and including a semiconductor layer.

US Pat. No. 10,510,759

SEMICONDUCTOR MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor memory device comprising:a plurality of lower electrodes located on a substrate and spaced apart from one another;
a first etch stop pattern located on the substrate and surrounding a lower portion of a sidewall of each of the plurality of lower electrodes; and
a second etch stop pattern located on the first etch stop pattern,
wherein a horizontal cross-sectional area of the second etch stop pattern decreases and then increases as the horizontal cross-sectional area of the second etch stop pattern goes away from the substrate in a vertical direction.

US Pat. No. 10,510,758

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A manufacturing method of a semiconductor memory device, comprising:forming a gate structure on a semiconductor substrate, wherein the gate structure comprises:
a floating gate electrode;
a control gate electrode disposed on the floating gate electrode;
a first oxide layer disposed between the floating gate electrode and the semiconductor substrate; and
a second oxide layer disposed between the floating gate electrode and the control gate electrode;
forming an oxide spacer layer conformally on the gate structure and the semiconductor substrate;
forming a nitride spacer on the oxide spacer layer and on a sidewall of the gate structure; and
performing an oxidation process after the step of forming the nitride spacer, wherein a thickness of an edge portion of the first oxide layer is increased by the oxidation process, and a thickness of an edge portion of the second oxide layer before the oxidation process is equal to the thickness of the edge portion of the second oxide layer after the oxidation process, wherein the oxide spacer layer directly contacts a topmost surface of the control gate electrode during the oxidation process.

US Pat. No. 10,510,756

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:forming a fin extending from a substrate;
forming an interface layer on the fin;
depositing a gate dielectric layer on the interface layer, the gate dielectric layer having a first surface facing towards the interface layer and a second surface facing away from the interface layer;
doping the gate dielectric layer with a dipole-inducing element, the gate dielectric layer having a first concentration of the dipole-inducing element at the second surface after the doping;
depositing a sacrificial layer on the gate dielectric layer;
removing the sacrificial layer, the gate dielectric layer having a second concentration of the dipole-inducing element at the second surface after the removing, the second concentration being less than the first concentration;
depositing a capping layer on the gate dielectric layer; and
forming a gate electrode layer on the capping layer.

US Pat. No. 10,510,755

SEMICONDUCTOR DEVICE AND MANUFACTURE METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first gate stack comprising:
a first work function conductor; and
a first filling conductor comprising a plug portion and a cap portion; and
a first gate spacer disposed on a first side of the first gate stack, wherein:
the cap portion overlies an uppermost surface of the first work function conductor, and
a sidewall of the plug portion is spaced apart from a sidewall of the first gate spacer by the first work function conductor.

US Pat. No. 10,510,753

INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit comprising:first and second semiconductor fins;
first and second epitaxy structures respectively on the first and second semiconductor fins, wherein the first epitaxy structure and the second epitaxy structure are merged together; and
first and second dielectric fin sidewall structures respectively on opposite first and second sidewalls of the first epitaxy structure, wherein the first sidewall of the first epitaxy structure faces the second epitaxy structure, and the first dielectric fin sidewall structure is shorter than the second dielectric fin sidewall structure.

US Pat. No. 10,510,751

FINFET ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate;
an insulating layer formed over the substrate;
a plurality of fins formed vertically from a surface of the substrate, the plurality of fins extending through the insulating layer and above a top surface of the insulating layer;
a gate structure formed over a portion of fins and over the top surface of the insulating layer;
a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting a portion of the fin;
a dielectric layer formed over the insulating layer;
a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material; and
a second contact trench extending a second depth into the dielectric layer, wherein:
the second contact trench contains the electrical conductive material;
the second contact trench is spaced away from the gate structure such that electrical conductive material in the second contact trench is free from contact with the gate structure;
the second depth is greater than the first depth; and
an air gap extends from a bottommost surface of the electrical conductive material to a bottommost surface of the second contact trench defined by the dielectric layer, wherein an entirety of the air gap is disposed within the dielectric layer.

US Pat. No. 10,510,748

TRANSISTOR FOR INCREASING A RANGE OF A SWING OF A SIGNAL

RichWave Technology Corp....

1. A transistor for increasing a range of a swing of a signal, comprising:a first doping well formed in a structure layer;
a second doping well formed in the structure layer, and the second doping well formed between the first doping well and the structure layer;
a first doping area formed in the first doping well for transmitting the signal;
a second doping area formed in the first doping well, wherein the first doping area, the second doping area, and the second doping well have a first conductivity type, and the first doping well has a second conductivity type;
a gate area for making a channel be formed between the first doping area and the second doping area; and
at least one compensation capacitor formed outside the first doping area, the second doping area, the first doping well, the second doping well and the structure layer, and electrically connected between the first doping well and the second doping well or between the second doping well and a first reference potential;
wherein a first parasitic junction capacitor exists between the first doping area and the first doping well, a second parasitic junction capacitor exists between the first doping well and the second doping well, a third parasitic junction capacitor exists between the second doping well and the structure layer; and the at least one compensation capacitor is used for adjusting a voltage drop of the second parasitic junction capacitor or a voltage drop of the third parasitic junction capacitor.

US Pat. No. 10,510,744

VERTICAL NANOWIRE TRANSISTOR FOR INPUT/OUTPUT STRUCTURE

Taiwan Semiconductor Manu...

1. A method comprising:receiving an input signal to an input terminal; and
attenuating an electrostatic discharge (ESD) voltage in the input signal by a drift region of a transistor that has a resistance in series between a first source region and a first drain region of the transistor, wherein the resistance is generated by a first nanowire channel between the first source region and the first drain region, and the first nanowire channel has a lengthwise direction perpendicular to a major top surface of a device die that comprises the transistor therein.

US Pat. No. 10,510,743

STEP FIN FIELD-EFFECT-TRANSISTOR (FINFET) WITH SLIM TOP OF FIN AND THICK BOTTOM OF FIN FOR ELECTRO-STATIC-DISCHARGE (ESD) OR ELECTRICAL OVER-STRESS (EOS) PROTECTION

Hong Kong Applied Science...

1. A Fin Field-Effect Transistor (FinFET) Electro-Static-Discharge (ESD) protection device comprising:a substrate having a substantially planar surface;
a fin formed on the substrate, the fin being of a semiconductor material and having a cross-sectional shape;
a gate formed around a top portion of the fin, the gate covering a top surface of the fin and wrapping around the top portion of two sidewalls of the fin;
a conducting region in the top portion of the fin, the conducting region being covered by the gate;
a gate oxide formed between the gate and the conducting region, the gate oxide being formed over the conducting region on the top portion of the fin including the top surface and the top portion of the two sidewalls, wherein the gate is non-planar;
a source region in the top portion of the fin, and adjacent to the conducting region, the source region having a first concentration of a first dopant;
a drain region in the top portion of the fin, and adjacent to the conducting region, the drain region having the first concentration of the first dopant;
wherein the conducting region has a second dopant having an opposite polarity type as the first dopant;
wherein a current conduction between the drain region and the source region through the conducting region has a first effective resistance;
a buried conducting region in a bottom portion of the fin, the buried conducting region being underneath the conducting region;
a buried source region in the bottom portion of the fin, and adjacent to the buried conducting region, the buried source region having a second concentration of the first dopant;
a buried drain region in the bottom portion of the fin, and adjacent to the buried conducting region, the buried drain region having the second concentration of the first dopant;
wherein a current conduction between the buried drain region and the buried source region through the buried conducting region has a second effective resistance;
wherein a normal current conduction between the source region and the drain region through the conducting region is controlled by a gate voltage applied to the gate during normal operation;
wherein during normal operation the gate voltage and a voltage between the source region and the drain region are less than a breakdown voltage;
wherein current conduction between the buried drain region and the buried source region through the buried conducting region does not occur during normal operation when applied voltages are less than the breakdown voltage;
wherein the first effective resistance is at least double the second effective resistance when the voltage between the source region and the drain region is more than the breakdown voltage,
wherein a breakdown current through the buried conducting region is at least double the breakdown current through the conducting region during an ESD event.

US Pat. No. 10,510,738

THREE-DIMENSIONAL MEMORY DEVICE HAVING SUPPORT-DIE-ASSISTED SOURCE POWER DISTRIBUTION AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:a memory-containing die comprising a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads included in the memory dielectric material layer and electrically connected to a respective node within the three-dimensional memory array; and
a logic die comprising a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers and electrically connected to a respective node of the peripheral circuitry and bonded to a respective one, or a respective subset, of the memory-side bonding pads, wherein the logic-side bonding pads comprise:
a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and including an array of discrete openings therethrough; and
discrete logic-side bonding pads electrically isolated one from another and from the pad-level mesh structure.

US Pat. No. 10,510,737

SEMICONDUCTOR PACKAGE

Samsung Electronics Co., ...

1. A semiconductor package comprising:a substrate;
a semiconductor memory chip on the substrate;
a second semiconductor chip on the substrate and spaced laterally apart from the semiconductor memory chip;
a mold layer on the substrate and covering sides of the semiconductor memory chip and the second semiconductor chip; and
an image sensor unit on the semiconductor memory chip, the second semiconductor chip and the mold layer, the image sensor unit comprising:
a third semiconductor chip having integrated circuitry constituting a logic circuit electrically connected to the semiconductor memory chip, and
a fourth semiconductor chip stacked on the third semiconductor chip and comprising photodiodes that convert light into electric charges,
wherein the fourth semiconductor chip is electrically connected to the third semiconductor chip and the integrated circuit of the third semiconductor chip is configured to convert the electric charges generated by the photodiodes of the fourth semiconductor chip into an electrical signal, and
wherein the semiconductor package further comprises a connection pad on an upper surface of the image sensor unit, and a bonding wire electrically connecting the connection pad to a terminal of the substrate.

US Pat. No. 10,510,735

PACKAGES AND METHODS OF FORMING PACKAGES

Taiwan Semiconductor Manu...

1. A structure comprising:a first die embedded in an encapsulant, a first pad being on an active side of the first die, a first die connector being on the first pad, the first pad having a first width and the first die connector having a second width, the first and second widths being measured in a first direction, the first direction being parallel to the active side of the first die;
a second die embedded in the encapsulant, a second pad being on an active side of the second die, a second die connector contacting the second pad, the second pad having a third width and the second die connector having a fourth width, the third and fourth widths being measured in the first direction, the fourth width being less than the third width; and
a redistribution structure over the encapsulant, the first die, and the second die, the first die being electrically coupled to the second die through the first die connector, the redistribution structure, and the second die connector.

US Pat. No. 10,510,732

POP DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A package-on-package (PoP) device, comprising:a first package structure, comprising:
a die;
a through integrated fan-out via (TIV) aside the die;
an encapsulant encapsulating sidewalls of the die and sidewalls of the TIV; and
a film over the TIV and the encapsulant, and aside the die; and
a second package structure, connected to the first package structure through a connector,
wherein the connector penetrates through the film to electrically connect to the TIV,
wherein the film is surrounded by the encapsulant, and a top surface of the film is coplanar with a top surface of the encapsulant.

US Pat. No. 10,510,731

PACKAGE-ON-PACKAGE (POP) STRUCTURE INCLUDING STUD BULBS

Taiwan Semiconductor Manu...

1. A device comprising:a first pad on a first surface of a first package;
a second pad on a second surface of a second package;
a metallic element interposed between the first pad and the second pad, the metallic element comprising a base portion and an elongated portion, the base portion being coupled to the first pad, the elongated portion extending from the base portion toward the second pad, wherein a width of the base portion is greater than a width of the elongated portion;
a solder connector in contact with the elongated portion and electrically coupled to the second pad; and
an inter-metallic compound (IMC) between the elongated portion and the solder connector.

US Pat. No. 10,510,728

MAGNETIC COUPLING PACKAGE STRUCTURE FOR MAGNETICALLY COUPLED ISOLATOR WITH DUO LEADFRAMES AND METHOD FOR MANUFACTURING THE SAME

LITE-ON SINGAPORE PTE. LT...

1. A method for manufacturing a magnetic coupling package structure with duo leadframes for a magnetically coupled isolator, comprising:a leadframe providing step including providing a first leadframe and a second leadframe, wherein the first leadframe includes a first chip-mounting portion, at least a first coil portion, a plurality of first pins and a plurality of floated pins, and the second leadframe includes a second chip-mounting portion, at least a second coil portion, a plurality of second pins and a plurality of second floated pins;
a chip connecting step including respectively disposing at least a first chip and at least a second chip on the first chip-mounting portion and the second chip-mounting portion and establishing electrical connections between the first chip and the first pins and between the second chip and the second pins; and
a coil aligning step including disposing the first leadframe at a position above or under the second leadframe and respectively applying a first magnetic field and a second magnetic field to the first leadframe and the second leadframe for aligning the first coil portion and the second coil portion;
wherein the first chip and the first coil portion together form a first closed circuit through a first connecting wire, and the at least one second chip and the at least one second coil portion together form a second closed circuit through a second connecting wire.

US Pat. No. 10,510,725

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device, the device comprising:a base member having a first surface and a second surface, the second surface being on a side opposite to the first surface, the base member including at least one interconnect extending in a first direction along the first surface;
two or more stacked bodies arranged in the first direction on the first surface, each of the two or more stacked bodies including a plurality of semiconductor chips stacked in a second direction perpendicular to the first surface;
two or more logic chips electrically connected respectively to the stacked bodies; and
a resin member over the first surface of the base member, the resin member sealing the two or more stacked bodies and the two or more logic chips on the base member, the resin member physically contacting the first surface of the base member,
each of the plurality of semiconductor chips including a first semiconductor layer and a second semiconductor layer,
the first semiconductor layer and the second semiconductor layer each having an element surface and a back surface, an active element being provided on the element surface, the back surface being on a side opposite to the element surface, and the first semiconductor layer and the second semiconductor layer being bonded such that the element surface of the second semiconductor layer faces the element surface of the first semiconductor layer.

US Pat. No. 10,510,724

SEMICONDUCTOR DEVICE PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device package comprising:a buffer layer having an upper surface perpendicular to a first direction;
a plurality of semiconductor chips stacked on the buffer layer one by one in the first direction; and
a chip sealing material sealing sidewalls of the plurality of semiconductor chips,
wherein the plurality of semiconductor chips comprise an upper semiconductor chip at a farthest position from the buffer layer and a remaining plurality of intermediate semiconductor chips,
each of the plurality of intermediate semiconductor chips comprises through silicon vias (TSVs) passing through each of the plurality of intermediate semiconductor chips,
the upper semiconductor chip comprises a trench formed in at least a portion of a periphery of the upper semiconductor chip and covered by the chip sealing material,
a depth of the trench varies as a function of position, and
a position at which the trench has a maximum depth is radially closer to a center of the upper semiconductor chip than a position at which the trench has a minimum depth when a depth of the trench is measured in the first direction.

US Pat. No. 10,510,723

BUFFER LAYER(S) ON A STACKED STRUCTURE HAVING A VIA

Taiwan Semiconductor Manu...

1. A structure comprising:a first substrate comprising a first semiconductor substrate and a first interconnect structure on the first semiconductor substrate;
a second substrate comprising a second semiconductor substrate and a second interconnect structure on a first side of the second semiconductor substrate, the first substrate being bonded to the second substrate at a bonding interface, the first interconnect structure and the second interconnect structure being disposed between the first semiconductor substrate and the second semiconductor substrate;
a via extending at least through the second semiconductor substrate into the second interconnect structure;
a first stress buffer layer on a second side of the second semiconductor substrate, the second side of the second semiconductor substrate being opposite from the first side of the second semiconductor substrate;
a post-passivation interconnect (PPI) structure on the first stress buffer layer and electrically coupled to the via;
a second stress buffer layer on the PPI structure and the first stress buffer layer, wherein a first portion of the second stress buffer layer and a second portion of the second stress buffer layer extend through a first region of the PPI structure to contact the first stress buffer layer, wherein the first portion and the second portion of the second stress buffer layer are separated and surrounded by the first region of the PPI structure, wherein the first region of the PPI structure is a continuous layer of electrically conductive material, wherein the second stress buffer layer contacts a sidewall and a top surface of the first region of the PPI structure;
an under-bump structure on the first region of the PPI structure, the second stress buffer layer having a continuous material composition from the first stress buffer layer to the under-bump structure; and
a bump contact on the under-bump structure.

US Pat. No. 10,510,722

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first electronic component having a first surface;
a second electronic component over the first electronic component, the second electronic component having a second surface facing the first surface of the first electronic component;
a plurality of interconnection structures between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures,
wherein the first electronic component comprises a plurality of electrical terminals, and each of the interconnection structures is electrically connected to two or more of the plurality of electrical terminals of the first electronic component, and wherein the plurality of interconnection structures comprises a first set of interconnection structures and a second set of interconnection structures, the interconnection structures of the first set are electrically connected, the interconnection structures of the second set are electrically connected, and the interconnection structures of the first set and the second set are arranged alternately in the second direction and electrically disconnected from one another; and
a plurality of capacitors each comprising a first electrode and a second electrodes overlapping to each other, wherein the first electrodes of the capacitors are electrically connected to the second electronic component through the first set of the interconnection structures, and the second electrodes of the capacitors are electrically connected to the second electronic component through the second set of the interconnection structures.

US Pat. No. 10,510,719

METHODS OF PACKAGING SEMICONDUCTOR DEVICES AND PACKAGED SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A packaged semiconductor device comprising:an integrated circuit die, the integrated circuit die having a plurality of contact pads disposed thereon,
a dam structure disposed on a periphery of the integrated circuit die; a molding material disposed along sidewalls of the integrated circuit die and along sidewalls of the dam structure, wherein the molding material extends over an upper surface of the integrated circuit die: and
an interconnect structure disposed over the integrated circuit die and the molding material, the interconnect structure comprising a first dielectric layer, the first dielectric layer being interposed between the dam structure and the plurality of contact pads.

US Pat. No. 10,510,717

CHIP ON PACKAGE STRUCTURE AND METHOD

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:an integrated fan out package, the integrated fan out package comprising a first semiconductor device, an encapsulant surrounding the first semiconductor device, a second semiconductor device, and a via in the encapsulant, the via having a first height at least as large as a second height of the first semiconductor device; and
a third semiconductor device attached to the integrated fan out package, wherein the third semiconductor device is connected to the second semiconductor device through the first semiconductor device, the third semiconductor device being electrically connected to through substrate vias extending through a substrate of the first semiconductor device.

US Pat. No. 10,510,716

PACKAGED SEMICONDUCTOR DEVICES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

15. A device comprising:a friction-reducing mask coating;
a first molding compound over the friction-reducing mask coating;
an integrated circuit die extending into the first molding compound;
an adhesive film between the integrated circuit die and the friction-reducing mask coating;
an interconnect structure over the integrated circuit die and the first molding compound;
a second molding compound over the interconnect structure; and
a heat spreader abutting the friction-reducing mask coating, the friction-reducing mask coating being interposed between the heat spreader and the integrated circuit die.

US Pat. No. 10,510,713

SEMICONDCUTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor package, comprising:a redistribution structure;
at least one semiconductor device disposed on and electrically connected to the redistribution structure;
a heat dissipation component disposed on the redistribution structure and comprising a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion connects the at least one semiconductor device; and
an encapsulating material disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

US Pat. No. 10,510,708

ANISOTROPIC CONDUCTIVE FILM (ACF) AND FORMING METHOD THEREOF, ACF ROLL, BONDING STRUCTURE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An anisotropic conductive film (ACF), comprising:an insulating adhesive layer, including a plurality of preset regions corresponding to electrodes to be bonded and spaced from each other; and
capsule structures, dispersed in the insulating adhesive layer of the plurality of preset regions and configured to realize a electrical connection in a direction perpendicular to a surface of the ACF when the ACF is subjected to a pressure in the direction perpendicular to the surface of the ACF,
wherein a number of the capsule structures in each of the plurality of preset regions is greater than a preset number,
wherein the anisotropic conductive film is disposed on a non-display region of a display device, and the capsule structure is not disposed outside the plurality of preset regions.

US Pat. No. 10,510,705

SEMICONDUCTOR PACKAGE STRUCTURE HAVING A SECOND ENCAPSULANT EXTENDING IN A CAVITY DEFINED BY A FIRST ENCAPSULANT

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a first semiconductor die;
a second semiconductor die disposed on the first semiconductor die;
a plurality of conductive elements each comprising a first portion and a second portion, and disposed around the first semiconductor die and the second semiconductor die;
a first encapsulant surrounding the first semiconductor die and the respective first portions of the conductive elements; and
a second encapsulant covering a portion of a top portion of the first semiconductor die and surrounding the respective second portions of the conductive elements, wherein the second encapsulant directly contacts the first encapsulant, the first encapsulant defines a cavity to expose at least the portion of the top portion of the first semiconductor die, and the second encapsulant covers the first encapsulant and extends into the cavity.

US Pat. No. 10,510,704

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A package structure, comprising:a first die;
an encapsulant aside the first die, encapsulating sidewalls of the first die;
a first redistribution layer (RDL) structure on the first die and the encapsulant; and
a conductive terminal, electrically connected to first die through the RDL structure,
wherein the first RDL structure comprises a first polymer layer and a first RDL, the first polymer layer comprises a non-shrinkage material and a top surface of the first polymer layer is substantially flat,
wherein a portion of the first polymer layer is extending into the encapsulant and is surrounded by the encapsulant.

US Pat. No. 10,510,700

SEMICONDUCTOR DEVICE

Rohm Co., Ltd., Kyoto (J...

1. A semiconductor device comprising:a semiconductor chip including:
an electrode pad portion on a face of a substrate;
a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;
a barrier metal layer on the electrode pad portion;
a second protection layer covering a region on the first protection layer and a region on the electrode par portion; and
a plurality of bump electrodes on the barrier metal layer;
a circuit board on which the semiconductor chip is mounted, the circuit board having, formed on a first face thereof facing the semiconductor chip, a connection pad portion connected to the bump electrodes;
a plurality of electrode terminals formed on a second face of the circuit board facing away from the semiconductor chip, the electrode terminals being electrically connected to the connection pad portion; and
a resin member filling a gap between the semiconductor chip and the circuit board,
wherein the barrier metal layer has a circumferential end part thereof formed inward of the first opening in the first protection layer as seen in a plan view,
wherein the electrode pad portion is rectangular as seen in a plan view;
wherein
a peripheral part of the barrier metal layer lies on the second protection layer, and
an upper surface and a lower surface of the barrier metal layer have a curved shape extending along the second protection layer so that a center point of a curvature of the curved shape as seen in a sectional view is located on a substrate side of the curved shape, and
wherein
the second protection layer is formed of polyimide,
the second protection layer has a second opening through which the top face of the electrode pad portion is exposed and which has an opening width smaller than the first opening,
a thickness of the second protection layer as seen in a sectional view increases gradually from a rim part of the second opening to the peripheral part of the barrier metal layer,
wherein
the bump electrodes are arrayed on a third face of the semiconductor chip facing the circuit board,
the electrode terminals are arrayed on the second face of the circuit board, and
an interval between adjacent ones of the electrode terminals on the second face is larger than an interval between adjacent ones of the bump electrodes on the third face, and
wherein the resin member covers the third face of the semiconductor chip and a part of a side face of the semiconductor chip neighboring the third face.

US Pat. No. 10,510,698

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING

Taiwan Semiconductor Manu...

1. A package comprising:a first die;
a first passivation layer overlying the first die;
a second die adjacent the first die;
a first insulating layer overlying the first die and the second die, wherein the first passivation layer is in physical contact with the first insulating layer; and
a molding material extending along sidewalls of the first die, sidewalls of the second die and sidewalls of the first passivation layer, wherein the molding material extends between the second die and the first insulating layer.

US Pat. No. 10,510,695

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A package structure, comprising:a die on an adhesive layer;
an encapsulant, laterally encapsulating the die and laterally encapsulating the adhesive layer;
a redistribution layer (RDL) structure electrically connected to the die, wherein the RDL structure and the adhesive layer are disposed at opposite sides of the die, and the RDL structure comprises:
a first dielectric layer on the encapsulant and the die;
a first RDL embedded in the first dielectric layer and comprising a first via and a first trace connected to each other, wherein a top surface of the first RDL is coplanar with a top surface of the first dielectric layer;
a second dielectric layer on the first dielectric layer and the first RDL; and
a second RDL embedded in the second dielectric layer and comprising a second via and a second trace connected to each other, wherein a top surface of the second RDL is coplanar with a top surface of the second dielectric layer,
wherein the second via is stacked directly on the first via.

US Pat. No. 10,510,690

WAFER LEVEL PACKAGE (WLP) AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:attaching a semiconductor device structure to a substrate, the semiconductor device structure comprising a chip structure, a conductive pad over the chip structure, a passivation layer over the conductive pad and the chip structure, a first protection layer over the passivation layer, and a post-passivation interconnect (PPI) pad extending through the first protection layer and the passivation layer, the PPI pad being electrically connected to the conductive pad;
forming an insulating layer surrounding the chip structure, the passivation layer, and the first protection layer;
forming a second protection layer over the insulating layer, the first protection layer, and the PPI pad;
etching the second protection layer to form first openings exposing top surfaces of the PPI pad;
forming a PPI structure in the first openings, the PPI structure being electrically connected to the PPI pad; and
forming a first moisture-resistant layer over the second protection layer and the PPI structure, the first moisture-resistant layer comprising a different material than the first protection layer and the second protection layer.

US Pat. No. 10,510,687

PACKAGING DEVICES AND METHODS FOR SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a semiconductor device bonded to a surface of a packaging substrate, wherein the semiconductor device comprises:
an interposer;
a first die bonded to a surface of the interposer;
a second die bonded to the surface of the interposer; and
a first stress isolation structure (SIS) attached to the surface of the interposer, the first SIS being interposed between the first die and the second die;
a second SIS bonded to the surface of the packaging substrate; and
a cover coupled to the packaging substrate, wherein the cover and the packaging substrate define an enclosed space, and wherein the semiconductor device and the second SIS are disposed in the enclosed space.

US Pat. No. 10,510,686

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

16. A manufacturing method of a semiconductor package, comprising:disposing a semiconductor die on a redistribution structure with a die attach material attached therebetween, wherein an extruded region of the die attach material is adhered to a bottom portion of the semiconductor die, and in a top view, a width of the extruded region of the die attach material decreases from a midpoint of a bottom edge of the extruded region to an endpoint of the bottom edge of the extruded region; and
covering the semiconductor die and the die attach material with an insulating encapsulant.

US Pat. No. 10,510,685

DISHING PREVENTION COLUMNS FOR BIPOLAR JUNCTION TRANSISTORS

Taiwan Semiconductor Manu...

1. An integrated circuit (IC) comprising:a first IC region comprising,
an emitter region disposed within a semiconductor substrate;
a ring-shaped base region disposed within the semiconductor substrate and laterally surrounding the emitter region;
a ring-shaped collector region disposed within the semiconductor substrate and laterally surrounding the ring-shaped base region;
a pre-metal dielectric layer disposed over an upper surface of the semiconductor substrate, and separating the upper surface of the semiconductor substrate from a lowermost metal interconnect layer; and
a plurality of dishing prevention columns arranged over the emitter region and within the pre-metal dielectric layer, wherein the plurality of dishing prevention columns each comprise a dummy gate that is conductive and electrically floating; a second IC region comprising,
a semiconductor device having a pair of source/drain regions disposed within the semiconductor substrate, wherein the source/drain regions are spaced apart; and
a gate stack disposed over the semiconductor substrate and arranged between the source/drain regions, wherein the gate stack comprises a first gate oxide layer separating a gate electrode from the semiconductor substrate, and wherein a sidewall spacer is disposed on sidewalls of the gate stack and sidewalls of each of the dishing prevention columns of the plurality of dishing prevention columns.

US Pat. No. 10,510,674

FAN-OUT PACKAGE HAVING A MAIN DIE AND A DUMMY DIE, AND METHOD OF FORMING

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:placing a functional die and a first dummy die on a first substrate, wherein the first dummy die comprises a polymer layer overlying a second substrate;
encapsulating sidewalls of the functional die and the first dummy die with a molding material;
forming a redistribution structure over the functional die and the first dummy die, the redistribution structure comprising a plurality of conductive lines and a plurality of dielectric layers, wherein the functional die is electrically connected to a first conductive line of the plurality of conductive lines, and wherein the polymer layer of the first dummy die faces the redistribution structure; and
forming a plurality of external connectors on the redistribution structure.

US Pat. No. 10,510,669

MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME

Intel Corporation, Santa...

1. A multi-chip package comprising:a substrate having a first side, an opposing second side, and a third side that extends from the first side to the second side, the third side constituting a portion of an outside perimeter of the substrate;
a first die attached to the first side of the substrate and a second die attached to the first side of the substrate;
a bridge within an opening of the substrate, the bridge attached to the first die and to the second die, wherein the bridge creates a connection between the first die and the second die; and
one or more wire bonds coupling the bridge die to the substrate.

US Pat. No. 10,510,668

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A method of fabricating a semiconductor device, comprising:providing a hybrid bonded structure;
providing a cover lid comprising a base portion and at least one dummy portion protruding from the base portion;
bonding the at least one dummy portion of the cover lid to the hybrid bonding structure;
removing the base portion; and
forming a redistribution structure over the hybrid bonding structure and the at least one dummy portion.

US Pat. No. 10,510,667

CONDUCTIVE COATING FOR A MICROELECTRONICS PACKAGE

Intel Corporation, Santa...

1. A microelectronics package comprising:a first reference plane and a second reference plane;
a signal routing layer located in between the first and second reference planes, the signal routing layer including a plurality of signal routing traces;
a first dielectric layer located adjacent to the signal routing layer and the first and second reference planes; and
a conductive layer applied to a side surface of the first dielectric layer such that the conductive layer spans the side surface of the first dielectric layer and electrically couples the first and second reference planes.

US Pat. No. 10,510,666

INTERCONNECT STRUCTURE AND METHOD OF FORMING SAME

Taiwan Semiconductor Manu...

1. An apparatus comprising:a first dielectric layer formed over a substrate;
a first conductive structure embedded in the first dielectric layer, wherein a top surface of the first conductive structure and a surface of the first dielectric layer form a first inverted trapezoidal shape;
a second conductive structure embedded in the first dielectric layer, wherein a top surface of the second conductive structure and the surface of the first dielectric layer form a second inverted trapezoidal shape;
a second dielectric layer formed over the first dielectric layer; and
a third conductive structure embedded in the second dielectric layer, wherein:
the third conductive structure is in direct contact with the top surface of the first conductive structure; and
the third conductive structure is in direct contact with a sidewall of the first dielectric layer, the sidewall of the first dielectric layer extending from a lateral extent of the top surface of the first conductive structure to an uppermost surface of the first dielectric layer, and wherein a portion of the sidewall of the first dielectric layer extending from the third conductive structure to the uppermost surface of the first dielectric layer is covered by a dielectric material.

US Pat. No. 10,510,663

TRANSISTOR STRUCTURES HAVING ELECTRICALLY FLOATING METAL LAYER BETWEEN ACTIVE METAL LINES

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising active metal lines arranged side-by-side and separated from electrically floating metal layers by an insulator material, the electrically floating metal layers alternating in the single wiring plane between the active metal lines, each of the electrically floating metal layers has a width less than a width of each of the active metal lines, wherein the active metal lines are source lines and drain lines of an active device.

US Pat. No. 10,510,662

VERTICALLY ORIENTED METAL SILICIDE CONTAINING E-FUSE DEVICE AND METHODS OF MAKING SAME

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate;
forming first and second oppositely doped regions in said VOS structure, said first and second oppositely doped regions constituting a diode; and
performing a metal silicide formation process to convert at least a portion of said VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse, wherein said first and second oppositely doped regions are positioned vertically above said conductive silicide vertically oriented e-fuse and wherein said first and second oppositely doped regions are formed prior to performing said metal silicide formation process.

US Pat. No. 10,510,661

SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a conductive layer;
a first dielectric layer disposed over the conductive layer;
a magnetic layer disposed over the first dielectric layer; and
a plurality of tantalum layers and a plurality of tantalum oxide layers, alternately disposed between the magnetic layer and the first dielectric layer.

US Pat. No. 10,510,660

SEMICONDUCTOR PACKAGE DEVICES INTEGRATED WITH INDUCTOR

TAIWAN SEMICONDUCTOR MANU...

1. An inductor structure, comprising:a first carrier having a first surface;
a first conductive pattern on the first surface of the first carrier;
a second carrier at one edge of the first carrier, the second carrier having a second surface substantially perpendicular to the first surface of the first carrier; and
a second conductive pattern on the second surface of the second carrier,
wherein the second conductive pattern is electrically connected with the first conductive pattern.

US Pat. No. 10,510,659

SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT

Invensas Corporation, Sa...

1. A microelectronic package, comprising:first conductive elements, including a first trace, obtained from a same conductive layer located on a lower side of the microelectronic package;
wire bond wires connected to and extending away from upper surfaces of the first conductive elements;
a first microelectronic component coupled with a first attachment layer to the first trace;
a first conductive via in the first attachment layer and interconnecting the first trace and a first contact structure of the first microelectronic component;
a second microelectronic component coupled to the first microelectronic component with a second attachment layer;
second conductive elements, including a second trace, respectively connected to upper surfaces of the wire bond wires; and
a second conductive via in a dielectric layer and interconnecting the second trace and a second contact structure of the second microelectronic component.

US Pat. No. 10,510,658

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate;
a first insulating film on the substrate;
a lower metal layer in the first insulating film;
a second insulating film on the first insulating film, wherein the lower metal layer is in the second insulating film, the second insulating film comprises a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film is upwardly convex;
a barrier dielectric film on the second insulating film, wherein the barrier dielectric film comprises a recess; and
a via metal layer in the recess of the barrier dielectric film and electrically connected with the lower metal layer,
wherein the barrier dielectric film extends on a side of a portion of the via metal layer,
wherein the first insulating film and the second insulating film are sequentially stacked on the substrate in a vertical direction, and
wherein a longest vertical distance between an upper surface of the lower metal layer and the substrate is less than a longest vertical distance between the upper surface of the second insulating film and the substrate.

US Pat. No. 10,510,656

SEMICONDUCTOR DEVICE

PANASONIC INTELLECTUAL PR...

1. A semiconductor device comprising:a substrate;
a semiconductor layer disposed on the substrate;
a first transistor including a first gate electrode, a plurality of first drain electrodes and a plurality of first source electrodes that are disposed vertically above the semiconductor layer;
a second transistor including a second gate electrode, a plurality of second drain electrodes and a plurality of second source electrodes that are disposed vertically above the semiconductor layer;
first drain pads that are disposed vertically above the first drain electrodes, are electrically connected to the first drain electrodes, and extend in a first direction;
a plurality of first source pads that are disposed vertically above the second source electrodes, are electrically connected to the second source electrodes, and extend along the first direction;
a plurality of first common interconnects, each of which is continuously disposed from vertically above one of the first source electrodes to vertically above one of the second drain electrodes, is electrically connected to the one of the first source electrodes and the one of the second drain electrodes, and extends in the first direction; and
a plurality of second common interconnects, each of which is connected to the first common interconnects, and extends in a second direction that intersects with the first direction,
wherein the plurality of first common interconnects and the plurality of second common interconnects are disposed in a same layer, and
wherein each of the plurality of second common interconnects is directly connected to the first common interconnects.

US Pat. No. 10,510,654

DUMMY METAL WITH ZIGZAGGED EDGES

Taiwan Semiconductor Manu...

1. An integrated circuit structure comprising:a metal pad;
a first dielectric layer over the metal pad;
a conductive line comprising a first portion over the first dielectric layer, and a second portion extending into the first dielectric layer to connect to the metal pad; and
a first metal plate over the first dielectric layer, wherein the first metal plate fully encircles the conductive line, and wherein the first metal plate comprises an edge, and the edge comprises:
a first portion and a second portion aligned to a straight line in a top view of the integrated circuit structure; and
a third portion between and connected to the first portion and the second portion, wherein the third portion offsets from the straight line.

US Pat. No. 10,510,653

FABRICATION PROCESS AND STRUCTURE OF FINE PITCH TRACES FOR A SOLID STATE DIFFUSION BOND ON FLIP CHIP INTERCONNECT

Compass Technology Compan...

1. A semiconductor package comprising:a flexible substrate;
a plurality of traces formed on said flexible substrate, each trace comprising:
a copper layer on said flexible substrate;
a nickel-phosphorus layer on top and side surfaces of said copper layer;
a palladium layer on said nickel-phosphorus layer; and
a gold layer on said palladium layer; and
at least one die mounted on said substrate wherein there is a diffusion bond between at least one of said plurality of traces and said at least one die and an underfill between said at least one die and said substrate.

US Pat. No. 10,510,651

HARD MACRO HAVING BLOCKAGE SITES, INTEGRATED CIRCUIT INCLUDING SAME AND METHOD OF ROUTING THROUGH A HARD MACRO

QUALCOMM Incorporated, S...

1. A method comprising:forming a first layer of an integrated circuit;
forming a second layer of the integrated circuit on the first layer of the integrated circuit, the second layer including at least one hard macro;
forming at least one via through the hard macro;
forming a third layer on top of the second layer; and
electrically connecting an element on the first layer to an element on the third layer using the at least one via.

US Pat. No. 10,510,648

FAN-OUT PACKAGE STRUCTURE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:embedding a semiconductor structure in a molding compound layer;
depositing a plurality of photo-sensitive material layers over the molding compound layer, the plurality of photo-sensitive material layers comprising a second photo-sensitive material layer over a first photo-sensitive material layer;
developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein the first photo-sensitive material layer is exposed to light prior to depositing the second photo-sensitive material layer, the first photo-sensitive material layer being developed after depositing the second photo-sensitive material layer, wherein a first portion and a second portion of an opening of the plurality of openings are formed in the first and second photo-sensitive material layers respectively; and
filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

US Pat. No. 10,510,647

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:an organic interposer including insulating layers and wiring layers disposed on the insulating layers;
a semiconductor chip disposed on one surface of the organic interposer and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant disposed on the organic interposer and encapsulating at least portions of the semiconductor chip;
a passivation layer disposed on another surface of the organic interposer opposing the one surface of the organic interposer on which the semiconductor chip is disposed and having openings extending to at least portions of the wiring layer; and
an underbump metallurgy (UBM) layer including UBM pads disposed on the passivation layer and UBM vias disposed in the openings and connecting the UBM pads and the wiring layer to each other,
wherein at least one groove portion is disposed in an outer circumferential surface of the UBM pad.

US Pat. No. 10,510,643

SEMICONDUCTOR PACKAGE WITH LEAD FRAME AND RECESSED SOLDER TERMINALS

TEXAS INSTRUMENTS INCORPO...

17. A semiconductor device comprising:a lead frame including a die attach pad, the die attach pad including a first surface and an opposite second surface;
a semiconductor chip attached to the die attach pad and electrically connected to a plurality of leads, each of the plurality of leads including a first lead surface, a second lead surface opposite to the first lead surface, a third lead surface and a fourth lead surface opposite to the third lead surface, wherein a plane along the third lead surface is below a plane along the first lead surface, and a plane along the fourth lead surface is below a plane along the second lead surface, the semiconductor chip including a third surface and an opposite fourth surface, the opposite fourth surface of the semiconductor chip attached to the first surface of the die attach pad;
a packaging compound covering portions of the semiconductor chip, the die attach pad and the plurality of leads forming a package, the opposite second surface of the die attach pad exposed from the package on a package surface, the opposite second surface being coplanar with the package surface; and
a plurality of recess holes having a conductive adhesive, each of the plurality of recess holes extending from a first surface of each of the plurality of leads to the package surface;
wherein a first distance between a plane along the package surface and a plane along the opposite fourth surface of the semiconductor chip is less than a second distance between the plane along the package surface and the plane along the third lead surface of each of the plurality of leads.

US Pat. No. 10,510,642

SEMICONDUCTOR DEVICE MODULE

Mitsubishi Electric Corpo...

1. A semiconductor device module, comprising:a semiconductor device including a top electrode and a bottom electrode;
a substrate on which the bottom electrode of the semiconductor device is bonded;
a heat sink on which the substrate is mounted;
a lead electrode through which a main current of the semiconductor device flows;
an insulating case disposed to enclose the substrate; and
a retainer disposed in a cantilevered manner in the insulating case, the retainer supporting the lead electrode,
wherein the lead electrode has one end brazed to the top electrode of the semiconductor device, and another end side inserted into a wall of the insulating case, and
the retainer is engaged on the one end of the lead electrode to restrict movement of the lead electrode.

US Pat. No. 10,510,641

SEMICONDUCTOR DEVICE HAVING BACKSIDE INTERCONNECT STRUCTURE ON THROUGH SUBSTRATE VIA AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a semiconductor substrate having a frontside and a backside, the frontside having a transistor formed thereon and the backside being opposite the frontside;
a through-substrate via extending from the frontside to the backside of the semiconductor substrate and comprising a convex portion protruding from the backside of the semiconductor substrate;
an isolation film comprising a first portion formed on a sidewall of the convex portion of the through-substrate via and a second portion formed on the backside of the semiconductor substrate, wherein the top of the convex portion of the through-substrate via is higher than a top surface of the second portion of the isolation film;
a conductive layer comprising a first portion formed on a top of the convex portion of the through-substrate via and a second portion formed on the second portion of the isolation film; and
a passivation layer partially covering a topmost surface of the conductive layer, the passivation layer including an opening therein that at least partially exposes the first portion of the conductive layer.

US Pat. No. 10,510,636

ELECTRONIC MODULE

SHINDENGEN ELECTRIC MANUF...

1. An electronic module comprising:a substrate;
an other-side electronic component provided on the other side of the substrate;
a one-side electronic component provided on the one side of the substrate;
a sealing part sealing the other-side electronic component; and
a connecting terminal having an other-side extending part extending to circumferential outside of the substrate on the other side of the substrate, the other-side extending part being exposed outside the sealing part, a one-side extending part extending to circumferential outside of the substrate on one side of the substrate, the one-side extending part being outside the sealing part, and a connecting part connecting the other-side extending part with the one-side extending part at the circumferential outside of the substrate, the connecting part being outside the sealing part, the connecting terminal electrically connecting the other-side electronic component in the sealing part with the one-side electronic component outside the sealing part,
wherein the one-side extending part, the other-side extending part, and the connecting part are integrally formed,
the other-side extending part is provided on an other side conductive layer provided on the other side of the substrate and the one-side extending part is provided on a one-side conductive layer provided on one side of the substrate, or the other-side extending part is provided on a surface on the other side of the substrate, the other side including a metal substrate and the one-side extending part is provided on a surface on one side of the substrate, the one side including the metal substrate, and
the surface on the other side of the substrate is entirely provided in the sealing part, and the surface on one side of the substrate is not sealed by the sealing part.

US Pat. No. 10,510,634

PACKAGE STRUCTURE AND METHOD

Taiwan Semiconductor Manu...

10. A method comprising:forming a dielectric layer on an interposer, the interposer comprising a through via;
patterning an opening in the dielectric layer;
depositing a seed layer in the opening and along the dielectric layer;
plating a first conductive material on the seed layer to form an under bump metallurgy (UBM) extending along the dielectric layer and through the opening, the first conductive material plated with the seed layer; and
plating a second conductive material on the first conductive material to form a conductive bump laterally offset from the through via, the second conductive material plated with the seed layer.

US Pat. No. 10,510,633

PACKAGE AND PRINTED CIRCUIT BOARD ATTACHMENT

Taiwan Semiconductor Manu...

1. A method comprising:disposing solder on first pads on a side of a package, the package including one or more dies; and
attaching pins on second pads on the side of the package, wherein the first pads and the second pads together form a matrix on the side of the package, the second pads being in outer rows, outer columns, or a combination thereof of the matrix.

US Pat. No. 10,510,629

INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming a first die structure, the first die structure comprising a die stack bonded to a carrier, wherein forming the first die structure comprises:
bonding a front side of a first integrated circuit die to the carrier;
bonding a first dummy die to the carrier adjacent the first integrated circuit die;
encapsulating the first integrated circuit die and the first dummy die in a first encapsulant;
bonding a front side of a second integrated circuit die to a backside of the first integrated circuit die, the backside of the first integrated circuit die being opposite the front side of the first integrated circuit die;
bonding a second dummy die to the first dummy die; and
encapsulating the second integrated circuit die and the second dummy die in a second encapsulant;
forming a second die structure, the second die structure comprising a third integrated circuit die; and
bonding the first die structure to the second die structure by bonding a backside of a topmost integrated circuit die of the die stack to a backside of the third integrated circuit die, the topmost integrated circuit die of the die stack being a farthest integrated circuit die of the die stack from the carrier.

US Pat. No. 10,510,622

VERTICALLY STACKED COMPLEMENTARY-FET DEVICE WITH INDEPENDENT GATE CONTROL

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a stack of semiconductor material layers above a substrate, the stack including an upper region and a lower region;
forming a first spacer adjacent the lower region positioned at a first end of the stack;
forming a second spacer adjacent the upper region positioned at a second end of the stack opposite the first end;
forming a sacrificial gate structure above the stack;
forming a sidewall spacer adjacent the sacrificial gate structure;
selectively removing the sacrificial gate structure to define a gate cavity defined by the sidewall spacer and selectively removing a first subset of the semiconductor material layers in the stack to define inner cavities between a second subset of remaining semiconductor material layers;
forming a gate insulation layer in the inner cavities and the gate cavity;
forming a first conductive material in the inner cavities;
forming a first mask covering the second end of the stack;
removing the first conductive material from the inner cavities in the upper region, wherein the first conductive material in the inner cavities in the lower region remain as a first gate electrode;
removing the first mask; and
forming a second conductive material different than the first conductive material in the inner cavities in the upper region to define a second gate electrode.

US Pat. No. 10,510,620

WORK FUNCTION METAL PATTERNING FOR N-P SPACE BETWEEN ACTIVE NANOSTRUCTURES

GLOBALFOUNDRIES, INC., G...

1. A field effect transistor (FET) structure, comprising:a first type field effect transistor having: a first active nanostructure on a substrate, a gate having a high dielectric constant (high-K) layer and a first work function metal (WFM) surrounding the first active nanostructure, and a source/drain (S/D) region at each of opposing ends of the first active nanostructure;
a second type field effect transistor having: a second active nanostructure on the substrate adjacent to the first active nanostructure and separated by a space, the second FET further including a gate having the first WFM and a second work function metal (WFM) surrounding the second active nanostructure, and a source/drain (S/D) region at each of opposing ends of the second active nanostructure, the second WFM being different than the first WFM; and
an isolation pillar positioned between the first and second active nanostructures in the space,
wherein one of the first and second WFMs extends along a sidewall of the isolation pillar but not over a part of the isolation pillar.

US Pat. No. 10,510,619

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor structure, comprising:forming a plurality of fin structures and a plurality of trenches over a semiconductor substrate, wherein the fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer;
forming a dielectric layer over the substrate, wherein the dielectric layer is in the plurality of trenches;
annealing the dielectric layer;
removing the dielectric layer outside the plurality of trenches;
forming a plurality of dopants in the dielectric layer when the fin structures are covered by the mask layer, after the removing the dielectric layer outside the plurality of trenches; and
after the dopants are formed in the dielectric layer, lowering a top surface of the dielectric layer to a level below a top surface of the fin structures by referring to a distribution of a doping concentration of the dopants to remove a portion of the dielectric layer in the trenches, wherein a middle portion between the top surface at the level and a bottom surface of the dielectric layer has a highest density of the doping concentration.

US Pat. No. 10,510,618

FINFET EPI CHANNELS HAVING DIFFERENT HEIGHTS ON A STEPPED SUBSTRATE

Taiwan Semiconductor Manu...

1. A method comprising:etching a substrate to form a stepped substrate having an upper step and a lower step;
depositing a hard mask over the stepped substrate;
forming a first recess and a second recess in the hard mask, with the first recess being over the lower step and the second recess being over the upper step;
epitaxially growing a first epitaxy material in the first recess and in the second recess;
epitaxially growing a second epitaxy material in the first recess and in the second recess, the second epitaxy material having a faceted top protruding from the hard mask;
planarizing the second epitaxy material to align upper surfaces of the second epitaxy material; and
removing the hard mask.

US Pat. No. 10,510,614

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

16. A semiconductor arrangement, comprising:a first set of fins;
a second set of fins, spaced apart from the first set of fins;
a first metal connect contacting the first set of fins;
a second metal connect contacting the second set of fins, wherein the second metal connect is separated from the first metal connect by a first dielectric layer;
a second dielectric layer over the first dielectric layer, the first metal connect, and the second metal connect; and
a third metal connect disposed in the second dielectric layer, wherein the third metal connect electrically couples the first metal connect to the second metal connect.

US Pat. No. 10,510,609

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:substrate having a first region and a second region;
a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature; and
a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure, wherein a center of curvature of the first fin-shaped structure is lower than a top surface of the STI and a center of curvature of the second fin-shaped structure is higher than the top surface of the STI.

US Pat. No. 10,510,608

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A method for manufacturing a semiconductor structure, the method comprising:forming an insulating layer covering a first fin and a second fin;
forming a mask layer over the insulating layer and covering the first fin and the second fin;
patterning the mask layer to form a gap between the first fin and the second fin;
forming an insulating structure in the gap, wherein the insulating structure is formed over a first portion of the insulating layer;
after forming the insulating structure, removing the mask layer, wherein removing the mask layer includes removing a first portion of the mask layer and a second portion of the insulating layer;
after removing the mask layer, forming a first dummy gate and a second dummy gate at the opposite sides of the insulating structure, wherein the first dummy gate and the second dummy gate are, respectively, at least partially present on the first fin and the second fin;
removing the first dummy gate and the second dummy gate; and
forming first and second gates at opposite sides of the insulating structure, wherein the first and second gates are respectively at least partially present on the first and second fins.

US Pat. No. 10,510,607

SEMICONDUCTOR DEVICE CONVEX SOURCE/DRAIN REGION

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:forming a first recess in a first fin, the first fin being on a substrate, the first recess being proximate a gate structure over the first fin;
forming a second recess in a second fin, the second fin being on the substrate, the second recess being proximate the gate structure over the second fin; and
epitaxially growing a source/drain region in the first recess and the second recess using a remote plasma chemical vapor deposition (RPCVD) process, the RPCVD process including using a silicon source precursor and a hydrogen carrier gas, wherein epitaxially growing the source/drain region comprises:
epitaxially growing a first portion of the source/drain region along a bottom surface and a side surface of the first recess and the second recess, wherein the first portion in the first recess has a first convex upper surface, wherein the first portion in the second recess has a second convex upper surface; and
epitaxially growing a second portion of the source/drain region over the first portion in the first recess and the first portion in the second recess, wherein the second portion has a third convex upper surface extending from a first plane to a second plane and being laterally between the first recess and the second recess, a first sidewall of the first fin being in the first plane, a second sidewall of the second fin being in the second plane, the first sidewall of the first fin being a sidewall of the first fin closest to the second fin, the second sidewall of the second fin being a sidewall of the second fin closest to the first fin.

US Pat. No. 10,510,602

METHODS OF PRODUCING SELF-ALIGNED VIAS

Mirocmaterials LLC, Wilm...

1. A method to provide a self-aligned via, the method comprising:forming a first metal film on recessed first conductive lines and on first insulating layers of a substrate with recessed first conductive lines extending along a first direction;
forming a sheet supported by a plurality of pillars from the first metal film, the sheet spaced a distance from a top of the first insulating layers to form a gap;
selectively removing a portion of the sheet and the pillars to leave at least one portion of sheet supported by at least two pillars;
depositing a flowable second insulating layer around the remaining pillars and the sheet and fill the gap;
removing the remaining pillars and the sheet to form vias in the second insulating layer;
depositing a third insulating layer in the vias onto the recessed first conductive lines to form filled vias;
forming an overburden of third insulating layer on the second insulating layer;
selectively etching a portion of the overburden from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of third insulating layer on the second insulating layer; and
etching the third insulating layer from the filled vias to form via openings to the first conductive line.

US Pat. No. 10,510,601

METHOD FOR REDUCING METAL PLUG CORROSION AND DEVICE

Taiwan Semiconductor Manu...

1. A method comprising:forming a transistor comprising:
forming a gate dielectric on a semiconductor region;
forming a gate electrode over the gate dielectric; and
forming a source/drain region extending into the semiconductor region;
forming a source/drain contact plug over and electrically coupled to the source/drain region;
forming a gate contact plug over and electrically coupled to the gate electrode, wherein forming at least one of the source/drain contact plug or the gate contact plug comprises a CMP operation; and
during the forming of the source/drain contact plug or gate contact plug, exposing at least one of the source/drain contact plug or the gate contact plug to a metal ion source solution, wherein a constituent metal of a metal ion in the metal ion source solution and a constituent metal of the at least one of the source/drain contact plug or gate contact plug are the same, and
minimizing a metal recess of the least one of the source/drain contact plug or the gate contact plug to a depth of less than two nm measured from a top surface of a dielectric layer adjacent to a respective contact plug surface while maintaining a CMP removal rate of the CMP operation greater than 30 nm/minute during formation of the respective contact plug.

US Pat. No. 10,510,600

SHARED CONTACT STRUCTURE AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

16. A method for semiconductor processing, the method comprising:forming a first transistor on a substrate, the first transistor comprising a source/drain region, a gate structure, and a spacer along a sidewall of the gate structure;
forming a first dielectric layer over the substrate, wherein a surface of a conductive feature and a surface of a protective layer is exposed, the conductive feature contacting the source/drain region and the protective layer contacting the gate structure;
forming a second dielectric layer over the first dielectric layer;
forming a butted contact opening, forming the butted contact opening comprising:
forming a first opening through the second dielectric layer;
filling the first opening with a sacrificial material;
forming a second opening through the second dielectric layer, wherein the second opening overlaps the first opening; and
removing the sacrificial material, thereby forming the butted contact opening, the butted contact opening exposing a surface of the conductive feature and a surface of the gate structure; and
forming a conductive material in the butted contact opening.

US Pat. No. 10,510,597

METHODS FOR HYBRID WAFER BONDING INTEGRATED WITH CMOS PROCESSING

Taiwan Semiconductor Manu...

1. A method, comprising:manufacturing a first front-end substrate having a plurality of active devices in the first front-end substrate in a first semiconductor process;
manufacturing a first back-end substrate in a second semiconductor process, the first back-end substrate comprising metallization layers disposed in dielectric material, wherein the first back-end substrate is free from active devices;
forming a first redistribution layer over the first front-end substrate and the first back-end substrate, the first redistribution layer including first metal pads and first dielectric material separating the first metal pads;
oxidizing a first surface of the first redistribution layer over the first front-end substrate and a second surface of the first redistribution layer over the first back-end substrate;
etching the oxidized first surface and the oxidized second surface of the first redistribution layer, wherein after the etching the oxidized first surface and the oxidized second surface of the first redistribution layer, the first metal pads have convex surfaces, and the convex surfaces of the first metal pads are recessed from a surface of the first dielectric material;
after the etching the oxidized first surface and the oxidized second surface of the first redistribution layer, physically contacting the first surface of the first redistribution layer and the second surface of the first redistribution layer; and
performing wafer bonding to form bonds between the first front-end substrate and the first back-end substrate to form a first integrated circuit.

US Pat. No. 10,510,596

METAL GATES OF TRANSISTORS HAVING REDUCED RESISTIVITY

Taiwan Semiconductor Manu...

1. An integrated circuit device comprising:gate spacers;
a gate dielectric extending into a space between the gate spacers;
a gate electrode over a bottom portion of the gate dielectric;
a gate contact plug over and contacting the gate electrode;
a source/drain region adjacent to the gate electrode;
a source/drain silicide region over and contacting the source/drain region; and
a source/drain contact plug over and contacting the source/drain silicide region, wherein the gate contact plug has a sidewall comprising a vertical lower portion, and a curved upper portion, and the curved upper portion has greater widths than the vertical lower portion, and wherein at least one of the gate electrode, the source/drain contact plug, and the gate contact plug comprises a metal silicide layer.

US Pat. No. 10,510,595

INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, the method comprising:attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil;
forming a conductive pillar on a first side of the metal foil distal to the carrier;
attaching a semiconductor die to the first side of the metal foil;
after attaching the semiconductor die, performing an etching process, wherein the etching process reduces a width of the conductive pillar, wherein the etching process removes a portion of the metal foil disposed laterally between the conductive pillar and the semiconductor die, and wherein a remaining portion of the metal foil disposed between the semiconductor die and the carrier has a width that is smaller than a width of the semiconductor die;
after performing the etching process, forming a molding material around the semiconductor die and the conductive pillar; and
forming a redistribution structure over the molding material.

US Pat. No. 10,510,594

METHOD OF CLEANING WAFER AFTER CMP

Taiwan Semiconductor Manu...

1. A structure comprising:a first dielectric layer;
a first metal plug in the first dielectric layer, wherein a top surface of the first metal plug is substantially coplanar with a top surface of the first dielectric layer;
a carbon-rich layer overlying and contacting the first metal plug, wherein the carbon-rich layer has a first carbon concentration higher than a second carbon concentration of the first metal plug; and
a second dielectric layer overlying and contacting the carbon-rich layer, wherein the second dielectric layer comprises carbon and has a third carbon concentration, and the first carbon concentration is higher than the third carbon concentration.

US Pat. No. 10,510,592

INTEGRATED CIRCUIT (IC) STRUCTURE FOR HIGH PERFORMANCE AND FUNCTIONAL DENSITY

Taiwan Semiconductor Manu...

1. An integrated circuit (IC) comprising:a semiconductor substrate, wherein the semiconductor substrate is a single, continuous piece of semiconductor material;
a first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure respectively under and over the semiconductor substrate, wherein the second BEOL interconnect structure comprises a plurality of wires and a plurality of vias, and wherein the semiconductor substrate is completely between the first and second BEOL interconnect structures;
a first electronic device and a second electronic device between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure, wherein the first electronic device is disposed at least partially in a bottom of the semiconductor substrate, between the semiconductor substrate and the first BEOL interconnect structure, and wherein the second electronic device is in a top of the semiconductor substrate, between the semiconductor substrate and the second BEOL interconnect structure;
a through substrate via (TSV) extending through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure;
a pad structure over and electrically coupled to the second BEOL interconnect structure, wherein the pad structure is at a top surface of the IC;
a dielectric layer over the semiconductor substrate and within the second BEOL interconnect structure, wherein the dielectric layer extends continuously from direct contact with the semiconductor substrate to direct contact with the pad structure, and wherein the wires and the vias are alternatingly stacked in the dielectric layer; and
wherein the second electronic device comprises a pair of source/drain regions and a gate electrode, wherein the source/drain regions are in the top of the semiconductor substrate, wherein the gate electrode is laterally between the source/drain regions, wherein the gate electrode is spaced over the semiconductor substrate by a gate dielectric layer that is arranged over and contacts a top surface of the TSV, and wherein the gate dielectric layer is within the dielectric layer of the second BEOL interconnect structure.

US Pat. No. 10,510,591

PACKAGE-ON-PACKAGE STRUCTURE AND METHOD OF MANUFACTURING PACKAGE

Taiwan Semiconductor Manu...

1. A method of manufacturing a package, comprising:providing a carrier having a de-bonding layer formed thereon;
forming a conductive structure over the de-bonding layer, wherein the conductive structure comprises a seed layer attached to the de-bonding layer;
attaching a die on the de-bonding layer through an adhesive layer, wherein the die comprises an amorphous layer attached to the adhesive layer;
removing the carrier;
removing the de-bonding layer and the adhesive layer to expose the amorphous layer; and
removing a portion of the seed layer after removing the de-bonding layer and the adhesive layer.

US Pat. No. 10,510,589

CYCLIC CONFORMAL DEPOSITION/ANNEAL/ETCH FOR SI GAPFILL

APPLIED MATERIALS, INC., ...

1. A method for manufacturing a semiconductor device, comprising:positioning a substrate having one or more features formed in a surface of the substrate, each of the one or more features having sidewalls and a bottom surface, in a process chamber;
depositing an amorphous silicon film over the substrate having one or more features;
annealing the deposited amorphous silicon film to heal one or more seams formed in the one or more features; and
etching a portion of the annealed amorphous silicon film to remove one or more voids formed in the annealed amorphous silicon film in the one or more features.

US Pat. No. 10,510,588

INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. An interconnection structure, comprising:a conductive feature;
a first dielectric layer in contact with a sidewall of the conductive feature;
a first etch stop layer comprising a metal, wherein the first etch stop layer overlies the first dielectric layer and the conductive feature;
a second etch stop layer, wherein the first etch stop layer and the second etch stop layer comprise different materials;
a second dielectric layer overlying the first etch stop layer, wherein the second etch stop layer is disposed between the first etch stop layer and the second dielectric layer;
a conductor present between a first portion of the second dielectric layer and a second portion of the second dielectric layer; and
a plurality of fragments comprising the metal and present on a sidewall of the first portion of the second dielectric layer facing the conductor, wherein a density of the fragments decreases with an increasing distance from the conductive feature.

US Pat. No. 10,510,584

VIA PATTERNING USING MULTIPLE PHOTO MULTIPLE ETCH

Taiwan Semiconductor Manu...

1. A method comprising:forming a dielectric layer;
forming a trench in the dielectric layer;
dispensing a filling material, wherein the filling material comprises a first portion filling the trench;
etching the filling material;
etching the dielectric layer to form a via opening in the dielectric layer, wherein a portion of the filling martial acts as a part of an etching mask, and the via opening penetrates through a first etch stop layer underlying the dielectric layer;
removing the filling material; and
after the filling material is removed, etching-through a second etch stop layer underlying the first etch stop layer to expose a conductive feature.

US Pat. No. 10,510,582

ENGINEERED SUBSTRATE STRUCTURE

Qromis, Inc., Santa Clar...

1. A substrate comprising:a polycrystalline ceramic core;
a first adhesion layer encapsulating the polycrystalline ceramic core;
a conductive layer encapsulating the first adhesion layer;
a second adhesion layer encapsulating the conductive layer;
a barrier layer encapsulating the second adhesion layer;
a bonding layer coupled to the barrier layer; and
a substantially single crystalline silicon layer coupled to the bonding layer.

US Pat. No. 10,510,581

METHODS OF FORMING STRAINED-SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES

Taiwan Semiconductor Manu...

1. A method comprising:forming a graded buffer layer over a first substrate;
forming a relaxed layer over the graded buffer layer;
epitaxially growing a compressively strained semiconductor layer over the relaxed layer, the relaxed layer inducing strain in the compressively strained semiconductor layer, the compressively strained semiconductor layer having an initial misfit dislocation density;
bonding the compressively strained semiconductor layer directly to a second substrate, the compressive strain in the compressively strained semiconductor layer being substantially maintained after the bonding;
removing the first substrate, the graded buffer layer, and the relaxed layer from the compressively strained semiconductor layer, the compressively strained semiconductor layer remaining bonded to second substrate after the removing, wherein removing the first substrate reduces the initial misfit dislocation density in the compressively strained semiconductor layer; and
planarizing the compressively strained semiconductor layer where the relaxed layer has been removed, the planarizing the compressively strained semiconductor layer comprises an anneal performed at a temperature greater than approximately 800° C.

US Pat. No. 10,510,580

DUMMY FIN STRUCTURES AND METHODS OF FORMING SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate;
depositing a dielectric material over the first dielectric film;
recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material, wherein recessing the first dielectric film comprises etching the first dielectric film at a faster rate than the dielectric material; and
forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

US Pat. No. 10,510,577

LIFT OFF PROCESS FOR CHIP SCALE PACKAGE SOLID STATE DEVICES ON ENGINEERED SUBSTRATE

Qromis, Inc., Santa Clar...

1. A method of processing an engineered substrate structure, the method comprising:providing an engineered substrate structure including:
a polycrystalline substrate; and
an engineered layer encapsulating the polycrystalline substrate;
forming a sacrificial layer coupled to the engineered layer;
forming a solid state device structure coupled to the sacrificial layer;
forming one or more channels in the solid state device structure by removing one or more portions of the solid state device structure to expose one or more portions of the sacrificial layer;
after the one or more channels are formed, forming a molding support on the solid state device structure, the molding support exposing the one or more portions of the sacrificial layer;
after the molding support is formed, flowing an etching chemical through the one or more channels to the one or more portions of the sacrificial layer; and
dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure.

US Pat. No. 10,510,575

SUBSTRATE SUPPORT WITH MULTIPLE EMBEDDED ELECTRODES

APPLIED MATERIALS, INC., ...

8. A processing chamber, comprising:one or more sidewalls and a bottom defining a processing volume; and
a substrate support, comprising:
a plurality of first electrodes within the substrate support, each electrode of the plurality of first electrodes electrically isolated from every other electrode of the plurality of first electrodes, wherein
each electrode of the plurality of first electrodes is configured to provide a pulsed DC bias to a region of a substrate through capacitive coupling therewith,
each electrode of the plurality of first electrodes is independently electrically coupled to a respective switching pair of a pulsed DC biasing switching system,
each switching pair comprises a distinct first switch and a distinct second switch,
each of the switching pairs is configured to operate independently of the other switching pairs, and
the first switches are electrically coupled to a first DC voltage source and the second switches are electrically coupled to a second DC voltage source; and
a second electrode disposed within the substrate support, and electrically isolated from the plurality of first electrodes, for electrically clamping the substrate to the substrate support.

US Pat. No. 10,510,571

RETICLE TRANSFER SYSTEM AND METHOD

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:transporting wafers and reticles between a global system and a local system, wherein an input terminal of the local system is connected to the global system, and wherein the local system comprises:
a first buffer at a boundary between the global system and the local system;
a second buffer at a default position of the local system, wherein the default position is a boundary between a first service area and a second service area, wherein the first service area comprises at least one carrier, wherein the second buffer and the at least one carrier are independently moveable; and
a third buffer at an end of the local system, wherein the first service area is from the first buffer to the second buffer and the second service area is from the second buffer to the third buffer;
transporting a reticle from a first scanner in the first service area to a second scanner in the second service area;
adjusting the boundary between the first service area and the second service area by moving the second buffer, wherein the second scanner is in the first service area as a result of performing the step of adjusting the boundary between the first service area and the second service area; and
transporting the reticle to the second scanner.

US Pat. No. 10,510,569

PATTERN FORMING APPARATUS AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A pattern forming apparatus comprising:a processing unit that applies processing to a substrate having a mark provided on a front surface of the substrate;
a transfer unit that transfers the substrate into the processing unit;
a placing table on which the substrate transferred into the processing unit is placed;
a first imaging element that is provided at a position included in the placing table and overlapping with an edge of the substrate, and captures an image of the substrate from a back side of the substrate to detect a position of the edge of the substrate;
a second imaging element that captures an image of the mark of the substrate on the placing table from a front side of the substrate to detect a position of the mark; and
a control unit that calculates, before performing alignment of the position of the substrate with the position of the mark detected by the second imaging element, a positional displacement amount of the substrate from the position of the edge of the substrate detected by the first imaging element, and controls the placing table based on the positional displacement amount of the substrate to correct the position of the substrate.

US Pat. No. 10,510,568

CORROSION INHIBITOR INJECTION APPARATUS

RKD Engineering Corporati...

1. An inhibitor solution injector system for an IC decapsulation apparatus, comprising:a first source reservoir containing inhibitor solution;
a second source reservoir containing etchant solution;
an injection coupling having an etchant input passage intersecting at an angle approximately 135 degrees with an etchant output passage, and an inhibitor input passage joining the etchant passages at the intersection of the etchant input passage and the etchant output passage;
an etchant pump coupled to the second source reservoir, pumping etchant to the etchant input passage and through the etchant output passage;
an inhibitor injection apparatus comprising a motor-driven syringe coupled to the first source reservoir and to the inhibitor input passage; and
control circuitry controlling the motor-driven syringe of the fluid injection apparatus;
wherein the etchant pump urges etchant from the second source reservoir through the etchant input and output passages, and the motor-driven syringe of the inhibitor injection apparatus draws inhibitor from the first source reservoir, and the control circuitry controls the motor-driven syringe to inject the inhibitor into the etchant passages at the point of intersection of the etchant input passage and the etchant output passage, the acute change in direction in the etchant passages causing turbulence enhancing efficiency of mixing the etchant and the inhibitor.

US Pat. No. 10,510,567

INTEGRATED SUBSTRATE TEMPERATURE MEASUREMENT ON HIGH TEMPERATURE CERAMIC HEATER

APPLIED MATERIALS, INC., ...

8. A processing chamber, comprising:a chamber body defining a processing volume; and
a substrate support assembly disposed in the processing volume, the substrate support assembly comprising:
a support shaft;
a substrate support disposed on the support shaft;
a substrate temperature monitoring system for measuring a temperature of a substrate to be disposed on the substrate support, comprising:
an optical fiber tube;
a light guide coupled to the optical fiber tube, wherein the light guide comprises a sapphire tube having a length of at least 400 mm and an inner diameter of at least about 40 mm, and at least a portion of the light guide is disposed in an opening extending through the support shaft and into the substrate support; and
a cooling assembly disposed about a junction of the optical fiber tube and the light guide, wherein the cooling assembly maintains the optical fiber tube at a temperature of less than about 100° C. during substrate processing.

US Pat. No. 10,510,564

DYNAMIC COOLANT MIXING MANIFOLD

LAM RESEARCH CORPORATION,...

1. A system for controlling temperature of a substrate arranged on a substrate support assembly, the system comprising:first and second sources to respectively supply a fluid at first and second temperatures;
a first three-way proportional valve with an input port connected to the first source, a first output port connected to a supply line to supply the fluid from the first source to the substrate support assembly, and a second output port connected to the first source;
a second three-way proportional valve with an input port connected to the second source, a first output port connected to the supply line to supply the fluid from the second source to the substrate support assembly, and a second output port connected to the second source;
a third three-way proportional valve with an input port connected to a return line to receive the fluid from the substrate support assembly, and first and second output ports respectively connected to the first and second sources to return the fluid received from the substrate support assembly to the first and second sources; and
a controller configured to control the first and second three-way proportional valves to:
output first portions of the fluid received from the first and second sources via the respective input ports to supply the fluid to the substrate support assembly via the supply line at a predetermined temperature and at a predetermined flow rate; and
return second portions of the fluid received from the first and second sources via the respective input ports to the first and second sources via the second output ports of the first and second three-way proportional valves, respectively; and
wherein the controller is further configured to control the third three-way proportional valve to divide the fluid received from the substrate support assembly via the return line between the first and second sources to maintain fluid levels of the first and second sources between first and second thresholds,
wherein the first threshold is a minimum allowable level of the fluid to prevent an under-filled condition in each of the first and second sources, and wherein the second threshold is a maximum allowable level of the fluid to prevent an overfilled condition in each of the first and second sources.

US Pat. No. 10,510,563

WAFER CARRIER ASSEMBLY

TAIWAN SEMICONDUCTOR MANU...

1. A wafer carrier assembly, comprising:a wafer carrier comprising a retainer ring confining a wafer accommodation space, a plate over the retainer ring, and a rim surrounding a periphery of the plate, wherein the plate has a bore through the plate; and
a fluid passage inside the wafer carrier and configured to deliver a fluid, wherein the fluid passage includes an inlet, and at least an outlet to dispense the fluid into the wafer accommodation space, and wherein the fluid passage comprises a first tube through the bore of the plate, and a second tube under the plate and in communication with the first tube, the first tube has a first end configured as the inlet of the fluid passage, the second tube has a first end in communication with a second end of the first tube, and a second end configured as the outlet of the fluid passage, and the second tube is rotatable with respect to the rim and the first tube,
wherein the first end of the second tube surrounds the second end of the first tube, and an inner diameter of the first end of the second tube is greater than an outer diameter of the second end of the first tube.

US Pat. No. 10,510,562

STACKED SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a die having:
contact pads thereon; and
a routing structure over the contact pads, the routing structure comprising:
a passivation layer over the contact pads;
a buffer layer over the contact pads and the passivation layer;
first conductive pillars over a first set of the contact pads, the first conductive pillars having first portions and second portions, the first portions extending through the passivation layer and the buffer layer, the first portions contacting the first set of the contact pads, the second portions extending over the buffer layer;
conductive lines over the buffer layer, the conductive lines connecting pairs of the first conductive pillars; and
a protective layer over the buffer layer and the passivation layer, a portion of the protective layer being between one of the first conductive pillars and the one of the conductive lines, the portion of the protective layer contacting the passivation layer; and
an external connector structure over the routing structure, the routing structure electrically coupling the contact pads to the external connector structure.

US Pat. No. 10,510,561

SEMICONDUCTOR DEVICE PACKAGE INCLUDING CONFORMAL METAL CAP CONTACTING EACH SEMICONDUCTOR DIE

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:bonding a first semiconductor die and a second semiconductor die to a first substrate;
forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate;
applying an encapsulant over the conductive layer;
removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer;
removing a portion of the conductive layer, wherein the removing the portion of the conductive layer exposes the first semiconductor die; and
performing a singulation process on the first substrate, a surface of the conductive layer and a surface of the encapsulant being formed by the singulation process, the surface of the conductive layer being coplanar with the surface of the encapsulant, a portion of the encapsulant extending from a first portion of the conductive layer on a first sidewall of the first semiconductor die to a second portion of the conductive layer on a second sidewall of the second semiconductor die after performing the singulation process, the first sidewall facing the second sidewall.

US Pat. No. 10,510,560

METHOD OF ENCAPSULATING A SUBSTRATE

Nanyang Technological Uni...

1. A method of encapsulating a substrate having at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, wherein the first semiconductor material is a group III-V semiconductor material or a material formed from combining different III-V semiconductor materials, and wherein the layer of first semiconductor material is arranged intermediate the CMOS device layer and the layer of second semiconductor material such that adjoining edges of the layer of first semiconductor material, the CMOS device layer and the layer of second semiconductor material define a circumferential edge of the substrate, the method comprising:(i) removing a portion of the circumferential edge, wherein the portion removed comprises a portion of the CMOS device layer and a portion of the layer of first semiconductor material; and
(ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material such that the layer of first semiconductor material is unexposed.

US Pat. No. 10,510,559

POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING THE SAME

Infineon Technologies AG,...

1. A power semiconductor module arrangement, comprising:a base plate configured to be arranged in a housing;
a contact element configured to, when the base plate is arranged in the housing, provide an electrical connection between an inside and an outside of the housing; and
a connecting element configured to connect the contact element to the base plate,
wherein the connecting element comprises:
a first electrically insulating layer;
a second electrically insulating layer configured to attach the contact element to the first electrically insulating layer; and
a third electrically insulating layer configured to attach the first electrically insulating layer to the base plate.

US Pat. No. 10,510,558

ELECTRONIC DEVICE, THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

BOE Technology Group Co.,...

1. A manufacturing method of an electronic device, comprising:forming a metallic structure on a base substrate;
forming an oxygen-free insulating layer on the metallic structure and the base substrate; and
forming an insulating protective layer on the oxygen-free insulating layer,
wherein the oxygen-free insulating layer is made from silane; and the manufacturing method of the electronic device further comprises:
forming a semiconductor layer on a side of the metallic structure away from the oxygen-free insulating layer; and
changing a part of the semiconductor layer making contact with the oxygen-free insulating layer into a conductor by hydrogen released from the silane in the process of forming the oxygen-free insulating layer.

US Pat. No. 10,510,557

ELECTRONIC PART MOUNTING SUBSTRATE AND METHOD FOR PRODUCING SAME

DOWA METALTECH CO., LTD.,...

1. A method for producing an electronic part mounting substrate, the method comprising the steps of:surface-machining one side of the metal plate of aluminum or the aluminum alloy by wet blasting or lapping so as to cause the surface roughness thereof to be 0.3 to 1.4 micrometers, wherein the wet blasting or lapping uses abrasive grains having average particle diameter of at least 20 micrometers;
applying the silver paste on the surface-machined side of the metal plate of aluminum or the aluminum alloy;
arranging an electronic part on the silver paste applied on the surface-machined side of the metal plate of aluminum or the aluminum alloy; and
heating the silver paste, on which the electronic part is arranged and which is applied on the surface-machined side of the metal plate of aluminum or the aluminum alloy, at a temperature of 220 to 300° C. while pressing the electronic part at a pressure of 3 to 8 MPa against the metal plate, to sinter silver in the silver paste to form a silver bonding layer between the electronic part and the surface-machined side of the metal plate of aluminum or the aluminum alloy to bond the electronic part to the surface-machined side of the metal plate of aluminum or the aluminum alloy with the silver bonding layer.

US Pat. No. 10,510,553

DRY ASHING BY SECONDARY EXCITATION

Taiwan Semiconductor Manu...

1. A method, comprising:generating a first plasma from a first gas;
diffusing, in a wafer processing chamber, the first plasma through a first gas distribution plate (GDP), forming a first low energy region;
diffusing the first plasma from the first low energy region through a second GDP, forming a substrate processing region; and
supplying a second gas in the substrate processing region, wherein the first plasma energizes the second gas to form radicals of the second gas, wherein the radicals of the second gas strip a layer from a substrate.

US Pat. No. 10,510,552

HARD MASK REMOVAL METHOD

Taiwan Semiconductor Manf...

1. A method of removing a hard mask, the method comprising:patterning gate stacks on a substrate, wherein the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer, wherein the gate stacks are patterned in an isolated region and a dense region, and wherein gate stacks of the isolated region have lower thicknesses than gate stacks of the dense region;
depositing a dielectric layer directly on exposed portions of the substrate between the gate stacks and on the gate stacks, wherein after the dielectric layer is deposited the dielectric layer has a first thickness in the isolated region and a second thickness in the dense region, the first thickness is greater than the second thickness, the first thickness is between a first surface of the dielectric layer that is closest to the substrate in the isolated region and a second surface of the dielectric layer that is farthest from the substrate in the isolated region, the second thickness is between a third surface of the dielectric layer that is closest to the substrate in the dense region and a fourth surface of the dielectric layer that is farthest from the substrate in the dense region, and the first surface of the dielectric layer is level with the third surface of the dielectric layer;
planarizing a first portion of the dielectric layer by a first chemical mechanical polishing (CMP) process, wherein after the first CMP process a difference in the first thickness and the second thickness has been reduced; and
removing the hard mask and a second portion of the dielectric layer by a second CMP process, wherein a thickness difference between the gate stacks in the isolated region and the gate stacks in the dense region is less than 30 ? after the removing of the hard mask and the second portion.

US Pat. No. 10,510,550

POLARIZATION-DEPENDENT LASER-ASSISTED PLASMA ETCHING

The Board of Trustees of ...

1. A method of laser-assisted plasma etching with polarized light, the method comprising:providing a surface of a substrate including at least one surface region having trenches arranged in a unidirectional pattern along an x-direction or a y-direction of the surface, each trench having a depth along a z-direction, wherein the trenches extend substantially in parallel with each other and have a half-pitch of about 100 nm or less;
exposing the surface to a plasma;
illuminating the surface with a pulsed laser beam during the exposure to the plasma, the pulsed laser beam having a predetermined polarization along the x-direction or the y-direction; and
etching the trenches.

US Pat. No. 10,510,549

METHOD OF FABRICATING A METAL LAYER

UNITED MICROELECTRONICS C...

1. A method of fabricating a metal layer, comprising:providing a conductive layer, a metal compound contacting a top surface of the conductive layer, a dielectric layer covering the conductive layer, and a trench disposed in the dielectric layer, the metal compound being exposed through the trench;
performing a first re-sputtering on the metal compound and the dielectric layer with inert ions and metal ions, wherein the metal compound is removed entirely during the first re-sputtering, wherein during the first re-sputtering, the metal ions bombard the surface of the dielectric layer, and turn into metal atoms to deposit onto the surface of the dielectric layer;
after the first re-sputtering, forming a barrier covering the trench, wherein the barrier is formed in a chamber;
performing a second re-sputtering on the barrier with the inert ions and the metal ions, wherein the barrier at a bottom of the trench is entirely removed during the second re-sputtering and the second re-sputtering is performed in the chamber; and
forming a metal layer in the trench.

US Pat. No. 10,510,548

SEMICONDUCTOR STRUCTURE

Semiconductor Manufacturi...

1. A semiconductor structure, comprising:a base including a first region, a second region, a third region, and a fourth region, used for a first transistor, a second transistor, a third transistor, and a fourth transistor, respectively;
a gate dielectric layer on the first, second, third and fourth regions of the base;
a first material layer on the gate dielectric layer;
a second material layer on the first material layer above the fourth region;
a third material layer on the first material layer above the third region and on the second material layer above the fourth region; and
a fourth material layer on the third material layer above the third and fourth regions and on the first material layer on the second region, wherein:
the first material layer above the first region is used as a first work function layer for the first transistor,
the first and fourth material layers above the second region are used as a second work function layer for the second transistor,
the first, third and fourth material layers above the third region are used as a third work function layer for the third transistor,
the first, second, third and fourth material layers above the fourth region are used as a fourth work function layer for the fourth transistor, and
a thickness of the first work function layer is smaller than a thickness of the second work function layer, the thickness of the second work function layer is smaller than a thickness of the third work function layer, the thickness of the third work function layer is smaller than a thickness of the fourth work function layer.

US Pat. No. 10,510,547

METAL AND METAL-DERIVED FILMS

APPLIED MATERIALS, INC., ...

1. A substrate processing method, comprising:depositing a metal containing film on a substrate;
depositing a metal derived film on the metal containing film;
repeating sequential deposition of a metal containing film and a metal derived film on the metal containing film in an alternating manner to form a film stack of metal containing films and metal derived films, wherein the film stack exhibits a resistivity of less than about 80 ??/cm, a stress of between about 0 MPa and about 500 MPa, and a surface roughness of less than about RMS=0.6 nm.

US Pat. No. 10,510,545

HYDROGENATION AND NITRIDIZATION PROCESSES FOR MODIFYING EFFECTIVE OXIDE THICKNESS OF A FILM

APPLIED MATERIALS, INC., ...

18. A method of forming a structure in a semiconductor device, the method comprising:depositing a high-k dielectric layer on a semiconductor substrate;
depositing a capping layer on the high-k dielectric layer to form a portion of the structure, wherein the portion includes the capping layer and the high-k dielectric layer, and wherein the deposited capping layer has an exposed surface; and
exposing the exposed surface to a plasma-excited hydrogen species and a plasma-excited nitrogen species, wherein the plasma-excited hydrogen species comprises ammonia, and the plasma-excited nitrogen species comprises nitrogen gas (N2).

US Pat. No. 10,510,544

NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a non-volatile memory semiconductor device, comprising:forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate,
forming a conductive layer over the plurality of memory cells;
forming a first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise over the plurality of memory cells;
performing a planarization operation on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer;
after the planarization operation, forming a hard mask layer on the plurality of memory cells; and
after forming the hard mask layer on the plurality of memory cells, completely removing portions of a lower region of the conductive layer between the memory cells.

US Pat. No. 10,510,541

ANGULAR CONTROL OF ION BEAM FOR VERTICAL SURFACE TREATMENT

VARIAN SEMICONDUCTOR EQUI...

1. A method for forming a semiconductor device, the method comprising:providing a set of surface features extending from a substrate, the set of surface features including a sidewall;
treating the sidewall with an ion beam disposed at an angle, the angle being a non-zero angle of inclination with respect to a perpendicular to a plane of an upper surface of the substrate, wherein the ion beam impacts just a portion of the sidewall;
rotating the substrate about the perpendicular to the plane of the upper surface of the substrate; and
treating the sidewall with the ion beam, wherein the ion beam impacts an entire height of the sidewall with the ion beam.

US Pat. No. 10,510,540

MASK SCHEME FOR CUT PATTERN FLOW WITH ENLARGED EPE WINDOW

MICROMATERIALS LLC, Wilm...

1. A method of forming a semiconductor device, the method comprising:forming a first spin-on-carbon layer, a hardmask and a photoresist on a film, the film comprising alternating columns of spacer mandrels and gapfill materials with oxide films located between the alternating columns of spacer mandrels and gapfill materials, the photoresist having an opening over one of the columns of gapfill materials;
etching the hardmask and the first spin-on-carbon layer through the opening in the photoresist to remove the photoresist and portions of the hardmask and the first spin-on-carbon layer to expose a top of one of the columns of gapfill materials;
removing the first spin-on-carbon layer, the hardmask and one of the columns of gapfill material to form a gap;
forming a second spin-on-carbon layer, a second hardmask and a second photoresist on the film, the second spin-on-carbon layer filling the gap, the film comprising alternating columns of spacer mandrels, gapfill materials, oxide films and the second spin-on-carbon layer, the second photoresist having a second opening over one of the columns of spacer mandrels;
etching the second hardmask and the second spin-on carbon layer through the second opening in the second photoresist to remove the second photoresist and portions of the second hardmask and second spin-on-carbon layer to expose a top of one of the columns of spacer mandrels;
removing the second spin-on-carbon layer, the second hardmask and the second spacer mandrel to form a second gap;
removing the oxide films to leave columns of the spacer mandrels and the gapfill materials on a first etch stop layer on a first oxide layer on a substrate, with exposed portions of the first etch stop layer and exposed portions of the first oxide layer on the substrate;
etching the exposed portions of the first etch stop layer and the first oxide layer and reducing a height of the columns of the spacer mandrels and the gapfill materials to expose portions of the substrate; and
fin etching the exposed portions of the substrate and removing the remaining columns of the spacer mandrels, the gapfill materials, the first etch stop layer and the first oxide layer.

US Pat. No. 10,510,536

METHOD OF DEPOSITING A CO-DOPED POLYSILICON FILM ON A SURFACE OF A SUBSTRATE WITHIN A REACTION CHAMBER

ASM IP Holding B.V., Alm...

1. A method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber, the method comprising:heating the substrate to a deposition temperature of less than 550° C.;
simultaneously contacting the substrate with a silicon precursor, a n-type dopant precursor, and a p-type dopant precursor; and
depositing the co-doped polysilicon film on the surface of the substrate,
wherein the deposited co-doped polysilicon film has a p-type dopant concentration greater than 1×1018/cm3 and an n-type dopant concentration greater than 1×1018/cm3.

US Pat. No. 10,510,533

NANOWIRE FABRICATION METHOD AND STRUCTURE THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a template layer having a predetermined template thickness;
a recess formed in the template layer and having a recess pattern, the recess further having a recess depth smaller than the template thickness and bounded by a bottom surface within the template layer and an upper surface of the semiconductor device;
a semiconductor structure formed in the recess and extending above the recess, the semiconductor structure extending in a substantially vertical direction with respect to the major surface of the substrate, the portion of the semiconductor structure extending above the recess having a generally uniform cross-section corresponding to the recess pattern; and
a pre-layer on the bottom surface of the template layer below the semiconductor structure,
wherein the template layer comprises amorphous materials, and the bottom surface defining the recess comprises an amorphous surface;
wherein the recess depth is substantially uniform and is about 1 nm to about 3 nm; and
wherein a thickness of the pre-layer is about 1 monolayer.

US Pat. No. 10,510,531

METHOD OF FABRICATION OF A SEMICONDUCTOR ELEMENT COMPRISING A HIGHLY RESISTIVE SUBSTRATE

Soitec, Bernin (FR)

1. A method of fabrication of a semiconductor element, the method comprising:applying a step of rapid heat treatment exposing a substrate comprising a base having a resistivity greater than 1000 Ohm·cm and less than 100,000 Ohm·cm, an insulator layer on the base and a surface layer on the insulator layer, to a peak temperature sufficient to deteriorate the resistivity of the base, the base consisting essentially of silicon, silicon with interstitial oxygen, p-type silicon, or p-type silicon with interstitial oxygen; and
after applying the step of rapid heat treatment, applying a curing heat treatment exposing the substrate to a curing temperature between 800° C. and 1250° C. and generating a concentration of holes and, thereafter, cooling the substrate at a cool down rate:
less than 5° C./second when the curing temperature is between 1250° C. and 1150° C.,
less than 20° C./second when the curing temperature is between 1150° C. and 1100° C.; and
less than 50° C./second when the curing temperature is between 1100° C. and 800° C.; and
while cooling the substrate, reducing the concentration of holes to their thermodynamic equilibrium concentration and avoiding freezing the holes in an excessive concentration in the form of hole/oxygen complexes having a negative charge.

US Pat. No. 10,510,530

METHODS FOR FORMING DOPED SILICON OXIDE THIN FILMS

ASM International N.V., ...

1. A method for depositing doped silicon oxide on a substrate in a reaction chamber comprising at least one doped silicon oxide deposition cycle comprising, in order:contacting the substrate with a dopant precursor;
exposing the substrate to a purge gas;
contacting the substrate with a first reactive species;
contacting the substrate with a silicon precursor; and
contacting the substrate with a second reactive species, wherein the second reactive species is formed by generating an oxygen plasma in the reaction chamber.

US Pat. No. 10,510,529

FORMATION OF SIOCN THIN FILMS

ASM IP Holding B.V., Alm...

1. A plasma enhanced atomic layer deposition (PEALD) method of forming a thin film comprising silicon, oxygen and carbon on a substrate that comprises a material that would be oxidized by exposure to oxygen plasma, wherein the PEALD method comprises at least one deposition cycle comprising:contacting a surface of the substrate with a vapor phase silicon precursor to thereby adsorb a silicon species on the surface of the substrate; and
contacting the adsorbed silicon species with at least one reactive species generated by plasma formed from a gas that does not comprise oxygen,
wherein the silicon precursor comprises a silicon atom, an alkoxide group bonded to the silicon atom and a ligand comprising an amino group bonded to the silicon atom through a carbon, and
wherein the substrate is not contacted with a reactive species generated by a plasma from oxygen in the at least one deposition cycle.

US Pat. No. 10,510,528

SUBSTRATE PROCESSING METHOD

SCREEN Holdings Co., Ltd....

1. A substrate processing method comprising:a replacement step of replacing a rinse liquid adhered to a front surface of a substrate with a low surface tension liquid whose surface tension is lower than a surface tension of the rinse liquid; and
a spin dry step of rotating, after completion of the replacement step, the substrate about a predetermined rotation axis to spin off the low surface tension liquid so as to dry the front surface,
wherein the replacement step includes:
a low surface tension liquid supply step of supplying the low surface tension liquid to the front surface while supplying a heating fluid to a rear surface on a side opposite to the front surface; and
a post-heating step of supplying the heating fluid to the rear surface on the side opposite to the front surface of the substrate, in a state in which the supply of the low surface tension liquid to the front surface is stopped, before start of the spin dry step after completion of the low surface tension liquid supply step,
wherein the low surface tension liquid supply step includes a step of discharging the low surface tension liquid from a low surface tension liquid nozzle which is located above the front surface of the substrate,
the spin dry step is performed in a state in which an opposite member is opposite above the front surface of the substrate and
in parallel with the post-heating step, the low surface tension liquid nozzle is retracted from above the substrate, and the opposite member is located above the substrate.

US Pat. No. 10,510,527

SINGLE WAFER CLEANING TOOL WITH H2SO4 RECYCLING

Taiwan Semiconductor Manu...

1. A single wafer cleaning tool, comprising:a processing chamber configured to house a semiconductor substrate having a photoresist residue having metal impurities;
an oxidative treatment unit in communication with the processing chamber by way of a first inlet and configured to apply an oxidative chemical pre-treatment to the semiconductor substrate to remove a part of the photoresist residue having metal impurities in a manner that results in a contaminant remainder;
a SPM cleaning unit in communication with the processing chamber by way of a second inlet configured to apply a sulfuric-peroxide mixture (SPM) cleaning solution to the semiconductor substrate separate from the oxidative chemical pre-treatment to remove the contaminant remainder from the semiconductor substrate as an SPM effluent; and
a recycling unit coupled to the processing chamber and configured to recover sulfuric acid (H2SO4) from the SPM effluent and to provide the recovered H2SO4 to the SPM cleaning unit via a feedback conduit, wherein the recycling unit comprises:
first and second collection tanks;
a first switching element having inputs directly coupled by first and second conduits to outputs of the first and second collection tanks, respectively;
a heating element having an input that is coupled to an output of the first switching element by a first fluid path;
a second switching element having an input that is coupled to an output of the heating element by a second fluid path;
a feedback path extending between a first output of the second switching element and an input of a third switching element, wherein the third switching element has a first output coupled to the first collection tank and a second output coupled to the second collection tank; and
wherein the feedback path further comprises a filter.

US Pat. No. 10,510,524

ION TRAP MASS SPECTROMETRY DEVICE AND MASS SPECTROMETRY METHOD USING SAID DEVICE

SHIMADZU CORPORATION, Ky...

1. A mass spectrometric method using an ion trap mass spectrometer in which an ion of sample origin is captured within an inner space of an ion trap formed by a plurality of electrodes, the ion is dissociated by a predetermined ion dissociation technique, and thereby generated product ions are ejected from the ion trap and detected, the mass spectrometric method comprising:a) an ion selection step in which ions other than a target ion having a specific mass-to-charge ratio are ejected from the ion trap, among ions captured within the ion trap;
b) an ion dissociation-ejection step in which an ion-dissociating operation and an ion-ejecting operation are repeatedly performed multiple times, where the ion-dissociating operation includes dissociating, by the predetermined dissociation technique, the target ion maintained within the ion trap by the ion selection step, and the ion-ejecting operation includes ejecting ions having smaller mass-to-charge ratios than the mass-to-charge ratio of the target ion among the ions captured within the ion trap after the ion-dissociating operation while performing a mass scan in a direction in which the mass-to-charge ratio increases from a low mass-to-charge-ratio side, or in an opposite direction; and
c) a mass spectrum creation step in which a mass spectrum is created based on a result of detection of the ions ejected from the ion trap during the ion-ejecting operation performed multiple times in the ion dissociation-ejection step.

US Pat. No. 10,510,521

INTERACTIVE ANALYSIS OF MASS SPECTROMETRY DATA

Protein Metrics Inc., Cu...

1. A computer-implemented method for dynamically preparing reports from a mass spectrometry data set associated with a molecule of interest, the method comprising:displaying an inspection view component of a user interface, the inspection view component comprising a table window and a spectrum window, the table window comprising a table of values comprising a plurality of mass-to-charge ratio values associated with the molecule of interest, the spectrum window comprising a graph indicating one or more peaks corresponding to mass-to-charge ratios of at least one molecular species associated with the molecule of interest;
receiving, from a user, one or more selections modifying one or more of the table of values and the graph indicating the one or more peaks;
displaying a report view component of the user interface comprising tabs selectable by the user, each of the tabs configured to display all or a subset of information from the modified one or more of the table of values and the graph indicating the one or more peaks of the inspection view component of the user interface;
selecting, in response to a user's tab selection, one of the tabs to display within the report view component of the user interface, wherein the selected tab comprises an active element window configured to display a first subset of pivot functions, a display window configured to display one or more of a report table and a report graph based on the first subset of pivot functions, and a storage window configured to display a second subset of pivot functions that is not displayed in the display window;
moving, in response to a user-input move command, one or more pivot functions between the active element window and the storage window to adjust the one or more of the report table and the report graph displayed in the display window; and
saving the pivot functions contained in the active element window as the first subset of pivot functions associated with the selected tab.

US Pat. No. 10,510,520

ELECTRICALLY CONDUCTIVE, GAS-SEALED, ALUMINUM-TO-ALUMINUM CONNECTION AND METHODS OF MAKING SAME

DOUGLAS ELECTRICAL COMPON...

20. A method of sealing an aluminum tube to an aluminum end cap comprising:i) applying a curable high elongation polymer to at least one of an aluminum tube or an aluminum end cap, each having a first segment and a second segment, wherein, when assembled, the first segments are correspondingly positioned relative to each other, and the second segments are correspondingly positioned relative to each other, the applying being performed such that the second segment of the at least one of the aluminum tube or aluminum end cap contains the high elongation polymer and the first segments are substantially free of the high elongation polymer; and
ii) causing a relative sliding motion between the first segments of the aluminum tube and aluminum end cap to cause galling between the respective first segments, while the respective second segments remain spaced apart from each other, but in contact with the high elongation polymer such that, when the high elongation polymer is cured, a flexible seal will exist between the respective second segments to form a gas-sealed, connection between the aluminum tube and aluminum end cap with a Helium gas leak rate of less than 1×10?8 bar l/s, and the joined first segments form an electrically conductive path between the aluminum tube and aluminum end cap.

US Pat. No. 10,510,519

PLASMA PROCESSING APPARATUS AND DATA ANALYSIS APPARATUS

Hitachi High-Technologies...

1. A plasma processing apparatus comprising:a processing chamber in which plasma processing is carried out on a plurality of samples as a plurality of lots;
a process monitor which acquires respective light emission data of plasma at a plurality of wavelengths of light corresponding to elements of the plasma as analysis targets over a plurality of plasma processing intervals for each plasma processing of each of the lots; and
a data analysis device configured to analyze the light emission data in which the plurality of plasma processing intervals are divided into a plurality of time intervals, wherein
the data analysis device is further configured to:
acquire a correlation data, for each of a plurality of combinations of the respective time intervals and the respective wavelengths, between a respective light emission intensity for the respective wavelength and a number of plasma processing of the samples based on the acquired light emission data, wherein the correlation data includes, for each of the plurality of combinations of the respective time intervals and the respective wavelengths, a respective direction of correlation between the respective light emission intensity for the respective wavelength and the number of plasma processing of the samples,
determine the elements having the respective direction of correlation which match each other among the elements of the plasma, and
identify one of the combinations of the respective time intervals and the respective wavelengths by using the correlation data corresponding to the determined elements as an indicator.

US Pat. No. 10,510,517

CLEANING APPARATUS FOR AN EXHAUST PATH OF A PROCESS REACTION CHAMBER

RETRO-SEMI TECHNOLOGIES, ...

1. A cleaning apparatus installed in an exhaust path of a process reaction chamber, the apparatus comprising:an inflow pipe having an associated gas inlet for receiving exhaust gas from an upstream portion of the exhaust path;
an outflow pipe having an associated gas outlet for expelling exhaust gas from the cleaning apparatus into a downstream portion of the exhaust path;
a connecting pipe fluidly connecting the inflow pipe to the outflow pipe;
a first radio frequency (RF) coil assembly wound around an outer circumferential surface of the inflow pipe and a second RF coil assembly wound around an outer circumferential surface of the outflow pipe;
an RF generator for generating RF power;
a matching network for receiving the RF power from the RF generator and for applying it to one end of each of the first and second RF coil assemblies, a second end of each of the first and second RF coils being connected to ground;
wherein flux lines for each of the first and second coil assemblies, when energized by RF power from the RF generator via the matching network, cause VHF resonance within the respective inflow or outflow pipe, thereby forming plasma within the exhaust gas flowing therethrough, the plasma forming free radicals from the exhaust gas for cleaning a portion of the exhaust path of the process reaction chamber downstream of the cleaning apparatus, and
wherein one or both of the inflow pipe and the outflow pipe is configured so that a diameter (r1) of an inlet side inner wall is formed smaller than a diameter (r2) of a central portion of the inflow or outflow pipe, and an outlet side inner wall has a tapered shape that gradually slopes inward toward the outlet.

US Pat. No. 10,510,516

MOVING FOCUS RING FOR PLASMA ETCHER

Taiwan Semiconductor Manu...

1. A method comprising:placing a wafer within a plasma chamber;
etching a first layer of the wafer to form a recess in the first layer using a first plasma process, wherein the first layer is a single layer, and the recess exposes first sidewalls of the first layer; and
moving a focus ring within the plasma chamber from a first vertical position relative to the wafer to a second vertical position relative to the wafer during the first plasma process, wherein the first vertical position and the second vertical position are different plasma etch positions, the first vertical position corresponds to a first etch rate for the first plasma process, and the second vertical position corresponds to a second etch rate for the first plasma process different from the first etch rate, wherein moving the focus ring comprises moving part of a focus ring holder that supports the focus ring, wherein moving the focus ring during the first plasma process produces a non-liner sidewall profile for the first sidewalls of the first layer, wherein the first sidewalls of the first layer comprises a first portion and a second portion underlying the first portion, wherein a first distance between first opposing sidewalls of the first portion decreases continuously along a first direction from a top of the recess toward a bottom of the recess, and a second distance between second opposing sidewalls of the second portion increases continuously along the first direction.

US Pat. No. 10,510,515

PROCESSING TOOL WITH ELECTRICALLY SWITCHED ELECTRODE ASSEMBLY

Applied Materials, Inc., ...

1. A plasma reactor comprising:a chamber body having an interior space that provides a plasma chamber;
a gas distributor to deliver a processing gas to the plasma chamber;
a pump coupled to the plasma chamber to evacuate the chamber;
a workpiece support to hold a workpiece;
an intra-chamber electrode assembly comprising a plurality of filaments extending laterally through the plasma chamber between a ceiling of the plasma chamber and the workpiece support, each filament including a conductor surrounded by a cylindrical insulating shell, wherein the plurality of filaments includes a first multiplicity of filaments and a second multiplicity of filaments arranged in an alternating pattern with the first multiplicity of filaments,
a first bus coupled to the first multiplicity of filaments and a second bus coupled to the second multiplicity of filaments;
an RF power source to apply an RF signal the intra-chamber electrode assembly; and
at least one RF switch configured to controllably electrically couple and decouple the first bus from one of i) ground, ii) the RF power source, or iii) the second bus.

US Pat. No. 10,510,514

GAS SUPPLY MECHANISM AND SEMICONDUCTOR MANUFACTURING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A gas supply mechanism for supplying a gas to a semiconductor manufacturing apparatus, comprising:a pipe connecting a gas source and the semiconductor manufacturing apparatus; and
a valve provided on the pipe, wherein
the valve includes
a plate rotatable about an axis, the axis extending in a plate thickness direction, and
a housing provided along the plate without contacting the plate to accommodate the plate, the housing providing a gas supply path along with the pipe,
a through hole is formed in the plate, the through hole penetrating the plate at a position on a circle which extends around the axis and intersects the gas supply path, and
the through hole is configured to move, by changing a rotation angle of the plate, between a first position, which overlaps with the gas supply path when viewed from a direction along the axis, and a second position, which does not overlap with the gas supply path when viewed from a direction along the axis.

US Pat. No. 10,510,513

PLASMA PROCESSING DEVICE AND HIGH-FREQUENCY GENERATOR

TOKYO ELECTRON LIMITED, ...

1. A plasma processing device which processes an object to be processed using plasma, the plasma processing device comprising:a processing container configured to perform a processing on the object by the plasma therein; and
a plasma generator including a high-frequency generator disposed outside the processing container to generate high-frequency waves, and the plasma generator being configured to generate the plasma in the processing container using the high-frequency waves generated by the high-frequency generator,
wherein the high-frequency generator includes a first high-frequency oscillator configured to generate the high-frequency waves and a branch circuit configured to inject a signal into the first high-frequency oscillator, wherein the first high frequency oscillator is a magnetron,
the branch circuit comprises a second high-frequency oscillator which is configured to detect a fundamental frequency of the high-frequency waves generated by the first high-frequency oscillator and to generate, based on the fundamental frequency of the high-frequency waves, the signal having a frequency which is the same as the fundamental frequency generated by the first high-frequency oscillator and having reduced different frequency components, and wherein the branch circuit injects the signal generated by the second high-frequency oscillator into the first high-frequency oscillator through a first band-pass filter,
wherein the fundamental frequency of the high-frequency waves is not changed after the branch circuit injects the signal generated by the second high-frequency oscillator into the first high-frequency oscillator.

US Pat. No. 10,510,509

EDGE DETECTION SYSTEM

Fractilia, LLC, Austin, ...

1. A computer program product in a computer-readable medium for performing edge detection, the computer program product in a computer-readable medium comprising instructions, which, when executed, cause a processor to perform:loading a first image of a pattern structure exhibiting a predetermined feature;
generating measured linescan information describing the pattern structure, wherein the measured linescan information includes image noise;
applying the measured linescan information to an inverse linescan model that relates the measured linescan information to feature geometry information; and
determining, from the inverse linescan model, feature edge positions of the predetermined feature that correspond to the measured linescan information.

US Pat. No. 10,510,508

CHARGED PARTICLE BEAM APPARATUS

HITACHI HIGH-TECH SCIENCE...

1. A charged particle beam apparatus comprising:a sample stage on which a sample is placed;
a sample chamber receiving the sample stage therein;
a charged particle beam column irradiating the sample with a charged particle beam;
a displacement member including an open/close portion displaceable between an insertion position, which is between a beam emitting end portion of the charged particle beam column and the sample stage so as to block an opening of the beam emitting end portion, and a withdrawal position which is away from the insertion position, and a contact portion provided at a contact position capable of contacting the sample before the beam emitting end portion during operation of the sample stage and configured so as not to interfere with the charged particle beam from the charged particle beam column with which the sample is irradiated;
driving means for displacing the displacement member; and
detecting means for detecting whether the sample is in contact with the contact portion.

US Pat. No. 10,510,507

FUSE UNIT

YAZAKI CORPORATION, Mina...

1. A fuse unit comprising:a fusible link connected to a battery terminal and including a fusible element that melts when an overcurrent flows through the fusible link;
a holding mechanism that includes a base portion disposed between a post standing surface of a battery housing and the battery terminal in a state where the battery terminal is fastened to a battery post provided in a recess on the post standing surface, and a holding portion that is integrally formed with the base portion, that is located between the fusible link and the post standing surface, and that holds the fusible link above the post standing surface; and
a locking mechanism that locks the holding mechanism onto the post standing surface, wherein
the holding portion has a side wall on a base portion side extending toward a lower side in a vertical direction in a manner corresponding to a difference in level formed by the recess on the post standing surface and is connected to the base portion at a lower end of the side wall.

US Pat. No. 10,510,506

NARROW PROFILE CIRCUIT BREAKER WITH ARC INTERRUPTION

Carling Technologies, Inc...

1. A circuit breaker comprising:a housing within which components of the circuit breaker are disposed, the housing having an outwardly facing exposed surface;
a line terminal adapted to be electrically connected to a source of electrical power;
a load terminal adapted to be electrically connected to at least one load;
a stationary contact positioned within the housing;
a moveable contact arm assembly having a generally longitudinal axis and a moveable contact positioned thereon, the moveable contact arm assembly being moveable between a closed position in which the moveable contact and the stationary contact are in physical contact and the line terminal and the load terminal are in electrical communication via at least the moveable contact, the stationary contact and a conductive strap, and an open position in which the moveable contact and the stationary contact are out of physical contact and the line terminal and the load terminal are out of electrical communication;
an overcurrent tripping device operably coupled to the moveable contact arm assembly via a linkage assembly and adapted to move the moveable contact arm assembly to the open position upon detection of an overcurrent situation;
a resetting mechanism, actuation of which is adapted to, when the moveable contact arm assembly is in the open position, move the moveable contact arm assembly to the closed position, the resetting mechanism extending from, or being accessible through, the outwardly facing exposed surface of the housing; and
an arc splitter adapted to quench an arc created between the stationary contact and the moveable contact as the stationary contact and the moveable contact are moveable into and/or out of contact with one another;
wherein the outwardly facing exposed surface of the housing generally defines an exposed surface plane, and wherein the longitudinal axis of the moveable contact arm assembly is generally orthogonal with respect to the exposed surface plane when the moveable contact arm assembly is in the closed position; and
wherein the conductive strap lies in a conductive strap plane, wherein the moveable contact arm assembly moves in a contact arm plane as it moves between the open and the closed position, and wherein the conductive strap plane and the contact arm plane are parallel to, but spaced apart from, one another.

US Pat. No. 10,510,505

FUSE UNIT AND METHOD OF MANUFACTURING FUSE UNIT

PACIFIC ENGINEERING CORPO...

3. A fuse unit which comprises a bus bar comprising a battery terminal, a fuse connection terminal, and an external connection terminal, wherein the bus bar and a resin covering body are integrated, the fuse connection terminal comprising an input side tuning fork terminal connected to the battery terminal and an output side tuning fork terminal connected to the external connection terminal, the input side tuning fork terminal and the output side tuning fork terminal once connected via a joining portion such that they face each other, the resin covering body comprising a cutting window which is provided between a base end portion of the input side tuning fork terminal and a base end portion of the output side tuning fork terminal and such that the cutting window only exposes the joining portion to the outside, and the joining portion having been cut and removed so as to separate the input side tuning fork terminal and the output side tuning fork terminal.

US Pat. No. 10,510,499

SMD SWITCH AND TOUCHPAD MODULE AND COMPUTING DEVICE USING SAME

PRIMAX ELECTRONICS LTD., ...

1. A touchpad module, comprising:a circuit board comprising at least one circuit board contact part; and
a surface mount device switch comprising:
a pedestal located under the circuit board, and comprising a first conducting part, a second conducting part and at least one pedestal contact part, wherein the at least one pedestal contact part is electrically connected with the at least one circuit board contact part;
a metal dome; and
at least one conductive buffering sheet arranged between the metal dome and the pedestal, and contacted with the first conducting part and/or the second conducting part,
wherein when the circuit board is pressed down and the surface mount device switch is moved downwardly to push a triggering part, the metal dome is subjected to deformation and contacted with the at least one conductive buffering sheet, so that the first conducting part and the second conducting part are electrically connected with each other.

US Pat. No. 10,510,498

TRAVEL SWITCH WITH HIGH-SAFETY LEVER STRUCTURE

Albert Chi Man Ao, Chino...

1. A travel switch with a high-safety lever structure, comprising:a travel adjustment device;
a transmission device;
a lever-structure electric-connection switch assembly;
an insulation assembly; and
a rivet fixing assembly;
wherein the lever-structure electric-connection switch assembly comprises a dual-energy-storage-reed structure and a stationary contact piece, wherein the dual-energy-storage-reed structure comprises a stationary reed and a moving reed, wherein one end of the moving reed and the stationary reed are arranged in intervals, and another end of the moving reed is fixedly connected with the stationary reed, wherein two sides of the moving reed are respectively provided with an energy storage reed, wherein one end of the energy storage reed is connected with a main body of the moving reed, and another end of the energy storage reed is provided with an open end, wherein two sides of the stationary reed are respectively provided with an energy storage reed positioning hook, and the open end of the energy storage reed is hooked with the energy storage reed positioning hook in a matched mode, wherein the moving reed is provided with a moving contact, and the stationary contact piece is provided with a stationary contact, wherein a moving contact limiting block is arranged on the stationary reed, wherein an upper portion of the moving contact is correspondingly connected with the stationary contact, and a lower portion of the moving contact is arranged to correspond to the moving contact limiting block; and
wherein the two sides of the stationary reed are respectively provided with a first reinforcing rib, wherein a positioning notch is formed in a tail portion of the stationary reed, wherein the two sides of the moving reed are respectively provided with a second reinforcing rib, wherein a positioning convex piece is arranged at an end portion of one end of the moving reed, wherein the positioning convex piece of the moving reed is arranged to correspond to the positioning notch of the stationary reed.

US Pat. No. 10,510,493

CORE-SHELL COMPOSITE, METHOD FOR PRODUCING THE SAME, ELECTRODE MATERIAL, CATALYST, ELECTRODE, SECONDARY BATTERY, AND ELECTRIC DOUBLE-LAYER CAPACITOR

TPR CO., LTD., Tokyo (JP...

1. A core-shell composite comprising a core formed from a carbon porous body having a large number of pores from an interior through to a surface, and a shell layer formed from conductive polymer nanorods that extend outward from cavities of pores on a surface of the core,wherein the conductive polymer nanorods narrow with increasing distance from the pores.

US Pat. No. 10,510,490

MULTILAYER CERAMIC ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic electronic component, comprising:a ceramic body including a dielectric layer and first and second internal electrodes stacked to be alternately exposed from one end surface and another end surface in a length direction with the dielectric layer disposed therebetween; and
first and second external electrodes disposed on the one end surface and the another end surface of the ceramic body and connected to the first and second internal electrodes, respectively,
wherein the ceramic body includes an area of overlap in a thickness direction of the first and second internal electrodes, and margin regions disposed on one side and another side in a width direction of the area of overlap, respectively,
the margin regions in the width direction include a phosphoric acid-based second phase, and
the phosphoric acid-based second phase has an acicular shape or a rhomboid shape.

US Pat. No. 10,510,489

MOUNTING STRUCTURE AND MULTILAYER CAPACITOR BUILT-IN SUBSTRATE

MURATA MANUFACTURING CO.,...

1. A mounting structure comprising:a circuit board including one principal surface on which a multilayer capacitor is mounted; wherein
the circuit board includes a first insulating layer, and a second insulating layer having a Young's modulus smaller than a Young's modulus of the first insulating layer;
the second insulating layer is disposed closer to the one principal surface on which the multilayer capacitor is mounted than the first insulating layer;
a land is provided on the one principal surface of the circuit board; and
the multilayer capacitor is mounted on the land on the one principal surface.

US Pat. No. 10,510,487

MULTI-LAYER CERAMIC ELECTRONIC COMPONENT AND METHOD OF PRODUCING THE SAME

TAIYO YUDEN CO., LTD., T...

1. A multi-layer ceramic electronic component, comprising:a multi-layer chip including
ceramic layers laminated in a first direction,
internal electrodes disposed between the ceramic layers,
a plurality of pores respectively formed at end portions of the internal electrodes in a second direction orthogonal to the first direction, and
a side surface that is orthogonal to the second direction and that includes a first area and a second area; and
a side margin that covers the side surface of the multi-layer chip,
wherein the plurality of pores include a first pore corresponding to the first area of the side surface and a second pore corresponding to the second area of the side surface,
wherein the second pore has a larger dimension than the first pore,
wherein each pore of the plurality of pores includes an open space between the side margin and the end portion of the respective internal electrode at which it is formed, and
wherein the first area and the second area each form a predetermined pattern.

US Pat. No. 10,510,485

HEAT TRANSFER IN MAGNETIC ASSEMBLIES

Hamilton Sundstrand Corpo...

1. A method of manufacturing a magnetic assembly comprising:determining an outer contour of a winding by three-dimensionally scanning the outer contour of the winding;
forming a contoured interior surface on a housing; and
assembling the winding into the housing such that the interior surface of the housing conforms to the winding to facilitate heat transfer between the winding and the housing.

US Pat. No. 10,510,484

FORMING AN ELECTRICAL COIL DEVICE BY CUTTING A STRIP CONDUCTOR WINDING INTO AT LEAST TWO PARTIAL COILS

SIEMENS AKTIENGESELLSCHAF...

1. A method for producing an electrical coil, the method comprising:winding a strip conductor into a coil winding having a stack of strip conductor layers,
wherein winding the strip conductor comprises winding a first portion of the strip conductor into the coil winding, but leaving at least one of an internal end piece or an external end piece of the strip conductor as an unwound projection, and
dividing the coil winding into at least two partial coils by performing at least one cut through the stack of strip conductor layers while the layers are wound in the coil winding,
wherein after the at least one cut through the stack of strip conductor layers, the strip conductor remains connected at end regions of the strip conductor, to thereby define the electrical coil including a contiguous loop shape of the strip conductor that includes the at least two partial coils and the connected end regions of the strip conductor.

US Pat. No. 10,510,483

PRODUCTION METHOD FOR R-T-B SINTERED MAGNET

HITACHI METALS, LTD., To...

1. A method for producing a sintered R-T-B based magnet, comprising:a step of providing a sintered R-T-B based magnet, where R is one or more rare-earth elements, T is one or more transition metal elements, and B is boron or is boron and carbon;
a step of applying onto a surface of the sintered R-T-B based magnet a layer of an RLM alloy powder (where RL is Nd and/or Pr; M is one or more elements selected from the group consisting of Cu, Fe, Ga, Co, Ni and Al), the layer of the RLM powder being at least one particle thick or greater, and then applying a layer of an RH compound powder (where RH is Dy and/or Tb; and an RH compound of the RH compound powder is at least one selected from the group consisting of an RH fluoride, an RH oxide, and an RH oxyfluoride) to the layer of the RLM powder; and
a step of performing a heat treatment at a sintering temperature of the sintered R-T-B based magnet or lower, wherein
the RLM alloy powder contains RL in an amount of 50 at % or more, and a melting point of the RLM alloy powder is equal to or less than a temperature of the heat treatment; and
the heat treatment is performed while the RLM alloy powder and the RH compound powder are present on the surface of the sintered R-T-B based magnet at a mass ratio of RLM alloy powder: RH compound powder=9.6:0.4 to 5:5.

US Pat. No. 10,510,475

INDUCTION COMPONENT

1. An induction component, comprisinga magnet core in the form of a closed ring comprising
a first section of the closed ring and
a second section of the dosed ring,
wherein the first section is an opposite side of the closed ring from the second section,
a first coil device on the first section and a second coil device on the second section, wherein each coil device includes
a plurality of coils, each coil including a plurality of turns, a winding start and an end winding, wherein the plurality of coils includes
a starter coil having a winding start guided outwards and exclusively connected to a starting solder pad and
an ending coil having an end winding guided outwards and exclusively connected to an ending solder pad and
wherein the end winding of at least one coil in the plurality of coils and the winding start of at least one other coil in the plurality of coils are guided outwards and both connected to an intermediary solder pad.

US Pat. No. 10,510,473

SWITCHGEAR

MITSUBISHI ELECTRIC CORPO...

1. A switchgear comprising:a closing coil that drives a movable element to the close contact side of said switchgear in an electromagnetic operating device;
a closing capacitor that supplies electrical energy to said closing coil;
a closing control section which is connected between said closing coil and said closing capacitor, and performs control of charging said closing capacitor and of energizing said closing coil;
an opening coil that drives said movable element to the open contact side of said switchgear in said electromagnetic operating device;
an opening capacitor that supplies electrical energy to said opening coil;
an opening control section which is connected between said opening coil and said opening capacitor, and performs control of charging said opening capacitor and of energizing said opening coil;
a first interlock circuit that energizes said opening control section;
a second opening coil that drives said movable element to the open contact side of said switchgear in said electromagnetic operating device;
a second opening capacitor that supplies electrical energy to said second opening coil;
a second opening control section which is connected between said second opening coil and said second opening capacitor, and performs control of charging said second opening capacitor and of energizing said second opening coil; and
a second interlock circuit that energizes said second opening control section,
wherein either said opening coil or said second opening coil is enabled to drive said movable element to the open contact side of said switchgear, and
wherein reception, by said closing control section, of a command to activate the closing coil is blocked on the basis of a signal showing that said second opening control section is energizing said second opening coil.

US Pat. No. 10,510,472

COIL ACTUATOR FOR LV OR MV APPLICATIONS

ABB S.p.A., Milan (IT)

1. A coil actuator for low and medium voltage applications comprising:an electromagnet operatively associated with a movable plunger to actuate said movable plunger;
a power & control unit electrically connected with said electromagnet to feed said electromagnet and control the operation of said electromagnet;
first and second input terminals (T1, T2) electrically connected with said power & control unit, wherein an input voltage (VIN) is applied between said first and second input terminals during the operation of said coil actuator; and
a third input terminal (T3) electrically connected with said power & control unit, said third input terminal being adapted to be in a first operating condition (A) of being electrically floating, said first operating condition corresponding to normal control conditions (NDC) for the operation of said electromagnet, or in a second operating condition (B) of being electrically coupled with one of said first and second input terminals (T1, T2), said second operating condition corresponding to overriding control conditions (ODC) for the operation of said electromagnet,
wherein said power & control unit is adapted to control the operation of said electromagnet according to said normal control conditions or said overriding control conditions depending on the operating condition (A, B) of said third input terminal.

US Pat. No. 10,510,470

DIFFUSION BARRIERS FOR METALLIC SUPERCONDUCTING WIRES

H.C. STARCK INC., Newton...

1. A superconducting wire possessing diffusion resistance and mechanical strength, the superconducting wire comprising:an outer wire matrix comprising Cu;
disposed within the wire matrix, a diffusion barrier comprising a Ta—W alloy containing 0.2%-10% W; and
a plurality of composite filaments surrounded by the diffusion barrier and separated from the outer wire matrix by the diffusion barrier,
wherein:
each composite filament comprises (i) a plurality of Nb-based monofilaments and (ii) a cladding comprising Cu surrounding the plurality of monofilaments,
the diffusion barrier occupies 2%-15% of a cross-sectional area of the superconducting wire, and
the diffusion barrier extends through an axial dimension of the superconducting wire.

US Pat. No. 10,510,468

LAN CABLE

Hitachi Metals, Ltd., To...

1. A LAN cable comprising:a sheath;
an electrical wire accommodated in the sheath and comprising a conductor and an insulating body covering the conductor; and
an intermediate layer having a mass reduction rate at 500° C. of less than or equal to 10% by mass and a mass reduction rate at 600° C. of less than or equal to 50% by mass, and located between the sheath and the electrical wire,
wherein the insulating body comprises polyethylene having a dielectric constant of smaller than or equal to 2.5,
wherein the sheath comprises a polyolefin-based polymer and a flame retardant,
wherein a content of the flame retardant in the sheath is greater than or equal to 150 parts by mass with respect to 100 parts by mass of the polyolefin-based polymer,
wherein the intermediate layer comprises polyimide, and
wherein the electrical wire is arranged at a center of the LAN cable and is coated with an aluminum laminate PET tape, a copper braid, the intermediate layer, and the sheath in this order radially outward.

US Pat. No. 10,510,465

METHODS AND SYSTEMS FOR SECURELY ACCESSING AND MANAGING AGGREGATED SUBMARINE CABLE SYSTEM INFORMATION

Global Broadband Solution...

1. An architecture for providing end users with the ability to securely access and manage aggregated submarine cable (SC) system information, comprising:an information management sub-system;
an SC information storage sub-system configured to allow display of a plurality of SC System information as distinct images, where each image represent a type of SC System information, and wherein the information management sub-system and the SC information storage sub-system are further operable to generate an audit signal or message each time a communication occurs or a connection is established between an end-user device and the information management sub-system and the SC information storage sub-system, respectively;
an SC System administrative sub-system; a multi-factor authentication (MFA) sub-system operable to enable completion of multi-factor authentication compliant with National institutes of Standard And Technology (NIST) SP 800-171 and US. Government Defense Federal Acquisition Regulations requirements to access the aggregated, SC system information; and
a remote data monitoring and protection sub-system.

US Pat. No. 10,510,455

MULTI-MODULAR POWER PLANT WITH OFF-GRID POWER SOURCE

NUSCALE POWER, LLC, Port...

1. A multi-modular power plant, comprising:a plurality of on-site nuclear power modules configured to generate a power plant output, wherein one or more of the nuclear power modules are designated as service modules which are configured to generate a first portion of the power plant output, and wherein a remainder of the nuclear power modules are configured to generate a second portion of the power plant output;
a number of power plant systems which are configured to operate using electricity associated with a house load of the power plant, wherein the first portion of the power plant output is equal to or greater than the house load; and
a switchyard configured to electrically connect the power plant to a distributed electrical grid and configured to electrically connect the power plant to a dedicated electrical grid, wherein the distributed electrical grid is configured to service a plurality of geographically distributed consumers and the dedicated electrical grid is configured to provide electricity to a dedicated service load, wherein the switchyard is configured to apply the second portion of the power plant output to the distributed electrical grid, and wherein the switchyard is further configured to apply at least part of the first portion of the power plant output to the power plant systems during a loss of power from the distributed electrical grid.

US Pat. No. 10,510,451

BASE PLATE MOUNTED CORE COMPONENTS FOR RELIABLE ROD ASSEMBLY AND RAPID FIELD DISASSEMBLY

Westinghouse Electric Com...

1. A mounting assembly for a nuclear core component that is secured to a base plate with the base plate having a given thickness that extends from one side to a second side, comprising;a hole extending through the base plate in an axial direction from the one side to and through the second side;
a stem on the nuclear core component, the stem being configured to extend into and through the hole and having a length greater than the given thickness;
a. seat on the stem, spaced from a distal end of the stem, the seat having a laterally extending seating surface that rests on the one side when the stem is inserted into and through the hole and prevents the stem from being inserted further;
projections extending radially outward from the stem, near a distal end of the stem and circumferentially spaced around the stem;
axially extending grooves in a wall surface of the hole that match up with the orientation of the projections on the stem, configured so the stem with the projections can pass through the hole from one side to the second side with at least a portion of the projections passing through the grooves;
slots on a surface of the second side around a circumference of the hole that extend through a wall of the hole, the slots having the same orientation as the projections and are circumferentially spaced from the grooves; and
a spring supported between the seat and the one side, with the length of the stem configured to be sufficiently long, so with the spring fully compressed, the projections extend through the hole to and through the second side and the stem can rotate to seat the projections in the slots when the spring is at least partially relaxed.

US Pat. No. 10,510,450

HEAT PIPE MOLTEN SALT FAST REACTOR WITH STAGNANT LIQUID CORE

Westinghouse Electric Com...

13. A nuclear reactor for operative connection to a power conversion system, the reactor comprising:a containment vessel;
a reactor core housed within the containment vessel;
a neutron reflector spaced froze the containment vessel and positioned between the core and the containment vessel;
a livid fuel comprised of a nuclear fission material dissolved in a molten salt enclosed within the core;
a plurality of heat transfer pipes, each pipe having a first end and a second end, the first end being positioned within the reactor core for absorbing heat from the fuel;
a heat exchanger external to the containment vessel, the heat exchanger receiving the second end of each heat transfer pipe for transferring heat from the core to the heat exchanger; and
at least three reactor shut down systems comprising a first shut down system, a second shut down system, and a third shut down system, the first shut down system comprising:
a rotatable member mechanism comprising:
a plurality of rotatable members positioned evenly within the neutron reflector, each rotatable member having a neutron absorber section and a non-absorber section; and,
a rotating drive mechanism operatively connected to each rotatable member for rotating the rotatable member to move the neutron absorber section to one of a first position facing the core and a second position facing away from the core;
the second shut down s stem comprising:
a melt-plug mechanism comprising:
an opening in the containment vessel;
a chamber fluidly connected to the opening in the containment vessel;
a first melt plug, to plug the opening in the containment vessel;
the first melt plug being made of a material that melts at a predetermined melting temperature deemed to be indicative of unsafe temperature conditions within the reactor core; and the third shut down system comprising:
a central axis extending through the core and a neutron absorber activation system comprising
a hollow tube defining a cavity and being positioned coaxially to the central axis and extending from an area above the core into the core;
a gate separating a first portion of the hollow tube above the core from a second portion of the hollow tube within the core;
a neutron absorber material housed in an unactivated position within the first portion of the hollow tube;
an activation rod operatively connected to the gate;
a release member for releasing the actuation rod from the unactivated position to move to an activated position, wherein in the activated position, the actuation rod opens the gate to release the neutron absorber material into the cavity within the second portion of the hollow tube in proximity to the fuel to absorb neutrons from the fuel sufficient to shut down the reactor.

US Pat. No. 10,510,449

EXPERT OPINION CROWDSOURCING

MERGE HEALTHCARE SOLUTION...

1. A computer-implemented method comprising:under direction of one or more hardware processors configured with specific software instructions,
receiving a medical image series including one or more medical images;
providing a user interface to a user, the user interface configured to allow the user to set preferences for selection of one or more reviewers of the medical image series, the preferences including:
first preferences identifying a first medical specialty and a first minimum quantity of reviewers having the first medical specialty;
second preferences identifying a second medical specialty and a second minimum quantity of reviewers having the second medical specialty; and
third preferences indicating a criteria regarding one or more of:
whether reviewers offer availability to be contacted directly by the user;
whether reviewers offer availability to review the medical image series as part of at least one of: a legal investigation, an insurance investigation, a consultation with a doctor, or a request of a patient;
a minimum and/or maximum quantity of reviewers to be selected to review the medical image series;
a minimum and/or maximum quantity of reviewers permitted to provide review information; and/or
a minimum average user feedback required for reviewers to be selected for review of the medical image series;
receiving, via the internet, the preferences provided by the user;
automatically analyzing the medical image series, at least in part based on natural language processing, to determine one or more characteristics of the medical image series;
accessing a reviewer database storing a plurality of reviewer records associated with a corresponding plurality of reviewers, each of the reviewer records indicating one or more characteristics of the corresponding reviewer;
comparing the preferences set by the user and the one or more characteristics of the medical image series to respective reviewer records in the reviewer database;
selecting, based on said comparison of the first preferences and the one or more characteristics of the medical image series to respective reviewer records, a first subset of reviewers including at least the first quantity of reviewers each having the first medical specialty;
selecting, based on said comparison of the second preferences and the one or more characteristics of the medical image series to respective reviewer records, a second subset of reviewers including at least the second quantity of reviewers each having the second medical specialty;
selecting, based on said comparison of the third preferences and the one or more characteristics of the medical image series to respective reviewer records, a third subset of reviewers including one or more reviewers having characteristics matching the third preferences;
automatically analyzing the medical image series to identify personally identifiable information in the medical image series;
automatically anonymizing the medical image series by removing or obscuring the personally identifiable information from the medical image series;
providing a notice, via a computerized user interface, to the selected first, second, and third subsets of reviewers indicating availability of the medical image series for review, the medical image series having been anonymized, wherein an identity of the user is also anonymized such that the first, second, and third subsets of reviewers cannot determine the identity of the user from the notice indicating availability of the medical image series or from the medical image series;
receiving separate medical reports from each reviewer of the first, second, and third subsets of reviewers;
anonymizing identities of each reviewer of the first, second, and third subsets of reviewers such that receivers of the medical reports cannot determine the identities of the reviewers of the first, second, and third subsets of reviewers from the medical reports;
providing, via a computerized user interface, the medical reports to a plurality of rating entities, the medical reports having been anonymized;
receiving, via a computerized user interface, from each of the rating entities, a separate rating for each of the medical reports, the ratings indicating accuracy of respective medical reports;
for each reviewer of the first, second, and third subsets:
compiling ratings of the reviewer from the plurality of rating entities; and
determining an overall rating of the reviewer;
generating a composite report comprising information on each of the medical reports from the first, second, and third subsets of reviewers, wherein the composite report indicates one of the medical reports associated with a highest overall rating and include one of:
the medical reports from each of the first, second, and third subsets of reviewers, the medical reports having been anonymized; or
summaries of at least some of the medical reports from the first, second, or third subsets of reviewers, the medical reports having been anonymized;
providing the composite report to the user;
receiving a request from the user to contact a first reviewer associated with a first medical report, the first medical report having been anonymized;
automatically determining an identity of the first reviewer;
requesting authorization from the first reviewer to provide the identity of the first reviewer to the user; and
in response to receiving authorization from the first reviewer to provide the identity of the first reviewer to the user, providing the identity of the first reviewer to the user.

US Pat. No. 10,510,442

CABINET FOR DISPENSING ITEMS

Peacock Law P.C., Albuqu...

1. A method of regulating, controlling and distributing products inside of a store comprising:providing a kiosk having a user interface for receiving identification information from a user;
prompting the user to request access to a prescribed regulated product;
the kiosk directing communications between a user and a healthcare professional authorized to write prescriptions;
delivering a quantity of the regulated product to the user; and
configuring the kiosk to also function as a self-checkout register for non-regulated store products.

US Pat. No. 10,510,441

DISTRIBUTED SYSTEMS FOR SECURE STORAGE AND RETRIEVAL OF ENCRYPTED BIOLOGICAL SPECIMEN DATA

Global Specimen Solutions...

1. A distributed system for secure storage and retrieval of encrypted biological specimen data comprising:a submission device client operable to:
send, to a patient record server device, a patient record; and
receive, from the patient record server device, a confirmation of receipt of the patient record; and
the patient record server device comprising:
a first processor and first memory, the patient record server device operable to:
create a patient blockchain that is empty at the start of a clinical trial, the patient blockchain corresponding to a patient enrolled in the clinical trial;
receive, from the submission device client, the patient record;
send, to the submission device client, the confirmation of receipt of the patient record;
receive, from a member device client, patient profile information;
determine search results based on the patient profile information;
send, to the member device client, information indicating the search results;
send, to the member device client, the search results based on the information indicating the search results;
update the patient blockchain during the clinical trial by adding blocks in a linear manner;
broadcast availability of the patient blockchain as updated during the clinical trial to network members at a conclusion of the clinical trial; and
update the patient blockchain with a record of third party access to a physical specimen corresponding to the patient blockchain; and
wherein the member device client is operable to:
send, to the patient record server device, the patient profile information;
receive, from the patient record server device, the information indicating the search results based on the patient profile information; and
receive the search results based on the information indicating the search results.

US Pat. No. 10,510,440

METHOD AND APPARATUS FOR IDENTIFYING MATCHING RECORD CANDIDATES

CHANGE HEALTHCARE HOLDING...

1. A method implemented by a health information infrastructure, the method comprising:receiving, via a communication interface, a plurality of records, each record having a plurality of demographic attributes associated with an individual, wherein receiving the plurality of records comprises receiving only a portion of a plurality of patient records created by one or more healthcare facilities by receiving, from the one or more healthcare facilities for each of the plurality of patient records created by the one or more healthcare facilities, information defining the demographic attributes associated with the individual, but not receiving information associated with encounters of the individual with a healthcare facility and not receiving documents included in the patient record;
for each record, determining, with processing circuitry, a digest by determining a fuzzy representation of one or more of the plurality of demographic attributes for the respective individual and combining by concatenating into a single string representations of one or more of the plurality of demographic attributes associated with the respective individual including the fuzzy representation of one or more of the plurality of demographic attributes associated with the respective individual;
receiving a query relating to a record for a person and demographic attributes associated with the person;
determining a digest based upon the demographic attributes associated with the person who is a subject of the query, wherein determining the digest comprises determining a fuzzy representation of one or more demographic attributes of the person who is the subject of the query and combining by concatenating into a single string representations of one or more of the demographic attributes of the person who is the subject of the query including the fuzzy representation of one or more demographic attributes of the person who is the subject of the query;
in response to the query, identifying one or more records that are associated with respective individuals who are candidates to match the person based upon a comparison of representations of the digests of the records and a representation of the digest of the person;
for each record that was identified and, as a result, for only a subset of the plurality of records, determining a confidence score by comparing the plurality of demographic attributes associated with the respective individuals to corresponding demographic attributes of the person;
identifying one or more records that are associated with respective individuals who match the person based upon the confidence scores; and
causing at least some of the one or more records that were identified based upon the confidence scores to be associated with respective individuals who are candidates to match the person to be provided via the communication interface.

US Pat. No. 10,510,437

METHOD FOR CREATING AND USING REGISTRY OF CLINICAL TRIAL PARTICIPANTS

Verified Clinical Trials,...

1. A method of screening participants for a clinical trial, including the steps of:a research site electronically obtaining consent from a prospective participant when applying for a clinical trial to collect and use identifying information chosen from the group consisting of a biometric sample, personal information, physical attributes, and combinations thereof;
obtaining the identifying information from the prospective participant and storing the identifying information on a database on non-transitory computer readable media;
accessing from a unique identifier code generator the identifying information on the database and generating a unique identifier code based on the identifying information and a unique biometric sample profile of the prospective participant as a unique digital fingerprint and storing the unique identifier code on the database on non-transitory computer readable media;
accessing a screening mechanism in electronic communication with the database and other existing databases and pulling all data on the databases regarding the identifying information, unique identifier code, and past clinical study history and unifying the data further supplementing the unique digital fingerprint to perform a screen, thereby preventing unreliable data in clinical trials and preventing health risks to the prospective participant;
the screening mechanism accessing the databases and screening the participant for the clinical trial based on the unique digital fingerprint comprising the unique identifier code, identifying information, and participant information regarding their history of clinical trials and searching for a match with another participant in the databases to prevent duplicate enrollment in the clinical trial, wherein the screening mechanism first searches the databases for a match of unique identifier code, and if no match occurs the screening mechanism searches the databases for a match with all identifying information and participant information, and if no match occurs, the screening mechanism searches the databases for a match with a subset of the unique identifier code, identifying information, and participant information, and wherein a match results in a verification failure and indicates an ineligible participant;
the screening mechanism searching the prospective participant's past clinical study history for protocol violations in the databases and existing databases of clinical trial participants and medical-related databases based on information in a protocol submission form including all of the following: the prospective participant currently being in-screening at the same or another research site, the prospective participant violating a required number of half-lives since a last research trial, the prospective participant violating a washout period in between trials, the prospective participant violating a biologic modifier washout period, the prospective participant exposed to a same investigational compound if exclusionary per the protocol, the prospective participant has exceeded a maximum number of clinical trials per period of time, the prospective participant already was a screen failure for a same trial if exclusionary, the prospective participant has a blood draw violation, the prospective participant has a plasma draw violation, and a last visit of the prospective participant is in violation of protocol;
electronically alerting a research site or clinical trial administration if the participant's past clinical study history indicates that the participant is attempting duplicate enrollment at a clinical trial site or is violating a protocol violation based on results of the screening mechanism; and
determining eligibility of the participant for the clinical trial and preventing the protocol violations.

US Pat. No. 10,510,436

USING SERIAL DILUTIONS OF REFERENCE SAMPLES TO CONSTRUCT A REFERENCE TABLE FOR SIGMOIDAL FITTING IN REAL-TIME PCR COPY NUMBER ANALYSIS

Credo Biomedical Pte Ltd....

1. A method for quantification of a target nucleic acid, comprising the steps of:(a) constructing a reference table of copy number vs. normalized cycle number from reference samples with the same nucleic acid sequence of the target nucleic acid, wherein the reference table is constructed by the steps of:
i. preparing the reference samples;
ii. amplifying the reference samples;
iii. monitoring and detecting the amplifications of the reference samples in real-time;
iv. normalizing the detected signals to fall into the range of 0-1 when the amplifications are saturated;
v. fitting curves of serial dilution by using the sigmoidal function:

 wherein NS is a normalized signal, t is a cycle number, t1/2 is a fractional cycle at which a reaction light reaches half of the maximal reaction light, ? is a slope of the curve;
vi. normalizing the cycle number of each reference sample by the slope of the curves themselves; and
viii. repeating the step v. to get t1/2 of each reference sample;
(b) amplifying the target nucleic acid;
(c) monitoring and detecting the amplification of the target nucleic acid in real-time;
(d) normalizing the detected signals within the range of 0-1 when the amplification of the target nucleic acid is saturated;
(e) fitting the curve of the target nucleic acid by using the sigmoidal function:

wherein NS is a normalized signal, t is a cycle number, t1/2 is a fractional cycle at which a reaction light reaches half of the maximal reaction light, ? is a slope of the curve;
(f) normalizing the cycle number of the target nucleic acid by the slope of the curve itself;
(g) repeating step (e) to get t1/2 of the target nucleic acid; and
(h) obtaining the copy number of the target nucleic acid contained in the sample by performing a look-up in the reference table, wherein the amplification reactions of the target nucleic acid and the reference samples are real-time PCR.

US Pat. No. 10,510,431

DETECTING RANDOM TELEGRAPH NOISE DEFECTS IN MEMORY

QUALCOMM Incorporated, S...

1. A method of detecting random telegraph noise defects in a memory, comprising:initializing a first bit cell of the memory to a first value;
reading the first value from the first bit cell;
writing a second value to the first bit cell;
performing back to back read operations on a second bit cell adjacent to the first bit cell, after writing the second value;
attempting to read the second value from the first bit cell; and
determining whether the first bit cell is defective based on whether the second value was read from the first bit cell.

US Pat. No. 10,510,425

SEMICONDUCTOR STORAGE DEVICE

Toshiba Memory Corporatio...

1. A semiconductor storage device comprising:a plurality of word lines;
a plurality of bit lines;
a plurality of memory cells;
a word line controller configured to apply a voltage to a selected word line among the word lines;
a bit line controller configured to apply voltages to the bit lines; and
a detection circuit configured to detect data of the memory cells, wherein
the word line controller and the bit line controller are configured to operate a write sequence of writing data in selected memory cells connected to the selected word line, the write sequence comprising at least one write loop including a write operation of applying a plurality of write voltages, and to operate a verify operation of verifying with the detection circuit whether a threshold voltage of each of the selected memory cells has reached a plurality of reference voltages for corresponding write data, and
the word line controller is configured to select write voltages corresponding to threshold voltages of the selected memory cells, respectively, from among the plurality of write voltages different from each other with respect to each of the write loops, and apply the selected write voltages to the selected memory cells in a subsequent write operation, respectively,
the bit line controller is configured to select a voltage corresponding to the threshold voltages of the selected memory cells, respectively, from among a plurality of bit line voltages different from each other and apply the selected voltage to the selected memory cells via the bit lines in a subsequent write operation,
the number of the write voltages applied to the selected memory cells in each write loop is two or more, the number of bit line voltages applied to the selected memory cells is two or more, the word line controller and the bit line controller are configured to apply a higher word line voltage among the word line voltages and a lower bit line voltage among the bit line voltages to a first memory cell of the selected memory cells in a second write loop after a first write loop, when the threshold voltage of the first memory cell is lower than a verify low level in the first write loop,
the word line controller and the bit line controller are configured to apply a higher word line voltage and a higher bit line voltage to the first memory cell in a third write loop after the second write loop, when the threshold voltage of the first memory cell is higher than the verify low level and lower than a verify high level in the second write loop,
the word line controller and the bit line controller are configured to apply a lower word line voltage and a lower bit line voltage to the first memory cell in a fourth write loop after the third write loop, when the threshold voltage of the first memory cell is still higher than the verify low level and lower than the verify high level in the third write loop, and
the word line controller and the bit line controller are configured to apply a lower word line voltage and a higher bit line voltage to the first memory cell in a fifth write loop after the fourth write loop, when the threshold voltage of the first memory cell is still higher than the verify low level and lower than the verify high level in the fourth write loop.

US Pat. No. 10,510,424

SEMICONDUCTOR MEMORY DEVICE FOR IMPROVING DIFFERENCES BETWEEN CURRENT CHARACTERISTICS OF MEMORY CELLS

SK hynix Inc., Gyeonggi-...

1. A semiconductor memory device comprising:a voltage supply unit configured to provide operating voltages to a plurality of pages;
a page buffer coupled to a bit line and configured to control and sense currents flowing through the bit line in response to a page buffer sensing signal; and
a control logic configured to control the voltage supply unit and the page buffer to successively program the plurality of pages, and adjust a potential level of the page buffer sensing signal used for a program verify operation when a page selected to be programmed is changed according to a program sequence of the plurality of pages,
wherein different potential levels of the page buffer sensing signal are respectively used for program operations of different pages among the plurality of pages, and
wherein the potential levels of the page buffer sensing signal are increased as the selected page is changed in the program sequence.