US Pat. No. 10,483,897

SWITCHED RELUCTANCE MOTOR SYSTEM, AND METHOD OF CONTROLLING SWITCHED RELUCTANCE MOTOR SYSTEM

TOYOTA JIDOSHA KABUSHII K...

1. A switched reluctance motor system comprising:a switched reluctance motor;
a rotor including a plurality of salient poles;
a stator including a plurality of salient poles;
coils of three phases wound around the salient poles of the stator; and
an electronic control unit configured to drive the switched reluctance motor in a pole configuration pattern in which the salient poles of the stator that have different polarities are alternately arranged,
the electronic control unit being configured to perform current waveform control when an excitation sound frequency of a given order coincides with a resonance frequency of the switched reluctance motor, the given order being at least one of an order that is a least common multiple of the number of the salient poles of the stator and the number of salient poles of the rotor, and an order that is an integral multiple of a product of the number of the salient poles of the rotor and the number of phases of the coils, the current waveform control being a control that controls current waveforms produced when current is passed through the coils of the three phases, such that a current waveform in the coils of at least one phase has a different shape from a current waveform in the coils of another phase.

US Pat. No. 10,483,893

MOTOR DRIVING APPARATUS AND HOME APPLIANCE INCLUDING THE SAME

LG ELECTRONICS INC., Seo...

1. A motor driving apparatus, comprising:a direct current (DC)-stage capacitor to store DC power;
an inverter including three-phase upper arm and lower arm switching elements, the inverter to convert, based on a switching operation, the DC power from the DC-stage capacitor to an alternate current (AC) power, and the inverter to output the converted AC power;
a controller to control the inverter, wherein the controller is configured to control the switching elements, and the controller is configured to control a turn-on time of the switching elements;
an output current detector to detect an output current in a motor,
wherein the controller is configured to:
provide a voltage command value based on the output current in the motor,
determine a position of a voltage vector based on the voltage command value,
when the position of the voltage vector is within a first region of a space vector area and any one of the three-phase switching elements in the inverter is continuously turned on during a first switching period and a second switching period contiguous to the first switching period, control others of the three-phase switching elements in the inverter to shift turn-on time in a direction to a boundary between the first switching period and the second switching period during the first switching period and the second switching period, and control all the three-phase switching elements in the inverter to turn on during a first period including the boundary between the first switching period and the second switching period,
when the position of the voltage vector is within a second region different from the first region of the space vector area and any one of the three-phase switching elements in the inverter is continuously turned off during the first switching period and the second switching period, control others of the three-phase switching elements in the inverter to shift turn-on time in the direction to the boundary between the first switching period and the second switching period during the first switching period and the second switching period, and control at least one of others of the three-phase switching elements in the inverter to turn on during a second period including the boundary between the first switching period and the second switching period.

US Pat. No. 10,483,889

OPERATION OF A LOCAL ALTERNATING CURRENT NETWORK WITH A GENSET AND A UPS

PILLER GROUP GMBH, Oster...

1. A method of operating a local AC power grid comprising a genset which includes a combustion engine and a generator, and an uninterruptable power supply (UPS) which includes an energy storage, the method comprisingdefining a frequency of an AC voltage of the AC power grid present at the genset by means of the UPS;
altering the frequency of the AC voltage defined by means of the UPS in one direction away from a desired frequency, if a present power demand in the AC power grid increases beyond a present power supply in the AC power grid, and altering the frequency of the AC voltage defined by means of the UPS in the other direction away from the desired frequency, if the present power demand falls below the present power supply in the AC power grid;
with increasing power demand of the AC power grid, limiting an alteration of the frequency of the AC voltage defined by means of the UPS in the one direction to a maximum value in that missing power is temporarily fed out of the energy storage into the AC power grid;
keeping a shift of the frequency of the AC voltage defined by means of the UPS in the one direction away from the desired frequency until no more power flows out of the energy storage into the AC power grid; and
responding to deviations of the frequency of the AC voltage of the AC power grid from the desired frequency in one direction by an increase of a genset power supplied by means of the genset, and responding to deviations of the frequency of the AC voltage of the AC power grid from the desired frequency in the other direction by a reduction of the genset power supplied by means of the genset.

US Pat. No. 10,483,887

GAS TURBINE GENERATOR TEMPERATURE DC TO DC CONVERTER CONTROL SYSTEM

Rolls-Royce North America...

1. A system comprising:a gas turbine operable at a rated constant speed to rotate an output shaft;
a temperature sensor configured to output a temperature signal indicative of an operational temperature of the gas turbine;
a generator rotatably coupled with the output shaft and operable to output electric power;
a DC to DC converter configured to receive electric power from the generator, the DC to DC converter coupled with a load bus;
an energy storage device coupled with the load bus; and
a controller configured to receive the temperature signal and dynamically adjust a demand output of the DC to DC converter in response to the operational temperature of the gas turbine, rotating at the rated constant speed, exceeding a predetermined threshold temperature value for a predetermined period of time, the controller configured to dynamically adjust the demand output lower in proportion to a duration of time that the operational temperature exceeds the predetermined threshold temperature value.

US Pat. No. 10,483,879

ON-LOAD TAP CHANGER AND METHOD OF AND SYSTEM FOR OPERATING SAME

MASCHINENFABRIK REINHAUSE...

1. An on-load tap changer for uninterrupted switching between winding taps of a control winding, comprisinga changeover switch that has a first changeover contact, a second changeover contact and a third changeover contact and that can assume a first position in which the first and third changeover contacts are connected to each other, a second position in which the second and third changeover contacts are connected to each other, and a bridging position in which the first, second, and third changeover contacts are connected to one another;
a first fixed contact that can be connected with an associated first winding tap;
a second fixed contact that can be connected with an associated second winding tap;
a first movable contact that can selectably contact each of the fixed contacts
a second movable contact that can selectably contact each of the fixed contacts;
a main branch that connects the first movable contact with the first changeover contact;
an auxiliary branch that connects the second movable contact with the second changeover contact by a current-limiting resistor or varistor; and
a switching element connected between the main branch and the second changeover contact.

US Pat. No. 10,483,878

ELECTRO-ADHESION GRIPPERS WITH FRACTAL ELECTRODES

1. An electroadhesion gripper for holding workpieces, comprising:a first electrode and a second electrode that mutually engage, in a plan view of the electrodes,
wherein, at least in a sub-region, the first electrode and the second electrode correspond to border lines of a two-dimensional fractal space-filling curve of a second or higher order, and
wherein the border lines result from enclosing a shape of the space-filling curve on both sides on an auxiliary grid that is offset with respect to a grid of the space-filling curve by half a grid spacing in each grid direction.

US Pat. No. 10,483,876

ELECTROSTATICALLY DEFLECTABLE MICROMECHANICAL DEVICE

1. A micromechanical device comprising:a deflectable element, wherein the deflectable element comprises:
an electrostatic actuator which is implemented as a plate capacitor extending along and spaced apart in a deflection direction from a neutral fiber of the deflectable element,
the capacitor comprising a distal electrode and a proximal electrode, wherein the proximal electrode is arranged between the distal electrode and the neutral fiber and the plate capacitor is subdivided along a direction into segments between which the distal electrode is fixed mechanically at segment boundaries such that the deflectable element, by providing the plate capacitor with a voltage, is deflected along the direction in or opposite to the deflection direction; and
wherein the proximal electrode is arranged at a side of an insulation material of the deflectable element facing the distal electrode and is structured along the direction so as to comprise gaps at the segment boundaries such that the distal electrode is mounted mechanically to the insulation material at the segment boundaries in a manner laterally spaced apart from the proximal electrode.

US Pat. No. 10,483,870

POWER CONVERSION METHOD USING VARIABLE POTENTIAL ENERGY STORAGE DEVICES

Offshore Renewable Energy...

1. A power conversion method, comprising:charging a plurality of energy storage devices of a power converter from an input power source, wherein the power converter comprises at least one branch including a first arm connected between an AC terminal and a first DC rail and a second arm connected between the AC terminal and a second DC rail; and
sequentially coupling and decoupling energy storage devices of the plurality of energy storage devices to an output, wherein
charging the plurality of energy storage devices comprises maintaining at least two of the plurality of energy storage devices at substantially different potentials, and wherein
a plurality of energy storage devices in each arm are grouped into sets of at least two energy storage devices, and a control unit is arranged to control charging of the energy storage devices, within each set, to a substantially equal potential, and the energy storage devices in each set of an arm are charged to a significantly different potential from all other sets of said arm.

US Pat. No. 10,483,867

SWITCHED MODE POWER CONVERTER CONFIGURED TO CONTROL AT LEAST ONE PHASE OF A POLYPHASE ELECTRICAL RECEIVER WITH AT LEAST THREE PHASES

THALES, Courbevoie (FR)

1. A switched-mode power converter configured to control at least one phase of a polyphase electrical receiver with at least three phases, comprising at least one block of two converter arms, wherein a half-arm of a converter arm comprises:a first set (ENS1) of P?2 switches (I1, I2) in series;
a second set (ENS2) of P?2 switches (I3, I4) in series, the second set (ENS2) being electrically connected in parallel between a power supply line (DCBUS+, DCBUS?) of a coplanar electrical power supply (DCBUS) and a power interface; and
a third set (ENS3) of diodes, arranged between the first set (ENS1) and the second set (ENS2), comprising M?2 subsets (SE1, SE2, . . . , SEM) in series, indexed i?[[1; M]], respectively comprising Ni?2 diodes in parallel, said third set (ENS3) being electrically connected between the power interface and the other power supply line (DCBUS+, DCBUS?) of the coplanar electrical power supply (DCBUS).

US Pat. No. 10,483,863

ISOLATED SYNCHRONOUS RECTIFICATION-TYPE DC/DC CONVERTER

ROHM CO., LTD., Tokyo (J...

1. A secondary controller used in an isolated synchronous rectification-type DC/DC converter, comprising:a control output pin to be coupled to a light emitting element of a photocoupler;
a power supply pin to be coupled to receive a power supply voltage;
a control input pin to be coupled to receive a detection voltage corresponding to an output voltage of the DC/DC converter;
a feedback circuit structured to amplify an error between the detection voltage and a reference voltage and to supply a current corresponding to the error to the light emitting element of the photocoupler; and
a power supply path coupled to supply power from the control output pin to the power supply pin.

US Pat. No. 10,483,862

BI-DIRECTIONAL ISOLATED DC-DC CONVERTER FOR THE ELECTRIFICATION OF TRANSPORTATION

VANNER, INC., Hilliard, ...

1. A bi-directional DC-DC converter (20) comprising:a first stage (30) comprising:
a first port (22) connected between a first node (N1) and ground;
the first port (22) being bi-directionally operable as an output or an input;
the first port (22) being operatively connected to a primary winding (80) of a first transformer (Tr1);
a second stage (40) comprising:
a second port (24) connected between seventh and eighth nodes (N7), (N8);
the second port (24) being bi-directionally operable as an output or an input;
the second port (24) being operatively connected to a secondary winding (82) of the first transformer (Tr1);
the secondary winding of the first transformer having first and second terminals;
a fifth switch (S5) having first and second terminals
the fifth switch having a body diode,
an anode of the body diode of the fifth switch being connected to the second terminal of the fifth switch,
a cathode of the body diode of the fifth switch being connected to the first terminal of the fifth switch;
a sixth switch (S6) having first and second terminals
the sixth switch having a body diode,
an anode of the body diode of the sixth switch being connected to the second terminal of the sixth switch,
a cathode of the body diode of the sixth switch being connected to the first terminal of the sixth switch;
a seventh switch (S7) having first and second terminals
the seventh switch having a body diode,
an anode of the body diode of the seventh switch being connected to the second terminal of the seventh switch,
a cathode of the body diode of the seventh switch being connected to the first terminal of the seventh switch;
an eighth switch (S8) having first and second terminals
the eighth switch having a body diode,
an anode of the body diode of the eighth switch being connected to the first terminal of the eighth switch,
a cathode of the body diode of the eighth switch being connected to the second terminal of the eighth switch;
a first resonant inductor (Lr1) having first and second terminals;
a first resonant capacitor (Cr1) having first and second terminals;
a second resonant capacitor (Cr2) having first and second terminals;
a third resonant capacitor (Cr3) having first and second terminals;
a fourth resonant capacitor (Cr4) having first and second terminals;
the first terminal of the fifth switch (S5) being connected to the seventh node (N7), the second terminal of the fifth switch (S5) being connected to a sixth node (N6);
the first terminal of the sixth switch (S6) being connected to the sixth node (N6);
the second terminal of the sixth switch (S6) being connected to the eighth node;
the first terminal of the seventh switch (S7) being connected to a tenth node (N10);
the second terminal of the seventh switch (S7) being connected to an eleventh node (N11);
the first terminal of the eighth switch (S8) being connected to the eleventh node (N11);
the second terminal of the eighth switch (S8) being connected to a twelfth node (N12);
the first terminal of the secondary winding (82) of the first transformer (Tr1) being connected to the sixth node (N6);
the second terminal of the secondary winding (82) of the first transformer (Tr1) being connected to a ninth node (N9);
the first terminal of the first resonant inductor (Lr1) being connected to the ninth node (N9);
the second terminal of the first resonant inductor (Lr1) being connected to the tenth node (N10);
the first terminal of the first resonant capacitor (Cr1) being connected to the seventh node (N7);
the second terminal of the first resonant capacitor (Cr1) being connected to the twelfth node (N12);
the first terminal of the second resonant capacitor (Cr2) being connected to the twelfth node (N12);
the second terminal of the second resonant capacitor (Cr2) being connected to the eighth node (N8);
the first terminal of the third resonant capacitor (Cr3) being connected to the seventh node (N7);
the second terminal of the third resonant capacitor (Cr3) being connected to the tenth node (N10);
the first terminal of the fourth resonant capacitor (Cr4) being connected to the tenth node (N10);
the second terminal of the fourth resonant capacitor (Cr4) being connected to the eighth node (N8).

US Pat. No. 10,483,855

POWER LIMIT PROTECTION FOR RESONANT POWER CONVERTER

SEMICONDUCTOR COMPONENTS ...

1. An electronic circuit comprising:an Inductor-Inductor-Capacitor (LLC) tank circuit comprising a first inductor, a second inductor, a capacitor, and a primary coil of a transformer, wherein the first inductor is coupled in series with the second inductor, the second inductor is coupled in series with the capacitor, and the primary coil of the transformer is coupled in parallel with the second inductor; and
an energizing circuit to supply power to the LLC tank circuit according to a switching period and to detect a power limit condition, wherein the power limit condition is detected according to a value of an integrated current sense signal and a duration of the switching period, wherein the integrated current sense signal corresponds to an integration over time of a current supplied to the LLC tank circuit by a first switch, and wherein the energizing circuit comprises:
an oscillator to receive a feedback signal and to generate a clock signal having the switching period according to the feedback signal;
the first switch to supply power to the LLC tank circuit from an input voltage during a first phase of the clock signal;
a second switch to configure components of the LLC tank circuit in a loop circuit during a second phase of the clock signal;
a ramp signal generation circuit to generate a constant dv/dt threshold signal according to the switching period; and
a comparator circuit to detect the power limit condition according to a comparison of the constant dv/dt threshold signal and the integrated current sense signal.

US Pat. No. 10,483,844

CHARGE PUMP ARRANGEMENT AND METHOD FOR OPERATING A CHARGE PUMP ARRANGEMENT

INFINEON TECHNOLOGIES AG,...

1. A charge pump arrangement, comprising:a charge pump circuit configured to convert an input voltage into an output voltage based on a pump clock signal;
a feedback path configured to provide a feedback signal representing the output voltage of the charge pump circuit;
a control circuit configured to receive a clock signal and to control the output voltage of the charge pump circuit by controlling the pump clock signal based on the feedback signal and the clock signal;wherein the feedback path comprises a voltage divider circuit, wherein the voltage divider circuit is coupled to the charge pump circuit to sense the output voltage and further coupled to the control circuit to provide the feedback signal;wherein the voltage divider circuit comprises a first capacitor and a second capacitor coupled in a series arrangement, wherein the feedback signal is tapped between the first capacitor and the second capacitor;additional voltage divider circuit to sense the output voltage of the charge pump circuit and to provide an additional feedback signal for the control circuit; wherein the additional voltage divider circuit comprises a third capacitor and a fourth capacitor coupled in a series arrangement, wherein the additional feedback signal is tapped between the third capacitor and the fourth capacitor; anda switch arrangement configured to switch the charge pump arrangement into a first operation mode and into a second operation mode by switching between the feedback signal of the voltage divider circuit and the additional feedback signal of the additional voltage divider circuit.

US Pat. No. 10,483,841

MOTOR VEHICLE

TOYOTA JIDOSHA KABUSHIKI ...

1. A motor vehicle, comprising:a motor for driving;
a power storage device;
a first converter connected with a first power line which the motor is connected with, and a second power line which the power storage device is connected with, the first converter including first and second switching elements, first and second diodes and a first reactor and being configured to transmit electric power between the first power line and the second power line through voltage conversion;
a second converter connected with the first power line and a third power line which the power storage device is connected with and which is different from the second power line, the second converter including third and fourth switching elements, third and fourth diodes and a second reactor and being configured to transmit electric power between the first power line and the third power line through voltage conversion; and
a control device configured to perform voltage control of the first converter such that a voltage of the first power line becomes equal to a target voltage and to perform current control of the second converter such that an electric current flowing in the second reactor becomes equal to a target current, wherein
in a process of cancelling shutdown of the second converter during transmission of electric power between the first power line and the second power line through the voltage conversion by the first converter in a shutdown state of the second converter, the control device performs single element switching control that switches on one switching element between the third and the fourth switching elements of the second converter while setting the other switching element off, to prevent the electric current from flowing in the second reactor in reverse to a current flow direction in the first reactor.

US Pat. No. 10,483,839

SEMICONDUCTOR DEVICE, POWER CONVERSION DEVICE, DRIVING DEVICE, VEHICLE, AND ELEVATOR

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a first capacitor having a first end and a first another end, the first end for electrically connecting to at least one of a first electrode and a second electrode of a transistor having the first electrode, the second electrode, and a gate electrode;
a first diode having a first anode and a first cathode, the first anode electrically connected to the first another end;
a second capacitor having a second end and a second another end, the second end electrically connected to the first cathode;
a sample and hold circuit electrically connected to the first cathode and the second end;
a switch electrically connected in parallel with the second capacitor between the second end and the second another end; and
a second diode having a second anode and a second cathode, the second cathode electrically connected to the first another end and the first anode,
wherein a power supply voltage VDD of the transistor, a capacitance C1 of the first capacitor, and a capacitance C2 of the second capacitor satisfy 15V?(C1VDD)/(C1+C2).

US Pat. No. 10,483,838

SYSTEM AND METHOD PROVIDING OVER CURRENT PROTECTION BASED ON DUTY CYCLE INFORMATION FOR POWER CONVERTER

On-Bright Electronics (Sh...

1. A signal generator for protecting a power converter, the signal generator comprising:a modulation and drive component configured to generate a modulation signal to output a drive signal to a switch in order to affect a primary current flowing through a primary winding of a power converter, the modulation signal including an on-time period, the switch being closed during the on-time period;
a ramping-signal generator configured to receive the modulation signal and generate a ramping signal based on at least information associated with the modulation signal;
a sampling-signal generator configured to receive the modulation signal and generate a sampling signal including a pulse in response to a falling edge of the modulation signal; and
a sample-and-hold component configured to receive the sampling signal and the ramping signal and output a sampled-and-held signal associated with a magnitude of the ramping signal corresponding to the pulse of the sampling signal;
wherein:
the falling edge of the modulation signal is at a first time;
the pulse of the sampling signal starts at a second time and ends at a third time;
the first time and the second time are the same; and
the on-time period ends at the first time.

US Pat. No. 10,483,832

MULTI-BAR LINKAGE ELECTRIC DRIVE SYSTEM

Indigo Technologies, Inc....

1. An electric drive system comprising:a rotary motor system comprising a hub assembly, a magnetic rotor assembly, a first coil stator assembly, and a second coil stator assembly, wherein the hub assembly defines a rotational axis and wherein each of the magnetic rotor assembly, the first coil stator assembly, and the second coil stator assembly is coaxially aligned with the rotational axis and is capable of rotational movement about the rotational axis; and
a multi-bar linkage mechanism connected to each of the first and second coil stator assemblies and connected to the hub assembly, said multi-bar linkage mechanism constraining movement of the hub assembly so that the rotational axis of the hub assembly moves along a defined path that is in a transverse direction relative to the rotational axis and wherein the multi-bar linkage mechanism causes the rotational axis of the hub assembly to translate along the defined path in response to relative rotation of the first coil stator assembly and the second coil stator assembly with respect to each other,
wherein the multi-bar linkage comprises a first swing arm rotatably coupled to the first stator assembly on a first side of the magnetic rotor assembly, a second swing arm rotatably coupled to the second stator assembly on a second side of the magnetic rotor assembly, and a member parallel to the rotational axis and rotatably coupled to the first swing arm and rotatably coupled to the second swing arm.

US Pat. No. 10,483,827

BUILT-IN CAPACITOR MOTOR STRUCTURE

Sagitta Industrial Corp.,...

1. An improved built-in capacitor motor structure comprising:a housing including a front cover and a rear cover;
a stator portion received in the housing including a core frame, the core frame is provided with an annular insulating frame body, a plurality of circularly arranged docking units extending from the periphery of a side of the insulating frame body;
an insulating member connected on the insulating frame body having an accommodating space in communication with the outside, a capacitor being combined inside the accommodating space of the insulating member, and a plurality of corresponding docking units being provided at the bottom side edge of the insulating member; and
a rotor portion received in the stator portion,
wherein the plurality of corresponding docking units are engaged with the docking units of the insulating frame body, respectively, to connect the insulating member on the insulating frame body.

US Pat. No. 10,483,818

INSULATED WIRE, MOTOR COIL, AND ELECTRICAL OR ELECTRONIC EQUIPMENT

FURUKAWA ELECTRIC CO., LT...

1. An insulated wire, comprising at least one thermosetting resin layer and at least one thermoplastic resin layer in this order, as covering layers, on a conductor having a quadrilateral cross-section,wherein, in each of 4 covering layer portions corresponding to 4 sides of the cross-section of said insulated wire, a difference between the maximum value and the minimum value of a coating thickness is each 20 ?m or less, and in the whole of the above 4 covering layer portions, a value of the maximum value divided by the minimum value of the coating thickness is 1.3 or more.

US Pat. No. 10,483,814

SYNCHRONOUS-GENERATOR POLE STACK

Wobben Properties GmbH, ...

1. A synchronous generator rotor pole pack, comprising:a plurality of pole shoes each comprising a plurality of pole pack segments, wherein each pole pack segment comprises a pole shank portion and a pole head portion, wherein the pole shank portions of the plurality of pole pack segments form a pole shank, wherein the pole head portions of the plurality of pole pack segments form a pole head having at least three pole head sections, wherein a front edge of each of the at least three pole head sections is arranged at an angle with respect to the pole shank, wherein a depth of the pole head portions of the plurality of pole pack segments are identical, wherein the pole head portions of the plurality of pole pack segments are offset with respect to adjacent pole head portions, wherein the segment in an area of the pole shank are not arranged offset with respect to each other, and wherein the pole shank is arranged as a straight continuous portion.

US Pat. No. 10,483,809

POWER TRANSMITTING APPARATUS, METHOD OF CONTROLLING THE SAME, AND POWER TRANSMISSION SYSTEM

Canon Kabushiki Kaisha, ...

1. A power transmitting apparatus comprising:a first antenna configured to perform wireless power transmission to a power receiving apparatus and perform wireless communication with the power receiving apparatus;
a second antenna configured to perform wireless communication with the power receiving apparatus, wherein the second antenna is different from the first antenna; and
one or more processors configured to:
communicate with the power receiving apparatus, by the first antenna, identification information of at least one of the power transmitting apparatus and the power receiving apparatus, wherein the identification information can be used for communicating by the second antenna;
determine whether or not a communication connection based on the identification information that is communicated by the first antenna is established via the second antenna;
perform wireless power transmission to the power receiving apparatus by the first antenna based on a determination that the communication connection based on the identification information that is communicated by the first antenna is established via the second antenna, and; and
restrict wireless power transmission to the power receiving apparatus based on a determination that the communication connection based on the identification information that is communicated by the first antenna is not established via the second antenna.

US Pat. No. 10,483,805

DEVICE FOR WIRELESS TRANSMISSION OF DATA AND POWER

KONINKLIJKE PHILIPS N.V.,...

1. A device for wireless transmission of data and power between the device and another device of a system, in particular of a patient monitoring system, said device comprising:an identification unit for storing a unique identifier of the device,
a connector comprising:
a data transmission unit arranged for transmitting data to and/or receiving data from another device of the system having a counterpart connector,
a magnetic coupling unit for transmitting power to and/or receiving power from another device of the system having a counterpart connector by use of inductive coupling, and
a detection unit for detecting the strength of magnetic coupling between the magnetic coupling unit and a magnetic coupling unit of a counterpart connector of another device and for detecting the intensity of data received by the data transmission unit from a data transmission unit of the other device, and
a control unit for controlling the data transmission unit to transmit the unique identifier of the device to the other device and/or to receive the unique identifier of the other device, if i) the detected intensity of received data is above a data intensity threshold and/or its increase is above a data intensity increase threshold and ii) the detected magnetic coupling is above a magnetic coupling threshold and/or its increase is above a magnetic coupling increase threshold,wherein said magnetic coupling unit comprises:a flux concentrator, at least part of which having a U-shaped cross-section forming a recess between the legs of the U,
a first coil arranged within the recess of the flux concentrator, and
a second coil arranged outside of the recess in which the first coil is arranged, andwherein the magnetic coupling unit is arranged to allow stacking of devices upon each other so that the flux concentrator and the first coil of the device and the flux concentrator and a second coil of another device stacked upon the device together form a transformer for inductive power transmission there between and/or the flux concentrator and the second coil of the device and the flux concentrator and a first coil of another device stacked upon the device together form a transformer for inductive power transmission there between.

US Pat. No. 10,483,798

WIRELESS PORTABLE CHARGER AND DISPLAY PANEL FOR A WIRELESS CHARGEABLE HAND HELD DEVICE

1. A wireless portable charger and display panel for a wireless chargeable hand held device, which comprises:a housing having a generally horizontal surface which includes a wireless charging receiving surface of a sufficient size only to receive the wireless chargeable hand held device and having a non horizontal surface extending outward from said generally horizontal surface configured to substantially inhibit placement of another object thereon from a diminished area of said generally horizontal surface beyond said wireless charging receiving surface throughout said non horizontal surface;
a generally vertical display panel connected to said housing;
a wireless charging coil operably disposed in said housing having adjacent said wireless charging receiving surface;
a power source;
an electronic controller board operably disposed in said housing connected to said power source and said wireless charging coil rechargeable; and
a power switch operably connected to said electronic controller board for actuating on/off flow of electrical power.

US Pat. No. 10,483,797

CONTACTLESS CONNECTOR AND CONTACTLESS CONNECTOR SYSTEM

11. A contactless connector system, comprising:a power transmitting connector having a primary inductive coupler connected to an input power source, a resonant circuit generating a magnetic field at the primary inductive coupler, a primary data transceiver, a primary data communication interface connected to the primary data transceiver and communicating with a primary external component, and a primary control unit controlling an operation of the resonant circuit, the primary data communication interface, and the primary data transceiver; and
a power receiving connector having a secondary inductive coupler electromagnetically coupled with the primary inductive coupler, the secondary inductive coupler receiving electric power from the primary inductive coupler, a terminal connected to a secondary external component, outputting the electric power to the secondary external component, and receiving power from an external power source different from the power transmitting connector connected to the terminal to supply power to the power receiving connector, a switch connected to the terminal and controlling the electric power output at the terminal, a secondary data transceiver forming a data link with the primary data transceiver, and a secondary data communication interface connected to the secondary data transceiver and communicating with the secondary external component, the secondary external component and the external power source are external to a structure of the power receiving connector containing the secondary inductive coupler, the switch, the secondary data transceiver, and the secondary data communication interface.

US Pat. No. 10,483,795

SYSTEM AND METHOD FOR ESTABLISHING COMMUNICATION WITH AN ARRAY OF INVERTERS

Enphase Energy, Inc., Pe...

1. A method for establishing communication between a controller and a plurality of inverters, the inverters configured to convert direct current (DC) power from an alternative energy source to AC power, the method comprising:receiving with an inverter of the plurality of inverters a response request transmitted by the controller via an AC line, the response request including a length of a response time window;
determining a random response time for the inverter based on the length of the response time window;
transmitting a response to the controller at the response time, the response including an identification of the inverter;
and
in response to receiving an acknowledgement from the controller in response to the transmitted response, updating the inverter's operation to ignore subsequent response requests from the controller.

US Pat. No. 10,483,788

CHARGING METHOD FOR SUB-MODULE BASED HYBRID CONVERTER

NR ELECTRIC CO., LTD, Ji...

1. A charging method for a sub-module based hybrid converter, wherein the charging method comprises the following specific steps:step (1): performing, by a converter, an uncontrolled charging process;
step (2): powering a full bridge sub-module based self-powered supply, and half-blocking full bridge sub-modules and blocking half bridge sub-modules after the powering succeeds;
step (3): performing, by the converter, a half-controlled charging process, and closing a bypass switch of a charging resistor after the half-controlled charging process is completed; and
step (4): performing, by the converter, a full-controlled charging process.

US Pat. No. 10,483,787

WIRELESS CHARGING APPARATUS BASED ON THREE-DIMENSIONAL (3D) WIRELESS CHARGING ZONE

Electronics and Telecommu...

1. A wireless charging apparatus comprising:a plurality of transmitting coils included in a wireless charging zone in a three-dimensional (3D) form; and
at least one power source configured to supply a current to the plurality of transmitting coils,
wherein the at least one pair of transmitting coils are configured to form a quiet zone indicating a magnetic field having an equalized energy density in the wireless charging zone.

US Pat. No. 10,483,786

WIRELESS CHARGING SYSTEMS WITH MULTICOIL RECEIVERS

Apple Inc., Cupertino, C...

1. A portable electronic device that is configured to receive wireless power transmitted from an array of tiled transmitting coils in a wireless power transmitting device, wherein the tiled transmitting coils are characterized by a center-to-center spacing, the portable electronic device comprising:a battery; and
wireless power receiving circuitry that includes an array of wireless power receiving coils and that includes rectifier circuitry that is configured to rectify alternating-current wireless power signals received by the array of wireless power receiving coils and to provide a corresponding direct-current voltage to the battery, wherein the wireless power receiving coils are laterally spaced from each other in a two-dimensional array, and wherein first, second, and third wireless power receiving coils of the array of wireless power receiving coils are respectively aligned with first, second, and third vertices of an equilateral triangle that has sides with lengths equal to half of the center-to-center spacing.

US Pat. No. 10,483,779

STATUS DETERMINING METHOD FOR SECONDARY BATTERY, STATUS DETERMINING APPARATUS FOR SECONDARY BATTERY, SECONDARY BATTERY SYSTEM, AND CHARGE/DISCHARGE CONTROL APPARATUS HAVING STATUS DETERMINING APPARATUS

HITACHI, LTD., Tokyo (JP...

1. A state determination device that improves accuracy of measuring deterioration in a secondary battery having a positive electrode and a negative electrode, the state determination device comprising:a current sensor that measures a current of the secondary battery;
a controller communicatively coupled to the current sensor, wherein the controller;
receives a current value A from the current sensor,
retrieves, from a memory of the controller, charge and discharge characteristics per reference quantity of the positive electrode and the negative electrode,
determines a capacity reduction parameter group A based on the charge and discharge characteristics and the current value A,
receives a current value B from the current sensor, and
determines a resistance increase parameter group B based on the charge and discharge characteristics, the capacity reduction parameter group A, and the current value B, wherein the current value B is larger than the current value A.

US Pat. No. 10,483,771

SYSTEMS AND METHODS FOR HYBRID ENERGY HARVESTING FOR TRANSACTION CARDS

Capital One Services, LLC...

1. A transaction card, comprising:a data storage device configured to supply account information to a transaction card terminal;
a first rechargeable power source configured to receive charging energy from the transaction card terminal during a transaction using the card;
a second rechargeable power source configured to receive energy from only the first rechargeable power source; and
a power controller configured to:
determine whether the second rechargeable power source requires recharging;
control a flow of energy from the first rechargeable power source to the second rechargeable power source; and
determine, in response to a request associated with the transaction, whether the transaction card has sufficient power to complete the transaction prior to conducting the transaction.

US Pat. No. 10,483,766

POWER RECEIVER CIRCUIT

uBeam Inc., Marina del R...

1. A power receiver circuit device comprising:a power generating mechanism comprising power generating elements configured to generate alternating current signals;
one or more rectifier circuits, each rectifier circuit comprising a rectifier configured to generate a direct current signal from an alternating current signal and a diode;
one or more group circuits, each group circuit connecting a group of rectifier circuits in an electrical circuit to combine the direct current signals from the rectifier circuits in the group into a single direct current signal;
a step down converter connected to the one or more group circuits, the step down converter configured to convert a direct current signal to a direct current signal of a target voltage level;
an output switch connected to the step down converter;
a linear regulator connected to the step down converter; and
a microcontroller connected to the linear regulator and the output switch and configured to control the output switch, wherein the microcontroller is configured to open the output switch, enter a standby state, and send a message using a radio of the microcontroller that the voltage of the voltage of the direct current signal from the step down converter has dropped when the microcontroller determines that the voltage of the direct current signal from the step down converter falls below a predetermined a threshold voltage.

US Pat. No. 10,483,765

POWER GENERATION AND DISTRIBUTION SYSTEM FOR OFFSHORE DRILLING UNITS

1. A power generation and distribution system for a drilling rig comprising:an AC bus and a DC bus,
an AC generator electrically connected to the AC bus,
an AC bus load electrically connected to the AC bus,
a first power transformer configured to convert a plurality of voltage phases of the AC bus into a plurality of corresponding secondary side voltage phases,
a first unidirectional AC-DC power converter connected between the secondary side voltage phases of the first power transformer and the DC bus for supplying power to the DC bus,
one or more DC bus loads connected to the DC bus, and
a second AC-DC power converter connected between the DC bus and at least one of an auxiliary transformer winding of the first power transformer and a second power transformer for supplying power from the DC bus to the AC bus.

US Pat. No. 10,483,763

PHOTOVOLTAIC DEVICE AND OPERATING POINT CONTROL CIRCUIT DEVICE FOR PHOTOVOLTAIC CELLS OR OTHER POWER SUPPLY ELEMENTS CONNECTED IN SERIES

Toyota Jidosha Kabushiki ...

1. A photovoltaic device comprising:a plurality of photovoltaic cells which are connected in series between output terminals or a plurality of photovoltaic cells and capacitors, wherein the photovoltaic cells are connected in series between output terminals, the capacitors are connected in series between output terminals, and the photovoltaic cells and the capacitors are connected in parallel;
a photovoltaic operating point control circuit device including an inductor and a switching element that are connected in parallel to each photovoltaic cell or each photovoltaic cell and capacitor which are connected in parallel, wherein the inductor and the switching element are connected in series, the photovoltaic operating point control circuit device being configured to output a current from the corresponding photovoltaic cell or capacitor to between the output terminals by periodically cutting off the switching elements,
wherein the photovoltaic operating point control circuit device fixes cutoff duty ratios of all switching elements in one cycle in which the switching elements corresponding to all the plurality of photovoltaic cells or the plurality of photovoltaic cells and capacitors which are connected in series are cut off once,
wherein a sum of cutoff durations of all the switching elements in one cycle is larger than a duration of one cycle, and
wherein a part of the cutoff times overlap in the neighboring cutoff times.

US Pat. No. 10,483,757

FAST-ACTING POWER PROTECTION SYSTEM INCORPORATING DISCRETE MOSFETS AND CONTROL IC ON HYBRID SUBSTRATES AND METHOD OF OPERATING THEREOF

Manufacturing Networks In...

1. A method of protecting an electrical device from a power surge, the method comprising the steps of:connecting an input terminal of a fast-acting power protector to an electrical source, wherein the fast-acting power protector incorporates a current-limiting block control unit as a universal control IC core chip mounted on a first hybrid substrate, an NMOS-based power switch unit mounted on a separate second hybrid substrate, and an output voltage clamp either integrated into the universal control IC core chip or connected to the universal control IC core chip as a separate unit, wherein the current-limiting block control unit and the NMOS-based power switch unit constitute a current limiting block;
connecting an output terminal of the fast-acting power protector to the electrical device for power surge protection;
determining whether an incoming electrical current multiplied by a sense resistor value (Rsense) is approximately equal to a surge protection trigger voltage (Vos) for a current trip;
if the incoming electrical current multiplied by the sense resistor value (Rsense) is approximately equal to the surge protection trigger voltage (Vos) for the current trip:
using at least one MOSFET and optionally at least one reverse-protection diode in the current limiting block to reduce or shut down the incoming electrical current as a current or voltage surge protection; and
if a voltage coming out of the current limiting block is surging higher than a clamp output voltage of the output voltage clamp at the output terminal of the fast-acting power protector:
holding down the voltage coming out of the current limiting block to the clamp output voltage at the output terminal to the clamp output voltage of the output voltage clamp as a voltage surge protection of the electrical device connected to the output terminal of the fast-acting power protector.

US Pat. No. 10,483,755

DISPLAY DEVICE INCLUDING POWER CONVERTER

Samsung Display Co., Ltd....

1. A display device, comprising:a display panel including a plurality of pixels, the pixels being configured to operate in response to a first driving voltage, a second driving voltage, and a data signal;
a voltage converter that provides the first driving voltage to the display panel through first wiring and the second driving voltage to the display panel through second wiring and controls a length of a detection period, the voltage converter selectively starting an output of the second driving voltage after the detection period, the detection period being after an output of the first driving voltage; and
a detector configured to control the output of the first and second driving voltages of the voltage converter based on a magnitude of a wiring voltage corresponding to voltage on the second wiring.

US Pat. No. 10,483,754

FAULT DETECTION AND LOCATION IN NESTED MICROGRIDS

ABB Schweiz AG, Baden (C...

1. A microgrid comprising:a plurality of switching devices;
a plurality of distribution line segments, each distribution line segment coupled to at least one switching device of the plurality of switching devices;
a plurality of measuring devices, each measuring device corresponding to one of the plurality of switching devices; and
at least one distributed energy resource (DER) coupled to one of the plurality of distribution line segments;
a network controller configured to:
receive measurements from the plurality of measurement devices,
determine a fault is occurring within the microgrid using the measurements,
assign a topology classification to each of the plurality of distribution line segments based on whether a load or a DER is coupled to the distribution line segment following the determining a fault is occurring,
assign a proximity classification to said each of the plurality of distribution line segments based on whether a fault current may flow through the distribution line segment in one direction or two directions following the determining a fault is occurring,
determine fault location using the topology classification and the proximity classification, and
isolate the fault by transmitting open commands at least one of the plurality of switching devices closest to the fault.

US Pat. No. 10,483,753

EMBEDDED BATTERY PROTECTION SYSTEM

BCD Semiconductor Manufac...

1. A battery control circuit for a mobile device, wherein the mobile device has an embedded battery and is configured for coupling to an external power source, the battery control circuit comprising:first and second high-voltage NMOS transistors coupled in series and configured for connecting between a ground terminal of the embedded battery in the mobile device and a ground terminal of the external power source; and
a battery protection IC (integrated circuit) including:
a power terminal for coupling to a power terminal of the embedded battery and a power terminal of the external power source;
a first ground terminal for coupling to the ground terminal of the external power source; and
a second ground terminal for coupling to the ground terminal of the embedded battery;
wherein the battery protection IC is configured to:
receive a signal from a functional block in the mobile device, the signal having a voltage level relative to the ground terminal of the external power source;
and
in response to the signal, provide one or more control signals having voltage levels relative to the ground terminal of the embedded battery, the control signals being configured to turn on the first and the second high-voltage NMOS transistors to connect the embedded battery to the external power source, or to turn off the first and the second high-voltage NMOS transistors to disconnect the embedded battery from the external power source;
wherein the battery protection IC comprises:
a signal processing circuit configured to receive an input signal having a voltage level relative to the first ground terminal and to provide an output signal having a voltage level relative to the second ground terminal in response to the input signal; and
a logic circuit coupled to the signal processing circuit and configured to provide one or more control signals having voltage levels relative to the second ground terminal in response to the output signal of the signal processing circuit;
wherein the signal processing circuit comprises:
a first circuit coupled between the power terminal and the first ground terminal, the first circuit being configured to receive an input signal having a voltage level relative to the first ground terminal and to provide first and second complementary digital signals in response to the input signal; and
a second circuit coupled between the power terminal and the second ground terminal, the second circuit being configured to provide a digital output signal relative to the second ground terminal in response to the first and second complementary digital signals;
wherein the one or more control signals are configured to turn on a switch device including the first and second high-voltage NMOS transistors between the first ground terminal and the second ground terminal to connect the first ground terminal to the second ground terminal, even when the second ground terminal is electrically floating relative to the first ground terminal.

US Pat. No. 10,483,752

POWER SUPPLY APPARATUS AND IMAGE FORMING APPARATUS

CANON KABUSHIKI KAISHA, ...

1. A power supply apparatus comprising:a transformer having a primary winding and a secondary winding;
a switching element connected in series to the primary winding of the transformer;
a control unit configured to control an output voltage induced in the secondary winding of the transformer by driving the switching element;
a feedback unit configured to feedback a detection result of a voltage induced on the secondary winding to the control unit; and
a detection unit configured to detect an overheat state of the transformer and output an overheat signal to the control unit,
wherein the detection unit has a voltage division unit configured to divide the output voltage,
wherein the voltage division unit includes a temperature detection element to detect a temperature of the transformer, and a resistance element connected in series to the temperature detection element, the voltage division unit disposed in a vicinity of the transformer,
wherein the detection unit outputs the overheat detection signal to the control unit in a case where the detection unit detects the overheat state of the transformer based on a voltage obtained by dividing the output voltage by the voltage division unit, and
the control unit turns off the switching element in response to the overheat detection signal output from the detection unit, and stops driving of the switching element.

US Pat. No. 10,483,751

TRIP CONTROL CIRCUIT FOR CIRCUIT BREAKER

LSIS CO., LTD., Anyang-s...

1. A trip control circuit for a circuit breaker, the trip control circuit comprising:a current transformer that has a ring-shaped core allowing a circuit to pass through and a secondary coil wound around the core for detecting a current flowing on the circuit and providing a current detection signal;
an oscillation circuit section that is configured to apply an electrical signal to the secondary coil of the current transformer to increase a slope of a hysteresis loop of the current transformer to allow the secondary coil to detect a DC current, as well as an AC current, flowing on the circuit; and
a trip determining circuit section that is configured to compare a current value indicated by the current detection signal having an AC component and a DC component output from the secondary coil of the current transformer with a predetermined reference current value, and output a trip control signal when the current value indicated by the current detection signal exceeds the reference current value, and
wherein the trip determining circuit section is configured to determine a current amount flowing on the circuit according to a change in time on the basis of the current detection signal, and determine a waveform and a frequency of the electrical signal to be supplied to the secondary coil through the oscillation circuit section.

US Pat. No. 10,483,750

SELECTIVE CIRCUIT BREAKER

EATON INTELLIGENT POWER L...

1. A selective circuit breaker, in operation connectable between a main supply line and a downstream circuit breaker, the selective circuit breaker comprising:a bypass switch in a supply line;
a controlled semiconductor switch connected in parallel to the bypass switch;
a bypass switch off detection circuitry; and
a short circuit detection circuitry configured to control the bypass switch and the controlled semiconductor switch in accordance with a switching characteristic,
wherein the switching characteristic is programmable,
wherein a short circuit current rating of the selective circuit breaker is substantially equal to a short circuit current rating of a downstream circuit breaker,
wherein the selective circuit breaker is operable in a normal operating mode or in a system limit selectivity mode,
wherein in the normal operating mode the selective circuit breaker is programmed to disconnect later than the downstream circuit breaker, and
wherein in the system limit selectivity mode the selective circuit breaker is programmed to apply a reconnect attempt.

US Pat. No. 10,483,745

METHODS OF MAKING MOISTURE-RESISTANT DOWNHOLE ELECTRICAL FEEDTHROUGHS

1. A method of forming a downhole electrical feedthrough package, the method comprising:combining at least two of the four components selected from Bi2O3, B2O3, MO, and optionally REO to form a glass mixture;
heating the glass mixture to approximately 650 to 1400 degrees Celsius;
quenching the heated glass mixture in de-ionized water bath to form glass frits;
sintering the glass frits with hollow cylinder shape and fitted into a conduit of a metal shell to form an electrical feedthrough assembly;
firing the electrical feedthrough assembly at first temperature (T1) for a first time period to form a dielectric seal and to provide a first thermal energy to the dielectric seal;
heating the electrical feedthrough assembly at second temperature (T2) for a second time period to provide a second thermal energy to the dielectric seal;
cooling the dielectric seal of the electrical feedthrough assembly to ambient temperature for a third time period; and
integrating two isolators into the conduit so that the dielectric seal is in contact with at least one of the isolators.

US Pat. No. 10,483,743

CABLE HOLDING DEVICE

PANASONIC INTELLECTUAL PR...

1. A cable holding device for holding a cable, comprising:a first member that has a first through hole through which the cable is to pass;
a second member that has a second through hole through which the cable is to pass; and
a fixing screw that fixes the second member to the first member in such a condition that the second through hole partially overlaps the first through hole to hold the cable by an inner periphery of the first through hole and an inner periphery of the second through hole,
wherein the second member is moved relative to the first member by a rotation of the fixing screw,
wherein the first member comprises a guide tab,
wherein the second member comprises a slide lever,
wherein the guide tab and the slide lever each extend in an axial direction of the cable, and
wherein a screw through hole through which the fixing screw is to pass is formed in one of the guide tab of the first member and the slide lever of the second member, and a female threaded hole, which is to engage with the fixing screw, is formed in another of the guide tab of the first member and the slide lever of the second member.

US Pat. No. 10,483,741

SEAL FOR ELECTRICAL BOX

ALLIED MOULDER PRODUCTS, ...

1. An electrical box configured to be received in an opening, the electrical box comprising:a front surface having an opening formed therein providing access to a hollow interior of the electrical box;
a sidewall extending rearwardly from the front surface to form the hollow interior; and
a tapered compressible seal compressed between an exterior surface of the sidewall and a surface forming the opening when the electrical box is received in the opening to form a vapor seal about a periphery of the exterior surface of the sidewall of the electrical box, wherein the seal abuts a rear surface of a retention flange of the electrical box.

US Pat. No. 10,483,737

ELECTRICAL BOX WITH DUAL-HINGED COVER

1. An outlet box with dual-hinged cover, comprising:a housing defining an opening and comprising a pair of spaced-apart sidewalls;
a cover coupled to said housing and positionable inside said opening;
a pair of spaced-apart pivot arms at opposite sides of said cover, said pivot arms having respective distal end portions pivotably coupled to said cover at opposite ends of said cover, and said pivot arms having proximal end portions pivotably coupled to respective ones of said sidewalls; and
a retaining element at each of said first and second pivot arms and a corresponding retaining element at each of said sidewalls, wherein each of said corresponding retaining elements is configured to interact with a corresponding one of said retaining elements to releasably secure said cover in a closed position, and to provide sensory feedback to a user as said cover moves from an open position to the closed position;
wherein said cover is openable from the closed position in a first direction about a first pivot axis extending through said proximal end portion of a first of said pivot arms, and said cover is openable from the closed position in a second direction about a second pivot axis extending through said proximal end portion of a second of said pivot arms.

US Pat. No. 10,483,735

NINETY DEGREE SNAP FIT ELECTRICAL FITTING FOR CONNECTION OF ELECTRICAL CABLES TO AN ELECTRICAL BOX

ARLINGTON INDUSTRIES, INC...

1. A snap fit electrical fitting, comprises:a one-piece connector body including a sidewall, a leading end having a circular outlet bore with an outlet axis, and a trailing end having a circular inlet bore with an inlet axis, said inlet axis and said outlet axis are at an angle to one another;
a leading flange extending around the periphery of said leading end of said connector body and a trailing flange between said leading end and said trailing end of said connector body;
said sidewall at said trailing end including a straight sidewall portion including a first inlet chamber and a second inlet chamber, said second inlet chamber including an inner periphery and an interior end;
a cylindrical sidewall portion extending from said straight wall portion to said leading end;
an internal shoulder is between said straight sidewall portion and said cylindrical sidewall portion;
an outer flange is between said trailing flange and said internal shoulder, said outer flange extending from said cylindrical sidewall portion of said connector body;
an outside bend and an inside bend of said connector body;
said angle between said inlet bore and said outlet bore is between 60 and 120 degrees;
a reduced-diameter seat has a constant diameter, and is on said leading end of said connector body, said seat extending from said leading flange to said trailing flange;
a snap ring is disposed on said seat;
an internal snap ring is within said first inlet chamber of said connector body;
a pusher tang is on said inside bend of said snap fit electrical fitting;
said pusher tang directing a cable inserted within said inlet bore toward said outside bend of said connector body; and
axially aligned openings extending through the sidewall on the second inlet chamber of the connector body, wherein the axially aligned openings are substantially orthogonal to a part of the straight side wall portion connecting to the outside bend.

US Pat. No. 10,483,726

POWER PEDESTAL WITH SKELETON TOWER ASSEMBLY AND COOPERATING OUTER SLEEVE AND RELATED METHODS

Eaton Intelligent Power L...

17. A power pedestal, comprising:a skeleton tower assembly comprising a skeleton tower frame that supports a first wall panel, the first panel comprising a plurality of power receptacles; and
an outer sleeve coupled to the skeleton tower frame,
wherein the outer sleeve terminates adjacent the first wall panel with the plurality of power receptacles facing outward and externally accessible, and
wherein the first wall panel resides at an angle from vertical that is in a range of about 10 and about 30 degrees.

US Pat. No. 10,483,717

LASER POWER ADJUSTMENT DURING TUNING TO COMPENSATE FOR DETECTOR RESPONSE AND VARYING BACKGROUND ABSORPTION

DAYLIGHT SOLUTIONS, INC.,...

1. An assembly for analyzing a sample, the assembly comprising:a detector assembly having a linear response range with an upper bound and a lower bound;
a tunable laser assembly that is tunable over a tunable range, the tunable laser assembly including a gain medium that generates an illumination beam that is directed at the detector assembly; and
a laser controller that dynamically adjusts a laser drive to the gain medium so that the illumination beam has a substantially constant optical power at the detector assembly while the tunable laser assembly is tuned over at least a portion of the tunable range.

US Pat. No. 10,483,711

METHOD AND APPARATUS FOR PROVIDING AMPLIFIED RADIATION

Nufern, East Granby, CT ...

1. An optical fiber amplifying system, the optical fiber amplifying system providing amplified optical radiation having a first amplified wavelength, the optical fiber amplifying system comprisingone or more first amplifying stages together having an output, each of the one or more first amplifying stages comprising a first active optical fiber, the first active optical fiber being configured to amplify radiation at the first amplified wavelength when pumped with pump radiation of a first amplifying stage pump wavelength; and
one or more first optical pump sources, each configured to output radiation of the first amplifying stage pump wavelength, each operatively coupled to one or more of the first active optical fibers of the first amplifying stages;
an intermediate stage having an input operatively coupled to the output of the one or more first amplifying stages and an output, the intermediate stage comprising an intermediate active optical fiber having an intermediate stage amplified wavelength and an intermediate stage pump wavelength, the intermediate stage amplified wavelength being substantially the same as the first amplified wavelength;
a final amplifying stage having an input coupled to the output of the intermediate stage and an output, the final amplifying stage comprising a final active optical fiber, the final active optical fiber being configured to amplify radiation at the first amplified wavelength when pumped with pump radiation of the intermediate stage pump wavelength; and
one or more final optical pump sources together operatively coupled to the final active optical fiber and the intermediate active optical fiber and configured to output radiation of the intermediate stage pump wavelength, the one or more final optical pump sources being configured to be driven by a common voltage source, the one or more final optical pump sources being configured to be switched together, separately from the one or more first optical pump sources, between a low power state sufficient to render the intermediate active optical fiber substantially non-transmissive to radiation of the first amplified wavelength, and a high power state sufficient to render the intermediate active optical fiber substantially transmissive to radiation of the first amplified wavelength, while maintaining the one or more first optical pump sources are in a high power state.

US Pat. No. 10,483,705

ELECTRICAL CONNECTOR AND ELECTRICAL CONNECTION ASSEMBLY

Tyco Electronics (Shangha...

1. An electrical connection assembly for electrically connecting any one of a plurality of battery cells in a battery pack to a circuit board, the electrical assembly comprising:one or more electrical connector modules, each electrical connector module comprising:
a first connector comprising a first connecting portion and a first protruding end portion that are integrally connected with each other;
a second connector comprising a second connecting portion and a second protruding end portion that are integrally connected with each other, the second connecting portion being electrically connected to the first connecting portion; and
a retainer integrally interconnected with the first connector and the second connector;
wherein the second connector and the first connector are independently and separately formed elements;
wherein the first protruding end portion is arranged to protrude from the retainer to electrically connect to a first mating connector; and
wherein the second protruding end portion is arranged to protrude from the retainer to electrically connect to a second mating connector;
a support frame having a plurality of mounting grooves, each of the mounting grooves is configured to removably retain one of the one or more electrical connector modules;
wherein the one or more electrical connector modules are removably retained in the plurality of mounting grooves.

US Pat. No. 10,483,703

CONNECTOR

Molex, LLC, Lisle, IL (U...

1. A connector comprising:a connector main body made from an insulating material formed in a columnar shape extending in an inserting and extracting direction with respect to a counterpart connector;
a contact part that makes contact with a counterpart terminal of the counterpart connector; and
a plurality of terminals made of a conductive material having tail parts connected to wires exposed from the connector main body on the side opposite the contact part,
wherein the terminals are arrayed such that the positions of the tail parts are polygonal in a plan view in a direction perpendicular to the wires around a wire extending in an inserting and extracting direction of the connector main body,
wherein the connector main body includes a tail holding part extending in the axial direction, and
wherein the tail parts of adjacent terminals are exposed in the tail holding part at a different positions in the axial direction.

US Pat. No. 10,483,699

RETRACTABLE CABLE AND CABLE REWIND SPOOL CONFIGURATION

HARMAN PROFESSIONAL, INC,...

1. An apparatus, comprising:a cable spool; and
a drive adaptor configured to turn while a cable is unwound from the cable spool and to lock while the cable spool is rewound.

US Pat. No. 10,483,698

CONNECTOR FOR CONNECTING ANTENNA AND ELECTRONIC DEVICE HAVING THE SAME

Samsung Electronics Co., ...

1. An electronic device comprising:a wireless communication circuit configured to receive wireless communication data; and
a universal serial bus (USB) type-C connector including:
a housing forming an outer surface of the connector,
an opening formed in at least a portion of the outer surface to allow a header-type external connector to be coupled to the connector in a forward direction or a reverse direction, and
a board disposed inside the opening, the board having a first surface on which a plurality of first pins corresponding to the forward direction are arranged and a second surface on which a plurality of second pins corresponding to the reverse direction are arranged,
wherein the plurality of first pins include one or more first ground pins and one or more first signal pins,
wherein the plurality of second pins include one or more second ground pins and one or more second signal pins,
wherein the one or more first signal pins include at least one first signal pin selectively connectable with the wireless communication circuit and a designated function circuit, and
wherein the one or more second signal pins include at least one second signal pin corresponding to the reverse direction of the at least one first signal pin, the at least one second signal pin selectively connectable with the designated function circuit and the wireless communication circuit.

US Pat. No. 10,483,681

INFORMATION HANDLING SYSTEM MOBILE ADAPTER WITH ROTATIONAL CABLE MANAGEMENT

Dell Products L.P., Roun...

1. A mobile peripheral adapter comprising:a first circular housing portion having plural port openings;
a second circular housing portion having a cable opening, the second circular housing portion rotationally coupled to the first circular housing portion;
plural ports disposed at the plural port openings, each port operable to accept a predetermined cable plug;
electronic components disposed in the first circular housing and operable to convert information to one or more protocols for communication through one or more of the plural ports; and
a cable terminating at one end at the electronic components and at an opposing end at a plug, the cable routing from the electronic components into the second circular housing along a cable guide and to the cable opening, the cable extending from the cable opening as rotation of the first and second housing portions brings the cable guide into alignment with the cable opening, the cable retracting into the cable opening as rotation of the first and second housing portions brings the cable guide out of alignment with the cable opening;
wherein the plural ports include at least plural video ports and plural data ports, the plural video and data ports communicating information in a protocol other than a protocol associated with the cable, the video ports coupled to a video circuit board, the data ports coupled to a communication circuit board separate from the video circuit board, the cable having video wirelines coupled directly to the video circuit board that communicate video information and all other wirelines coupled to the communications circuit board, the communication circuit board providing power and ground to the video circuit board through a flexible cable.

US Pat. No. 10,483,661

SYSTEM AND METHOD FOR SEALING ELECTRICAL TERMINALS

TE CONNECTIVITY CORPORATI...

1. A system for sealing an electrical terminal, comprising:(a) a device for sealing a plurality of electrical wires to a wire attachment portion of an electrical terminal, wherein the device further includes:
(i) a shrinkable tubing having a predetermined length, wherein the shrinkable tubing has been placed over the plurality of electrical wires such that one end thereof extends over the wire attachment portion of the electrical terminal;
(ii) a sealant/adhesive, placed within the shrinkable tubing, the sealant/adhesive having a first portion proximate to an edge of the shrinkable tubing and a second portion connected to the first portion, the first portion extends further from an inside surface of the shrinkable tubing than the second portion;
(iii) the sealant/adhesive having a strip of high viscosity sealant/adhesive proximate a strip of low viscosity sealant/adhesive;
(b) wherein upon an application of heat to the device after installation of the device over the electrical terminal, the shrinkable tubing starts to recover, the first portion of the sealant/adhesive flows and seals free ends of the plurality of electrical wires.

US Pat. No. 10,483,660

HOUSING WITH SELF-ORIENTING GROUNDING STUD

CommScope Connectivity Be...

1. A grounding stud arrangement comprising:a grounding stud assembly including a grounding stud extending from a first end to a second end with an anti-rotation flange positioned between the first end and the second end of the grounding stud, the grounding stud including a first attachment feature positioned between the first end of the grounding stud and the anti-rotation flange and further including a second attachment feature positioned between the second end of the grounding stud and the anti-rotation flange; and
a housing including a wall with a hole and an anti-rotation receiver, a portion of the grounding stud positioned within the hole and at least a portion of the anti-rotation flange received by the anti-rotation receiver, the housing further including at least one guide for rotationally orienting the anti-rotation flange with the anti-rotation receiver.

US Pat. No. 10,483,652

MULTI-BEAM ANTENNA AND MULTI-BEAM ANTENNA ARRAY SYSTEM INCLUDING THE SAME

AJOU UNIVERSITY INDUSTRY-...

1. A multi-beam antenna comprising:a dielectric substrate; and
a radiating part which includes a first radiating element and a second radiating element formed on the dielectric substrate so as to radiate electromagnetic waves,
wherein the first radiating element includes a first upper radiating member which is formed on an upper portion of the dielectric substrate at one side based on a first direction of the dielectric substrate, and a first lower radiating member which is formed on a lower portion of the dielectric substrate at the other side based on the first direction of the dielectric substrate, and the second radiating element includes a second upper radiating member which is formed on the upper portion of the dielectric substrate at one side based on a second direction of the dielectric substrate, and a second lower radiating member which is formed on the lower portion of the dielectric substrate at the other side based on the second direction of the dielectric substrate,
the multi-beam antenna further comprising:
a connecting part which includes a semi-ring-shaped first connecting portion that connects the first upper radiating member and the second upper radiating member, and a semi-ring-shaped second connecting portion that connects the first lower radiating member and the second lower radiating member.

US Pat. No. 10,483,651

TRANSMIT-ARRAY ANTENNA COMPRISING A MECHANISM FOR REORIENTING THE DIRECTION OF THE BEAM

RADIALL, Aubervillers (F...

1. A transmit-array radiofrequency antenna comprising:a support;
a transmit-array arranged in a transmission plane, the transmit-array comprising a printed circuit and a plurality of basic cells produced in a central zone of the printed circuit,
at least one focal source, fixed on the support and arranged at the focal length from the array;
a displacement mechanism for moving the transmit-array, the mechanism being connected to the support and being adapted to translationally move the transmit-array in at least one of the two directions in the transmission plane, the displacement mechanism being connected to the printed circuit in its peripheral zone;
wherein the displacement mechanism comprises:
two servomotors;
two first pantograph devices, each comprising two deformable parallelograms each formed by four articulation segments connected pairwise by a flexible articulation forming a pivot link and one of the segments of which is common to the two parallelograms,
in which displacement mechanism, the common segment of each of the two first pantograph devices is connected to one of the two servomotors, whereas one of the segments parallel to the common segment is fixed on the printed circuit in its peripheral zone and the other one of the segments parallel to the common segment is fixed on the support, the connection between each of the common segments with one of the two servomotors being carried out such that one of the servomotors may move the common segment of one of the two first devices and hence move the printed circuit in approximately one of the two directions (X) in the transmission plane, whereas the other one of the servomotors may move the common segment of one of the two first devices and hence move the printed circuit in approximately the other one of the two directions (Y) in the transmission plane.

US Pat. No. 10,483,650

LENSED ANTENNAS FOR USE IN CELLULAR AND OTHER COMMUNICATIONS SYSTEMS

CommScope Technologies LL...

1. A multi-beam antenna, comprising:a radio frequency (“RF”) lens;
a plurality of radiating elements that are orbitally arranged part of the way around a first side of the RF lens,
wherein the radiating elements are arranged in a plurality of rows and columns, where each row extends in a respective arc in a respective one of a plurality of horizontal planes and each column extends in a respective arc in a respective one of a plurality of vertical planes,
wherein the multi-beam antenna is configured for multi-input-multi-output transmission.

US Pat. No. 10,483,647

ANTENNA DEVICE

GEMTEK TECHNOLOGY CO., LT...

1. An antenna device, comprising:a first radiator, configured to radiate a first radio wave comprising a first wavelength value;
a second radiator, configured to radiate a second radio wave comprising a second wavelength value; and
a first reflection board, located between the first radiator and the second radiator;
wherein a first ratio between the first wavelength value and a length value of the first reflection board is less than 0.5, and a second ratio between the second wavelength value and the length value of the first reflection board is greater than 0.5;
wherein a main beam corresponding to the first wavelength value and a main beam corresponding to the second wavelength value points in the same direction.

US Pat. No. 10,483,646

ANTENNA DEVICE

SUMIDA CORPORATION, (JP)...

1. An antenna device comprising:a core formed from a magnetic material;
a terminal mounting unit arranged adjacent to one side of the core, the terminal mounting unit having a sidewall member, the sidewall member including opposite sides and a plurality of through holes, each of the plurality of through holes extending from one of the opposite sides to the other of the opposite sides;
a coil which is arranged on an outer circumference of the core, the coil being a wound conductive wire;
a coil which is arranged on an outer circumference of the core, the coil being a wound conductive wire;
a plurality of elongated terminals which are inserted into the plurality of through holes; and
an electronic component provided on the terminal mounting unit,
wherein the plurality of elongated terminals included a first terminal, and the first terminal is configured with a pin-shaped portion at one end and an outward portion at the other end, and
when the first terminal is inserted into one of the plurality of through holes, the pin-shaped portion and the outward portion of the first terminal are partially exposed outside of the sidewall member.

US Pat. No. 10,483,642

COMPOSITE RIGHT/LEFT-HANDED TRANSMISSION LINE ANTENNA

HUAWEI TECHNOLOGIES CO., ...

1. A composite right/left-handed transmission line antenna, comprising:a first radiator;
a second radiator coupled to the first radiator, wherein the first radiator and second radiator together form a ring shape;
a feed-in point of the first radiator or the second radiator;
a matching circuit coupled to the feed-in point; and
a high-frequency splitter coupled to the first radiator or the second radiator.

US Pat. No. 10,483,641

ANTENNA SWITCH MODULES AND METHODS OF MAKING THE SAME

Skyworks Solutions, Inc.,...

1. An antenna switch module that interconnects a transceiver and an antenna, the module comprising:a first transmit port and a first receive port that operate at a first frequency range;
a second transmit port and a second receive port that operate at a second frequency range;
a plurality of switches that selectively connect the first transmit port, the first receive port, and one of the second transmit port or the second receive port to a common antenna for the first and second transmit and receive ports; and
a resonance impedance circuit that connects at least one of the second transmit port or the second receive port to the antenna, the resonance impedance circuit having components selected to provide a high impedance path when signals are being transmitted at the first frequency range, the resonance impedance circuit including a ¼ wave impedance transformer including a parallel LC circuit component in series with an inductor, the resonance impedance circuit connecting the second transmit port to the antenna and one of the plurality of switches connecting the second receive port to the antenna.

US Pat. No. 10,483,632

DEVICE FOR TRANSMITTING AND/OR RECEIVING RADIOFREQUENCY SIGNALS

INSIGHT SIP, Grasse (FR)...

1. An apparatus for transmitting and/or receiving radiofrequency signals comprising at least a broadband antenna and a substrate; the antenna comprising at least a first radiating surface and being superimposed on the ground plane, the ground plane being located on a first face of the substrate, at least a side tongue of a power supply and at least a side wall connected to at least the first radiating surface, wherein:the antenna comprises at least a second radiating surface excitable by coupling with the first radiating surface,
the side wall is connected to a coupling trace located on a second face of the substrate, the second face opposite to the first face of the substrate, and the side wall and the coupling trace being configured to act as a capacitive coupling between at least the first radiating surface, the second radiating surface and the ground plane, and
wherein the coupling trace is configured to form a coupling capacitor whose value is ?S/e where ? is the dielectric constant of the dielectric material constituting the substrate. S is the surface of the coupling trace and e is the thickness between the coupling trace located on the second face of the substrate and the ground plane located on the first face of the substrate, and
wherein the first face of the substrate is a lower surface of the substrate and the second surface of the substrate is a surface of the substrate above the first face.

US Pat. No. 10,483,628

ANTENNA AND ATTACHMENT METHOD FOR RECHARGEABLE IMPLANTABLE MEDICAL DEVICE

Pacesetter, Inc., Sylmar...

1. An implantable medical device, comprising:a device housing having electronic components therein;
a feedthrough assembly joined to the device housing;
an antenna assembly; and
a header body mounted to the device housing and enclosing the antenna assembly and feedthrough assembly,
the antenna assembly including an inner conductor, an outer conductor and a dielectric material disposed between the inner conductor and the outer conductor, wherein the inner conductor, the dielectric material and the outer conductor are concentrically arranged relative to one another about a longitudinal axis to form a tubular coaxial structure.

US Pat. No. 10,483,610

WAVEGUIDE MOUNT FOR MICROSTRIP CIRCUIT AND MATERIAL CHARACTERIZATION

United States of America ...

1. A superconducting film device comprising:a superconducting microstrip device including:
a silicon substrate disposed on a silicon handling wafer;
a microstrip feed line; and
a plurality of superconducting microstrip resonators and a half-wavelength resonator, disposed on said silicon substrate and coupled to said microstrip feed line;
wherein said silicon substrate is a single-crystal silicon substrate of 50 ?m in thickness.

US Pat. No. 10,483,609

DIELECTRIC WAVEGUIDE HAVING A CORE AND CLADDING FORMED IN A FLEXIBLE MULTI-LAYER SUBSTRATE

Texas Instruments Incorpo...

1. A system comprising:a multilayer substrate having at least a core layer having a first dielectric constant value, a top layer adjacent the core layer and a bottom layer opposite adjacent the core layer, wherein the top layer and the bottom layer have a dielectric constant value that is lower than the first dielectric constant value;
a dielectric waveguide (DWG) formed within the multilayer substrate, wherein the dielectric waveguide comprises:
a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer, such that the dielectric core member has the first dielectric constant value; and
a cladding surrounding the dielectric core member formed by the top layer and the bottom layer infilling the corresponding slot portions of the core layer, wherein the cladding has a dielectric constant value that is lower than the first dielectric constant value.

US Pat. No. 10,483,608

RF DIELECTRIC WAVEGUIDE DUPLEXER FILTER MODULE

CTS Corporation, Lisle, ...

2. An RF dielectric waveguide duplexer filter module for the transmission of Tx and Rx RF signals comprising:an antenna block of dielectric material including an antenna input/output, the antenna block including a plurality of exterior surfaces covered with a layer of conductive material and first and second antenna Tx and Rx signal transmission regions on one of the exterior surfaces defining a direct coupling path for the transmission of the Tx and Rx RF signals;
a Tx RF signal waveguide filter including:
stacked Tx blocks of dielectric material including exterior surfaces covered with a layer of conductive material and defining a plurality of resonators;
a plurality of Tx RF signal transmission regions defined between the stacked Tx blocks defining a direct coupling path for the transmission of the Tx RF signal between the stacked Tx blocks;
a third antenna Tx RF signal transmission region defined on one end exterior surface of one of the Tx blocks defining a direct coupling path for the transmission of the Tx RF signal from the one of the Tx blocks into the antenna block; and
a Tx RF signal input/output defined on one of the Tx blocks;
an RF Rx signal waveguide filter including:
stacked Rx blocks of dielectric material including exterior surfaces covered with a layer of conductive material and defining a plurality of resonators;
a plurality of Rx RF signal transmission regions defined between the Rx blocks defining a direct coupling path for the transmission of the Rx RF signal between the stacked Rx blocks;
a fourth antenna Rx RF signal transmission region defined on one end exterior surface of one of the Rx blocks defining a direct coupling path for the transmission of the Rx RF signal from the antenna block into the one of the Rx blocks;
an Rx RF signal input/output defined on one of the Rx blocks; and
the Tx and Rx RF signal waveguide filters being attached in side-by-side relationship and the antenna block being attached to the Tx and Rx blocks of the respective Tx and Rx signal waveguide filters in a side-by-side relationship along the end of the Tx and Rx signal blocks with the respective antenna Tx and Rx signal transmission regions.

US Pat. No. 10,483,602

BATTERY HOUSING FOR A LITHIUM-ION BATTERY

FORD GLOBAL TECHNOLOGIES,...

1. A vehicle comprising:an engine disposed within an engine compartment;
a traction motor coupled to a battery; and
a housing disposed within the engine compartment and containing the battery, the housing comprising a shell having solid thermal insulation surrounding the battery and forming first and second slots between the battery and the shell, the first slot being configured for connecting to ambient, and the second slot being configured for connecting to a vehicle cooling system, wherein the housing further comprises braces between the shell and the solid thermal insulation.

US Pat. No. 10,483,597

FIBER-CONTAINING MATS WITH ADDITIVES FOR IMPROVED PERFORMANCE OF LEAD ACID BATTERIES

Johns Manville, Denver, ...

1. A fiber-containing mat for a lead acid battery, the mat comprising:a plurality of fibers;
a binder holding the plurality of fibers together in the fiber-containing mat; and
one or more additives incorporated into the fiber-containing mat, wherein the one or more additives comprise benzyl benzoate.

US Pat. No. 10,483,596

SECONDARY BATTERY WITH HYDROXIDE-ION-CONDUCTING CERAMIC SEPARATOR

NGK Insulators, Ltd., Na...

1. A secondary battery comprising:a positive electrode;
a negative electrode;
an alkaline electrolytic solution;
a ceramic separator that is composed of a hydroxide-ion-conductive inorganic solid electrolyte comprising a layered double hydroxide and separates the positive electrode from the negative electrode;
a porous substrate disposed on at least one surface of the ceramic separator; and
a container accommodating at least the negative electrode and the alkaline electrolytic solution,
wherein the inorganic solid electrolyte is in the form of a membrane or layer densified enough to have water impermeability, and the porous substrate has a thickness of 100 to 1,800 ?m.

US Pat. No. 10,483,594

POSITIVE ELECTRODE PLATES FOR NONAQUEOUS ELECTROLYTE SECONDARY BATTERIES, AND NONAQUEOUS ELECTROLYTE SECONDARY BATTERIES

PANASONIC CORPORATION, K...

1. A positive electrode plate for wound nonaqueous electrolyte secondary batteries, comprising:a current collector, and
a mixture layer disposed on the current collector,
the mixture layer having a thin portion with a thickness of less than 200 ?m disposed on an inner coil half of the current collector and a thick portion having a larger thickness than the thin portion, the thick portion having a yield loop height H measured by a stiffness test of 6 mm

US Pat. No. 10,483,590

ELECTROLYTE FOR LITHIUM ION BATTERY AND LITHIUM ION BATTERY INCLUDING THE SAME

OPTIMUM BATTERY CO., LTD....

1. An electrolyte for lithium ion battery, comprising:a mixture of organic solvents consisting of ethylene carbonate, ethyl methyl carbonate, dimethyl carbonate and carboxylate ester, wherein a mass ratio of ethylene carbonate, ethyl methyl carbonate, dimethyl carbonate and carboxylate ester is (20%-30%):(45%-55%):(10%-20%):(5%-15%);
a mixture of additives consisting of vinylene carbonate, propane sultone, fluorinated ethylene carbonate and perfluorohexylsulfonyl fluoride; and
a lithium salt.

US Pat. No. 10,483,585

ION-CONDUCTING GLASS CERAMIC HAVING GARNET-LIKE CRYSTAL STRUCTURE

SCHOTT AG, Mainz (DE)

1. A lithium-ion conducting glass ceramic comprising a garnet-like main crystal phase having an amorphous proportion of at least 5 wt.-%, wherein said garnet-like main crystal phase has the chemical formula:Li7+x?yMxIIM3?xIIIM2?yIVMyVO12,
wherein MII is a bivalent cation, MIII a trivalent cation, MIv a tetravalent cation, and MV a pentavalent cation.

US Pat. No. 10,483,582

SEMI-SOLID ELECTRODES HAVING HIGH RATE CAPABILITY

24M Technologies, Inc., ...

1. An electrochemical cell, comprising:an anode; and
a cathode;
wherein at least one of the anode and the cathode is a slurry electrode that includes about 35% to about 75% by volume of an active material and a conductive carbon in an electrolyte,
wherein the electrochemical cell has an area specific capacity of at least 7 mAh/cm2 at a C-rate of C/4, and
wherein the electrolyte is a liquid at room temperature.

US Pat. No. 10,483,579

SOLID OXIDE FUEL CELL

NISSAN MOTOR CO., LTD., ...

1. A solid oxide fuel cell comprising:a metal support which is formed from a porous metal substrate and which supports a power generation cell, wherein
the metal support includes a power generating area in which the power generation cell is disposed, a buffer area which is formed on an outer side of the power generating area in an in-plane direction, and an outer peripheral area which is formed on an outer side of the buffer area in the in-plane direction, the metal support is located on the anode side of the power generation cell, a separator is located on the anode side of the power generation cell such that a void region is formed between the separator and the buffer area of the metal support,
the power generation cell is formed as a stacked body of an anode electrode, a solid oxide electrolyte, and a cathode electrode, and
a pore in the metal support in the buffer area is filled with a filler material with a thermal conductivity lower than that of a formation material of the metal support.

US Pat. No. 10,483,577

COMPOSITE POLYMER ELECTROLYTE MEMBRANE, AND CATALYST-COATED MEMBRANE, MEMBRANE ELECTRODE ASSEMBLY, AND POLYMER ELECTROLYTE FUEL CELL USING THE COMPOSITE POLYMER ELECTROLYTE MEMBRANE

Toray Industries, Inc., ...

1. A composite polymer electrolyte membrane comprising:a composite layer of an aromatic hydrocarbon-based polymer electrolyte and a fluorine-containing polymer porous membrane, wherein
a ratio (O/F ratio) of an atomic composition percentage of oxygen O (at %) to an atomic composition percentage of fluorine F (at %) on an outermost surface of the fluorine-containing polymer porous membrane as measured by X-ray photoelectron spectroscopy (XPS) is 0.20 or more to 2.0 or less, and
the aromatic hydrocarbon-based polymer electrolyte in the composite layer forms a phase separation structure.

US Pat. No. 10,483,563

CATHODE SUPPLY FOR A FUEL CELL

Volkswagen AG, Wolfsburg...

1. A cathode supply for a fuel cell of a fuel cell unit for a fuel cell system, the cathode supply comprising:a cathode supply path;
a cathode exhaust gas path; and
at least two fluid pumps for pumping a cathode operating medium for the fuel cell being fluido-mechanically coupled into the cathode supply path;
at least one first fluid pump of the at least two fluid pumps being drivable by enthalpy in a cathode exhaust gas of the fuel cell.

US Pat. No. 10,483,561

FLAT PLATE-SHAPED SOLID OXIDE FUEL CELL AND CELL MODULE COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A flat plate-shaped solid oxide fuel cell comprising:a porous ceramic support;
a fuel electrode provided on the porous ceramic support;
an electrolyte layer provided on the fuel electrode;
an air electrode provided on the electrolyte layer; and
a fuel electrode current collector connected to the fuel electrode and extending in a direction away from the air electrode.

US Pat. No. 10,483,557

LAMINATE-TYPE POWER STORAGE ELEMENT AND CARD ELECTRONIC DEVICE

FDK Corporation, Tokyo (...

1. A laminate-type power storage element, comprising:an exterior body that is formed in a flat bag shape by welding a first laminated film and a second laminated film by thermocompression bonding; and
an electrode body that is sealed inside the exterior body, the electrode body having a sheet-shaped positive electrode and a sheet-shaped negative electrode, wherein
the first laminated film and the second laminated film each includes
a first resin layer that has a property of transmitting a laser beam,
a metal foil that is layered to the first resin layer, and
a second resin layer that is layered to the metal foil and has a thermal weldability,
the exterior body is configured such that the second resin layer of the first laminated film opposes the second resin layer of the second laminated film,
a label is formed in a surface of the metal foil facing the first resin layer of at least on of the first laminated film or the second laminated film by laser marking without altering the first resin layer of the first laminated film or the second laminated film by the laser beam, and
the label is formed at a region where the first laminated film and the second laminated film are welded.

US Pat. No. 10,483,552

CATALYST COMPRISING COBALT CORE AND CARBON SHELL FOR ALKALINE OXYGEN REDUCTION AND METHOD FOR PREPARING THE SAME

Korea Institute of Scienc...

1. A method for preparing a catalyst, consisting of:(a) preparing a dispersion by dispersing a carbon support in a solvent;
(b) preparing a mixture solution by mixing the dispersion with a cobalt precursor and oleylamine;
(c) preparing a catalyst precursor by heat-treating the mixture solution at a low temperature of 250-350° C. under an inert gas atmosphere, wherein an oleylamine-coated cobalt oxide nanoparticle is supported on the carbon support in the catalyst precursor; and
(d) preparing a catalyst by heat-treating the catalyst precursor at a high temperature of 550-800° C. under the inert gas atmosphere, wherein the catalyst contains the carbon support and a core-shell nanoparticle supported on the carbon support,
wherein the core of the core-shell nanoparticle is cobalt metal without having the heterogeneous element and the shell of the core-shell contains carbon.

US Pat. No. 10,483,550

HIGH TEMPERATURE SOLID OXIDE CELL COMPRISING DIFFUSION BARRIER LAYER AND METHOD FOR MANUFACTURING THE SAME

Korea Institute of Scienc...

1. A method for manufacturing a solid oxide cell, comprising the steps of:(a) preparing a fuel electrode support;
(b) coating an electrolyte layer on the fuel electrode support;
(c) sintering the fuel electrode support and the electrolyte layer at the same time;
(d) coating a paste containing nanopowder and macropowder of a ceria-based metal oxide on the electrolyte layer to form a first coating layer;
(e) coating a mixed paste containing a ceria-based metal oxide and a sintering aid on the first coating layer to form a second coating layer;
(f) sintering the first coating layer and the second coating layer at the same time to provide a bilayer type diffusion barrier layer having a densified structure comprising a first diffusion barrier layer and a second diffusion barrier layer formed on the first diffusion barrier layer; and
(g) forming an air electrode layer on the bilayer type diffusion barrier layer.

US Pat. No. 10,483,548

ELECTRON COLLECTOR STRUCTURE AND LITHIUM BATTERY CONTAINING THE SAME

Samsung SDI Co., Ltd., G...

1. An electron collector structure, comprising:a conductive thin film; and
a graphene layer consisting of one or more graphene sheets, the graphene layer partially coated on a top surface of the conductive thin film such that a portion of the conductive thin film is not coated by the graphene layer, and
an electrode active material layer disposed on the graphene layer and directly contacting the portion of the conductive thin film that is not coated by the graphene layer;
wherein the graphene layer is coated on an area in the range of about 50% or less of the top surface of the conductive thin film, and wherein the thickness of the graphene layer is less than 200 nm.

US Pat. No. 10,483,538

MIXED OXIDE CONTAINING A LITHIUM MANGANESE SPINEL AND PROCESS FOR ITS PREPARATION

Johnson Matthey Public Li...

1. A mixed oxide containinga) a mixed-substituted lithium manganese spinel as a first constituent in which a first portion of the manganese lattice sites are occupied by lithium ions and
b) a boron-oxygen compound as a second constituent,
wherein the mixed oxide is a single-phase homeotype mixed crystal comprising the constituents a) and b), wherein the second constituent is in the same phase as the first constituent, and
wherein the mixed oxide has a composition satisfied by the following formula:
[(Li1-aMa)(Mn2-c-dLicGd)Ox].(bB2O3.f*bLi2O)
wherein:
0?a<0.1;
d<1.2;
3.5 0.01 0 1 M is at least one element selected from the group of Zn, Mg and Cu; and
G is at least one element selected from the group of Al, Mg, Zn, Co, Ni, Cu and Cr; and
wherein in the mixed-substituted lithium manganese spinel an element of G occupying a second portion of the manganese lattice sites is Ni or Co, wherein when Ni is present, the contribution of Ni to “d” is 0.5+/?0.1 or when Co is present, the contribution of Co to “d” is 1+/?0.2, and
the size of the primary crystallites of the mixed oxide, measured as D50, is at least 0.5 ?m.

US Pat. No. 10,483,532

BINDER-FREE AND CARBON-FREE NANOPARTICLE CONTAINING COMPONENT, METHODS AND APPLICATIONS

CORNELL UNIVERSITY, Itha...

1. An electrochemical apparatus comprising:a component comprising:
a substrate; and
a hollow core morphology transition metal based nanoparticle material layer located over the substrate and absent a binder material, absent a polymeric material, and absent a carbon material, wherein the hollow core morphology transition metal based nanoparticle material layer is first formed upon the substrate as a solid core morphology transition metal based nanoparticle material layer using an electrophoretic deposition method, and wherein the solid core morphology transition metal based nanoparticle material layer adhered upon the substrate is treated to provide the hollow core morphology transition metal based nanoparticle material layer;
wherein the electrochemical apparatus is selected from the group consisting of a battery, a fuel cell, a capacitor and a catalytic reactor.

US Pat. No. 10,483,530

CATHODE ACTIVE MATERIAL AND FLUORIDE ION BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A cathode active material used in a fluoride ion battery, the cathode active material comprising:a Ce element, a S element, and a F element; and
a composition represented by CeSF.

US Pat. No. 10,483,525

NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY

SANYO Electric Co., Ltd.,...

1. A non-aqueous electrolyte secondary battery comprising a positive electrode, a negative electrode, and a non-aqueous electrolyte, whereinthe negative electrode includes a negative electrode current collector and a negative electrode mixture layer formed on the current collector,
the negative electrode mixture layer contains a water-soluble polymer and a negative electrode active material containing a silicon-based active material,
the water-soluble polymer includes 70% by mass or more of acrylamide, 0.30 mol/100 g or more and 0.40 mol/100 g or less of an acrylic acid monomer unit and 10?4 mol/100 g or more and 10?3 mol/100 g or less of a tetrafunctional (meth)acrylate monomer unit, and an aqueous solution containing 1% by mass of the polymer in terms of solid content has a viscosity of 0.05 Pa·s or higher and 0.70 Pa·s or lower.

US Pat. No. 10,483,523

DUAL FUNCTION CURRENT COLLECTOR

American Lithium Energy C...

1. A battery, comprising:a separator;
a first current collector;
a protective layer disposed on the first current collector, the protective layer comprising a polymer and/or a polymer composite that is impenetrable to dendrites comprising a first electrode that is formed in situ between the protective layer and the first current collector, the first current collector and the protective layer being disposed on one side of the separator, and the protective layer being non-ionically conductive in an absence of an electrolyte; and
a second electrode, the second electrode being disposed on an opposite side of the separator as the first current collector and the protective layer;
wherein subjecting the battery to an activation process causes metal to be extracted from the second electrode and deposited between the first current collector and the protective layer, wherein the deposit of the metal forms the first electrode between the first current collector and the protective layer, and wherein the protective layer prevents the dendrites comprising the first electrode from penetrating the separator.

US Pat. No. 10,483,520

BATTERY CELL COMPRISING A FIRST TERMINAL ARRANGED INSIDE A SECOND TERMINAL

Robert Bosch GmbH, Stutt...

1. A battery cell (10) having a first terminal (1) which is electrically conductively connected to a first electrode and a second terminal (2) which is electrically conductively connected to a second electrode, wherein the first terminal (1) is arranged within the second terminal (2), wherein the first terminal (1) comprises a first screw thread (1a) and the second terminal (2) comprises a second screw thread (2a), wherein the second screw thread is positioned around the first screw thread.

US Pat. No. 10,483,514

DECOUPLED ALIGNMENT SHROUD FOR VARIABLE CONNECTOR ROUTING

Vitesco Technologies USA,...

1. A connector system for a hybrid motor vehicle, the connector system comprising:a leadframe configured to provide an electrical and mechanical connection between a power inverter and a battery system of an electric motor, the leadframe having at least one leadframe alignment feature;
a shroud configured to connect the leadframe to the battery system, the shroud being removably attached to the leadframe, the shroud having at least one shroud alignment feature, the shroud being removably attached to the leadframe in a predetermined orientation wherein the at least one shroud alignment feature is aligned with the at least one leadframe alignment feature, the shroud comprises:
at least one connecting feature attaching the shroud to the leadframe, and
a wall shaped as a hollow cylinder, the wall defining an opening along a height of the wall,
a bolt extending from the leadframe;
a power inverter electrically and mechanically connected to the leadframe,
a battery system connector attached to the shroud,
wherein the shroud defines a hollow interior within the wall and the bolt extends into the hollow interior, the at least one shroud alignment feature comprises a first shroud alignment feature disposed along a first line and a second shroud alignment feature disposed along a second line, the first and second lines having an angle of about 120 degrees therebetween as measured from a center of the shroud.

US Pat. No. 10,483,513

ASYMMETRICAL SEPARATOR

CARL FREUDENBERG KG, Wei...

1. An asymmetric separator comprising:a base having two sides, wherein each side independently contacts an electrode of a battery, wherein the base comprises a nonwoven, wherein the base is coated on one of the two sides with a first material mixture and is coated on another of the two sides with a second material mixture,
wherein the two coated sides have a different material consistency and the first material mixture and the second material mixture at least partially penetrate into the nonwoven,
wherein the first material mixture comprises Al2O3 particles configured to set a porosity of the side coated with the first material mixture,
wherein the second material mixture comprises polyvinylidene fluoride particles having a mean particle size in a range from 0.2 ?m to 10 ?m and binder particles,
wherein the polyvinylidene fluoride particles are configured to set a porosity of the side coated with the second material mixture,
wherein at least a portion of the polyvinylidene fluoride particles is disposed on an outer surface of the side coated with the second material mixture so as to enable direct contact with the electrode in contact with the side coated with the second material mixture,
wherein the polyvinylidene fluoride particles are bound to the nonwoven using the binder particles,
wherein the nonwoven has a melting point higher than 140° C., and
wherein the separator has a maximum shrinkage of 5% at a temperature of 150° C.

US Pat. No. 10,483,511

METHOD FOR INSULATING A BATTERY MODULE

Robert Bosch GmbH, Stutt...

1. A method for insulating a battery module (100) which has a multiplicity of battery cells (10), having at least one foldable insulation element (20), the method comprising at least the following steps:a) forming from the insulation element (20) a first receptacle pocket (21) for receiving at least one battery cell (10),
b) closing the first receptacle pocket (21) by means of attachment sections (22) which are arranged laterally on the insulation element (20), as a result of which the battery cell (10) is surrounded at least on five sides by the insulation element (20), as a result of which the individual battery cell (10) is insulated with respect to an adjacent battery cell (10),
c) forming from the insulation element a second receptacle pocket for receiving the adjacent battery cell, the second receptacle pocket formed from the same insulation element as the first receptacle pocket, the second receptacle pocket formed adjacent to and seamlessly connected to the first receptacle pocket via the insulation element, and
d) closing the second receptacle pocket (21) by means of second attachment sections (22) which are arranged laterally on the insulation element (20) such that the adjacent battery cell (10) is surrounded at least on five sides by the insulation element (20) and is insulated with respect to an adjacent battery cell (10).

US Pat. No. 10,483,507

INSULATING OF ADJACENT LITHIUM-ION BATTERIES BY COMPLETE OVERMOULDING/POURING OF CONTAINERS IN A DEVICE

Robert Bosch GmbH, Stutt...

1. A cell module for lithium ion batteries, comprising:at least two lithium ion cells;
a cell module housing having at least one side wall;
at least one electrical insulation disposed between the cells, the insulation configured in one piece with the cell module housing; and
operating electronics contained in one or more of the insulation and the cell module housing.

US Pat. No. 10,483,496

ELECTROLUMINESCENT DEVICES WITH IMPROVED OPTICAL OUT-COUPLING EFFICIENCIES

NATIONAL TAIWAN UNIVERSIT...

1. An organic electroluminescent device, comprising:an optically reflective concave structure, comprising:
a first optically reflective surface; and
a second optically reflective surface, intersecting said first optically reflective surface at an obtuse angle;
a first light propagation layer in direct contact with said first optically reflective surface and said second optically reflective surface, comprising:
a first refractive surface, parallel to and separated from said first optically reflective surface;
a second refractive surface, parallel to and separated from said second optically reflective surface; and
an electroluminescent area, disposed entirely within said first light propagation layer, between said first optically reflective surface and said first refractive surface, without directly contacting any of said first optically reflective surface, said second optically reflective surface, said first refractive surface and said second refractive surface; and
a second light propagation layer, disposed on the first light propagation layer, wherein said second light propagation layer has a greater refractive index than said electroluminescent area minus 0.2.

US Pat. No. 10,483,493

ELECTRONIC DEVICE HAVING DISPLAY WITH THIN-FILM ENCAPSULATION

Apple Inc., Cupertino, C...

1. Apparatus, comprising:a glass substrate;
a thin-film encapsulation layer;
a layer of thin-film transistor circuitry including transistors and organic light-emitting diodes that is configured to form a pixel array that displays images, wherein the layer of thin-film transistor circuitry has a first surface that contacts the thin-film encapsulation layer and an opposing second surface that contacts the glass substrate;
a light-blocking layer, wherein the glass substrate layer has a first surface that is contacted by the thin-film transistor circuitry and has a second surface that is contacted by the light-blocking layer; and
a heat spreading layer, wherein the light-blocking layer is interposed between the heat spreading layer and the glass substrate.

US Pat. No. 10,483,486

FRAME SEALING GLUE, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A frame sealing glue, comprising:a frame sealing glue body having an inner layer portion and an outer layer portion; and
an intermediate film layer disposed between the inner layer portion and the outer layer portion;
wherein a plurality of enclosed spaces are formed by the intermediate film layer and the inner layer portion or the outer layer portion of the frame sealing glue body,
wherein the intermediate film layer comprises a wave-shaped curved line having a plurality of semicircular curved line portions, the wave-shaped curved line forming a discontinuous curved line such that the intermediate film layer is disconnected at a corner of an enclosed frame formed by the frame sealing glue,
wherein a peak and a valley of the wave-shaped curved line intersect with the inner layer portion and the outer layer portion of the frame sealing glue body, respectively, or with the outer layer portion and the inner layer portion of the frame sealing glue body, respectively,
wherein each of the inner layer portion and the outer layer portion is a continuous closed line, and
wherein the intermediate film layer is made of different material from the frame sealing glue body.

US Pat. No. 10,483,483

ELECTROLUMINESCENT DEVICE AND ELECTROLUMINESCENT DISPLAY DEVICE INCLUDING THE SAME

LG Display Co., Ltd., Se...

1. An electroluminescent device comprising:an anode and a cathode facing each other;
a light compensation layer located between the anode and the cathode, the light compensation layer having a first refractive index;
an emitting material layer located between the light compensation layer and the cathode, the emitting material layer having a second refractive index higher than the first refractive index; and
a hole injection layer located between the emitting material layer and the light compensation layer or between the light compensation layer and the anode, wherein the hole injection layer has a third refractive index higher than the first refractive index, and
wherein the light compensation layer has a thickness smaller than a thickness of the emitting material layer and a thickness of the hole injection layer.

US Pat. No. 10,483,479

METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DEVICE AND ORGANIC LIGHT EMITTING DEVICE

PIONEER CORPORATION, Tok...

1. A method of manufacturing a light emitting device, the method comprising:a first step of coating a first region of a substrate, in which a first light emitting unit is formed, with a first solution comprising a light emitting material;
a second step of coating a second region of a substrate, in which a second light emitting unit is formed, with a second solution comprising a coating material, before or after the first step;
a third step of drying the first solution in the first region and the second solution in the second region after the first step and the second step; and
a fourth step of depositing a light emitting material in the second region after the third step.

US Pat. No. 10,483,477

EXCITED STATE MANAGEMENT

THE REGENTS OF THE UNIVER...

1. An emissive layer of an opto-electronic device, the emissive layer comprising:a host material;
a first dopant; and
a second dopant that has a solid state sink energy level,
wherein the first dopant is a blue-emitting, phosphorescent dopant that has a triplet energy level T1 that is lower than the solid state sink energy level of the second dopant, wherein the solid state sink energy level is at least 0.2 eV below the multiply-excited energy level of the first dopant, and
wherein the emissive layer is disposed between an electron-transport layer (ETL) and a hole-transport layer (HTL), and the concentration of the first dopant is graded within the host material from about 20% at the HTL/emitting layer interface to about 8% at the ETL/emitting layer interface.

US Pat. No. 10,483,466

P-DOPING CROSS-LINKING OF ORGANIC HOLE TRANSPORTERS

SIEMENS AKTIENGESELLSCHAF...

1. A method for producing hole-transporting electrical layers, the method comprising:providing a substrate;
providing at least one crosslinking reagent; and
reacting a functionalized organic matrix compound with the at least one crosslinking reagent on the substrate to form compounds of relatively high molecular mass,
wherein the functionalized organic matrix compound conforms to formula 1:

where:
L is a bond or is selected from the group consisting of substituted or nonsubstituted, saturated or unsaturated C1-C50 alkyl, aryl, polyethylene glycol, polyethylenediamine, polyester, polyurethane, polyvinylidenephenyl chains, and mixtures thereof;
E1, E2 independently of one another may be oxygen, sulfur, selenium, NH or NE3,
optionally E3, wherein E3 is selected from the group consisting of substituted or nonsubstituted alkyl and aryl, and E3 is bound to R as follows:

R is selected from the group consisting of H, D, C1-C10 alkyl-silyl or aryl-silyl esters, fluorinated or nonfluorinated branched or unbranched C1-C10 alkyl, aryl, and heteroaryl,
RHTL is selected from the group consisting of PEDOT (poly(3,4-ethylenedioxythiophene)), PVK (poly(9-vinylcarbazole)), PTPD (poly(N,N?-bis(4-butylphenyl)-N,N?-bis(phenyl)benzidine)), PANI (polyaniline), P3HT (poly(3-hexylthiophene)), and mixtures thereof, and
the crosslinking reagent comprises at least one metal atom from groups 13-15 and at least one organic ligand.

US Pat. No. 10,483,462

FORMATION OF STRUCTURALLY ROBUST NANOSCALE AG-BASED CONDUCTIVE STRUCTURE

Crossbar, Inc., Santa Cl...

1. A selector device, comprising:a first metal containing layer wherein the first metal containing layer is configured to provide a first plurality of metal particles;
a second metal containing layer wherein the second metal containing layer is configured to provide a second plurality of metal particles; and
a selector material layer disposed between and in contact to the first metal containing layer and the second metal containing layer, wherein the selector material layer comprises a plurality of defect regions configured to receive the first plurality of metal particles and form a first conductive filament through the selector material layer in response to a first polarity stimulus applied to the selector device, and to receive the second plurality of metal particles and form a second conductive filament through the selector material layer in response to a second polarity stimulus applied to the selector device, wherein the first metal containing layer includes an alloy of silver.

US Pat. No. 10,483,449

THERMOELECTRIC GENERATOR

AVX Corporation, Fountai...

1. A thermoelectric device for converting thermal energy to electrical energy based on temperature differences between portions of the device, comprising:a plurality of N-type oxide ceramic elements comprising an N-type ceramic material;
a plurality of P-type oxide ceramic elements comprising a P-type ceramic material and respectively paired with said plurality of N-type elements;
a pair of supporting generally planar ceramic substrates, supporting a plurality of conductive traces thereon, and with said paired N-type and P-type elements received on selected of said conductive traces so as to form an array of such pairs captured between said substrates;
insulating foam potting material captured between said substrates in between said array pairs; and
at least one pair of connection terminals provided on at least one of said substrates, and associated lead wires respectively connected thereto;
wherein said paired elements are electrically connected in series by said conductive traces and thermally connected in parallel relative to said substrates, so that generated electricity may be conducted from such array based on temperature differences between portions of said paired elements based on the Peltier/Seebeck effect, and wherein said plurality of N-type elements and said plurality of P-type elements comprise a plurality of porosity layers, the plurality of porosity layers being spaced apart in a heat-flow direction perpendicular to said generally planar ceramic substrates, the plurality of porosity layers having thicknesses in the heat-flow direction that range from 1 micron to 100 microns, and wherein the plurality of porosity layers comprise pores formed inside the N-type ceramic material and P-type ceramic material.

US Pat. No. 10,483,448

FLEXIBLE THERMOELECTRIC DEVICES, METHODS OF PREPARATION THEREOF, AND METHODS OF RECOVERING WASTE HEAT THEREWITH

North Carolina State Univ...

1. A flexible thermoelectric device comprising:a flexible substrate having a surface;
a first conductive ink having a Seebeck coefficient; and
a second conductive ink having a Seebeck coefficient that is different from the Seebeck coefficient of the first conductive ink;
wherein each of the first conductive ink and the second conductive ink independently comprises a carrier and conductive particles;
wherein each of the first conductive ink and the second conductive ink independently has a resistance that is no more than two orders of magnitude greater than the resistance of the conductive particles alone;
wherein the first conductive ink and the second conductive ink are arranged on the surface of the flexible substrate so as to form a series of thermopile junctions; and
wherein the flexible substrate is shaped such that alternating thermopile junctions are positioned so as to be spaced apart from intervening thermopile junctions.

US Pat. No. 10,483,447

STRUCTURES, SYSTEM AND METHOD FOR CONVERTING ELECTROMAGNETIC RADIATION TO ELECTRICAL ENERGY

Redwave Energy, Inc., Bo...

1. A system for converting electromagnetic energy emitted by heat from hot gases into electricity comprising a composite stack, the composite stack comprising a plurality of vertically stacked composite stack rings, wherein each composite stack ring comprises a plurality of composite ring elements, wherein each composite ring element has an interior region through which the hot gases flow, wherein each composite ring element has a plurality of similarly shaped, concentric layers, and wherein each composite ring element comprises a converting layer that converts the electromagnetic energy to electricity, wherein each composite ring element has a wedge shape.

US Pat. No. 10,483,444

METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT, OPTOELECTRONIC SEMICONDUCTOR COMPONENT, AND TEMPORARY CARRIER

OSRAM Opto Semiconductors...

1. A method of producing an optoelectronic semiconductor component comprising:providing a carrier comprising two metal layers, wherein the metal layers are detachable from one another,
applying a photoresist on the first metal layer,
patterning the photoresist such that regions composed of the photoresist comprising a predefined cross section are present on the first metal layer,
electrolytically applying a further metal on free regions of the first metal layer not covered by the photoresist, wherein the further metal comprises a greater thickness than the photoresist and partly projects laterally beyond regions of the photoresist,
removing the photoresist, wherein a body composed of the further metal arises, said body comprising a laterally projecting upper edge region,
securing an optoelectronic semiconductor chip on the further metal, and
mechanically detaching the second metal layer from the first metal layer.

US Pat. No. 10,483,440

CADMIUM-FREE QUANTUM DOT NANOPARTICLES

Nanoco Technologies Ltd.,...

1. A quantum dot nanoparticle comprising:a core having an etched surface and comprising indium, phosphorus, magnesium, zinc, and sulfur;
a first shell disposed on the etched surface of the core; and
a second shell disposed on the first shell,
wherein the quantum dot nanoparticle emits light in the green region of the visible spectrum.

US Pat. No. 10,483,407

METHODS OF FORMING SI3NX, METHODS OF FORMING INSULATOR MATERIAL BETWEEN A CONTROL GATE AND CHARGE-STORAGE MATERIAL OF A PROGRAMMABLE CHARGE-STORAGE TRANSISTOR, AND METHODS OF FORMING AN ARRAY OF ELEVATIONALLY-EXTENDING STRINGS OF MEMORY CELLS AND A PROGRA

Micron Technology, Inc., ...

1. A method of forming Si3Nx, where “x” is less than 4 and at least 3, comprising:decomposing a Si-comprising precursor molecule into at least two decomposition species that are different from one another within a chamber having a chamber pressure of from 100 to 500 mTorr, at least one of the at least two different decomposition species comprising Si;
after the decomposing the Si-precursor molecule, contacting an outer substrate surface with the at least two decomposition species, at least one of the decomposition species that comprises Si attaching to the outer substrate surface to comprise an attached species; and
after the contacting the outer substrate surface, contacting the attached species with a N-comprising precursor that reacts with the attached species to form a reaction product comprising Si3Nx, where “x” is less than 4 and at least 3.

US Pat. No. 10,483,402

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:an oxide semiconductor film comprising a channel formation region of a transistor;
a gate insulating film over the oxide semiconductor film;
a gate electrode over the gate insulating film;
an interlayer insulating film over the gate electrode;
a source electrode electrically connected to the oxide semiconductor film through a first opening in the interlayer insulating film; and
a drain electrode electrically connected to the oxide semiconductor film through a second opening in the interlayer insulating film,
wherein, in a cross section in a channel width direction of the transistor, the gate electrode continuously covers a first side surface, a top surface, and a second side surface of the oxide semiconductor film, and
wherein a thickness of the oxide semiconductor film is twice or more a length of the oxide semiconductor film in the channel width direction.

US Pat. No. 10,483,392

CAPACITIVE TUNING USING BACKSIDE GATE

QUALCOMM Incorporated, S...

1. A balanced radio frequency (RF) integrated circuit (RFIC) including a stack of switch multi-finger transistors, comprising:a first dual gate transistor having a first gate with a first gate length on a first side of a substrate, and a second gate with a second gate length on a second side of the substrate;
a second dual gate transistor having a third gate with a third gate length on the first side of the substrate, and a fourth gate with a fourth gate length on the second side of the substrate, in which the second gate length is different than the fourth gate length, and the second dual gate transistor is coupled in series with the first dual gate transistor in the RFIC; and
a dielectric layer on the second side of the substrate and in contact with the second gate and the fourth gate.

US Pat. No. 10,483,387

LATERAL/VERTICAL SEMICONDUCTOR DEVICE WITH EMBEDDED ISOLATOR

Sensor Electronic Technol...

1. A lateral/vertical device comprising:a device structure including a device channel, wherein the device channel includes a lateral portion, a vertical portion, and a transition region between the lateral portion and the vertical portion;
a first contact to the lateral portion of the device channel;
a second contact to the vertical portion of the device channel, wherein the first and second contacts are located on opposing surfaces of the device structure;
a set of insulating layers having a resistivity above 1010 Ohm×cm and located in the device structure between the lateral portion of the device channel and the second contact, wherein an opening in the set of insulating layers defines the transition region of the device channel; and
a channel layer located between the set of insulating layers and the second contact, and within the opening in the set of insulating layers.

US Pat. No. 10,483,377

DEVICES AND METHODS OF FORMING UNMERGED EPITAXY FOR FINFET DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a device having at least one source, at least one drain, and at least one fin on a semiconductor layer;
a first dielectric layer over the device and positioned around at least a portion of the at least one fin;
a first layer of epitaxial growth on the at least one fin, the first layer of epitaxial growth including a first top surface, a first side surface extending away from the first top surface in a first direction at an angle toward the semiconductor layer, and a second side surface extending away from the first top surface in a second direction at an angle toward the semiconductor layer;
second dielectric layer over the first dielectric layer, the second dielectric layer positioned around at least a portion of the first layer of epitaxial growth and at least a portion of the at least one fin;
a second layer of epitaxial growth superimposing the first layer of epitaxial growth;
a first contact region over the at least one source; and
a second contact region over the at least one drain,
wherein the second interlayer dielectric layer contacts the first side surface of the first layer of epitaxial growth and the second side surface of the first layer of epitaxial growth.

US Pat. No. 10,483,374

ELECTRONIC DEVICE INCLUDING TRANSISTOR AND METHOD FOR FABRICATING THE SAME

SK hynix Inc., Icheon-si...

1. An electronic device comprising a transistor, wherein the transistor comprises:a semiconductor substrate including an active region defined by an isolation layer;
a gate electrode crossing the active region; and
a landing plug contact formed over the active region at both sides of the gate electrode, and
wherein a top surface of the active region at both sides of the gate electrode has a shape that a center relatively far from the gate electrode is higher than an edge relatively near to the gate electrode.

US Pat. No. 10,483,373

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a first insulating interlayer on a substrate;
a second insulating interlayer on the first insulating interlayer;
a gate structure extending through the first insulating interlayer and the second insulating interlayer on the substrate, a lower portion of the gate structure having a constant first width, and an upper portion of the gate structure having a second width that is greater than the first width and that gradually increases from a bottom toward a top thereof; and
a spacer structure on a sidewall of the gate structure, a width of an upper portion of the spacer structure being less than a width of a lower portion of the spacer structure.

US Pat. No. 10,483,371

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method of forming a semiconductor structure, comprising:providing a substrate;
forming a gate dielectric layer on the substrate;
forming a dielectric barrier layer structure on the gate dielectric layer, wherein a first silicon source gas is used to dope silicon in the dielectric barrier layer structure;
forming a work function layer on the dielectric barrier layer structure;
forming a gate barrier layer structure on the work function layer, wherein a second silicon source gas is used to dope silicon in the gate barrier layer structure, wherein the dielectric barrier layer structure has a stacked structure and an average atomic percentage concentration of silicon in the dielectric barrier layer structure is smaller than an average atomic percentage concentration of silicon in a layer of the stacked structure adjacent to the work function layer; and
forming a gate electrode layer on the gate barrier layer structure.

US Pat. No. 10,483,367

VERTICAL GATE ALL AROUND (VGAA) DEVICES AND METHODS OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a semiconductor substrate having a doped region;
a spacer layer over the semiconductor substrate;
a protrusion extending from the doped region away from the semiconductor substrate, the protrusion comprising a first source/drain region adjacent the doped region, a channel region disposed over the first source/drain region, and a second source/drain region disposed over the channel region;
a gate stack encircling the channel region of the protrusion, the gate stack being over the spacer layer; and
an epitaxial semiconductor material disposed over a top surface and extending from sidewalls of the second source/drain region of the protrusion, the epitaxial semiconductor material having an octagonal shape in cross-sectional view.

US Pat. No. 10,483,365

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductor, the first conductor being a first ring-shaped conductor;
an oxide semiconductor comprising a region extending through an inside of a ring of the first conductor;
a first insulator between the first conductor and the oxide semiconductor;
a second insulator between the first conductor and the first insulator; and
a second conductor inside the ring of the first conductor,
wherein the second conductor is inside the second insulator,
wherein the second conductor is configured to be in a floating state,
wherein an inner surface and an outer surface of the second conductor are in contact with the second insulator, and
wherein the inner surface of the second conductor faces to the first insulator.

US Pat. No. 10,483,359

METHOD OF FABRICATING A POWER SEMICONDUCTOR DEVICE

Infineon Technologies Ame...

1. A method of fabricating a power semiconductor device, said method comprising:forming a gate trench in a semiconductor substrate, said gate trench including a gate electrode; and
forming a field plate trench structure in said substrate separate from said gate trench, wherein forming said field plate trench structure comprises:
forming an upper trench situated over a lower trench in said substrate, said upper trench being wider than said lower trench and extending deeper into said substrate than said gate trench, a width of said lower trench being greater than one half a width of said upper trench;
forming a trench dielectric in said lower trench and on sidewalls of said upper trench, said trench dielectric filling completely said lower trench; and
forming a field plate electrode within said trench dielectric;
wherein said trench dielectric is formed such that a bottom thickness of said trench dielectric is greater than a sidewall thickness of said trench dielectric on said sidewalls of said upper trench.

US Pat. No. 10,483,358

SEMICONDUCTOR CELL STRUCTURE AND POWER SEMICONDUCTOR DEVICE

1. A semiconductor cell structure, at least comprising:a highly-doped semiconductor material region (101);
an epitaxial layer (102) formed on the highly-doped semiconductor material region (101);
an active device region (105) formed on the epitaxial layer (102);
the epitaxial layer (102) is provided with a deep groove (109), the deep groove (109) vertically extends into the highly-doped semiconductor material region (101), a dielectric insulating layer (103) is formed on a side wall inside the deep groove (109), the deep groove (109) is filled with a semi-insulating material (104);
an electrode (106) in contact with the semi-insulating material (104) is formed above the semi-insulating material (104), and a bottom portion of the semi-insulating material (104) is in contact with the highly-doped semiconductor material region (101);
wherein, the highly-doped semiconductor material region 101 is N+ type, the epitaxial layer 102 is N? type; when the highly-doped semiconductor material region 101 is P+ type, the epitaxial layer 102 is P? type,
wherein, the bottom portion of the semi-insulating material (104) and a bottom portion of the dielectric insulating layer (103) vertically extend into the highly doped semiconductor material region (101) at a same depth of h;
wherein, a thickness t of the dielectric insulating layer 103 is in a sublinear relationship with the depth h.

US Pat. No. 10,483,355

FORMING NON-LINE-OF-SIGHT SOURCE DRAIN EXTENSION IN AN NMOS FINFET USING N-DOPED SELECTIVE EPITAXIAL GROWTH

APPLIED MATERIALS, INC., ...

1. A finFET device, comprising:a semiconductor substrate having a bulk semiconductor region;
a semiconductor fin structure that is disposed on the bulk semiconductor region, the semiconductor fin structure comprising:
a source extension region epitaxially grown on the bulk semiconductor region, the source extension region comprising a first n-type dopant;
a drain extension region epitaxially grown on the bulk semiconductor region, the drain extension region comprising the first n-type dopant;
a first carbon-containing layer that is surrounded by the source extension region and not in direct contact with the bulk semiconductor region;
a second carbon-containing layer that is surrounded by the drain extension region and not in direct contact with the bulk semiconductor region;
a source region comprising a second n-type dopant, wherein the source region is surrounded by the first carbon-containing layer and not in direct contact with the bulk semiconductor region;
a drain region comprising the second n-type dopant, wherein the drain region is surrounded by the second carbon-containing layer and not in direct contact with the bulk semiconductor region; and
a channel region between the source extension region and the drain extension region; and
a gate electrode structure that is formed on a portion of the semiconductor fin structure, the gate electrode structure comprising:
a gate electrode layer;
a first gate spacer formed on a first sidewall of the gate electrode layer and on the source extension region; and
a second gate spacer formed on a second sidewall of the gate electrode layer and on the drain extension region wherein
the first n-type dopant is different than the second n-type dopant,
the first n-type dopant in the source extension region prevents diffusion of the second n-type dopant in the source region to the channel region, and
the first n-type dopant in the drain extension region prevents diffusion of the second n-type dopant in the drain region to the channel region.

US Pat. No. 10,483,349

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first semiconductor region including a first partial region and a second partial region and being of a first conductivity type;
a second semiconductor region separated from the first partial region in a second direction crossing a first direction, the second semiconductor region being of the first conductivity type, the first direction being from the first partial region toward the second partial region;
a third semiconductor region provided between the first partial region and the second semiconductor region, the third semiconductor region being of a second conductivity type and comprising a third partial region and a fourth partial region, the fourth partial region being positioned between the first partial region and the third partial region;
a first electrode separated from the second partial region in the second direction and separated from the second semiconductor region and the third semiconductor region in the first direction;
a first insulating film comprising a first insulating region and a second insulating region, the first insulating region being provided between the second semiconductor region and the first electrode in the first direction and between the third semiconductor region and the first electrode in the first direction, a portion of the first insulating region contacting the third partial region, the second insulating region being provided between the second partial region and the first electrode in the second direction; and
a fourth semiconductor region comprising a first portion and being of the first conductivity type, the first portion being provided between the fourth partial region and at least a portion of the first insulating film in the first direction,
wherein
an impurity concentration of the second conductivity type in the third partial region is higher than an impurity concentration of the second conductivity type in the fourth partial region,
the third semiconductor region further comprises a fifth partial region provided between the fourth partial region and the first partial region in the second direction, and
the impurity concentration of the second conductivity type in the fourth partial region is higher than an impurity concentration of the second conductivity type in the fifth partial region.

US Pat. No. 10,483,345

ELECTRONIC COMPONENT EMBEDDED SUBSTRATE

TDK CORPORATION, Tokyo (...

1. An electronic component embedded substrate comprising:a substrate configured to include an insulating layer and to have a first principal surface and a second principal surface on the opposite side of the first principal surface; and
an electronic component embedded in the substrate and configured to have a plurality of first terminals provided close to the first principal surface, a plurality of second terminals provided close to the second principal surface, and a capacity part provided between the plurality of first terminals and the plurality of second terminals,whereinthe electronic component is configured such that at least a part of the second terminals is embedded in the insulating layer,
an insulating member is provided between the neighboring second terminals to be in contact with both of the neighboring second terminals,
the insulating member and the insulating layer are formed of materials whose thermal expansion coefficients are different from each other, and
the thermal expansion coefficient of the material of which the insulating member is formed is smaller than that of the material of which the insulating layer is formed, and is greater than that of a material of which the second terminals are formed.

US Pat. No. 10,483,343

INDUCTORS FOR CHIP TO CHIP NEAR FIELD COMMUNICATION

HUAWEI TECHNOLOGIES CO., ...

1. A device comprising:at least one inductor positioned on a substrate, the substrate having at least one major surface defining a horizontal plane, the at least one inductor having a plurality of turns about a horizontal axis parallel to the horizontal plane, the at least one inductor being positioned for near field coupling with another inductor, wherein:
a first turn of the plurality of turns comprises a plurality of segments positioned in a plurality of metal layers of the substrate, each segment being electrically connected to a subsequent segment by a via, a first such segment being a first end segment and a last such segment being a second end segment;
at least two of the plurality of segments being displaced along the horizontal axis relative to a prior segment such that a projection of the first end segment onto the horizontal axis does not overlap with a projection of the second end segment onto the horizontal axis; and
a second turn of the plurality of turns has a first end segment connected to the second end segment of the first turn.

US Pat. No. 10,483,341

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:first pixels in a first pixel area and coupled with first scan lines;
first scan stage circuits in a first peripheral area outside the first pixel area, and configured to supply a first scan signal to the first scan lines;
second pixels in a second pixel area having a width that is less than a width of the first pixel area, and coupled with second scan lines;
second scan stage circuits in a second peripheral area outside the second pixel area, and configured to generate a second scan signal; and
first load matching units respectively between the second scan stage circuits, and configured to delay the second scan signal, and to supply the delayed second scan signal to the second scan lines.

US Pat. No. 10,483,336

ORGANIC LIGHT EMITTING DISPLAY APPARATUS

LG Display Co., Ltd., Se...

1. An organic light emitting display apparatus, comprising:a substrate;
an auxiliary line on the substrate;
an anode electrode on the substrate;
an auxiliary electrode on the substrate;
an organic emission layer on the anode electrode;
a cathode electrode on the organic emission layer and on the auxiliary electrode;
a bank overlapping with a first portion of the auxiliary electrode and exposing a second portion of the auxiliary electrode;
a partition wall on the second portion of the auxiliary electrode; and
a separation space between the partition wall and the bank, the cathode electrode being electrically connected to the auxiliary electrode through the separation space,
wherein the auxiliary line is connected to the second portion of the auxiliary electrode through a contact hole, and
wherein the auxiliary line is disposed between a plurality of the anode electrodes.

US Pat. No. 10,483,333

TOUCH DISPLAY PANEL AND TOUCH DISPLAY APPARATUS

Shanghai Tianma Micro-Ele...

1. A touch display panel, comprising:a substrate comprising a display area and non-display areas;
an organic light emitting device formed in the display area of the substrate;
at least one retaining wail arranged in the non-display areas of the substrate, wherein the at least one retaining wall comprises a first retaining wall which is adjacent to the display area, and a width of the at least one retaining wall is greater than or equal to 30 ?m and less than or equal to 200 ?m;
a thin film encapsulation layer, wherein the thin film encapsulation layer is arranged on the organic light emitting device, and the thin film encapsulation layer comprises at least one inorganic encapsulation layer and at least one organic encapsulation layer, and the thin film encapsulation layer covers the at least one retaining wall, a height difference between the first retaining wall and a part of the thin film encapsulation layer located between the first retaining wall and the display area is greater than or equal to 0 ?m and less than or equal to 3 ?m;
touch electrodes, wherein the touch electrodes are arranged on the thin film encapsulation layer, and at least a part of at least one of the touch electrodes is located in the display area of the substrate; and
electrode wires, wherein at least a part of at least one of the electrode wires is located in the non-display area of the substrate, is disposed on the thin film encapsulation layer, and is arranged along an extension direction of the at least one retaining wall, wherein projections of the electrode wires on the substrate are located within a projection of the at least one retaining wall on the substrate.

US Pat. No. 10,483,331

COLOR FILTER ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE USING THE SAME

LG DISPLAY CO., LTD., Se...

1. A method of fabricating an organic light emitting diode display device, the method comprising:forming a thin film transistor on a first substrate;
forming an organic light emitting element, which is electrically connected to the thin film transistor, on the first substrate;
forming a black matrix, in which openings are formed, on one surface of a second substrate opposite to the first substrate;
forming a color filter layer in the openings;
forming a transparent insulation layer having a first surface and a second surface opposing the first surface on the second substrate, with the first surface of the transparent insulating layer in direct contact with the color filter layer;
forming a plurality of optical patterns at the second surface of the transparent insulation layer; and
attaching the first substrate and the second substrate such that the second surface of the transparent insulating layer is closer to the thin film transistor than the first substrate.

US Pat. No. 10,483,330

ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS

SEIKO EPSON CORPORATION, ...

1. An electro-optical device comprising:a first pixel;
a second pixel;
a third pixel;
a first color filter covering a light emitting region of the first pixel;
a second color filter covering a light emitting region of the second pixel;
a third color filter covering a light emitting region of the third pixel, the second color filter having a projection portion that projects toward the light emitting region of the first pixel;
a first light shielding portion provided between the first pixel and the second pixel, the first light shielding portion being the projection portion; and
a second light shielding portion provided between the second pixel and the third pixel,
wherein the second light shielding portion does not project toward the light emitting region of the second pixel, and
wherein a width of the first light shielding portion and a width of the second light shielding portion are different.

US Pat. No. 10,483,326

IMAGE SENSOR AND MANUFACTURING METHOD THEREOF

INDUSTRIAL TECHNOLOGY RES...

1. An image sensor, comprising:a substrate;
a patterned electrode layer disposed on the substrate and comprising a plurality of electrode blocks separated from one another;
a pixel isolation structure disposed on the substrate and comprising a metal halide; and
a patterned photo-electric conversion layer disposed on the plurality of electrode blocks to form a plurality of photo-electric conversion blocks corresponding to the plurality of electrode blocks, wherein the plurality of photo-electric conversion blocks comprise a perovskite material and are separated from one another by the pixel isolation structure,
wherein a top surface of the patterned photo-electric conversion layer is located higher than a top surface of the pixel isolation structure;
wherein the perovskite material is represented by a formula as follows: (AMX3)1-n(B2MX4)n, wherein “A” denotes a positive monovalent metal cation or a positive monovalent organic cation and “B” denotes an R1-NH3 cation, wherein R1 is an alkyl group having 4-18 carbon atoms, “M” denotes a positive bivalent metal cation, “X” denotes a halogen, and n=0-1.

US Pat. No. 10,483,323

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

12. A three-dimensional semiconductor device, comprising:a substrate; and
a cell array comprising:
a plurality of electrodes vertically stacked on the substrate, the plurality of electrodes forming m number of stepwise stacks at ends of the plurality of electrodes in a first direction;
a plurality of dummy electrodes vertically stacked and adjacent to the plurality of electrodes in a second direction, the second direction being perpendicular to the first direction, the plurality of dummy electrodes forming n number of stepwise stacks in the second direction;
a capping insulating layer covering the plurality of electrodes and the plurality of dummy electrodes; and
a plurality of contact plugs penetrating the capping insulating layer and contacting the plurality of electrodes at each step of the m number of stepwise stacks,
wherein the m and n are natural numbers equal to or greater than two, and the m is greater than n.

US Pat. No. 10,483,319

PIXILATED DISPLAY DEVICE BASED UPON NANOWIRE LEDS AND METHOD FOR MAKING THE SAME

GLO AB, Lund (SE)

1. A method of forming a pixilated display device, comprising:growing an array of nanowire LEDs on a substrate, each nanowire LED in the array including a vertical stack, from bottom to top, of a first-wavelength light emitting portion including a first material emitting a first-wavelength light and a second-wavelength light emitting portion including a second material emitting a second-wavelength light; and
while masking a first nanowire LED within the array with a patterned masking layer, removing a second-wavelength light emitting portion from a second nanowire LED within the array;
wherein growing the array of nanowire LEDs on the substrate comprises:
forming a growth mask over the substrate, the growth mask having a first aperture in a first area of the first nanowire LED and a second aperture in a second area of the second nanowire LED;
forming a first nanowire core through the first aperture; and
forming a second nanowire core through the second aperture:
wherein:
the first nanowire LED comprises a core-shell nanowire device that comprises the first nanowire core and a first quantum well shell comprising the first-wavelength light emitting portion, the second-wavelength light emitting portion, and a first pyramidal plane quantum well;
the second nanowire LED comprises a core-shell nanowire device that comprises the second nanowire core and a second quantum well shell comprising the first-wavelength light emitting portion, the second-wavelength light emitting portion, and a second pyramidal plane quantum well;
the first quantum well shell is formed by deposition of an InGaN layer and a GaN layer around the first nanowire core;
the second quantum well shell is formed by deposition of the InGaN layer and the GaN layer around the second nanowire core;
the first quantum well shell and the second quantum well shell are deposited during the same deposition steps;
the first-wavelength light emitting portion of the first nanowire LED comprises a lower portion of the first quantum well shell located over m-plane sidewalls of the first nanowire core;
the second-wavelength light emitting portion of the first nanowire LED comprises an eave region of the first quantum well shell located between the lower portion of the first quantum well shell and the first pyramidal plane quantum well of the first quantum well shell located over pyramidal p-plane sidewalls of the first nanowire core;
the first-wavelength light emitting portion of the second nanowire LED comprises a lower portion of the second quantum well shell located over m-plane sidewalls of the second nanowire core; and
the second-wavelength light emitting portion of the second nanowire LED comprises an eave region of the second quantum well shell located between the lower portion of the second quantum well shell and the second pyramidal plane quantum well of the second quantum well shell located over pyramidal p-plane sidewalls of the second nanowire core.

US Pat. No. 10,483,310

ISOLATION STRUCTURE FOR REDUCING CROSSTALK BETWEEN PIXELS AND FABRICATION METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. An isolation structure, comprising:a reflective layer;
a first dielectric layer disposed on the reflective layer;
a second dielectric layer disposed on the first dielectric layer; and
a third dielectric layer disposed on the second dielectric layer, wherein the second dielectric layer is located between the first dielectric layer and the third dielectric layer and a dielectric constant of the first dielectric layer is different from that of the second dielectric layer.

US Pat. No. 10,483,309

IMAGE SENSORS WITH MULTIPART DIFFRACTIVE LENSES

SEMIDUCTOR COMPONENTS IND...

1. An image sensor comprising a plurality of imaging pixels, wherein each imaging pixel of the plurality of imaging pixels comprises:a photodiode; and
a diffractive lens formed over the photodiode,
wherein the diffractive lens has an edge portion with a first refractive index and a center portion with a second refractive index that is different than the first refractive index and wherein the edge portion is adjacent a solid material with a third refractive index that is different than the first and second refractive indices.

US Pat. No. 10,483,305

IMAGE SENSOR INCLUDING PLANAR BOUNDARY BETWEEN OPTICAL BLACK AND ACTIVE PIXEL SENSOR AREAS

Samsung Electronics Co., ...

1. An image sensor comprising:a substrate comprising a sensor array area, a pad area, and a circuit area, wherein the sensor array area comprises a first area including active pixels and a second area including optical black pixels, the pad area is disposed around the sensor array area, and the circuit area is disposed between the sensor array area and the pad area;
a wiring layer extending on a level spaced apart from the substrate by a first distance, on the pad area; and
a light-shielding pattern comprising a first portion, a second portion, and a third portion, wherein the first portion extends on a level spaced apart from the substrate by a second distance less than the first distance, the second portion is disposed between the first portion and the wiring layer and extends on the level of the wiring layer, and the third portion is disposed between the first portion and the second portion and is integrally formed with the first portion and the second portion.

US Pat. No. 10,483,302

SOLID-STATE IMAGING DEVICE

HAMAMATSU PHOTONICS K.K.,...

1. A solid-state imaging device comprising:a plurality of photoelectric converting units aligned in a first direction;
a plurality of charge-accumulating units, each being aligned with a corresponding photoelectric converting unit in a second direction orthogonal to the first direction, and each being configured to accumulate a charge generated in the corresponding photoelectric converting unit;
a charge-output unit configured to obtain charges respectively transferred from the plurality of charge-accumulating units, and transfer in the first direction, to output the charges; and
a plurality of transfer units, each being disposed between a corresponding charge-accumulating unit of the plurality of charge-accumulating units and the charge-output unit in the second direction, and each being configured to obtain the charge accumulated in the corresponding charge-accumulating unit and transfer the obtained charge to the charge-output unit,
each of the photoelectric converting units including:
a photosensitive region configured to generate the charge in accordance with light incidence; and
an electric potential gradient forming unit configured to form, for the photosensitive region, an electric potential gradient increasing along the second direction, the electric potential gradient forming unit being configured to accelerate migration of the charge in the second direction in the photosensitive region, and each of the charge-accumulating units including:
a plurality of regions, including a first region, a second region, and a third region, in which an impurity concentration is gradually changed in one way in the second direction, wherein the plurality of regions are disposed in an order of the first region, the second region, and the third region in the second direction; and
an electrode, including a first electrode and a second electrode, disposed over the plurality of regions in which the impurity concentration is gradually varied, and configured to apply an electric field to the plurality of regions, wherein the first electrode is disposed over the first region and the second region, the second electrode is disposed over the second region and the third region, and wherein the second electrode is applied with a voltage higher than that applied to the first electrode.

US Pat. No. 10,483,300

OPTICALLY RESTORABLE SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING THE SAME, AND FLASH MEMORY DEVICE USING THE SAME

Electronics and Telecommu...

1. An optically restorable semiconductor device comprising:a gate electrode;
a gate insulation film on the gate electrode;
a photo-responsive semiconductor film on the gate insulation film;
an interface charge part disposed adjacent to an interface between the photo-responsive semiconductor film and the gate insulation film; and
a plasma treatment area provided on the gate insulation film,
wherein the interface charge part comprises charge traps,
wherein the interface charge part and the photo-responsive semiconductor film directly contact each other, and
wherein the plasma treatment area directly contacts the interface charge layer and comprises deep traps.

US Pat. No. 10,483,298

MULTI-SENSOR OPTICAL DEVICE FOR DETECTING CHEMICAL SPECIES AND MANUFACTURING METHOD THEREOF

STMicroelectronics S.R.L....

1. A device, comprising:a substrate;
a semiconductor layer on the substrate, the semiconductor layer having a first portion with a first thickness and a second portion with a second thickness, the first portion having a first surface;
a first optical sensor in the first portion, the first optical sensor including:
a first anode recessed in the first portion, the first anode having an exposed surface coplanar with the first surface; and
a second optical sensor in the second portion.

US Pat. No. 10,483,293

ACTIVE MATRIX DISPLAY DEVICE, AND MODULE AND ELECTRONIC APPLIANCE INCLUDING THE SAME

Semiconductor Energy Labo...

6. A semiconductor device comprising:first to fifth transistors;
a first light-emitting element;
a first capacitor comprising first and second electrodes;
first to third gate wirings; and
first to fourth wirings,
wherein the second transistor, the fourth transistor, and the third transistor are electrically connected in series between the first wiring and the third wiring,
wherein the first electrode is electrically connected to a first node to which the second transistor and the fourth transistor are electrically connected,
wherein one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring,
wherein the second electrode is electrically connected to the first light-emitting element,
wherein a gate of the first transistor is electrically connected to a second node to which the fourth transistor and the third transistor are electrically connected,
wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the first light-emitting element and the other of the source and the drain of the fifth transistor,
wherein the first gate wiring is electrically connected to a gate of the second transistor,
wherein the second gate wiring is electrically connected to a gate of the third transistor,
wherein the third gate wiring is electrically connected to a gate of the fourth transistor,
wherein the first gate wiring is not electrically connected to the second gate wiring, and
wherein the third gate wiring is not electrically connected to the first gate wiring and the second gate wiring.

US Pat. No. 10,483,283

FLASH MEMORY DEVICE AND MANUFACTURE THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a flash memory device, comprising:providing a substrate;
forming a plurality of sacrificial layers and a plurality of interval insulation layers on the substrate, with the sacrificial layers and the interval insulation layers stacking over each other alternately;
forming a through-hole by etching the sacrificial layers and the interval insulation layers until an upper surface of the substrate is exposed;
forming a channel structure in the through-hole, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer, wherein the channel layer comprises a first component substantially perpendicular to the upper surface of the substrate and a second component on the first component;
forming a plurality of interval cavities by removing the sacrificial layers;
forming a plurality of gate structures in the interval cavities, with a topmost gate structure wrapped around the second component of the channel layer; and
forming a channel contact component contacting the second component of the channel layer, wherein the channel contact component and the second component of the channel layer form a Schottky contact.

US Pat. No. 10,483,275

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, the method comprising:(a) forming a first insulating film having a first thickness over a main surface of a semiconductor substrate and then forming a second insulating film having a second thickness larger than the first thickness over the first insulating film;
(b) sequentially processing the second insulating film, the first insulating film, and the semiconductor substrate to form a plurality of trenches and to form a plurality of projecting portions which include portions of the semiconductor substrate extending in a first direction along the main surface of the semiconductor substrate and are spaced apart from each other in a second direction orthogonal to the first direction along the main surface of the semiconductor substrate;
(c) depositing a third insulating film over the main surface of the semiconductor substrate such that the third insulating film is embedded in the trenches;
(d) planarizing an upper surface of the third insulating film and an upper surface of the second insulating film;
(e) removing the second insulating film;
(f) performing isotropic dry etching to remove the first insulating film, expose respective upper surfaces of the projecting portions, recess an upper surface and a side surface of the third insulating film, and expose respective side walls of the projecting portions from the upper surface of the third insulating film;
(g) forming a first gate electrode extending in the second direction such that a fourth insulating film is interposed between the first gate electrode and each of the respective upper surfaces and side walls of the projecting portions which are exposed from the upper surface of the third insulating film; and
(h) forming a second gate electrode extending in the second direction such that a fifth insulating film including a trapping insulating film is interposed between the second gate electrode and each of the respective upper surfaces and side walls of the projecting portions which are exposed from the upper surface of the third insulating film and one of side walls of the first gate electrode,
wherein, between the projecting portions adjacent to each other in the second direction, a portion of the upper surface of the third insulating film is higher in level than a first surface obtained by connecting a position of the upper surface of the third insulating film which is in contact with the side wall of one of the projecting portions to a position of the upper surface of the third insulating film which is in contact with the side wall of other projecting portion.

US Pat. No. 10,483,274

THREE-DIMENSIONAL SEMICONDUCTOR DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A three-dimensional (3D) semiconductor device, comprising:an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a plurality of electrodes which are stacked in a direction perpendicular to a top surface of the substrate,
wherein the plurality of the electrodes respectively include pads which define a stepped structure in the second region of the substrate;
dummy pillars penetrating the pads and a portion of the electrode structure under the pads; and
contact plugs electrically connected to the pads, respectively,
wherein at least one of the dummy pillars penetrate a boundary between adjacent pads.

US Pat. No. 10,483,272

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A method for fabricating an electronic device including a semiconductor memory, comprising:forming a first stacked structure over a substrate, the first stacked structure including a plurality of first interlayer dielectric layers and first material layers which are alternately stacked over each other;
forming a first channel hole by selectively etching the first stacked structure;
forming a first channel layer in the first channel hole;
forming a channel connection pattern and an etch stop pattern over the first stacked structure, wherein the channel connection pattern overlaps the first channel hole and, wherein the etch stop pattern is formed of the same material as the channel connection pattern, is isolated from the channel connection pattern, and is formed at substantially the same level as the channel connection pattern;
forming a second stacked structure over the channel connection pattern and the etch stop pattern, the second stacked structure including a plurality of second interlayer dielectric layers and second material layers which are alternately stacked over each other;
forming a second channel hole to expose the channel connection pattern by selectively etching the second stacked structure;
forming a second channel layer in the second channel hole;
forming an initial slit by etching the second stacked structure to expose the etch stop pattern; and
forming a final slit by etching the exposed etch stop pattern and the first stacked structure located under the exposed etch stop pattern.

US Pat. No. 10,483,266

FLEXIBLE MERGE SCHEME FOR SOURCE/DRAIN EPITAXY REGIONS

Taiwan Semiconductor Manu...

1. A method comprising:forming a first gate stack extending on top surfaces and sidewalls of first semiconductor fins, wherein the first semiconductor fins are parallel to, and are neighboring, each other;
forming a second gate stack extending on top surfaces and sidewalls of second semiconductor fins, wherein the second semiconductor fins are parallel to, and are neighboring, each other;
forming a dielectric layer, wherein the dielectric layer comprises a first portion extending on the first gate stack and the first semiconductor fins, and a second portion extending on the second gate stack and the second semiconductor fins;
in a first etching process, etching the first portion of the dielectric layer to form first fin spacers on sidewalls of the first semiconductor fins, wherein the first fin spacers have a first height;
in a second etching process, etching the second portion of the dielectric layer to form second fin spacers on sidewalls of the second semiconductor fins, wherein the second fin spacers have a second height greater than the first height;
recessing the first semiconductor fins to form first recesses between the first fin spacers;
recessing the second semiconductor fins to form second recesses between the second fin spacers; and
simultaneously growing first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses, wherein the first epitaxy semiconductor regions grown from neighboring ones of the first recesses merge with each other, and the second epitaxy semiconductor regions grown from neighboring ones of the second recesses are separate from each other.

US Pat. No. 10,483,265

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:a hybrid pillar-type bottom electrode including a cylindrical first bottom electrode and a pillar-type second bottom electrode filling a cylindrical inside of the cylindrical first bottom electrode;
a supporter suitable for supporting an outer wall of the hybrid pillar-type bottom electrode;
a dielectric layer formed over the hybrid pillar-type bottom electrode and the supporter; and
a top electrode disposed over the dielectric layer,
wherein the cylindrical first bottom electrode includes:
a cylinder body; and
a cylinder head disposed on the cylinder body and having a sloped side wall to have a wider upper surface than the cylinder body.

US Pat. No. 10,483,262

DUAL NITRIDE STRESSOR FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:forming a fin structure over a substrate;
forming a shallow trench isolation region along a lower part of the fin structure;
forming a first gate structure over a first portion of the fin structure;
forming a first nitride layer over a second portion of the fin structure and the shallow trench isolation region;
exposing the first nitride layer to ultraviolet radiation;
removing a part of the second portion of the fin structure after exposing the first nitride layer to ultraviolet radiation so that the second portion of the fin structure above the shallow trench isolation region is removed and a residual portion of the first nitride layer remains over the shallow trench isolation region; and
forming source/drain regions at the second portion of the fin structure so that the source/drain regions extend along and contact a side surface of the residual portion of the first nitride layer from a bottom of the residual portion to a top of the residual portion and a portion of the source/drain regions are formed vertically and laterally over the residual portion of the first nitride layer.

US Pat. No. 10,483,260

SEMICONDUCTOR CARRIER WITH VERTICAL POWER FET MODULE

1. A monolithic power management module, comprising:a chip carrier further comprising surfaces, ground traces, signal and power interconnects;
a three dimensional FET formed on the chip carrier to modulate currents through the chip carrier or on the surfaces;
a toroidal inductor or transformer coil with a ceramic magnetic core formed on the chip carrier adjacent to the three dimensional FET and having a first winding connected to the three dimensional FET, and
a plurality of passive ceramic components formed on the chip carrier surfaces including clock circuitry in a form of an LCR resonator further comprising an inductor coil, a capacitive element and a resistive element; and
wherein the three dimensional FET includes an elongated gate electrode comprising a conductor that forms a resonant transmission line by configuring the conductor to form a serpentine electrode that contains a capacitive element determined by charge-collected beneath the gate, a resistive dement determined by the conductor, length and cross-sectional area, of the conductor used to form the serpentine electrode, and an Inductive element formed by half-turns that loop the serpentine electrode winding back upon itself.

US Pat. No. 10,483,258

SEMICONDUCTOR DEVICES AND METHODS TO ENHANCE ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS, LATCH-UP, AND HOT CARRIER IMMUNITY

INDIAN INSTITUTE OF SCIEN...

2. A semiconductor device comprising at least one ESD protection device and at least one functional device, wherein the at least one ESD protection device comprises one or more fins having a selective epitaxial growth before a silicidation, and wherein the at least one functional device comprises one or more fins fully silicided, without an epitaxial growth.

US Pat. No. 10,483,255

SEMICONDUCTOR DEVICE

SOCIONEXT INC., Yokohama...

1. A semiconductor device, comprising:a substrate;
a first circuit;
a first power supply line;
a second power supply line which is electrically coupled to the first circuit;
a first ground line which is electrically coupled to the first circuit;
a first switch circuit which includes a first switch section;
a first well tap which is electrically coupled to the substrate and the second power supply line;
a second circuit;
a third power supply line;
a fourth power supply line which is electrically coupled to the second circuit;
a second ground line which is electrically coupled to the second circuit; and
a second switch circuit which includes a second switch section,
wherein
the first switch section is adjacent to the first well tap in a plan view,
the first switch section includes a first switch transistor which is disposed between the first power supply line and the second power supply line,
the second switch section is adjacent to no well tap in a plan view,
the second switch section includes a second switch transistor which is disposed between the third power supply line and the fourth power supply line.

US Pat. No. 10,483,250

THREE-DIMENSIONAL SMALL FORM FACTOR SYSTEM IN PACKAGE ARCHITECTURE

Intel Corporation, Santa...

1. An apparatus comprising:a first package having a first side and an opposite second side, the first package including:
a plurality of embedded electronic components, ones of the plurality of embedded electronic components laterally adjacent to one another, and
one or more embedded via bars, each via bar including a plurality of through vias;
and
a second package having a first side and an opposite second side, the second package including:
a plurality of embedded electronic components, ones of the plurality of embedded electronic components laterally adjacent to one another;
wherein a first side of the first package and a second side of second package are coupled together by a plurality of connections, including at least a first connection connecting the second package to a first component of the first package and a second connection connecting one of the plurality of embedded electronic components of the second package to a first via bar of the one or more embedded via bars, wherein the one of the plurality of embedded electronic components of the second package is directly over the first via bar of the one of the one or more embedded via bars of the first package.

US Pat. No. 10,483,249

INTEGRATED PASSIVE DEVICES ON CHIP

Intel Corporation, Santa...

1. A device comprising:a semiconductor die;
a semiconductor die package, a first side of the package being coupled with the semiconductor die; and
one or more separate dies to provide a plurality of passive components for operation of the semiconductor die, wherein the plurality of passive components for operation of the semiconductor die includes a plurality of inductors and a plurality of capacitors, and wherein a first separate die includes a first set of passive components on a first side of the first separate die and a second, different set of passive components on a second, opposite side of the first separate die.

US Pat. No. 10,483,248

WAFER LEVEL CHIP SCALE FILTER PACKAGING USING SEMICONDUCTOR WAFERS WITH THROUGH WAFER VIAS

SKYWORKS SOLUTIONS, INC.,...

1. An electronics package comprising:a semiconductor substrate having one or more passive devices formed on the semiconductor substrate and a cavity defined in a first surface of the semiconductor substrate; and
a piezoelectric substrate bonded to the semiconductor substrate and having a microelectromechanical device formed on the piezoelectric substrate, the microelectromechanical device disposed within the cavity defined in the semiconductor substrate.

US Pat. No. 10,483,241

SEMICONDUCTOR DEVICES WITH THROUGH SILICON VIAS AND PACKAGE-LEVEL CONFIGURABILITY

Micron Technology, Inc., ...

11. A semiconductor device assembly, comprising:a substrate including a substrate contact; and
a plurality of semiconductor dies, each including:
a first contact pad electrically coupled to a first circuit on the semiconductor die including at least one active circuit element,
a first through-silicon via (TSV) electrically coupling the first contact pad to a first backside contact pad of the semiconductor die, and
a second contact pad electrically coupled to a second circuit on the semiconductor die including only passive circuit elements;
wherein the first contact pads, the first TSVs, and the first backside contact pads of all of the plurality of semiconductor dies are electrically coupled to the substrate contact, and
wherein the second contact pads of some, but less than all, of the plurality of semiconductor dies are electrically coupled to the substrate contact.

US Pat. No. 10,483,239

SEMICONDUCTOR DEVICE INCLUDING DUAL PAD WIRE BOND INTERCONNECTION

SanDisk Semiconductor (Sh...

1. A semiconductor die, comprising:a first major surface;
a second major surface opposed to the first major surface;
integrated circuits formed adjacent the first major surface in an active area;
a set of functional die bond pads spaced inward from an edge of the semiconductor die and electrically connected to the integrated circuits by metal interconnects within the active area;
a set of dummy die bond pads at the edge of the semiconductor die and adjacent the set of functional die bond pads, the set of dummy die bond pads configured to receive a first set of bond wires; and
a second set of bond wires electrically interconnecting respective pairs of functional die bond pads from the set of functional die bond pads and dummy die bond pads from the set of dummy die bond pads.

US Pat. No. 10,483,238

INK PRINTED WIRE BONDING

STMICROELECTRONICS S.R.L....

1. A device, comprising:a package substrate;
a plurality of contact pads on the package substrate;
a first die coupled to the package substrate;
a first plurality of pillars on the first die; and
a first plurality of ink printed wires, each of the first plurality of ink printed wires electrically coupled between at least one of the plurality of contact pads on the package substrate and at least a corresponding one of the first plurality of pillars on the first die, at least one of the first plurality of ink printed wires having a first width adjacent to the first die and a second width adjacent to the respective at least one of the plurality of contact pads, the first width being different than the second width, wherein the at least one of the first plurality of ink printed wires contacts a top surface and a side surface of one of the first plurality of pillars.

US Pat. No. 10,483,232

METHOD FOR FABRICATING BUMP STRUCTURES ON CHIPS WITH PANEL TYPE PROCESS

PHOENIX PIONEER TECHNOLOG...

1. A method for fabricating a bump structure on a chip with panel type process, comprising in sequential order:providing an integrated carrier and a plurality of semiconductor chips, which has an active side and a reverse side relative to the active side, the active side of each semiconductor chip has a plurality of metal electrode pads and an insulated protecting layer, which is exposed out of the metal electrode pads;
fixing the reverse side of each semiconductor chip on the integrated carrier;
executing an electroless plating process to form an under bump metallurgy (UBM) structure on the metal electrode pad of each semiconductor chip, wherein the coverage range of the UBM structure is equal to the coverage range of the metal electrode pad;
forming a dielectric layer to cover the integrated carrier, the semiconductor chips and the UBM structure;
forming a plurality of via holes through the dielectric layer and are exposed out of the UBM structure by laser drill or lithography including exposure and development processes; and forming a plurality of metal bumps in the corresponding via hole of the dielectric layer, respectively;
wherein the electrode pad is an aluminum metal electrode pad, and the electroless plating process includes an electroless nickel plating process, a first electroless gold plating process, an electroless palladium plating process and a second electroless gold plating process that is forming a nickel metal layer on the aluminum metal electrode pad, forming a first gold metal layer on the nickel metal layer, forming a palladium metal layer on the first gold metal layer and forming a second gold metal layer on the palladium metal layer; and
wherein the order of arrangement from below is respectively the aluminum metal electrode pad, the nickel metal layer, the first gold metal layer, the palladium metal layer, the second gold metal layer and the metal bump.

US Pat. No. 10,483,230

BONDING PACKAGE COMPONENTS THROUGH PLATING

Taiwan Semiconductor Manu...

1. A package comprising:a first package component comprising a first electrical connector, wherein the first electrical connector comprises a first sidewall surface;
a second package component comprising a second electrical connector, wherein the second electrical connector comprises a second sidewall surface; and
a metal layer formed of a non-solder metallic material, the metal layer comprising:
a first portion on the first sidewall surface;
a second portion on the second sidewall surface, wherein the first portion is continuously connected to the second portion, and the first electrical connector and the second electrical connector are physically separated from each other; and
a third portion completely separating the first electrical connector and the second electrical connector from each other, wherein the first portion, the second portion, and the third portion form a single continuous layer.

US Pat. No. 10,483,228

APPARATUS FOR BONDING SEMICONDUCTOR CHIP AND METHOD FOR BONDING SEMICONDUCTOR CHIP

PROTEC CO., LTD., Gyeong...

1. A semiconductor chip bonding apparatus, comprising:a fixing member configured to fix a lower surface of a plurality of chip-substrate assemblies in which a non-conductive resin layer and a semiconductor chip are sequentially stacked on a substrate;
a pressing member arranged above the fixing member, the pressing member comprising a transparent portion through which a laser beam penetrates;
a lifting member configured to lift or lower one of the fixing member and the pressing member relative to the other of the fixing member and the pressing member to pressurize the semiconductor chips of the plurality of chip-substrate assemblies such that solder bumps of one of the semiconductor chips and the substrate penetrate the non-conductive resin layer to electrically contact the other of the semiconductor chips and the substrate; and
a laser head configured to irradiate the laser beam to the chip-substrate assemblies pressurized by using the pressing member, through the transparent portion of the pressing member, so as to bond solder bumps of one of the semiconductor chips and the substrate to the other of the semiconductor chips and the substrate,
wherein the pressing member further comprises a mask portion that is formed of an opaque material and supports the transparent portion,
wherein the transparent portion of the pressing member is disposed in areas respectively corresponding to the plurality of chip-substrate assemblies,
wherein the mask portion is disposed in a corresponding area between the plurality of chip-substrate assemblies.

US Pat. No. 10,483,213

DIE IDENTIFICATION BY OPTICALLY READING SELECTIVELY BLOWABLE FUSE ELEMENTS

STMicroelectronics S.r.l....

1. An integrated circuit, comprising:integrated functional circuitry;
an array of fuse elements, each fuse element having a first terminal and a second terminal, wherein the first terminals are directly connected to a fuse sensing node;
a first switch actuated by a first control signal to apply a programming voltage to the fuse sensing node;
a second switch actuated by a second control signal to apply a reading current to the fuse sensing node; and
a demultiplexing circuit comprising:
a switching circuit connected in series with each fuse element within the array of fuse elements at the second terminal; and
a decoder circuit configured to:
selectively actuate the switching circuits in a first mode when the first control signal actuates the first switch and the second switch is deactuated so as to cause the programming voltage to be applied at the fuse sensing node and across selected ones of the fuse elements within the array of fuse elements which is sufficient to blow the selected fuse element so as to program individual fuse elements within the array of fuse elements with data bits defining a die identification that specifies a location of the integrated circuit die on a wafer from which the integrated circuit die was singulated; and
selectively actuate the switching circuits in a second mode when the second control signal actuates the second switch and the first switch is deactuated so as to cause the reading current to be applied at the fuse sensing node and across the fuse elements within the array of fuse elements to generate an output signal at the fuse sensing node indicating whether the fuse element is blown so as to read the data bits defining the die identification.

US Pat. No. 10,483,205

CONTACT USING MULTILAYER LINER

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:patterning an opening within a substrate of a multi-layer integrated circuit device, said substrate comprising silicon;
performing a cleaning process of the opening;
forming a lower blocking layer within the opening, and the lower blocking layer contacts a surface of the opening, wherein the cleaning process leaves oxygen and fluorine particles within an area of the substrate adjacent the lower blocking layer;
forming a middle liner layer within the opening, and the middle liner layer contacts the lower blocking layer and comprises an oxide;
forming an upper blocking layer within the opening, and the upper blocking layer contacts the middle liner layer, and the middle liner layer is formed to be between the lower blocking layer and the upper blocking layer; and
forming a conductor layer within the opening, and the conductor layer contacts the upper blocking layer and comprises a conductive contact within the multi-layer integrated circuit device.

US Pat. No. 10,483,199

SEMICONDUCTOR DEVICE WITH COILS IN DIFFERENT WIRING LAYERS

Renesas Electronics Corpo...

1. A semiconductor device comprising:a substrate having a main surface and a rear surface opposite the main surface;
a first insulating film formed on the main surface of the substrate;
a first coil formed on the first insulating film;
a second insulating film formed on the first coil;
a first wiring formed on the second insulating film;
a third insulating film formed on the first wiring;
a groove formed in the third insulating film and separating the third insulating film into a first portion of the third insulating film and a second portion of the third insulating film in a plan view;
a second coil formed on the first portion of the third insulating file and overlapped with the first coil in a cross section view; and
a second wiring formed on the second portion of the third insulating film and in the groove,
wherein the groove surrounds the first and second coils in the plan view, and
wherein the groove overlaps with the first wiring in the cross section view.

US Pat. No. 10,483,196

EMBEDDED TRACE SUBSTRATE STRUCTURE AND SEMICONDUCTOR PACKAGE STRUCTURE INCLUDING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A substrate structure, comprising:a carrier having a first surface and a second surface;
a first metal layer disposed on the first surface of the carrier, wherein the first metal layer includes a base metal layer and a conductive metal layer, the base metal layer is disposed on the first surface of the carrier, and the conductive metal layer is disposed on the base metal layer;
a circuit layer disposed on the conductive metal layer of the first metal layer; and
a dielectric layer covering the circuit layer and defining a plurality of openings to expose portions of the circuit layer and portions of the first metal layer.

US Pat. No. 10,483,187

HEAT SPREADING DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:placing a die stack on a front side of a device wafer;
forming conductive connectors on a back side of the device wafer;
singulating the device wafer to form an integrated circuit die, the die stack disposed on the integrated circuit die;
placing the integrated circuit die on a carrier substrate;
bonding a front side of a dummy wafer to the integrated circuit die, the die stack disposed in a recess in the front side of the dummy wafer;
debonding the integrated circuit die from the carrier substrate; and
singulating the dummy wafer to form a dummy semiconductor feature, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die.

US Pat. No. 10,483,170

METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION

Taiwan Semiconductor Manu...

1. A method comprising:providing a substrate including a first fin element and a second fin element extending from the substrate;
forming a first layer including an amorphous material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements; and
performing an anneal process to remove the gap in the first layer,
wherein the amorphous material of the first layer remains amorphous during the performing of the anneal process.

US Pat. No. 10,483,159

MULTI-METAL FILL WITH SELF-ALIGN PATTERNING

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate with a metallization layer;
a dielectric layer formed over the metallization layer;
first conductive structures formed of a first conductive material and embedded in the dielectric layer; and
second conductive structures formed of a second conductive material and embedded in the dielectric layer, wherein the first conductive material and the second conductive material are different from one another, the first and second conductive structures have an alternating arrangement, and the first and second conductive structures have coplanar top surfaces with the dielectric layer.

US Pat. No. 10,483,158

CONTACT HOLE STRUCTURE AND METHOD OF FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A contact hole structure, comprising:a substrate having a top surface;
an epitaxial layer embedded within the substrate;
a contact hole disposed in the epitaxial layer, wherein the contact hole in the epitaxial layer has an inner surface comprising a convex curved portion and a concave curved portion, the convex curved portion is in a shape of a first circular arc and the concave curved portion is in a shape of a second circular arc, and wherein the contact hole has an intersection coplanar with the top surface, and a first width of the intersection is larger than a third width of any part of the contact hole below the intersection, and the first width and the third width are parallel; and
a silicide layer filling in the contact hole, wherein the convex curved portion and the concave curved portion directly contact the silicide layer.

US Pat. No. 10,483,154

FRONT-END-OF-LINE DEVICE STRUCTURE AND METHOD OF FORMING SUCH A FRONT-END-OF-LINE DEVICE STRUCTURE

GLOBALFOUNDRIES Inc., Gr...

14. A method, comprising:etching a first trench into a semiconductor substrate;
consecutively forming first and second insulating liners in said first trench;
forming a first insulating filling material on said first and second insulating liners in said first trench;
performing a recessing process after said first insulating filling material is formed, wherein an upper portion of said first insulating filling material is removed and an upper portion of said second insulating liner is exposed;
performing a pullback etching process, wherein said exposed upper portion of said second insulating liner material is removed and an upper surface portion of said first insulating liner is exposed; and
filling said first trench with a second insulating filling material, wherein said exposed upper surface portion of said first insulating liner is directly contacted by said second insulating filing material.

US Pat. No. 10,483,152

HIGH RESISTIVITY SEMICONDUCTOR-ON-INSULATOR WAFER AND A METHOD OF MANUFACTURING

GlobalWafers Co., Ltd., ...

1. A multilayer structure comprising:a single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 3000 ohm-cm;
a relaxed semiconductor layer comprising germanium in a molar percent of germanium of at least 20 molar %, the relaxed semiconductor layer in interfacial contact with the front surface of the single crystal semiconductor handle substrate;
a charge trapping layer comprising a polycrystalline silicon layer in interfacial contact with the relaxed semiconductor layer, wherein the charge trapping layer has a resistivity of at least about 1000 ohm-cm;
a dielectric layer in interfacial contact with the charge trapping player comprising the polycrystalline silicon layer; and
a single crystal semiconductor device layer in interfacial contact with the dielectric layer.

US Pat. No. 10,483,151

SUBSTRATE TRANSFER APPARATUS, SUBSTRATE PROCESSING APPARATUS, AND SUBSTRATE PROCESSING METHOD

SHIBAURA MECHATRONICS COR...

1. A substrate transfer apparatus, comprising:a first gripping plate;
a first claw fixedly supported by the first gripping plate, and has an abutment surface, which abuts on an outer peripheral surface of a substrate, located above and below a surface of the first gripping plate;
a second gripping plate overlapping the first gripping plate;
a second claw fixedly supported by the second gripping plate, and has an abutment surface, which abuts on the outer peripheral surface of the substrate, located above and below the surface of the first gripping plate; and
a gripper to move both the first gripping plate and the second gripping plate such that both the first claw and the second claw move to approach and separate from each other in a direction intersecting the outer peripheral surface of the substrate,
wherein the gripper includes
a support plate,
a linear guide supported by the support plate and extending in a direction in which the first claw and the second claw move to approach and separate from each other,
a first linear motion block fixed to the first gripping plate and configured to be movable along the linear guide,
a second linear motion block fixed to the second gripping plate and configured to be movable along the linear guide,
a cylinder connected to one of the first gripping plate and the second gripping plate to move the one of the gripping plates in the direction in which the first claw and the second claw move to approach and separate from each other, and
a swing pin mover configured to convert and transmit the movement of the one of the gripping plates caused by the cylinder to the other of the gripping plates such that the other of the gripping plates moves in a direction opposite to the movement of the one of the gripping plates.

US Pat. No. 10,483,149

WAFER PROCESSING METHOD FOR DIVIDING A WAFER, INCLUDING A SHIELD TUNNEL FORMING STEP

DISCO CORPORATION, Tokyo...

1. A wafer processing method for dividing a wafer including a single-crystal silicon substrate having on a face side thereof a plurality of devices disposed in respective areas demarcated by a plurality of intersecting projected dicing lines, into individual device chips, the method comprising:a protective member placing step of placing a protective member on the face side of the wafer;
a shield tunnel forming step of, after performing the protective member placing step, applying a laser beam, which has a wavelength that is transmittable through single-crystal silicon, to areas of the wafer that correspond to the projected dicing lines from a reverse side of the wafer, thereby successively forming a plurality of shield tunnels in the wafer, each including a fine pore extending from the reverse side to the face side of the wafer and an amorphous region surrounding the fine pore; and
a dividing step of, after performing the shield tunnel forming step, dividing the wafer into individual device chips by etching the shield tunnels according to plasma etching,
wherein the pulsed laser beam used in the shield tunnel forming step has a wavelength of 1950 nm or higher.

US Pat. No. 10,483,148

PROTECTIVE TAPE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

DEXERIALS CORPORATION, T...

1. A method for manufacturing a semiconductor device, the method comprising:pasting a protective tape to a surface of a wafer on which a bump electrode is formed, the protective tape having an adhesive agent layer, a thermoplastic resin layer, and a matrix film layer in this order;
grinding a surface of the wafer opposite to the surface on which the protective tape is pasted;
pasting an adhesive tape to the ground surface of the wafer;
peeling the protective tape so that the adhesive agent layer remains and other layers are removed;
dicing the wafer to which the adhesive tape is pasted to obtain individual semiconductor chips; and
curing the adhesive agent layer before dicing, wherein:
the adhesive agent layer after curing has a shear storage modulus of 3.0E+08 Pa to 5.0E+09 Pa, and
the ratio of the thickness of the adhesive agent layer of the protective tape before pasting to the height of the bump electrode is 1/30 to 1/6.

US Pat. No. 10,483,146

ELECTROSTATIC CHUCK HEATER

NGK Insulators, Ltd., Na...

1. An electrostatic chuck heater comprising:an electrostatic chuck in which an electrostatic electrode is embedded in a ceramic sintered body;
a small-zone formation region provided inside the ceramic sintered body or a heater support body that is integrated with the ceramic sintered body, the small-zone formation region including a plurality of small zones in which small heater electrodes are wired;
a power source to which the plurality of small heater electrodes are connected in parallel; and
a small-zone control apparatus that performs control such that desired electric power is supplied to each of the small heater electrodes by using an output ratio to a suppliable output corresponding to each of the small heater electrodes,
wherein among the plurality of small heater electrodes, a small heater electrode that is wired in a small zone including a cool spot has a resistance that is set to a smaller value than that of the other small heater electrodes.

US Pat. No. 10,483,145

WAFER EDGE MEASUREMENT AND CONTROL

APPLIED MATERIALS, INC., ...

1. An apparatus for processing a substrate, comprising:a chamber body defining an inner volume;
a substrate positioning assembly disposed in the inner volume, wherein the substrate positioning assembly is capable of positioning and rotating the substrate at least within a horizontal plane;
a first capacitive sensor disposed in the inner volume, wherein the first capacitive sensor is positioned to detect a location of an edge of the substrate at a first edge location;
a second capacitive sensor disposed in the inner volume, wherein the second capacitive sensor is positioned to detect the location of the edge of the substrate at a second edge location;
a third capacitive sensor disposed in the inner volume at a position between the first and second capacitive sensors, wherein the third capacitive sensor is positioned to detect a vertical location of the substrate; and
a controller coupled to the first, second, and third capacitive sensors, wherein the controller is programmed to determine a first time period when a non-uniform portion on the edge of the substrate passes through a field of view of the first capacitive sensor and to determine a second time period when the non-uniform portion passes through a field of view of the second capacitive sensor.

US Pat. No. 10,483,143

END EFFECTOR AND SUBSTRATE CONVEYING ROBOT

KAWASAKI JUKOGYO KABUSHIK...

1. An end effector capable of holding two or more substrates, comprising:a base at least a part of which advances below a lowermost substrate or above an uppermost substrate of a plurality of substrates stored in substrate storage;
a substrate holder provided on the base so as to hold the two or more substrates including the lowermost substrate or the uppermost substrate, the substrate holder comprising
a substrate support provided on a distal end side of an end effector body including the base, the substrate support including a surface supporting a bottom surface edge portion of the substrate, and
a connector comprising a rotary spindle connecting the substrate support to the distal end side of the end effector body so that the substrate support pivots in response to an external force when the external force is applied to the substrate support; and
a servo motor for changing a protrusion amount of the substrate holder from a reference surface including a surface of the base opposed to the lowermost substrate or the uppermost substrate,
wherein the servo motor is configured for applying a drive force to a whole of the substrate holder, and
wherein a vertical pitch of the two or more substrates held by the substrate holder is changed by changing the protrusion amount of the substrate holder by the servo motor.

US Pat. No. 10,483,141

SEMICONDUCTOR PROCESS EQUIPMENT

APPLIED MATERIALS, INC., ...

1. A substrate transport system, comprising:a chamber having an interior wall;
a planar motor disposed on the interior wall;
a substrate carrier magnetically coupled to the planar motor, the substrate carrier comprising:
a base;
a substrate supporting surface coupled to a support member extending from the base in a cantilevered orientation; and
an electrically conductive plate to apply radio frequency power to the chamber.

US Pat. No. 10,483,136

CERAMIC HEATER AND ELECTROSTATIC CHUCK

NGK SPARK PLUG CO., LTD.,...

1. A ceramic heater having a plate-like form and comprising:a laminate of a ceramic substrate and a base substrate, the ceramic substrate including an internal heat-generating element,
wherein, as viewed in a thickness direction, the ceramic heater has heating zones and a hole region disposed within a certain one of the heating zones, the hole region corresponding to:
(a) a hole defined by the ceramic substrate, or
(b) a through hole defined by the base substrate;
the internal heat-generating element includes zone heat-generating elements disposed in respective heating zones so as to heat the ceramic substrate independently; and
a zone heat-generating element disposed in the certain one of the heating zones having the hole region is formed of a heat-generating conductor which has a first parallel segment disposed in parallel with a second adjacent parallel segment and a turning-back segment which connects, while turning back, the first and second parallel segments of the heat-generating conductor extending toward the hole region so as to prevent the first and second parallel segments extending toward the hole region from overlying the hole region;
wherein, as viewed in the thickness direction, the entire turning-back segment is positioned between the first parallel segment and the second parallel segment.

US Pat. No. 10,483,135

ETCHING METHOD

TOKYO ELECTRON LIMITED, ...

1. An etching method for a target object including a main surface, grooves formed in the main surface, and an etching target film covering the main surface and surfaces of the grooves, the method comprising:a first step of accommodating the target object in a processing chamber of a plasma processing apparatus;
a second step of supplying a first gas into the processing chamber; and
a third step of supplying a second gas and a high frequency power for plasma generation into the processing chamber and generating in the processing chamber a plasma of a gas including the second gas in the processing chamber,
wherein: the first gas contains an oxidizing agent that does not include a hydrogen atom;
the second gas contains a compound that includes one or more silicon atoms and one or more fluorine atoms and does not include a hydrogen atom;
the etching target film is made of a material that is dry etched by using fluorine;
portions of the etching target film which cover the surfaces of the grooves are selectively removed;
the etching target film is made of TiN; and
the temperature of the target object in the third step is lower than 250° C.

US Pat. No. 10,483,127

METHODS FOR HIGH PRECISION PLASMA ETCHING OF SUBSTRATES

Tokyo Electron Limited, ...

1. A method for treating a substrate, comprising:receiving a substrate on a substrate holder in a plasma process chamber, a patterned overlying layer being formed over the substrate to form a first exposed portion of the substrate;
treating a first exposed portion of the substrate using a first plasma in the plasma process chamber so as to form a first adsorbed layer in the first exposed portion of the substrate, the first adsorbed layer being formed using a combination of elements from the first plasma and the substrate, the first adsorbed layer extending into the substrate with a first thickness;
removing the first adsorbed layer selectively from the substrate using a second plasma in the plasma process chamber so that a second exposed portion of the substrate is formed, the second exposed portion of the substrate having sidewalls and a bottom;
treating the second exposed portion of the substrate using the first plasma so as to form a second adsorbed layer in the second exposed portion of the substrate, the second adsorbed layer being formed using the combination of elements from the first plasma and the substrate, the second adsorbed layer having side portions extending into the sidewalls of the second exposed portion of the substrate with a second thickness, and a bottom portion extending into the bottom of the second exposed portion of the substrate with a third thickness; and
removing, selectively, the second adsorbed layer using the second plasma.