US Pat. No. 10,171,200

OPTICAL COMMUNICATION USING SUPER-NYQUIST SIGNALS

ZTE Corporation, Shenzhe...

23. An optical communication system, comprising:an optical signal transmission apparatus that transmits a multi-channel optical signal carrying data; and
an optical signal receiver that receives the multi-channel optical signal and recovers the data using a 9-Quadrature Modulated (9-QAM) multi-modulus blind equalization (MMBE) algorithm with maximum likelihood sequence detection (MLSD);
wherein the optical signal transmission apparatus:
for a first optical channel from a plurality of optical channels having an equal baud rate:
maps data using a quadrature phase shift keying (QPSK) constellation into a modulated signal;
upsamples the modulated signal, thereby generating an upsampled signal;
filters the upsampled signal using a digital super-Nyquist lowpass filter having a cutoff frequency that is less than or equal to half of the baud rate, thereby generating a bandlimited modulated digital signal; and
converts the bandlimited modulated digital signal into a first optical analog signal; and
optically multiplexes the first optical analog signal of the first optical channel with a second optical analog signal of a second optical channel from the plurality of optical channels to generate a multi-channel optical signal carrying data.

US Pat. No. 10,171,199

TUNABLE LASER IN AN OPTICAL ACCESS NETWORK

Google LLC, Mountain Vie...

16. A method comprising:receiving, at data processing hardware, a request to transmit a data packet from an optical network unit (ONU) to an optical line terminal (OLT) of an optical access network having a multiplexer optically coupled between the ONU and the OLT, the multiplexer having a wavelength pass-band, the ONU comprising a tunable laser configured to continuously transmit an optical signal that alternates between a burst-on state and a burst-off state;
triggering, by the data processing hardware, the burst-on state of the tunable laser by transmitting a burst-on current to the tunable laser, the burst-on current biasing the tunable laser to transmit the optical signal at a transmit wavelength within the wavelength pass-band of the multiplexer, the multiplexer configured to allow passage therethrough of the optical signal at the transmit wavelength;
instructing, by the data processing hardware, the tunable laser to transmit the data packet in the optical signal; and
after transmission of the data packet, enabling, by the data processing hardware, the burst-off state of the tunable laser by transmitting a burst-off current to the tunable laser, the burst-off current biasing the tunable laser to transmit the optical signal at a non-transmit wavelength outside of the wavelength pass-band of the multiplexer, the multiplexer configured to block passage therethrough of the optical signal at the non-transmit wavelength.

US Pat. No. 10,171,198

CHANNEL SET UP METHOD OF OPTICAL RECEIVER WITH WAVELENGTH TUNABLE FILTER

PHOVEL. CO.LTD., Yuseong...

1. A method of controlling a temperature of a wavelength tunable filter in order to select desired channels of an optical receiver, and the channels being selected by changing a temperature of the wavelength tunable filter using two adjacent transmissive modes among transmissive modes of an FP type etalon filter have a cyclic characteristic, the method comprising:(a) selecting a referenced channel temperature range via the FP type etalon filter and scanning the temperature of the wavelength tunable filter, in the selected referenced channel temperature range, to determine a wavelength of a transmissive peak in a current transmissive mode selected in the selected referenced channel temperature range from communication signal channels having a predetermined wavelength spacing;
(b) storing a first temperature (TO+T1) of the wavelength tunable filter into a memory, and, based on a current temperature (TO) of the wavelength of the transmissive peak, increasing the temperature of the wavelength tunable filter to the first temperature (TO+T1) to obtain a first reference channel located within a predetermined temperature range;
(c) increasing the temperature of the wavelength tunable filter via one of a heater and a thermoelectric element, with regard to a communication signal channel having a wavelength existing after the transmissive peak in the current transmissive mode, by a second increase in temperature (+A) which corresponds a second reference channel (+1);
(d) increasing the temperature of the wavelength tunable filter via one of the heater and the thermoelectric element, with regard to the communication signal channel having the wavelength existing after the transmissive peak in the current transmissive mode, by a third increase in temperature (+2A) which corresponds a third reference channel (+2);
(e) increasing the temperature of the wavelength tunable filter via one of the heater and the thermoelectric element, with regard to the communication signal channel having the wavelength existing after the transmissive peak in the current transmissive mode, by a fourth increase in temperature (+3A) which corresponds a third reference channel (+3); and
(f) storing, in the memory, information which corresponds to at least the first reference channel, the second reference channel (+1), the third reference channel (+2), and the fourth reference channel (+3).

US Pat. No. 10,171,197

METHOD AND APPARATUS FOR ROUTING TRAFFIC USING ASYMMETRICAL OPTICAL CONNECTIONS

1. A method for routing traffic in a reconfigurable optical add-drop multiplexer layer of a dense wavelength division multiplexing network, the method comprising:determining, by a processor, the reconfigurable optical add-drop multiplexer layer has asymmetric traffic, wherein a symmetry ratio is calculated by an equation of,
wherein ?network is the symmetry ratio of the entire network, t(Zi?Ai) is an amount of traffic in bits per second traveling from node Z to node A for each link i and t(Ai?Zi) is an amount of traffic in bits per second traveling from node A to node Z for each link i; androuting, by the processor, the asymmetric traffic in the reconfigurable optical add-drop multiplexer layer over a plurality of asymmetrical optical connections, wherein the plurality of asymmetrical optical connections is provided with only uni-directional equipment in the reconfigurable optical add-drop multiplexer layer, wherein the routing comprises changing a route of the asymmetric traffic in one direction from travelling directly from an internet protocol layer to the reconfigurable optical add-drop multiplexer layer by by-passing an optical transport network layer to travelling from the internet protocol layer to the reconfigurable optical add-drop multiplexer layer via the optical transport network layer.

US Pat. No. 10,171,196

TERMINAL DEVICE, BASE STATION APPARATUS, AND INTEGRATED CIRCUIT

SHARP KABUSHIKI KAISHA, ...

1. A terminal device that communicates with a base station device, comprising:higher layer processing circuitry configured to receive configuration information;
reception circuitry configured to monitor downlink control information (DCI) via a physical downlink control channel (PDCCH); and
signal detection circuitry configured to detect a modulation and coding scheme (MCS) for the terminal device based on the monitored DCI,
wherein, the configuration information includes whether a prescribed reception scheme for a multi-user transmission is applied or not,
in a case where the prescribed reception scheme is applied, the signal detection circuitry detects a modulation scheme of an interference from the DCI,
in a case where the prescribed reception scheme is not applied, the signal detection circuitry detects the MCS for the terminal device from the DCI, and
the DCI is defined in a same DCI format regardless of whether the prescribed reception scheme is applied or not.

US Pat. No. 10,171,195

NAICS SIGNALING FOR ADVANCED LTE FEATURES

Qualcomm Incorporated, S...

1. A method of wireless communication of a user equipment (UE), comprising:receiving a configuration with carrier aggregation; and
determining a first starting symbol for a physical downlink shared channel (PDSCH), wherein the first starting symbol for the PDSCH is determined based on a blind detection, wherein the determining the first starting symbol for the PDSCH comprises:
performing blind detection of one or more PDSCH symbols on a per resource block basis in order to determine the first starting symbol.

US Pat. No. 10,171,194

INTERFERENCE MANAGEMENT AND DECENTRALIZED CHANNEL ACCESS SCHEMES IN HOTSPOT-AIDED CELLULAR NETWORKS

Board of Regents, The Uni...

1. A system for decentralized spectrum allocation in a two-tier network, comprising:one or more low power base stations deployed in a secondary tier within a coverage range of a macro cellular base station deployed in a first tier, wherein the macro cellular base station utilizes a wireless frequency band and respective low power base stations utilize a wireless frequency band that is the same as the macro cellular base station wireless frequency band,
wherein respective low power base stations are configured to employ at least one cross-tier interference avoidance technique such that coexistence between the macro cellular base station and the corresponding low power base station is enabled, the at least one cross-tier interference avoidance technique comprising the use of two or more transmit antennas at the low power base station to null interference in the direction of a nearby macro cellular base station's user, and
wherein the direction to null the low power base station's transmissions is determined by channel state feedback sent from the macro cellular base station's downlink user to its associated macro base station.

US Pat. No. 10,171,193

FRACTIONAL MULTIPLEXING OF SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE LINKS

Microsemi Solutions (U.S....

1. A method in a Serial Attached SCSI (SAS) system, the method comprising:establishing an SAS serial connection between an SAS initiator and an SAS expander over a physical link for communications between the SAS initiator and a plurality of target devices, the plurality of target devices being in communication with the SAS expander; and
transmitting SAS packets associated with each of the plurality of target devices over the SAS connection, wherein the transmitting comprises dynamically multiplexing the SAS packets of each of the plurality of target devices over the SAS connection, and wherein each SAS packet comprises one or more information bits indicating the target device with which the SAS packet is associated,
wherein the dynamic multiplexing comprises scheduling the SAS packets associated with each of the target devices according to a weighted round robin scheme where the weight assigned to SAS packets of each of the target devices is proportionally based on the maximum physical link rate supported by the respective target device.

US Pat. No. 10,171,192

METHOD OF PROVIDING AN EMERGENCY ALERT SERVICE VIA A MOBILE BROADCASTING AND APPARATUS THEREFOR

LG ELECTRONICS INC., Seo...

1. A method of providing an emergency alert in a broadcast transmitter, the method comprising:generating service data of a broadcast service;
generating an emergency alert table including an emergency alert message;
generating an additional content related to the emergency alert message;
generating wake-up information indicating whether a broadcast receiver is to be woken up; and
transmitting a broadcast signal including the service data, the emergency alert table, the additional content, and the wake-up information,
wherein the emergency alert table further includes information for identifying a viewing target for the emergency alert message and emergency-related broadcast service information for an emergency-related broadcast service,
wherein the emergency-related broadcast service information includes information for identifying the emergency-related broadcast service and information for identifying a broadcast stream delivering the emergency-related broadcast service,
wherein the wake-up information indicates a wake-up call by being changed from 0 to 1, and
wherein the wake-up information indicates a different wake-up call from the wake-up call by being changed from 1 to 2.

US Pat. No. 10,171,191

BROADCAST RECEIVING APPARATUS AND BROADCAST RECEIVING METHOD

DENSO TEN Limited, Kobe ...

1. A broadcast receiving apparatus comprising:a processor programmed to:
receive a signal of an analog broadcast and a signal of a digital broadcast having a same broadcast content;
perform, when an output of the broadcast receiving apparatus is switched into the analog broadcast from the digital broadcast, a switching control of switching into an acoustic characteristic of the analog broadcast from an acoustic characteristic of the digital broadcast so that the acoustic characteristic of the output digital broadcast gradually approaches the acoustic characteristic of the analog broadcast based on a reception intensity of the received signal of the analog broadcast; and
determine, after the switching control is started and in a middle of gradual switching from the acoustic characteristic of the digital broadcast to the acoustic characteristic of the analog broadcast, whether or not the started switching control is to be continued, based on a reception state of the received signal of the digital broadcast.

US Pat. No. 10,171,190

DEVICE AND METHOD FOR TESTING MIMO SCHEME SYSTEM

ANRITSU CORPORATION, Kan...

1. A device for testing a multi input multi output (“MIMO”) scheme system adopting a multicarrier modulation scheme using K carriers in communication with one mobile terminal,a MIMO scheme having the number of transmitting antennas N and the number of receiving antennas M, and a beam forming process scheme for setting radiation beam characteristics based on transmitting antennas having the number of antennas N, in which N×M channels and
a pseudo-propagation channel having U paths in each of the channels are assumed between the transmitting antennas and the receiving antennas, and signals received by the M receiving antennas through the propagation channel are generated to be given to a test object, the device comprising:
a layer frequency domain signal generation unit that generates R×K series of modulation signals in a frequency domain for each of the K carriers with the input of R layers' worth of data signal sequences to be transmitted to the test object;
a window function operation unit that performs a convolution operation of frequency characteristics of a window function in a time domain with the input of the R×K series of modulation signals, output by the layer frequency domain signal generation unit, as a process equivalent to signal excision based on multiplication of the window function in the time domain;
a fading setting unit that obtains propagation channel characteristics of all paths assumed between the transmitting antennas and the receiving antennas;
a beam forming equivalence operation unit that performs an operation process equivalent to the beam forming process for setting the radiation beam characteristics based on the transmitting antennas having the number of antennas N to desired characteristics, with the input of the N×M×U paths' worth of propagation channel characteristics obtained in the fading setting unit;
a Fourier transform unit that performs Fourier transform taking account of a delay for each path with the input of the propagation channel characteristics of all paths obtained by the beam forming equivalence operation unit, and obtains propagation channel characteristics in the frequency domain;
an operation unit that obtains spectrum information of a signal to be received in each of the receiving antennas by multiplications of the propagation channel characteristics in the frequency domain obtained by the Fourier transform unit and operation results of the window function operation unit;
a time domain signal generation unit that performs inverse Fourier transform processes with the input of the operation results of the operation unit, and generates signals in the time domain to be received by the receiving antennas; and
a shift addition unit that shifts and adds the signals in the time domain generated by the time domain signal generation unit by a length of the window function in the time domain, and generates consecutive signals to be received by the receiving antennas.

US Pat. No. 10,171,189

ROBUST POWER DETECTOR FOR WIDEBAND SIGNALS AMONG MANY SINGLE TONE SIGNALS

1. A method performed by a processor of a computing device, the method comprising:receiving signal data from a radar antenna that is in communication with the processor, the signal data comprising a plurality of amplitude values of a signal over a period of time, wherein the signal is received by the antenna, the signal comprising an echo return and a noise signal, the echo return present in the signal for a subset of the period of time;
determining that a ratio of an amplitude value in the amplitude values to a mean amplitude value of the amplitude values over the period of time exceeds a threshold value;
based upon determining that the ratio exceeds the threshold value, outputting an indication that the signal includes the echo return at a time corresponding to the amplitude value; and
isolating the echo return based upon the indication that the signal includes the echo return at the time corresponding to the amplitude value.

US Pat. No. 10,171,188

MOBILE COMPUTING DEVICE INCLUDING A GRAPHICAL INDICATOR

Hewlett-Packard Developme...

1. A mobile computing device, comprising:a display;
a housing coupled to the display, the housing including a chamber, a first antenna to communicate with a first wireless network, a first exterior antenna region, a second antenna to communicate with a second wireless network, and a second exterior antenna region;
a first graphical indicator to identify the first exterior antenna region on the housing and a first signal strength of a connection to the first wireless network; and
a second graphical indicator to identify the second exterior antenna region on the housing and a second signal strength of a connection to the second wireless network.

US Pat. No. 10,171,187

SYSTEM AND METHOD FOR TESTING HIGH-SPEED ADC IN DP-QPSK RECEIVER

XIAMEN UX HIGH-SPEED IC C...

1. A system for testing a high-speed analog-to-digital converter (ADC) in a Dual-Polarization Quadrature Phase Shift Keying (DP-QPSK) receiver, being characterized in comprising:a simulation module, for generating a DP-QPSK data flow, performing coupling and phase shift, and outputting a data flow;
an arbitrary waveform generator, connected to the simulation module for receiving the data flow and outputting a high-speed analog signal and a clock signal;
a high-speed ADC, connected to the arbitrary waveform generator, for converting the high-speed analog signal and the clock signal into a high-speed digital signal;
a cache memory circuit, connected to the high-speed ADC, for converting the high-speed digital signal into a low-speed digital signal; and
a logic analyzer, connected to the cache memory circuit, for sending the low-speed digital signal to the simulation module;
wherein the simulation module receives the low-speed digital signal and performs signal recovery and compares a recovered signal to an original signal so as to realize testing.

US Pat. No. 10,171,186

METHOD AND DEVICE FOR DETECTING NOTCH BAND

MSTAR SEMICONDUCTOR, INC....

1. A method for detecting a notch band in a bandwidth of a frequency spectrum of a received signal, applied to a multicarrier system operating in a wideband, the method comprising:receiving the received signal, and generating a plurality of frequency-domain signals according to the received signal;
performing a magnitude operation on the plurality of frequency-domain signals to obtain a plurality of magnitude values; and
determining whether there is a notch band in the bandwidth of the frequency spectrum of the received signal according to a plurality of ratios of a first magnitude set among the plurality of magnitude values to a second magnitude set among the plurality of magnitude values;
wherein, a first magnitude value in the first magnitude set corresponds to a second magnitude value in the second magnitude set, and a frequency where the first magnitude value is located is spaced from a second frequency where the second magnitude value is located by a fixed interval,
wherein the step of determining whether there is a notch band in the bandwidth of the frequency spectrum of the received signal according to the plurality of ratios of the first magnitude set among the plurality of magnitude values to the second magnitude set among the plurality of magnitude values comprises;
obtaining the plurality of ratios of the first magnitude set among the plurality of magnitude values to the second magnitude set among the plurality of magnitude values; and
determining whether there is a notch band in the bandwidth of the frequency spectrum of the received signal according to the plurality of ratios; and
wherein the step of obtaining the plurality of ratios comprises:
obtaining each of the plurality of ratios as a ratio of a third magnitude value in the first magnitude set to a fourth magnitude value in the second magnitude set corresponding to the third magnitude value.

US Pat. No. 10,171,185

DEVICE AND METHOD OF HANDLING SOFT INFORMATION

Realtek Semiconductor Cor...

1. A receiving device, comprising:a signal detection circuit, for receiving a plurality of compensated symbols on a plurality of subcarriers, to generate a plurality of soft information and a plurality demodulated symbols of the plurality of compensated symbols according to the plurality of compensated symbols;
a reliability circuit, coupled to the signal detection circuit, for generating a plurality of weights of the plurality of soft information according to a plurality of reliability information of the plurality of subcarriers; and
a decoding circuit, coupled to the signal detection circuit and the reliability circuit, for decoding the plurality of compensated demodulated symbols according to the plurality of soft information and the plurality of weights, to generate a plurality of decoded bits.

US Pat. No. 10,171,184

METHODOLOGY OF USING THE VARIOUS CAPABILITIES OF THE SMART BOX TO PERFORM TESTING OF OTHER FUNCTIONALITY OF THE SMART DEVICE

W2BI, INC., South Plainf...

1. An automatic system level testing (ASLT) system for testing smart devices, said system comprising:a system controller operable to be coupled to a smart device, wherein the system controller comprises a memory comprising test logic and a processor;
an enclosure comprising a plurality of components, the plurality of components comprising:
a robotic arm comprising a stylus, wherein the robotic arm and the stylus are operable to actuate buttons on a screen of the smart device;
a platform comprising a device holder, wherein the device holder is operable to hold the smart device inserted therein; and
a wireless access point, wherein the wireless access point is configured to transmit wireless signals for performing a test selected from the group consisting of: a Bluetooth test, a Wi-Fi test, a Near Field Communication (NFC) test and a wireless charge test;
and wherein the processor is configured to automatically control the smart device and the plurality of components in accordance with the test logic, and wherein the processor is further configured to:
control the smart device to activate a wireless mode therein by actuating a button associated with the wireless mode on the screen of the smart device using the robotic arm and the stylus;
receive wireless signals from the wireless access point using the smart device;
retrieve wireless scan results from the smart device; and
analyze the wireless scan results to determine wireless functionality for the smart device.

US Pat. No. 10,171,183

METHOD AND SYSTEM FOR INTERFERENCE MITIGATION IN WIRELESS COMMUNICATIONS ASSEMBLIES

PERASO TECHNOLOGIES INC.,...

1. A method in a wireless communications assembly having an antenna, a transceiver and a baseband processor, comprising:at the transceiver:
receiving, from the antenna, a modulated carrier signal having a carrier frequency and containing payload data;
demodulating the carrier signal to extract a baseband signal having a baseband frequency and containing the payload data;
generating from the baseband signal, at a converter, a digital baseband signal containing the payload data;
at an encoder:
receiving the digital baseband signal from the converter;
generating an encoded digital baseband signal encoding the payload data for transmission at an operating frequency; the encoded digital baseband signal having at least a threshold proportion of signal level transitions that, when transmitted at the operating frequency, have transition frequencies outside a predefined restricted frequency band; and
transmitting the encoded digital baseband signal to the baseband processor via an interface at the operating frequency.

US Pat. No. 10,171,182

SENDING KNOWN DATA TO SUPPORT FAST CONVERGENCE

Valens Semiconductor Ltd....

1. A transceiver configured to assist a second transceiver to recover rapidly from quality degradation in operating point of the second transceiver, the transceiver comprising:a receiver configured to receive from the second transceiver an indication to transmit known data; wherein utilizing the known data enables the second transceiver to recover within less than 1 millisecond from the quality degradation;
a transmitter configured to transmit the known data; wherein the known data comprises bitwise complement code words of an idle sequence, and each bitwise complement code word appears in the idle sequence; and
the transmitter is further configured to transmit the idle sequence within less than 1 millisecond from the moment of starts transmitting the known data, and before transmitting a data frame.

US Pat. No. 10,171,181

HIGH-BANDWIDTH UNDERWATER DATA COMMUNICATION SYSTEM

Fairfield Industries, Inc...

1. A system to perform seismic exploration in an aqueous medium, comprising:a detector to provide an indication to a wake-up system to turn on one or more of a storage and control system, a sensor, or an optical transmitter;
the wake-up system, in response to the indication from the detector, operational to:
identify an optical communication link established via the optical transmitter through the aqueous medium;
determine a quality control parameter of the optical communication link; and
validate, based on the quality control parameter the optical communication link established via the optical transmitter through the aqueous medium; and
the storage and control system operational to cause the optical transmitter to transmit, via the optical communication link validated by the wake-up system, data indicative of a parameter sensed by the sensor.

US Pat. No. 10,171,180

FIBER OPTIC COMMUNICATIONS AND POWER NETWORK

Radius Universal, LLC, L...

1. A method for providing power and data communication for at least one client end device, comprising:connecting at least one fiber optic cable of a fiber optic network from an external remote data source to a power insertion device, wherein the power insertion device is connected to a source of mains power;
converting, by the power insertion device, the mains power to low voltage power, wherein the low voltage power is approximately 60 volts or less;
delivering, via at least one hybrid cable and via at least one connection interface device, the low voltage power from the power insertion device to the at least one client end device, wherein the at least one connection interface device is connected to the power insertion device via the at least one hybrid cable, wherein the at least one hybrid cable comprises at least one fiber optic line and at least one low voltage power line, and wherein the at least one connection interface device is configure to request power in a first mode of operation and to leech power from power being provided to the at least one client end device in a second mode of operation; and
communicating, between the at least one client end device and the external remote data source, digital data via the at least one fiber optic line of the at least one hybrid cable and via the at least one fiber optic cable of the fiber optic network.

US Pat. No. 10,171,178

LASER COMMUNICATION SYSTEM

1. A laser communication system comprising;a plurality of lasers each having a laser beam populated by a plurality of entangled photons, at least one of said plurality of lasers having a laser scanner for moving said at least one laser beam emanating therefrom;
a laser beam detector array positioned for each said laser beam to impinge thereupon, each of the laser beams partially overlapping each other laser beam of said plurality of laser beams of entangled photons to create at least one interference pattern therebetween;
an encoding computer for encoding the interference patterns between at least two of said plurality of intersecting laser beams; and
a decoding computer for decoding the encoded interference patterns of said at least two of said plurality of overlapping laser beams impinging upon said laser beam detector array;
whereby data can be transmitted between points of a laser beam using the interference patterns in overlapping laser beams of entangled photons.

US Pat. No. 10,171,177

DIGITAL SIGNAL PROCESSOR, DIGITAL OPTICAL RECEIVER USING THE SAME, AND DIGITAL SIGNAL PROCESSING METHOD

NEC CORPORATION, Tokyo (...

1. A digital signal processor, comprising:a fixed equalizer configured to perform a distortion compensation process based on a fixed equalization coefficient on an input digital signal;
an adaptive equalizer configured to perform an adaptive distortion compensation process based on an adaptive equalization coefficient on an equalized digital signal output by the fixed equalizer;
a low-speed signal generator configured to generate a low-speed digital signal by intermittently extracting one of the input digital signal and the equalized digital signal;
a low-speed equalization coefficient calculation part implemented at least in hardware and configured to calculate a low-speed equalization coefficient to be used for a distortion compensation process of the low-speed digital signal; and
a fixed equalization coefficient calculation part implemented at least in the hardware and configured to calculate the fixed equalization coefficient by using, out of the low-speed equalization coefficient and a predetermined coefficient obtained by back calculation from a transfer function of a transmission line, the predetermined coefficient.

US Pat. No. 10,171,176

PHASE DEMODULATION METHOD AND CIRCUIT

Elenion Technologies, LLC...

18. An electrical circuit for demodulating a received PSK modulated carrier signal, the electrical circuit comprising:a first signal splitter configured to split the received PSK modulated carrier signal into two analog PSK-modulated signals, each comprising a PSK-modulated carrier wave with a carrier wave frequency f that may vary in time;
a multiplying circuit disposed to receive a first of the two analog PSK-modulated signals and configured to convert it into a frequency-multiplied carrier signal absent of PSK modulation;
a first frequency dividing flip-flop circuit configured to convert the frequency multiplied carrier signal into a first reference carrier wave signal with the carrier wave frequency f,
a first electrical signal mixer configured to mix the first reference carrier wave signal with the second of the two analog PSK-modulated signals to extract a first de-modulated signal therefrom; and,
an electrical transmission line connecting the first signal splitter with the first electrical signal mixer;wherein the received PSK modulated carrier signal comprises a BPSK modulated signal, wherein the multiplying circuit comprises a signal squaring circuit configured to output a frequency-doubled carrier wave signal, and wherein the electrical circuit further comprises:a second frequency dividing circuit connected in parallel with the first frequency dividing circuit so as to obtain a second reference carrier wave signal that is phase-shifted relative to the first reference carrier wave,
a second electrical signal mixer configured to mix the second reference carrier wave signal with a portion of the second of the two analog PSK-modulated signals, and
an electrical signal combiner disposed to combine outputs from the first and second electrical signal mixers to produce an output de-modulated signal.

US Pat. No. 10,171,175

METHOD AND APPARATUS FOR DESPREADING IN OPTICAL DOMAIN

Huawei Technologies Co., ...

1. An apparatus for despreading in an optical domain, comprising:an optical splitter configured to:
split a received optical signal into a first optical signal and a second optical signal;
output the first optical signal to an optical coupler; and
output the second optical signal to an optical modulator,
wherein the optical modulator is coupled to the optical splitter and is configured to:
perform field modulation on the second optical signal to obtain a third optical signal; and
output the third optical signal to the optical coupler, wherein a phase difference between the third optical signal and the first optical signal is a first difference,
wherein the optical coupler is coupled to the optical splitter and the optical modulator and is configured to:
perform phase deflection processing on the first optical signal and the third optical signal to obtain a fourth optical signal and a fifth optical signal respectively; and
output the fourth optical signal and the fifth optical signal to a balanced receiver,
wherein the balanced receiver is coupled to the optical coupler and is configured to:
superimpose electrical signals obtained by converting the fourth optical signal and the fifth optical signal to generate a first electrical signal; and
output the first electrical signal to an accumulator, and
wherein the accumulator is coupled to the balanced receiver and is configured to accumulate the first electrical signal in each code word period.

US Pat. No. 10,171,174

METHOD AND SYSTEM FOR OPTICAL VECTOR ANALYSIS

SUZHOU LIUYAOSI INFORMATI...

1. An apparatus comprising:a phase modulator having a first input port to receive a radiation and having a first output port to provide a first signal toward a device under test (DUT), wherein the phase modulator is configured to generate the first signal by performing phase modulation on the radiation received at the first input port;
an intensity modulator having a second input port to receive the radiation and having a second output port to provide a second signal toward the DUT, wherein the intensity modulator is configured to generate the second signal by performing intensity modulation on the radiation received at the second input port; and
a transfer function analyzer configured to determine a transfer function of the DUT based on the first signal and the second signal.

US Pat. No. 10,171,173

OPTICAL SIGNAL TRANSMISSION APPARATUS AND OPTICAL SIGNAL TRANSMISSION METHOD

NIPPON TELEGRAPH AND TELE...

1. An optical signal transmission apparatus comprising:a modulation unit which modulates a transmission signal;
a training signal sequence generation unit which generates a training signal sequence by generating a plurality of signal sequences which have power concentrated in a plurality of different frequency bands and subsequently modulating at least one of an amplitude and a phase of the plurality of signal sequences;
a signal multiplexing unit which appends the training signal sequence to the transmission signal; and
an electro-optical conversion unit which converts a signal sequence obtained by appending the training signal sequence to the transmission signal into an optical signal and transmits the optical signal.

US Pat. No. 10,171,172

OPTICAL TRANSMITTER OPERABLE FOR PULSE-AMPLITUDE MODULATION SIGNAL

SUMITOMO ELECTRIC DEVICE ...

1. An optical transmitter that outputs an optical signal with a pulse amplitude modulation (PAM) configuration, comprising:a light-generating device that generates the optical signal by receiving an electrical driving signal, the light-generating device having non-linearity in a transfer characteristic between the electrical driving signal and the optical signal; and
a driver that generates the electrical driving signal by receiving an input electrical signal, the driver including,
a PAM signal generator that receives the input electrical signal and outputs a PAM signal,
a level controller that adjusts electrical levels of the PAM signal based on the transfer characteristic of the light-generating device, the electrical levels setting optical levels of the optical signal to have preset ratios, and
an output driver that generates the electrical driving signal by superposing the electrical levels adjusted by the level controller with the PAM signal provided from the PAM signal generator,
wherein the driver further includes a memory that stores a plurality of transfer characteristics, the level controller adjusting the electrical levels based on one of the transfer characteristics read out from the memory.

US Pat. No. 10,171,171

METHOD AND SYSTEM FOR SELECTABLE PARALLEL OPTICAL FIBER AND WAVELENGTH DIVISION MULTIPLEXED OPERATION

Luxtera, Inc., Carlsbad,...

20. A system for communication, the system comprising:an optoelectronic transceiver integrated in a silicon photonics die, the optoelectronic transceiver comprising optical modulators, photodetectors, grating couplers, an optical source module coupled to the photonics die, and a fiber interface coupled to the photonics die, the optoelectronic transceiver being operable to:
in a first communication mode, communicate continuous wave (CW) optical signals from the optical source module to a first subset of the grating couplers for processing coarse wavelength division multiplexing (CWDM) signals
in a second communication mode, communicate CW optical signals from the optical source module to a second subset of the grating couplers for processing parallel single mode 4-channel (PSM-4) signals in the optical modulators;
transmit processed signals out of the photonics die utilizing a third subset of the grating couplers;
receive CWDM optical signals from the fiber interface coupled to a fourth subset of the grating couplers or receive PSM-4 optical signals from the fiber interface coupled to a fifth subset of the grating couplers; and
generate electrical signals from the received modulated optical signals utilizing the photodetectors.

US Pat. No. 10,171,170

MULTI-CHANNEL PARALLEL OPTICAL TRANSCEIVER MODULE

Global Technology Inc., ...

1. A multi-channel parallel optical transceiver module, comprising:a shell body and a circuit board located in the shell body;
an optical emitter base soldered to a first end of the circuit board;
a notch located on the optical emitter base for engaging the first end of the circuit board with the first end of the optical emitter base being soldered to two opposite sides of the circuit board;
a plurality of optical emitters disposed in parallel on the optical emitter base, wherein at least two of the optical emitter of the plurality of optical emitters are separated from each other by a block;
a plurality of lasers, each laser of the plurality of lasers disposed at a first side of an associated optical emitter of the plurality of optical emitters;
a plurality of lenses, each lens of the plurality of lenses being associated with a laser of the plurality of lasers and disposed at the first side of an associated optical emitter of the plurality of optical emitters;
a plurality of optical monitors, each optical monitor of the plurality of optical monitors disposed on a second end of the circuit board adjacent to an associated laser of the plurality of lasers, wherein each optical monitor is connected to an associated laser by a bonding wire, each optical monitor of the plurality of optical monitors and laser of the plurality of lasers being connected to a laser controller and a driving chip disposed on the circuit board;
an optical fiber array and a processing chip for received optical signals adhered onto the circuit board;
a first metal shielding mask disposed on the circuit board for covering and sealing the optical fiber array and the processing chip for the received optical signals; and
a second metal shielding mask disposed on the circuit board, for covering and sealing the first metal shielding mask, the optical monitor, the laser controller, and the driving chip.

US Pat. No. 10,171,169

SOFTWARE PROGRAMMABLE FLEXIBLE AND DYNAMIC OPTICAL TRANSCEIVERS

Ciena Corporation, Hanov...

1. A software programmable optical transceiver, comprising:one or more Field Programmable Gate Arrays (FPGAs); and
an electro-optical front end communicatively coupled to the one or more FPGAs, wherein the electro-optical front end comprises a transmitter and a receiver, wherein the transmitter is adapted to transmit a transmit signal from the one or more FPGAs and the receiver is adapted to receive a receive signal and provide the receive signal to the one or more FPGAs,
wherein one or more applications are utilized to dynamically configure the one or more FPGAs for digital functionality to operate the software programmable optical transceiver in an associated mode of a plurality of modes, the plurality of modes comprising a Data Center interconnect mode, a metro mode, a regional mode, a long-haul mode, and a submarine mode, each of said plurality of modes requiring different digital functionality based in part on distance, wherein the one or more applications for the associated mode are loaded in the one or more FPGAs as needed such that the software programmable optical transceiver is configured to operate in any one of the plurality of modes with only the one or more applications loaded for the associated mode.

US Pat. No. 10,171,168

OPTOELECTRONIC TRANSCEIVER WITH POWER MANAGEMENT

Intel Corporation, Santa...

1. An optoelectronic device comprising:a photodetector to receive an optical signal and generate an electrical signal based at least in part on the optical signal;
a loss of signal detector coupled with the photodetector, to detect when the photodetector is not receiving the optical signal; and
a re-timer coupled with the loss of signal detector, wherein a first component of the re-timer is to be disabled in response to a detection by the loss of signal detector that the optical signal has not been received for a first predetermined time period, and wherein a second component of the re-timer is to be disabled in response to a detection by the loss of signal detector that the optical signal has not been received for a second predetermined time period, the second predetermined time period being longer than the first predetermined time period.

US Pat. No. 10,171,167

MULTIMEDIA NETWORK DATA PROCESSING SYSTEM

Beijing JiShi HuiTong Tec...

1. A multimedia network data processing system, comprising:a head-end switch, configured to transmit multimedia network data of the data sent from a server to a terminal device, to a head-end network processor, wherein the multimedia network data is multimedia network data based on the TCP/HTTP protocol;
the head-end network processor, configured to encapsulate the multimedia network data to form a UDP packet, and send the UDP packet to a unidirectional broadcasting optical fiber network;
a data processing module, configured to receive the UDP packet from the unidirectional broadcasting optical fiber network, and decapsulate the UDP packet to obtain the multimedia network data based on the TCP/HTTP protocol for the terminal device to play; and
the unidirectional broadcasting optical fiber network, whose physical layer is based on fiber optic Ethernet protocol, configured to use one or more optical amplifiers and one or more optical splitters for unidirectional broadcasting to transmit IP data stream, the IP data stream comprising at least UDP multicast packets or UDP broadcast packets.

US Pat. No. 10,171,166

OPTICAL COMMUNICATION SYSTEM AND OPTICAL COMMUNICATION METHOD

NIPPON TELEGRAPH AND TELE...

1. An optical communication system comprising: a signal processing apparatus; and a wireless apparatus, in which functions of a base station are divided between the signal processing apparatus and the wireless apparatus, a periodic symbol sequence comprising a cyclic prefix appended to a signal of a predetermined size to which an IFFT (Inverse Fast Fourier Transform) has been applied is transmitted between the signal processing apparatus and the wireless apparatus by means of digital RoF (Radio over Fiber) transmission,the signal processing apparatus and the wireless apparatus each comprises a transmission unit and a reception unit,
the transmission unit comprises:
a first separation unit that acquires symbol information relating to a starting position of the symbol sequence and lengths of symbols constituting the symbol sequence and that equalizes the lengths of the symbols by separating a portion of the symbol sequence based on the acquired symbol information; and
a compression unit that compresses symbols that are to be compressed from which the separated portion of the symbol sequence has been removed, and
the reception unit comprises an expansion unit that expands the compressed symbols and restores the symbols.

US Pat. No. 10,171,165

VISIBLE LIGHT SIGNAL GENERATING METHOD, SIGNAL GENERATING APPARATUS, AND PROGRAM

PANASONIC INTELLECTUAL PR...

1. A method comprising:generating a preamble in which a first luminance value and a second luminance value alternately appear along a time axis, the first luminance value and second luminance value being different luminance values from each other;
generating a first payload in which the first luminance value and the second luminance value alternately appear along the time axis by determining a first time length of the first luminance value and a second time length of the second luminance value using a first formula, the first time length being a time length in which the first luminance value continues in the first payload, the second time length being a time length in which the second luminance value continues in the first payload, the first formula determining the first time length and the second time length according to a transmission target signal;
generating a visible light signal by joining the preamble and the first payload; and
transmitting the visible light signal by a change in luminance of a light source.

US Pat. No. 10,171,164

2D BARCODE-BASED BI-DIRECTIONAL WIRELESS TRANSMISSION SYSTEM

NATIONAL CHUNG CHENG UNIV...

1. A 2D barcode-based bi-directional wireless transmission system, comprising:a first apparatus comprising a first display screen, a first processing system and a first camera, the first processing system configured to store information, to execute software, to encode data to be transmitted into one or more 2D barcodes, to capture 2D barcodes of other apparatuses, and to decode the captured 2D barcodes;
a second apparatus comprising a second display screen, a second processing system and a second camera, the second processing system configured to store information, to execute software, to encode data to be transmitted into one or more 2D barcodes, to capture 2D barcode images of other apparatuses and to decode the captured 2D barcode images;
wherein said first apparatus is further configured to encode said data to be sent into multiple 2D barcode images, and then sequentially display said multiple 2D barcode images on the first display screen;
wherein said second apparatus is configured to use the second camera to photograph the first display screen so as to sequentially capture said multiple 2D barcode images from said first apparatus, and then decode the captured said multiple 2D barcode images into a received data for storage;
wherein said second apparatus is further configured to encode a feedback information into a first 2D barcode image and display the first 2D barcode image on the second display screen;
wherein said first apparatus is further configured to capture the first 2D barcode image of said feedback information by aiming the first camera at the second display screen and then decoding the captured first 2D barcode image of said feedback information so as to obtain said feedback information, and
wherein said second apparatus is configured to encode the data to be sent into multiple 2D barcode images and sequentially display the multiple 2D barcode images on the second display screen;
wherein said first apparatus is configured to capture the multiple 2D barcode images from said second apparatus by aiming the first camera at the second display screen, and then decode the captured 2D barcode images into a second received data for storage;
wherein said first apparatus is configured to encode a second feedback information into a second 2D barcode image and display the second 2D barcode image on the first display screen; and
wherein said second apparatus is configured to capture the 2D barcode image of said feedback information by aiming the second camera at the first display screen and then decoding the captured second 2D barcode image of said second feedback information so as to obtain said second feedback information.

US Pat. No. 10,171,163

SIGNAL QUALITY MEASUREMENT DEVICE AND SIGNAL QUALITY MEASUREMENT METHOD

FUJITSU LIMITED, Kawasak...

1. A signal quality measurement device that measures quality of an optical signal that is transmitted from a transmitter, passes through wavelength selective switches and optical amplifiers, and is received by a receiver,the signal quality measurement device comprising:
a memory, and
a processor coupled to the memory, the processor being coupled to:
set respective passbands of the wavelength selective switches; and
calculate the quality of the optical signal by acquiring a first power of an optical component in a first wavelength band including a center wavelength of the optical signal received by the receiver, and a second power of an optical component in a second wavelength band adjacent to the first wavelength band,
wherein the processor
detects a combined power of various amplified spontaneous emissions of the optical amplifiers from the second power, and detects a power of the optical signal from the first power and the second power, when the processor sets each of the passbands of the wavelength selective switches as a wavelength band including the first wavelength band and the second wavelength band,
detects, from the second power, the amplified spontaneous emission of at least one optical amplifier existing between one of the wavelength selective switches and the receiver among the optical amplifiers, when the processor sets the passband of one of the wavelength selective switches as the first wavelength band, and
calculates the quality of the optical signal from each of the detected powers.

US Pat. No. 10,171,162

APPARATUS AND METHOD FOR MEASURING FREQUENCY RESPONSE CHARACTERISTICS OF OPTICAL TRANSMITTER AND OPTICAL RECEIVER

FUJITSU LIMITED, Kawasak...

8. A method for measuring frequency response characteristics of an optical transmitter and an optical receiver, the optical transmitter including a modulator, and the optical receiver including a photoelectric detector, the modulator of the optical transmitter being directly connected to the photoelectric detector of the optical receiver, and signals outputted by the modulator being directly inputted into the photoelectric detector, the method comprising:generating a driving signal for driving the modulator of the optical transmitter, which driving signal comprises at least two frequencies; and
respectively calculating the frequency response characteristics of the optical transmitter and the optical receiver according to output signal components in output signals of the optical receiver corresponding to at least two detection signal components of identical amplitudes and different frequencies in detection signals;
wherein the detection signals have photoelectric conversion performed by the photoelectric detector of the optical receiver.

US Pat. No. 10,171,161

MACHINE LEARNING FOR LINK PARAMETER IDENTIFICATION IN AN OPTICAL COMMUNICATIONS SYSTEM

Ciena Corporation, Hanov...

1. A method for link parameter identification in an optical communications system, the method comprising:applying a first trained artificial neural network (ANN) to first input values representative of nonlinear noise in a signal received at a receiver from a transmitter over a link in the optical communications system, thereby generating first output values;
applying a second trained ANN to second input values comprising the first output values and one or more known parameters of the link, thereby generating second output values; and
identifying one or more link parameter estimates of the link based on the second output values.

US Pat. No. 10,171,160

ACCESSING LP TRANSPONDERS WITH CP TERMINALS VIA WAVEFRONT MULTIPLEXING TECHNIQUES

SPATIAL DIGITAL SYSTEMS, ...

1. A satellite communications system for communicating at a first frequency slot with a first pair of satellite transponders in linear polarization format and a second pair of satellite transponders in linear polarization format, the satellite communications system comprising:a first terminal configured for receiving at least one first input signal including a first pilot signal, processing the at least one first input signal, outputting a first output signal, and concurrently radiating the first output signal at the first frequency slot to the first pair of satellite transponders via a first beam in right-hand circularly polarized format and to the second pair of satellite transponders via a second beam in right-hand circularly polarized format;
a second terminal configured for receiving at least one second input signal including a second pilot signal, processing the at least one second input signal, outputting a second output signal, and concurrently radiating the second output signal in the first frequency slot to the first pair of satellite transponders via a third beam in left-hand circularly polarized format and to the second pair of satellite transponders via a fourth beam in left-hand circularly polarized format; and
a station configured for receiving first and second satellite signals from the first pair of satellite transponders, third and fourth satellite signals from the second pair of satellite transponders, each of the first, second, third, and fourth satellite signals comprising a linear combination of the first output signal and the second output signal, the station comprising:
a multi-beam antenna configured for receiving the first, second, third, and fourth satellite signals;
a set of frequency-down-converters coupled to the multi-beam antenna and configured for receiving and frequency-down-converting the first, second, third, and fourth satellite signals and outputting a set of down-converted signals;
an equalization unit coupled to the set of frequency-down-converters and configured for receiving and equalizing the down-converted signals and outputting equalized signals;
a wavefront de-multiplexer coupled to the equalization unit and configured for receiving the equalized signals, performing a wavefront de-multiplexing transformation on the equalized signals, and outputting at least one first recovered signal and at least one second recovered signal, the at least one first recovered signal being a recovered version of the at least one first input signal and including a first recovered pilot signal, the at least one second recovered signal being a recovered version of the at least one second input signal and including a second recovered pilot signal, the first and second recovered pilot signals being recovered versions of the first and second pilot signals, respectively; and
an optimizer configured for optimizing orthogonality of the wavefront de-multiplexer using the first and second recovered pilot signals.

US Pat. No. 10,171,159

DONOR SELECTION FOR RELAY ACCESS NODES USING REFERENCE SIGNAL BOOSTING

Sprint Spectrum L.P., Ov...

1. A method for donor selection in a relay access node, the method comprising:identifying a plurality of candidate donor access nodes;
obtaining one or more characteristics associated with each of the plurality of candidate donor access nodes;
determining a primary donor access node based on a comparison of the one or more characteristics between each of the plurality of candidate donor access nodes;
receiving a reference signal transmitted by the primary donor access node at a transmission power higher than a transmission power of downlink information transmitted by the primary donor access node;
evaluating one or more quality characteristics of the primary donor access node; and
based on the one or more quality characteristics meeting a predetermined threshold, requesting a connection to the primary donor access node.

US Pat. No. 10,171,158

ANALOG SURFACE WAVE REPEATER PAIR AND METHODS FOR USE THEREWITH

1. An analog surface wave repeater pair comprising:a first launcher configured to transmit and receive first guided electromagnetic waves that propagate on an outer surface of a first segment of a transmission medium without requiring an electrical return path;
a second launcher configured to transmit and receive second guided electromagnetic waves that propagate on an outer surface of a second segment of transmission medium without requiring an electrical return path;
a first transceiver including:
a first low noise amplifier configured to receive a first microwave signal from the first launcher, wherein the first microwave signal is generated by the first launcher in response to receiving the first guided electromagnetic waves from the first segment of the transmission medium;
a first notch filter configured to attenuate signals in a fourth generation (4G) wireless frequency band from the first microwave signal;
a first amplifier configured to amplify a second microwave signal; and
a first directional coupler configured to couple the first microwave signal from the first launcher and the second microwave signal to the first launcher to facilitate transmission of the first guided electromagnetic waves on the first segment of the transmission medium; and
a second transceiver including:
a second low noise amplifier configured to receive the second microwave signal from the second launcher, wherein the second microwave signal is generated by the second launcher in response to receiving the second guided electromagnetic waves from the second segment of the transmission medium;
a second notch filter configured to attenuate signals in the 4G wireless frequency band from the second microwave signal;
a second amplifier configured to amplify the first microwave signal; and
a second directional coupler configured to couple the second microwave signal from the second launcher and the first microwave signal to the second launcher to facilitate transmission of the second guided electromagnetic waves on the second segment of the transmission medium.

US Pat. No. 10,171,157

REPEATER

DENSO CORPORATION, Kariy...

1. A repeater for organizing a communication network, the repeater comprising:a port section having a plurality of ports, the port section configured to transmit and receive frames;
a memory configured to store communication efficiency information and connection information for each of a plurality of communication nodes on the communication network; and
a repeat processor configured
to retrieve a destination address of a frame received by the port section,
to select one of the plurality of the ports of the port section to transmit the received frame based on the destination address and the connection information stored in the memory, and
to transmit the received frame from the selected port, wherein
the repeat processor is further configured to perform a distribute-transfer process when a plurality of frames having a same destination address is received by the port section, by
defining a plurality of communication paths to the same destination address by referencing the connection information stored in the memory,
selecting one or more of the plurality of communication paths as a broadest path based on a preset communication efficiency parameter, the communication efficiency information stored in the memory, and the connection information stored in the memory,
selecting one communication path as the broadest path having a high communication efficiency when more than one of the plurality of communication paths are selected as the broadest path,
distributing one of the plurality of frames having the same destination address and having a highest communication speed to a port in connection with the broadest path, wherein
the communication efficiency information indicates a communication efficiency of each of the plurality of ports of the repeater and of each of a plurality of other ports associated with the communication nodes, and wherein
the connection information indicates connections among the communication nodes on the communication network.

US Pat. No. 10,171,156

APPARATUS AND METHOD FOR TRANSMITTING UPLINK INFORMATION IN A BROADCASTING SYSTEM

Samsung Electronics Co., ...

1. A mobile broadcasting system comprising:a first terminal including a transceiver configured to receive a broadcast signal and at least one processor configured to generate a first uplink signal comprising a first broadcast service identifier (ID) and first data using the broadcast signal;
a second terminal;
a repeater; and
a transmitting station for providing a broadcast service,
wherein the transceiver is further configured to transmit the first uplink signal to the repeater,
wherein a second uplink signal comprising a second broadcast service ID and second data is transmitted from the second terminal to the repeater,
wherein, in response to the first broadcast service ID matching the second broadcast service ID, the first broadcast service ID and the second broadcast service ID are removed, by the repeater, from the first uplink signal and the second uplink signal, respectively, to store the first data and the second data in a queue corresponding to the broadcast service identified by the first broadcast ID and the second broadcast ID, and generate, by the repeater, a third uplink signal comprising the first data and the second data based on information stored in the queue, and
wherein the third uplink signal is transmitted from the repeater to a transmitting station corresponding to the broadcast service identified by the first broadcast service ID and the second broadcast service ID.

US Pat. No. 10,171,155

PUCCH TRANSMIT DIVERSITY WITH ONE-SYMBOL STBC

QUALCOMM Incorporated, S...

1. A scheduling entity within a wireless communication network, comprising:a processor;
a memory communicatively coupled to the processor; and
a transceiver communicatively coupled to the processor, wherein the processor is configured to:
receive an uplink signal comprising an uplink control channel via the transceiver, the uplink control channel comprising a plurality of uplink control information, each transmitted by one of a set of scheduled entities, wherein each of the plurality of uplink control information comprises a plurality of single-carrier frequency division multiple access (SC-FDMA) symbols;
time domain de-spread the plurality of SC-FDMA symbols to produce a plurality of code blocks;
identify, from the plurality of code blocks, a first code block and a second code block that each comprise a same spreading code;
apply space-time block decoding over the first code block and the second code block to produce a first information block comprising a first set of modulated control symbols and a first cyclic affix appended to the first set of modulated control symbols and a second information block comprising a second set of modulated control symbols and a second cyclic affix appended to the second set of modulated control symbols; and
demodulate the first set of modulated control symbols and the second set of modulated control symbols to produce a plurality of control data.

US Pat. No. 10,171,154

METHOD FOR REPORTING BEAM INDEX FOR 3D MIMO TRANSMISSION IN WIRELESS COMMUNICATION SYSTEM, AND DEVICE THEREFOR

LG ELECTRONICS INC., Seo...

1. A method of reporting a beam index by a user equipment (UE) to an enhanced Node B (eNB) in a wireless access system, the method comprising:receiving a plurality of reference signals from the eNB;
measuring a plurality of beams using the plurality of the reference signals;
reporting an index of a most preferred beam among the plurality of the beams to the eNB; and
reporting information on at least one second preferred beam, which is determined on the basis of the most preferred beam, to the eNB,
wherein the information on the at least one second preferred beam corresponds to information on an index difference between the most preferred beam and the at least one second preferred beam.

US Pat. No. 10,171,153

METHOD AND APPARATUS FOR TRANSMITTING CHANNEL STATE INFORMATION IN WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for transmitting channel state information (CSI) by a user equipment in a wireless communication system, the method comprising:subsampling a first codebook associated with a first PMI (precoding matrix indicator) and a second codebook associated with a second PMI according to a reporting submode for 4 antenna ports,
wherein the subsampling, for selecting Discrete Fourier Transform (DFT) vectors, comprises selecting a second codebook index for the second PMI based on a first codebook index for the first PMI,
wherein the DFT vectors selected are odd-numbered vectors of vectors of a beam group constructing the first codebook if the first codebook index corresponds to an even number, and
wherein the DFT vectors selected are even-numbered vectors of the vectors of the beam group if the first codebook index corresponds to an odd number; and
transmitting the channel state information based on the subsampled first codebook and the second codebook.

US Pat. No. 10,171,152

COMMUNICATION METHOD AND APPARATUS USING SINGLE RADIO FREQUENCY CHAIN ANTENNA

ELECTRONICS AND TELECOMMU...

1. A communication method of a wireless device to which a single radio frequency (RF) chain antenna is applied, the communication method comprising:storing a plurality of beam sets for the single RF chain antenna and a plurality of quality values for the plurality of beam sets;
selecting a first beam set having a first quality value that is a best quality value among the plurality of stored beam sets;
confirming a second quality value for the first beam set using received data when the data are received using the first beam set; and
selecting a second beam set different from the first beam set among the plurality of stored beam sets when the second quality value is poorer than the first quality value,
wherein the confirming includes receiving a plurality of symbols within a predetermined time for receiving one symbol by beam switching based on the number of beams included in the first beam set.

US Pat. No. 10,171,151

THROUGHPUT OPTIMIZATION BY GUARD INTERVAL SELECTION FROM BEAMFORMING FEEDBACK

QUALCOMM Incorporated, S...

1. An apparatus for wireless communication, comprising:a processor;
memory in electronic communication with the processor; and
instructions stored in the memory and operable, when executed by the processor, to cause the apparatus to:
obtain compressed beamforming (CBF) information from one or more stations (STAs) as part of a sounding procedure, the CBF information comprising signal-to-noise ratio (SNR) information for a channel;
obtain, based at least in part on the compressed beamforming information, an indication of frequency variation within a per-tone SNR information using a fast Fourier transform (FFT) of the per-tone SNR information;
determine a delay spread based on the indication of frequency variation within the per-tone SNR information;
determine a guard interval (GI) based at least in part on the determined delay spread; and
transmit a plurality of orthogonal frequency-division multiplexing (OFDM) symbols utilizing the determined GI.

US Pat. No. 10,171,150

DYNAMIC OPTIMIZATION OF BEAMFORMING WEIGHTS

Sprint Communications Com...

1. A method of dynamic beamforming based on detected parameters, the method comprising:receiving, from a first user device, a first set of communication parameters associated with communication between a first antenna array associated with a base station and the first user device, wherein the first set of communication parameters comprises user device location data and at least one of channel quality index (CQI), channel load, band load, and signal-to-noise ratio (SINR);
receiving, from a second user device, a second set of communication parameters associated with communication between the first antenna array and the second user device;
analyzing the first set of communication parameters and the second set of communication parameters;
based on the analyzing, determining how to modify at least one component of a first set of beamforming weights to produce a second set of beamforming weights used to modify a beam emitted by a second antenna array associated with the base station;
dynamically applying the second set of beamforming weights to the second antenna array; and
in response to the dynamic application, transferring communication between the second device and the first antenna array to the second antenna array.

US Pat. No. 10,171,149

APPARATUS, SYSTEM AND METHOD OF WIRELESS BACKHAUL AND ACCESS COMMUNICATION VIA A COMMON ANTENNA ARRAY

INTEL CORPORATION, Santa...

1. A wireless communication apparatus comprising:a memory; and
a beamforming processor component to process Multi-User (MU) Multi-Input-Multi-Output (MIMO) communications via an antenna array of a wireless communication node, the beamforming processor component to cause one or more first sub-arrays of the antenna array to form one or more first directional beams to allow communications on one or more backhaul links between the wireless communication node and one or more other wireless communication nodes, and to cause one or more second sub-arrays of the antenna array to form one or more second directional beams to allow communications on one or more access links between the wireless communication node and one or more User Equipment (UEs);
a backhaul processor component to process the communications on said one or more backhaul links; and
an access processor component to process the communications on said one or more access links.

US Pat. No. 10,171,148

WIRELESS COMMUNICATION DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A wireless communication device comprising:a transmitter configured to multiplex and transmit a plurality of first frames;
a receiver configured to receive a plurality of second frames that represent acknowledgement responses to the plurality of first frames and are multiplexed and transmitted; and
controlling circuitry, wherein
first information necessary for transmission of the plurality of second frames is set in the plurality of first frames, and
the controlling circuitry is configured to separate the plurality of second frames based on the first information, wherein
the plurality of second frames are transmitted in spatial multiplexing,
the first information is information necessary to separate the plurality of second frames transmitted in the spatial multiplexing, and
the first information contains information specifying preamble patterns to be disposed in the plurality of second frames.

US Pat. No. 10,171,147

METHOD FOR TRANSMITTING SIGNAL IN MULTIPLE-ANTENNA WIRELESS COMMUNICATION SYSTEM AND APPARATUS FOR SAME

LG ELECTRONICS INC., Seo...

1. A method of transmitting a signal, the method performed by a first base station (BS) supporting a plurality of vertical beam directions in a wireless communication system that supports multiple antennas and comprising:configuring a group of a plurality of BSs including the first BS for a user equipment (UE) at a location higher than locations of the plurality of BSs;
setting a sector for supporting coverage of the group;
determining whether to perform beamforming on the set sector for the UE;
transmitting information to other of the plurality of BSs included in the group, the information indicating that the first BS will perform beamforming for the UE when it is determined to perform the beamforming for the UE; and
transmitting the signal through the BS transmitting the information to other BSs of the plurality of BSs to the UE in an upward beam direction of the plurality of BSs.

US Pat. No. 10,171,146

MIMO RANK REDUCTION TO IMPROVE DOWNLINK THROUGHPUT

Telefonaktiebolaget L M E...

13. A device adapted to:determine at least one of that an imbalance between a plurality of parallel channels of a spatial multiplexing downlink transmission to a wireless device based on a plurality of measurements where each measurement is indicative of a signal quality for a corresponding one of the parallel channels is greater than an imbalance threshold and that a Negative Acknowledgement (NACK) rate over time for the plurality of parallel channels of a spatial multiplexing downlink transmission reported by the wireless device is greater than a NACK rate threshold; and
in response to determining at least one of that the imbalance between the plurality of parallel channels is greater than the imbalance threshold and that the NACK rate is greater than the NACK rate threshold, perform a rank reduction for the next downlink transmission whereby a rank is reduced from a rank indicator reported by the wireless device to some lower rank.

US Pat. No. 10,171,145

CODEBOOK CONFIGURATION METHOD AND USER EQUIPMENT

Huawei Technologies Co. L...

1. A codebook configuration method, comprising:receiving, by a user equipment (UE), a reference signal that is of an antenna whose quantity of antenna ports is X and that is sent by a base station and configuration information of a codebook subset restriction for the quantity X of antenna ports, wherein the configuration information of the codebook subset restriction for the quantity X of antenna ports comprises first configuration information and second configuration information, and X is a positive integer greater than or equal to 2;
determining, by the UE according to the configuration information of the codebook subset restriction for the quantity X of antenna ports, a precoding matrix on which channel measurement and feedback need to be performed, wherein the codebook subset restriction for the quantity X of antenna ports is used to instruct the UE to select some precoding matrices from all precoding matrices in a codebook whose quantity of antenna ports is X for measurement and feedback; and
obtaining, by the UE via measurement according to the reference signal of the antenna whose quantity of antenna ports is X, the precoding matrix on which channel measurement and feedback need to be performed.

US Pat. No. 10,171,144

LOW COMPLEXITY HIGH PERFORMANCE SINGLE CODEWORD MIMO FOR 5G WIRELESS COMMUNICATION SYSTEMS

1. A transmitter device, comprising:a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
determining a rank associated with a first transmission via a control channel to a receiver device;
determining a first number of codewords to be used to transmit control channel information for the first transmission based on the rank; and
scheduling a second number of control channel grants to transmit the first number of codewords, wherein respective codewords of the first number of codewords are scheduled separately on respective control channel grants of the second number of control channel grants, and wherein a control channel grant of the second number of control channel grants comprises information relating to an antenna port corresponding to the control channel grant.

US Pat. No. 10,171,143

MICROWAVE RADIO TRANSMITTER AND RECEIVER FOR POLARIZATION MISALIGNMENT COMPENSATION

Telefonaktiebolaget LM Er...

1. A microwave radio transmitter for radio transmission to a microwave radio receiver, the microwave radio transmitter comprising:an antenna arrangement comprising an antenna having a polarization;
a baseband processing circuitry connected to the antenna arrangement, the baseband processing circuitry being configured to:
receive a polarization misalignment indication from the microwave radio receiver, the polarization misalignment indication being indicative of a misalignment between the polarization of the antenna and a corresponding polarization of a receive antenna comprised in the microwave radio receiver; and
compensate for polarization misalignment between the antenna and the receive antenna by adjusting the radio transmission based on the polarization misalignment indication.

US Pat. No. 10,171,142

DATA TRANSMISSION METHOD, APPARATUS, AND DEVICE

Huawei Technologies Co., ...

1. A data transmission method, wherein the method comprises:determining, by a transmit end device, a signature matrix S according to a quantity L of layers of a data stream and a quantity R of receive antennas used by a receive end device, wherein the signature matrix S comprises L first element sequences arranged in a first dimensional direction, the L first element sequences are in one-to-one correspondence with the L layers of the data stream, each first element sequence of the L first element sequences comprises R first elements arranged in a second dimensional direction, the R first elements are in one-to-one correspondence with the R receive antennas, the R first elements comprise at least one zero element and at least one non-zero element, R?2, the L first element sequences are different from each other, the L layers of the data stream correspond to a same time-frequency resource, and L?2;
determining, by the transmit end device, a precoding matrix P according to a channel matrix H and the signature matrix S, and performing precoding processing on the L-layer data stream according to the precoding matrix P, wherein the channel matrix H corresponds to channels between the transmit end device and the receive end device, the precoding matrix P comprises L second element sequences arranged in the first dimensional direction, the L second element sequences are in one-to-one correspondence with the L first element sequences, and the L second element sequences are in one-to-one correspondence with the L layers of the data stream; and
sending, by the transmit end device to the receive end device, the L-layer data stream on which the precoding processing has been performed and information used to indicate the signature matrix S.

US Pat. No. 10,171,141

HYBRID BEAM-FORMING ANTENNA ARRAY USING SELECTION MATRIX FOR ANTENNA PHASE CALIBRATION

ROSS SCIENCES LIMITED, H...

1. A hybrid beam-forming antenna array used in a multi-user massive multi-input multi-output (MU-MIMO) communication system, comprising:a single digital beam-former connected to M number of passive beam-former sub-arrays, wherein M is an integer equal to or greater than 1;
the M number of passive beam-former sub-arrays, each of the passive beam-former sub-arrays comprising:
a radio frequency (RF) transceiver having an output connected to an input of a single RF chain;
a 2N-inputs-2N-outputs selection matrix having all its inputs connected to the single RF chain output; and
2N number of antennas, each connected to and fed by one of the outputs of the selection matrix, wherein N is an integer equal to or greater than 0;
wherein the single digital beam-former output is connected to and feeding the RF transceiver of the passive beam-former sub-arrays; and
wherein the selection matrix has no power-consuming element and no external control, and configured to be fed with an RF signal at one or more of its 2N number of inputs and produce 2N number of separate RF signal beams with progressive phase distribution at its 2N number of outputs; and
wherein hybrid beam-forming antenna array has no antenna calibration network.

US Pat. No. 10,171,140

MU-MIMO GROUP SELECTION

Hewlett Packard Enterpris...

1. A communications device, comprising:communications circuitry to wirelessly communicate with a number of client devices using multiple possible bandwidth settings; and
control circuitry to determine signal-to-interference-plus-noise ratios (SINRs) for the client devices based on compressed client-side channel state information received from the client devices, and to select a set of multi-user-multiple-input-multiple-output (MU-MIMO) groups and bandwidth settings respectively assigned thereto, by:
estimating, based on the SINRs, bandwidth-specific throughputs for potential MU-MIMO groups at a specified bandwidth setting from among the multiple-possible bandwidth settings, and
selecting the set of MU-MIMO groups together with their respectively assigned bandwidth settings based on the bandwidth-specific throughputs.

US Pat. No. 10,171,138

INDICATING OPTIONAL PARAMETER GROUPS

NOKIA TECHNOLOGIES OY, E...

1. A method, comprising:determining optional configurations for parameters that override or supplement a default configuration of the parameters, wherein the optional configurations are grouped into optional parameter groups;
determining a number of the optional parameter groups to be encoded so as to not exceed a container size of a physical broadcast channel;
encoding the optional parameter groups in a system information block; and
transmitting the system information block from a network node to a user equipment.

US Pat. No. 10,171,137

METHOD AND DEVICE FOR TRANSMITTING DATA BY USING SPATIAL MODULATION SCHEME IN WIRELESS ACCESS SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for transmitting data signals from a transmitter by using a spatial modulation (SM) scheme in a wireless access system, the method performed an enhanced Node-B (eNB) and comprising:selecting two or more transmitting antennas for transmitting the data signals by using two or more ranks;
deriving data bit streams by applying the SM scheme,
wherein the data bit streams correspond to the two or more ranks;
configuring the data signals by using the SM scheme on the basis of the data bit streams;
transmitting, to a user equipment (UE), an enhanced physical downlink control channel (E-PDCCH) and demodulation reference signals (DM-RSs) through one of the two or more transmitting antennas, the E-PDCCH including rank information indicating a number of rank used for transmitting the data signals; and
transmitting, to the UE, the configured data signals through the selected two or more transmitting antennas and DM-RSs matched with each of the selected two or more transmission antennas,
wherein each of the two or more transmission antennas uses different predetermined DM-RSs from each other,
wherein combinations of the rank information and the DM-RSs identify each of the two or more transmission antennas,
wherein, if the E-PDCCH is transmitted through a first transmission antenna of the two or more transmission antennas, this represents a positive acknowledgment (ACK) for uplink data transmitted from the UE, and
wherein, if the E-PDCCH is transmitted through a second transmission antenna of the two or more transmission antennas, this represents a negative acknowledgement (NACK) for the uplink data transmitted from the UE.

US Pat. No. 10,171,136

REDUCING INTERNAL SIGNALING BURDEN IN THE DISTRIBUTED ANTENNA SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for a user equipment (UE) to receive signals from a network, the method comprising:receiving a first information unit from the network by a first distributed unit (DU) among multiple DUs distributed within the UE;
reporting, by the first DU, reception information of the first information unit to a central unit (CU) of the UE before decoding the received first information unit, wherein the CU controls the multiple DUs;
receiving, at the first DU from the CU, a direction indicating whether the first DU is to decode the received first information unit or not, and indicating whether the first DU is to transfer the received first information unit to the CU or another DU within the UE,
wherein the CU sends the direction based on the reception information of the first received information unit; and
decoding and transferring, by the first DU, the received first information unit to the CU and the another DU within the UE when the direction indicates a specific value,
wherein the CU sends the direction with an indication that the first DU is to transfer the first information unit.

US Pat. No. 10,171,135

PRECODING METHOD, APPARATUS, AND SYSTEM

HUAWEI TECHNOLOGIES CO., ...

1. A precoding method for a level 1 data center comprising:obtaining, by the level 1 data, center, a channel information signal between a terminal and the level 1 data center, wherein the channel information signal comprises a channel matrix;
encoding, by the level 1 data center, the channel matrix according to a precoding matrix to obtain an equivalent channel;
sending, by the level 1 data center, the equivalent channel to a level 2 data center for further processing when a frequency selectivity of the equivalent channel is less than or equal to a frequency selectivity of the channel; and
sending, by the level 1 data center, the channel matrix and the precoding matrix to the level 2 data center for further processing when the frequency selectivity of the equivalent channel is greater than the frequency selectivity of the channel.

US Pat. No. 10,171,134

ELECTRIC DEVICE AND OPERATION METHOD

Canon Kabushiki Kaisha, ...

1. An electric device for performing short distance wireless communication with a mobile terminal, comprising:an antenna configured to generate induced power by an RF signal from the mobile terminal;
a resistor configured to drop a peak voltage generated by the induced power;
a circuit driven by the voltage dropped by the resistor and configured to perform the short distance wireless communication; and
a light emission element driven by the voltage dropped by the resistor and configured to emit light, wherein
the resistor is series-connected between the circuit and the antenna.

US Pat. No. 10,171,132

CURRENT-MODE RECEIVERS FOR INDUCTION-BASED COMMUNICATION AND RELATED METHODS

MEDIATEK Singapore Pte. L...

1. A method comprising:generating a current with a transmitter of an integrated circuit (IC) and coupling the current to an inductor via an input/output (I/O) terminal of the IC; and
sensing information received at the IC through the inductor by sensing a variation in impedance seen at the I/O terminal, wherein sensing the variation in impedance comprises:
sensing the current coupled to the inductor;
converting the sensed current into a voltage; and
sensing a variation in the voltage with a receiver.

US Pat. No. 10,171,131

ELECTRONIC TUNING SYSTEM

William Redman-White, Al...

1. A circuit configured to control a resonant frequency of a tuned circuit so as to correspond with an applied excitation frequency over a continuous range of excitation frequencies, the tuned circuit comprising: an inductor; at least two capacitors; and at least one switch connected in combination with one of the at least two capacitors, wherein an apparent resonant frequency can be varied by controlling the duty cycle of an opening and closing of the at least one switch; and a source providing an excitation signal to the tuned circuit, the circuit configured to control the resonant frequency comprising:a voltage sensor configured to sense a voltage across two terminals of the at least one switch when the at least one switch is in an open state;
tuning control circuitry configured to derive a tuning control input signal from the sensed voltage; and
switch timing circuitry configured to control the timing of the opening and closing of the at least one switch in a manner based on the derived tuning control input signal, wherein the opening and closing instants of the said at least one switch are synchronous with the applied excitation signal and wherein the opening and closing instants of the said at least one switch are substantially equally spaced in time around a peak of a voltage at the connection between the inductor and the capacitors when the circuit is at resonance.

US Pat. No. 10,171,130

RECEIVER CIRCUIT

Power Integrations, Inc.,...

1. An analog receiver frontend, comprising:a first amplification circuit coupled to receive an input signal, wherein the first amplification stage is coupled to amplify a difference between the input signal and a threshold to generate the first signal;
a second amplification circuit coupled to receive the first signal from the first amplification circuit, wherein the second amplification circuit is coupled to amplify the first signal to generate a second signal;
an output circuit coupled to receive the second signal from the second amplification circuit, wherein the output circuit is coupled to output a recovered signal wherein the recovered signal is a pulse waveform of high and low sections; and
an input hysteresis circuit coupled to the output circuit to receive the recovered signal and generate a hysteresis signal, wherein one or both of the input signal and the threshold are level shifted by the hysteresis signal in response to the recovered signal.

US Pat. No. 10,171,129

PULSE SHAPING INTEROPERABILITY PROTOCOL FOR ULTRA WIDEBAND SYSTEMS

Apple Inc., Cupertino, C...

1. An electronic device comprising:a memory; and
one or more processors communicatively coupled to the memory and configured to:
receive pulse shape information from an other electronic device, wherein the pulse shape information is used in Ultra Wideband (UWB) communications between the electronic device and the other electronic device, and wherein the pulse shape information comprises a time-zero index that identifies a time instant reference to be used to process the UWB communications;
receive a ranging signal based at least in part on the pulse shape information; and
determine an estimated distance between the electronic device and the other electronic device based at least in part on the time-zero index and the ranging signal.

US Pat. No. 10,171,128

DATA TRANSMISSION METHOD AND APPARATUS

1. A data transmission method, comprising the following steps:determining a transmission resource to be used and a complex-valued spreading sequence to be used;
processing a data symbol to be sent by using the complex-valued spreading sequence to generate a symbol sequence; and
sending the symbol sequence through the transmission resource,
wherein each element of the complex-valued spreading sequence is a complex number, and values of a real part and an imaginary part of each element are both from an M-element real number set, wherein the M is an integer greater than or equal to 2, and the M-element real number set is selected from:
a set formed by M integers within a range of [?(M?1)/2, (M?1)/2], wherein the M is an odd number;
a set formed by M odd numbers within a range of [?(M?1), (M?1)], wherein the M is an even number;
a set formed by M real numbers obtained through multiplying respectively M integers within a range of [?(M?1)/2, (M?1)/2] by specified coefficient(s), wherein the M is an odd number; and
a set formed by M real numbers obtained through multiplying respectively M odd numbers within a range of [?(M?1), (M?1)] by specified coefficient(s), wherein the M is an even number.

US Pat. No. 10,171,127

METHOD, SYSTEM AND COMPUTER PROGRAM FOR SYNCHRONIZING PSEUDORANDOM BINARY SEQUENCE MODULES

1. A method for synchronizing a first pseudorandom binary sequence module of a receiver and a second pseudorandom binary sequence module of a transmitter, the method comprising:initializing the first pseudorandom binary sequence module with a first received bit sequence and performing bit sequence generation with the aid of the second pseudorandom binary sequence module;
comparing received remaining bits to bit sequences generated with the aid of the first pseudorandom binary sequence module to determine whether a bit error rate is below a predefined threshold;
accounting for phase ambiguities to check whether the bit error rate of each of a number of candidate phase positions for an initial phase is below the predefined threshold; and
in a case where there is no phase information available, testing each of a plurality of possible phase positions for the respective number of candidate phase positions.

US Pat. No. 10,171,126

APPARATUS FOR UPLINK MULTI-ANTENNA COMMUNICATION BASED ON A HYBRID COUPLER AND A TUNABLE PHASE SHIFTER

Intel IP Corporation, Sa...

1. Front end module (FEM) circuitry, comprising:a hybrid coupler to generate a first antenna transmit signal and a second antenna transmit signal based on hybrid coupler input signals; and
one or more tunable phase shifters to generate the hybrid coupler input signals based at least partly on an FEM input signal,
wherein the first antenna transmit signal is based on a first signal summation that comprises summation of a first hybrid coupler input signal and a second hybrid coupler input signal phase-shifted, by the hybrid coupler, according to a predetermined hybrid coupler phase shift, and
wherein the second antenna transmit signal is based on a second signal summation that comprises summation of the second hybrid coupler input signal and the first hybrid coupler input signal phase-shifted, by the hybrid coupler, according to the predetermined hybrid coupler phase shift.

US Pat. No. 10,171,125

TUNABLE ANTENNA SYSTEMS

Apple Inc., Cupertino, C...

1. An electronic device having a periphery, comprising:radio-frequency transceiver circuitry;
an antenna having an antenna feed and ground plane structures;
a transmission line path coupled between the radio-frequency transceiver circuitry and the antenna feed;
peripheral conductive housing structures that run along the periphery and surround the ground plane structures, wherein the peripheral conductive housing structures include a portion that forms at least part of the antenna;
storage and processing circuitry configured to generate a control signal; and
an adjustable electrical component coupled to the peripheral conductive housing structures, wherein the adjustable electrical component has a control input that receives the control signal and the adjustable electrical component is configured to adjust a frequency response of the antenna based on the control signal.

US Pat. No. 10,171,124

LOW NOISE AMPLIFIER ARBITER FOR LICENSE ASSISTED ACCESS SYSTEMS

Apple Inc., Cupertino, C...

1. An electronic device, comprising:a network interface configured to allow the electronic device to communicate over one or more channels of a wireless network;
a transceiver operably coupled to the network interface and configured to transmit data and to receive data over the one or more channels; and
a front end module (FEM) operably coupled to the transceiver and configured to receive licensed cellular signals and unlicensed cellular signals over the one or more channels, the FEM having an arbiter device configured to receive information related to the licensed cellular signals and the unlicensed cellular signals and to control at least one variable-gain amplifier and at least one gain adjustment device to independently amplify the licensed cellular signals and the unlicensed cellular signals.

US Pat. No. 10,171,123

TRIPLE-GATE PHEMT FOR MULTI-MODE MULTI-BAND SWITCH APPLICATIONS

SKYWORKS SOLUTIONS, INC.,...

1. A switch element comprising:a source including a plurality of source fingers and a drain including a plurality of drain fingers interleaved with the source fingers;
an active mesa region defined between at least one of the plurality of source fingers and an adjacent at least one of the plurality of drain fingers; and
a plurality of gates disposed between the at least one of the plurality of source fingers and the adjacent at least one of the plurality of drain fingers, at least one of the plurality of gates including a finger extending into the active mesa region from outside of the active mesa region and terminating within the active mesa region, the plurality of gates including a first gate, a second gate, and a third gate, a non-zero voltage difference across the source and the drain being evenly divided between the first gate, the second gate, and the third gate.

US Pat. No. 10,171,122

HAND STRAP FOR ELECTRONIC APPARATUS

Panasonic Intellectual Pr...

1. A charging adapter comprising:a hook which forms a seesaw structure having a first locker and a second locker at both ends , and a charging pin on an inner wall of the charging adapter;
wherein when the charging adapter is installed in an electronic apparatus, the first locker locks into a concave portion of the electronic apparatus, and
when the charging adapter is installed in a stand, a projection provided on the stand locks into the second locker and the projection continues to press the second locker, whereby the first locker is released.

US Pat. No. 10,171,121

RUGGEDIZED PROTECTIVE CASE WITH INTEGRATED EASEL KICKSTAND FOR MOBILE DEVICE

MobileDemand LC, Hiawath...

1. A ruggedized protective case for a mobile computing device, comprising:an inner housing configured to partially enclose a mobile computing device, the inner housing fashioned of a rigid material;
an outer housing configured to partially enclose the inner housing, the outer housing fashioned of a flexible material and including one or more reinforced corners, each reinforced corner configured to provide impact protection to a corner of the mobile computing device;
a kickstand consisting of a rigid core entirely overmolded with the flexible material, the kickstand having an inner end hingedly coupled to the inner housing and an outer end coupled to the kickstand at a first angle and configured to hold the mobile computing device at a second angle to a flat surface, the kickstand positionable at a third angle of at most 170 degrees to the inner housing.

US Pat. No. 10,171,120

APPARATUS AND METHOD FOR SUPPRESSING INTERMODULATION DISTORTION COMPONENT IN RECEPTION SIGNAL, AND COMMUNICATION APPARATUS

FUJITSU LIMITED, Kawasak...

1. An apparatus for suppressing an intermodulation distortion component in a reception signal, the apparatus comprising:a memory; and
processor circuitry coupled to the memory and configured to
execute acquisition to acquire a plurality of transmission signals transmitted at frequencies different from each other,
execute reception to receive a reception signal including an intermodulation distortion component caused by the plurality of transmission signals,
execute generation to generate a replica of the intermodulation distortion component according to the plurality of transmission signals,
execute normalization to normalize the reception signal so that the reception signal has certain amplitude,
execute calculation to calculate a correlation value between the normalized reception signal and the replica,
execute adjustment to adjust delay in the replica relative to the reception signal according to the correlation value, and
execute combination to combine the replica for which the delay is adjusted with the reception signal.

US Pat. No. 10,171,118

METHOD FOR TRANSMITTING REFERENCE SIGNAL IN CELL THAT USES UNLICENSED FREQUENCY BAND AND DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A method for transmitting a reference signal in a cell that uses an unlicensed frequency band, comprising:determining a candidate resource set that is used when a first reference signal is transmitted in the cell that uses the unlicensed frequency band, wherein the candidate resource set comprises a preset resource and at least one flexible candidate resource, wherein the preset resource is a resource that is in a time window and that is required, when the cell is in an active state, for transmission of the first reference signal according to a first period, and wherein the flexible candidate resource is a candidate resource that is in the time window and that is obtained after the preset resource is translated in terms of time, wherein a period in which the time window emerges is a second period, and the second period is greater than the first period;
determining a first candidate resource that is used when the first reference signal is transmitted in the cell that uses the unlicensed frequency band, wherein a channel on the unlicensed frequency band corresponding to the first candidate resource is in an idle state, and wherein the first candidate resource is one of the preset resource or a flexible candidate resource in the candidate resource set; and
sending the first reference signal on the first candidate resource.

US Pat. No. 10,171,117

METHODS AND APPARATUS TO MEASURE EXPOSURE TO BROADCAST SIGNALS HAVING EMBEDDED DATA

The Nielsen Company (US),...

1. A broadcast signal exposure meter comprising:a first decoder to obtain an identifier of a broadcast station from an audio signal output by an end user broadcast receiver;
a radio to tune to a broadcast signal from the broadcast station associated with the identifier of the broadcast station;
a second decoder to obtain embedded data from the broadcast signal, the embedded data representing media contained in the broadcast signal;
a location detector to determine location information; and
an interface to provide the embedded data and the location information to a server, the server to determine audience measurement information for the media based on the provided embedded data.

US Pat. No. 10,171,116

DATA TRANSMISSION METHOD AND DEVICE

SOOCHOW UNIVERSITY, Suzh...

1. A data transmission method, comprising:establishing, by a transmitting end, N different first paths between the transmitting end and a receiving end in an established network, wherein N is an integer greater than 1;
splitting, by the transmitting end, a fixed-length data frame into N first fragments, wherein each of the first fragments corresponds to a different one of the first paths, and a length of an i-th first fragment is L*P(i)/?i=1NP(i), wherein L is the length of the data frame, P(i) is a random number generated from a pre-set key by a pre-set algorithm, P(i) is greater than 0 and less than 1, and ?i=1NP(i)=1;
transmitting, by the transmitting end, the first fragments to the receiving end through the corresponding first paths respectively, wherein the receiving end combines the first fragments based on the pre-set algorithm;
splitting, by the transmitting end, the data frame into N-M second fragments in a case that a failure occurs in M of the first paths during transmission of the data frame, wherein M is an integer not less than 1 and not greater than N?1, a length of an i-th second segment is L*P?(i)/?i=1N-MP?(i), P?(i) is a random number generated from the pre-set key by the pre-set algorithm, P?(i) is greater than 0 and less than 1, and ?i=1N-MP?(i)=1;
establishing, by the transmitting end, N-M different second paths between the transmitting end and the receiving end, wherein each of the second fragments corresponds to a different one of the second paths; and
transmitting, by the transmitting end, the second fragments to the receiving end through the corresponding second paths respectively, wherein the receiving end combines the second fragments based on the pre-set algorithm.

US Pat. No. 10,171,115

OUTPHASING CALIBRATION IN A RADIO FREQUENCY (RF) TRANSMITTER DEVICE

Movandi Corporation, New...

1. An outphasing calibration method, comprising:in an outphasing radio frequency (RF) transmitter:
detecting, by a plurality of circuits, differences of a first plurality of signal characteristics of a first plurality of amplified RF signals across at least a transmitter antenna and a plurality of load impedances, wherein the first plurality of amplified RF signals corresponds to a first plurality of constant-envelope signals;
controlling, by the plurality of circuits, based on the detected differences of the first plurality of signal characteristics, at least a generation of a second plurality of constant-envelope signals and at least one signal characteristic of each of the second plurality of constant-envelope signals on a plurality of transmission paths; and
at least one of first calibrating, by the plurality of circuits, or second calibrating, by the plurality of circuits, a second plurality of signal characteristics of the second plurality of constant-envelope signals based on the controlled generation of the second plurality of constant-envelope signals and the at least one controlled signal characteristic of each of the second plurality of constant-envelope signals.

US Pat. No. 10,171,114

RADIO FREQUENCY SWITCH APPARATUS HAVING IMPROVED NOISE SUPPRESSION CHARACTERISTICS

Samsung Electro-Mechanics...

1. A radio frequency switch apparatus, comprising:a first switching circuit connected between an antenna terminal and a first signal terminal, comprising a first series switching circuit and a first shunt switching circuit configured to switch a first signal band on and off;
a second switching circuit connected between the antenna terminal and a second signal terminal, configured to switch a second signal band, different from the first signal band, on and off; and
an inductor circuit comprising a first inductor device connected between the first shunt switching circuit and a ground,
wherein the first inductor device suppresses noise, except for the first signal band and the second signal band, by being resonant with a capacitance present upon the first shunt switching circuit being turned off.

US Pat. No. 10,171,113

MULTIPLEXER, TRANSMISSION DEVICE, AND RECEPTION DEVICE

MURATA MANUFACTURING CO.,...

1. A multiplexer that transmits and receives high-frequency signals via an antenna element, the multiplexer comprising:a plurality of elastic wave filters with passbands different from each other;
a common terminal, with which at least one first circuit element is connected between a connection path of the common terminal and the antenna element, and a reference terminal, and at least one second circuit element is connected in series to the connection path; and
a first inductance element; wherein
one elastic wave filter of the plurality of elastic wave filters includes:
a series resonator connected between an input terminal and an output terminal; and
a parallel resonator connected between a connection path connecting the input terminal and the output terminal, and a reference terminal;
each of the plurality of elastic wave filters other than the one elastic wave filter includes a series resonator connected between an input terminal and an output terminal;
in the one elastic wave filter of the plurality of elastic wave filters, one of the input terminal and the output terminal of the one elastic wave filter, which is a terminal closer to the antenna element, is connected to the common terminal via the first inductance element that is connected to the terminal closer to the antenna element and the common terminal, and the terminal closer to the antenna element is connected to the parallel resonator; and
in each of the plurality of elastic wave filters other than the one elastic wave filter, one of the input terminal and the output terminal of the elastic wave filter, which is a terminal closer of to the antenna element, is connected to the common terminal, and is connected to the series resonator.

US Pat. No. 10,171,112

RF MULTIPLEXER WITH INTEGRATED DIRECTIONAL COUPLERS

QUALCOMM Incorporated, S...

1. A circuit comprising:an RF diplexer including a first channel and a second channel, wherein the first channel includes a first primary inductor and the second channel includes a second primary inductor;
a first directional coupler for the first channel including a first transformer that includes the first primary inductor and a first secondary inductor, wherein a first terminal for the first secondary inductor is a coupled port for the first directional coupler and a second terminal for the first secondary inductor is an isolated port for the first directional coupler;
a second directional coupler for the second channel including a second transformer that includes the second primary inductor and a second secondary inductor, wherein a first terminal for the second secondary inductor is a coupled port for the second directional coupler and a second terminal for the second secondary inductor is an isolated port for the second directional coupler;
an input port for the first channel coupled to a first terminal for the first primary inductor;
a first capacitor coupled between a second terminal for the first primary inductor and the second terminal for the first secondary inductor;
a second capacitor coupled between the input port for the first channel and ground;
a third capacitor coupled in parallel with the first primary inductor;
a first antenna;
a first inductor coupled between the second terminal of the first secondary inductor and the first antenna; and
a fourth capacitor coupled between the second terminal of the first secondary inductor and ground.

US Pat. No. 10,171,111

GENERATING ADDITIONAL SLICES BASED ON DATA ACCESS FREQUENCY

INTERNATIONAL BUSINESS MA...

1. A method for execution by a computing device of a dispersed storage network (DSN), the method comprises:determining whether a frequency of access via the DSN from one or more other computing devices to a set of encoded data slices that is stored in a set of storage units of the DSN exceeds a frequently accessed threshold, wherein a data segment of a data object is dispersed storage error encoded in accordance with first dispersed error encoding parameters including a first encoding matrix to produce the set of encoded data slices that is stored in the set of storage units of the DSN, wherein the set of encoded data slices includes a pillar width number and a decode threshold number, wherein the pillar width number corresponds to number of encoded data slices in the set of encoded data slices, and wherein the decode threshold number corresponds to a number of encoded data slices of the set of encoded data slices to retrieve a corresponding data segment of the data object;
when the frequency of access via the DSN from the one or more other computing devices to the set of encoded data slices that is stored in the set of storage units of the DSN exceeds the frequently accessed threshold, determining an access amount indicative of a degree in which the frequency of access exceeds the frequently accessed threshold;
generating a number of additional encoded data slices for the set of encoded data slices based on the access amount in accordance with second dispersed error encoding parameters including a second encoding matrix that includes at least one of more rows or more columns than the first encoding matrix;
storing the number of additional encoded data slices in a number of additional storage units within the DSN, wherein the set of storage units and the number of additional storage units produce an expanded set of storage units within the DSN that includes more storage units than the set of storage units; and
sending, via the DSN from at least one of the computing device or the one or more other computing devices, a plurality of data access requests for the set of encoded data slices to different respective subsets of the expanded set of storage units in a distributed manner to load balance the plurality of data access requests for the set of encoded data slices among the expanded set of storage units within the DSN, wherein, over time, each storage unit of the expanded set of storage units within the DSN receives approximately an equal number of the plurality of data access requests and less than all of the plurality of data access requests.

US Pat. No. 10,171,110

SEQUENTIAL POWER TRANSITIONING OF MULTIPLE DATA DECODERS

Seagate Technology LLC, ...

1. An apparatus comprising:a non-volatile memory (NVM) configured to store data in the form of code words, each code word comprising a user data payload and associated code bits;
a plurality of data decoder circuits each configured to use the code bits to detect and correct bit errors in the code words during a read operation; and
a power transition circuit configured to transition each of the data decoder circuits from a first power mode to a different, second power mode in accordance with a time varying profile in which each data decoder circuit is transitioned at a different time and at a conclusion of a predetermined time interval.

US Pat. No. 10,171,109

FAST ENCODING METHOD AND DEVICE FOR REED-SOLOMON CODES WITH A SMALL NUMBER OF REDUNDANCIES

Hefei High-Dimensional Da...

1. A fast encoding method for Reed-Solomon codes with a small number of redundancies, the method comprising:a step of setting parity-check matrices comprising:
presetting parity-check matrices H2 and H3; wherein the number of redundant symbols s in the Reed-Solomon codes is 2 or 3, and when s is 3, the preset parity-check matrix is:

when s is 2, the preset parity-check matrix is:

a step of constructing shortened Reed-Solomon codes comprising:
constructing (k, s) Reed-Solomon codes over a finite field GF(2m) that conform to the preset parity-check matrix; using k points {oi}i=1k in R-points input {oi}i=0R?1 as message symbols, and setting the remaining points to zero; setting the remaining points of the R points to zero, that is, o0=0 and ok+1=. . . =oR?1=0;
wherein m denotes the number of binary bits for each symbol, R=2r, r=? log2(k+1)?, k denotes the number of message symbols, s denotes the number of redundant symbols, i=0,1 , . . . , R?1, and oi denotes the message symbol;
a step of encoding comprising:
calculating s redundant symbols according to the R-points input and the base vector of the finite field, to achieve the encoding of Reed-Solomon codes with a small number of redundancies.

US Pat. No. 10,171,108

PARALLEL CRC CALCULATION FOR MULTIPLE PACKETS WITHOUT REQUIRING A SHIFTER

ALTERA CORPORATION, San ...

1. A programmable integrated circuit device for parallel calculation of cyclic redundancy check (“CRC”) values for a plurality of packets received in a clock cycle, the programmable integrated circuit device comprising:a padding bit-replacement block configured to:
receive a stream comprising the plurality of packets, wherein the plurality of packets have N packets;
generate N copies of the stream, wherein each copy of the stream is associated with a respective packet of the plurality of packets; and
for each respective copy of the N copies of the stream, replace with padding bits all packets but the respective packet associated with the respective copy to create a respective padded copy of a plurality of padded copies;
a CRC calculation block configured to:
receive the plurality of padded copies; and
calculate a packet CRC value for each packet of the plurality of packets to form a plurality of packet CRC values by calculating a respective CRC value for each respective padded copy of the plurality of padded copies; and
a matrix reverse block configured to iteratively merge each padded copy of the plurality of padded copies by removing the padding bits from each padded copy of the plurality of padded copies to produce a reformed stream.

US Pat. No. 10,171,107

GROUPS OF PHASE INVARIANT CODEWORDS

Hewlett-Packard Developme...

1. A system comprising:a lookup table (LUT) to store in a non-transitory computer readable medium (CRM) associations between phase invariant codewords and bit strings in which each phase invariant codeword belongs to a group of codewords having a particular property, wherein the particular property is a range of values defining a number of active bits in the phase invariant codeword, each bit string having a first length; and
an encoder which upon execution instructs at least one processor coupled to the CRM to:
read a message comprising a bit string of a second length longer than the first length;
divide the message into a plurality of substrings from the LUT such that each substring is of the first length; and
encode in a halftone image, on a data bearing medium, a composite codeword comprising each phase invariant codeword associated in the LUT with a substring from the message;
wherein less storage in the CRM is needed for messages of a given bit size than encoding schemes implemented in the CRM with a simple table including all non-composite phase invariant codewords packed in order.

US Pat. No. 10,171,106

SYSTEMS AND METHODS FOR MULTI-STAGE DATA SERIALIZATION IN A MEMORY SYSTEM

Micron Technology, Inc., ...

1. A memory system, comprising:a memory device configured to provide a set of data in parallel;
a memory controller configured to coordinate data transmission of a memory device;
multi-stage serializer circuitry configured to receive the set of data in parallel and provide, to the memory controller, the data serially as a serialized data burst;
wherein the multi-stage serializer circuit comprises a set of two or more double data rate (DDR) shift registers; and
wherein each of the two or more DDR shift registers comprises at least two single data rate (SDR) shift registers, wherein each of the at least two SDR shift registers comprises a series of data flip flops configured to load an error data control (EDC) hold pattern in parallel.

US Pat. No. 10,171,105

CARRY-LESS POPULATION COUNT

INTERNATIONAL BUSINESS MA...

1. A population count circuit that determines a population count of an n-bit input bit-string, wherein:the population count circuit is configured to output the population count, wherein the population count is a number of 1s in the n-bit input bit-string; and
the population count circuit comprises:
a carryless counter circuit configured to determine a pair of 3-bit counts of 1 s, one for each 4-bit nibble from a pair of 4-bit nibbles from an n-bit input bit-string input to the population count circuit; and
an adder circuit configured to determine the population count by summing the pair of 3-bit counts of 1s from the carryless counter circuit corresponding to each 4-bit nibble, the adder circuit comprising a plurality of adders that perform the summing without propagating a carry bit that results from a most significant bit (MSB) of a sum of the pair of 3-bit counts of 1s being added, the plurality of adders setup as a sequential tree to propagate the 3-bit counts, where the tree comprises log2(n/4) levels, and wherein:
at level k of the tree, k being 2 to log 2(n/4), the 3-bit counts from a level k?1 of the tree in consecutive pairs are used by a first adder to determine the MSB of the sum based on the MSBs of the 3-bit counts only, without depending on carry propagation;
at level k of the tree, results from the level k?1 of the tree are added by a second adder for sum bits other than the MSB; and
result of additions at level log 2(n/4) of the tree is output as the population count of the n-bit input bit-string.

US Pat. No. 10,171,104

ENCODING VARIABLE LENGTH INTEGERS FOR GRAPH COMPRESSION

INTERNATIONAL BUSINESS MA...

1. A graph compression system comprising:a memory unit configured to store graph data; and
an electronic hardware controller in signal communication with the memory unit, the electronic hardware controller configured to determine a distribution of a set of vertices in a graph, and to encode each vertex included in the set of vertices as a variable length integer (VLI) that includes a variable number of bytes,
wherein the variable number of bytes of each vertex is based on the determined distribution, and
wherein the memory unit stores each encoded vertex.

US Pat. No. 10,171,103

HARDWARE DATA COMPRESSION ARCHITECTURE INCLUDING SHIFT REGISTER AND METHOD THEREOF

Mellanox Technologies, Lt...

1. A hardware compression architecture, comprising:a shift register including a plurality of sequentially coupled stages and a window stage coupled at an output end of the shift register, the shift register configured to receive an uncompressed data stream at an input end and output the uncompressed data from the window stage;
a plurality of comparators each coupled to receive a data value held in a corresponding stage of the shift register and a data value held in the window stage, each of the comparators being configured to output a comparison result indicating whether the received stage value and the window stage data value match;
logic, coupled to the comparators to receive the comparison results, to selectively compute one or more indexes based on the comparisons; and
an encoder coupled to receive the one or more indexes and output, based on the one or more indexes, a position of a matching data value and a length of a matching sequence of data values.

US Pat. No. 10,171,102

OVERSAMPLED CONTINUOUS-TIME PIPELINE ADC WITH VOLTAGE-MODE SUMMATION

Analog Devices Global Unl...

1. A stage in a multi-stage analog-to-digital converter, comprising:a voltage-output digital-to-analog converter (DAC) to generate a reconstructed voltage input signal from a digital input signal provided by an analog-to-digital converter (ADC) digitizing an input signal to the stage;
a resistor in series with an output of the voltage-output DAC; and
a summation node to sum a delayed voltage input signal and the reconstructed voltage input signal; and
a transconductor to sense a voltage signal at the summation node to generate an output signal of the stage.

US Pat. No. 10,171,101

MODULATORS

Cirrus Logic, Inc., Aust...

1. An analogue to digital converter comprising:a time-encoding modulator comprising:
a first controlled oscillator configured to receive a first oscillator driving signal and output a first oscillation signal;
an accumulator configured to provide an accumulator value based on a number of pulses of the first oscillation signal; and
a hysteretic comparator configured to output either a first output state or a second output state and to alternate between said first and second output states based on a hysteretic comparison of said accumulator value with a defined reference;
wherein the first oscillator driving signal is based on a combination of an input signal and a feedback signal derived from an output of the hysteretic comparator; and
at least one further controlled oscillator and a counter, wherein the at least one further controlled oscillator is driven by the output state of the hysteretic comparator and the counter is configured to generate a count value based on the number of pulses in an output of the at least one further controlled oscillator in a frame period defined a received clock signal.

US Pat. No. 10,171,100

CIRCUIT AND METHOD FOR GENERATING REFERENCE SIGNALS FOR HYBRID ANALOG-TO-DIGITAL CONVERTORS

STMICROELECTRONICS INTERN...

1. A circuit configured to generate a plurality of reference signals for an analog-to-digital convertor (ADC) comprising a first stage and a second stage, the circuit comprising:a first reference source comprising a first output terminal and a second output terminal coupled to respective terminals of the first stage of the ADC, the first reference source being configured to generate a first reference voltage between the first output terminal and the second output terminal of the first reference source, the first reference voltage being configured to be provided as a first reference signal to the first stage of the ADC, the first reference voltage comprising a first transient signal generated by the first stage of the ADC;
a filter coupled to the first output terminal and the second output terminal of the first reference source and configured to filter the first transient signal from the first reference signal to produce a filtered first reference signal; and
a second reference source having input terminals coupled to the filter, wherein the filter comprises at least one first capacitive element coupled between the input terminals of the second reference source, the second reference source comprising a first output terminal and a second output terminal coupled to respective terminals of the second stage of the ADC, the second reference source configured to generate a second reference signal between the first output terminal and the second output terminal of the second reference source based on the filtered first reference signal, the second reference signal being configured to be provided as a second reference signal to the second stage of the ADC.

US Pat. No. 10,171,099

TIME-BASED DELAY LINE ANALOG TO DIGITAL CONVERTER

MICROCHIP TECHNOLOGY INCO...

1. A differential digital delay line analog-to-digital converter (ADC), comprising:a plurality of differential digital delay lines;
a first circuit comprising a set of delay elements included in the differential digital delay lines; and
a second circuit comprising another set of delay elements included in the differential digital delay lines; wherein:
the first circuit is configured to generate data representing an analog to digital conversion of an input; and
the second circuit is configured to calibrate a source to the differential digital delay lines based on an out of input range determination.

US Pat. No. 10,171,098

ANALOG-TO-DIGITAL CONVERTER (ADC) WITH IMPROVED POWER DISTURBANCE REDUCTION

SK Hynix Inc., Gyeonggi-...

1. An analog-to-digital converter (ADC) for converting an input analog voltage to an output digital code, the ADC comprising:a first node of the input analog voltage;
nodes of a plurality of reference voltages;
a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage among the plurality of reference voltages;
a logic circuit block adapted to receive outputs of the plurality of comparators and generating the output digital code; and
a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages,
wherein the voltage stabilizer is configured to reduce a phase difference between a first disturb on the input analog voltage of the first node and a second disturb on the node of the first reference voltage.

US Pat. No. 10,171,097

CORRECTING DEVICE OF SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION

REALTEK SEMICONDUCTOR COR...

1. A correcting device of successive approximation analog-to-digital conversion, comprising:a successive approximation register analog-to-digital converter (SAR ADC) configured to generate a digital output; and
a digital circuit configured to determine whether the digital output conforms to a metastable output, and configured to correct the digital output according to predetermined correction when the digital output conforms to the metastable output,
wherein the metastable output is related with a metastable binary comparison-results sequence including successive K comparison results, the successive K comparison results include a first comparison result, a second comparison result and M comparison results in turn, the first comparison result and the second comparison result are identical, the M comparison results are identical, each of the first comparison result and the second comparison result is different from any of the M comparison results, and each of the K and the M is a positive integer.

US Pat. No. 10,171,096

PIPELINED SAR WITH TDC CONVERTER

Taiwan Semiconductor Manu...

12. An analog-to-digital converter (ADC), comprising:a voltage-based signal processing element configured to receive an input signal and to generate a first digital signal and a residue voltage;
a residue offset circuit configured to provide a residue offset voltage to the residue voltage;
a voltage-to-time conversion element configured to use the residue voltage and the residue offset voltage to generate a time domain representation of the residue voltage; and
a time-based signal processing element configured to convert the time domain representation to a second digital signal.

US Pat. No. 10,171,095

ATOMIC OSCILLATOR, ELECTRONIC APPARATUS, MOVING OBJECT, AND MANUFACTURING METHOD OF ATOMIC OSCILLATOR

Seiko Epson Corporation, ...

1. An atomic oscillator comprising:a cell which encapsulates metal atoms therein;
a light source which generates light for irradiation of the cell; and
a frequency modulation signal generator configured to generate a frequency modulation signal for causing the light source to generate the light, the light being frequency-modulated and including a resonance light pair, the resonance light pair causing an electromagnetically induced transparency phenomenon in the metal atoms,
wherein modulation indexes of the frequency modulation signal include a first modulation index, and
a first-order differential value of oscillation frequency deviation of the atomic oscillator is zero at the first modulation index.

US Pat. No. 10,171,094

HIGH ACCURACY CLOCK SYNCHRONIZATION CIRCUIT

SEIKO EPSON CORPORATION, ...

1. A circuit device comprising:a comparator that performs a comparison between an input signal based on an oscillation signal and a reference signal, the comparator including a counter that performs a count operation by using the input signal, and performs the comparison by comparing a count value in the counter in n (where n is an integer of 2 or more) cycles of the reference signal with an expected value of the count value in integers;
a processor that performs a signal process on frequency control data based on a result of the comparison; and
an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of the frequency control data having undergone the signal process.

US Pat. No. 10,171,093

SLEW RATE LOCKED LOOP

2. A slew rate locked loop circuit for controlling and maintaining a constant slew rate at an output of a buffer, wherein said buffer receives (i) a first input signal and (ii) at least one of a control voltage, said slew rate locked loop circuit comprising:a slew rate determining unit that comprises:
a first reference voltage generator that generates (i) an upper threshold voltage (Vh) and (ii) a lower threshold voltage (Vl);
a first comparator that compares said upper threshold voltage (Vh) with said output of said buffer to obtain a first output digital signal;
a second comparator, that compares said lower threshold voltage (Vl) with said output of said buffer to obtain a second output digital signal; and
a phase detector that determines a phase difference between said first output digital signal and said second output digital signal, wherein said phase difference is directly proportional to said slew rate at said output of said buffer;
a loop filter that produces a DC voltage from an output of said phase detector;
a second reference voltage generator that generates a reference voltage; and
an amplifier that (a) receives said DC voltage from said loop filter and said reference voltage generated by said second reference voltage generator, and (b) amplifies the difference between (i) said DC voltage from said loop filter and (ii) said reference voltage to obtain a control voltage, wherein said control voltage is fed back to said buffer, wherein said slew rate at said output of said buffer is determined using said control voltage.

US Pat. No. 10,171,092

TIME CLOCK SIGNAL PROCESSING SYSTEM AND METHOD THEREOF

LYRA SEMICONDUCTOR INCORP...

1. A clock signal processing method, applicable to an environment of audio clock reconstruction for universal serial bus (USB) audio synchronous mode, comprising the following steps:performing frequency increase: increasing the frequency of an inputted USB start-of-frame (SOF), and outputting a higher frequency clock signal, the frequency of the higher frequency clock signal being the increased frequency of the inputted USB SOF; and
performing timing jitter processing: receiving the higher frequency clock signal and reducing timing jitter on the higher frequency clock signal;
wherein in the step of performing frequency increase, a first-stage phase-locked loop (PLL) is used to increase the frequency of the inputted USB SOF to provide the higher frequency clock signal, and output the higher frequency clock signal to a second-stage PLL.

US Pat. No. 10,171,091

PHASE INTERPOLATOR FOR INTERPOLATING PHASE OF DELAY CLOCK SIGNAL AND DEVICE INCLUDING THE SAME AND FOR PERFORMING DATA SAMPLING BY USING PHASE INTERPOLATED CLOCK SIGNAL

SAMSUNG ELECTRONICS CO., ...

1. A phase interpolator comprising:a control circuit configured to generate a selection control signal that corresponds to a selected coarse phase interval, and generate a weight setting signal for generating a phase interpolation clock signal with an interpolated phase within the coarse phase interval;
a phase selector configured to receive a plurality of inversion delay clock signal pairs, select at least two inversion delay clock signal pairs from the plurality of inversion delay clock signal pairs based on the selection control signal, select and output a selection delay clock signal pair corresponding to the coarse phase interval from the selected at least two inversion delay clock signal pairs; and
a phase mixer configured to receive the selection delay clock signal pair from the phase selector and generate the phase interpolation clock signal based on the weight setting signal.

US Pat. No. 10,171,090

OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT

SEIKO EPSON CORPORATION, ...

1. An oscillator comprising:a vibrator element;
a container in which the vibrator element is housed;
a base substrate on which the container is mounted via one or more supporting bodies;
at least one of a heating element and a cooling body configured to control temperature on an inside of the container;
an oscillation circuit electrically connected to the vibrator element;
a D/A conversion circuit configured to control a frequency output by the oscillation circuit;
a first reference-voltage generation circuit configured to supply voltage to the D/A conversion circuit; and
a second reference-voltage generation circuit configured to generate, on the basis of a power supply voltage supplied from outside of the oscillator, a power supply voltage of the oscillation circuit, wherein
temperature of the first reference-voltage generation circuit is controlled by the at least one of the heating element and the cooling body, and
the container is elevated and separated from the base substrate by being supported by the one or more supporting bodies.

US Pat. No. 10,171,089

PVT-FREE CALIBRATION FUNCTION USING A DOUBLER CIRCUIT FOR TDC RESOLUTION IN ADPLL APPLICATIONS

Taiwan Semiconductor Manu...

1. A circuit, comprising:a time-to-digital converter (TDC) configured to generate a phase variation signal indicative of a phase difference between a first signal and a reference signal; and
a doubler electrically coupled to the TDC, wherein the doubler is configured to receive a first voltage signal and generate a second voltage signal, wherein the second voltage signal is provided to a voltage input of the TDC, and wherein the TDC generates one or more control signals configured to adjust the second voltage signal, wherein the doubler comprises:
a first ring oscillator;
a first flip-flop electrically coupled to the first ring oscillator; and
a first clock generator electrically coupled to an output of the first flip-flop.

US Pat. No. 10,171,088

QUANTUM CIRCUIT FOR SHIFTING PHASE OF TARGET QUBIT BASED ON CONTROL QUBIT

ELECTRONICS AND TELECOMMU...

1. A quantum circuit that shifts a phase of a target qubit by ?/2n?1 based on a control qubit, the quantum circuit comprising:a first auxiliary circuit configured to convert a first qubit state according to an entanglement of the control qubit, the target qubit, and an ancillary qubit having a |0> state to a second qubit state;
a rotation gate configured to shift a phase for at least one basis state of the second qubit state by ?/2n?1 to convert the second qubit state to a third qubit state; and
a second auxiliary circuit configured to convert the third qubit state to a fourth qubit state so as to shift the phase of the target qubit by ?/2n?1,
wherein the first auxiliary circuit determines a |111> basis state of the second qubit state based on a |110> basis state of the first qubit state, and the second auxiliary circuit determines a |110> basis state of the fourth qubit state based on a |111> basis state of the third qubit state.

US Pat. No. 10,171,087

LARGE FAN-IN RQL GATES

Northrop Grumman Systems ...

1. A reciprocal quantum logic (RQL) gate circuit comprising:an input stage having more than two logical inputs each configured to be asserted based on receiving a positive single flux quantum (SFQ) pulse, the input stage comprising, for each logical input, at least one storage loop associated with the logical input, each storage loop comprising at least one input Josephson junction (JJ), at least one inductor, and a logical decision JJ, the logical decision JJ being common to all the storage loops associated with the logical inputs; and
an output stage configured to assert an output based on a triggering of the logical decision JJ in response to a combination of logical inputs.

US Pat. No. 10,171,086

SUPERCONDUCTING THREE-TERMINAL DEVICE AND LOGIC GATES

Massachusetts Institute o...

1. A three-terminal device comprising:a main channel connecting a first terminal and a second terminal;
a gate channel connecting a control terminal to the main channel; and
a low-resistance constriction formed in the gate channel between the control terminal and the main channel, wherein the constriction is configured to increase a gate current density proximal to the main channel and the constriction is located within approximately 200 nm of an edge of the main channel.

US Pat. No. 10,171,085

NOISE-IMMUNE REFERENCE (NREF) INTEGRATED IN A PROGRAMMABLE LOGIC DEVICE

AnDAPT, Inc., San Jose, ...

1. A reference voltage block comprising:an accumulator configured to receive a digital reference value and generate a carry out signal;
a low-pass filter configured to receive the carry out signal from the accumulator and generate a filtered signal; and
an analog gain amplifier configured to amplify the filtered signal using a gain selected from a predetermined set of gains and generate a reference voltage output signal,
wherein the reference voltage block is integrated in a programmable logic device (PLD) including a programmable fabric and a signal wrapper, and
wherein the digital reference value and the predetermined set of gains of the reference voltage block are programmable using the programmable fabric and fed to the reference voltage block via the signal wrapper.

US Pat. No. 10,171,084

SPARSE CODING WITH MEMRISTOR NETWORKS

The Regents of The Univer...

1. A system for sparse coding with an array of resistive memory devices, comprising:an array of resistive memory devices arranged in columns and rows to form a matrix, wherein each column represents a potential feature of an input;
an interface circuit electrically coupled to the matrix, wherein the interface circuit cooperatively operates with the array of resistive memory devices to perform computing in the array of resistive memory devices, wherein the interface circuit controls a computation of:
(a) a first dot product operation by feeding an input vector forward through the matrix to yield an output vector, where the input vector is a column vector with each element representing intensity of a pixel in an image and the output vector is row vector with each element representing the dot product between the input vector and a feature vector stored in a corresponding column of the matrix;
(b) a second dot product operation by feeding a neuron activity vector backward through the matrix to yield an intermediate result vector, where the neuron activity vector is a row vector representing a level of activity from all of the neurons in the matrix and the intermediate result vector is a column vector;
(c) a new input vector by subtracting the intermediate result vector from the input vector; and
(d) a third dot product operation by feeding the new input vector forward through the matrix to yield a new output vector, where the output vector is a row vector with each element representing the dot product between the input vector and the feature vector stored in the corresponding column of the matrix.

US Pat. No. 10,171,083

MEMRISTOR LOGIC DESIGN USING DRIVER CIRCUITRY

Board of Regents, The Uni...

1. A logic gate, comprising:a first memristor and a second memristor connected in series;
a switch, wherein a node of said second memristor is connected to said switch;
a third memristor connected to said switch in series;
a first voltage source connected to said first memristor via a first resistor;
a second voltage source connected in series to said switch and third memristor;
a second resistor connected to said second memristor and ground; and
a third resistor connected to said third memristor and said ground.

US Pat. No. 10,171,082

DRIVING CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A driving circuit which drives a subsequent stage circuit depending on a set signal and a reset signal that are inputted, comprising:a set side level shift circuit which operates depending on the set signal, and generates a set potential,
a reset side level shift circuit which operates depending on the reset signal, and generates a reset potential, and
a control circuit which generates a control signal depending on the set potential and the reset potential, and drives the subsequent stage circuit, wherein
each of the set side level shift circuit and the reset side level shift circuit has
an input transistor which is provided between a high potential and a reference potential, operates depending on the set signal or the reset signal, and outputs a drain potential as the set potential or the reset potential, and
a serial transistor unit which includes a first MOS transistor and a second MOS transistor which are connected in series between a drain terminal of the input transistor and the high potential,
the first MOS transistors in the set side level shift circuit and the reset side level shift circuit complementarily operate to each other corresponding to a logical value of the control signal which the control circuit outputs,
the set side level shift circuit further has a set side buffer which compares a level of the set potential with a threshold value of the set side buffer depending on the high potential, and controls the second MOS transistor of the reset side level shift circuit based on a result of the comparison of the level of the set potential with the threshold value of the set side buffer,
the reset side level shift circuit further has a reset side buffer which compares a level of the reset potential with a threshold value of the reset side buffer depending on the high potential, and controls the second MOS transistor of the set side level shift circuit based on a result of the comparison of the level of the reset potential with the threshold value of the reset side buffer.

US Pat. No. 10,171,081

ON-CHIP SUPPLY NOISE VOLTAGE REDUCTION OR MITIGATION USING LOCAL DETECTION LOOPS IN A PROCESSOR CORE

INTERNATIONAL BUSINESS MA...

1. A device, comprising:a first voltage noise sensor located at a first unit of a processor core, wherein the first voltage noise sensor detects a first voltage droop at the first unit, and wherein the processor core is divided into the first unit and a second unit;
a global noise manager component located in the processor core and associated with a global control loop of the processor core, and that receives, from the first voltage noise sensor, an indication of the first voltage droop; and
a first local noise manager component located in the first unit and associated with a first local control loop of the first unit, where the first local noise manager component is distinct from the global noise manager component and:
receives, from the first voltage noise sensor, the indication of the first voltage droop; and
implements a first noise mitigation procedure at the first unit.

US Pat. No. 10,171,080

VOLTAGE LEVEL SHIFTER (VLS) CIRCUITS EMPLOYING A PRE-CONDITIONING CIRCUIT FOR PRE-CONDITIONING AN INPUT SIGNAL TO BE VOLTAGE LEVEL SHIFTED IN RESPONSE TO A PRE-CHARGE PHASE

QUALCOMM Incorporated, S...

1. A voltage level shifter (VLS) circuit, comprising:a pre-conditioning circuit configured to:
receive an input signal in a first voltage domain; and
generate a pre-conditioned input signal on an input node in the first voltage domain at a voltage level on an input node indicating a charge logic state, in response to a pre-condition control signal having a voltage level of the charge logic state indicating a pre-charge phase;
a pre-charge circuit coupled to an output node and a first supply rail of a supply voltage relative to a second supply rail in a second voltage domain higher than the first voltage domain, the pre-charge circuit configured to couple the first supply rail to the output node in response to a pre-charge control signal indicating the pre-charge phase;
a pull-up circuit coupled to the first supply rail and the output node, the pull-up circuit configured to couple the first supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the charge logic state; and
a pull-down circuit coupled to the input node and the second supply rail, the pull-down circuit configured to:
decouple the second supply rail from the output node in response to the pre-condition control signal indicating the pre-charge phase; and
couple the second supply rail to the output node in response to the pre-conditioned input signal having a voltage level of a discharge logic state in response to the pre-condition control signal having the voltage level of the discharge logic state indicating an evaluation phase.

US Pat. No. 10,171,079

METHODS AND APPARATUSES FOR DYNAMIC STEP SIZE FOR IMPEDANCE CALIBRATION OF A SEMICONDUCTOR DEVICE

Micron Technology, Inc., ...

1. An apparatus comprising:a resistor; and
a chip comprising a driver impedance calibration circuit configured to determine an impedance of a driver based on an impedance of the resistor, wherein, during a calibration operation, the driver impedance calibration circuit is configured to adjust an impedance code that controls an impedance of the driver and to provide a next impedance code based on a comparison of a driver output voltage with a reference voltage, wherein an adjustment step size of the impedance code is determined based on a value of the impedance code, wherein the driver impedance calibration circuit comprises an adder/subtractor circuit configured to adjust the impedance code based on a comparison of a driver output voltage with a reference voltage and wherein the adder/subtractor circuit is configured to adjust the impedance code by a value equal to a value of a subset of most significant bits of the impedance code.

US Pat. No. 10,171,078

NONVOLATILE MEMORY DEVICES WITH ON DIE TERMINATION CIRCUITS AND CONTROL METHODS THEREOF

Samsung Electronics Co., ...

1. A method of operating a nonvolatile memory device, comprising:receiving a write command via data input/output terminals in synchronization with a write enable signal while a command latch enable signal (CLE) is enabled;
receiving an address via the data input/output terminals in synchronization with the write enable signal while an address latch enable signal (ALE) is enabled, wherein after the receiving the write command and the address, the CLE and the ALE are disabled;
after the CLE and the ALE are disabled, activating an on-die termination mode of the data input/output terminals in response to an initial falling edge of a data strobe signal and before a rising edge of the data strobe signal, the rising edge of the data strobe signal following the initial falling edge of the data strobe signal;
receiving write data in synchronization with the data strobe signal; and
deactivating the on-die termination mode of the data input/output terminals in response to a transition of at least one of a chip enable signal, the ALE, and the CLE;
wherein the activating the on-die termination mode of the data input/output terminals includes activating a pseudo differential signaling mode of the data input/output terminals and activating a differential signaling mode of the data strobe signal.

US Pat. No. 10,171,077

SCALABLE QUBIT DRIVE AND READOUT

INTERNATIONAL BUSINESS MA...

1. A system for qubit drive and readout, the system comprising:a lossless microwave signal distributor connected to a quantum system, wherein a first input line is connectable to the lossless microwave signal distributor;
a lossless microwave switch connected to the quantum system, wherein a second input line is connectable to the lossless microwave switch, wherein the second input line is configured to drive the quantum system via the lossless microwave switch and the first input line is configured to read out the quantum system via the lossless microwave signal distributor;
a first circulator configured to connect the first input to the lossless microwave signal distributor and configured to connect a quantum-limited amplifier to the lossless microwave signal distributor.

US Pat. No. 10,171,076

INDEPENDENT CONTROL OF BRANCH FETS FOR RF PERFORMANCE IMPROVEMENT

pSemi Corporation, San D...

1. A switch circuit including:(a) at least two switching branches, each switching branch including:
(1) at least two gateway switches configured to be connected to respective external circuit elements;
(2) a common node coupled to the at least two gateway switches; and
(3) a shunt circuit connected to the common node and programmatically settable to selectively isolate such switching branch independently of any other switching branch.

US Pat. No. 10,171,075

HIGH SPEED AND HIGH VOLTAGE DRIVER

pSemi Corporation, San D...

1. A high speed high voltage (HSHV) open drain driver comprising:a main stack of N transistors of a first type coupled between a reference voltage and an output node of the HSHV driver, the N transistors comprising a first transistor as an input transistor of the HSHV open drain driver and an Nth transistor as an output transistor of the HSHV open drain driver, N being an integer equal to or greater than three;
a biasing circuit configured to provide biasing voltages to the main stack, the biasing circuit comprising a biasing stack of N?1 transistors of a second type;
wherein:
a gate node of the first transistor of the main stack is coupled to a drain node of a first transistor of the biasing stack,
gate nodes of a second to the (N?1)th transistor of the main stack are coupled to respective N?2 common source-drain nodes of the transistors of the biasing stack,
a gate node of the Nth transistor of the main stack is coupled to a source node of the (N?1)th transistor of the biasing stack,
N?1 common source-drain nodes of transistors of the main stack are coupled to respective N?1 gate nodes of transistors of the biasing stack,
the output node is a drain node of the output transistor of the main stack of transistors adapted to be coupled to a high voltage by way of a pull-up element, and
transistors of the main stack and the biasing stack have operating voltages substantially smaller than the high voltage.

US Pat. No. 10,171,074

ELECTRONIC SYSTEM

CHICONY POWER TECHNOLOGY ...

1. An electronic system electrically connected to an alternative current (AC) power source, the electronic system comprising:a switch; and
a parallel power conversion device comprising:
a first power conversion module electrically connected to the AC power source and the switch and comprising a first current-sampling unit and a first sensing component arranged between the first current-sampling unit and the switch;
a second power conversion module electrically connected to the AC power source; and
a driver electrically connected to the second power conversion module and comprising an amplifier electrically connected to the first sensing component, a comparator electrically connected to the amplifier, a first semiconductor switch electrically connected to the second power conversion module, and a second semiconductor switch electrically connected to the second power conversion module,
wherein the driver makes the second power conversion module operate in a sleep mode to stop outputting a current and to reduce level of an outputting voltage when another current outputted from the first power conversion module is smaller than a specific value.

US Pat. No. 10,171,073

REGULATING TRANSITION SLOPE USING DIFFERENTIAL OUTPUT

SEMICONDUCTOR COMPONENTS ...

1. A circuit for producing a differential output signal pair, the circuit comprising:a first driver for a first output signal in the differential output signal pair;
a second driver for a second output signal in the differential output signal pair;
one or more monitor modules coupled to the first and second drivers to measure slope times of the first and second drivers during each transition;
a comparator coupled to the one or more monitor modules to compare the slope times of the first and second drivers;
one or more regulators coupled to the comparator and at least one of the first and second drivers to regulate at least one slope time of the first or second driver, based on output of the comparator, to provide the first and second output signals in the differential output signal pair with a constant average.

US Pat. No. 10,171,072

OPTIMIZED CMOS ANALOG SWITCH

MICROCHIP TECHNOLOGY INC....

1. An analog switch, comprising:a first butterfly circuit comprising a first thin gate oxide NMOS transistor in series with a second thin gate oxide NMOS transistor, the first butterfly circuit comprising a first terminal and a second terminal, the second terminal directly coupled to a high voltage source;
a second butterfly circuit comprising a third thin gate oxide NMOS transistor in series with a fourth thin gate oxide NMOS transistor, the second butterfly circuit comprising a third terminal directly coupled to the second terminal and a fourth terminal directly coupled to ground.

US Pat. No. 10,171,071

DEVICE AND METHOD FOR PRODUCING A DYNAMIC REFERENCE SIGNAL FOR A DRIVER CIRCUIT FOR A SEMICONDUCTOR POWER SWITCH

Power Integrations, Inc.,...

1. A device for producing a dynamic reference signal for a control circuit for a power semiconductor switch, wherein the device comprises:a reference signal generator for providing a dynamic reference signal having a steady-state signal level after a predetermined time has elapsed after a switchover process of the power semiconductor switch;
a passive charging circuit, which is configured to increase a signal level of the dynamic reference signal in reaction to a switchover of a control signal of the power semiconductor switch from an OFF state into an ON state for at least one part of the predetermined time above the steady-state signal level, in order to produce the dynamic reference signal; and
an output for tapping off the dynamic reference signal.

US Pat. No. 10,171,070

SIGNAL TRANSMISSION CIRCUIT AND POWER CONVERSION DEVICE

Mitsubishi Electric Corpo...

1. A signal transmission circuit comprising:a first circuit to output first and second transmission signals on the basis of an external input signal;
first and second transformers to receive said first and second transmission signals on a primary side and obtain first and second transformer output signals on a secondary side; and
a second circuit to generate an external output signal on the basis of said first and second transformer output signals,
wherein said external input signal has first and second logic levels, changes from the second logic level to the first logic level at a first transition time, and changes from the first logic level to the second logic level at a second transition time,
said first circuit outputs said first and second transmission signals such that said first transmission signal changes between the first and second logic levels in a first period when said external input signal is at the first logic level, is fixed to the second logic level when said external input signal is at the second logic level, and is set at the first logic level for a predetermined period at said first transition time of said external input signal, and
such that said second transmission signal changes between the first and second logic levels in a second period when said external input signal is at the second logic level, is fixed to the second logic level when said external input signal is at the first logic level, and is set at the first logic level for a predetermined period at said second transition time of said external input signal, and
said second circuit includes
first and second control protectors to invalidate said first and second transformer output signals for first and second mask periods on the basis of the first or second logic level of said external output signal,
a first signal shaping circuit to receive said first transformer output signal via said first control protector and generate a first logic setting signal indicating an active level for a first logic setting period exceeding a period for which said first transformer output signal indicates an active level,
a second signal shaping circuit to receive said second transformer output signal via said second control protector and generate a second logic setting signal indicating an active level for a second logic setting period exceeding a period for which said second transformer output signal indicates an active level,
a logic setting signal control circuit to receive said first and second logic setting signals and invalidate indication of an active level by said first and second logic setting signals when both said first and second logic setting signals indicate an active level, and
an output signal generation circuit to receive said first and second logic setting signals via said logic setting signal control circuit and generate said external output signal that is set at one logic level of first and second logic levels when said first logic setting signal indicates an active level, and set at the other logic level when said second logic setting signal indicates an active level.

US Pat. No. 10,171,069

SWITCH CONTROLLER FOR ADAPTIVE REVERSE CONDUCTION CONTROL IN SWITCH DEVICES

GENERAL ELECTRIC COMPANY,...

1. A switch controller configured to control a voltage-controlled power switch device, comprising:an output stage coupled to a control terminal of the voltage-controlled power switch device, wherein the output stage is configured to receive a driving signal and provide a driving voltage to the control terminal of the voltage-controlled power switch device;
a voltage sensor configured to provide a measurement of a voltage across the power switch device; and
a digital processing unit configured to receive a switching command and the measurement of the voltage, and to provide the driving signal to the output stage, wherein the digital processing unit is configured to:
compare the measurement with a limit voltage;
cause, using the driving signal, the output stage to provide a first voltage as the driving voltage when the digital processing unit receives the switching command and the measurement is above the limit voltage; and
cause, using the driving signal, the output stage to provide a second voltage as the driving voltage when the digital processing unit receives the switching command and the measurement is below the limit voltage.

US Pat. No. 10,171,068

INPUT INTERFACE CIRCUIT

MSTAR SEMICONDUCTOR, INC....

1. An input interface circuit, comprising:a power line, supplying a default operating voltage;
a ground line, supplying a ground voltage;
an input pad, receiving a pad voltage;
a clamping circuit, coupled between the input pad and a first node, the clamping circuit causing a voltage at the first node to be maintained at the default operating voltage when the pad voltage is higher than the default operating voltage;
a first inverter, having an input end and an output end, the input end coupled to the first node and the output end coupled to a second node;
a high-voltage buffering circuit, having a first input end, a second input end and an output end, the first input end coupled to the input pad, the second input end coupled to the second node, and the output end coupled to a third node, wherein a voltage at the third node is adjusted along with the pad voltage and a voltage at the second node, and the voltage at the third node has a same voltage change trend as the pad voltage;
a second inverter, having an input end and an output end, the input end coupled to the third node and the output end coupled to a fourth node;
a voltage recovery circuit, connected between the power line and the ground line, having an input end and an output end, the input end coupled to the fourth node and the output end coupled to the third node, the third node is selectively coupled to one of the power line and the ground line according to a voltage at the fourth node; and
a third inverter, having an input end thereof coupled to the fourth node and an output end thereof providing a converted voltage.

US Pat. No. 10,171,067

WAVEFORM SHAPING FILTER, INTEGRATED CIRCUIT, RADIATION DETECTION DEVICE, METHOD FOR ADJUSTING TIME CONSTANT OF WAVEFORM SHAPING FILTER, AND METHOD FOR ADJUSTING GAIN OF WAVEFORM SHAPING FILTER

KABUSHIKI KAISHA TOSHIBA,...

1. A waveform shaping filter comprising:a filter stage comprising:
a differentiation signal generation circuit which generates a differentiation signal by amplifying a signal obtained by differentiating an input signal,
a proportional signal generation circuit which generates a proportional signal by amplifying the input signal, and
an adder circuit which outputs an output signal obtained by adding the proportional signal and the differentiation signal; and
a control circuit connected to the filter stage, the control circuit comparing the output signal and a first value so as to detect an overshoot or an undershoot of the output signal, and controlling a time constant of the filter stage, based on whether the overshoot or the undershoot of the output signal has been detected.

US Pat. No. 10,171,066

COMPACT HIGH VOLTAGE RF GENERATOR USING A SELF-RESONANT INDUCTOR

SMITHS DETECTION-WATFORD ...

1. An RF circuit for providing a radio frequency signal, the circuit comprising:a dual inductor including one winding including an input and an output, and another winding including an input and an output;
wherein the one winding and the another winding are arranged to provide, between the one winding and the another winding, a parasitic capacitance selected to determine the frequency of the radio frequency signal; and
wherein the outputs of the windings are configured to electrically couple to a capacitive load.

US Pat. No. 10,171,065

PVT STABLE VOLTAGE REGULATOR

International Business Ma...

1. An apparatus comprising:a voltage regulation module configured to provide an output voltage signal (Vout);
an auto-calibration module configured to provide a calibration current signal (Isink) corresponding to a voltage difference between a target voltage signal (Vtarget) and the output voltage signal (Vout), wherein the output voltage signal (Vout) is substantially equal to the target voltage signal (Vtarget); and
the voltage regulation module configured to adjust the output voltage in response to changes in the calibration current signal.

US Pat. No. 10,171,064

ELASTIC WAVE DEVICE AND ELASTIC WAVE MODULE

MURATA MANUFACTURING CO.,...

1. An elastic wave device comprising:a first piezoelectric substrate including a first principal surface and a second principal surface;
a second piezoelectric substrate including a first principal surface and a second principal surface, a thickness of the second piezoelectric substrate being greater than a thickness of the first piezoelectric substrate;
a plurality of first interdigital transducer (IDT) electrodes and a plurality of second IDT electrodes, the plurality of first IDT electrodes being located on the first principal surface of the first piezoelectric substrate, and the plurality of second IDT electrodes being located on the first principal surface of the second piezoelectric substrate; and
a plurality of external connection terminals located on the second principal surface of the first piezoelectric substrate; wherein
a first elastic wave filter including the plurality of first IDT electrodes is located on the first principal surface of the first piezoelectric substrate;
a second elastic wave filter including the plurality of second IDT electrodes is located on the first principal surface of the second piezoelectric substrate;
at least one of the plurality of external connection terminals is a ground terminal;
the first piezoelectric substrate and the second piezoelectric substrate are joined with a support member located therebetween, with the first principal surface of the first piezoelectric substrate and the first principal surface of the second piezoelectric substrate facing each other;
the support member surrounds a region where the first elastic wave filter and the second elastic wave filter are located, in a planar view;
out-of-band attenuation of the first elastic wave filter is greater than out-of-band attenuation of the second elastic wave filter; and
a maximum value of out-of-band attenuation in a frequency band in a range between about 0.85 times and about 1.15 times a center frequency of a passband of the first elastic wave filter, both inclusive, is greater than any out-of-band attenuation in a frequency band in a range between about 0.85 times and about 1.15 times a center frequency of a passband of the second elastic wave filter, both inclusive.

US Pat. No. 10,171,063

FILTER MODULE

WISOL CO., LTD., Osan-si...

14. A mobile communication terminal comprising:an antenna; and
a filter module connected to the antenna, wherein the filter module includes:
a substrate;
a plurality of filters formed on the substrate;
an amplifier formed on the substrate;
a connection part for connecting the plurality of filters and the amplifier to the substrate;
a cover layer formed on the substrate to cover the plurality of filters and the amplifier; and
a matching element formed on the substrate for matching impedances of the plurality of filters and the amplifier,
wherein the plurality of filters and the amplifier are simultaneously or sequentially packaged, and
wherein the matching element is formed in a shape of a layered spiral in a space between input terminals and output terminals of the plurality of filters.

US Pat. No. 10,171,062

VARIABLE-FREQUENCY FILTER

MURATA MANUFACTURING CO.,...

1. A variable-frequency filter allowing a pass band and an attenuation range to be adjusted, the filter comprising:a series-arm resonant circuit connected between a first input/output terminal and a second input/output terminal; and
a parallel-arm resonant circuit connected between a ground and a transmission line connecting one of the first input/output terminal and the second input/output terminal to the series-arm resonant circuit,
wherein each of the series-arm resonant circuit and the parallel-arm resonant circuit includes a piezoelectric resonator, an inductor connected to the piezoelectric resonator, and a variable capacitor connected to the piezoelectric resonator,
wherein the pass band or attenuation range is adjusted by using at least one of a sub-resonant point or a sub-anti-resonant point of the series-arm resonant circuit, or a sub-resonant point or a sub-anti-resonant point of the parallel-arm resonant circuit,
wherein the inductor of the parallel-arm resonant circuit is connected in parallel with the piezoelectric resonator of the parallel-arm resonant circuit, and generates sub-anti-resonance at a lower frequency than a resonant point of the parallel-arm resonant circuit, and
wherein the pass band is set by using the sub-anti-resonant point of the parallel-arm resonant circuit.

US Pat. No. 10,171,061

ELASTIC WAVE DEVICE

MURATA MANUFACTURING CO.,...

1. An elastic wave device comprising:a piezoelectric film;
a high acoustic velocity material in which an acoustic velocity of a bulk wave that propagates through the high acoustic velocity material is higher than that of an elastic wave that propagates through the piezoelectric film;
a low acoustic velocity film which is laminated on the high acoustic velocity material and in which an acoustic velocity of a bulk wave that propagates through the low acoustic velocity film is lower than that of the elastic wave that propagates through the piezoelectric film; and
an IDT electrode on one surface of the piezoelectric film; wherein
the piezoelectric film is laminated on the low acoustic velocity film;
the IDT electrode includes a first busbar, a second busbar that is spaced apart from the first busbar, a plurality of first electrode fingers with proximal ends electrically connected to the first busbar and distal ends extending towards the second busbar, and a plurality of second electrode fingers with proximal ends connected to the second busbar and distal ends extending towards the first busbar;
a direction that is perpendicular or substantially perpendicular to a direction in which the first electrode fingers and the second electrode fingers extend is a width direction, the first electrode fingers, or the second electrode fingers, or each of the first electrode fingers and the second electrode fingers, includes a wide width portion with a dimension in the width direction that is larger than a dimension at a center in a length direction of the first electrode fingers and the second electrode fingers and being provided closer to at least one of a side of the proximal end and a side of the distal end than a central region;
at least one of the first busbar and the second busbar includes a plurality of cavities that are distributed in a length direction of the first busbar or the second busbar; and
the first busbar, or the second busbar, or each of the first busbar and the second busbar, includes an inner busbar portion which is positioned closer to a side of the first electrode fingers or a side of the second electrode fingers than the cavities are and which extends in the length direction of the first busbar and the second busbar, a central busbar portion that includes the cavities, and an outer busbar portion that is positioned opposite to the inner busbar portion with the central busbar portion being interposed therebetween.

US Pat. No. 10,171,060

HIGH PASS FILTER

MURATA MANUFACTURING CO.,...

1. A high pass filter comprising:a first input and output terminal;
a second input and output terminal;
at least one ground terminal;
a signal path disposed between the first input and output terminal and the second input and output terminal;
a first LC series resonator including a first inductor, a first capacitor, a first end electrically connected to the signal path, and a second end electrically connected to the at least one ground terminal, the first inductor, and the first capacitor;
a second LC series resonator including a second inductor, a second capacitor, a third end electrically connected to the signal path, and a fourth end electrically connected to the at least one ground terminal, the second inductor, and the second capacitor;
a third capacitor; and
a multilayer body including a stack of a plurality of insulator layers in a stacking direction; wherein
one electrode of the third capacitor is connected between the first capacitor and the first inductor, and another electrode of the third capacitor is connected between the second capacitor and the second inductor;
the first LC series resonator includes at least one first conductor layer disposed on a corresponding one of the plurality of insulator layers;
the second LC series resonator includes at least one second conductor layer disposed on a corresponding one of the plurality of insulator layers;
the third capacitor includes a first capacitor conductor layer facing at least one of the at least one first conductor layer and the at least one second conductor layer, with a corresponding at least one of the plurality of insulator layers interposed therebetween;
the at least one first conductor layer includes at least one first inductor conductor layer wound in a predetermined direction when viewed in the stacking direction and a second capacitor conductor layer; and
the at least one second conductor layer includes at least one second inductor conductor layer wound in a direction opposite to the predetermined direction when viewed in the stacking direction and a third capacitor conductor layer.

US Pat. No. 10,171,059

COMPOSITE COMPONENT AND FRONT-END MODULE

MURATA MANUFACTURING CO.,...

1. A composite component adapted for being disposed on a mounting substrate, the composite component comprising:a transmitting filter;
a first substrate adapted for being disposed adjacent to the mounting substrate and electrically connected to the mounting substrate;
a second substrate disposed opposite to the first substrate;
a spacer member interposed between the first substrate and the second substrate to support the first substrate and the second substrate, the spacer member being configured to electrically connect the first substrate to the second substrate,
wherein the second substrate is adapted for being electrically connected to the mounting substrate through a second spacer member; and
the transmitting filter is disposed in an internal space and on a principal surface of the first substrate, the internal space being surrounded by the first substrate and the second substrate.

US Pat. No. 10,171,058

ELECTRONIC DEVICE WITH IN-POCKET AUDIO TRANSDUCER ADJUSTMENT AND CORRESPONDING METHODS

Motorola Mobility LLC, C...

1. A method in an electronic device, the method comprising:detecting, with one or more sensors of the electronic device, an enclosed condition;
determining, with one or more processors, an audio signal adjustment function for one or more audio transducers of the electronic device in response to the enclosed condition, wherein the one or more audio transducers comprise a plurality of microphones;
applying, with the one or more processors, the audio signal adjustment function to signals received from, or delivered to, the one or more audio transducers during the enclosed condition;
determining, with the one or more processors, which microphone of the plurality of microphones receives a least amount of enclosure noise; and
selecting, with the one or more processors, the microphone receiving the least amount of enclosure noise to capture audio input from an environment of the electronic device during the enclosed condition.

US Pat. No. 10,171,057

AUTOMATIC GAIN CONTROL LOOP

Elenion Technologies, LLC...

1. An optical receiver comprising:a photodetector for converting an optical signal into an input electrical current signal;
a transimpedance amplifier (TIA) for converting the input electrical current signal into an input voltage signal, the TIA including a variable feedback resistor and a variable gain feed-forward amplifier;
a variable gain amplifier (VGA) for amplifying the input voltage signal to a desired voltage level; and
an automatic gain control loop for generating a first gain control signal for controlling gain of the VGA, and a second gain control signal for controlling the gain of the TIA;
wherein the automatic gain control loop further comprises a signal conditioning circuit for generating the second gain control signal for controlling gain of the TIA based on the first gain control signal;
wherein the second gain control signal is capable of adjusting a value of the variable feedback resistor, whereby the TIA gain varies linearly with a level of the second gain control signal; and
wherein the second gain control signal is also capable of varying a feed forward gain Ao of the TIA.

US Pat. No. 10,171,056

APPARATUS AND METHOD FOR IMPROVING NONLINEARITY OF POWER AMPLIFIER IN WIRELESS COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method for operating an apparatus comprising a transceiver and a power amplifier, in a wireless communication system, the method comprising:attenuating a power of a signal based on a gain compensation value corresponding to the power of the signal, if the power of the signal inputted to the transceiver coupled with the power amplifier is smaller than a reference value; and
transmitting the signal with the attenuated power to the power amplifier.

US Pat. No. 10,171,055

AUDIO CONTROL SYSTEM AND RELATED METHODS

iZotope, Inc., Cambridge...

1. A method for use with an audio system comprising at least one amplifier, the method comprising acts of:(A) receiving, at the audio system, audio input produced by at least one audio source;
(B) determining a gain level associated with the audio input;
(C) automatically, without intervention by a user of the audio system, adjusting a gain level of the at least one amplifier, so that subsequent output of the at least one amplifier falls within a dynamic range delimited by a lower gain level and an upper gain level;
wherein the method comprises, after the act (B), receiving a second audio input while the audio source is not producing sound, and the act (C) comprises determining the lower gain level of the dynamic range based at least in part on a gain level of the second audio input.

US Pat. No. 10,171,054

AUDIO ADJUSTMENT BASED ON DYNAMIC AND STATIC RULES

International Business Ma...

1. A method implemented by an information handling system that includes a processor and a memory accessible by the processor, the method comprising:prioritizing a plurality of dynamic rules and a plurality of static rules, wherein the dynamic rules and the static rules are included in a set of rules applied to an output of an audio system;
comparing a set of one or more inputs to the set of rules, wherein the comparing is performed according to the prioritization of the dynamic rules and the static rules;
retrieving at least one audio adjustment based on the comparisons; and
automatically adjusting the output of the audio system based on the retrieved audio adjustment.

US Pat. No. 10,171,053

APPARATUS AND METHODS FOR POWER AMPLIFIERS WITH AN INJECTION-LOCKED OSCILLATOR DRIVER STAGE

SKYWORKS SOLUTIONS, INC.,...

1. A multi-mode power amplifier comprising:a driver stage including an injection-locked oscillator configured to receive a radio frequency input signal and to generate an injection-locked radio frequency signal;
an output stage configured to amplify the injection-locked radio frequency signal to generate a radio frequency output signal, the output stage configured to receive power from an adjustable supply voltage; and
a supply control circuit configured to control a voltage level of the adjustable supply voltage based on a mode of the multi-mode power amplifier.

US Pat. No. 10,171,052

OPERATIONAL AMPLIFIER AND DIFFERENTIAL AMPLIFYING CIRCUIT THEREOF

REALTEK SEMICONDUCTOR COR...

1. An operational amplifier, having a differential input pair and a differential output pair, comprising:an output stage amplifying circuit, using a first terminal and a second terminal as an input port thereof and using said differential output pair as an output port thereof;
a first transistor pair, comprising a first transistor and a second transistor, wherein a first end of said first transistor and a first end of said second transistor are respectively coupled to a first input end and a second input end of said differential input pair, and a second end of said first transistor and a second end of said second transistor are respectively coupled to said first terminal and said second terminal;
a second transistor pair, comprising a third transistor and a fourth transistor, wherein a first end of said third transistor and a first end of said fourth transistor are respectively coupled to said first input end and said second input end of said differential input pair, and a second end of said third transistor and a second end of said fourth transistor are respectively coupled to said first terminal and said second terminal;
a first current source, coupled to said first terminal;
a second current source, coupled to said second terminal;
a third transistor pair, comprising a fifth transistor and a sixth transistor, wherein a first end of said fifth transistor and a first end of said sixth transistor respectively receive a control signal, and a second end of said fifth transistor and a second end of said sixth transistor are respectively coupled to said first terminal and said second terminal; and
a control circuit, coupled to said differential output pair, for generating said control signal according to voltages of said differential output pair and a common mode voltage.

US Pat. No. 10,171,051

AMPLIFICATION CIRCUIT, OPTICAL MODULE, AND AMPLIFICATION METHOD

FUJITSU LIMITED, Kawasak...

1. An amplification circuit coupled to a first circuit by alternating current (AC) coupling comprising:an amplifier that amplifies an input signal by gain A and outputs the amplified input signal as a first signal to a second circuit;
a loopback circuit that positively feeds back the first signal output from the amplifier to an input of the amplifier, the loopback circuit includes
a low pass filter that attenuates a high frequency component of the first signal and outputs the attenuated first signal as a second signal, and
a feedback circuit that attenuates the second signal output from the low pass filter by a feedback factor (gain) ? and positively feeds back to the input of the amplifier; and
a high pass filter using AC coupling is formed at an input of the amplification circuit,
a loop gain of the loopback circuit is represented as a product A·?, and the loop gain is designed so as to satisfy 0 the amplifier is a differential amplifier, and the feedback circuit includes
a first feedback circuit that positively feeds back a normal output of the differential amplifier to an input of the differential amplifier, and
a second feedback circuit that positively feeds back an inversion output of the differential amplifier to the input of the differential amplifier.

US Pat. No. 10,171,050

CIRCUITS FOR PROVIDING CLASS-E POWER AMPLIFIERS

The Trustees of Columbia ...

1. A circuit for forming an amplifier comprising:a first switch having a first side and a second side;
one of a first inductor and a first transmission line, the one of the first inductor and the transmission line having a first side connected to the first side of the first switch and having a second side connected to a non-ground power supply voltage;
one of a second inductor and a second transmission line, the one of the second inductor and the second transmission line having a first side and a second side, the second side of the one of the second inductor and the second transmission line connected to a non-ground power supply voltage; and
a second switch having a first side and a second side, the first side of the second switch being directly connected to the second side of the first switch and the first side of the one of the second inductor and the second transmission line.

US Pat. No. 10,171,049

CLASS-D AMPLIFIER CIRCUITS

Cirrus Logic, Inc., Aust...

1. A Class-D amplifier circuit for amplifying an input signal comprising:an output stage comprising at least first and second switches;
a modulator comprising a signal input for receiving said input signal and a clock input for receiving a first clock signal, the modulator being configured to control the duty cycles of said first and second switches within a switching cycle based on said input signal, wherein said switching cycle has a switching frequency based on said clock signal; and
a frequency controller configured to control the frequency of said first clock signal in response to an indication of amplitude of the input signal;
wherein the frequency controller is configured to implement a transition in frequency of said first clock signal from a first switching frequency to a second switching frequency over a period of time, such that the rate of change of switching frequency with time is variable during said transition.

US Pat. No. 10,171,048

POWER AMPLIFIER

Samsung Electro-Mechanics...

1. A power amplifier comprising:an amplifying circuit comprising
a first field effect transistor configured to amplify an input signal, and
a second field effect transistor connected to the first field effect transistor in a cascode structure, and configured to receive the signal amplified by the first field effect transistor and to output the received signal;
a feedback circuit connected to the amplifying circuit, and configured to feedback the signal amplified in the amplifying circuit into the amplifying circuit; and
a feedback controlling circuit connected to the feedback circuit, and configured to control a power of the signal fed-back by the feedback circuit based on a power of the input signal,
wherein the feedback controlling circuit is configured to control the feedback circuit to increase the power of the signal fed-back by the feedback circuit, in response to the power of the input signal input to the amplifying circuit being increased.

US Pat. No. 10,171,046

SYSTEM AND METHOD FOR LOW DISTORTION CAPACITIVE SIGNAL SOURCE AMPLIFIER

INFINEON TECHNOLOGIES AG,...

1. A method comprising:amplifying a signal provided by a capacitive signal source to form an amplified signal;
detecting a peak voltage of the amplified signal;
comparing the detected peak voltage to a predetermined threshold; and
adjusting a controllable bias voltage of the capacitive signal source in response to detecting the peak voltage, the controllable bias voltage of the capacitive signal source being adjusted to a value inversely proportional to the detected peak voltage, wherein adjusting the controllable bias voltage comprises
decreasing the controllable bias voltage at a first rate if the detected peak voltage exceeds the predetermined threshold, and
increasing the controllable bias voltage at a second rate if detected peak voltage does not exceed the predetermined threshold, wherein the first rate is greater than the second rate.

US Pat. No. 10,171,045

APPARATUS AND METHODS FOR LOW NOISE AMPLIFIERS WITH MID-NODE IMPEDANCE NETWORKS

SKYWORKS SOLUTIONS, INC.,...

1. A low noise amplifier comprising:a cascode device;
a transconductance device configured to generate an amplified signal based on amplifying an input signal received at an input node, the transconductance device further configured to provide the amplified signal to an output node via the cascode device; and
a mid-node impedance network electrically connected between the transconductance device and the cascode device, the mid-node impedance configured to compensate for a parasitic capacitance of the transconductance device, the mid-node impedance network including a resistor, a capacitor, and an inductor electrically connected in parallel with one another.

US Pat. No. 10,171,044

POWER AMPLIFICATION CIRCUIT

MURATA MANUFACTURING CO.,...

1. A power amplification circuit comprising:a first amplifier that is input with a first signal and outputs a second signal obtained by amplifying the first signal;
a bias circuit that supplies a bias current or a bias voltage to the first amplifier; and
a control voltage generating circuit that generates a control voltage in accordance with a signal level of the first signal,
wherein the bias circuit includes:
a first transistor, the bias current or bias voltage being output from an emitter or source of the first transistor,
a second transistor that is provided between the emitter or the source of the first transistor and ground; and
a third transistor, wherein the control voltage is supplied to a base or gate of the third transistor and an emitter or source of the third transistor supplies a first current or a first voltage to a base or gate of the second transistor,
wherein the control voltage generating circuit includes:
a second amplifier that is input with the first signal and outputs a third signal obtained by amplifying the first signal, and
a voltage outputting circuit that outputs the control voltage in accordance with the third signal, and
wherein the voltage outputting circuit includes:
a current-voltage converting circuit that outputs a second voltage in accordance with a current of the third signal, and
a voltage-level converting circuit that converts the second voltage into the control voltage such that the value of the first current or the first voltage is larger when the signal level of the first signal is the first level than when the signal level of the first signal is the second level.

US Pat. No. 10,171,043

AMPLIFICATION DEVICE INCORPORATING LIMITING

Telefonaktiebolaget LM Er...

1. An amplification device, comprising:an amplifier circuit comprising a signal input for an input signal to be amplified and a first signal output for a first output signal; and
a limiter, wherein the limiter comprises:
a differential amplifier comprising:
a first differential amplifier input for a threshold control signal;
a second differential amplifier input for a feedback signal; and
a differential amplifier output for a threshold signal indicative of a difference between the threshold control signal and the feedback signal;
a first diode having a first anode coupled to the first signal output and a first cathode coupled to the differential amplifier output; and
a feedback stage coupled between the differential amplifier output and the second differential amplifier input, wherein the feedback stage is configured to generate the feedback signal dependent on the threshold signal.

US Pat. No. 10,171,042

DEGENERATED TRANSIMPEDANCE AMPLIFIER WITH WIRE-BONDED PHOTODIODE FOR REDUCING GROUP DELAY DISTORTION

International Business Ma...

1. An integrated circuit comprising:a degeneration network configured to improve group delay across one or more variations;
wherein the degeneration network comprises:
one or more degeneration inductors; and
a transimpedance amplifier including the one or more degeneration inductors;
wherein the transimpedance amplifier includes at least two transistors, and the one or more degeneration inductors are connected between emitters of each of the at least two transistors.

US Pat. No. 10,171,041

PREDISTORTION DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A device, comprising:an input terminal configured to receive an input signal;
a predistortion filter, connected between the input terminal and a non-linear power amplifier (PA), the predistortion filter having second filter weights;
a first delay element coupled to the input terminal, and configured to delay the input signal by a time delay D to provide a delayed input signal;
an adaptive filter having first filter weights, and configured to filter the delayed input signal; and
an adjuster configured to, according to an adaptive algorithm and the delayed input signal, adjust the first filter weights of the adaptive filter and the second filter weights of the predistortion filter so that the first filter weights are the same as the second filter weights,
wherein both the adaptive filter and the adjuster are coupled to the first delay element to receive the delayed input signal.

US Pat. No. 10,171,040

TRANS-IMPEDANCE AMPLIFIER

HANGZHOU HONGXIN MICROELE...

1. A trans-impedance amplifier, comprising:an equivalent secondary amplifier module, having an input end and an output end, the input end being coupled to an optical diode and used for accessing an input voltage signal, the output end being used for outputting a secondarily amplified first voltage signal;
an inverting amplifier unit, coupled to the output end of the equivalent secondary amplifier module and used for accessing the first voltage signal and outputting an inverting amplified voltage signal, the inverting amplifier unit comprising a third N-type transistor and a fourth N-type transistor, both a first end and a second end of the third N-type transistor being used for receiving a third DC voltage signal, a third end thereof being used for outputting an inverting amplified voltage signal; a first end of the fourth N-type transistor being coupled to the third end of the third N-type transistor, a second end thereof being coupled to the output end of the equivalent secondary amplifier module and used for receiving the first voltage signal, and a third end thereof being grounded; and
a feedback resistor, coupled to the input end of the equivalent secondary amplifier module and an output end of the inverting amplifier unit.

US Pat. No. 10,171,039

DEVICES AND METHODS THAT FACILITATE POWER AMPLIFIER OFF STATE PERFORMANCE

Infineon Technologies AG,...

1. A peaking amplifier comprising:a driver stage having a load impedance and configured to generate a driver output signal based on an input signal;
a final stage having a final stage input impedance and configured to generate a peaking output signal at an output based on the driver output signal; and
an interstage matching network coupled to the driver stage and the final stage and configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is in an ON state and provide a short circuit from an output of the driver stage to an input of the final stage when the peaking amplifier is in an OFF state.

US Pat. No. 10,171,038

ENVELOPE-TRACKING POWER SUPPLY MODULATOR

REALTEK SEMICONDUCTOR COR...

1. An envelope-tracking power supply modulator (ETSM), supplying power to a radio frequency power amplifier (RFPA) of a radio frequency (RF) circuit according to a baseband envelope signal, comprising:a linear amplifier having an input terminal and an output terminal, wherein the input terminal receives the baseband envelope signal, and the output terminal is coupled to a power input of the RFPA;
a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to a reference voltage, and the second terminal is coupled to a power input of the linear amplifier;
a single-inductor multiple-output (SIMO) switch-mode converter having a first output terminal and a second output terminal, wherein the first output terminal is coupled to the capacitor and the power input of the linear amplifier, and the second output terminal is coupled to the output terminal of the linear amplifier and the power input of the RFPA; and
a controller, coupled to the linear amplifier, the capacitor, and the SIMO switch-mode converter, controlling the SIMO switch-mode converter.

US Pat. No. 10,171,037

MULTI-MODE POWER MANAGEMENT SYSTEM SUPPORTING FIFTH-GENERATION NEW RADIO

Qorvo US, Inc., Greensbo...

1. A multi-mode power management system comprising:a power amplifier circuit configured to amplify a fifth-generation new radio (5G-NR) signal to an output power level for transmission in a 5G-NR band, the power amplifier circuit comprising:
a carrier amplifier configured to amplify the 5G-NR signal to a first power level in response to receiving a first bias voltage at a first bias voltage input; and
a peaking amplifier configured to amplify the 5G-NR signal to a second power level in response to receiving a second bias voltage at a second bias voltage input;
wherein a sum of the first power level and the second power level equals the output power level;
first tracker circuitry configured to generate a first voltage at a first voltage output;
second tracker circuitry configured to generate a second voltage at a second voltage output; and
control circuitry configured to:
couple the first voltage output to the first bias voltage input and the second bias voltage input in a 5G-NR low power mode; and
couple the first voltage output and the second voltage output to the first bias voltage input and the second bias voltage input, respectively, in a 5G-NR high power mode.

US Pat. No. 10,171,036

POWER AMPLIFICATION CIRCUIT

MURATA MANUFACTURING CO.,...

1. A power amplification circuit comprising:an amplifier that amplifies an input signal and outputs an amplified signal;
a first bias circuit that supplies a first bias current or voltage to the amplifier;
a second bias circuit that supplies a second bias current or voltage to the amplifier;
a first control circuit that outputs a first current that controls a level of the first bias current or voltage; and
a second control circuit that outputs a second current that controls a level of the second bias current or voltage;
wherein a current supplying capacity of the first bias circuit is different from a current supplying capacity of the second bias circuit,
wherein the first bias circuit comprises a first transistor that outputs the first bias current or voltage in accordance with the first current,
wherein the second bias circuit comprises a second transistor that outputs the second bias current or voltage in accordance with the second current, and comprises a fourth transistor, wherein a collector of the fourth transistor is connected to a base or gate of the second transistor, a base of the fourth transistor is connected to an emitter or source of the second transistor, an emitter of the fourth transistor is connected to ground, and the second current is supplied to the collector of the fourth transistor, and
wherein a size of the first transistor is different from a size of the second transistor.

US Pat. No. 10,171,035

POWER FACTOR CORRECTION CIRCUIT AND MULTIPLIER

COSEMITECH (SHANGHAI) CO....

1. A multiplier comprising:a Gilbert multiplier circuit comprising a first differential input stage, a second differential input stage and an output stage; said output stage outputting the output current calculated by the input of said first differential input stage and the input of the second differential input stage;
a first differential voltage conversion circuit configured to generate a first differential voltage to bias said first differential input stage based on an error feedback voltage signal and a first reference voltage;
a second differential voltage conversion circuit configured to generate a second differential voltage to bias said second differential input stage based on an input voltage and a second reference voltage; and
a bias current generating circuit configured to generate a bias current to bias a first signal conversion circuit and a second signal conversion circuit;
wherein said output stage comprises:
a current mirror unit comprising two current input terminals and a current output terminal; and
a feedback control unit configured to ensure that the current output terminal does not output current when the voltage difference received by the multiplier is zero;
wherein the feedback control unit includes
a first operational amplifier comprising two input terminals connected to the current input terminals of said current mirror unit respectively;
a first switching element comprising a first terminal connected to the current output terminal of said current mirror unit, a second terminal connected to one input terminal of said first operational amplifier, and a control terminal connected to an output terminal of said first operational amplifier; and
a second switching element comprising a first terminal connected to the current output terminal of said current mirror unit, a second terminal configured to output said output current, and a control terminal connected to the output terminal of said first operational amplifier.

US Pat. No. 10,171,034

PHASE-ROTATED HARMONIC-REJECTION MIXER APPARATUS

MEDIATEK INC., Hsin-Chu ...

8. A harmonic-rejection mixer apparatus comprising:a mixing circuit, configured to receive a first input signal, a second input signal, and a local oscillator (LO) signal, and further configured to mix the first input signal and the LO signal to generate a first output signal and mix the second input signal and the LO signal to generate a second output signal, wherein the first input signal and the second input signal have a same peak amplitude but different phases; and
a combining circuit, configured to combine the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.

US Pat. No. 10,171,033

CRYSTAL OSCILLATOR INTERCONNECT ARCHITECTURE WITH NOISE IMMUNITY

Intel Corporation, Santa...

1. An apparatus comprising:a crystal having an input and an output;
a first interconnect having first and second ends, wherein the first end is coupled to the input;
a second interconnect having first and second ends, wherein the first end is coupled to the output;
a first capacitor coupled between the input and a ground; and
a second capacitor coupled to the second end of the second interconnect, wherein
the second capacitor is split between:
on-board and on-package; or
on-board and on-die.

US Pat. No. 10,171,032

APPARATUSES AND METHODS FOR TEMPERATURE INDEPENDENT OSCILLATORS

Micron Technology, Inc., ...

1. An apparatus, comprising:a pulse generator circuit configured to provide a periodic pulse based on the charging and discharging of a capacitor and further based on first and second reference voltages, the pulse generator comprising:
the capacitor coupled between the first reference voltage and a first node, wherein the capacitor is configured to be charged and discharged through the first node in response to the periodic pulse;
a resistor and a diode coupled in series between a second node and the second reference voltage; and
a comparator coupled to the first and second nodes and configured to provide the periodic pulse based on voltages on the first and second nodes, wherein a period of the periodic pulse is based at least on the resistor and a current.

US Pat. No. 10,171,031

OSCILLATOR PHASE NOISE USING ACTIVE DEVICE STACKING

International Business Ma...

1. An integrated electronic circuit, comprising:active decoupling circuits, including,
a first active device with a first capacitive device connected across the non-current control terminals of the first active device, and the current control terminal of the first active device connected to ground across a third capacitive device, wherein the current control terminal of the first active device is not electrically coupled to the non-current control terminals of the first active device; and
a second active device with a second capacitive device connected across the non-current control terminals of the second active device, and the current control terminal of the second active device connected to ground across a fourth capacitive device, wherein the current control terminal of the second active device is not electrically coupled to the non-current control terminals of the second active device, and wherein a first non-current control terminal of the first active device is electrically coupled to a first non-current control terminal of the second active device through an inductor.

US Pat. No. 10,171,030

METHOD OF AMPLIFYING POWER

IsoLine Component Company...

1. A method of amplifying power for components mounted on a printed circuit board using a printed circuit board-mounted power supply, the method comprising:optically coupling one or more than one photovoltaic device to a photoluminescent light source, wherein the one or more than one photovoltaic device receives light from the photoluminescent light source;
supplying light source electrical input power to the photoluminescent light source, wherein the light source electrical input power is received from a power source external to the printed circuit board-mounted power supply;
collecting photovoltaic-generated electrical output power from the one or more than one photovoltaic device;
providing the photovoltaic-generated electrical output power to components mounted on the printed circuit board; and
creating the photoluminescent light source, wherein the step of creating the photoluminescent light source comprises a step of optically coupling a light-emitting device that emits high energy light photons in response to receiving light source electrical input power to a photoluminescent material, wherein the photoluminescent material absorbs the high energy light photons emitted by the light-emitting device, and emits more than one low energy light photon for each of the high energy light photons absorbed.

US Pat. No. 10,171,029

SOILING MEASUREMENT DEVICE FOR PHOTOVOLTAIC ARRAYS EMPLOYING MICROSCOPIC IMAGING

1. A device comprisinga transparent window,
an imaging unit, and
a computing element coupled to said imaging unit,
wherein
said device is configured to allow soiling particles to accumulate on a surface of said transparent window,
said imaging unit is configured to capture an image of said surface, and
said computing element is configured to perform analysis of said image to determine a soiling level of said transparent window,
wherein said analysis comprises
determining a reference brightness of said image corresponding to a clean state of said transparent window, and
determining said soiling level based at least upon a brightness of said image relative to said reference brightness.

US Pat. No. 10,171,028

METHOD AND APPARATUS FOR MONITORING PHOTOVOLTAIC MODULE

HUAWEI TECHNOLOGIES CO., ...

1. A method for monitoring a photovoltaic module, the method being applied to a module voltage monitoring system, the module voltage monitoring system comprising a primary monitoring apparatus and several module voltage monitoring apparatuses, a communication address being allocated to each module voltage monitoring apparatus, the primary monitoring apparatus establishing a connection to the corresponding module voltage monitoring apparatus using the communication address, each module voltage monitoring apparatus corresponding to a module of a photovoltaic string, the module voltage monitoring apparatus being configured to sample a relative voltage of the corresponding module relative to a voltage reference point, and the method comprising:obtaining, by the primary monitoring apparatus, communication addresses of all the module voltage monitoring apparatuses;
establishing a connection to a corresponding module voltage monitoring apparatus using the communication address;
obtaining a relative voltage of a corresponding module relative to the voltage reference point from the module voltage monitoring apparatus to which the connection is established;
obtaining, by the primary monitoring apparatus according to relative voltages obtained from all the module voltage monitoring apparatuses, a physical location that is of a module corresponding to each module voltage monitoring apparatus and that is in the photovoltaic string;
establishing, by the primary monitoring apparatus, an information table according to the communication address of each module voltage monitoring apparatus and the physical location of the module corresponding to each module voltage monitoring apparatus; and
performing module abnormality detection according to the information table, the information table comprising at least a correspondence between the communication address of each module voltage monitoring apparatus and the physical location of the module corresponding to each module voltage monitoring apparatus, the module voltage monitoring apparatus and the module in the photovoltaic string corresponding one-to-one to each other, a module at an odd-number physical location in the photovoltaic string and the module voltage monitoring apparatus corresponding one-to-one to each other when a quantity of modules in the photovoltaic string is an odd number, or the first module of a positive pole of the photovoltaic string and a module at an even-number physical location corresponding one-to-one to the module voltage monitoring apparatuses when a quantity of modules in the photovoltaic string is an even number.

US Pat. No. 10,171,027

PHOTOVOLTAIC MODULE MOUNT

SunPower Corporation, Sa...

1. A photovoltaic (PV) module coupling, comprising:a body plate having an upper surf ace along a first plane between a first end and a second end;
a retainer extending downward from the second end, wherein the retainer includes a retention surface along a second plane orthogonal to the first plane; and
a toe extending orthogonal to the second plane from the retainer to a terminal edge, the PV module to couple to a module stand, wherein the module stand includes a base portion and an upright extending from the base portion to a support surface, wherein the module stand further includes a locking plate having a locking surf ace coupled to the upright, and wherein the locking plate includes a locking toe slot through the locking surface, wherein the module stand further includes a pair of alignment protrusions extending upward from the support surface, wherein the pair of alignment protrusions define a rail notch between the pair of alignment protrusions and the support surface, and wherein the rail notch is longitudinally aligned with the locking toe slot.

US Pat. No. 10,171,026

STRUCTURAL ATTACHMENT SEALING SYSTEM

Solsera, Inc., Phoenix, ...

1. A method of securing structural attachments comprising the steps of:a. placing a mount on a structure, the mount comprising:
i. a base that conforms to the shape of the surface of the structure, the base comprising an internal cavity further comprising at least one concave section wherein the at least one concave section forms an external cavity, the external cavity further comprising a base;
ii. a port hole coupled to the internal cavity that is accessible from an outer surface of the mount;
iii. a vent coupled to the internal cavity that is accessible from the outer surface of the mount;
iv. a bolt for securing the mount to the structure, the bolt further comprising a head, and a shaft extending from the head;
v. an opening through the external cavity of the at least one concave section, the opening configured to receive the bolt; and
vi. a generally U-shaped guide comprising a pair of vertical members, the vertical members extending from the at least one concave section forming an aperture that is configured to secure a solar panel mounting rail guide to the mount wherein each vertical member further comprising a front side and a rear side;
b. inserting the shaft of the bolt through the opening and through the volume of the internal cavity so that the head resides on the base of the external cavity thereby securing the mount to the structure; and
c. injecting a liquid into the port hole of the mount until the liquid fills the volume of the internal cavity.

US Pat. No. 10,171,025

APPARATUS AND METHOD FOR SOLAR PANEL MODULE MOUNTING INSERTS

LUMETA, LLC, Irvine, CA ...

1. A photovoltaic module, comprisingan upper transparent protective layer;
a photovoltaic layer positioned beneath the upper transparent protective layer, the photovoltaic layer comprising a plurality of electrically interconnected photovoltaic cells disposed in an array;
a rigid substrate layer positioned beneath the photovoltaic layer; and
a plurality of inserts configured to be fixedly attached to (i) a bottom surface of the rigid substrate and (ii) a surface of a roof, the plurality of inserts being disposed in an array, each insert having a substantially triangular-shaped cross section when viewed from a side orthogonal to a line of a roof downward slope, each insert having a thickness to maintain the entire bottom surface of the rigid substrate at about one inch from the surface of the roof, each insert having a thickness in the down-roof direction which is thinner than a thickness in an up-roof direction, at least one insert supporting two adjacent photovoltaic modules.

US Pat. No. 10,171,024

SOLAR ENERGY COLLECTOR

DIVERSIFIED SOLAR SYSTEMS...

1. A solar collector comprising:a frame for supporting a plurality of photovoltaic (PV) panels, wherein the frame is adapted to removably attach to a base;
a first panel assembly, including at least one of the plurality of PV panels, pivotally attached to the frame about a first axis; and
a second panel assembly, including at least one of the plurality of PV panels, pivotally attached to the first panel assembly to collectively move with the first panel assembly about the first axis and to pivot relative to the frame, and to pivot about a second axis that is substantially parallel to and radially offset from the first axis, to move between a deployed position and a retracted position.

US Pat. No. 10,171,023

MOTOR STARTER APPARATUS WITH START-UP FAULT DETECTION CAPABILITY

Eaton Intelligent Power L...

1. An apparatus comprising:at least one semiconductor switch;
at least one current sensor configured to sense a current provided to a load via the at least one semiconductor switch; and
a control circuit configured to cause the at least one semiconductor switch to couple a power source to the load for an interval having a duration of less than one-half of a period of an AC voltage of the power source and to detect a rate of change of the sensed current in response to the coupling.

US Pat. No. 10,171,022

MOTOR DRIVING DEVICE, AN AIR CONDITIONER INCLUDING SAME AND A CONTROL METHOD THEREFOR

SAMSUNG ELECTRONICS CO., ...

1. A motor driving device comprising:a rectifier configured to output an input voltage by rectifying alternating current (AC) power into direct current (DC) power;
a first buck-boost converter configured to convert the input voltage into a DC-link voltage by stepping down the input voltage in a buck mode or stepping up the input voltage in a boost mode;
an inverter configured to convert the DC-link voltage for driving a motor into an AC voltage and transfer the AC voltage to the motor; and
a controller configured to
receive motor information related to driving of the motor,
identify a DC-link voltage for driving the motor according to the motor information,
compare the input voltage with the identified DC-link voltage, to thereby produce a comparison result, and
based on the comparison result, control the first buck-boost converter to operate one of the buck mode and the boost mode for converting the input voltage into the identified DC-link voltage by switching one of a plurality of switches included in the first buck-boost converter,
wherein the controller is configured to
compare an instantaneous value of the input voltage with the identified DC-link voltage,
in response to the instantaneous value of the input voltage being larger than the identified DC-link voltage, control the first buck-boost converter to operate in the buck mode, and
in response to the instantaneous value of the input voltage being smaller than the identified DC-link voltage, control the first buck-boost converter to operate in the boost mode.

US Pat. No. 10,171,021

METHODS FOR DETERMINING A VOLTAGE COMMAND

GM GLOBAL TECHNOLOGY OPER...

1. A method comprising:providing a system with an electric machine that operates in response to a voltage command;
determining, based on characteristics of the system, a minimum voltage for the voltage command;
operating the electric machine only at or above the minimum voltage;
determining, based on capabilities of the system, a maximum voltage for the voltage command;
operating the electric machine only at or below the maximum voltage;
determining, by testing the system, a first representation of a first performance curve for the electric machine corresponding to the minimum voltage;
determining, by testing the system, a second representation of a second performance curve for the electric machine corresponding to the maximum voltage;
obtaining, by a controller and in response to a required torque and a required speed for the electric machine, an operating point of the electric machine to be achieved through the voltage command;
evaluating, by the controller, whether the operating point lies between the first and second representations;
when the operating point lies between the first and second representations, determining, by the controller, a magnitude of the voltage command, by evaluating which of a plurality of voltages corresponding to a third performance curve falling between the first and second representations is most efficient in operating the electric machine at the operating point;
supplying, by a power supply controlled by the controller and to the electric machine, the voltage command at the magnitude; and
operating the electric machine using the voltage command.