US Pat. No. 10,142,179

SELECTING RESOURCES FOR AUTOMATIC MODELING USING FORECAST THRESHOLDS

CA, Inc., New York, NY (...

1. A method, comprising:retrieving capacity utilization data for a plurality of resources;
applying a linear regression analysis on the capacity utilization data;
projecting, using a processor, the capacity utilization data through a future time based on results of the linear regression analysis;
determining a deviation from a predetermined threshold range in the projected capacity utilization data for a first resource on a host, wherein the first resource is a virtual processor;
in response to determining the deviation, automatically selecting a plurality of alternative resource configurations for the plurality of resources based on predefined resource templates that specify resource options available for the alternative resource configurations, wherein each of the alternative resource configurations is selected based on whether it allocates additional resources to the first resource;
in further response to determining the deviation, automatically determining, for each of the plurality of alternative resource configurations, future capacity utilization of the first resource based on a non-linear capacity consumption model corresponding to the resource configuration, wherein the non-linear capacity consumption model comprises a plurality of resource scores that each characterize a capacity of each resource in the resource configuration to service additional workloads in view of scalability characteristics of a virtual memory and virtual storage I/O on the host in the non-linear capacity consumption model, and wherein the future capacity utilization of the first resource is dependent upon the scalability characteristics of the host virtual memory and virtual storage I/O; and
applying a selected resource configuration from the plurality of alternative resource configurations to the first resource to prevent the first resource from deviating from the predetermined threshold range.

US Pat. No. 10,142,176

UTILIZING REALLOCATION VIA A DECENTRALIZED OR DISTRIBUTED, AGREEMENT PROTOCOL (DAP) FOR STORAGE UNIT (SU) REPLACEMENT

International Business Ma...

1. A storage unit (SU) comprising:an interface configured to interface and communicate with a dispersed or distributed storage network (DSN);
memory that stores operational instructions; and
processing circuitry operably coupled to the interface and to the memory, wherein the processing circuitry is configured to execute the operational instructions to:
based on a change from a first system configuration of a Decentralized, or Distributed, Agreement Protocol (DAP) to a second system configuration of the DAP based on a storage unit to be replaced (SUTBR) within a plurality of storage units (SUs) that includes the SU within the DSN, operate based on the first system configuration of the DAP and service read and write requests from one or more computing devices for at least one encoded data slice (EDS) that is stored within the SU based on the first system configuration of the DAP during transfer of a plurality of EDSs from the SUTBR to a replacement storage unit (RSU) for storage within the RSU, wherein:
the first system configuration of the DAP and the second system configuration of the DAP respectively provide for deterministic calculation of locations of EDS sets that correspond respectively to a plurality of data segments of a data object that are distributedly stored across the plurality of SUs within the DSN;
the data object is segmented into the plurality of data segments, and a data segment of the plurality of data segments is dispersed error encoded in accordance with dispersed error encoding parameters to produce a set of EDSs of the EDS sets that is of pillar width having a plurality of EDS names;
a write threshold number of EDSs of the set of EDSs provides for a successful transfer of the set of EDSs from a first at least one location in the DSN to a second at least one location in the DSN; and
operate based on the second system configuration of the DAP and service other read and write requests from the one or more computing devices for the at least one EDS that is stored within the SU based on the second system configuration of the DAP after the plurality of EDSs have been successfully transferred from the SUTBR to the RSU.

US Pat. No. 10,142,163

BFD OVER VXLAN ON VPC UPLINKS

CISCO TECHNOLOGY, INC, S...

1. A method, comprising:receiving, by a primary virtual port channel (vPC) node, a packet from a remote node;
determining, by the primary vPC node, the packet includes a media access control (MAC) address corresponding to either the primary vPC node or a secondary vPC node and at least one inner packet identifier;
identifying, by the primary vPC node, an access control list (ACL) entry from a set of access control list entries based on the at least one inner packet identifier;
based on an identified access control list (ACL) entry, generating, by the primary vPC node, a copy of the packet; and
based on the determined MAC address and after generating a copy of the packet, transmitting, by the primary vPC node to the secondary vPC node, the packet;
receiving, by the primary vPC node, a second packet;
authorizing, by the primary vPC node in response to determining the secondary vPC node generated a copy of the second packet, receipt of the second packet;
restricting by the primary vPC node in response to determining the secondary vPC node did not generate a copy of the second packet, receipt of the second packet.

US Pat. No. 10,142,154

MINIMIZING INTER-SYMBOL INTERFERENCE IN OFDM SIGNALS

Imagination Technologies ...

1. A method of determining correct path positions of a channel impulse response for a particular Fast Fourier transform (FFT) window position at an orthogonal frequency-division multiplexing receiver, the method comprising:generating a frequency domain representation of pilots in a received pilot-dense symbol of an orthogonal frequency-division multiplexing signal based on the particular FFT window position;
applying each of a plurality of phase rotations to the frequency domain representation of the pilots to generate a plurality of phase rotated frequency domain representations of the pilots;
generating a channel frequency response estimate for each phase rotated frequency domain representation of the pilots;
equalizing the received pilot-dense symbol based on each channel frequency response estimate;
measuring an amount of noise on layer 1 (L1)-pre sub-carriers for each equalized pilot-dense symbol; and
selecting path positions based on the phase rotation associated with the channel frequency response producing the lowest noise on the L1-pre sub-carriers as the correct path positions.

US Pat. No. 10,142,151

PEAK TO AVERAGE POWER RATIO (PAPR) REDUCTION IN A WIRELESS NETWORK

NEWRACOM, INC., Lake For...

1. A method performed by a wireless device, the method comprising:generating a frame including a first field and a second field immediately following the first field; and
transmitting the frame,
wherein the first field is associated with a first set of subcarriers, and a set of tones for channel estimation are transmitted on the first set of subcarriers in the first field,
wherein the second field is associated with a second set of subcarriers, the second set of subcarriers includes the first set of subcarriers and four extra subcarriers, and a first set of four extra tones for channel estimation are transmitted on the four extra subcarriers in the second field,
wherein first, second, third, and fourth values of the first set of four extra tones respectively correspond to Binary Phase Shift Keying (BPSK) constellation values of ?1, ?1, ?1, and +1.

US Pat. No. 10,142,148

METHOD FOR TRANSMITTING FRAME, CLEAR CHANNEL ASSESSMENT METHOD, AND APPARATUS IMPLEMENTING THE SAME METHOD

NEWRACOM, INC., Lake For...

1. A method for transmitting frames of a device in a wireless local area network (WLAN), the method comprising:generating a symbol, the symbol including a data duration and a cyclic prefix prepended to the data duration, in which a plurality of legacy cyclic prefixes are periodically located in the data duration at intervals corresponding to a symbol duration of a Very High Throughput (VHT) symbol; and
transmitting a frame including the symbol,
wherein the length of the data duration is 12.8 microseconds.

US Pat. No. 10,142,145

WIRELESS RECEIVER

Cohda Wireless Pty Ltd., ...

1. A method comprising:receiving, at a first antenna, an observation of a symbol transmitted across a wireless communications channel perceived by the first antenna;
generating a modified observation of the symbol based on a product of the received observation and the complex conjugate of a channel estimate of the channel; and
generating, based on the modified observation and the channel estimate, log-likelihood ratios (LLRs) for the symbol for a maximum-likelihood-based decoder to decode,
wherein generating log-likelihood ratios includes:
generating a LLR associated with a most significant bit of the symbol, and
generating a LLR associated with a next most significant bit of the symbol;
wherein the log-likelihood ratio (LLR) associated with the most significant bit is generated based on the ratio of the real part (yI) or imaginary part (yQ) of the modified observation to Gaussian-distributed noise power of the channel.

US Pat. No. 10,142,142

PHASE NOISE SUPPRESSION

Maxlinear, Inc., Carlsba...

1. A system comprising:a modulator operable to generate a modulated data signal according to a reference signal;
a transmitter circuit operable to generate a combined signal by combining the modulated data signal with a test signal, wherein an amount of whitespace surrounding the test signal is based on a status of a microwave backhaul link, and wherein a nominal frequency of the test signal is based on the status of the microwave backhaul link and the reference signal; and
a control circuit operable to determine the status of the microwave backhaul link according to a determination of a performance metric for the combined signal.

US Pat. No. 10,142,133

SUCCESSIVE SIGNAL INTERFERENCE MITIGATION

Uhnder, Inc., Austin, TX...

1. A radar sensing system for a vehicle, the radar sensing system comprising:a transmitter configured for installation and use on a vehicle, and configured to transmit radio signals;
a receiver configured for installation and use on the vehicle, and configured to receive radio signals that include the transmitted radio signals reflected from objects in the environment;
an interference mitigation processor;
wherein the receiver is configured to process and digitize the received radio signals to produce a sample stream;
wherein the sample stream is provided to the interference mitigation processor;
wherein the interference mitigation processor is configured to successively (i) generate respective signals corresponding to selected signals of the received radio signals that are the transmitted radio signals reflected from respective ones of a selected plurality of objects, and (ii) add the respective signals to the sample stream to form a modified sample stream, and wherein the addition of the respective signals removes from the sample stream those selected signals that are the transmitted radio signals reflected from the selected plurality of objects; and
wherein the receiver is configured to use the modified sample stream to detect a first object at a first range which is more distant than respective ranges of the selected plurality of objects because interfering radio signals, which are the transmitted radio signals reflected from the selected plurality of objects, have been removed from the modified sample stream.

US Pat. No. 10,142,122

USER INTERFACES, SYSTEMS AND METHODS FOR CONFIGURING SMART DEVICES FOR INTEROPERABILITY WITH A SMART HUB DEVICE

GOOGLE LLC, Mountain Vie...

1. A method for commissioning a smart device to a smart home environment, comprising:at a smart home hub in a premise of the smart home environment, the smart home hub having one or more processors and memory storing one or more programs for execution by the one or more processors, wherein the smart home hub is configured to communicate with a client device and a plurality of smart devices in the premise through a plurality of communication networks in the premise:
receiving from the client device over a first communication network of the plurality of communication networks a request to commission a new smart device in the premise to the smart home environment, wherein the new smart device is not associated with the plurality of communication networks in the premise and the request is issued by a client-side application executed by the client device, the client-side application being associated with a user account;
in response to the request to commission the new smart device:
determining using a second communication network of the plurality of communication networks that the new smart device is available for commissioning to the smart home environment, wherein the second communication network is a short range communication network and is distinct from the first communication network;
connecting to the new smart device via the second communication network;
obtaining device information of the new smart device via the second communication network;
causing a notification to be provided to a user concerning association of the new smart device with the user account;
commissioning of the new smart device to the smart home environment, thereby enabling the new smart device to communicate via the first communication network; and
storing the device information at the smart home hub.

US Pat. No. 10,142,117

INFORMATION HANDLING SYSTEM SELECTIVE LOCAL AND REMOTE CHARGER CONTROL

Dell Products L.P., Roun...

1. A portable information handling system comprising:a housing;
a processor disposed in the housing and operable to execute instructions to process information;
a memory disposed in the housing and interfaced with the processor, the memory operable to store the information;
a port disposed at the housing and operable to accept an external cable;
a port controller interfaced with the port and operable to communicate with one or more external devices through the external cable;
a charger interfaced with the port and operable to accept power provided to the port and convert the power to a system voltage;
a switch interfaced with the port to selectively direct the power from the port to one of either the charger or a system bus; and
a power manager interfaced with the port controller and the switch, the power manager comprising one or more processing components executing instructions stored in non-transitory memory to selectively direct the power with the switch based at least in part on information communicated with the one or more external devices through the port;
wherein the information communicated with the one or more external devices comprises an identifier of the information handling system associated with power sink capabilities of the information handling system.

US Pat. No. 10,142,116

INSPECTION DEVICE AND METHOD FOR POWERED DEVICES IN A POWER OVER ETHERNET SYSTEM

IC PLUS CORP., Hsinchu (...

1. An inspection device of power source equipment for detecting a powered device of a power over Ethernet system, wherein the power source equipment comprises a connecting port adapted to connect to the powered device through a network wire, and wherein the inspecting device connects to the connecting port, the inspection device comprising:an inspection computing unit that controls application of a plurality of testing voltage signals to the connecting port, whereas the plurality of testing voltage signals comprise, sequentially, a first voltage V1, a second voltage V2, a third voltage V3 and a fourth voltage V4, wherein the first voltage V1 and the third voltage V3 are substantially the same, the second voltage V2 and the fourth voltage V4 are substantially the same, and an application period for the fourth voltage V4 is a sum of an application period for the second period V2 with an extension period;
a power supply that supplies the plurality of testing voltage signals to the connecting port; and
a current measurement device that measures at the connecting port a first current I1 after a predetermined period following applying the first voltage V1, measures a second current I2 after the predetermined period following applying the second voltage V2, measures a third current I3 after the predetermined period following applying the third voltage V3, and measures a fourth current I4 after a time period, which is longer than the predetermined period, following applying the fourth voltage V4, wherein
the inspection device calculates a first resistance by Rdet1=(V1-V2)/(I1-I2) and a second resistance by Rdet2=(V3-V4)/(I3-I4); and
the inspection device determines that the connecting port is not connected to a suitable powered device if (1) any of the first current I1, the second current I2, the third current I3, and the fourth current I4 exceeds a first predetermined value, or (2) ?Rdet=Rdet1-Rdet2 is greater than a second predetermined value, and otherwise determines that the connecting port is connected to the suitable powered device.

US Pat. No. 10,142,100

MANAGING USER-CONTROLLED SECURITY KEYS IN CLOUD-BASED SCENARIOS

SAP SE, Walldorf (DE)

1. A system comprising:at least one hardware data processor; and
at least one memory storing instructions which, when executed by the at least one data processor, result in operations comprising:
receiving, at a database server and from a client device, a client request for information;
generating, in response to the received client request, a database request to obtain the information;
generating, at the database server, a request for a secret key for decrypting encrypted data to obtain encrypted data associated with the information;
encrypting the request with a public key of a security key management entity associated with the client device and signing the request with a private key associated with the database server;
providing, by the database server, the encrypted and signed request to the security key management entity via a network;
receiving, by the database server, secret key information from the security key management entity via the network;
storing, at the database server, the secret key information in a working memory rather than persisting the secret key information within a long term storage of the database server;
decrypting, at the database server, the encrypted data using the secret key information to form decrypted data responsive to the client request for the information; and
removing, from the database server, the secret key information from the working memory after the secret key information is used to decrypt the encrypted data.

US Pat. No. 10,142,097

SYSTEM FOR SERIALIZING HIGH SPEED DATA SIGNALS

Synopsys, Inc., Mountain...

1. A system for serializing a plurality of intermediate signals including first through fourth intermediate signals, comprising:a first intermediate serializer circuit for receiving a first intermediate clock signal and the first and second intermediate signals, and generating a fifth intermediate signal, wherein the first intermediate serializer circuit receives the first intermediate signal and provides the first intermediate signal as the fifth intermediate signal when the first intermediate clock signal is deactivated, and wherein the first intermediate serializer circuit receives the second intermediate signal and provides the second intermediate signal as the fifth intermediate signal when the first intermediate clock signal is activated, thereby serializing the first and second intermediate signals, and wherein the first intermediate serializer circuit provides the serialized first and second intermediate signals as the fifth intermediate signal responsive to receiving a selected one of an asynchronous enable signal and the first intermediate clock signal;
a second intermediate serializer circuit for receiving a second intermediate clock signal and the third and fourth intermediate signals, and generating a sixth intermediate signal, wherein the first and second intermediate clock signals have a first predetermined phase difference therebetween, wherein the second intermediate serializer circuit receives the third intermediate signal and provides the third intermediate signal as the sixth intermediate signal when the second intermediate clock signal is deactivated, and wherein the second intermediate serializer circuit receives the fourth intermediate signal and provides the fourth intermediate signal as the sixth intermediate signal when the second intermediate clock signal is activated, thereby serializing the third and fourth intermediate signals, and wherein the second intermediate serializer circuit provides the serialized third and fourth intermediate signals as the sixth intermediate signal responsive to receiving a selected one of the asynchronous enable signal and the first intermediate clock signal;
a tri-state circuit for receiving an external signal and an external select signal, and is connected to the first and second intermediate serializer circuits for receiving the fifth and sixth intermediate signals, and generating seventh and eighth intermediate signals, wherein the tri-state circuit provides the fifth and sixth intermediate signals as the seventh and eighth intermediate signals, respectively, when the external select signal is at a first logic state and the external signal as the seventh and eighth intermediate signals when the external select signal is at a second logic state;
a first output serializer circuit for receiving the seventh and eighth intermediate signals and a first output clock signal, and generating a first serialized signal, wherein the first output serializer circuit provides the seventh intermediate signal as the first serialized signal when the first output clock signal is deactivated and the eighth intermediate signal as the first serialized signal when the first output clock signal is activated, and wherein a frequency of each of the first and second intermediate clock signals is half of a frequency of the first output clock signal, thereby serializing the first through fourth intermediate signals, and wherein the first output serializer circuit provides the serialized seventh and eighth intermediate signals as the first serialized signal responsive to receiving a selected one of the asynchronous enable signal and the first output clock signal; and
a second output serializer circuit for receiving inverted fifth and sixth intermediate signals and a second output clock signal, and generating a second serialized signal, wherein the second output serializer circuit provides the inverted fifth intermediate signal as the second serialized signal when the second output clock signal is deactivated, wherein the second output serializer circuit provides the inverted sixth intermediate signal as the second serialized signal when the second output clock signal is activated, and wherein a phase and a frequency of the second output clock signal is equal to a phase and a frequency of the first output clock signal, thereby serializing the inverted fifth and sixth intermediate signals, and wherein the second output serializer circuit provides the serialized inverted fifth and sixth intermediate signals as the second serialized signal responsive to receiving a selected one of the asynchronous enable signal and the second output clock signal.

US Pat. No. 10,142,095

TIMING FOR IC CHIP

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit (IC) chip comprising:a synchronization input;
a root timer that generates a frame pulse based on a start trigger signal;
a hardware clock control that provides a clock signal based on a selected one of the frame pulse and a synchronization signal provided from one of the root timer and another IC chip, the hardware clock control including:
a clock selector having a first input coupled to an output of the root timer, a second input coupled to the synchronization input of the IC chip, and an output; and
circuitry having an input coupled to the output of the clock selector and having an output configured to output the clock signal, the IC chip further comprising:
a plurality of analog to digital converters (ADCs) coupled to the output of the circuitry in the hardware clock control, each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.

US Pat. No. 10,142,093

FAST CLOCK AND DATA RECOVERY FOR FREE-SPACE OPTICAL COMMUNICATIONS

X Development LLC, Mount...

1. A method comprising:receiving, at a first communication terminal, an optical signal containing an incoming stream of data from a second communication terminal, the first communication terminal having a clock and data recovery circuit operable in a normal mode to synchronize a recovered clock with the incoming data stream for recovering data from the optical signal;
determining, by control hardware of the first communication terminal, a receiving power for the optical link based on the optical signal, the control hardware implementing the clock and data recovery circuit;
comparing, by the control hardware, the receiving power to a first receiving power threshold; and
when the receiving power for the optical link is less than the first receiving power threshold, transitioning, by the control hardware, the clock and data recovery circuit from the normal mode to a holdover mode, the clock and data recovery circuit, when operating in the holdover mode, configured to hold the recovered clock to a known-good clock frequency.

US Pat. No. 10,142,086

REPEATER AND METHODS FOR USE THEREWITH

1. A repeater device, comprising:an amplifier configured to amplify first channel signals and a reference signal to generate amplified first channel signals and an amplified reference signal, wherein the first channel signals and reference signal are extracted from a distributed antenna system;
a first transceiver configured to select one or more of the amplified first channel signals via channel selection filtration and to convert the one or more of the amplified first channel signals to a spectral segment for wireless transmission to at least one device via a first antenna of the distributed antenna system based on the amplified reference signal, wherein the amplified reference signal reduces a phase error in converting the one or more of the amplified first channel signals to the spectral segment;
a second transceiver; and
a duplexer configured to transfer at least a portion of the amplified first channel signals to the second transceiver for transmission to an other repeater device of the distributed antenna system having a second antenna and further to transfer the first channel signals to the first transceiver.

US Pat. No. 10,142,082

PRE-CODING IN OFDM

Genghiscomm Holdings, LLC...

1. A method employed by a radio transceiver, comprising:selecting a data symbol block comprising a plurality N of data symbols;
spreading the data symbol block to produce N spread symbols, wherein each spread symbol is expressible by
wherein wm is an mth one of the N spread symbols, ?m is an mth complex-valued scaling factor, sn is an nth one of the plurality N of data symbols, e is natural log, i=??1, ? is mathematical constant Pi, m and n are indices each having integer values of 0 to N?1, e?i2?mn/N expresses elements of a Discrete Fourier Transform (DFT) spreading matrix, and N is equal to a number of Orthogonal Frequency Division Multiplexing (OFDM) subcarriers assigned to the radio transceiver for transmission, where N>2;mapping each of the N spread symbols to one of the OFDM subcarriers; and
impressing each of the N spread symbols onto one of the OFDM subcarriers to generate an OFDM transmission signal comprising a superposition of data-bearing subcarriers, wherein the spreading provides the superposition with a reduced peak-to-average-power ratio.

US Pat. No. 10,142,079

METHOD AND APPARATUS FOR MANAGING CONTENTION WINDOW IN WIRELESS COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method for managing a contention window by a base station in a wireless communication system, the method comprising:transmitting multiple data in a first subframe;
obtaining values of reception result corresponding to the multiple data;
determining a ratio of negative acknowledge (NACK) signals to the values of reception result;
adjusting or maintaining the contention window based on the determined ratio;
setting a value within the contention window as a counter value;
sensing the channel during a first interval to determine whether the sensed channel is idle;
if the channel is idle, reducing the counter value and transmitting data in a second subframe using the channel based on the counter value; and
if the channel is not idle, sensing the channel during a second interval.

US Pat. No. 10,142,078

TRANSMISSION OF ACKNOWLEDGEMENT SIGNALS IN A COMMUNICATION SYSTEM

Samsung Electronics Co., ...

5. The method of claim 1, wherein the first resource is associated with a first resource element from one or more downlink resource elements used for the reception of the first SA.

US Pat. No. 10,142,066

JITTER ANALYSIS SYSTEMS AND METHODS

Keysight Technologies, In...

1. A method comprising:generating a first detection threshold by a decision feedback equalizer, the generating comprising the decision feedback equalizer operating upon at least a first symbol present in an input signal;
detecting at least a first transition in the input signal by utilizing the first detection threshold; and
evaluating one or more timing characteristics of the input signal by evaluating at least the first transition in the input signal.

US Pat. No. 10,142,059

METHOD FOR VERIFYING THE INTEGRITY OF DATA TRANSMISSION BETWEEN A MAIN UPSTREAM UNIT AND A MAIN DOWNSTREAM UNIT

1. Method for verifying the integrity of data transmission between a main upstream unit and a main downstream unit, the method being characterized in that it comprises implementing the steps of:(a) Generation, by a data processing module of the main upstream unit, of a first frame comprising a data packet to be transmitted and a cyclic redundancy code of said packet, and transmission to an interface module of the main upstream unit;
(b) Encapsulation, by said interface module of the main upstream unit, of the first frame in a second frame also including a cyclic redundancy code of the first frame;
(c) Transmission of the second frame to interface modules of the main downstream unit and of at least one auxiliary upstream unit;
(d) Extraction of the first frame from the second frame by the interface modules of the main downstream unit and of the at least one auxiliary upstream unit; and transmission to data processing modules of the main downstream unit and of the at least one auxiliary upstream unit;
(e) Extraction of the packet from the first frame by the data processing module of the main downstream unit; and extraction of the cyclic redundancy code of packet by the data processing module of the at least one auxiliary upstream unit;
(f) Encapsulation, by said interface module of the main upstream unit, of the cyclic redundancy code of packet in a third frame;
(g) Transmission of the third frame to the interface module of the at least one auxiliary upstream unit;
(h) Extraction of the cyclic redundancy code of packet from the third frame by the interface module of the at least one auxiliary upstream unit; and transmission to the data processing module of the at least one auxiliary upstream unit;
(i) Comparison by the data processing module of the at least one auxiliary upstream unit of each of the cyclic redundancy codes extracted from the first frame and from the third frame; and confirmation of the integrity of data transmission to the main downstream unit only if comparison is positive.

US Pat. No. 10,142,058

COMMUNICATION DEVICE AND COMMUNICATION METHOD

LSIS CO., LTD., Anyang-s...

1. A communication method for a first communication device transmitting data to a second communication device, the communication method comprising:generating, by a safety unique identifier generation unit of the first communication device, a safety unique identifier (ID) for confirming validity of connection between the first communication device and the second communication device using a unique ID of the first communication device and a unique ID of the second communication device;
calculating by an error detection code calculation unit of the first communication device, a header error detection code for detecting an error of header data using the generated safety unique ID, a sequence number and the header data;
calculating by the error detection code calculation unit of the first communication device, a data error detection code for detecting an error of safety data using the generated safety unique ID, the sequence number and the safety data;
generating by a PDU generation unit of the first communication device, a packet comprising the safety data, the calculated data error detection code, and the calculated header error detection code; and
transmitting by a data transmission unit of the first communication device, the generated packet to the second communication device,
wherein the safety unique identifier is generated by using a source Media Address Control (MAC) address of the first communication device, a source device ID of the first communication device, a destination MAC address of the second communication device and a destination device ID of the second communication device,
wherein the safety data is related to a command field, and
wherein if a value of the command field is a first value, the safety data represents a reset command,
if the value of the command field is a second value, the safety data represents a connection command,
if the value of the command field is a third value, the safety data represents a parameter transmission command, and
if the value of the command field is a fourth value, the safety data represents a data transmission command.

US Pat. No. 10,142,057

METHOD AND DEVICE FOR RECEIVING DATA

LG Electronics Inc., Seo...

1. A method for receiving data in a wireless communication system, the method comprising:receiving, by a wireless device, a code block from one cell among a plurality of configured cells; and
upon detecting a decoding error of the code block, storing, by the wireless device, a part or all of the code block wherein the number of coded bits of the code block stored in the reception buffer is determined based on a maximum modulation order supported by the cell from which the code block is received, and
wherein the plurality of configured cells comprise at least one high order cell supporting a modulation order higher than a reference modulation order and at least one low order cell supporting a modulation order lower than or equal to the reference modulation order.

US Pat. No. 10,142,054

TRANSMISSION APPARATUS, CONTROL METHOD, AND PROGRAM

NEC Corporation, Tokyo (...

1. A transmission apparatus transmitting collection information to a collection apparatus through multiple portable terminals, comprising:a communication unit performing directly wireless communication with a portable terminal;
a collection information acquisition unit acquiring the collection information;
a division transmission unit generating multiple pieces of partial collection information by dividing the collection information, and transmitting pieces of partial collection information being different from each other to the multiple portable terminals using the communication unit;
a redundancy transmission unit transmitting same collection information to the multiple portable terminals using the communication unit;
an index value acquisition unit acquiring any one or two of a reliability index value and a capacity index value for the portable terminal, the reliability index value indicating reliability of communication being performed between the portable terminal and the transmission apparatus, the capacity index value indicating capacity of the portable terminal; and
a transmission control unit selecting either of the division transmission unit or the redundancy transmission unit, based on any one or two of the reliability index value and the capacity index value of the portable terminal, and causing the selected unit to perform the transmission of the collection information.

US Pat. No. 10,142,052

METHODS AND APPARATUS FOR COMMUNICATION OVER AN ISOLATION BARRIER WITH MONITORING

Allegro MicroSystems, LLC...

1. A method, comprising:receiving an input data stream having first and second states;
generating a first pulse train type for the first state;
generating a second pulse train type for second state, wherein the first and second pulse train types comprise different characteristics;
transmitting the first and second pulse train types across a voltage barrier of a digital signal isolator;
receiving pulses for the transmitted first and second pulse train types from the voltage barrier;
demodulating the first and second pulse trains types to recover the input data stream in an output data stream;
setting a signal integrity timeout to detect a lack of pulses received or transmitted for the first and second pulse train types corresponding to a fault condition; and
recovering from a glitch on the received pulses using one of the received refresh pulses.

US Pat. No. 10,142,050

ENCODING MODULATION METHOD AND TRANSMITTER

1. An encoding modulation method, comprising:performing a process of oversampling and noise-shaping for received multi-bit data to obtain N-bit data;
looking up a table to obtain a pulse modulation signal of a Pulse Width Modulator, PWM, according to the N-bit data used as an address of the lookup table;
multiplexing In-phase Quadrature, IQ, complex data of the pulse modulation signal of the PWM to be a stream of real number signal data to realize up-conversion transformation with a quarter of a sampling rate;
converting the multiplexed real number signal data to an analog signal and performing power amplification on the analog signal to output, and
wherein, N is an integer of which a number of bits is smaller than that of the received multi-bit data.

US Pat. No. 10,142,047

OPTICAL TRANSMISSION APPARATUS AND OPTICAL TRANSMISSION METHOD

FUJITSU LIMITED, Kawasak...

1. An optical transmission apparatus, comprising:a receiver configured to receive a wavelength division multiplexing optical signal including a first optical signal modulated based on a first modulation system and a second optical signal modulated based on a second modulation system with a higher multi-level degree than the first modulation system;
a wavelength selective switch configured to attenuate power of the first optical signal to a first level and attenuate power of the second optical signal to a second level lower than the first level;
an optical amplifier configured to amplify the wavelength division multiplexing optical signal including the first optical signal and the second optical signal output from the wavelength selective switch; and
a transmitter configured to transmit the wavelength division multiplexing optical signal amplified by the optical amplifier.

US Pat. No. 10,142,044

MANAGED TIMING ENGINE

QULSAR, INC., San Jose, ...

1. A method, comprising operating a managed timing engine that providesa physical-layer timing output aligned to a physical-layer input timing reference using a phase locked loop, the physical-layer input timing reference selected from a multiplicity of physical-layer input timing references, and
a packet-based clock providing timing outputs synchronized to a packet-layer input timing reference,
wherein the managed timing engine has programmable multipier ratios for each of the physical-layer references,
wherein a time-stamping clock in the packet-based clock is derived from a physical-layer clock,
wherein the packet-based clock timing outputs include a 1-PPS signal with a programmable delay offset and
wherein at least one of the multiplicity of physical-layer input timing references that are not selected is measured against the physical-layer input timing reference that is selected using a digital phase lock loop where divider and multiplier factors are chosen to generate two nominal comparison frequency versions that are compared using a clock phase comparator and a phase differences signal is filtered to generate a correction term for a programmable multiplier.

US Pat. No. 10,142,043

TIME DIFFERENTIAL DIGITAL CIRCUIT

VIAVI SOLUTIONS INC., Mi...

1. A time differential digital circuit comprising:a synchronization pattern generator to generate synchronization bit pattern;
a first input to receive the synchronization bit pattern or a first change in the synchronization bit pattern;
a second input to receive the synchronization bit pattern or a second change in the synchronization bit pattern;
a bit pattern detector to:
detect the first change in feedback of the synchronization bit pattern at the first input caused by a first event signal, and generate a first timestamp of the detected first change at the first input; and
detect the second change in the feedback of the synchronization bit pattern at the second input caused by a second event signal, and generate a second timestamp of the detected second change at the second input; and
a differential time detector to determine, based on the first and second timestamps and delays associated with delay paths for the first and second inputs, a time difference between receiving the first and second event signals.

US Pat. No. 10,142,042

METHOD AND SYSTEM FOR A DISTRIBUTED RECEIVER

Radioxio, LLC, Saint Pau...

1. A first semiconductor die comprising:an interface receiver circuit operable to:
receive an externally-generated signal that carries decision outputs of a symbol de-mapper that is external to the first semiconductor die, the externally-generated signal comprising a plurality of time stamps, each one of the plurality of time stamps corresponding to one of the decision outputs of the symbol de-mapper, and
process the externally-generated signal to recover the decision outputs of the symbol de-mapper carried in the externally-generated signal; and
a demodulation circuit operable to recover one datastreams based on the decision outputs of the symbol de-mapper.

US Pat. No. 10,142,041

HOMODYNE RECEIVER CALIBRATION

Telefonaktiebolaget LM Er...

1. A method for calibrating a homodyne receiver in a signal distribution network for time division duplex, the method being performed by a baseband calibration module, the method comprising:acquiring a transmission signal being input to a homodyne transmitter of the signal distribution network;
acquiring, from a heterodyne transmitter observation receiver of the signal distribution network, a first received version of said transmission signal;
acquiring, from a homodyne receiver of the signal distribution network, a second received version of said transmission signal; and,
calibrating the homodyne receiver using a comparison of said first received version of said transmission signal and said second received version of said transmission signal, using said first received version of said transmission signal as a reference signal, and using said transmission signal as a calibration signal.

US Pat. No. 10,142,038

MIMO SIGNAL GENERATOR WITH FREQUENCY MULTIPLEXING

1. A MIMO signal generator, adapted to generate a MIMO signal, comprising:a signal generator, a signal divider, and a frequency shifter,
wherein the signal generator is adapted to generate a plurality of frequency shifted partial MIMO signals within a first signal generator output signal, the plurality of frequency shifted partial MIMO signals being arranged on a frequency axis in a non-overlapping manner,
wherein the signal divider is adapted to divide the first signal generator output signal onto a plurality of signal paths,
wherein the frequency shifter is adapted to shift frequencies of the plurality of frequency shifted partial MIMO signals to a joint carrier frequency, resulting in a plurality of partial MIMO signals, forming the MIMO signal, and
wherein the signal generator is adapted arrange the plurality of frequency shifted partial MIMO signals on the frequency axis in the non-overlapping manner, by placing a carrier frequency of all but one of the plurality of frequency shifted partial MIMO signals to different frequencies.

US Pat. No. 10,142,037

MEASUREMENT DEVICE AND MEASUREMENT METHOD

ANRITSU CORPORATION, Kan...

3. A measurement device, comprising:a plurality of measurement means that are respectively connected to a plurality of devices to be measured capable of using a plurality of communication frequency bands, and perform measurements of at least one of transmission characteristics and reception characteristics of the plurality of devices to be measured in parallel using different communication frequency bands,
wherein the communication frequency bands correspond to different channels and/or different communication protocols,
wherein each of the plurality of measurement means comprises:
signal input means for receiving a signal for measuring the transmission characteristics with a frequency in a communication frequency band from each of the plurality of measurement devices, respectively; and
signal output means for outputting a signal for measuring the reception characteristics with a frequency in a communication frequency band to each of the plurality of devices to be measured, respectively,
wherein the measurement device further comprises:
band information storage means for storing information on the communication frequency bands handled by the plurality of signal input means and the plurality of signal output means;
band setting means for setting a communication frequency band handled by the plurality of signal input means and the plurality of signal output means; and
band management means for executing a process of storing information on a communication frequency band handled by the plurality of signal input means and the plurality of signal output means in the band information storage means, and clearing the information on the used communication frequency band from the band information storage means when the plurality of signal input means and the plurality of signal output means end measurement,
wherein the band setting means outputs a use request for use of the signal input means or the signal output means, and a communication frequency band desired to be used, to the band management means,
wherein the band management means determines permission or refusal in response to the use request on the basis of the information on the communication frequency band stored in the band information storage means with respect to the band setting means, and
wherein in the plurality of measurement means:
the band information storage means is included in the plurality of measurement means, and includes a plurality of used band information storage means for storing information on a communication frequency band handled by the signal input means and the signal output means of the own measurement means; and
the band setting means is included in the plurality of measurement means, and includes used band setting means for setting the communication frequency band handled by the signal input means and the signal output means of the own measurement means on the basis of information on the communication frequency band stored in the used band information storage means of another measurement means.

US Pat. No. 10,142,032

TEMPERATURE INSENSITIVE DELAY LINE INTERFEROMETER

INPHI CORPORATION, Santa...

1. A photonics optical system comprising:a photonics device with temperature insensitive characteristics comprising:
a first waveguide comprising a first length of a first material characterized by a first group index corresponding to a first phase delay for transferring a first light wave with a first peak frequency at an ambient temperature;
a second waveguide comprising a second length of a second material characterized by a second group index corresponding to a second phase delay for transferring a second light wave with a second peak frequency with a time-delay difference relative to the first light wave at the same ambient temperature;
wherein the first phase delay and the second phase delay are configured to change by a same amount upon any change of the ambient temperature, and the time-delay difference of the first light wave and the second light wave is equal to an inversed value of a free spectral range (FSR) configured to align the first peak frequency and the second peak frequency to two channels in a designated frequency grid; and
a network.

US Pat. No. 10,142,030

M-ARY FREQUENCY PRESENCE MODULATION COMMUNICATION SYSTEM AND METHOD

BOOZ ALLEN HAMILTON INC.,...

1. An optical communication system, comprising:a data transmitter including:
at least one optical emission device configured to output light energy as an optical beam having an operating bandwidth,
a beam divider to receive and divide the operating bandwidth of the optical beam into bandwidth portions of plural communication bands,
a focusing grating, and
a digital mirror array having a plurality of digital mirrors,
wherein in an imaging mode, the optical communication system is configured to perform hyperspectral imaging by setting all of the plurality of digital mirrors to positions that transmit all wavelengths of a communication band among the plural communication bands to the focusing grating;
a frequency presence modulation unit that includes the digital mirror array, the focusing grating, a grating, a focusing mirror, and a detector; and
a controller for providing a control signal to the frequency presence modulation unit to control the positions of the plurality of digital mirrors.

US Pat. No. 10,142,029

DEVICE FOR MODULATING THE INTENSITY OF AN OPTICAL SIGNAL ON FOUR DIFFERENT LEVELS

1. Device for modulating the intensity of an optical signal on four different levels, wherein the device comprises:a power divider comprising an input to receive an initial optical signal to be modulated and first and second outputs which each deliver, respectively, first and second optical signals to be modulated, the intensity of each of these first and second optical signals to be modulated being equal to a non-zero fraction of the intensity of the initial optical signal received on the input of the power divider,
a first resonant ring modulator comprising:
an input port optically coupled to the first output of the power divider to receive the first optical signal to be modulated,
a first output port configured to deliver a first intensity-modulated optical signal, constructed by modulating the intensity of the optical signal received on the input port between only a high level and a low level,
a control port configured to receive a first binary control signal in response to which the first resonant ring modulator varies the intensity of the first optical signal to be modulated between the high and low levels to obtain the first modulated optical signal,
a second output configured to deliver an optical signal complementary to the first modulated optical signal, the intensity of the complementary optical signal being at the low level when the intensity of the first modulated optical signal is at the high level and vice versa,
second resonant ring modulator comprising:
an input port optically coupled to the second output of the power divider to receive the second optical signal to be modulated,
an output port configured to deliver a second modulated optical signal constructed by modulating the intensity of the optical signal received on its input port between only a high level and a low level,
a control port configured to receive a second binary control signal in response to which the second resonant ring modulator varies the intensity of the optical signal received on its input port between the high and low levels to obtain the second modulated optical signal,
a first optical assembler comprising:
a first input optically coupled to one of the first and second output ports of the first resonant ring modulator to receive the first modulated optical signal,
a second input optically coupled to the output port of the second resonant ring resonator modulator to receive the second modulated optical signal, and
an output configured to generate a first combined optical signal constructed by combining optical signals received on the first and second inputs of the first optical assembler,
a second optical assembler comprising:
a first input optically coupled to the output port of the first optical assembler
a second input optically coupled to the other of the first and second output ports of the first resonant ring modulator, and
an output configured to deliver the optical signal of which the intensity is modulated on at most four different levels constructed by combining optical signals received on its first and second inputs.

US Pat. No. 10,142,027

COMMUNICATION DEVICE AND COMMUNICATION SYSTEM

Sony Corporation, Tokyo ...

1. A communication device comprising:a first terminal that outputs a power supply voltage;
a second terminal coupled directly or indirectly to the first terminal;
a communication section that operates on a basis of the power supply voltage to communicate with a communication peer;
a communication controller that sets the communication section to be in an ON state or in an OFF state on a basis of a voltage on the second terminal; and
a switch inserted between the first terminal and the second terminal, the switch being turned into an ON state to cause the second terminal to be coupled to the first terminal.

US Pat. No. 10,142,018

VISIBLE LIGHT COMMUNICATION VIA SOLID STATE LIGHTING DEVICES

Cree, Inc., Durham, NC (...

1. A solid-state lighting fixture comprising:a first plurality of solid-state light elements configured to emit visible light at a first wavelength;
a second plurality of solid-state light elements configured to emit the visible light at a second wavelength, which is different than the first wavelength; and
a light controller modulator configured to simultaneously:
modulate the visible light emitted from the first plurality of solid-state light elements, to emit a modulation pattern of the emitted visible light that communicates a first subset of data while being undetectable to a human eye; and
modulate the visible light emitted from the second plurality of solid-state light elements, to emit the modulation pattern of the emitted visible light that communicates a second subset of data while being undetectable to the human eye.

US Pat. No. 10,142,015

METHOD AND APPARATUS FOR DETECTING SHARED RISK LINK GROUPS

Alibaba Group Holding Lim...

2. A method of detecting shared risk link groups, the method comprising:injecting probe beams into a first test link and a second test link;
receiving a first backlight and a second backlight of the probe beams back from the first test link and the second test link, respectively;
filtering the first backlight with a first polarizer such that light with a first designated direction can pass through the first polarizer, and filtering the second backlight with a second polarizer such that light with a second designated direction can pass through the second polarizer;
detecting and recording a first time-varying response of a power level of the light that passes through the first polarizer, and detecting and recording a second time-varying response of a power level of the light that passes through the second polarizer;
calculating a resemblance value for the first time-varying response and the second time-varying response by:
associating the first and second time-varying responses with a timeline, transforming the timeline into a series of discrete time points, and associating a first power value from the first response and a second power value from the second response with each discrete time point; and
calculating the resemblance value from the first power value and the second power value associated with each discrete time point; and
determining, based on the resemblance value, whether the first test link and the second test link are located in a same shared risk link group.

US Pat. No. 10,142,012

CO-ORBITING LASER COMMUNICATIONS RELAY SATELLITE

THE AEROSPACE CORPORATION...

1. A relay satellite for relaying data from a client satellite to thereby reduce power and pointing accuracy requirements of the client satellite, said relay satellite comprising:a short-range communications link configured to receive data from the client satellite; and
a long-range communications link configured to retransmit the received data to a ground station or another satellite,
wherein the relay satellite is deployed in one of (a) a quasi-orbit with respect to the client satellite such that the relay satellite and the client satellite can be kept within a pre-determined distance or (b) the same orbit as the client satellite but with an in-track offset that keeps the relay satellite and the client satellite within a pre-determined distance;
wherein the short-range communications link can be used to receive data from the client satellite when the client satellite is within a pre-determined distance of the relay satellite;
wherein the relay satellite is deployable from the client satellite after the client satellite reaches orbit.

US Pat. No. 10,142,010

REPEATER AND METHODS FOR USE THEREWITH

1. A repeater device, comprising:an amplifier configured to amplify first channel signals to generate amplified first channel signals, wherein the first channel signals are extracted via a first coupler from a first transmission medium of a distributed antenna system as first guided electromagnetic waves, wherein the first guided electromagnetic waves propagate along the first transmission medium without requiring an electrical return path;
a channel selection filter configured to select one or more of the amplified first channel signals for wireless transmission to at least one device via a first antenna of the distributed antenna system; and
a channel duplexer configured to transfer to the distributed antenna system via a second coupler, at least a portion of the amplified first channel signals for use by an other repeater device of the distributed antenna system having a second antenna and further to transfer the first channel signals to the channel selection filter, wherein the second coupler launches second guided electromagnetic waves conveying the amplified first channel signals on a second transmission medium of the distributed antenna system and wherein the second guided electromagnetic waves propagate along the second transmission medium without requiring an electrical return path.

US Pat. No. 10,142,001

METHOD AND SYSTEM FOR HYBRID RADIO FREQUENCY DIGITAL BEAMFORMING

Maxlinear, Inc., Carlsba...

1. An electronic device, the device comprising:one or more circuits coupled to an antenna array comprising antennas arranged along first and second directions, said one or more circuits being operable to:
beamform signals in an analog domain along the first direction of the antenna array; and
beamform signals in a digital domain along the second direction of the antenna array, with wider beam steering in the second direction as compared to narrower beam steering in the first direction.

US Pat. No. 10,141,999

REFERENCE SIGNAL TRACKING IN A WIRELESS COMMUNICATION SYSTEM

TELEFONAKTIEBOLAGET LM ER...

1. A method performed by network equipment in a wireless communication system, the method comprising:transmitting a tracking process base signal to a wireless device;
responsive to receiving a report from the wireless device indicating reception of the tracking process base signal, configuring the wireless device with a tracking process for the wireless device to track a reference type signal by tuning a receiver configuration with which the wireless device received the tracking process base signal; and
transmitting a reference signal to the wireless device and identifying to the wireless device that the reference signal is to be tracked with the configured tracking process.

US Pat. No. 10,141,997

POWER AMPLIFIER ADJUSTMENT FOR TRANSMIT BEAMFORMING IN MULTI-ANTENNA WIRELESS SYSTEMS

Marvell World Trade Ltd.,...

1. A method, comprising:applying, at one or more integrated circuits, one or more beamsteering matrices to one or more signals to produce a plurality of signals to be transmitted via multiple antennas;
after applying the one or more beamsteering matrices to the one or more signals, providing the plurality of signals to a plurality of power amplifiers coupled to the multiple antennas;
determining, at the one or more integrated circuits, signal energies for the plurality of signals provided to the plurality of power amplifiers;
determining, at the one or more integrated circuits, a highest signal energy among the determined signal energies;
determining, at the one or more integrated circuits, respective measures of relative signal energies corresponding to one or more other signal energies among the determined signal energies relative to the determined highest signal energy; and
adjusting, based on the determined respective measures of relative signal energies, output power levels of the plurality of power amplifiers to make the output power levels of the plurality of power amplifiers equal.

US Pat. No. 10,141,990

METHOD FOR DETERMINING PRECODING MATRIX INDICATOR, USER EQUIPMENT, AND BASE STATION

HUAWEI TECHNOLOGIES CO., ...

1. A method for determining a precoding matrix indicator, comprising:receiving a first reference signal set sent by a base station, wherein the first reference signal set is associated with a user equipment-specific matrix set that includes at least two matrices;
selecting a precoding matrix based on the first reference signal set, wherein the precoding matrix w is a product of two matrices W1 and W2, wherein W=W1W2;
wherein the matrix W1 is a block diagonal matrix that comprises at least two block matrices, each block matrix X is a function of matrix A in the user equipment-specific matrix set or matrix B in the user equipment-specific matrix set, wherein the Matrix W2 is used for selection or weighted combination of column vectors in the matrix W1, wherein the precoding matrix w has the following matrix structure:

wherein []T is a matrix transpose, both M and N are positive integers, and ?, ? and ? are phase shifts; and
sending a precoding matrix indicator (PMI) to the base station, wherein the PMI corresponds to the selected precoding matrix.

US Pat. No. 10,141,983

METHOD FOR ACTIVATING PSCELL AND SCELL IN MOBILE COMMUNICATION SYSTEM SUPPORTING DUAL CONNECTIVITY

Samsung Electronics Co., ...

1. A method of a user equipment (UE), the method comprising:receiving, from a first base station, a first message for requesting UE capability information; and
transmitting, to the first base station, a second message including the UE capability information, the UE capability information including information on band combinations supported by the UE and information on each of at least one band combination among the band combinations including first information indicating that the UE supports a dual connectivity for each of the at least one band combination,
wherein the at least one band combination is used to configure a cell associated with a second base station and a cell associated with the first base station for the UE, and
wherein the first information includes second information indicating that the UE supports asynchronous dual connectivity.

US Pat. No. 10,141,980

WIRELESS POWER TRANSMISSION SYSTEM, AND COMMUNICATION AND PROTECTION METHODS FOR THE SAME

MINEBEA MITSUMI INC., Na...

1. A wireless power transmission system comprising a power supply device and a power receiving device,the power supply device comprising:
a power supply coil wirelessly transmitting electric power;
an inverter driving the power supply coil;
a first radio unit performing radio communication with the power receiving device; and
a first processor controlling the first radio unit and the inverter, and
the power receiving device comprising:
a resonant circuit including a power receiving coil wirelessly receiving electric power from the power supply coil of the power supply device and a capacitor to generate a resonant voltage;
a rectifying circuit rectifying the resonant voltage to output a rectified voltage;
a second radio unit performing radio communication with the first radio unit included in the power supply device; and
a second processor controlling the second radio unit,
wherein the second processor transmits a communication packet to the power supply device in a predetermined period of time, the communication packet including information about a rectified voltage value generated based on the rectified voltage and a circulation index value indicating transmission sequence and
the first processor outputs a signal according to the rectified voltage value included in the communication packet every time the first processor receives the communication packet without delay.

US Pat. No. 10,141,972

TOUCH SCREEN CONTROLLER FOR INCREASING DATA PROCESSING SPEED AND TOUCH SYSTEM INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A touch screen controller (TSC) comprising:a front end circuit configured to send a control signal to a touch panel and to receive a touch signal from the touch panel;
an algorithm processing circuit configured to process source data generated based on the touch signal according to a predetermined algorithm;
a memory configured to store the source data and result data obtained as a result of processing the source data at the algorithm processing circuit; and
a bus configured to transfer data among the front end circuit, the algorithm processing circuit, and the memory,
wherein the algorithm processing circuit comprises:
a buffer configured to temporarily store the source data or the result data and shared by at least two circuits; and
a special function register (SFR) configured to store a setting value necessary for an operation of the algorithm processing circuit,
wherein the buffer comprises a source buffer configured to store the source data; and
wherein the algorithm processing circuit is configured to continuously read the source data from the memory during a plurality of cycles of an operating clock signal in a burst mode or a continuous single mode, and to store the source data in the source buffer.

US Pat. No. 10,141,968

DEVICE FOR REFLECTING, DEFLECTING, AND/OR ABSORBING ELECTROMAGENTIC RADIATION EMITTED FROM AN ELECTRONIC DEVICE AND METHOD THEREFOR

ROWTAN TECHNOLOGIES, LLC,...

1. A device for deflecting radio frequency (RF) radiation away from a user of a mobile phone comprising:a metallic plate configured to be positioned between the mobile phone and at least one of a decorative or protective cover, the metallic plate positioned over a rear surface of the mobile phone, wherein the metallic plate is removable and non-permanently attached to the mobile phone and the at least one of a decorative or protective cover and wherein the metallic plate includes:
a copper plate; and
a powder coating formed over the copper plate.

US Pat. No. 10,141,967

VIRTUAL NETWORK INTERFACE CONNECTIVITY

Ford Global Technologies,...

1. A system comprising:a mobile device programmed to
receive a message from a vehicle computing platform via remote process communication (RPC),
update an origin address of the message to indicate the mobile device,
send the message to a destination address of the message,
receive a response message from the destination,
update a destination address of the response message to indicate the computing platform, and
send the response message to the computing platform via the RPC.

US Pat. No. 10,141,961

PASSIVE INTERMODULATION CANCELLATION

NanoSemi, Inc., Waltham,...

1. A method for enhancing a received signal to remove distortion components of a concurrently transmitted signal, the method comprising:receiving a reference signal corresponding to a transmit signal transmitted in a radio frequency transmission band;
receiving via receiving circuitry a received signal acquired in a radio frequency reception band concurrently with transmission of the transmit signal in the transmit frequency band, wherein the received signal includes a distortion component of the transmit signal, and wherein the transmit frequency band and the receive frequency band are non-overlapping bands;
upsampling the reference signal to yield an upsampled transmit signal, and upsampling the received signal to yield an upsampled received signal, wherein the upsampled reference signal and the upsampled received signal have a same sampling rate, and wherein a relative frequency between the upsampled reference signal and the upsampled received signal matches a relative frequency between the transmit frequency band and the receive frequency band;
passing the upsampled reference signal to a configurable predictor configured with predictor parameters, the configurable predictor providing an upsampled distortion signal determined from the upsampled reference signal as input;
downsampling the upsampled distortion signal to yield a distortion signal;
enhancing the received signal using the distortion signal by removing components from the received signal corresponding to the distortion signal;
correlating the upsampled distortion signal and the upsampled received signal to determine a relative delay, wherein upsampling the reference signal includes synchronizing the upsampled reference signal and the upsampled received signal according to the relative delay; and
estimating the parameters for the predictor using the upsampled reference signal and the upsampled received signal.

US Pat. No. 10,141,957

RADIO FREQUENCY FRONT END CIRCUITRY WITH REDUCED INSERTION LOSS

Qorvo US, Inc., Greensbo...

1. Circuitry comprising:a primary antenna node and a secondary antenna node;
a first set of input/output nodes, each associated with radio frequency (RF) signals within a first RF frequency band;
a second set of input/output nodes, each associated with RF signals within a second RF frequency band;
a first diplexer configured to separate RF signals within the first RF frequency band from RF signals within a first subset of the second RF frequency band;
a second diplexer configured to separate RF signals within the first RF frequency band from RF signals within a second subset of the second RF frequency band;
switching circuitry coupled between the primary antenna node, the secondary antenna node, the first set of input/output nodes, the second set of input/output nodes, the first diplexer, and the second diplexer; and
means for controlling the switching circuitry configured to cause the switching circuitry to:
in a carrier aggregation mode of operation between RF signals within the first RF frequency band and RF signals within the second RF frequency band, couple at least one of the first set of input/output nodes and at least one of the second set of input/output nodes to one of the primary antenna node and the secondary antenna node via one of the first diplexer and the second diplexer such that an insertion loss due to switching elements in the path between the at least one of the first set of input/output nodes and the primary antenna node is between 0.575 dB and 0.9 dB; and
in a non-carrier aggregation mode of operation, couple at least one of the first set of input/output nodes and the second set of input/output nodes to one of the primary antenna node and the secondary antenna node such that the first diplexer and the second diplexer are bypassed and an insertion loss due to switching elements in the path between the at least one of the first set of input/output nodes and the primary antenna node is between 0.625 dB and 0.9 dB.

US Pat. No. 10,141,955

METHOD AND APPARATUS FOR SELECTIVE AND POWER-AWARE MEMORY ERROR PROTECTION AND MEMORY MANAGEMENT

International Business Ma...

1. A method for providing selective error protection for a memory in a computing system, the method comprising:predicting a number of future errors likely to occur in at least one portion of the memory;
obtaining an active error correcting code (ECC) configuration for the at least one portion of the memory;
determining whether the active ECC configuration is sufficient to correct the number of predicted future errors in the at least one portion of the memory;
at least when the active ECC configuration is insufficient, determining whether data in the at least one portion of the memory is critical to an application running on the computing system;
when the data is not critical, tolerating corruption of the data; and
when the data is critical, determining whether a stronger ECC level is available and, when the stronger ECC level is available, increasing a strength of the active ECC configuration for the at least one portion of the memory.

US Pat. No. 10,141,948

DELTA-SIGMA MODULATOR, ANALOG-TO-DIGITAL CONVERTER AND ASSOCIATED SIGNAL CONVERSION METHOD BASED ON MULTI STAGE NOISE SHAPING STRUCTURE

MediaTek Inc., Hsin-Chu ...

1. A delta-sigma modulator, for digitizing a first stage input, comprising:a first signal converter, comprising:
a first input summer, for summing a first converted output and the first stage input to generate a first delta signal;
a first loop filter, coupled to the first input summer, for filtering the first delta signal to generate a first sigma signal;
a noise shaping quantizer, coupled to the first loop filter, for quantizing the first sigma signal to generate the first converted output, and shaping a first stage quantization error to generate a second stage input, wherein the first stage quantization error is inherent in quantization operation of the noise shaping quantizer, and the first stage input and the second stage input are analog signals;
a second signal converter, for converting the second stage input to a second converted output; and
a digital cancellation logic, coupled to the first input summer, the noise shaping quantizer and the second signal converter for generating a digital output according to the first converted output and the second converted output,
wherein the noise shaping quantizer comprises:
a first inner summer, coupled to the first loop filter, for summing the first converted output and the first sigma signal to generate a first inner summation signal, wherein the first inner summation signal is used as the second stage input;
a noise shaping filter, coupled to the first inner summer, for filtering the first inner summation signal to generate a noise shaped signal;
a second inner summer, coupled to the first loop filter, the noise shaping filter and the first inner summer, for summing the noise shaped signal and the first sigma signal to generate a second inner summation signal; and
a first noise shaping quantizer, coupled to the first inner summer, the second inner summer and the digital cancellation logic, for quantizing the second inner summation signal to generate the first converted output, wherein the first stage quantization error is generated by the first noise shaping quantizer.

US Pat. No. 10,141,945

RADIO FREQUENCY FLASH ADC CIRCUITS

Maxlinear Asia Singapore ...

1. A system, the system comprising:a plurality of capacitors, a first port of each of the plurality of capacitors being operably coupled to a radio frequency (RF) input;
a plurality of resistors, a first port of each of the plurality of resistors being operably coupled to a reference level of a plurality of reference levels, a second port of each of the plurality of resistors being operably coupled to a second port of each of the plurality of capacitors; and
a sampling circuit operably coupled to the second port of each of the plurality of resistors, wherein the sampling circuit is operable to produce a plurality of digital outputs.

US Pat. No. 10,141,944

METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY

MAXLINEAR, INC., Carlsba...

1. A method, comprising:in an electronic device that performs analog-to-digital conversion:
generating a distorted digital signal by sampling an output from a non-linear analog frontend;
generating a corrected digital signal by applying a compensation signal to said distorted digital signal; and
generating said compensation signal according to a non-linearity estimation and a spectral analysis of said corrected digital signal.

US Pat. No. 10,141,943

HIGH SPEED ACQUISITION SYSTEM FOR PHASE LOCKED LOOPS

TELEDYNE DEFENSE ELECTRON...

1. A signal generator, comprising:a voltage window generator to receive an analog frequency select signal from a digital-to-analog converter (DAC) and to generate a first reference threshold voltage and a second reference threshold voltage based on the analog frequency select signal;
a window comparator coupled to the voltage window generator, the window comparator to receive a voltage controlled oscillator (VCO) tuning voltage from a phase locked loop (PLL), receive the first and second reference threshold voltages from the voltage window generator, and generate a first steering current control signal and a second steering current control signal; and
a steering current circuit coupled to the window comparator, the steering current circuit to receive the first and second steering current control signals to control a steering current coupled to a PLL and apply a phase comparator/detector signal to an PLL based on the first and second steering current control signals.

US Pat. No. 10,141,942

APPARATUSES AND METHODS FOR PROVIDING FREQUENCY DIVIDED CLOCKS

Micron Technology, Inc., ...

1. An apparatus, comprising:a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock;
a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock; and
a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks, wherein the third circuit comprises:
a delay circuit configured to delay the first intermediate clock to produce a delayed intermediate clock;
a phase detector configured to compare a phase of the delayed intermediate clock and the second intermediate clock; and
a multiplexer coupled to receive the second and third intermediate clocks, the multiplexer configured to select one of the second and third intermediate clocks responsive, at least in part, to an output from a phase detector, the multiplexer comprising:
a first logic gate including a first input coupled to receive the second intermediate clock;
a first inverter circuit including an output coupled to a second input of the first logic gate;
a second logic gate including a first input coupled to receive the third intermediate clock;
a second inverter circuit including an input coupled to an output of the first inverter circuit and further including an output coupled to a second input of the second logic gate; and
a third logic gate coupled to receive outputs of the first and second logic gates and including an output from which the output clock is provided.

US Pat. No. 10,141,940

FORWARDED CLOCK RECEIVER BASED ON DELAY-LOCKED LOOP

1. A delay-locked loop comprising:a voltage-controlled delay line generating a clock signal; and
a phase detector obtaining a first sample group by sampling a data signal in at least two positions at a unit interval based on the clock signal and a second sample group by sampling the data signal in at least two positions at the unit interval based on the clock signal, wherein a difference between the positions in which the second sample group is obtained and the positions in which the first sample group is obtained is a half of the unit interval,
selecting, for a first mode, the first sample group as an edge sample of the data signal and the second sample group as a data sample of the data signal, and for a second mode, the first sample group as the data sample of the data signal and the second sample group as the edge sample of the data signal, and
controlling the voltage-controlled delay line by toggling between the first mode and the second mode.

US Pat. No. 10,141,937

PULSE-WIDTH MODULATION (PWM) CONTROL LOOP FOR POWER APPLICATION

ANDAPT, INC., San Jose, ...

1. A method comprising:receiving error signals from a signal wrapper of a programmable fabric, wherein the programmable fabric and the signal wrapper are integrated in a programmable logic device (PLD);
looking up one or more lookup tables storing rows of pre-calculated data and obtaining a matching pre-calculated data corresponding to the error signals; and
generating a compensated output signal using the matching pre-calculated data to drive a switch of a power regulator,
wherein the pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper, and
wherein the PLD comprises a high voltage power transistor, and the PLD is configured as the power regulator by configuring the high voltage power transistor, and wherein the compensated output signal is a pulse width of a pulse-width modulation (PWM) signal of a digital filter for driving a switch of the high voltage power transistor.

US Pat. No. 10,141,928

QUANTUM LIMITED JOSEPHSON AMPLIFIER WITH SPATIAL SEPARATION BETWEEN SPECTRALLY DEGENERATE SIGNAL AND IDLER MODES

INTERNATIONAL BUSINESS MA...

1. A system for remotely entangling qubits via measurement, the system comprising:a Josephson parametric converter (JPC);
a first qubit-resonator system connected to the JPC, the first qubit-resonator system including a first qubit coupled to a first readout resonator; and
a second qubit-resonator system connected to the JPC, the second qubit-resonator system including a second qubit coupled to a second readout resonator, wherein the JPC is configured to remotely entangle the first qubit and the second qubit by reading out both the first and the second readout resonators at a frequency X.

US Pat. No. 10,141,925

CIRCUITS AND METHODS FOR STRENGTHENING LOAD TRANSIENT RESPONSE COMPENSATION

WISTRON CORP., New Taipe...

1. A circuit for strengthening load transient response compensation, comprising:a comparator, comparing a system voltage of an electronic device with a reference voltage;
a first MOSFET, coupled to the comparator and a first power supply;
a second MOSFET, coupled to the comparator and a second power supply of the electronic device;
wherein when an external device is connected to the electronic device such that the system voltage is lower than the reference voltage, the comparator outputs a low-level signal and the first MOSFET becomes conductive, so that the external device is powered by the first power supply;
wherein when the system voltage is higher than the reference voltage, the comparator outputs a high-level signal and the second MOSFET becomes conductive, so that the external device is powered by the second power supply; and
wherein the first power supply is a supercapacitor, and when the second MOSFET becomes conductive, the second power supply charges the supercapacitor at the same time.

US Pat. No. 10,141,924

SEMICONDUCTOR CIRCUIT, VOLTAGE DETECTION CIRCUIT, AND VOLTAGE DETERMINATION CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor circuit comprising:a PMOS transistor that includes a first source connected to a power supply, a first drain, and a first gate to which a fixed potential is supplied;
an output circuit that outputs a first output signal, which is a reset signal or a power-on signal, and that outputs a second output signal according to a potential of the first drain;
a first constant current source connected to the first drain; and
a control circuit including an NMOS transistor that includes a second source to which a fixed potential is supplied, a second drain connected to the first drain, and a second gate to which the second output signal from the output circuit is applied,
wherein, according to the second output signal which is output from the output circuit, the control circuit is configured to control the NMOS transistor to increase a reference current flowing in the PMOS transistor such that a threshold voltage of the PMOS transistor increases in a case in which the power supply is in a rising state, and to control the NMOS transistor to decrease the reference current flowing in the PMOS transistor such that the threshold voltage of the PMOS transistor decreases in a case in which the power supply is in a falling state.

US Pat. No. 10,141,914

OSCILLATION CIRCUIT

Kabushiki Kaisha Toshiba,...

1. An oscillation circuit comprising:a delay circuit that includes a first inverter having an input terminal connected to a first node; and
a delay adjustment circuit including a first current supply path and a second current supply path through which the first node is charged in response to an output signal of the delay circuit, wherein,
during charging of the first node, a current with positive temperature characteristics is supplied to the first node through the first current supply path, and a current with negative temperature characteristics is supplied to the first node through the second current supply path, and
the second current supply path includes a source-drain path of an NMOS transistor having a gate to which a bias voltage with negative temperature characteristics is applied.

US Pat. No. 10,141,908

MULTI-DENSITY MIM CAPACITOR FOR IMPROVED PASSIVE ON GLASS (POG) MULTIPLEXER PERFORMANCE

QUALCOMM Incorporated, S...

1. A passive on glass (POG) device, comprising:a spiral inductor comprising a single layer of a plurality of interconnected trace segments; and
a plurality of parallel plate capacitors, each of the plurality of parallel plate capacitors having a dielectric layer between a pair of conductive plates, and each of the plurality of parallel plate capacitors is overlapped by only one of the plurality of interconnected trace segments of the single layer spiral inductor.

US Pat. No. 10,141,905

AMPLIFIER WITH ADJUSTMENT OF THE AUTOMATIC SOUND LEVEL

DEVIALET, Paris (FR)

10. An amplifier for producing a volume gain to at least one audio signal, according to a desired volume gain selected by a user, comprising:a calculator for calculating a standardized total slow sound level from the-at least one audio signal;
a calculator for calculating a maximum slow volume gain and a minimum slow volume gain as the quotient of the product of the desired volume gain by a maximum slow gain, respectively by a minimum slow gain divided by the standardized total slow sound level;
a device for determining a first minimum volume gain out of the desired volume gain and the maximum slow volume gain;
a device for determining a second minimum volume gain out of the desired volume gain multiplied by a maximum volume gain and the minimum slow volume gain;
a device for determining, as a slow volume gain, the maximum of the first and second determined minimum volume gains: and
a calculator for calculating the volume gain according to the slow volume gain.

US Pat. No. 10,141,900

OFFSET TRIMMING FOR DIFFERENTIAL AMPLIFIER

SANDISK TECHNOLOGIES LLC,...

1. An apparatus comprising:a differential amplifier comprising a non-inverting input, an inverting input, and an output coupled to the inverting input via a voltage divider;
a first variable current source coupled to the non-inverting input, such that increasing a current from the first variable current source increases a voltage at the non-inverting input; and
a second variable current source coupled to the inverting input, and to the output via the voltage divider, such that increasing a current from the second variable current source decreases a voltage at the output.

US Pat. No. 10,141,893

INPUT STAGE OF AN AMPLIFIER AND CORRESPONDING AMPLIFIER

Devialet, Paris (FR)

1. An input stage of an amplifier comprising:an input for the digital signal to be converted;
a voltage output for the converted voltage;
a digital-to-analog converter, the input of which forms the input for the digital signal to be converted, the digital-to-analog converter comprising a signal terminal for generating a current;
a resistance for converting the current into a voltage, connected to said voltage output and to a reference potential; and
a current-voltage converter with a voltage output, connected to said signal terminal and to said voltage output, the current-voltage converter comprising a transistor such that the gate of the transistor is connected to a voltage source, the drain of the transistor is connected to a current source and the source of the transistor is connected to said digital-to-analog converter, the current source generating a continuous current,wherein the source of said transistor is exclusively connected to said signal terminal of said digital-to-analog converter and wherein said digital-to-analog converter is able to generate a current comprising a continuous component and a fixed component, the current source being able to provide a current equal to the continuous component of the current generated by said digital-to-analog converter, said digital-to-analog converter being connected between a fixed potential and the source of said transistor.

US Pat. No. 10,141,892

BIAS CIRCUIT FOR SUPPLYING A BIAS CURRENT TO A RF POWER AMPLIFIER

RAFAEL MICROELECTRONICS, ...

1. A bias circuit for supplying a bias current to an RF power amplifier, said bias circuit comprising:a first bipolar transistor having a base terminal, a collector terminal and an emitter terminal, wherein the emitter terminal is electrically coupled to the RF power amplifier;
a first voltage reference circuit for clamping a first terminal of first voltage reference circuit at a first reference voltage, wherein the first terminal of the first voltage reference circuit is electrically coupled to base terminal of the first bipolar transistor through a first resistive component, and a second terminal of the first voltage reference circuit is electrically coupled to a ground; and
a second voltage reference circuit for clamping a first terminal of second voltage reference circuit at a second reference voltage, wherein the first terminal of the second voltage reference circuit is electrically coupled to the first terminal of the first voltage reference circuit transistor through a second resistive component, and a second terminal of the second voltage reference circuit is electrically coupled to the ground;
wherein a first terminal of the second voltage reference circuit is electrically coupled to a voltage supply through a third resistive component so as to generate a bias current to the RF power amplifier through the emitter terminal of the first bipolar transistor;
wherein the first resistive component, the second resistive component and the third resistive component are connected in series one by one in a conductive path connecting the base terminal of the first bipolar transistor to the voltage supply, wherein the second resistive component is located between the first resistive component and the third resistive component in said conductive path.

US Pat. No. 10,141,891

POWER AMPLIFIER WITH SUPPLY SWITCHING

Avago Technologies Genera...

1. A power amplifier, comprising:a gain circuit;
a supply switch circuit configured to:
detect a magnitude of an outgoing broadband communication signal; and
determine whether the magnitude of the outgoing broadband communication signal exceeds a predetermined voltage threshold;
a first bias transformer coupled to a first voltage supply rail and configured to bias the gain circuit with the first voltage supply rail;
a second bias transformer coupled to a second voltage supply rail and configured to bias the gain circuit with the second voltage supply rail; and
a capacitive coupling combiner coupled to the first bias transformer and the second bias transformer and configured to reduce a residual flux change between the first bias transformer and the second bias transformer,
wherein the gain circuit is configured to:
apply a first gain to the outgoing broadband communication signal using a first voltage supply rail when it is determined that the magnitude exceeds the predetermined voltage threshold;
apply a second gain to the outgoing broadband communication signal using a second voltage supply rail when it is determined that the magnitude does not exceed the predetermined voltage threshold, the second voltage supply rail being smaller than the first voltage supply rail; and
produce an output signal from the outgoing broadband communication signal with the applied first gain or the applied second gain,
wherein a current of the outgoing broadband communication signal is switched between the first voltage supply rail and the second voltage supply rail in response to the magnitude being detected by the supply switch circuit.

US Pat. No. 10,141,882

MOTOR HEALTH MONITORING AND MEDICAL DEVICE INCORPORATING SAME

Medtronic MiniMed, Inc., ...

1. A method of detecting degradation in a drive system including a motor, the method comprising:applying a modulated voltage to the motor;
adjusting a duty cycle of the modulated voltage to achieve a commanded rotation of a rotor of the motor; and
identifying a degradation condition based on the duty cycle.

US Pat. No. 10,141,879

MOTOR CONTROL APPARATUS, SHEET CONVEYANCE APPARATUS, DOCUMENT FEEDING APPARATUS, DOCUMENT READING APPARATUS, AND IMAGE FORMING APPARATUS

Canon Kabushiki Kaisha, ...

1. A motor control apparatus to control a motor based on an instructed phase indicating a target phase of a rotor of the motor, the motor control apparatus comprising:a detector configured to detect a driving current flowing through a winding of the motor;
a phase determiner configured to determine a rotation phase of the rotor based on the driving current detected by the detector;
a converter configured to convert a current value in a stationary coordinate system which is detected by the detector into a current value in a rotational coordinate system based on the rotation phase determined by the phase determiner; and
a controller including a first control mode for controlling the driving current in a manner that a magnitude of the driving current detected by the detector becomes a target value set in a manner that a phase deviation between the instructed phase indicating the target phase of the rotor of the motor and the rotation phase determined by the phase determiner is decreased, and a second control mode for controlling the driving current based on a current having a previously determined magnitude,
wherein, in a case where the control mode for controlling the driving current is switched from the second control mode to the first control mode, the target value in the first control mode is set based on a value of a torque current component of the driving current detected by the detector during execution of the second control mode, and
wherein the torque current component corresponds to a current component represented by the rotational coordinate system of the driving current converted by the converter.

US Pat. No. 10,141,875

AIRCRAFT STARTING AND GENERATING SYSTEM

GE Aviation Systems LLC, ...

1. An aircraft starting and generating system, comprising:a starter/generator that includes a main machine, an exciter, and a permanent magnet generator;
an inverter/converter/controller (ICC) having a metal oxide semiconductor field effect transistor (MOSFET)-based bridge configuration that is connected to the starter/generator and that generates alternating current (AC) power to drive the starter/generator in a start mode for starting a prime mover of the aircraft, and that converts AC power, obtained from the starter/generator after the prime mover have been started, to direct current (DC) power in a generate mode of the starter/generator; and
a main bridge gate driver configured to drive the MOSFET-based bridge;
wherein the main bridge gate driver operates to drive the MOSFET-based bridge during start mode using Space Vector Pulse Width Modulation (SVPWM) and during generate mode using reverse conduction based inactive rectification.

US Pat. No. 10,141,869

IMPEDANCE COMPENSATION

DET International Holding...

1. Method for operating a power converter that delivers output current into a grid, including the steps ofa) determining the output current of the power converter,
b) monitoring an output voltage of the power converter;
c) controlling the output current in order to prevent the output voltage from exceeding an output voltage limit,
d) adjusting the output voltage limit to compensate for a voltage variation due to a line impedance of a line between the power converter and the grid, wherein the output voltage limit can be higher than a maximum voltage allowed at the grid without the output voltage exceeding the output voltage limit thereby allowing an efficient use of an available output power of the power converter in a wider operating range.

US Pat. No. 10,141,850

COMPARATOR CIRCUIT, POWER SUPPLY CONTROL IC, AND SWITCHING POWER SUPPLY DEVICE

Rohm Co., Ltd., Kyoto (J...

1. A comparator circuit comprising:a first comparator arranged to compare an input signal with a reference voltage so as to generate a first comparison signal;
a second comparator arranged to compare the input signal with a variable reference voltage so as to generate a second comparison signal;
a variable reference voltage generator arranged to generate the variable reference voltage; and
a logic unit arranged to output one of the first comparison signal and the second comparison signal as a comparison signal, wherein
a response speed of the first comparator is faster than a response speed of the second comparator, and a power consumption of the second comparator is smaller than a power consumption of the first comparator, and wherein
the logic unit outputs the first comparison signal as the comparison signal while controlling the variable reference voltage generator to sweep the variable reference voltage until, as a result of the variable reference voltage crossing the reference voltage and the second comparator responding faster than the first comparator, a logic level of the second comparison signal is switched before a logic level of the first comparison signal is switched, and moves to a state capable of outputting the second comparison signal as the comparison signal after the sweep of the variable reference voltage is completed.

US Pat. No. 10,141,826

LINEAR VIBRATION MOTOR IN WHICH A PRINTED CIRCUIT BOARD HAVING A COIL COUPLED THERETO IS POSITIONED TO COVER THE COIL, SUCH THAT THE COIL DOES NOT DIRECTLY CONTACT A STATOR PART, THEREBY PREVENTING A PHENOMENON THAT THE COIL IS UNWOUND OR DISCONNECTED AND

MPLUS CO., LTD., Suwon-s...

1. A linear vibration motor, comprising:a stator part comprising a magnet;
a vibrator part comprising a coil positioned to face the magnet and a printed circuit board coupled to the coil and accommodated in an internal space of the stator part; and
an elastic member connecting the stator part and the vibrator part to each other,
wherein the printed circuit board has one end coupled to the stator part and the other end coupled to the vibrator part and at least partially covers the coil facing the stator part,
wherein the printed circuit board comprises:
a coupling plate fixed to the stator part;
an elastic part extended from the coupling plate in a spiral direction to have elastic force;
a contact part connected to the elastic part and having an end portion of the coil coupled thereto; and
a disk part connected to the contact part and having the coil coupled thereto,
wherein the coil is coupled to the disk part to be covered with the disk part; and
wherein the stator part corresponding to the disk part is mounted with a first damping member,
wherein the stator part comprises:
a case having the internal space formed therein to accommodate the vibrator part and having an opened one side;
a bracket closing the internal space of the case; and
a second damping member facing the vibrator part and installed on a surface of the case,
wherein the first damping member faces the vibrator part and is installed on a surface of the bracket;
wherein the first damping member and the second damping member are each ring-shaped, are each aligned with the coil, are each spaced apart from the coil and each at least partially overlap the coil in the movement direction, and
wherein the contact part of the printed circuit board is positioned in the outer area of the disk part not to overlap the first damping member.

US Pat. No. 10,141,785

WIRELESS POWER TRANSMISSION APPARATUS AND WIRELESS POWER TRANSMISSION METHOD

Wilus Institute Of Standa...

1. A wireless power transmitting method of a wireless power transmitting apparatus,wherein a standby state of determining whether at least one wireless power receiving apparatus is positioned within a wireless charge range of the wireless power transmitting apparatus and a power transfer state of transmitting power to the corresponding wireless power receiving apparatus when at least one wireless power receiving apparatus is detected in the standby state are provided, and
the standby state includes a first standby state of periodically transmitting a weak detector signal and a strong detector signal and a second standby state in which at least one of a transmission period of the weak detector signal and a transmission period of the strong detector signal is different from that of the first standby state, the method comprising:
determining any one state of the first standby state and the second standby state of the wireless power transmitting apparatus; and
transmitting the weak detector signal and the strong detector signal based on the determined standby state,
wherein the transmission period of the weak detector signal in the second standby state is longer than the transmission period of the weak detector signal in the first standby state.

US Pat. No. 10,141,774

CHARGING CIRCUIT AND TERMINAL FOR WIRED AND WIRELESS CHARGING

Huawei Device (Dongguan) ...

1. A charging circuit, comprising:a wired connection module, a wireless charging module, a switch circuit, a control circuit, a shunt circuit, and a charging management module, wherein:
a first input/output end of the wired connection module is configured to connect to an output end of a wired charger, a second input/output end of the wired connection module connects to a first input end of the switch circuit, and the second input/output end further connects to a first input/output end of the shunt circuit;
a first input end of the control circuit connects to the second input/output end of the wired connection module, and an output end of the control circuit connects to an enabling end of the wireless charging module;
an output end of the wireless charging module connects to a second input end of the switch circuit;
a first output end of the switch circuit connects to an input/output end of the charging management module;
a second input/output end of the shunt circuit connects to the input/output end of the charging management module, and a third end of the shunt circuit connects to the output end of the wireless charging module; and
an output end of the charging management module is configured to connect to a battery.

US Pat. No. 10,141,772

COMMUNICATION DEVICE

PANASONIC INTELLECTUAL PR...

1. A communication device comprising:a substrate having an upper surface, a lower surface, and a first edge surface connecting to the upper surface and the lower surface;
a magnetic sheet disposed above the upper surface of the substrate;
a first coil disposed above an upper surface of the magnetic sheet;
a second coil having a portion facing the first edge surface of the substrate in a direction parallel with the upper surface of the substrate; and
an electronic component disposed on the upper surface of the substrate, the electronic component configured to generate noise,
wherein the magnetic sheet has a portion overlapping the second coil in a thickness direction of the magnetic sheet, and
wherein the electronic component does not overlap the magnetic sheet in the thickness direction of the magnetic sheet such that the electronic component is exposed from the magnetic sheet when viewed in plan.

US Pat. No. 10,141,758

POWER CARD AND BASE

Westhill Innovation, LLC,...

1. A power card configured to be charged by a power base and configured to charge an electronic device, including:a case configured to enclose at least one rechargeable battery and a circuit board,
wherein the at least one rechargeable battery and the circuit board are electrically connected;
a connector electrically connected to the circuit board;
each of at least two charging jacks include at least two charging contacts;
at least one charging contact of the at least two charging contacts is electrically connected to the circuit board;
the at least two charging jacks are configured to receive power and charge the at least one rechargeable battery, wherein first and second charging jacks of the at least two charging jacks are disposed near the connector and located on the same side of the power card as the connector; and
the first charging jack is symmetrical to the second charging jack about an axis of the connector such that the power card can be inserted into a charging position of the power base in at least two configurations, wherein the power base charges the power card in each configuration of the at least two configurations.

US Pat. No. 10,141,753

STORAGE BATTERY SYSTEM

TOSHIBA MITSUBISHI-ELECTR...

1. A storage battery system for which N (N?2) power conditioning systems are connected to a power system and a storage battery module group formed by connecting one or more storage battery modules in parallel is connected to each of the N power conditioning systems, and which is operated on a basis of a charge/discharge request from an energy management system that manages electric power supply/demand of the power system, the storage battery system comprising:battery management units that monitor a state of the storage battery module group; and
a controller that receives the charge/discharge request and storage battery information supplied from the battery management units, and controls the N power conditioning systems on the basis of the charge/discharge request and the storage battery information, wherein the power conditioning system has a function of converting AC power of the power system to DC power and charging the DC power to the storage battery module group, and a function of converting the DC power of the storage battery module group to the AC power and discharging the AC power to the power system,
wherein a maximum power storage capacity of the storage battery modules configuring at least one storage battery module group is different from a maximum power storage capacity of the storage battery modules configuring the other storage battery module groups, and
wherein the controller includes a charge/discharge command unit that determines a charge/discharge amount of each of the N power conditioning systems so as to satisfy a relational expression (1) below:

 where,
Pi is the charge/discharge amount of an i-th power conditioning system (1?i?N),
Preq is the charge/discharge request,
Bnumi is the number of the storage battery modules connected to the i-th power conditioning system, and
Cratioi is a capacity ratio of the maximum power storage capacity of the storage battery modules connected to the i-th power conditioning system to a reference power storage capacity.

US Pat. No. 10,141,751

CONTROL SYSTEM FOR ELECTRIC STORAGE SYSTEM

Hitachi, Ltd., Tokyo (JP...

1. A control system to control an electric storage system in which a plurality of pairs of storage batteries and converters are connected in parallel to a power system, comprising:a controller configured to control a charge total power received by the plurality of pairs of storage batteries and converters,
wherein a total number of the plurality of pairs of storage batteries and converters is N, and N is ?2,
wherein the controller is configured to:
compare the charge total power (P) to be received by the plurality of pairs of storage batteries and converters with a limit output (p0) corresponding to a predetermined conversion efficiency of a first pair of the storage batteries and converters
when p0?P?N×p0, determine an operation number (n) of the pairs of storage batteries and converters which are to operate to receive the P in parallel, where n is equal to an integer quotient of P/p0, and
wherein the controller is further configured to:
determine respective charge powers (Pi) of each of the n pairs of storage batteries and converters for a charge operation based on respective states of charge (SOCi) of each of the n pairs of storage batteries and converters and a predetermined upper limit charge amount (SOCmax).

US Pat. No. 10,141,742

SYSTEM AND METHOD FOR PROVIDING A BALANCING POWER FOR AN ELECTRICAL POWER GRID

CATERVA GMBH, Pullach Im...

1. A regulating system adapted to provide in the event of a deviation from a nominal grid frequency a balancing power for an electrical power grid that is operated at the nominal grid frequency,wherein the regulating system comprises:
multiple energy storage system, ESS, units that are connected in each case by means of an inverter to the electrical power grid and comprise in each case at least one energy storage device; and
a control centre adapted to divide into sub-frequency intervals a frequency deviation interval that lies between a minimum grid frequency and a maximum grid frequency around the nominal grid frequency and adapted, in dependence upon the states of charge of the energy storage devices that are included in the energy storage system, ESS, units, to allocate different energy storage system, ESS, units to each sub-frequency interval so as to form an ESS cluster for the respective sub-frequency interval, wherein said ESS-cluster delivers a portion of the balancing power that is to be provided by the regulating system in the respective sub-frequency interval.

US Pat. No. 10,141,688

PLUG CONNECTOR WITH RESILIENT ENGAGEMENT ELEMENT AND SEAL

Radiall S.A., Aubervilli...

1. A connector comprising:a first connector portion; and
a second connector portion,
said first connector portion comprising a seal, a resilient detent element, a first inner conductor portion, a first outer conductor portion and a first insulating portion, said first insulating portion supporting said first inner conductor portion radially inward of and coaxially to said first outer conductor portion, a portion of said resilient detent element contacting a radially outward facing surface of said first outer conductor portion,
said second connector portion comprising a counterpart detent element, a second inner conductor portion, a second outer conductor portion and a second insulating portion, said second insulating portion supporting said second inner conductor portion radially inward of and coaxially to said second outer conductor portion,
in a mated configuration of said first connector portion and said second connector portion, said first inner conductor portion electrically and mechanically contacts said second inner conductor portion, and said first outer conductor portion electrically and mechanically contacts said second outer conductor portion,
in said mated configuration said resilient detent element engages said counterpart detent element and locks said first connector portion to said second connector portion, and
a compression of said seal in said mated configuration effecting a force parallel to a longitudinal axis of said first connector portion, said force inhibiting play between said resilient detent element and said counterpart detent element.

US Pat. No. 10,141,655

SWITCH ASSEMBLY WITH INTEGRATED TUNING CAPABILITY

Ethertronics, Inc., San ...

1. A radio frequency integrated circuit (RFIC) containing a switch assembly with integrated tuning capability, the RFIC comprising:a plurality of multi-port switches, including:
a first multi-port switch configured to couple with a first antenna adapted for communication at low-frequency bands between 698 MHz and 960 MHz,
a second multi-port switch configured to couple with a second antenna adapted for communication at mid-frequency bands between 850 MHz and 900 MHz, and
a third multi-port switch configured to couple with a third antenna adapted for communication at high-frequency bands between 1710 MHz and 2700 MHz,
each of the first through third multi-port switches further configured to couple with a plurality of RF paths of an RF front end within a communication system;
a first tunable component coupled to the first multi-port switch, wherein the first tunable component is configured to vary an impedance associated with the first multi-port switch;
a second tunable component coupled to the second multi-port switch, wherein the second tunable component is configured to vary an impedance associated with the second multi-port switch;
a memory cell configured for storing information; and
a look-up table resident in said memory cell and containing said information, wherein the information includes: switch state data for configuring a state of each of the first through third multi-port switches, and tuning state data for configuring a state of each of the first and second tunable components;
wherein each of the first through third multi-port switches and the first and second tunable components are adapted to couple with a processor for receiving control signals for configuring a switch state or tuning state, respectively; and
wherein the third multi-port switch is not connected to a tunable component.

US Pat. No. 10,141,637

PATTERN ANTENNA

MegaChips Corporation, O...

1. A pattern antenna comprising:a substrate;
a first ground formed on a first surface of the substrate;
an antenna including a first conductor in which a plurality of bents are formed, the first conductor being formed on the first surface of the substrate and being electrically connected to the first ground;
a circuit including a second conductor formed in a second surface, which is a different surface from the first surface, the second conductor being formed so as to at least partially overlap with the first conductor of the antenna as viewed in planar view, the circuit including:
a first taper with a tapered shape, a feed point being disposed at a tip of the first taper or in proximity of the tip of the first taper; and
an extension extended toward a side opposite to the feed point as viewed in planar view, the extension being electrically connected to the first taper;
a connector configured to electrically connect the first conductor with the second conductor; and
a second ground, with no contact with the first taper, with such a shape that sandwiches at least a part of the first taper as viewed in planar view, wherein
the second ground includes a second taper, and
the second taper is tapered such that the second ground does not contact with the first taper.

US Pat. No. 10,141,631

ELECTRONIC DEVICE WITH ANTENNA

Apple Inc., Cupertino, C...

1. An electronic device having a front face and an opposing rear face, comprising:a housing having first and second parallel metal speaker grills that respectively form the front and rear faces and a housing wall that extends between and is perpendicular to the first and second metal speaker grills;
an antenna mounted under the housing wall and interposed between the first and second metal speaker grills that transmits and receives antenna signals through the housing wall, wherein the antenna has a sheet metal layer that forms a planar inverted-F antenna resonating element, that forms a ground, that forms a return path that extends between the planar inverted-F antenna resonating element and the ground, and that forms a feed path extending from the planar inverted-F antenna resonating element; and
a printed circuit to which the antenna is mounted, wherein the printed circuit has an opening, the feed path formed from the sheet metal layer passes at least partway through the opening, the antenna has an outer side facing outwardly towards the first metal speaker grill and an opposing inner side, and the antenna has a feed that includes the feed path and that is formed adjacent to the inner side.

US Pat. No. 10,141,586

FUEL CELL MODULE, COMBINED POWER GENERATION SYSTEM INCLUDING THE SAME, AND TEMPERATURE CONTROL METHOD OF FUEL CELL POWER GENERATION SECTION

MITSUBISHI HITACHI POWER ...

1. A fuel cell module comprising:a pressure vessel which forms an internal space in which a gas is present;
an insulation board which partitions the internal space into an outer space and an inner space;
a plurality of cell stacks disposed in the inner space; and
a convection flow rate adjusting device,
wherein a lower flow passage which connects a lower portion of the outer space on a side vertically lower than the plurality of cell stacks to a lower portion of the inner space on a side vertically lower than the plurality of cell stacks, and an upper flow passage which connects an upper portion of the outer space on a side vertically higher than the plurality of cell stacks to an upper portion of the inner space on a side vertically higher than the plurality of cell stacks are formed in the insulation board,
wherein the convection flow rate adjusting device adjusts a flow rate of at least a part of the gas that flows toward the inner space from the outer space via the lower flow passage and flows toward the outer space from the inner space via the upper flow passage, and
wherein the convection flow rate adjusting device includes a lower damper that adjusts the flow rate of the gas that passes through the lower flow passage.

US Pat. No. 10,141,535

OPTOELECTRONIC COMPONENT AND A METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT

OSRAM OLED GMBH, Regensb...

1. An optoelectronic component, comprising:a first electrode comprising at least one outer electrode segment which is formed at a lateral edge of the first electrode, and at least one inner electrode segment which is formed in a manner spaced apart from the lateral edge of the first electrode,
an electrically conductive current distribution structure formed above the first electrode and comprising at least one outer substructure which extends at least over the outer electrode segment, and at least one inner substructure which extends at least over the inner electrode segment and which is electrically insulated from the outer substructure,
at least one current lead which extends from the lateral edge of the first electrode toward the inner substructure, which is electrically coupled to the inner substructure, which is electrically insulated from the outer substructure and which structure corresponds to the current distribution structure,
an insulation structure, which covers the current distribution structure and the current lead,
an organic functional layer structure above the first electrode, the current distribution structure, the current lead and the insulation structure, and a second electrode above the organic functional layer structure.

US Pat. No. 10,141,520

COATING LIQUID FOR FORMING LIGHT EMITTING LAYER, ORGANIC ELECTROLUMINESCENT ELEMENT, METHOD FOR MANUFACTURING ORGANIC ELECTROLUMINESCENT ELEMENT, AND LIGHTING/DISPLAY DEVICE

Konica Minolta, Inc., To...

1. A coating solution for forming a luminous layer included in one or more organic layers disposed between an anode and a cathode, the coating solution comprising:a thermally-activated delayed fluorescent, compound, and
a heavy atom compound having an external heavy-atom effect to promote intersystem crossing of the thermally-activated delayed fluorescent compound from a triplet excited state to a singlet excited state to increase a fluorescent intensity,
wherein the heavy atom compound is a phosphorescent metal complex,
a lowest excited triplet energy level (T1(TADF)) of the thermally-activated delayed fluorescent compound and a lowest excited triplet energy level (T1(P)) of the phosphorescent metal complex are within ranges allowing transfer of energy electrons therebetween,
a difference in energy between a lowest excited singlet energy level (S1(TADF)) of the thermally-activated delayed fluorescent compound and the lowest excited triplet energy level (T1(P)) of the phosphorescent metal complex is within a range represented by Expression (1):
?0.2 eV?[S1(TADF)-T1(P)]?1.0 eV  (1), and
a difference in energy between the lowest excited triplet energy level (T1(TADF)) of the thermally-activated delayed fluorescent compound and the lowest excited triplet energy level (T1(P)) of the phosphorescent metal complex is within a range represented by Expression (3):
?0.2 eV?[T1(TADF)?T1(P)]?0.5 eV  (3)

US Pat. No. 10,141,518

COMPOUNDS FOR ELECTRONIC DEVICES

Merck Patent GmbH, Darms...

1. A compound of a formula (I)
wherein A is, identically or differently on each occurrence, a group of the following formula (II) or (III)

wherein the dashed line emanating from the nitrogen atom represents the bond from the group A to the central benzene ring;
wherein the group HetAr including the nitrogen atom shown is, identically or differently on each occurrence, a heteroaryl group having 5 to 30 aromatic ring atoms, optionally substituted by one or more radicals R2;
wherein the group Ar1 is, identically or differently on each occurrence, an aromatic or heteroaromatic ring system having 5 to 30 aromatic ring atoms, optionally substituted by one or more radicals R2, and wherein the two groups Ar1 may be connected via a group Y so that a ring is formed with the nitrogen atom of the group A, wherein
Y is selected from a single bond, BR2, C(R2)2, Si(R2)2, NR2, PR2, P(?O)R2, P(?S)R2, O, S, S?O, and S(?O)2; and
R1 is, identically or differently on each occurrence, CN, C(?O)R3, C(?O)OR3, C(?O)N(R3)2, P(?O)(R3)2, OSO2R3, S(?O)R3, S(?O)2R3, or a heteroaryl group selected from pyridyl, pyrazinyl, pyridazinyl, pyrimidyl and triazinyl, each of which optionally substituted by one or more radicals R3;
R2 is, identically or differently on each occurrence, H, D, F, Cl, Br, I, B(OR3)2, CHO, C(?O)R3, CR3?C(R3)2, CN, C(?O)OR3, C(?O)N(R3)2, Si(R3)3, N(R3)2, NO2, P(?O)(R3)2, OSO2R3, OR3, S(?O)R3, S(?O)2R3, a straight-chain alkyl, alkoxy or thioalkyl group having 1 to 20 C atoms, a branched or cyclic alkyl, alkoxy or thioalkyl group having 3 to 20 C atoms, or an alkenyl or alkynyl group having 2 to 20 C atoms, wherein the above-mentioned groups are optionally substituted by one or more radicals R3 and wherein one or more CH2 groups in the above-mentioned groups are optionally replaced by —R3C?CR3—, Si(R3)2, C?O, C?S, C?NR3, —C(?O)O—, —C(?O)NR3—, NR3, P(?O)(R3), —O—, —S—, SO, or SO2, and wherein one or more H atoms in the above-mentioned groups are optionally replaced by D, F, Cl, Br, I, CN, or NO2, or an aromatic or heteroaromatic ring system having 5 to 60 aromatic ring atoms, optionally substituted by one or more radicals R3, or an aryloxy or heteroaryloxy group having 5 to 60 aromatic ring atoms, optionally substituted by one or more radicals R3, or an aralkyl or heteroaralkyl group having 5 to 60 aromatic ring atoms, optionally substituted by one or more radicals R3, wherein two or more radicals R2 are optionally linked to one another and optionally form a ring;
R3 is, identically or differently on each occurrence, H, D, F, Cl, Br, I, B(OR4)2, CHO, C(?O)R4, CR4?C(R4)2, CN, C(?O)OR4, C(?O)N(R4)2, Si(R4)3, N(R4)2, NO2, P(?O)(R4)2, OSO2R4, OR4, S(?O)R4, S(?O)2R4, a straight-chain alkyl, alkoxy or thioalkyl group having 1 to 20 C atoms, or a branched or cyclic alkyl, alkoxy or
thioalkyl group having 3 to 20 C atoms, or an alkenyl or alkynyl group having 2 to 20 C atoms, wherein the above-mentioned groups are optionally substituted by one or more radicals R4 and wherein one or more CH2 groups in the above-mentioned groups are optionally replaced by —R4C?CR4—, —C?C—, Si(R4)2, C?O, C?S, C?NR4, —C(?O)O—, —C(?O)NR4—, NR4, P(?O)(R4), —O—, —S—, SO, or SO2, and wherein one or more H atoms in the above-mentioned groups are optionally replaced by D, F, Cl, Br, I, CN, or NO2, or an aromatic or heteroaromatic ring system having 5 to 60 aromatic ring atoms, optionally substituted by one or more radicals R4, or an aryloxy or heteroaryloxy group having 5 to 60 aromatic ring atoms, optionally substituted by one or more radicals R4, or an aralkyl or heteroaralkyl group having 5 to 60 aromatic ring atoms, optionally substituted by one or more radicals R4, wherein two or more radicals R3 are optionally linked to one another and optionally form a ring; and
R4 is, identically or differently on each occurrence, H, D, F, or an aliphatic, aromatic or heteroaromatic organic radical having 1 to 20 C atoms, in which, in addition, one or more H atoms are optionally replaced by D or F; two or more substituents R4 are optionally linked to one another and optionally form a ring.

US Pat. No. 10,141,516

COMPOUND FOR ORGANIC ELECTRIC ELEMENT, ORGANIC ELECTRIC ELEMENT COMPRISING THE SAME AND ELECTRONIC DEVICE THEREOF

DUK SAN NEOLUX CO., LTD.,...

1. A compound represented by Formula 1 below:
wherein,
m is an integer from 1 to 4,
n is an integer from 1 to 3,
R1 is selected from the group consisting of hydrogen, deuterium, tritium, a C6-C60 aryl group, and a fluorenyl group, and R2 is selected from the group consisting of hydrogen, deuterium, tritium, a C6-C60 aryl group, a fluorenyl group, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, wherein the aryl group, heterocyclic group, and fluorenyl group may be substituted by one or more substituents selected from the group consisting of halogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group,
Ar1 is selected from the group consisting of a fluorenyl group, a C6-C60 aryl group, a C2-C20 alkenyl group, a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, and a C1-C50 alkyl group, wherein the aryl group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group; and the heterocyclic group, fluorenyl group, alkyl group, and alkenyl group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group,
L1 is selected from the group consisting of a single bond, a C6-C60 arylene group, a fluorenylene group, and a C2-C60 bivalent heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, wherein the arylene group, fluorenylene group, and heterocyclic group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group, and
Ar2 and Ar3 are independently selected from the group consisting of a C6-C60 aryl group, a fluorenyl group, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, wherein the aryl group, heterocyclic group, and fluorenyl group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a silane group, -L?-N(R?)(R?), a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group, wherein L? is selected from the group consisting of a single bond, a C6-C60 arylene group, a fluorenylene group, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; and R? and R? are independently selected from the group consisting of a C6-C60 aryl group, a fluorenyl group, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P.

US Pat. No. 10,141,503

SELECTIVE PHASE CHANGE MATERIAL GROWTH IN HIGH ASPECT RATIO DIELECTRIC PORES FOR SEMICONDUCTOR DEVICE FABRICATION

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a phase change memory (PCM) device comprising:depositing a first dielectric material;
forming an opening in the first dielectric material;
depositing a bottom metal electrode within the opening and polishing the bottom metal electrode;
depositing a second dielectric material on a surface of the bottom metal electrode and the first dielectric material;
depositing a metal nitride conformally to a pore within the second dielectric material of the phase change memory (PCM) device, the pore extending through the second dielectric material and exposing a portion of a top surface of the bottom metal electrode;
etching the metal nitride such that the metal nitride only and directly remains on an entire sidewalls of the pore, exposing the portion of the top surface of the bottom metal electrode after the etching of the metal nitride; and
selectively depositing a phase change material only within the pore of the second dielectric layer to completely fill an entire of the pore with the phase change material, the selective deposition of the phase change material producing a growth rate of phase change material on the metal nitride at a substantially greater rate than a growth rate of the phase change material on exposed surfaces of the second dielectric material;
applying a vacuum during the depositing of the metal nitride, etching of the metal nitride, and the selective depositing of the phase change material;
depositing a top metal electrode in contact with a top surface of the phase change material and in contact with portions of a top surface of second dielectric material; and
depositing a third dielectric material, the third dielectric material is in contact with sidewalls of the top metal electrode.

US Pat. No. 10,141,499

PERPENDICULAR MAGNETIC TUNNEL JUNCTION DEVICE WITH OFFSET PRECESSIONAL SPIN CURRENT LAYER

Spin Transfer Technologie...

1. A magnetic device, comprising:a first synthetic antiferromagnetic structure in a first plane having a magnetization vector that is perpendicular to the first plane and having a fixed magnetization direction;
an antiferromagnetic coupling layer in a second plane and disposed above the first synthetic antiferromagnetic structure;
a second synthetic antiferromagnetic structure in a third plane and disposed over the antiferromagnetic coupling layer;
a magnetic reference layer in a fourth plane and disposed over the second synthetic antiferromagnetic structure, the magnetic reference layer having a magnetization vector that is perpendicular to the fourth plane and having a fixed magnetization direction;
a non-magnetic tunnel barrier layer in a fifth plane and disposed over the magnetic reference layer;
a free magnetic layer having a first diameter and disposed in a sixth plane over the non-magnetic tunnel barrier layer, the free magnetic layer having a magnetization vector that is perpendicular to the sixth plane and having a magnetization direction that can switch between a first magnetization direction to a second magnetization direction, the magnetic reference layer, the non-magnetic tunnel barrier layer and the free magnetic layer forming a magnetic tunnel junction; and
a precessional spin current magnetic layer having a second diameter that is less than the first diameter and a center that is offset relative to a center of the free magnetic layer, the precessional spin current magnetic layer disposed in a seventh plane that is physically separated from the free magnetic layer and coupled to the free magnetic layer by a filter coupling layer that may induce ferromagnetic or antiferromagnetic coupling between the free magnetic layer and the filter layer.

US Pat. No. 10,141,483

SEMICONDUCTOR ILLUMINATING DEVICE

OSRAM Opto Semiconductors...

1. A semiconductor illuminating device for emitting illumination light comprising:an LED configured for emitting blue primary radiation; and
an LED phosphor arranged and configured such that it emits secondary light that forms at least one component of the illumination light,
wherein the LED phosphor comprises a red phosphor for emitting red light as a component of the secondary light and a green phosphor for emitting green light as a component of the secondary light, wherein the green light has a color point located above a first straight line having a slope m1 and a y-intercept n1 in a CIE standard chromaticity diagram, with the slope m1=1.189 and the y-intercept n1=0.226, and
wherein the components of the illumination light are at such a ratio to one another that the illumination light has a color temperature of at most 5500 K.

US Pat. No. 10,141,482

SEMICONDUCTOR LIGHT EMITTING DEVICE

ALPAD CORPORATION, Tokyo...

1. A semiconductor light emitting device, comprising:a light emitting chip having a semiconductor layer at a first surface of the light emitting chip;
a transparent film on the first surface and forming an interface with the semiconductor layer;
a phosphor resin layer including a resin and a phosphor, on the transparent film;
a first electrode having an upper surface on which the light emitting chip is disposed;
a second electrode having an upper surface and being spaced from the first electrode in a direction parallel to the upper surface of the first electrode; and
a reflection layer provided on the upper surfaces of the first and second electrodes, wherein
a refractive index of the transparent film is greater than a refractive index of the semiconductor layer.

US Pat. No. 10,141,480

LIGHT EMITTING DIODE CHIP HAVING DISTRIBUTED BRAGG REFLECTOR AND METHOD OF FABRICATING THE SAME

Seoul Viosys Co., Ltd., ...

1. A method of fabricating a light emitting diode chip, the method comprising:forming a light emitting structure on a first surface of a substrate, the light emitting structure comprising:
a first conductive-type semiconductor layer;
a second conductive-type semiconductor layer; and
an active layer disposed between the first conductive-type semiconductor layer and the second conductive-type semiconductor layer;
removing a portion of the substrate by grinding a second surface of the substrate;
after the grinding, reducing the surface roughness of the second surface of the substrate by lapping the substrate; and
forming a distributed Bragg reflector on the second surface of the substrate,
wherein the distributed Bragg reflector comprises a first material layer comprising TiO2, a second material layer comprising SiO2, a third material layer comprising TiO2, and a fourth material layer comprising SiO2, and
wherein the first material layer has an optical thickness that is different from an optical thickness of the third material layer.

US Pat. No. 10,141,471

PROXIMITY DETECTOR DEVICE WITH INTERCONNECT LAYERS AND RELATED METHODS

1. A device, comprising:a first interconnect layer comprising a first dielectric layer and a plurality of first electrically conductive traces;
an integrated circuit (IC) layer overlying the first interconnect layer and comprising an image sensor IC and a light source IC laterally spaced from the image sensor IC;
a second interconnect layer overlying the IC layer and comprising a second dielectric layer and a plurality of second electrically conductive traces, the second interconnect layer having first and second openings respectively aligned with the image sensor IC and the light source IC, the image sensor IC and the light source IC being electrically coupled to the plurality of first electrically conductive traces and the plurality of second electrically conductive traces;
a transparent adhesive material filling the first and second openings and contacting surfaces of the image sensor IC and the light source IC;
a lens assembly overlying the second interconnect layer and comprising first and second lenses respectively aligned with the first and second openings, the first and second lenses being adhered to the transparent adhesive material; and
a plurality of contacts coupled respectively to the plurality of first electrically conductive traces.

US Pat. No. 10,141,469

RADIALLY STACKED SOLAR CELLS BASED ON 2D ATOMIC CRYSTALS AND METHODS FOR THEIR PRODUCTION

STC.UNM, Albuquerque, NM...

1. A method for fabricating a solar cell, comprising:forming a sacrificial layer;
forming a barrier layer having a gradient strain on the sacrificial layer;
attaching a heterostructure comprising a first light absorbing layer and at least a second light absorbing layer to the barrier layer, wherein the second light absorbing layer is attached to the first light absorbing layer and thereby forms a heterojunction at an interface between the first light absorbing layer and the second light absorbing layer; and
removing the sacrificial layer subsequent to the attaching of the first light absorbing layer and the second light absorbing layer to the barrier layer,
wherein the barrier layer, the first light absorbing layer, and the second light absorbing layer form a spiral structure having a spiral shape resulting from the gradient strain of the barrier layer.

US Pat. No. 10,141,464

SOLAR CELL MODULE

LG ELECTRONICS INC., Seo...

1. A solar cell module comprising:a plurality of bi-facial solar cells having a front surface and a back surface, respectively, wherein light is incident to both of the front surface and the back surface of each of the plurality of bi-facial solar cells;
a light transmission protection part positioned on the front surfaces of the plurality of bi-facial solar cells;
a front protection part positioned between the light transmission protection part and the front surfaces of the plurality of bi-facial solar cells;
a back sheet positioned on the back surfaces of the plurality of bi-facial solar cells, wherein the back sheet includes a first area overlapping the plurality of bi-facial solar cells and having a first transmittance, and a second area being a remaining portion except the first area and having a second transmittance different from the first transmittance; and
a back protection part positioned between the back sheet and the back surfaces of the plurality of bi-facial solar cells,
wherein the back sheet includes:
a base layer,
a first sheet layer positioned between a first surface of the base layer and the back protection part,
a second sheet layer selectively positioned on a second surface of the base layer to correspond to the second area, and
a third sheet layer positioned on the second surface of the base layer and on the second sheet layer.

US Pat. No. 10,141,451

ELECTRODE LAYER, THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY APPARATUS HAVING THE SAME, AND FABRICATING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor, comprising an active layer, and a source electrode and a drain electrode on the active layer;wherein each of the source electrode and the drain electrode comprises a combination of a metal electrode sub-layer that is substantially non-transparent, and a diffusion barrier sub-layer between the metal electrode sub-layer and the active layer;
wherein the diffusion barrier sub-layer is made of a material comprising M1OaNb doped with one or more metal element, one or more non-metal element, or a combination thereof, wherein M1 is a single metal or a combination of metals, a?0, and b>0.

US Pat. No. 10,141,450

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a substrate;
a gate electrode and an oxide semiconductor film over the substrate, the gate electrode and the oxide semiconductor film overlapping each other with a gate insulating film therebetween;
a metal oxide film in contact with the oxide semiconductor film, the metal oxide film and a first region of the oxide semiconductor film overlapping each other with a second region of the oxide semiconductor film therebetween; and
a conductive film in contact with the metal oxide film, the conductive film comprising a metal element,
wherein the metal oxide film is in contact with the second region of the oxide semiconductor film,
wherein each of the first region of the oxide semiconductor film and the second region of the oxide semiconductor film comprises a first metal and oxygen,
wherein a concentration of the first metal in the second region of the oxide semiconductor film is higher than a concentration of the first metal in the first region of the oxide semiconductor film, and
wherein the concentration of the first metal in the second region of the oxide semiconductor film is higher than a concentration of the first metal in the metal oxide film.

US Pat. No. 10,141,434

COMPLEMENTARY TUNNELING FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR

Huawei Technologies Co., ...

1. A complementary tunneling field effect transistor, comprising:a first drain region and a first source region disposed on a substrate, wherein the first drain region and the first source region comprise a first dopant;
a first channel disposed on the first drain region and a second channel disposed on the first source region;
a second source region disposed on the first channel and a second drain region disposed on the second channel, wherein the second source region and the second drain region comprise a second dopant;
a first epitaxial layer disposed on the first drain region and the second source region, and a second epitaxial layer disposed on the second drain region and the first source region, wherein the first epitaxial layer covers a side wall of the first channel and the second source region, and the second epitaxial layer covers a side wall of the second channel and the second drain region;
a first gate stack layer disposed on the first epitaxial layer, and a second gate stack layer disposed on the second epitaxial layer;
a first isolator disposed on the second source region and the first drain region, and a second isolator disposed on the first source region and the second drain region, wherein the first isolator is in contact with the first epitaxial layer and the first gate stack layer, and the second isolator is in contact with the second epitaxial layer and the second gate stack layer; and
wherein the first drain region, the first channel, the second source region, the first epitaxial layer, and the first gate stack layer form a first tunneling field effect transistor, and the second drain region, the second channel, the first source region, the second epitaxial layer, and the second gate stack layer form a second tunneling field effect transistor.

US Pat. No. 10,141,431

EPITAXY SOURCE/DRAIN REGIONS OF FINFETS AND METHOD FORMING SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming isolation regions extending into a semiconductor substrate, wherein the forming the isolation regions comprises:
in a common etching process, etching the semiconductor substrate to form two first trenches and a second trench between the two first trenches;
forming a hard mask layer comprising first bottom portions extending to bottoms of the two first trenches, and a second bottom portion extending to a bottom of the second trench;
performing an etching step, wherein both the two first bottom portions and the second bottom portion are exposed to an etchant used in the etching step, and the first bottom portions and portions of the semiconductor substrate directly underlying the first bottom portions are etched to extend the two first trenches down, and the second bottom portion protects a portion of the semiconductor substrate directly underlying the second bottom portion; and
filling the two first trenches and the second trench with a dielectric material to form isolation regions;
recessing the isolation regions, so that portions of semiconductor strips between the isolation regions protrude higher than the isolation regions to form semiconductor fins;
recessing the semiconductor fins to form recesses;
epitaxially growing a first semiconductor material from the recesses;
etching the first semiconductor material; and
epitaxially growing a second semiconductor material from the first semiconductor material that has been etched back.

US Pat. No. 10,141,404

POWER SEMICONDUCTOR DEVICE HAVING FULLY DEPLETED CHANNEL REGION

Infineon Technologies AG,...

1. A power semiconductor device, comprising:a semiconductor body coupled to a first load terminal structure and a second load terminal structure and configured to conduct a load current;
a first cell and a second cell, each being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type;
a first mesa included in the first cell, the first mesa including a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region;
a second mesa included in the second cell, the second mesa including a second port region having a second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region;
each of the first mesa and the second mesa being spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and having a total extension of less than 100 nm in the direction, wherein the insulation structure houses:
a control electrode structure for controlling the load current within the first mesa and the second mesa, the control electrode structure being electrically insulated from the first load terminal structure; and
a guidance electrode electrically insulated from the control electrode structure and arranged in between the first mesa and the second mesa,
wherein the control electrode structure is configured to induce an inversion channel within the first channel region and an accumulation channel within the second channel region.

US Pat. No. 10,141,399

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first semiconductor region of a first conductivity type;
a second semiconductor region of the first conductivity type provided on a portion of the first semiconductor region, an impurity concentration of the first conductivity type of the second semiconductor region being lower than an impurity concentration of the first conductivity type of the first semiconductor region;
a third semiconductor region of a second conductivity type provided on the second semiconductor region; and
a first insulating layer provided on another portion of the first semiconductor region, the first insulating layer being provided around the portion of the first semiconductor region, the second semiconductor region, and at least a portion of the third semiconductor region, the first insulating layer contacting the third semiconductor region,
a length in a second direction of the first semiconductor region being longer than a length in the second direction of the second semiconductor region and being longer than a distance from one end portion in the second direction of the first insulating layer to one other end portion in the second direction of the first insulating layer,
the second direction being orthogonal to a first direction from the second semiconductor region toward the third semiconductor region,
any semiconductor region which opposes to the second semiconductor region with the first insulating layer interposed being not provided.

US Pat. No. 10,141,398

HIGH VOLTAGE MOS STRUCTURE AND ITS MANUFACTURING METHOD

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a high-voltage (HV) NMOS structure, comprising:
a source region and a drain region separated from each other;
a channel region disposed between the source region and the drain region, the channel region having a channel direction from the source region toward the drain region;
a gate dielectric disposed on the channel region and on portions of the source region and the drain region; and
a gate electrode disposed on the gate dielectric, the gate electrode comprising:
a first portion of n-type doping; and
two second portions of p-type doping disposed at two sides of the first portion, the two second portions having an extending direction perpendicular to the channel direction;
wherein the HV NMOS structure further comprises:
a substrate;
a first n-type doped region and a second n-type doped region disposed in the substrate and separated from each other;
an isolation structure disposed in the substrate, the isolation structure having a first through opening and a second through opening in the first n-type doped region and the second n-type doped region, respectively;
a first n-type heavily doped region and a second n-type heavily doped region disposed in the first through opening and the second through opening, respectively;
wherein the first n-type doped region and the first n-type heavily doped region are disposed in the source region, and the second n-type doped region and the second n-type heavily doped region are disposed in the drain region.

US Pat. No. 10,141,391

MICROSTRUCTURE MODULATION FOR 3D BONDED SEMICONDUCTOR CONTAINING AN EMBEDDED RESISTOR STRUCTURE

International Business Ma...

11. A method of forming a three-dimensional (3D) bonded semiconductor structure, the method comprising:providing a first semiconductor structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and a first metallic pad structure having a columnar grain microstructure embedded in the first bonding oxide layer, and a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and a second metallic pad structure having a columnar grain microstructure embedded in the second bonding oxide layer;
forming a metal resistor structure on a recessed surface of the first metallic pad structure or the second metallic pad structure; and
bonding the first semiconductor structure to the second semiconductor structure, wherein the bonding provides a bonding interface between the first and second bonding oxide layers and another bonding interface between the metal resistor structure and the first metallic pad structure or the second metallic pad structure.

US Pat. No. 10,141,388

DISPLAY DEVICE WITH TRANSISTOR SAMPLING FOR IMPROVED PERFORMANCE

SONY CORPORATION, Tokyo ...

1. An apparatus comprising:a plurality of pixels arranged in a matrix form, each of the pixels including a capacitor, a first transistor, a second transistor, and a light emitting element;
a plurality of first lines that extend along a first direction and connected to the pixels;
a plurality of second line that extend along a second direction and connected to the pixels, the second direction being perpendicular to the first direction;
wherein,
(a) each of the first lines includes a first lower wiring portion, a second lower wiring portion, and an upper wiring portion, and
(b) in each of the first lines:
(i) the upper wiring portion is connected to the first lower wiring portion via a first plurality of contact holes formed in an insulating film, and connected to the second lower wiring portion via a second plurality of contact holes formed in the insulating film,
(ii) the upper wiring portion is on the insulating film,
(iii) the insulating film is on the lower wiring portion,
(iv) the power supply line crosses the first lower wiring portion, and
(v) the second lower wiring portion crosses a corresponding one of the second lines.

US Pat. No. 10,141,384

ORGANIC ELECTROLUMINESCENT PANEL AND LUMINESCENT UNIT

Joled Inc., Tokyo (JP)

1. An organic electroluminescent panel comprising:a plurality of pixels each including a plurality of subpixels, the subpixels each including an organic electroluminescent element, the organic electroluminescent element including a first electrode, a second electrode, and an organic material layer that is provided between the first electrode and the second electrode; and
a plurality of banks that define each of the subpixels in each of the pixels,
the organic electroluminescent element in each of the subpixels being provided in a gap between adjacent two of the plurality of banks, and
the following relational expression being satisfied:
y?0.0001714x2+0.0151429x+0.2914286
where y denotes a height, from a bottom surface of the gap, of a pinning position at which a surface of the organic material layer and one of the banks are in contact with each other, and x denotes a width of the bottom surface of the gap.

US Pat. No. 10,141,359

IMAGE SENSOR

HIMAX TECHNOLOGIES LIMITE...

1. An image sensor, comprising:an infrared receiving portion configured to receive infrared, and
a visible light receiving portion configured to receive a visible light, wherein the visible light receiving portion comprises an infrared cutoff filter grid and a color filter;
wherein the infrared cutoff filter grid has a grid structure;
wherein the infrared cutoff filter grid is configured to block the transmission of the infrared laterally passing the color filter;
wherein when viewed in cross section, the infrared cutoff filter grid comprises a base portion having an upper surface, and a plurality of pillar portions extending upwardly from the upper surface of the base portion, each adjacent pair of the pillar portions forming a space therebetween to thereby form a plurality of spaces;
wherein the color filter comprises a red color filter unit, a blue color filter unit, and a green color filter unit, and each of the red color filter unit, the blue color filter unit, and the green color filter unit is filled in one of the spaces;
wherein the visible light receiving portion further comprises a visible light photodiode and an infrared cutoff filter disposed on the visible light photodiode;
wherein the infrared cutoff filter and infrared cutoff filter grid are formed in one-piece.

US Pat. No. 10,141,350

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a substrate; and
a plurality of data lines and a plurality of gate lines disposed on the substrate, the data lines and the gate lines being configured to define a plurality of pixel units,
wherein each pixel units comprises:
a pixel electrode;
a thin film transistor electrically connected to the data line and the gate line and configured to drive the pixel electrode; and
a resin layer disposed on the data line and/or the gate line and provided with at least one gas discharging structure each having an opening facing away from the substrate.

US Pat. No. 10,141,348

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a first base;
a first thin-film transistor (TFT) and a second TFT which are disposed on the first base to be adjacent to each other along a first direction;
an organic layer which covers the first TFT and the second TFT and comprises a first opening overlapping a first drain electrode of the first TFT and a second opening overlapping a second drain electrode of the second TFT;
a common electrode which is located on the organic layer and comprises a first common electrode opening overlapping the first opening and a second common electrode opening overlapping the second opening;
a bump spacer which is located on the common electrode;
an insulating layer which is located on the common electrode and the bump spacer;
a first pixel electrode which is disposed on the insulating layer to overlap the common electrode and is electrically connected to the first TFT; and
a second pixel electrode which is disposed on the insulating layer to overlap the common electrode and is electrically connected to the second TFT,
wherein a minimum distance between the bump spacer and the first common electrode opening is equal to a minimum distance between the bump spacer and the second common electrode opening in a plan view,
wherein the bump spacer and the insulating layer are formed of different materials.

US Pat. No. 10,141,345

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:common electrodes;
pixel electrodes overlapped with the common electrodes in a direction perpendicular to the array substrate;
common electrode lines;
at least one auxiliary common electrode line formed in a same layer as the pixel electrodes;
a passivation layer and an insulation layer provided between the common electrode lines and the at least one auxiliary common electrode line; and
data lines provided between the insulation layer and the passivation layer,
wherein the at least one auxiliary common electrode line is arranged to intersect with the common electrode lines and be electrically connected to the common electrode lines through via holes formed in the insulation layer and the passivation layer, and
wherein the at least one auxiliary common electrode line is disposed overlapped with the data lines in the direction perpendicular to the array substrate, the at least one auxiliary common electrode line is arranged parallel to the data lines, and the insulation layer is provided between the at least one auxiliary common electrode line and the data lines.

US Pat. No. 10,141,344

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor comprising:
a first conductor over a substrate;
a first insulator over the first conductor;
a first oxide over the first insulator;
a second insulator over the first oxide;
a second conductor over the second insulator;
a third insulator over the second conductor;
a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, and a side surface of the third insulator; and
a fifth insulator in contact with the first oxide and the fourth insulator,
a second transistor comprising:
a third conductor;
a fourth conductor at least part of which overlaps with the third conductor; and
a second oxide between the third conductor and the fourth conductor,
wherein the third conductor and the fourth conductor are electrically connected to the first conductor.

US Pat. No. 10,141,340

THIN-FILM-TRANSISTOR, THIN-FILM-TRANSISTOR ARRAY SUBSTRATE, FABRICATING METHODS THEREOF, AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A method for fabricating a thin-film-transistor (TFT), the method comprising:forming an initial conductive layer on a base substrate;
forming an oxidation preventing layer on a portion of the initial conductive layer to be removed;
performing an oxidization process to partially oxidize the initial conductive layer to form an oxidized insulating sub-layer and a non-oxidized conductive sub-layer, a portion of the non-oxidized conductive sub-layer being exposed through the oxidized insulating sub-layer;
removing the oxidation preventing layer after forming the oxidized insulating sub-layer;
removing, after the oxidation preventing layer is removed, the portion of the initial conductive layer to be removed to expose a portion of the base substrate; and
forming an active layer, a source electrode and a drain electrode over a portion of the oxidized insulating sub-layer that is separated by the exposed portion of the base substrate from the portion of the non-oxidized conductive sub-layer exposed through the oxidized insulating sub-layer.

US Pat. No. 10,141,333

DOMAIN WALL CONTROL IN FERROELECTRIC DEVICES

International Business Ma...

1. A ferroelectric device comprising:a first electrode comprising one or more electrically conductive layers,
a second electrode comprising one or more electrically conductive layers;
a layer of ferroelectric material disposed between, and in electrical communication with, the first electrode and the second electrode;
wherein at least one of the first electrode and the second electrode comprises a recessed region and the layer of ferroelectric material comprises a corresponding region of increased thickness;
wherein a programming signal that is applied across the first and second electrodes does not change a polarity of a portion of the layer of ferroelectric material that is proximate to the region of increased thickness; and
wherein the programming signal that is applied across the first and second electrodes changes a polarity of one or more other portions of the layer of ferroelectric material.

US Pat. No. 10,141,322

METAL FLOATING GATE COMPOSITE 3D NAND MEMORY DEVICES AND ASSOCIATED METHODS

Intel Corporation, Santa...

1. A method of making a 3D NAND memory structure having improved process margin and enhanced performance, comprising:etching a cell pillar trench into a cell stack substrate having alternating layers of conducting and insulating materials disposed on a select gate source region;
etching a plurality of floating gate recesses into sidewalls of the cell pillar trench at the layers of conductive material;
forming an interpoly dielectric (IPD) layer in the plurality of floating gate recesses;
depositing a metal layer onto the IPD layer in the plurality of floating gate recesses;
depositing a floating gate layer onto the metal layer in the plurality of floating gate recesses to form a plurality of floating gate units having a floating gate core surrounded on at least three sides by the metal layer.

US Pat. No. 10,141,316

SEMICONDUCTOR DEVICE WITH PILLAR AND BACKGROUND PATTERNS AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other;
bit lines on the substrate, the bit lines including bit line contacts on the active regions;
a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, and the plurality of pillar patterns having a non-overlapping relationship with the bit line contacts; and
a background pattern on the substrate, the background pattern being completely peripheral with respect to all the plurality of pillar patterns in the pillar array pattern,
wherein the plurality of pillar patterns includes first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, and
wherein a distance between the background pattern and a most adjacent one of the plurality of pillar patterns is larger than a distance between two adjacent ones of the plurality of pillar patterns.

US Pat. No. 10,141,311

TECHNIQUES FOR ACHIEVING MULTIPLE TRANSISTOR FIN DIMENSIONS ON A SINGLE DIE

INTEL CORPORATION, Santa...

1. An integrated circuit including at least one transistor device, the integrated circuit comprising:a first fin above and native to a substrate, the first fin having a channel region, wherein the first fin includes a first width (W1) in a sub-channel region below the channel region and a second width (W2) in the channel region, W1 is greater than 15 nanometers (nm), W2 is 15 nm or less, and W1 is at least 1 nm greater than W2; and
a second fin above and native to the substrate, the second fin having a channel region, wherein the second fin includes a third width (W3) in the channel region, and W3 is different from W2.

US Pat. No. 10,141,308

LOW RESISTANCE SOURCE/DRAIN CONTACTS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES

International Business Ma...

1. A semiconductor device, comprising:source/drain regions (S/D) in an n-type field effect transistor (NFET) region and in a p-type field effect transistor (PFET) region;
contacts formed to recrystallized layers of the S/D regions in the NFET and PFET regions; and
metastable recrystallized interface layers formed between the contacts and the S/D regions in respective NFET and PFET regions, the recrystallized interface layers including an alloy element concentration that exceeds solubility with a respective material of the S/D regions in the respective NFET and PFET regions.

US Pat. No. 10,141,304

SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor substrate;
an upper electrode provided on an upper surface of the semiconductor substrate; and
a lower electrode provided on a lower surface of the semiconductor substrate;
wherein
an anode region and an upper Insulated Gate Bipolar Transistor (IGBT) structure are provided in a range in the semiconductor substrate that is exposed at the upper surface,
a trench is provided in the upper surface,
the anode region is separated from the upper IGBT structure by the trench, the anode region is in contact with the trench, and the upper IGBT structure is in contact with the trench,
the anode region is a p-type region connected to the upper electrode,
the upper IGBT structure includes an n-type emitter region and a p-type body region, the emitter region connected to the upper electrode, and the body region being in contact with the emitter region and connected to the upper electrode,
a gate insulating film and a gate electrode are provided in the trench,
a cathode region and a collector region are provided in a range in the semiconductor substrate that is exposed at the lower surface, the cathode region bordering the collector region at an interface;
the cathode region is an n-type region connected to the lower electrode and provided in at least a part of a region below the anode region,
the collector region is a p-type region connected to the lower electrode, provided in at least a part of a region below the upper IGBT structure, and being in contact with the cathode region,
an n-type drift region is provided between an upper structure including the anode region and the upper IGBT structure and a lower structure including the cathode region and the collector region,
a crystal defect region is provided across a portion of the drift region that is above the cathode region and a portion of the drift region that is above the collector region so that the crystal defect region is provided in a part of the portion of the drift region that is above the collector region,
the crystal defect region having a density of crystal defects higher than a density of crystal defects in a surrounding region of the crystal defect region,
the semiconductor substrate has a dimension that satisfies a relationship of y?0.007x2?1.09x+126 within a range of 165 ?m?x?60 ?m, where x is a number in the unit of ?m and represents a thickness of the semiconductor substrate and y is a number in the unit of ?m and represents a width of a portion of the crystal defect region that protrudes along a direction parallel to the upper surface of the semiconductor substrate from the portion of the drift region that is above the cathode region to the portion of the drift region that is above the collector region,
the trench and the interface are separate from each other when viewed in plan view, with the trench above the collector region and the interface below the anode region and without the interface directly below the trench, such that the anode region extends toward the upper IGBT structure more than the cathode region does, and
the portion of the crystal defect region does not protrude beyond the trench to a portion of the drift region that is below the upper IGBT structure.

US Pat. No. 10,141,303

RF AMPLIFIER PACKAGE WITH BIASING STRIP

Cree, Inc., Durham, NC (...

1. An RF amplifier package, comprising:a flange shaped body section,
an electrically conductive die pad centrally located on the body section;
an electrically insulating window frame disposed on an upper surface of the body section and surrounding the die pad;
a first electrically conductive lead disposed on the window frame adjacent to a first side of the die pad and extending away from the first side of the die pad towards a first edge side of the body section
a second electrically conductive lead disposed on the window frame adjacent to a second side of the die pad and extending away from the second side of the die pad towards a second edge side of the body section, the second side of the die pad being opposite the first side of the die pad; and
a first electrically conductive biasing strip that is: disposed on the window frame, continuously connected to the second lead, and extends along and a third side of the die pad, the third side of the die pad extending between the first and second sides of the die pad.

US Pat. No. 10,141,302

HIGH CURRENT, LOW SWITCHING LOSS SIC POWER MODULE

Cree, Inc., Durham, NC (...

1. A power module comprising:a housing with an interior chamber; and
a plurality of switch modules mounted within the interior chamber and interconnected to facilitate switching power to a load wherein each of the plurality of switch modules comprises at least one transistor and at least one diode and the power module is able to block at least 1200 volts, conduct at least 120 amperes, and has switching losses less than 25 milli-Joules.

US Pat. No. 10,141,295

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method for manufacturing a semiconductor device, comprising the steps of:(a) mounting a first semiconductor chip over a second semiconductor chip such that a first surface of the first semiconductor chip faces to a second surface of the second semiconductor chip,
wherein the second semiconductor chip includes a plurality of electrode pads and a recognition mark arranged on the second surface, and a plurality of through electrodes electrically coupled with the electrode pads respectively, and
wherein the first semiconductor chip includes a plurality of projection electrodes arranged on the first surface,
the (a) step including the steps of:
(a1) recognizing the recognition mark;
(a2) performing alignment of the first semiconductor chip and the second semiconductor chip based on a result of having recognized the recognition mark; and
(a3) mounting the first semiconductor chip over the second semiconductor chip, and electrically coupling the electrode pads of the second semiconductor chip and the projection electrodes of the first semiconductor chip respectively,
(b) before the (a) step, forming the through electrodes such that the through electrodes are formed penetrating a silicon base portion of the first semiconductor chip, and
(c) after the (b) step, forming the recognition mark on the second surface such that the recognition mark is electrically separated from the through electrodes and not overlapped with the through electrodes in plan view.

US Pat. No. 10,141,292

DRIVING CHIP BUMP HAVING IRREGULAR SURFACE PROFILE, DISPLAY PANEL CONNECTED THERETO AND DISPLAY DEVICE INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a display panel driven to display an image, the display panel comprising a substrate, the substrate comprising a display area at which the image is displayed;
a terminal pad on the substrate and through which a driving signal is applied to the display area;
a driving chip through which the driving signal is applied to the terminal pad; and
a non-conductive film which fixes the driving chip to the substrate,
wherein the driving chip comprises:
an elastic support body projected from a surface of the driving chip;
a bump wiring on the elastic support body, the bump wiring directly contacting the terminal pad to apply the driving signal to the terminal pad; and
a dispersed particle on the elastic support body,
wherein
the dispersed particle is disposed inside a first portion of the bump wiring,
a second portion of the bump wiring is adjacent to the first portion thereof,
the first portion of the bump wiring at the dispersed particle protrudes further from the elastic support body than the second portion of the bump wiring adjacent to the first portion thereof, and
the protruded first portion of the bump wiring corresponds to a shape of the dispersed particle.

US Pat. No. 10,141,290

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

MIKRO MESA TECHNOLOGY CO....

1. A method for manufacturing a display device, the method comprising:forming at least two bottom conductive lines on an array substrate;
disposing at least four micro light emitting devices respectively on the bottom conductive lines;
forming at least one filling material covering the micro light emitting devices;
forming at least four openings in the filling material by photolithography, such that the micro light emitting devices are respectively exposed by the openings; and
forming at least two upper conductive lines on the filling material, wherein the upper conductive lines are electrically connected to the micro light emitting devices through the openings, the upper conductive lines and the bottom conductive lines cross at the micro light emitting devices, and a vertical projection of one of the bottom conductive lines on the array substrate overlaps with a vertical projection of each of the upper conductive lines on the array substrate.

US Pat. No. 10,141,289

SEMICONDUCTOR PACKAGES HAVING PACKAGE-ON-PACKAGE STRUCTURES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package, comprising:a lower package including a lower semiconductor chip on a lower package substrate;
an upper package, stacked on the lower package, including an upper semiconductor chip on an upper package substrate, the upper semiconductor chip having a plurality of chip pads and the upper package substrate having a plurality of substrate pads; and
connection terminals provided between the lower and upper packages,
wherein the chip pads have a first pitch and the substrate pads have a second pitch greater than the first pitch, and
wherein the upper package substrate comprises a plurality of connection lines that electrically connect the substrate pads to the chip pads,
wherein the lower package further including a lower mold layer and a plurality of connection patterns on the lower mold layer,
wherein the connection patterns are electrically connected to the connection lines,
wherein the lower mold layer comprises an opening exposing a portion of the lower package substrate, the opening being along a peripheral side of the lower mold layer and extending to a depth lower than that of the lower semiconductor chip on the lower package substrate,
wherein the connection patterns conformally extend along a sidewall of the opening to be electrically connected to the lower package substrate,
wherein the connection terminals are spaced apart from the opening in a plan view,
wherein the connection terminals are electrically connected to the substrate pads and the connection patterns, and
wherein the opening has a ring-type trench shape that continuously extends along lateral sides of the lower semiconductor chip and fully surrounds the lower semiconductor chip in the plan view.

US Pat. No. 10,141,287

TRANSFERRING METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS OF MICRO-LED

GOERTEK, INC., Weifang, ...

1. A method for transferring micro-LED, comprising:forming micro-LEDs on a laser-transparent original substrate, wherein the micro-LEDs are lateral micro-LEDs whose P electrodes and N electrodes are located on one side;
bringing the P electrodes and the N electrodes of the lateral micro-LEDs into contact with pads preset on a receiving substrate; and
irradiating the original substrate with laser from an original substrate side to lift-off the lateral micro-LEDs from the original substrate;
wherein the lateral micro-LEDs contain magnetic substance, and the P electrodes and the N electrodes of the lateral micro-LEDs are brought into contact with the pads preset on the receiving substrate by means of an action of electromagnetic force.

US Pat. No. 10,141,286

METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGES

Samsung Electronics Co., ...

1. A method of manufacturing a semiconductor package, the method comprising:manufacturing a semiconductor chip in a first semiconductor manufacturing environment;
mounting the semiconductor chip on an upper surface of a printed circuit board, the printed circuit board comprising a lower surface opposite the upper surface;
forming a molding member on the semiconductor chip in a second semiconductor manufacturing environment different from the first semiconductor manufacturing environment;
forming a capping member comprising a material different from the molding member and covering an exposed outer surface of the molding member;
attaching a carrier substrate onto the capping member, the semiconductor chip being between the printed circuit board and the carrier substrate;
forming a redistribution line layer on the lower surface of the printed circuit board in a third semiconductor manufacturing environment different from the second semiconductor manufacturing environment, the redistribution line layer being electrically connected to the semiconductor chip;
forming an external connection member on the redistribution line layer; and
removing the carrier substrate.

US Pat. No. 10,141,284

METHOD OF BONDING SEMICONDUCTOR SUBSTRATES

IMEC vzw, Leuven (BE)

1. A method of bonding semiconductor substrates, the method comprising:providing a first semiconductor substrate and a second semiconductor substrate to be bonded;
pre-bond processing each of the first and second semiconductor substrates prior to bonding, pre-bond processing comprising:
depositing a dielectric layer on a major surface of the each of first and second semiconductor substrates,
chemical-mechanical polishing the dielectric layer of the each of the first and second semiconductor substrates to reduce the roughness of the dielectric layer,
depositing a silicon carbon nitride (SiCN) layer on the dielectric layer of the each of the first and second semiconductor substrates,
pre-bond annealing the each of the first and second semiconductor substrates, and
chemical-mechanical polishing the SiCN layer to reduce the roughness of the SiCN layer;
bonding the first and second semiconductor substrates, bonding comprising:
aligning the first and second substrates, and
contacting the SiCN layers of the first and second substrates, thereby forming an assembly of bonded substrates; and
post-bond annealing the assembly of bonded substrates.

US Pat. No. 10,141,278

CHIP MOUNTING STRUCTURE

International Business Ma...

1. A method for changing a shape of a substrate to reduce stress exerted on an interlayer insulating layer of a chip, the method comprising:providing the substrate;
mounting the chip on the substrate such that a center of the chip corresponds to a center of the substrate and such that sides of the chip are parallel to sides of the substrate;
measuring a distance B between a side of the chip and a nearest side of the substrate; and
cutting off square portions of the substrate from each corner of the substrate such that a distance between a corner of the chip and a nearest corner of the substrate is less than the distance B,
wherein each square portion has sides of a length c, and wherein

US Pat. No. 10,141,267

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package comprising:a first connection member including a redistribution layer;
a first semiconductor chip disposed on the first connection member and having an active surface having a first connection pad disposed thereon and an inactive surface opposing the active surface;
a first encapsulant disposed on the first connection member and encapsulating at least portions of the first semiconductor chip;
a second semiconductor chip disposed on the first encapsulant and having an active surface having a second connection pad disposed thereon and an inactive surface opposing the active surface;
a second encapsulant disposed on the first encapsulant and encapsulating at least portions of the second semiconductor chip; and
a second connection member having a through-hole,
wherein the active surfaces of the first semiconductor chip and the second semiconductor chip face the first connection member,
the first connection pad and the second connection pad are electrically connected to the redistribution layer of the first connection member through a first via and a second via that do not overlap each other, respectively,
the first semiconductor chip is disposed in the through-hole of the second connection member, and
the first encapsulant encapsulates at least portions of the second connection member.

US Pat. No. 10,141,263

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method for fabricating semiconductor device, comprising:providing a substrate;
forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer;
performing a first etching process to remove part of the ILD layer for forming a recess;
performing a second etching process to remove part of the first spacer for expanding the recess after performing the first etching process; and
forming a contact plug in the recess.

US Pat. No. 10,141,261

DEVICE COMPRISING NANOSTRUCTURES AND METHOD OF MANUFACTURING THEREOF

1. A device (300, 410-412) having individually addressable sets of nanostructures (207) comprising:a first substrate (200), wherein the first substrate comprises a first face (202) and a second face (203), wherein an insulating layer (201) comprising an insulating material arranged on said first face (202) of said first substrate (200);
a plurality of electrically conductive portions (208) within said insulating layer (201), said portions being spaced apart from each other;
a set of nanostructures (207) arranged on said first face (202) of the first substrate, such that the nanostructures are spatially separated and grown on top of the said first face (202), wherein said sets of nanostructures (207) are arranged on each of said electrically conductive portions (208) such that each electrically conductive portion is in electrical connection with a respective one of said sets of nanostructures;
a connecting structure (210) in a second substrate (209) underlying said second face (203) of said insulating layer (201), wherein the said connecting structure (210) is comprised of materials different than the composition materials of the conductive portions (208), the insulating material and the said second substrate (209), said connecting structure being connectable to an external device and configured to provide a first electrical connection to each of said electrically conductive portions (208), and thereby enabling individual addressing of each set of nano structures (207).

US Pat. No. 10,141,259

SEMICONDUCTOR DEVICES HAVING ELECTRICALLY AND OPTICALLY CONDUCTIVE VIAS, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:a first semiconductor die having a first optical component for receiving and/or transmitting optical signals;
a second semiconductor die adjacent to the first semiconductor die and having a second optical component for receiving and/or transmitting optical signals; and
a via extending at least between the first optical component and the second optical component, the via having a transparent and electrically conductive material disposed therein, wherein the transparent and electrically conductive material (a) optically couples the first and second optical components and (b) electrically couples the first and second semiconductor dies.

US Pat. No. 10,141,258

SEMICONDUCTOR DEVICES HAVING STAGGERED AIR GAPS

Samsung Electronics Co., ...

9. A semiconductor device comprising:a substrate including a first region and a second region spaced apart from each other in a first direction;
lower conductive patterns disposed on the substrate and including first lower conductive patterns on the first region and second lower conductive patterns on the second region;
a first interlayer dielectric layer disposed between the first lower conductive patterns
a lower air gap provided in a space between the second lower conductive patterns;
a middle conductive pattern disposed on the lower conductive pattern in the second region;
upper conductive patterns including first upper conductive patterns disposed on the first lower conductive patterns and second upper conductive patterns disposed on the second lower conductive patterns; and
an upper air gap provided in a space between the second upper conductive patterns,
wherein the first interlayer dielectric layer completely fills a space between the first lower conductive patterns.

US Pat. No. 10,141,256

SEMICONDUCTOR DEVICE AND LAYOUT DESIGN THEREOF

Taiwan Semiconductor Manu...

1. A device, comprising:a substrate having formed therein an active region, the active region including an edge extending in a first direction;
a plurality of gates;
a first conductive segment over the active region,
wherein a first distance is present between a first gate of the gates and the first conductive segment, a second distance is present between a second gate of the gates and the first conductive segment, and the first distance is greater than the second distance, and further wherein the second gate of the gates has a major axis in the first direction that extends over the edge of the active region in the first direction; and
a via contacting the first conductive segment wherein the first conductive segment is between the via and the substrate; and further wherein
a third distance between the first gate of the gates and the via is different than the first distance and a fourth distance between the second gate of the gates and the via is different than the second distance.

US Pat. No. 10,141,253

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

16. A method comprising:receiving an interposer, the interposer comprising a first redistribution layer (RDL) over a first side of a substrate, and a plurality of external connectors attached to a second side of the substrate opposing the first side;
attaching a plurality of dies to the first RDL, wherein after attaching the plurality of dies, the first RDL is between the substrate and the plurality of dies;
filling a space between the plurality of dies and the first RDL with an underfill material;
forming a molding material over the first RDL and around the plurality of dies and the underfill material;
dispensing a polymer material on the second side of the substrate without covering top surfaces of the plurality of external connectors distal the substrate; and
curing the polymer material.

US Pat. No. 10,141,252

SEMICONDUCTOR PACKAGES

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a passivation layer having a first surface and a second surface opposite to the first surface, the passivation layer defining a through hole extending from the first surface to the second surface, the through hole further defined by a first sidewall and a second sidewall of the passivation layer;
a first conductive layer on the first surface of the passivation layer and the first sidewall;
a second conductive layer on the second surface of the passivation layer and the second sidewall; and
a third conductive layer between the first conductive layer and the second conductive layer,
wherein the third conductive layer comprises a first seed layer adjacent to the first conductive layer and a second seed layer adjacent to the second conductive layer,
wherein the passivation layer comprises a first polymer layer and a second polymer layer,
wherein the first seed layer is disposed between the first conductive layer and the first polymer layer and the second seed layer is disposed between the second conductive layer and the second polymer layer.

US Pat. No. 10,141,251

ELECTRONIC PACKAGES WITH PRE-DEFINED VIA PATTERNS AND METHODS OF MAKING AND USING THE SAME

GENERAL ELECTRIC COMPANY,...

1. An electronic package, comprising:a substrate having a first side and a second side;
a seed metal layer disposed on at least a portion of the first side of the substrate;
a patterned resist layer disposed on at least a portion of the seed metal layer, wherein the patterned resist layer and the seed metal layer are at least partly removed exposing the first side of the substrate during formation of the electronic package to define a plurality of pre-defined via locations, a plurality of pre-defined via patterns, and a plurality of pre-defined trace patterns;
a metal built-up layer disposed on at least a portion of the seed metal layer corresponding to the plurality of pre-defined via locations and the plurality of pre-defined trace patterns, the metal built-up layer disposed on at least a portion of the seed metal layer such that the seed metal layer is disposed between the substrate and the metal built-up layer,
an adhesive layer disposed on at least a portion of the second side of the substrate;
a contact pad disposed on at least a portion of the adhesive layer and aligned with at least one of the plurality of pre-defined via locations;
an electronic device coupled to the contact pad and aligned with one of the plurality of pre-defined via locations, the plurality of pre-defined via patterns, and the plurality of pre-defined trace patterns, wherein the substrate and the adhesive layer are at least partly removed to extend the plurality of pre-defined via locations to the electronic device;
a first conductive layer disposed on at least a portion of the plurality of pre-defined via locations, the plurality of pre-defined via patterns, and the plurality of pre-defined trace patterns; and
a second conductive layer disposed on the first conductive layer such that the second conductive layer is disposed within the plurality of pre-defined via locations,
wherein a plurality of vias, a plurality of via patterns and a plurality of trace patterns are formed by selectively removing a portion of the first conductive layer and the second conductive layer disposed outside the plurality of pre-defined via locations, the plurality of pre-defined via patterns and the plurality of pre-defined trace patterns.

US Pat. No. 10,141,250

CHIP AND ELECTRONIC DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A chip comprising:a substrate;
a die wrapped together with the substrate by a package;
a plurality of conductive bumps disposed on the die;
an attachment point matrix arranged on a first surface of the substrate, the attachment point matrix comprising multiple attachment points;
a solder joint matrix arranged on a second surface of the substrate, the solder joint matrix comprising a plurality of solder joints comprising a first solder joint group and a second solder joint group; and
multiple substrate cables corresponding to the multiple attachment points, each of the multiple substrate cables extending through an entire thickness of the substrate and extending through a portion of a length of the substrate, each of the multiple substrate cables comprising a first end and a second end, each of the multiple substrate cables comprising at least one bend between the first end and the second end, each of the plurality of conductive bumps being electrically coupled to a corresponding one of the multiple attachment points, the first end of each of the multiple substrate cables being electrically coupled to a corresponding one of the multiple attachment points, the second end of each of the multiple substrate cables being electrically coupled to a corresponding one of the plurality of solder joints, the first solder joint group being arranged along a first parallel line, the second solder joint group being arranged along a second parallel line that is parallel to the first parallel line, a first subset of the multiple substrate cables electrically coupled to the first solder joint group being a first length value, a second subset of the multiple substrate cables electrically coupled to the second solder joint group being a second length value, and a difference between the first length value and the second length value equaling a predetermined value that is not equal to zero.

US Pat. No. 10,141,247

POWER SEMICONDUCTOR DEVICE

1. A power semiconductor device, comprising:a substrate and power semiconductor components arranged on the substrate and electrically conductively connected to the substrate;
an electrically conductive DC voltage bus bar system and comprising a capacitor electrically conductively connected to the DC voltage bus bar system;
wherein the power semiconductor device further comprises:
a capacitor securing apparatus for securing the capacitor and a receptacle device for receiving the capacitor, in which at least part of the capacitor is arranged;
wherein, from the DC voltage bus bar system, a plurality of electrically conductive bus bar system terminal elements are electrically conductively connected thereto and run in a direction of the substrate;
at least one elastic first deformation element is materially bonded to the capacitor securing apparatus and is formed from an elastomer and is arranged on a facing side of the capacitor securing apparatus facing the DC voltage bus bar system;
wherein the capacitor securing apparatus, via the at least one first deformation element, presses the DC voltage bus bar system in the direction of the substrate and thereby further presses the bus bar system terminal elements against designated electrically conductive contact areas of the substrate such that the bus bar system terminal elements are electrically conductively pressure-contacted with said contact areas of the substrate.

US Pat. No. 10,141,246

LEADFRAME PACKAGE WITH SIDE SOLDER BALL CONTACT AND METHOD OF MANUFACTURING

STMicroelectronics, Inc.,...

1. A method, comprising:removing portions of a metal layer on a first surface and a second surface of a leadframe;
forming a first plurality of recesses and a second plurality of recesses in the first surface of the leadframe;
coupling a solder ball to each of the first plurality of recesses;
coupling a die to the metal layer on the first surface of the leadframe;
coupling a plurality of wires between the die and the first surface of the leadframe;
encapsulating the die, the plurality of wires and at least a portion of each solder ball with an encapsulant, a portion of each solder ball extending from a sidewall of the leadframe and into a body of the encapsulant;
removing remaining portions of a body of the leadframe opposite the first plurality of recesses and the second plurality of recesses; and
cutting the encapsulant, the leadframe and the plurality of solder balls to form a leadframe package.

US Pat. No. 10,141,245

HIGH-POWER ACOUSTIC DEVICE WITH IMPROVED PERFORMANCE

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a substrate comprising a substrate body and a die pad on a top surface of the substrate body;
a die-attach material applied over the die pad, wherein the die-attach material is a sintered material;
an acoustic die coupled to the die pad via the die-attach material, wherein:
the acoustic die includes a plurality of acoustic components, a die body and a metallization structure;
the plurality of acoustic components resides over a top surface of the die body and the metallization structure resides over a bottom surface of the die body; and
the metallization structure is vertically sandwiched between the die body and the die-attach material.

US Pat. No. 10,141,239

THERMAL DISSIPATION THROUGH SEAL RINGS IN 3DIC STRUCTURE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a plurality of dies bonded to each other;
an interposer bonded to one of the plurality of dies;
a seal-ring comprising thermal path extending through each of the plurality of dies;
a metal line on the interposer, the metal line extending away from the plurality of dies in a direction parallel with a major surface of the interposer;
an interposer seal ring extending at least partially through the interposer; and
a through via extending at least partially through the interposer, the through via in thermal connection with the metal line through the interposer seal ring.

US Pat. No. 10,141,237

FINGERPRINT RECOGNITION MODULE AND MANUFACTURING METHOD THEREFOR

PRIMAX ELECTRONICS LTD., ...

1. A manufacturing method for a fingerprint recognition module, comprising the following steps:(a) directly connecting and fixing a die to a flexible printed circuit (FPC) board, and electrically connecting the die to the FPC board;
(b) coating an adhesive layer on an upper surface of the die;
(c) covering the adhesive layer with a cover plate, to adhere the cover plate to the adhesive layer; and
(d) applying low pressure injection modeling encapsulation to an encapsulation space defined between the cover plate and the FPC board, so as to form an encapsulation layer in the encapsulation space, wherein step (d) further comprises the following steps:
(d1) placing the FPC board, the die, the adhesive layer, and the cover plate together into a mold;
(d2) adjusting pressure of the mold into a range of 1.5 to 40 bars; and
(d3) injecting a hot melt material into the mold to make the hot melt material flow into the encapsulation space and be cured in the encapsulation space to form the encapsulation layer, wherein the encapsulation layer seals the die.

US Pat. No. 10,141,234

FLIPPED VERTICAL FIELD-EFFECT-TRANSISTOR

International Business Ma...

1. A circuit comprising:a top supply rail and a top ground rail disposed within a top level of the circuit;
a bottom supply rail and a bottom ground rail disposed within a bottom level of the circuit;
at least one input line disposed within a middle level of the circuit;
an output line disposed within the top level of the circuit;
a plurality of p-type vertical FETs coupled to the at least one input line and having at least one p-type vertical FET coupled to the output line, where the plurality of p-type vertical FETs comprises an odd number of plurality of p-type vertical FETs, and wherein at least one p-type vertical FET in the plurality of p-type vertical FETs is coupled to the bottom supply rail; and
at least one n-type vertical FET coupled to one of the bottom ground rail and the top ground rail.

US Pat. No. 10,141,232

VERTICAL CMOS DEVICES WITH COMMON GATE STACKS

International Business Ma...

1. A semiconductor structure, comprising:a first nanowire of a first material disposed on a top surface of a substrate;
at least a second nanowire of a second material different than the first material disposed on the top surface of the substrate; and
a common gate stack surrounding the first nanowire and the second nanowire;
wherein the first nanowire and the second nanowire are vertical with respect to a horizontal plane of the top surface of the substrate;
wherein the first nanowire forms at least a portion of a negative field-effect transistor (NFET) vertical transport channel of a complementary metal-oxide-semiconductor (CMOS) device;
wherein the second nanowire forms at least a portion of a positive field-effect transistor (PFET) vertical transport channel of the CMOS device; and
wherein the first material comprises a group III-V material and the second material comprises a group IV material.

US Pat. No. 10,141,229

PROCESS FOR FORMING SEMICONDUCTOR LAYERS OF DIFFERENT THICKNESS IN FDSOI TECHNOLOGIES

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming semiconductor devices, the method comprising:epitaxially growing a portion of a first semiconductor layer above a buried insulating layer in a first device region, said first semiconductor layer having a first thickness after said epitaxial growth process is performed;
forming a second semiconductor layer of a second thickness above said buried insulating layer in a second device region, said second thickness differing from said first thickness, wherein forming said second semiconductor layer comprises, prior to epitaxially growing said portion of said first semiconductor layer, epitaxially growing a portion of said second semiconductor layer so as to obtain said second thickness, forming a growth mask above said second semiconductor layer, and selectively epitaxially growing said portion of said first semiconductor layer by using said growth mask;
forming a first transistor element in and on said first semiconductor layer; and
forming a second transistor element in and on said second semiconductor layer, said second transistor element comprising a fully depleted channel region.

US Pat. No. 10,141,227

METHOD AND SYSTEM FOR ACHIEVING SEMICONDUCTOR-BASED CIRCUITS OR SYSTEMS HAVING MULTIPLE COMPONENTS WITH ONE OR MORE MATCHED OR SIMILAR CHARACTERISTICS OR FEATURES

NXP USA, INC., Austin, T...

1. A method of achieving at least one part of a semiconductor system having matched or similar components, the method comprising:directing a pick and place head mechanism, by way of a processing device associated with an assembly machine, to move to a first position at a first column of a first row of a singulated semiconductor wafer having a plurality of rows including the first row and a plurality of columns including a first set of columns each including a plurality of first dice of a first type and a second set of columns each including a plurality of second dice of a second type, the first set of columns including the first column;
directing the pick and place head mechanism to implement a first one of the first dice from the first position at a first location on one or more substrates, wherein the first one of the first dice includes a first component;
determining whether the first one of the first dice was implemented at the first location as directed;
subsequent to determining that the first one of the first dice was implemented at the first location as directed, determining that a first one of the second dice is present at a second position at a second column that is also within the first row and that satisfies a proximity criterion indicative of a maximum distance on the wafer that can separate matched or similar dice, the second set of columns including the second column; and
upon determining that the first one of the second dice is present at the second position at the second column that satisfies the proximity criterion, directing the pick and place head mechanism to implement the first one of the second dice from the second position at the second location, wherein the first one of the second dice includes a second component that is matched or similar to the first component due to the first and second type being matched or similar;
wherein, upon the first one of the first dice and the first one of the second dice being implemented on the one or more substrates, the one or more substrates constitutes or constitute the at least one part of the semiconductor system having the matched or similar components, the matched or similar components including the first and second components.

US Pat. No. 10,141,226

SELF-ALIGNED CONTACTS

Intel Corporation, Santa...

1. A nonplanar transistor comprising:a body;
a pair of spacers on the body;
a gate dielectric layer on a surface of the body between the pair of spacers and along sidewalls of the pair of spacers;
a gate electrode on the gate dielectric layer and between the pair of spacers, wherein the gate electrode is separated from the pair of spacers by portions of the gate dielectric layer along the sidewalls of the pair of spacers;
an insulating cap layer on the gate electrode between the pair of spacers and directly on the portions of the gate dielectric layer along the sidewalls of the pair of spacers; and
a pair of diffusion regions adjacent to the pair of spacers.

US Pat. No. 10,141,225

METAL GATES OF TRANSISTORS HAVING REDUCED RESISTIVITY

Taiwan Semiconductor Manu...

1. A method comprising:forming a transistor comprising:
forming a gate dielectric on a semiconductor region;
forming a gate electrode over the gate dielectric; and
forming a source/drain region extending into the semiconductor region;
forming a source/drain contact plug over and electrically coupling to the source/drain region; and
forming a gate contact plug over and in contact with the gate electrode, wherein at least one of the forming the gate electrode, the forming the source/drain contact plug, or the forming the gate contact plug comprises:
removing a hard mask between opposite portions of gate spacers;
forming a metal nitride barrier layer;
depositing a metal-containing layer over and in contact with the metal nitride barrier layer, wherein the metal-containing layer comprises at least one of a cobalt layer or a metal silicide layer, and wherein the metal nitride barrier layer and the metal-containing layer extend into an opening left by the removed hard mask; and
performing a planarization to remove excess portions of the metal nitride barrier layer and the metal-containing layer.

US Pat. No. 10,141,223

METHOD OF IMPROVING MICRO-LOADING EFFECT WHEN RECESS ETCHING TUNGSTEN LAYER

UNITED MICROELECTRONICS C...

1. A method for improving micro-loading effect when recess etching a tungsten layer, comprising:providing a semiconductor substrate having a main surface, wherein a plurality of trenches is formed in the semiconductor substrate;
blanket depositing a tungsten layer on the semiconductor substrate, wherein the plurality of trenches is filled with the tungsten layer;
subjecting the tungsten layer to a planarization process to form a planarization layer on the tungsten layer;
performing a first etching process to completely remove the planarization layer and partially remove the tungsten layer with an etch selectivity of planarization layer:tungsten layer=1:1; and
performing a second etching process to etch remainder of the tungsten layer until a top surface of the tungsten layer is lower than the main surface of the semiconductor substrate.

US Pat. No. 10,141,221

METHOD FOR MANUFACTURING THREE DIMENSIONAL STACKED SEMICONDUCTOR STRUCTURE AND STRUCTURE MANUFACTURED BY THE SAME

MACRONIX INTERNATIONAL CO...

1. A method of manufacturing a three-dimensional (3D) stacked semiconductor structure, comprising:forming a multi-layered stack above a substrate, and the multi-layered stack comprising a plurality of nitride layers and polysilicon layers arranged alternately;
forming a plurality of channel holes vertically to the substrate;
patterning the multi-layered stack to form linear spaces between the plurality of channel holes and vertical to the substrate, wherein the linear spaces extend downwardly to expose sidewalls of the plurality of nitride layers and the plurality of polysilicon layers;
replacing the plurality of polysilicon layers with insulating layers having air-gaps through the linear spaces; and
replacing the plurality of nitride layers with conductive layers through the linear spaces.

US Pat. No. 10,141,219

COMBINED PRODUCTION METHOD FOR SEPARATING A NUMBER OF THIN LAYERS OF SOLID MATERIAL FROM A THICK SOLID BODY

Siltectra GmbH, Dresden ...

1. A method for producing layers of solid material comprising:providing a solid body to be split into a number of layers of solid material, the solid body having a first level surface portion and a second level surface portion;
introducing or generating defects in the solid body using laser beams in order to determine a first detachment plane along which a first layer of solid material is separated from the solid body, the laser beams penetrating into the solid body via the second level surface portion;
providing a receiving layer for holding the layer of solid material on the second level surface portion of the solid body, the receiving layer being in the form of a polymer layer;
applying heat to the receiving layer in order to mechanically generate stresses in the solid body, the application of heat including cooling of the receiving layer to a temperature below ambient temperature, the cooling taking place such that the polymer layer undergoes a glass transition and such that due to the stresses a crack propagates in the solid body along the detachment plane, the crack separating the first layer of solid material from the solid body, wherein the second level surface portion is part of the first layer, wherein the first detachment plane is determined closer to the second level surface portion than to the first level surface portion;
introducing or generating defects in the solid body in order to determine a second detachment plane along which a second layer of solid material is separated from the solid body, then providing a second receiving layer for holding another layer of solid material on the solid body reduced by the first layer of solid material; and
applying heat to the second receiving layer in order to mechanically generate stresses in the solid body such that due to the stresses a crack propagates in the solid body along the second detachment plane, the crack separating the second layer of solid material from the solid body.

US Pat. No. 10,141,218

ROOM TEMPERATURE METAL DIRECT BONDING

INVENSAS BONDING TECHNOLO...

1. A method of bonding substrates, comprising:providing a first substrate having a first non-metallic region proximate to a first plurality of metallic pads;
providing a second substrate having a second non-metallic region proximate to a second plurality of metallic pads;
directly contacting the first non-metallic region with the second non-metallic region, wherein a first pad of the first plurality of metallic pads is spaced from a second pad of the second plurality of metallic pads by a gap after directly contacting the first non-metallic region with the second non-metallic region;
non-adhesively bonding the first non-metallic region to the second non-metallic region along an interface without an adhesive and without application of external pressure; and
after directly contacting the first non-metallic region with the second non-metallic region, directly contacting the first pad with the second pad to form a contact between the first pad and the second pad, the interface between the first non-metallic region and the second non-metallic region extending substantially to the contact.

US Pat. No. 10,141,213

APPARATUS FOR STORING AND HANDLING ARTICLE AT CEILING

DAIFUKU CO., LTD., Osaka...

1. An apparatus for storing and handling an article at a ceiling, comprising:an internal rail configured to hang on the ceiling;
a storage system configured to hang on the ceiling and including a shelf of a first row and a shelf of a second row disposed on both sides of the internal rail to face each other and a transport in/out port connected to any one of the shelf of the first row and the shelf of the second row; and
an internal transfer robot configured to be movably connected to the internal rail and convey the article between any one of the shelf of the first row and the shelf of the second row and the transport in/out port; and
a purge unit configured to supply purge gas to the article seated on the shelf of the first row and the shelf of the second row,
wherein the internal transfer robot includes:
a two-way sliding unit configured to slide a holding unit holding the article toward any one of the shelf of the first row and the shelf of the second row; and
an elevation-driving unit configured to elevate the two-way sliding unit along a height direction of the shelf of the first row and the shelf of the second row,
wherein the purge unit includes:
a gas tank configured to communicate with the article and providing the purge gas to the article;
a recovering pump configured to communicate with the article to recover the purge gas supplied to the article; and
a controller configured to operate the recovering pump when a predetermined time elapses after the purge gas is supplied to the article.

US Pat. No. 10,141,211

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE TRANSFER METHOD

EBARA CORPORATION, Tokyo...

1. A substrate processing apparatus, comprising:a substrate holder configured to hold a substrate;
a fixing unit configured to mount and remove the substrate on and from the substrate holder,
a substrate dryer configured to dry the substrate;
a robot configured to transfer the substrate at least between the fixing unit and the substrate dryer;
a processing bath configured to process the substrate while the substrate holder is holding the substrate such that the substrate is in a vertical orientation; and
a substrate transfer device including a grasping section configured to grasp the substrate holder, and a transferring section configured to transfer the substrate holder grasped by the grasping section,
wherein the substrate transfer device is configured to transfer the substrate holder at least between the fixing unit and the processing bath,
the grasping section is configured to rotate the substrate holder between the vertical orientation and a horizontal orientation, which is angularly offset from the vertical orientation while the substrate holder is holding the substrate, and
the transferring section is configured to transfer the substrate holder and the substrate while the substrate holder is holding the substrate from the processing bath to the fixing unit, with the substrate in the horizontal orientation, along a path that is above the processing bath.

US Pat. No. 10,141,210

PURGE MODULE AND LOAD PORT HAVING THE SAME

RORZE SYSTEMS CORPORATION...

1. A purge module comprising:a jig detachably attached to an upper side of a stage of a load port, the jig comprising a gas inlet for providing a wafer carrier with gas and a gas outlet for receiving gas from the wafer carrier;
a gas control box detachably attached to the load port to control gas flow; and
pipes connecting the jig and the gas control box,
wherein at least one of the gas inlet and the gas outlet further comprises a sealing member making contact with the wafer carrier, when the wafer carrier is disposed thereon, the sealing member including an elastic material;
a sealing protection member disposed surrounding the sealing member; and
wherein the sealing protection member is higher than the sealing member with respect to a surface of the jig.

US Pat. No. 10,141,198

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

1. An electronic package, comprising:a middle patterned conductive layer having a first surface, a second surface opposite to the first surface and a plurality of middle conductive pads;
a first redistribution circuitry disposed on the first surface of the middle patterned conductive layer and comprising a first patterned conductive layer, wherein the first patterned conductive layer has a plurality of first conductive elements, each of the first conductive elements has a first conductive pad and a first conductive via that form a T-shaped section, and each of the first conductive via connects the corresponding middle conductive pad and is tapering facing towards the corresponding middle conductive pad; and
a second redistribution circuitry disposed on the second surface of the middle patterned conductive layer and comprising a second patterned conductive layer, wherein the second patterned conductive layer has a plurality of second conductive elements, each of the second conductive elements has a second conductive pad and a second conductive via that form an inversed T-shaped section, and each of the second conductive via connects the corresponding middle conductive pad and is tapering facing towards the corresponding middle conductive pad.

US Pat. No. 10,141,196

POWER SEMICONDUCTOR DEVICE WITH THICK TOP-METAL-DESIGN AND METHOD FOR MANUFACTURING SUCH POWER SEMICONDUCTOR DEVICE

ABB Schweiz AG, Baden (C...

1. A method for manufacturing a power semiconductor device, the method comprising the following steps:providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side;
forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane (B; B?) parallel to the first main side;
forming an isolation layer on the first main side to cover the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane (A) parallel to the first main side;
after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and
thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel,
wherein the second plane (A) is at most 1 ?m further away from the wafer than the first plane (B; B?), wherein
the step of forming the metallization layer comprises:
a first step of forming a lower portion of the metallization layer on the first main side in the active cell area before the step of forming the isolation layer; and
a second step of forming an upper portion of the metallization layer on the lower portion of the metallization layer in the active cell area after the step of forming the isolation layer.

US Pat. No. 10,141,187

MASK PATTERN FORMING METHOD, FINE PATTERN FORMING METHOD, AND FILM DEPOSITION APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A mask pattern forming method comprising steps of:loading a substrate which has a thin film and a pattern on the thin film, into a process chamber, the pattern having a line and a space therein;
slimming the pattern using a first oxygen-containing gas plasma in the process chamber for a predetermined period of time such that the line is slimmed to have a predetermined width; and
forming an oxide film on the slimmed pattern and the thin film in the process chamber by performing a cycle of adsorbing an aminosilane based precursor on the thin film and the slimmed pattern and oxidizing the aminosilane based precursor on the thin film and the slimmed pattern using a second oxygen-containing gas plasma a predetermined number of times such that the deposited oxide film has a predetermined thickness,
wherein the steps of slimming the pattern and forming the oxide film are performed in the same process chamber, and
wherein temperatures at which the pattern is slimmed and at which the oxide film is formed on the pattern are 100 degrees C. or less.

US Pat. No. 10,141,185

OXIDE SEMICONDUCTOR, COATING LIQUID, METHOD OF FORMING OXIDE SEMICONDUCTOR FILM, SEMICONDUCTOR ELEMENT, DISPLAY ELEMENT, IMAGE DISPLAY DEVICE AND IMAGE DISPLAY SYSTEM

RICOH COMPANY, LTD., Tok...

1. An oxide semiconductor comprising an oxide having a layered structure expressed by an expression
wherein an atom A is a positive monovalent element, an atom Z is a positive divalent element, an atom B is a positive trivalent element, L is a positive integer, and mi and ni are independent integers greater than or equal to zero, that satisfy

US Pat. No. 10,141,182

MICROELECTRONIC SYSTEMS CONTAINING EMBEDDED HEAT DISSIPATION STRUCTURES AND METHODS FOR THE FABRICATION THEREOF

NXP USA, INC., Austin, T...

1. A method for fabricating a microelectronic system, comprising:obtaining a substrate having a tunnel therethrough:
attaching a microelectronic component to a frontside of the substrate at a location enclosing the tunnel utilizing a solder material having a first thermal conductivity; and
producing an embedded heat dissipation structure at least partially contained within the tunnel after attaching the microelectronic component to the substrate, producing comprising:
applying a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate;
curing the bond layer precursor material to form a thermally-conductive component bond layer in contact with the microelectronic component; and
formulating the bond layer precursor material such that, after curing, the thermally-conductive component bond layer has a second thermal conductivity substantially equivalent to or exceeding the first thermal conductivity.

US Pat. No. 10,141,180

SILICON WAFER AND METHOD FOR MANUFACTURING THE SAME

GLOBALWAFERS JAPAN CO., L...

1. A method of manufacturing a silicon wafer comprising:subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by a Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380° C., and kept at the maximum temperature for 5 to 60 seconds and then cooled at a cooling rate of 3 to 5° C./second, wherein the rapid thermal process is performed in an oxygen-containing atmosphere comprising oxygen gas having a partial pressure of 20 to 100%;
calculating a surface layer of the wafer having a thickness of not less X [?m] according to the following equations (1) to (3):
X [?m]=a [?m]+b [?m]  (1);
a [?m]=(0.0031×(said maximum temperature) [° C.]?3.1)×6.4×(cooling rate)?0.4 [° C./second]  (2); and
b [?m]=a/(solid solubility limit of oxygen) [atoms/cm3]/(oxygen concentration in substrate) [atoms/cm3]  (3); and
removing the surface layer having the thickness of not less than X,
to obtain a silicon wafer comprising a laser scattering tomography defect (LSTD) density of less than 1×10?1/cm2 and a slip dislocation length of 5 mm or less.

US Pat. No. 10,141,176

MULTI-REFLECTION MASS SPECTROMETER WITH DECELERATION STAGE

Thermo Fisher Scientific ...

1. A multi-reflection mass spectrometer comprising two ion mirrors spaced apart and opposing each other in an X direction, each mirror elongated generally along a drift direction Y, the X direction being orthogonal to the drift direction Y, and an ion injector for injecting ions as an ion beam into the space between the ion mirrors at an inclination angle to the X direction, wherein along a first portion of their length in the drift direction Y the ion mirrors converge with a first degree of convergence and along a second portion of their length in the drift direction Y the ion mirrors converge with a second degree of convergence or are parallel, the first portion of their length being closer to the ion injector than the second portion and the first degree of convergence being greater than the second degree of convergence.

US Pat. No. 10,141,175

QUASI-PLANAR MULTI-REFLECTING TIME-OF-FLIGHT MASS SPECTROMETER

LECO Corporation, St. Jo...

1. A multi-reflecting time-of-flight mass spectrometer comprising:two quasi-planar electrostatic ion mirrors extended along a drift Z-direction and formed of parallel electrodes, wherein said mirrors are separated by a field-free region;
a pulsed ion source to release ion packets at a small angle to an X-direction which is orthogonal to the drift Z-direction, such that the ion packets are reflected between the ion mirrors and drift along the drift Z-direction direction;
a receiver to receive the ion packets;
wherein said mirrors are positioned to provide time-of-flight focusing on said receiver and provide spatial focusing in a Y-direction orthogonal to both the drift Z-direction and the ion injection X-direction;
wherein at least one of said mirrors has a periodic feature providing modulation of electrostatic field along the drift Z-direction for the purpose of periodic spatial focusing of the ion packets in the Z-direction; and
wherein said periodic feature comprises at least one of the following:
at least one mirror electrode having an opening varying in height in the Y-direction;
at least one mirror electrode with varying width along the X-direction; or
a set of periodic lenses incorporated into an internal electrode of at least one of said mirrors.

US Pat. No. 10,141,173

SYSTEMS FOR SEPARATING IONS AND NEUTRALS AND METHODS OF OPERATING THE SAME

Rapiscan Systems, Inc., ...

1. A mass spectrometer system comprising:a sample injection device defining a sample injection aperture;
an ion trap defining an ion outlet aperture, said ion trap coupled to said sample injection device;
a detector positioned downstream of said ion outlet aperture, wherein the detector is positioned in a detector enclosure defining a detector chamber;
an ion source coupled to said ion trap, said ion source configured to ionize a sample injected into said ion trap and generate a plurality of ionized molecules within said ion trap, said ion trap configured to maintain said plurality of ionized molecules therein while a plurality of neutral molecules migrate out of said ion trap, and into the detector chamber, until a predetermined pressure is attained in said ion trap;
a first vacuum pump coupled to the ion trap wherein the first vacuum pump is configured to decrease a pressure in the ion trap; and
a second vacuum pump coupled to the detector chamber wherein the second vacuum pump is configured to decrease a pressure in the detector chamber such that a pressure in the detector chamber induced by the neutral molecules therein decays at a predetermined rate.

US Pat. No. 10,141,165

PLASMA PROCESSING APPARATUS AND SAMPLE STAGE THEREOF

HITACHI HIGH-TECHNOLOGIES...

1. A plasma processing apparatus comprising: a processing chamber disposed in a vacuum vessel in which a wafer located therein is processed using plasma generated therein; a sample stage disposed in the processing chamber on which the wafer is mounted on a top surface thereof; an electrode disposed in the sample stage which is constituted by an electrically conductive material; a radio frequency power supply which is electrically connected to the electrode in the sample stage and supplies the radio frequency power for generating a bias potential above the wafer mounted on the sample stage to the electrode; a plurality of heater units each of which are respectively disposed in each of a plurality of areas in a cylindrical interior of the sample stage, the plurality of areas including a central region of the cylindrical interior of the sample stage and a plurality of ring-shaped regions which are disposed on an outer circumference of the central region and surrounds the central region; one or more DC power supplies which is connected to each of the plurality of heater units disposed in each of the ring-shaped regions and is configured to supply DC power to each of the plurality of heater units; a plurality of arcuate heaters which constitutes each of the plurality of heater units disposed in each of the plurality of ring-shaped regions and is circumferentially disposed around the central region of the sample stage, the plurality of arcuate heaters in each of the heater units in each of the plurality of the ring-shaped regions being connected in series to the one or more DC power supplies which is connected to the one of the plurality of heater units disposed in the one or more ring-shaped regions and constituting a circuit; wherein each of the plurality of arcuate heaters constituting the circuit in the each of the heater units disposed in each of the plurality of the ring-shaped regions is connected to the adjacent arcuate heater by each of a plurality of connection portions and has a same length forming a same circumferential angle around the central region, and, the each of the heater units disposed in each of the plurality of the ring-shaped regions constitutes a loop, and the arcuate heaters disposed in one of the ring-shaped region closer to the center region form greater circumferential angle around the central region than those of the arcuate heaters disposed in the ring-shaped region outwardly located, and the apparatus further comprising: a plurality of adjusting devices each of which is connected with the circuit in front and behind of each of the plurality of the arcuate heaters in parallel thereto, the plurality of adjusting devices are configured to be capable of adjusting amounts of current from the one or more DC power supplies flowing through the each of the plurality of arcuate heaters to which the each of the plurality of adjusting devices is connected in parallel; a control unit which is configured to be enable to adjust amounts of heat generated by the one of the plurality of heater units disposed in the one or more ring-shaped regions by adjusting operations of the plurality of adjusting devices.

US Pat. No. 10,141,160

APPARATUS OF PLURAL CHARGED-PARTICLE BEAMS

HERMES MICROVISION, INC.,...

1. A multi-beam apparatus for observing a surface of a sample, comprising:an electron source;
a condenser lens below said electron source;
a source-conversion unit below said condenser lens;
an objective lens below said source-conversion unit;
a deflection scanning unit below said source-conversion unit;
a sample stage below said objective lens;
a beam separator below said source-conversion unit; and
a detection unit above said beam separator and comprising a secondary projection imaging system and an electron detection device with a plurality of detection elements,
wherein said electron source, said condenser lens, said source-conversion unit, said objective lens, said deflection scanning unit and said beam separator are aligned with a primary optical axis of said apparatus, said sample stage is configured to sustain said sample so that said surface faces to said objective lens, said detection unit is aligned with a secondary optical axis of said apparatus, and said secondary optical axis is not parallel to said primary optical axis,
wherein said plurality of detection elements is placed on a detection plane, said secondary projection imaging system comprises a zoom lens, an anti-scanning deflection unit and a projection lens,
wherein said electron source is configured to generate a primary electron beam along said primary optical axis, said condenser lens is configured to focus said primary electron beam, said source-conversion unit is configured to change said primary electron beam into a plurality of beamlets and make said plurality of beamlets form a plurality of first images of said electron source, said objective lens is configured to focus said plurality of beamlets to image said plurality of first images onto said surface and therefore form a plurality of probe spots thereon respectively, and said deflection scanning unit is configured to deflect said plurality of beamlets to scan said plurality of probe spots respectively over a plurality of scanned regions within an observed area on said surface,
wherein a plurality of secondary electron beams is generated by said plurality of probe spots respectively from said plurality of scanned regions and then incident to said objective lens, said objective lens is configured to in passing focus said plurality of secondary electron beams, and said beam separator is configured to deflect said plurality of secondary electron beams to enter said secondary projection imaging system along said secondary optical axis,
wherein said zoom lens is configured to focus said plurality of secondary electron beams onto a transfer plane, said transfer plane is between said zoom lens and said projection lens, and said plurality of secondary electron beams is configured to form a first crossover between said zoom lens and said transfer plane,
wherein said projection lens is configured to focus said plurality of secondary electron beams onto said detection plane, said plurality of secondary electron beams is configured to form a second crossover between said projection lens and said detection plane and a plurality of secondary-electron spots on said detection plane, said plurality of secondary-electron spots is inside said plurality of detection elements respectively, consequently a corresponding relationship between said plurality of probe spots and said plurality of detection elements is established, and accordingly each detection element is configured to generate an image signal of one corresponding scanned region,
wherein said anti-scanning deflection unit is configured to deflect said plurality of secondary electron beams in step with said plurality of probe spots scanning over said plurality of scanned regions to remain positions of said plurality of secondary-electron spots and thereby keeping said corresponding relationship all the time,
wherein an imaging magnification of said zoom lens is configured to be adjusted to keep said corresponding relationship when observing said surface in different conditions.

US Pat. No. 10,141,150

HIGH CURRENT ONE-PIECE FUSE ELEMENT AND SPLIT BODY

LITTELFUSE, INC., Chicag...

1. A high breaking capacity fuse comprising:a first outer insulative layer, the first outer insulative layer having a first cavity formed therein;
a second outer insulative layer disposed on the first outer insulative layer, the second outer insulative layer having a second cavity formed therein;
a cup-shaped first ceramic insert disposed within the first cavity;
a cup-shaped second ceramic insert disposed within the second cavity, wherein the first and second ceramic inserts fit together to define a chamber; and
a single piece fusible element disposed between the first outer insulative layer and the second outer insulative layer, the single piece fusible element comprising a first terminal portion, a second terminal portion, a fusible element portion having a plurality of rolls along its longitudinal axis, a first mid portion connecting the fusible element portion to the first terminal portion, and a second mid portion connecting the fusible element to the second terminal portion, wherein the fusible element portion is disposed at least partially within the chamber, wherein the first terminal portion extends along at least one outer surface of the second outer insulative layer, and the second terminal portion extends along at least one outer surface of the second outer insulative layer;
wherein each of the first and second terminal portions has grooves formed in opposing sides thereof, and wherein the first outer insulative layer includes tongue portions formed in a top edge thereof, the tongue portions disposed within the grooves.

US Pat. No. 10,141,149

THIN FILM FUSE

Continental Automotive Sy...

1. A thin film fuse comprising:a non-conductive substrate having a surface;
first and second substantially planar conductors, each conductor having a corresponding thickness and a peripheral edge, the planar conductors being disposed on the substrate's surface, the first conductor having a substantially rectangular-shaped first portion from which extends a substantially key-hole shaped second portion, the second conductor being substantially oarlock-shaped and partially surrounding the substantially key-hole shaped second portion of the first substantially planar conductor, the substantially oarlock-shaped portion having a break through which extends a part of the substantially rectangular-shaped first portion of the first conductor, the peripheral edges of the substantially key-hole shaped second portion and the substantially oarlock-shaped second conductor being separated from each other by a substantially C-shaped gap having a predetermined substantially uniform-width, the gap being located between the key-hole shaped portion and the oarlock-shaped portion, the gap also having a predetermined gap length;
a thin metallic film disposed on the top of the substantially key-hole shaped second portion and the substantially oarlock-shaped second conductor and extending across the substantially uniform width gap.

US Pat. No. 10,141,135

KEYBOARD

PRIMAX ELECTRONICS LTD, ...

1. A keyboard, comprising: a key, comprising: a keycap, exposed outside the keyboard and comprising: a first hook, disposed on an inner surface of the keycap and located on an outer side of the keycap, wherein the first hook has a first opening; and a second hook, disposed on the inner surface of the keycap and located in a central area of the keycap, wherein the second hook has a second opening; and a balance bar, disposed below the keycap and fastened in the first opening and the second opening; a switch circuit board, located below the key and used to be triggered by the key to output a key signal; and a base plate, disposed below the switch circuit board, connected to the balance bar, and used to carry the key, wherein the first opening has a round shape, and the second opening has an elliptic shape; wherein a width of the first opening is less than a width of the second opening, so that the balance bar is fastened in the first opening and the second opening.