US Pat. No. 11,115,147

MULTICHIP FAULT MANAGEMENT

Groq, Inc., Mountain Vie...


1. A network of interconnected processing circuit chips, a processing circuit chip in the network comprising:an internal signal ring;
an external signal ring; and
a plurality of circuits coupled to the internal and external signal rings, the plurality of circuits configured to:capture, via the external signal ring, external fault data originating from a first of the processing circuit chips in the network and comprising information about a fault detected at the first processing circuit chip,
pass the captured external fault data via the external signal ring to a first communication path outside of the processing circuit chip for conveyance of the external fault data to one of the processing circuit chips in the network,
transfer, from the internal signal ring to the external signal ring, internal fault data originating from an internal circuit of the processing circuit chip and comprising information about another fault detected at the internal circuit,
pass the internal fault data via the external signal ring to a second communication path outside of the processing circuit chip for conveyance of the internal fault data to a second of the processing circuit chips,
receive, from the second processing circuit chip, a query for determining an origin of the fault, and
transfer the query via the external signal ring to a control circuit of the processing circuit chip, the control circuit configured to:determine a validity of the query,
transfer the query via the external signal ring to an inter-chip circuit of the plurality of circuits, in response to the determined validity indicating the query is not intended for the processing circuit chip, and
pass the query from the inter-chip circuit to a third communication path outside of the processing circuit chip for conveyance of the query to the first processing circuit chip.



US Pat. No. 11,115,146

OPTICAL SIGNAL DEMULTIPLEXING DEVICE, OPTICAL SIGNAL RECEPTION DEVICE, AND OPTICAL SIGNAL DEMULTIPLEXING METHOD

NEC CORPORATION, Tokyo (...


1. An optical demultiplexing device comprising:a first optical coupler configured to branch an optical signal in which signals having a plurality of wavelength intervals different from one another are multiplexed by the number of wavelength intervals;
a plurality of band division units arranged so as to correspond to each of the plurality of wavelength intervals, the plurality of band division units generating, for each of the wavelength intervals, a band division signal in which a signal band of an optical signal branched by the first optical coupler is divided by a predetermined bandwidth and an odd channel and an even channel are separated from each other in each of the wavelength intervals;
a plurality of multiplexing units arranged, for each of the signal bands that have been divided, so as to correspond to the odd channel and the even channel, the plurality of multiplexing units multiplexing, for each of the signal bands that have been divided, the band division signals, output from the band division units, including odd channels of the respective wavelength intervals, and multiplexing, for each of the signal bands that have been divided, the band division signals including the even channels of the respective wavelength intervals;
a plurality of second optical couplers arranged, for each of the signal bands that have been divided, so as to correspond to the odd channel and the even channel, the plurality of second optical couplers branching each of a multiplexed signal including odd channels of the respective wavelength intervals multiplexed by using each of the multiplexing units and a multiplexed signal including even channels of the respective wavelength intervals into a plurality of communication devices; and
a controller configured to control the band division units,
wherein each of the plurality of band division units includes a wavelength selective switch, and
wherein the controller controls the wavelength selective switch based on information indicating a signal arrangement of the signals in the respective wavelength intervals in the optical signal, causes the wavelength selective switch to output a signal of a wavelength band in which a signal of a corresponding wavelength interval is present to the multiplexing units, and causes the wavelength selective switch to cut off a signal of a wavelength band in which a signal of the corresponding wavelength interval is not present.

US Pat. No. 11,115,145

METHOD FOR OPERATING IOT IN CELLULAR SYSTEM AND SYSTEM THEREFOR

Samsung Electronics Co., ...


1. A method of a base station in a cellular system, the method comprising:generating, by the base station, a master information block (MIB) including operation mode information indicating an operation mode, among a plurality of operation modes for narrow band internet of things (IoT) communication; and
transmitting, by the base station, the MIB to a user equipment (UE),
wherein the plurality of operation modes include a first in-band mode indicating that the cellular system and a narrow band IoT system share a same cell identifier (ID), a second in-band mode indicating that the cellular system and the narrow band IoT system have a different cell ID, a guard-band mode indicating a guard-band deployment, and a standalone mode indicating a standalone deployment.

US Pat. No. 11,115,144

CELL SEARCH METHOD IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR

LG ELECTRONICS INC., Seo...


1. A method of performing, by a user equipment (UE), cell search in a wireless communication system, the method comprising:receiving, from a base station (BS), a Narrowband Primary Synchronization Signal (NPSS) and a Narrowband Secondary Synchronization Signal (NSSS); and
acquiring time synchronization and frequency synchronization with the BS and detecting an identifier of the BS based on the NPSS and the NSSS,
wherein the NPSS is transmitted in a sixth subframe of a each frame of a plurality of frames, and
wherein the NSSS is transmitted in a tenth subframe of a every other frame of the plurality of frames.

US Pat. No. 11,115,143

ELECTRONIC APPARATUS WITH DATA TRANSCEIVING MECHANISM AND DATA TRANSCEIVING METHOD

Realtek Semiconductor Cor...


1. An electronic apparatus with a data transceiving mechanism, comprising:a processing circuit, configured to generate a data request;
a transceiving apparatus, coupled to the processing circuit, the transceiving apparatus configured to transmit the data request to at least one target electronic apparatus, wherein the data request is for requesting the target electronic apparatus to generate data corresponding to the data request; and
a monitoring circuit, coupled to the processing circuit and the transceiving apparatus, the monitoring circuit configured to calculate data-related parameters for the data received by the transceiving apparatus within a predetermined time period after the transceiving apparatus transmits the data request;
wherein if the data-related parameter does not match a predetermined rule, the monitoring circuit substitutes the processing circuit to complete data transaction corresponding to the data request and to generate notification message to the processing circuit; and if the data-related parameter matches the predetermined rule, the monitoring circuit does not substitute the processing circuit to complete the data transaction corresponding to the data request and to generate the notification message.

US Pat. No. 11,115,142

TIMING SYNCHRONIZATION SERVICE AND DISTRIBUTION SYSTEM

Equinix, Inc., Redwood C...


1. A method comprising:sending, by a first probing device in a network comprising a plurality of probing devices, and to a second probing device of the plurality of probing devices in the network, a timestamp for the first probing device, wherein the first probing device and the second probing device are included in a probing device pair;
receiving, by the first probing device, and from the second probing device, a timestamp for the second probing device;
determining, by the first probing device, a timestamp offset between the timestamp for the first probing device and the timestamp for the second probing device;
receiving, by the first probing device, an independent timestamp offset for the probing device pair;
when the timestamp offset is classified as a valid timestamp offset based on a difference between the timestamp offset and the independent timestamp offset for the probing device pair, determining, by the first probing device, based at least in part on the timestamp for the first probing device and the timestamp for the second probing device, an upper-bound delta time and a lower-bound delta time for the probing device pair;
calculating, by the first probing device, and based at least in part on the upper-bound delta time and the lower-bound delta time for the probing device pair, a slope value and an intercept value for the first probing device; and
sending, by the first probing device, and to a local system master clock, the slope value and the intercept value for the first probing device.

US Pat. No. 11,115,141

WIRED COMMUNICATIONS DEVICE AND METHOD FOR OPERATING A WIRED COMMUNICATIONS DEVICE

NXP B.V., Eindhoven (NL)...


1. A method for operating a wired communications device, the method comprising:generating a random data sequence based on a thermal noise within the wired communications device;
including a frame boundary bit sequence and the random data sequence as a preamble of a bit stream, wherein the preamble including the random data sequence is not scrambled;
encoding the bit stream into an encoded bit stream; and
transmitting the encoded bit stream using the wired communications device.

US Pat. No. 11,115,140

SIGNAL STRENGTH MEASUREMENT METHOD, AND RELATED APPARATUS AND SYSTEM

HUAWEI TECHNOLOGIES CO., ...


1. A signal strength measurement method, comprising:receiving first indication information from a network device, wherein the first indication information comprises first sub-information, second sub-information, and third sub-information, the first sub-information is used to indicate a measurement period for measurement, the measurement period comprises at least one second time unit, the second time unit comprises at least two first time units, the third sub-information is used to indicate an offset of a start position of a second time unit for measurement relative to a start position of the measurement period, and the second sub-information is used to indicate an offset of a start position of a first time unit for measurement in the measurement period relative to the start position of the second time unit for measurement;
determining a measurement resource based on the first indication information, wherein the measurement resource is determined in the measurement period based on the start position of the first time unit and the start position of the second time unit;
performing signal strength measurement on a signal on the measurement resource, to obtain a measurement result; and
sending the measurement result to the network device.

US Pat. No. 11,115,138

METHOD FOR ANTENNA OCCLUSION DETECTION

Apple Inc., Cupertino, C...


1. An electronic device comprising:a transmitter;
a receiver;
an antenna coupled to the transmitter and to the receiver;
one or more data processors; and
a non-transitory computer readable storage medium containing instructions which, when executed on the one or more data processors, cause the one or more data processors to perform actions including:identifying a transmission time at which the transmitter transmitted a signal;
detecting a response signal received at the receiver subsequent to the transmission time;
determining, based at least in part on the response signal and on the transmission time, one or more response-signal characteristics;
determining, based at least in part on the one or more response-signal characteristics, that the antenna is at least partly blocked from emitting or receiving signals; and
in response to determining that the antenna is at least partly blocked:identifying a subset of antennas of the electronic device that does not include the antenna; and
performing a directionality analysis using the subset of antennas to identify a direction of another device relative to the electronic device.



US Pat. No. 11,115,137

METHOD AND ELECTRONIC TESTING DEVICE FOR DETERMINING OPTIMAL TEST CASE FOR TESTING USER EQUIPMENT

SAMSUNG ELECTRONICS CO., ...


1. A method comprising:determining, in a determination by an electronic testing device, one or more locations in a cellular network where a test case is to be executed, a time at which the test case is to be executed at the one or more locations, a number of times the test case is to be executed at the one or more locations, and/or a type of a test equipment on which the test case is to be executed;
determining, by the electronic testing device, a test context for testing a user equipment based on at least one of the one or more locations where the test case is to be executed, the time at which the test case is to be executed at the one or more locations, the number of times the test case is to be executed at the one or more locations, and the type of the test equipment on which the test case is to be executed;
determining, by the electronic testing device from a test case repository, an optimal test case for testing the user equipment, based on the test context; and
executing, by the electronic testing device, the optimal test case to test the user equipment.

US Pat. No. 11,115,136

METHOD FOR CALIBRATING AN ARRAY ANTENNA IN A WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREOF

LG ELECTRONICS INC., Seo...


1. A method of calibrating an array antenna, the method performed by an apparatus for calibrating an array antenna in a wireless communication system comprising:a first step of transmitting a radio signal through a first antenna and a second antenna determined among a plurality of antennas included in the array antenna;
a second step of measuring the radio signal through a specific coupling antenna of a plurality of coupling antennas adjacent to the plurality of antennas;
a third step of estimating an error of the second antenna based on a result of the measurement of the radio signal; and
a fourth step of calibrating the second antenna based on the error,
wherein the first step to the fourth step are repeatedly performed until a calibration of the plurality of antennas is completed,
wherein the first antenna is a reference antenna or the second antenna on which the calibration has already been performed, and
wherein the second antenna is an antenna which is adjacent to the first antenna and on which the calibration has not been performed.

US Pat. No. 11,115,135

SIGNAL SENDING METHOD FOR TERMINAL DEVICE AND TERMINAL DEVICE

HUAWEI TECHNOLOGIES CO., ...


1. A Multiple Input Multiple Output (MIMO) Over The Air (OTA) performance test system, comprising a base station simulator, a channel emulator, and a terminal device, wherein:the base station simulator is configured to send multiple streams of downlink test signals to a channel emulator through multiple downlink ports;
the channel emulator is configured to:perform channel emulation processing on the multiple streams of received downlink test signals according to a complex number pattern of each multiple receive antennas of a terminal device, a downlink radiation channel inverse matrix, and a specified downlink channel fading model, and
send the multiple streams of processed downlink test signals to the terminal device in an anechoic chamber by using multiple downlink antennas in the anechoic chamber; and

the terminal device is configured to:receive, by using the multiple receive antennas, the multiple streams of processed downlink test signals sent by the channel emulator, and
feedback an acknowledgement message to the base station simulator according to each stream of received processed downlink test signal, wherein the acknowledgement message fed back according to the stream of processed downlink test signal includes information for facilitating notifying the base station simulator whether the terminal device correctly demodulates the processed downlink test signal, wherein

the base station simulator is further configured to determine a downlink throughput of the terminal device according to a quantity of streams of downlink test signals that are sent and a quantity of pieces of acknowledgement information, among received acknowledgement messages, indicating that the terminal device performs correct demodulation and the system further comprises at least a first signal analyzer configured to determine the complex number pattern of each receive antenna; and
the channel emulator is further configured to obtain the complex number pattern of each receive antenna from the first signal analyzer, and
the terminal device is further configured to sequentially transmit a monophonic signal according to a specified sequence by using all of the multiple receive antennas; and
the first signal analyzer is configured to perform the following for each receive antenna:separately measuring amplitudes and phases of the monophonic signal on an in-phase I channel and a quadrature Q channel in each measurement direction of a three-dimensional radiation spherical surface, wherein the monophonic signal is transmitted by the receive antenna; and
obtaining the complex number pattern of the receive antenna according to the amplitudes and the phases, obtained by means of measurement specific to the receive antenna, on the I channel and the Q channel in each measurement direction of the three-dimensional radiation spherical surface.


US Pat. No. 11,115,134

TEST METHOD IMPLEMENTED BY AN APPARATUS COMPRISING AT LEAST TWO RADIO COMMUNICATION DEVICES

SAGEMCOM BROADBAND SAS, ...


1. A method for testing a communication device comprising a controller and at least two radio-communication devices disposed in the communication device and coupled to the controller, each of said at least two radio-communication devices including a transmitter and a receiver, wherein a first radio-communication device of the at least two radio-communication devices uses a first communication protocol and a second radio-communication device of the at least two radio-communication devices uses a second communication protocol different from the first communication protocol and said at least two radio-communication devices share the same frequency band, the method comprising:transmitting, by a transmitter to be tested of the first radio-communication device of the at least two radio-communication devices and configured to use the first communication protocol, a test signal in a transmission channel of the first radio-communication device of the at least two radio-communication devices, wherein the test signal is signed in the form of a sequence of predetermined time and/or frequency bits and/or transmitted power levels that the receiver can distinguish from transmission schemes that surrounding transmitters are likely to use, and
detecting, by the receiver to be tested of the second radio-communication device and configured to use the second communication protocol, the test signal in a reception channel of the second radio-communication device of the at least two radio-communication devices, wherein
a frequency range of the transmission channel overlaps with a frequency range of the reception channel, and wherein the detecting includes noting triggering, by said receiver of the second radio-communication device, of an event caused by presence of said test signal in the reception channel, the event including a channel in operation of the second radio-communication device or presence of an error message.

US Pat. No. 11,115,133

METHOD AND APPARATUS FOR A WIRELESS CHARGING AND COMMUNICATION SYSTEM


1. A communicator and energy transmission circuit coupled with an electrical power source, comprising:a controller, the controller including a first energy channel and a second energy channel, wherein the controller selectively provides electrical energy to the first energy channel and the second energy channel;
a first piezoelectric transducer, the first piezoelectric transducer coupled with the first energy channel, and the first piezoelectric transducer adapted to transmit a first output pressure wave energy emission;
a first electromagnetic energy transducer, the first electromagnetic energy transducer coupled with the second energy channel, and the first electromagnetic energy transducer adapted to transmit a first output electromagnetic wave energy emission; and
a plurality of piezoelectric transducers, wherein each piezoelectric transducer is communicatively coupled with the controller and each piezoelectric transducer receives and converts external pressure wave energy into a component of input electromagnetic energy, and each piezoelectric transducer partially delivers the input electromagnetic energy to the controller, and at least one piezoelectric transducer delivers an information-bearing component of the external pressure wave energy of the input electromagnetic energy delivered to the controller.

US Pat. No. 11,115,132

METHOD AND APPARATUS FOR TRANSMITTING ELECTRIC SIGNALS OR POWER USING A FIBER OPTIC CABLE

BAKER HUGHES OILFIELD OPE...


1. A method for transmitting an optical signal and an electrical signal and/or power in a borehole penetrating the earth, the method comprising:transmitting the optical signal using a hybrid fiber optic cable disposed in the borehole, the hybrid fiber optic cable comprising an optical fiber for transmitting the optical signal; and
transmitting the electrical signal and/or power using the hybrid fiber optic cable, the hybrid fiber optic cable further comprising (i) a first electrically conductive sheath circumferentially surrounding the optical fiber and in electrical communication with a first electrical connector and (ii) a second electrically conductive sheath circumferentially surrounding the first electrically conductive sheath and in electrical communication with a second electrical connector for transmitting the electrical signal and/or power.

US Pat. No. 11,115,131

SYSTEM AND METHOD FOR CRYOGENIC OPTOELECTRONIC DATA LINK

SeeQC Inc., Elmsford, NY...


1. An optoelectronic modulator, comprising:a sheet of graphene deposited on a surface of an optical waveguide, configured to detectably modulate optical rays in response to an alteration of a Fermi energy of the sheet of graphene due to an electronic modulation signal of less than 1 V, applied across the sheet of graphene to produce a modulated optical signal; and
an optical port comprising the optical waveguide, configured to interface with the modulated optical signal, and provide an optical interaction between the optical rays and the sheet of graphene,
wherein the optical waveguide comprises a fiber optic.

US Pat. No. 11,115,130

WAVELENGTH CONTROL AND MONITOR FOR DENSE WAVELENGTH DIVISION MULTIPLEXING (DWDM) SILICON PHOTONIC RECEIVER

Hewlett Packard Enterpris...


1. A multi-channel dense-wavelength-division-multiplexing (DWDM) silicon photonic receiver, comprising:an optical receiver, wherein the optical receiver comprises:a microring drop filter (MDF) having an incident optical wavelength corresponding to a wavelength from multiple wavelengths for multiple DWDM channels; and
automatic gain control (AGC) circuitry; and

circuitry to control and monitor a resonant wavelength of the MDF in real-time and in a manner that compensates for deviation between the resonant wavelength of the MDF and the incident optical wavelength of the MDF, the circuitry comprising a wavelength monitor to detect signals from the optical receiver indicating the resonant wavelength of the MDF;
wherein the circuitry comprising the wavelength monitor includes a reused portion of the AGC circuitry.

US Pat. No. 11,115,129

OPTICAL RECEIVER, OPTICAL TERMINAL, AND OPTICAL COMMUNICATION SYSTEM

MITSUBISHI ELECTRIC CORPO...


1. An optical receiver comprising:a pre-amplifier to convert a current signal, into which an input optical signal is converted, into a voltage signal;
a limiting amplifier to amplify and limit an amplitude of the voltage signal;
a transmission line connecting the pre-amplifier with the limiting amplifier;
an alternating current coupling capacitor inserted in a middle of the transmission line or at an end of the transmission line;
a termination circuit connected with the transmission line, to switch to a first resistance or to a second resistance higher than the first resistance in response to a switching signal; and
an alternating current load connected with the transmission line, the alternating current load being open in a first-frequency range of the voltage signal and having a resistance enabling impedance matching with the pre-amplifier and the transmission line in a second-frequency range of the voltage signal, wherein
the termination circuit and the alternating current load are electrically connected in parallel, and
the second-frequency range of the voltage signal is higher than the first-frequency range of the voltage signal.

US Pat. No. 11,115,128

OPTICAL TRANSMISSION DEVICE, TRANSMISSION SYSTEM, AND CONTROL METHOD FOR TRANSMISSION SYSTEM

NEC CORPORATION, Tokyo (...


1. An optical transmission device comprising:an output branching unit that multiplexes an added main signal and dummy light and outputs the multiplexed signal to an optical transmission line;
a wavelength adjustment unit that adjusts a wavelength band of the dummy light;
a signal detection unit that inputs an optical signal to be output by the output branching unit, detects a wavelength band of an added main signal, and outputs a detection result; and
a control unit that controls the wavelength adjustment unit according to a detection result of the signal detection unit, wherein
the output branching unit selects the wavelength band of the added main signal, outputs a signal of the selected wavelength band to the signal detection unit, and outputs the signal of the selected wavelength band to the optical transmission line in response to the wavelength adjustment unit controlling the wavelength band of the dummy light.

US Pat. No. 11,115,127

LASER COMMUNICATION SYSTEM AND LASER COMMUNICATION METHOD

MITSUBISHI HEAVY INDUSTRI...


1. A laser communication system comprising:a first communication station; and
a second communication station configured to carry out a laser optical communication with the first communication station,
wherein the first communication station comprises a high-power laser oscillator configured to generate a high-power laser beam which can be used to remove a solid body.

US Pat. No. 11,115,126

FIBER COMMUNICATION SYSTEMS AND METHODS

Cable Television Laborato...


1. An optical communication network for a passive optical network (PON) system architecture, comprising:an optical hub including at least one parent seed laser source and at least one optical line terminal (OLT) configured to transmit a downstream signal of the parent seed laser source, wherein the downstream signal includes a plurality of spaced wavelength channels;
an optical transport medium configured to carry the downstream signal from the optical hub; and
a plurality of distributed optical network units (ONUs) operably coupled to the optical transport medium, each ONU of the plurality of distributed ONUs (i) configured to receive at least one channel of the plurality of spaced wavelength channels, and (ii) including at least one child laser source injection locked to the parent seed laser source,
wherein each ONU comprises (i) an optical circulator configured to receive a linewidth of the parent laser source and inject the received linewidth into a respective child laser source of the ONU, (ii) an optical receiver configured to perform homodyne detection to detect the at least one channel received at the respective ONU.

US Pat. No. 11,115,125

MONOLITHIC INTEGRATED COHERENT TRANSCEIVER

SIFOTONICS TECHNOLOGIES C...


1. A monolithic coherent transceiver, comprising:a first input port to receive an optical input, the optical input comprising a carrier modulated by a signal through a modulation scheme;
a second input port to receive an optical local oscillation (LO), a frequency of the optical LO substantially equal to a frequency of the carrier;
a LO splitter to split the optical LO into a first LO and a second LO with a splitting ratio between the first LO and the second LO;
a coherent receiver module (CRM) to detect the signal based on the optical input and the first LO;
a third input port to receive an electrical modulation signal;
a coherent transmitter module (CTM) to generate an optical output signal based on the second LO and the electrical modulation signal; and
an output port to transmit the optical output signal,
wherein the modulation scheme comprises polarization multiplexed quadrature amplitude modulation (PM-QAM) or polarization multiplexed quadrature phase shift keying (PM-QPSK),
wherein the CTM comprises:a first IQ modulator configured to modulate, based on a first half of information represented by the electrical modulation signal, the second LO into a first portion of the optical output signal;
a second IQ modulator configured to modulate, based on a second half of the information represented by the electrical modulation signal, the second LO into a second portion of the optical output signal; and
a polarization beam rotator-combiner (PBRC) configured to combine the first portion of the optical output signal and the second portion of the optical output signal into the optical output signal,

wherein the first portion of the optical output signal is combined as a transverse electric (TE) component of the optical output signal, and wherein the second portion of the optical output signal is combined as a transverse magnetic (TM) component of the optical output signal,
wherein each of the first and second IQ modulators comprises:an I-arm comprising a first Mach-Zehnder modulator (MZM) and configured to generate an I-arm output;
a Q-arm comprising a second MZM and configured to generate a Q-arm output;
a 3 dB coupler to combine the I-arm output and the Q-arm output into an IQ output;
a monitoring photodiode (MPD) to monitor a power of the IQ output; and
an IQ phase tuner configured to tune, based on a reading of the MPD, a phase difference between the I-arm output and the Q-arm output so that the phase difference is substantially 90 degrees,

wherein each of the first and second MZMs comprises a dual-drive push-pull configuration, and wherein the dual-drive push-pull configuration comprises two serpentine optical paths, and
wherein each of the two serpentine optical paths comprises a plurality of p-n junction diodes connected in parallel, and wherein each of the first and second MZMs comprises an electrical pad to receive a direct-current bias voltage that biases the plurality of p-n junction diodes.

US Pat. No. 11,115,124

ADAPTIVE SCHEDULING FOR PERIODIC DATA TRAFFIC IN AN OPTICAL COMMUNICATIONS NETWORK FOR A WIRELESS COMMUNICATIONS SYSTEM (WCS)


1. An optical communications network, comprising:a plurality of optical network units (ONUs) each configured to communicate periodic data traffic in a plurality of scheduled periods, each of the plurality of scheduled periods beginning at a scheduled start time that is different among the plurality of scheduled periods and lasting for a scheduled duration that is identical among the plurality of scheduled periods; and
an optical line terminator (OLT) comprising:a control circuit configured to:determine that a schedule misalignment exists in a selected scheduled period among the plurality of scheduled periods associated with any of the plurality of ONUs;
determine a temporal step based on the determined schedule misalignment; and
adjust the scheduled start time of one or more of the plurality of scheduled periods succeeding the selected scheduled period based on the temporal step to reduce the schedule misalignment to below a predefined threshold; and

an OLT interface coupled to the plurality of ONUs and configured to provide the adjusted scheduled start time to the any of the plurality of ONUs, wherein:
the OLT interface is further configured to receive an indication indicating the schedule misalignment from the any of the plurality of ONUs; and
the control circuit is further configured to:determine the temporal step to be equal to the schedule misalignment; and
bring forward the scheduled start time of each of the one or more of the plurality of scheduled periods succeeding the selected scheduled period by the temporal step,

wherein the any of the plurality of ONUs comprises:a data buffer configured to queue the periodic data traffic;
a processing circuit configured to:enqueue a selected data packet in the periodic data traffic in the data buffer at a time before the scheduled start time of the selected scheduled period; and
determine the schedule misalignment that equals the time the selected data packet is enqueued in the data buffer minus the scheduled start time of the selected scheduled period; and

an ONU interface coupled to the OLT interface and configured to provide the indication comprising the determined schedule misalignment to the OLT.



US Pat. No. 11,115,123

MINIATURE EMBEDDED SELF-ORGANIZED OPTICAL NETWORK

MEADOWAVE, LLC, Washingt...


1. A node configured for broad-beam optical communication with other nodes forming a wireless optical network, comprising:a substrate having a main surface;
first and second broad-beam optical interfaces disposed on the main surface of the substrate, and each configured to receive and transmit broad-beam optical signals for optical communication with the other nodes;
a processor communicatively connected to the first and second broad-beam optical interfaces and configured to process the optical signals received and transmitted via the first and second broad-beam optical interfaces;
third and fourth broad-beam optical interfaces mounted to a second surface of the substrate opposite to the main surface, and each configured to receive and transmit broad-beam optical signals for optical communication with the other nodes;
an energy harvester disposed on the main surface of the substrate and configured to harvest energy for operation of the node; and
a reflective coating disposed on portions of the main surface of the substrate other than the energy harvester and the first and second broad-beam optical interfaces, and configured to reflect light and optical signals incident thereon, wherein each of the first and second broad-beam optical interfaces includes an optical emitter configured to transmit broad-beam uncollimated optical signals therefrom, and an optical receiver configured to receive broad-beam uncollimated optical signals therethrough.

US Pat. No. 11,115,122

OPTICAL WIRELESS MESH NETWORK COMMUNICATION SYSTEM

QUANTUM DRIVE CO., LTD.


1. An optical wireless mesh network communication system; comprisingan optical wireless communication transceiver having an optical transmitter and an optical receiver and an optical fiber cable or a coaxial cable for transmitting signals received by the optical receiver to the optical transmitter in each node;
the optical wireless mesh network communication system connects n+1 nodes (n is a positive integer greater than or equal to 2, hereinafter the same in the claims) in the network; wherein
the optical wireless communication transceiver in each of the nodes is capable of communicating with the optical wireless communication transceiver in the correspondent node if the correspondent node satisfies conditions that (1) the correspondent node is within a predetermined straight-line distance for optical communication, (2) there is no obstacle blocking or absorbing light on the way, and (3) both the optical transmitter and the optical receiver are active;
the optical wireless communication transceiver in each of the nodes is capable of simultaneously transmitting with a wide angle of transmitted light to 3/5 or more optical wireless communication transceivers in the other n nodes and simultaneously receiving a wide angle of transmitted light from 3/5 or more optical wireless communication transceivers in the other n nodes when its own node and all of the other n nodes satisfy the conditions of (1) to (3);
in each of the nodes, the optical wireless communication transceiver includes a controller for format conversion of the input signal to a communication signal according to the network when an input signal is input from the input apparatus in a node to which the input apparatus is connected, and a controller for format conversion of a communication signal relating to the network to the output signal when the output apparatus outputs an output signal from the optical wireless communication transceiver to the output apparatus in a node to which the output apparatus is connected;
the optical receiver having a photodiode (hereinafter also referred to as “PD” in the claims), a resistor, and a capacitor connected on the downstream side in the electric current flow direction of the PD; wherein the optical receiver has a peak of a light receiving wavelength set to a wavelength shorter than the wavelength of ambient light, a function of performing a multiplication function in response to the energy of an incident photon unit, a function of not accepting the next photon until one photon enters and the multiplication function is restored, and when a voltage is applied between the terminals of the PD, a free carrier in the PD is activated, when the photon enters the PD in such a state, electrons are multiplied in the PD, electric current by the multiplied electrons is output; wherein the optical receiver which is a photon detection receiver having a device is capable to detect an alternating electric current component corresponding to the acceleration fluctuation of the photon passing through the capacitor from the output current as a signal is used.

US Pat. No. 11,115,121

POWER AMPLIFIER SYSTEM WITH AN INTERNAL OPTICAL COMMUNICATION LINK

EMPOWER RF SYSTEMS, INC.,...


17. A system comprising:an enclosure comprising:
a front panel comprising a first plurality of signal endpoints and a first optical interface, the first optical interface being coupled to each of the first plurality of signal endpoints; and
a rear panel comprising a second plurality of signal endpoints and a second optical interface, the second optical interface being coupled to each of the second plurality of signal endpoints;
an amplifier circuit disposed within the enclosure, the amplifier circuit generating electromagnetic interference (EMI) during operation;
a motherboard disposed within the enclosure, the motherboard comprising a third optical interface and a fourth optical interface;
a first optical link coupled between the first optical interface and the third optical interface, wherein the motherboard communicates each of the first plurality of signal endpoints over the first optical link; and
a second optical link coupled between the second optical interface and the fourth optical interface, wherein the motherboard communicates each of the second plurality of signal endpoints over the second optical link.

US Pat. No. 11,115,120

DISINTEGRATED SOFTWARE DEFINED OPTICAL LINE TERMINAL

Sterlite Technologies Lim...


13. A method for establishment of functional disintegration of internal functions of optical line terminal, the method comprising:disintegrating the optical line terminal into a plurality of points of presence, wherein the plurality of points of presence comprises a data center point of presence, one or more aggregation points of presence and one or more access points of presence;
disaggregating the plurality of points of presence at one or more locations;
establishing logical connections between each of the plurality of points of presence, wherein the logical connections between each of the plurality of points of presence determines compute and network capacity requirements for each of the plurality of points of presence; and
distributing the internal functions of the optical line terminal, wherein each of the plurality of points of presence performs distribution of the internal functions of the optical line terminal, wherein the internal functions of the optical line terminal are aggregated in a ratio of n:m:1, wherein n corresponds to a number of access points of presence and m corresponds to a number of aggregation points of presence, wherein 1 represents the centrally hosted internal functions of the optical line terminal at the data center point of presence,
wherein the method utilizes software defined networking technology for establishment of the functional disintegration of the internal functions of the optical line terminal.

US Pat. No. 11,115,119

RF-FSO LINKAGE METHOD AND GROUND STATION SYSTEM PERFORMING THE SAME

CONTEC CO., LTD., Daejeo...


3. A ground station system for performing a radio frequency-free space optics (RF-FSO) linkage method, the ground station system comprising:a first receiver comprising a first antenna configured to receive an optical signal comprising data from a satellite;
a second receiver comprising a second antenna configured to receive a radio frequency (RF) signal comprising data from the satellite; and
a processor configured to estimate data that is determined to have been transmitted from the satellite using the data received from the first receiver and thereby decoded and the data received from the second receiver and thereby decoded and transmit the estimated data to a data server,
wherein the processor comprises:
a data processing unit configured to process first data received using optical tracking from the first receiver and second data received using RF signal tracking from the second receiver, in a baseband; and
a data reformatting unit configured to format at least one of the first data and the second data and match a format and synchronization point in time between the first data and the second data.

US Pat. No. 11,115,118

METHOD TO AUTHENTICATE A SUBSTRATE USING SPECKLE PATTERNS AND A DEVICE TO PERFORM THE METHOD

COLOP DIGITAL GMBH, Wels...


1. A method to authenticate a substrate based on unique microstructure inherent to a region of interest of a substrate surface of the substrate, the method comprising:a. emitting photons from a light source onto the region of interest;
b. emitting ultrasound waves from an ultrasound source onto the region of interest;
c. capturing at least one photo acoustic speckle image of the region of interest by capturing a light image from the emitted photons in the presence of the emitted ultrasound to obtain the at least one captured photo acoustic speckle image of the region of interest; and
d. comparing the at least one captured photo acoustic speckle image with at least one reference in order to determine authenticity of the substrate,
wherein step d further comprises:
e. extracting a plurality of specific features from the at least one captured image;
f. identifying the location of each specific feature; and
g. comparing the identified locations with reference identified locations from an at least one reference image previously taken from the region of interest and stored in a database.

US Pat. No. 11,115,117

SUBMARINE OPTICAL COMMUNICATION CONTROL DEVICE, CONTROL METHOD, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM

NEC CORPORATION, Tokyo (...


1. A submarine optical communication system control device comprising:a light intensity distribution determination device configured to determine an optimum distribution of signal light intensity of an optical path for each allocated frequency;
a light intensity distribution measuring device configured to measure a light intensity distribution of an optical path after transmission through a submarine cable transmission line;
an equalization setting calculation unit configured to calculate a gain equalization setting for compensating for a difference between an optimum distribution in the light intensity distribution determination device and a measured distribution in the light intensity distribution measuring device; and
a variable gain equalizer configured to compensate for a light intensity distribution of an optical path to the optimum distribution, based on a gain equalization setting in the equalization setting calculation unit.

US Pat. No. 11,115,116

LOW DATA VOLUME SATELLITE COMMUNICATION SYSTEM

eSat Global, Inc., Solan...


1. A communication system, comprising:at least one terminal;
at least one satellite which creates a beam having a beam shape that enables communication with the at least one terminal when the at least one terminal is located inside the beam;
at least one network infrastructure in wireless communication with the at least one terminal, the at least one network infrastructure having an information element which includes beam shape information representing the beam shape;
wherein, the at least one terminal receives the information element from the at least one network infrastructure and calculates the at least one terminal's initial transmit power based on the beam shape information.

US Pat. No. 11,115,115

NON-ACCESS STRATUM CONNECTION HANDLING

Ofinno, LLC, Reston, VA ...


1. A method comprising:receiving, by a wireless device from a non-terrestrial network (NTN) base station, access network information indicating an access network type of a plurality of access network types comprising:a geostationary earth orbit (GEO) NTN access network type; and
a low earth orbit (LEO) NTN access network type;

selecting, based on the access network type, a first non-access stratum (NAS) period among a plurality of periods comprising:a first value associated with the GEO NTN access network type; and
a second value associated with the LEO NTN access network type;

initiating a NAS procedure by sending, to an access and mobility management function (AMF) via the NTN base station, a first NAS request message, wherein a start of the first NAS period is based on the sending; and
in response to an expiration of the first NAS period, aborting the NAS procedure.

US Pat. No. 11,115,114

HANDOVER OF A MOBILE TERMINAL IN A MULTI-BEAM SATELLITE BASED ON NETWORK CONDITIONS

Viasat, Inc., Carlsbad, ...


1. A method for satellite beam handover management for aircraft in a satellite communication system comprising a plurality of satellites, the method comprising:retrieving flight plan data for a plurality of aircraft being provided a network access service for passengers via the satellite communication system;
identifying, for each aircraft of the plurality of aircraft based at least in part on the flight plan data, respective candidate satellites of the plurality of satellites for providing the network access service over a service timeframe;
determining a service utilization for each aircraft of the plurality of aircraft for the service timeframe;
selecting, over the service timeframe, satellite beams of one or more satellites of the plurality of satellites for providing the network access service for each aircraft of the plurality of aircraft based at least in part on the respective candidate satellites and the determined service utilization for the plurality of aircraft; and
scheduling at least one handover for at least one of the plurality of aircraft to a selected satellite beam during the service timeframe.

US Pat. No. 11,115,113

TECHNIQUE FOR SELECTING A UAV APPLICATION SERVER

Telefonaktiebolaget LM Er...


1. A computing unit for executing a cellular network entity configured to select an Unmanned Aerial Vehicle (UAV) application server residing in a cellular network to be assigned to a UAV connecting to the cellular network, the computing unit comprising:processing circuitry;
memory containing instructions executable by the processing circuitry whereby the cellular network entity is operative to:trigger selecting, as part of an attach procedure of the UAV to the cellular network, a UAV application server in the cellular network to be assigned to the UAV.


US Pat. No. 11,115,112

SYSTEM FOR TRANSMITTING COMMANDS AND A VIDEO STREAM BETWEEN A REMOTE CONTROLLED MACHINE SUCH AS A DRONE AND A GROUND STATION

UAVIA, Evry (FR)


1. A system for transmitting commands and a video stream between a remote-controlled drone and a ground station, the system comprising a bidirectional link between craft and ground station, at least partly implementing a commercial cellular communication network, said bidirectional link being ensured by means of a cellular modem on the craft side and conveying, on the one hand, a compressed video stream generated by a camera and a video encoding module, and, on the other hand, information belonging to a group comprising movement control commands and flight data or piloting characteristics of the remote-controlled drone, the system further comprising a network management module for managing the bidirectional link capable of (i) ensuring that said link is maintained while taking account of the variability of topology and of performance levels of the link induced by the implementation of the cellular communication network and (ii) performing an adaptation of the bit rate of the compressed video stream by reserving an incompressible portion of the bandwidth available for the routing of critical information.

US Pat. No. 11,115,110

DEFAULT BEAM SELECTION BASED ON A SUBSET OF CORESETS

Qualcomm Incorporated, S...


1. A method of wireless communication at a User Equipment (UE), comprising:receiving, from a base station, an indication corresponding to a Channel Occupancy Time (COT), wherein the indication is for at least one of a set of Control Resource Sets (CORESETs), a set of Quasi co-location (QCL) assumptions, a set of uplink resources, or a set of spatial relations for determining a default beam;
determining the default beam from the base station for use during the COT based on the indication; and
transmitting or receiving a transmission using the default beam.

US Pat. No. 11,115,109

METHODS AND SYSTEMS FOR ESTABLISHING A CONNECTION BETWEEN DEVICES IN UNLICENSED RADIO FREQUENCY SPECTRUM

Cable Television Laborato...


1. A method for establishing a wireless connection between a user equipment (UE) device and a base station in unlicensed radio frequency (RF) spectrum, comprising:receiving, at the UE device, a plurality of RF signals broadcasted by the base station;
identifying a selected RF signal of the plurality of RF signals based on a maximum received signal level;
detecting, in the selected RF signal, a plurality of slots including control information;
incrementing a counter each time a slot including control information is detected in the selected RF signal; and
in response to the counter exceeding a threshold value, identifying a first channel occupancy time (COT1) of the base station from control information transmitted over the selected RF signal.

US Pat. No. 11,115,108

METHOD AND SYSTEM FOR FIELD AGNOSTIC SOURCE LOCALIZATION

Tata Consultancy Services...


1. A processor implemented method comprising:receiving, via one or more hardware processors, (i) a plurality of direct multiband spectrum (MBS) signals and (ii) a plurality of delayed MBS signals from a plurality of sensor elements in a sensor receiver array of a predefined dimension;
sampling, via the one or more hardware processors, the plurality of direct MBS signals and the plurality of delayed MBS signals at one of (i) at Nyquist sampling rate (ii) above Nyquist sampling rate or (iii) below Nyquist sampling rate;
obtaining, via the one or more hardware processors, (i) discrete Fourier transform (DFT) of each of the sampled direct MBS signal of the plurality of sampled direct MBS signals and (ii) discrete Fourier transform of each of the sampled delayed MBS signal of the plurality of sampled delayed MBS signals;
computing, via the one or more hardware processors, a direct-direct correlation for each sensor element of the plurality of sensor elements from the DFT of each of the sampled direct MBS signal;
computing, via the one or more hardware processors, a direct-delay correlation for each sensor element of the plurality of sensor elements from the DFT of each of the sampled delayed MBS signal and the DFT of each of the sampled direct MBS signal;
obtaining, via the one or more hardware processors, a direct correlation data matrix using the direct-direct correlation for each sensor element of the plurality of sensor elements;
obtaining, via the one or more hardware processors, a delay correlation matrix using the direct-delay correlation for each sensor element of the plurality of sensor elements;
estimating, via the one or more hardware processors, a signal subspace matrix from the direct correlation data matrix;
estimating, via the one or more hardware processors, a transformation matrix based on the signal subspace matrix;
estimating, via the one or more hardware processors, a plurality of diagonal matrices based on the delay correlation matrix, the signal subspace matrix and the transformation matrix;
jointly estimating, via the one or more hardware processors, a carrier frequency and a corresponding direction of arrival (DOA) of each source signal of a plurality of source signals from a plurality of data sources based on the plurality of diagonal matrices, the signal subspace matrix and the transformation matrix using an element-wise division of the plurality of diagonal matrices;
computing, via the one or more hardware processors, a covariance matrix using one of (i) the plurality of sampled direct MBS signals or (ii) the plurality of sampled delayed MBS signals;
estimating, via the one or more hardware processors, noise subspace by decomposing the covariance matrix; and
iteratively performing a set of steps for estimating range of each source signal of the plurality of source signals, the estimating comprising:computing a maximum possible range based on the sensor receiver array dimension and the carrier frequency of the source signal;
dividing the maximum possible range into a plurality of bins of predefined size;
forming a steering matrix from the carrier frequency, the DOA and the plurality of bins; and
determining the range of the source signal as one of (i) near field or (ii) far field by projecting the steering matrix onto the noise subspace.


US Pat. No. 11,115,107

COMMUNICATION RECEIVING DEVICE AND METHOD FOR OPERATING THE SAME

SAMSUNG ELECTRONICS CO., ...


1. A communication receiving device comprising:a cross-correlation measuring circuit configured to repetitively measure a cross-correlation degree between a received legacy signal symbol (“L-SIG”) of a preamble within a data frame, and a second symbol succeeding L-SIG;
an accumulating circuit configured to accumulate a real part of results of the repetitive cross-correlation degree measurements;
a comparator configured to compare the accumulated real part of the results with a variable threshold value and based on the comparison, to indicate whether the second symbol is a repeated symbol (“RL-SIG”) of L-SIG;
a threshold value calculator configured to calculate the variable threshold value; and
an Error Vector Magnitude circuit configured to detect whether there is an error in RL-SIG after a demodulation of L-SIG and a subsequent Orthogonal Frequency Division Multiplexing (OFDM) symbol of L-SIG.

US Pat. No. 11,115,105

METHOD AND APPARATUS FOR MANAGING USER PLANE OPERATION IN WIRELESS COMMUNICATION SYSTEM

Samsung Electronics Co., ...


1. A method performed by a source distributed unit (DU), the method comprising:receiving, from a centralized unit (CU), a message including a radio resource control (RRC) reconfiguration message for a handover; and
transmitting, to a user equipment (UE), the RRC reconfiguration message for the handover,
wherein the RRC reconfiguration message indicates a reset of a MAC entity and a re-establishment of a RLC entity,
wherein, in case that a security key for a radio bearer changes, the RRC reconfiguration message includes an indicator to perform a packet data convergence protocol (PDCP) re-establishment,
wherein, in case that the security key for the radio bearer does not change, the RRC reconfiguration message does not include the indicator,
wherein the CU is associated with a PDCP layer, and
wherein the source DU is associated with a radio link control (RLC) layer and a medium access control (MAC) layer.

US Pat. No. 11,115,104

ENHANCED SIGNALING AND USE OF MULTIPLE TRANSMISSION CHAINS

Intel Corporation, Santa...


1. A device, the device comprising storage coupled to processing circuitry, the processing circuitry configured to:determine four bits indicative of spatial streams;
encode the four bits, wherein to encode the four bits comprises to generate a first indication of a first number of spatial streams up to eight spatial streams using three of the four bits, and a second indication of a second number of either zero or eight additional spatial streams using a fourth bit of the four bits, wherein the first indication of the first number of spatial streams is encoded in a Control Information subfield of an Operating Mode Control Field, the Control Information subfield comprising a Channel Width indication and a Disable Uplink Multi-User indication;
determine one or more fields of a frame, wherein the one or more fields comprise the Operating Mode Control Field; and
cause to send the frame, the frame comprising the four encoded bits.

US Pat. No. 11,115,103

METHOD AND APPARATUS FOR BEAM MEASUREMENT AND MANAGEMENT IN WIRELESS SYSTEMS

Samsung Electronics Co., ...


1. A method for operating a user equipment (UE) in a wireless communication system, the method comprising:receiving, from a base station (BS), configuration information regarding a channel state information (CSI) reporting, the configuration information configuring the UE to transmit report information for at least two transmit beams that are associated with a same receive beam of the UE; and
transmitting, to the BS, the report information based on the configuration information, the report information comprising first information for indicating a first of the two transmit beams and second information for indicating a second of the two transmit beams,
wherein a receive beam of the UE is usable for receiving a first signal based on the first transmit beam and a second signal based on the second transmit beam.

US Pat. No. 11,115,102

WIRELESS SIGNAL TRANSMITTING ANTENNA, WIRELESS SIGNAL RECEIVING ANTENNA, WIRELESS SIGNAL TRANSMITTING SYSTEM, WIRELESS SIGNAL TRANSMITTING METHOD, AND WIRELESS SIGNAL RECEIVING METHOD

NEC CORPORATION, Tokyo (...


1. A wireless signal transmitting method comprising:generating, from an input first signal, N number of second signals having a phase difference from one another, wherein N is an integer greater than or equal to 2;
generating, from an input third signal, N number of fourth signals having a phase difference from one another;
outputting the N number of second signals to N number of antenna elements equally spaced on a circumference of a circle, respectively, so that a first spiral beam with an equiphase surface inclined spirally is output from the N number of antenna elements; and
outputting the N number of fourth signals to the N number of antenna elements, respectively, so that a second spiral beam with an equiphase surface inclined spirally is output from the N number of antenna elements,
wherein the first spiral beam and the second spiral beam are orthogonally polarized.

US Pat. No. 11,115,101

TRANSMISSION METHOD, TRANSMISSION DEVICE, AND COMMUNICATION SYSTEM

PANASONIC INTELLECTUAL PR...


1. A communication system comprising:a first access point (AP) fixedly located in a first location;
a second AP fixedly located in the first location;
a control circuit located in the first location and configured to control the first AP and the second AP to unicast such that:in a first period, the first AP and the second AP unicast first data and second data to a reception device simultaneously at a first frequency channel, respectively, the first data being same as the second data; and
in a second period, the first AP unicasts third data to the reception device and the second AP does not unicast to the reception device; and

the reception device fixedly located in a second location within communication areas of the first AP and the second AP.

US Pat. No. 11,115,099

SYSTEM AND METHOD FOR SUPPORTING ANTENNA BEAMFORMING IN A CELLULAR NETWORK

Apple Inc., Cupertino, C...


1. A method for operating a receiver, the method comprising:by the receiver:receiving pilot channel indicator signals from an access node corresponding to a plurality of spatial beams, wherein each of the pilot channel indicator signals is transmitted in a beamformed fashion on one of the plurality of spatial beams;
exchanging layer 3 signaling, wherein the layer 3 signaling indicates a feedback mode;
generating a feedback signal based on the layer 3 signaling, wherein:when the feedback mode is a first mode, said feedback signal includes a first beam index, wherein the first beam index corresponds to the pilot channel indicator signal of the first beam among the plurality of spatial beams; and
when the feedback mode is a second mode, said feedback signal includes two beam indices corresponding to two pilot channel indicator signals of two spatial beams among the plurality of spatial beams, wherein the second mode facilitates transmission to the receiver on the two spatial beams simultaneously;

transmitting said feedback signal to the access node from the first receiver;
receiving a transmission from the access node, the transmission at least in part based on an analysis of the feedback signal.


US Pat. No. 11,115,098

CONFIGURATION AND DESIGN OF CQI AND MCS TABLES FOR 5G COMMUNICATIONS

Apple Inc., Cupertino, C...

and
decode the PDSCH based on the DL grant and using modulation order and target code rate corresponding to the MCS index to the MCS table.

US Pat. No. 11,115,097

ADAPTIVE EXPLICIT CSI FEEDBACK AND OVERHEAD REDUCTION

Nokia Technologies Oy, E...


1. A method, comprising:evaluating, using circuitry of a user terminal, a number of constituent precoders to be used in providing a single precoder to include in an explicit channel state information report, to be transmitted from the user terminal to at least one device in a network;
wherein the evaluating of the number of constituent precoders to be used in providing the single precoder is at least partially based on a measurement using the user terminal comprising: a speed of the user terminal, and/or an angular spread associated with the at least one device in the network;
determining, using the circuitry of the user terminal, the number of constituent precoders based on the user terminal measurement;
wherein the constituent precoders comprise eigenvectors and the single precoder comprises at least one of a dominant eigenvector and a single vector combined of several eigenvectors;
wherein determining a number of eigenvectors to be used in providing the single vector comprises determining the angular spread associated with the at least one device in the network based on eigen-decomposition of a channel covariance matrix;
determining that the single precoder is the dominant eigenvector, in response to a determination that the number of constituent precoders to be used in providing the single precoder is equal to or less than one;
determining the angular spread based on: a power gain difference between respective eigenvalues of the eigenvectors and a dominant eigenvalue; and a steering direction difference between respective eigenvectors and the dominant eigenvector;
combining the constituent precoders to form the single precoder in response to a determination that the number of constituent precoders to be used in providing the single precoder is greater than one; and
configuring a signal to transmit the explicit channel state information report including the single precoder from the user terminal to the at least one device in the network.

US Pat. No. 11,115,096

USE OF UPLINK BEAM TRACKING RESULTS IN REFERENCE SYMBOL SESSIONS

QUALCOMM Incorporated, S...


1. A method for wireless communication by a user equipment (UE), comprising:receiving a request message from a base station, the request message comprising a request for the UE to transmit a set of sounding reference signals (SRSs);
transmitting, using at least two beamformed signals, the set of SRSs to the base station in accordance with the request message, the at least two beamformed signals being associated with a co-phasing parameter;
receiving, from the base station based at least in part on the transmitted set of SRSs and the co-phasing parameter, an antenna port precoder configuration associated with the co-phasing parameter; and
communicating with the base station using one or more beamformed signals configured according to the received antenna port precoder configuration.

US Pat. No. 11,115,095

FINITE-ALPHABET BEAMFORMING FOR MULTI-ANTENNA WIDEBAND SYSTEMS

Cornell University, Itha...


1. A method for digitally beamforming signals for an antenna array, the method comprising:estimating a wireless channel associated with a plurality of digital baseband signals and an antenna array to produce estimates of the wireless channel; and
beamforming, with a finite-alphabet equalizer, the plurality of digital baseband signals based on the estimates of the wireless channel;
wherein the plurality of digital baseband signals is beamformed at a given resolution less than a resolution of the estimates of the wireless channel.

US Pat. No. 11,115,094

ELECTRONIC DEVICE AND METHOD FOR ANTENNA SWITCHING

QUANTA COMPUTER INC., Ta...


1. An electronic device, comprising:a plurality of built-in antennas, receiving a wireless signal of mobile communication;
a communication processor, calculating the reception strength of the wireless signal received by each of the built-in antennas or each of antennas of a mobile device;
a plurality of antenna switching circuits; wherein each of the antenna switching circuits is electrically coupled to one of the built-in antennas or one of the antennas of the mobile device according to a control signal;
a control processor, correspondingly outputting the control signal according to the reception strength of the wireless signal received by the one of the built-in antennas or the one of the antennas of the mobile device;
wherein the electronic device is able to be embedded in the mobile device, and is electrically coupled to the antennas of the mobile device through a connector.

US Pat. No. 11,115,093

ELECTRONIC DEVICE SUPPORTING THERMAL MITIGATING AND A CONTROL METHOD OF THEREOF

LG ELECTRONICS INC., Seo...


16. A method of controlling an electronic device, the method comprising:performing wireless communication according to a first communication scheme through any one of a plurality of antenna modules provided in the electronic device;
detecting an antenna module exceeding a preset first temperature among the plurality of antenna modules;
detecting a temperature difference between a highest temperature antenna module and a lowest temperature antenna module among the plurality of antenna modules when the antenna module exceeding the first temperature is not detected;
determining a threshold temperature difference according to a surface temperature of the electronic device; and
switching from using a first antenna module performing wireless communication with a base station to a second antenna module among the plurality of antenna modules to perform the wireless communication with the base station according to a result of comparing the temperature difference and the threshold temperature difference.

US Pat. No. 11,115,092

APPARATUS, SYSTEM AND METHOD OF COMMUNICATING ACCORDING TO A TRANSMIT SPACE-FREQUENCY DIVERSITY SCHEME

INTEL CORPORATION, Santa...


1. An apparatus comprising:memory circuitry; and
a processor comprising logic and circuitry configured to cause a wireless communication station (STA) to:modulate encoded data bits into a plurality of data blocks according to a Dual Carrier Modulation (DCM), a data block of the plurality of data blocks comprising a plurality of pairs of complex constellation points;
map the plurality of data blocks to a first stream and a second stream,
wherein a first pair of complex constellation points in a first data block of the plurality of data blocks is mapped to two first pairs of encoded points over two first pairs of data subcarriers, one pair of the two first pairs of encoded points comprises the first pair of complex constellation points, another pair of the two first pairs of encoded points comprises a complex conjugate of the first pair of complex constellation points, one pair of the two first pairs of data subcarriers comprises a k-th subcarrier and a P(k)-th subcarrier in a first Orthogonal Frequency Division Multiplexing (OFDM) symbol in the first stream, another pair of the two first pairs of data subcarriers comprises a k-th subcarrier and a P(k)-th subcarrier in a second OFDM symbol in the second stream, wherein P(k) is a predefined function of k,
and wherein a second pair of complex constellation points in a second data block of the plurality of data blocks is mapped to two second pairs of encoded points over two second pairs of data subcarriers, one pair of the two second pairs of encoded points comprises the second pair of complex constellation points, another pair of the two second pairs of encoded points comprises a sign-inversed complex conjugate of the second pair of complex constellation points, one pair of the two second pairs of data subcarriers comprises a k-th subcarrier and a P(k)-th subcarrier in a second OFDM symbol in the first stream, another pair of the two second pairs of data subcarriers comprises a k-th subcarrier and a P(k)-th subcarrier in a first OFDM symbol in the second stream; and
transmit an OFDM transmission over a wireless communication channel in a frequency band above 45 Gigahertz (GHz), the OFDM transmission based on the first and second streams.


US Pat. No. 11,115,091

CHANNEL STATE INFORMATION FEEDBACK AND RECEIVING METHODS, TRANSMIT-END DEVICE AND RECEIVE-END DEVICE

HUAWEI TECHNOLOGIES CO., ...


9. A method, comprising:generating codebook indication information of K transport layers, wherein K is an integer greater than or equal to 2; wherein the codebook indication information comprises: L pieces of beam information used by the K transport layers, beam superposition coefficient information of at least one of m transport layers, and indication information used to indicate beam information associated with each of the K transport layers; wherein L is an integer greater than or equal to 2, and a quantity of pieces of beam information associated with at least one of the K transport layers is less than L to reduce a quantity of beam superposition coefficients that are fed back; and
sending the codebook indication information.

US Pat. No. 11,115,090

APPARATUS AND METHOD FOR JAMMER RESISTANT PROTOCOL STACK DESIGN

ANDRO COMPUTATIONAL SOLUT...


1. A communication system, comprising:a transceiver assembly including a transmitter component, the transmitter component comprising:a rate-2 orthogonal space-time block code (OSTBC) encoder for processing a set of information symbols to produce a set of encoded signals;
a precoder module coupled to an output of the rate-2 OSTBC encoder for modifying a signal-to-jammer plus noise ratio (SJNR) of the set of encoded signals; and
an eigen-beamformer module coupled to an output of the precoder module, and configured to generate a set of symbols for transmission via a set of eigenmodes of a channel covariance matrix for the transceiver assembly.


US Pat. No. 11,115,089

RADIO APPARATUSES FOR LONG-RANGE COMMUNICATION OF RADIO-FREQUENCY INFORMATION

UBIQUITI INC., New York,...


1. A method of multiple-input, multiple-output (MIMO) processing in a radio apparatus, the method comprising:receiving a reference signal from a transmitter in the radio apparatus for each of a plurality of different polarizations;
determining, from the received reference signal, an isolation between the plurality of different polarizations;
scaling matrix processing of signals received by each of the plurality of different polarizations based on the isolation between the plurality of different polarizations; and
outputting the scaled matrix processed signals.

US Pat. No. 11,115,088

ANTENNA ARRAY OPERATION CONTROL

Telefonaktiebolaget LM Er...


1. A method for controlling operations of an antenna array comprising two or more controllable sections and antenna ports connected to transceiver circuitry, the method comprising:determining a scenario of one of transmission and reception by the antenna array, determining the scenario comprising selecting one of a plurality of predefined scenarios, the plurality of predefined scenarios comprising one or more of a high path loss scenario, a high traffic capacity scenario and a high peak rate scenario, the scenario being defined in terms of a requirement for a number of users intended as one of receivers and transmitters, respectively, of the one of the transmission and the reception and in terms of one or more of:a path loss requirement;
a peak rate requirement; and
a traffic capacity requirement; and

configuring the transceiver circuitry responsive to the determined scenario, the configuration comprising, for the one of the transmission and the reception, one or more of:allocating, for each user, a number of sections of the two or more sections of the antenna array and determining a sub-division of the allocated sections;
determining, for each user, a number of information data layers for multiple-input multiple-output, MIMO, application; and
allocating, for each user, a bandwidth;

configuring the transceiver circuitry responsive to the high path loss scenario comprises, for each user:allocating a number of sections and determining that the allocated sections are sub-divided into a single group;
determining a number of information data layers; and
allocating a bandwidth;

configuring the transceiver circuitry responsive to the high traffic capacity scenario comprises, for each user:allocating a number of sections and determining that the allocated sections are sub-divided into a single group; and
determining a number of information data layers; and

configuring the transceiver circuitry responsive to the high peak rate scenario comprises, for each user:allocating a number of sections higher than a predetermined amount and determining that the allocated sections are sub-divided into a plurality of groups;
determining a relatively low number of information data layers lower than a predetermined amount; and
allocating a bandwidth higher than a predetermined amount.


US Pat. No. 11,115,087

METHOD FOR DISTRIBUTED ANTENNA-BASED COMMUNICATION DEVICE TO PERFORM COMMUNICATION BASED ON INTER-PANEL INTERFERENCE

LG ELECTRONICS INC., Seo...


1. A method for performing communication based on inter-panel interference by a distributed antenna-based communication device, the method comprising:measuring interference between transmission beams of a transmission panel and reception beams of a reception panel;
configuring inter-panel beam pair information by pairing the beams of the transmission panel and the beams of the reception panel on the basis of the measurement; and
transmitting the inter-panel beam pair information to a base station or a neighboring communication device.

US Pat. No. 11,115,086

REFERENCE SIGNAL PORT ALLOCATION

QUALCOMM Incorporated, S...


1. A method of wireless communication performed by a user equipment (UE), comprising:receiving multiple spatial dimension multiplexed (SDM) communications associated with multiple transmission reception points (TRPs) via a single antenna panel of the UE;
estimating a phase noise based on phase tracking reference signals (PT-RSs) received via a single communication of the multiple SDM communications; and
performing phase noise correction for the multiple SDM communications based at least in part on estimating the phase noise received via the single communication of the multiple SDM communications.

US Pat. No. 11,115,085

MIMO-OFDM SYSTEM FOR INCREASING RELIABILITY

INDUSTRY-ACADEMIA COOPERA...


1. A MIMO-OFDM system for increasing reliability comprising:a transmission terminal that includes Nt transmission antennas and transmits a MIMO signal through relay terminals; and
a reception terminal that receives the MIMO signal from the relay terminal through Nr reception antennas,
wherein the transmission terminal extracts a composite channel coefficient from a composite channel generated by matching a channel between the transmission terminal and the reception terminal with a channel between each of a plurality of the relay terminals and the reception terminal, selects the relay terminal corresponding to the composite channel coefficient having a maximized channel capacity from among the plurality of relay terminals by using the extracted composite channel coefficient, and transmits a MIMO signal to the reception terminal through the selected relay terminal,
wherein the transmission terminal includes:
a communication unit that estimates the composite channel by respectively transmitting pilot signals to the plurality of relay terminals;
a singular value extraction unit that acquires information on a channel matrix by using the estimated composite channel and extracts a singular value by applying a singular value decomposition (SVD) method to the channel matrix;
a composite channel coefficient calculation unit that calculates the composite channel coefficient by using the extracted singular value; and
a relay terminal selection unit that calculates a channel capacity by using the calculated composite channel coefficient and selects a relay terminal having a maximum value among the calculated channel capacities from among the plurality of relay terminals.

US Pat. No. 11,115,084

ISOLATED DATA TRANSFER SYSTEM

Allegro MicroSystems, LLC...


1. A system, comprising:a drive coil to transmit information;
a receive coil magnetically coupled to the drive coil for receiving the information from the drive coil; and
a first magnetic field sensing element proximate the receive coil to detect the information from the receive coil, wherein the receive coil includes a first narrowed portion for concentrating magnetic field generated by the current through the receive coil on the first magnetic field sensing element.

US Pat. No. 11,115,083

DIRECT CONVERSION POLAR TRANSMITTER FOR AN RFID READER

CLAIRVOYANT TECHNOLOGY, I...


1. A radio frequency identification (RFID) system comprising:a receiver to receive responses from RFID tags; and
a polar transmitter, the polar transmitter further comprising:a power amplifier to produce a transmitter output signal;
an envelope amplifier connected to the power amplifier to supply an envelope signal to the power amplifier;
a quadrature modulator connected to the power amplifier to provide modulation for the transmitter output signal using a cartesian input signal; and
a continuous wave source connected to the quadrature modulator.


US Pat. No. 11,115,082

WIRELESS POWER TRANSMISSION/RECEPTION DEVICE AND METHOD USED IN ELECTRONIC APPARATUS

Samsung Electronics Co., ...


1. An electronic device comprising:at least one antenna;
a first circuit configured to wirelessly receive or transmit power using at least a portion of the at least one antenna;
a second circuit configured to perform at least one type of communication using at least a portion of the at least one antenna;
a first electric path configured to connect the at least one antenna and the first circuit;
a second electric path configured to connect the at least one antenna and the second circuit;
a third electric path configured to connect a point on the first electric path and a point on the second electric path; and
at least one passive element or active element connected to at least one of the first electric path, the second electric path, and the third electric path,
wherein the at least one passive element or active element blocks introduction of a wireless power signal into the second circuit when the first circuit wirelessly receives or transmits power via the at least one antenna.

US Pat. No. 11,115,081

ROUTING METHOD FOR MULTIPLE SECURITY ELEMENTS, NFC CONTROLLER AND NFC DEVICE

ZTE CORPORATION, Shenzhe...


1. A routing method for multiple security elements (SEs), which is applied to a Near Field Communication (NFC) device having at least three SEs, the routing method comprising:receiving, by an NFC controller in the NFC device, a request from an external device for accessing an NFC application;
searching, by the NFC controller, a routing table for a security element (SE) to be routed according to an Application ID (AID) carried in the request, AID routes for part of the SEs in the NFC device being stored in the routing table:
sending, by the NFC controller in a case where the SE is not found, the request to all other SEs in the NFC device except the part of SEs;
the routing table initially stores AID routes for one SE, said one SE being an SE with the smallest number of AIDs registered in the NFC device.

US Pat. No. 11,115,080

METHOD AND APPARATUS FOR DETERMINATION OF VECTORING MATRICES

Alcatel Lucent, Nozay (F...


1. A vectoring controller configured to determine a vectoring matrix that is used for joint processing of Discrete Multi-Tone DMT communication signals to be transmitted over, or received from, a plurality of subscriber lines, the vectoring controller being configured to determine first coefficient values for the vectoring matrix at a first tone based on a first number of iterations through an iterative update algorithm and based on a first channel matrix estimate at the first tone, and to determine second coefficient values for the vectoring matrix at a second neighboring tone based on a second number of iterations through the iterative update algorithm and based on a second channel matrix estimate at the second tone,wherein the vectoring controller is further configured to start with default coefficient values as initial values for the determination of the first coefficient values through the iterative update algorithm, and to start with the first coefficient values as initial values for the determination of the second coefficient values through the iterative update algorithm,
and wherein the vectoring controller is further configured to set the second number of iterations to a value that is lower than the first number of iterations.

US Pat. No. 11,115,079

SIGNAL POWER REDUCTION SYSTEMS AND METHODS

Cable Television Laborato...


1. A signal transmission system for reducing transmission power for an encoded data stream, comprising:a receiver configured to receive an incoming data stream having a first average transmit power for a plurality of incoming data bits;
a symbol scheme processor configured to assign a symbol scheme, implementing a non-uniform number of bits per symbol, to at least a portion of the incoming data bits according to probabilities of occurrence of the incoming data bits;
a memory communicatively coupled to the symbol scheme processor and the receiver for storing the incoming data stream; and
a transmitter configured to transmit an outgoing data stream comprising a plurality of outgoing symbols according to the assigned symbol scheme at a second average transmit power.

US Pat. No. 11,115,078

WIDE AREA POSITIONING SYSTEM

NextNav, LLC, Sunnyvale,...


1. A method for estimating one or more positions of a receiver, wherein the method comprises:generating, for each of a plurality of positioning signals transmitted from a plurality of terrestrial transmitters and received by the receiver, a cross-correlation function by cross-correlating one or more signal samples extracted from that positioning signal with a reference sequence corresponding to that positioning signal;
determining a vector of cross-correlation samples from each cross-correlation function by selecting a first set of cross-correlation samples left of a peak of the cross-correlation function and a second set of cross-correlation samples right of the peak of the cross-correlation function;
identifying, for each of the positioning signals, a time of arrival estimate corresponding to an earliest arriving signal path of one or more signal paths corresponding to that positioning signal using a high resolution time of arrival measurement method; and
estimating a first position of the receiver based on the time of arrival estimate.

US Pat. No. 11,115,077

WIRELESS COMMUNICATION METHOD FOR MODULATING DATA SIGNALS IN A CHIRP SPREAD SPECTRUM COMMUNICATION SYSTEM

King Abdulaziz University...


1. A wireless communication method for modulating data signals with a plurality of overlapping chirps by an adaptive overlapping transmitter in a chirp spread spectrum communication system (CSS), comprising:receiving a stream of data signals at a first data rate (Rold);
increasing the first data rate of the data signals to a second data rate (Rnew);
encoding the data signals at the second data rate with a phase difference between each two consecutive bits and generating a phase encoded bit stream;
converting the data signals to positive and negative pulses;
generating a plurality of overlapping chirp signals from the positive and negative pulses;
increasing the gain of the chirp signals by a factor equal to the ratio of the second data rate divided by the first data rate and outputting an encoded stream of data signals modulated by a plurality of overlapping chirps;
transmitting the encoded stream in the chirp spread spectrum communications system over a wireless communication channel to a non-coherent receiver.

US Pat. No. 11,115,076

TRANSCEIVER ASSEMBLY PROTECTION ELEMENT

Microsoft Technology Lice...


1. A transceiver assembly, including:a radio frequency (RF) transceiver configured to transmit and receive RF signals;
a transceiver controller operatively coupled with the transceiver via a transmit path and a receive path;
a power amplifier disposed along the transmit path between the transceiver controller and the transceiver, the power amplifier configured to amplify RF signals received from the transceiver controller for transmission by the transceiver;
a power detection line configured to provide power control feedback to the transceiver controller indicating an amplitude of current flowing from the power amplifier to the transceiver; and
a directionally-specific protection element disposed along the power detection line, the directionally-specific protection element configured to allow the power control feedback to flow to the transceiver controller over the power detection line in a first direction, while preventing at least some electrical noise originating from the transceiver controller from flowing through the power detection line in a second direction, thereby preventing the electrical noise from entering the receive path.

US Pat. No. 11,115,075

SAFE CASE WITH SECURITY CHOKE POINT CONTROL

PPIP LLC, Chandler, AZ (...


1. A method comprising:at a first apparatus including a housing, a controller, a non-transitory memory, and one or more communication devices at least partially supported by the housing, wherein the housing is arranged to hold a second device that is distinct from the first apparatus:
receiving, by the first apparatus, a first input, wherein the first input is detected by a second sensor on the second device and a second input is detected by a first sensor on the first apparatus;
classifying the first input as a first input type based on an input type classification, wherein a respective input type in the input type classification corresponds to a plurality of inputs, and the second input also corresponds to the first input type, wherein the first input type comprises inputs associated with moving a mechanical part;
determining which of a combination of one or more sensors on the second device that the first input is directed to based on the input type classification and sensor assignments, wherein the sensor assignments specify each corresponding input type for a set of sensors on the second device; and
directing the second device to selectively enable or disable a first combination of the one or more sensors on the second device without intervening user inputs in accordance with determining that the first input corresponds to the first input type and the first input type corresponds to the first combination of the one or more sensors on the second device in the sensor assignments.

US Pat. No. 11,115,074

WEARABLE DEVICE ANTENNA

Snap Inc., Santa Monica,...


1. An eyewear device including:a frame including a bridge;
a temple connected to a lateral side of the frame;
a magnetic coupler opening formed in the temple or the bridge;
a processor;
a memory accessible to the processor; and
a very high frequency (VHF) radio transceiver for data transmission and reception and connected to the processor, including:a transmitter to modulate a VHF band radio carrier signal with data to generate transmitted VHF band radio modulated signals during transmission; and
a receiver to demodulate received VHF band radio modulated signals into data during reception;

a magnetic coupler connected to the VHF radio transceiver and including a diamagnetic material shaped to form a VHF transmission or reception terminal that partially or fully aligns with the magnetic coupler opening, the magnetic coupler configured to:during transmission, radiate the transmitted VHF band radio modulated signals into tissue of the user; and
during reception, absorb the received VHF band radio modulated signals from the tissue of the user;

the memory accessible to the processor; and programming in the memory
wherein execution of the programming by the processor configures the eyewear device to perform functions, including functions to:modulate, via the VHF radio transceiver, the VHF band radio carrier signal with data to generate the transmitted VHF band radio modulated signals during transmission;
during transmission, radiate, via the magnetic coupler, the transmitted VHF band radio modulated signals into the tissue of the user;
during reception, absorb, via the magnetic coupler, the received VHF band radio modulated signals from the tissue of the user; and
demodulate, via the VHF radio transceiver, the received VHF band radio modulated signals into data during reception.


US Pat. No. 11,115,073

METHOD AND DEVICE FOR DECREASING ELECTROMAGNETIC RADIATION SPECIFIC ABSORPTION RATE

HUAWEI TECHNOLOGIES CO., ...


1. A method implemented by a terminal, wherein the method comprises:separately collecting a transmit power of the terminal at different time points during a second duration after a first duration from a power-on moment to obtain a plurality of transmit powers;
calculating an average transmit power of the transmit powers;
determining, based on the average transmit power, an electromagnetic radiation specific absorption rate (SAR) corresponding to the average transmit power;
determining that the electromagnetic radiation SAR is greater than a preset threshold; and
decreasing the transmit power after the second duration in response to determining that the electromagnetic radiation SAR is greater than the preset threshold.

US Pat. No. 11,115,072

INTERFERENCE PROCESSING METHOD AND APPARATUS


1. An interference processing method, comprising:detecting an interference degree of a component of a terminal equipment to the terminal equipment when the component is working; and
adjusting component parameters corresponding to the component within a preset range when the interference degree satisfies a preset condition;
wherein, detecting the interference degree of the component of the terminal equipment to the terminal equipment when the component is working comprises:
acquiring a first signal strength of the component before working and a second signal strength of the component when it is working;
calculating the interference degree of the component to the terminal equipment when the component is working, the interference degree being a difference between the second signal strength and the first signal strength;
wherein, adjusting component parameters corresponding to the component within the preset range when the interference degree satisfies the preset condition, comprises:
when the difference between the second signal strength and the first signal strength is less than a preset signal threshold, determining an adjusted component parameter value according to a signal strength corresponding to a parameter value of each of the component parameters within the preset range.

US Pat. No. 11,115,071

MULTIMODE AND MULTI-FREQUENCY RADIO FREQUENCY FRONT END MODULE, CHIP, AND COMMUNICATION TERMINAL

SHANGHAI VANCHIP TECHNOLO...


1. A multi-mode and multi-frequency radio frequency front end module, comprising an input matching unit, an amplification unit, an output matching unit and a control unit; wherein the output matching unit comprises a first output matching module, a first switch module and a second output matching module; a radio frequency signal input end is connected to an input end of the amplification unit through the input matching unit; an output end of the amplification unit is connected to an input end of the first output matching module; an output end of the first output matching module is correspondingly connected to an input end of the first switch module, an input end of the second output matching module and a radio frequency transmission path; an output end of the first switch module and an output end of the second output matching module are separately grounded; the control unit is connected to the amplification unit;the first switch module comprises m switches, m being a positive integer; and one end of each switch is connected to a corresponding radio frequency transmission path and a corresponding output end in the first output matching module, and the other end of the each switch is grounded, and
the control unit is connected to the first switch module and is configured to control an on-off state of the first switch module, to input a radio frequency signal to one or more radio frequency transmission paths.

US Pat. No. 11,115,070

METHOD FOR EMITTING AND RECEIVING A RADIOFREQUENCY SIGNAL IN A SATELLITE TRANSMISSION SYSTEM, CORRESPONDING EMITTER, CHARACTERIZATION RECEIVER AND COMPUTER PROGRAM

ENENSYS TEAMCAST, Cesson...


1. A reception method for receiving a radiofrequency signal, in a system comprising an emitter, a satellite and at least one characterization receiver, said method comprising the at least one characterization receiver implementing a characterization phase of the satellite, comprising:transmitting to said emitter, over a first transmission link between said characterization receiver and said emitter, at least one transmission command of at least one reference signal,
receiving said at least one reference signal, emitted by said emitter over a second transmission link between said emitter and said characterization receiver via said satellite, termed a received signal,
estimating at the characterization receiver at least one distortion generated by the satellite, from said at least one reference signal; delivering at least one piece of information on compensation of distortions affecting the received signal based on the estimated distortion, and
transmitting to said emitter, over said first transmission link, said at least one piece of information on compensation of distortions.

US Pat. No. 11,115,069

NEAR-FIELD WIRELESS DEVICE FOR DISTANCE MEASUREMENT

NXP B.V., Eindhoven (NL)...


1. A wireless device, comprising:a first near-field device, including a near-field transmitter or receiver and a controller, configured to be coupled to a near-field antenna having a first conductive surface and a set of feed-points;
wherein the controller is configured to receive a transmitter output voltage from the set of feed-points;
wherein the controller is configured to generate a correction signal based on a difference between the transmitter output voltage and a target transmitter output voltage;
wherein the correction signal varies in response to a change in a distance between the first surface and a second conductive surface; and
wherein the controller is configured to calculate the distance, between the first conductive surface and the second conductive surface, based on the correction signal.

US Pat. No. 11,115,068

DATA-BASED PRE-DISTORTION FOR NONLINEAR POWER AMPLIFIER

Cypress Semiconductor Cor...


1. A method, comprising:pre-distorting a digital baseband data signal for conversion to a radio frequency (RF) signal, and amplification by a nonlinear power amplifier (PA) to generate an RF output signal, wherein the RF output signal is output to an antenna for transmission;
coupling a portion of the RF output signal to generate a second RF output signal;
comparing a digitized, down-converted version of the second RF output signal with the digital baseband data signal, to determine distortion coefficients of the non-linear PA, wherein frames of the digitized, down-converted version of the second RF output signal and the digital baseband data signal are aligned using a separate dedicated buffer for each prior to the comparison, and wherein transmission of the RF output signal is not interrupted by transmission of non-data calibration signals; and
updating a set of pre-distortion coefficients, based on the comparison, to compensate for the distortion coefficients of the nonlinear PA.

US Pat. No. 11,115,067

MULTI-BAND LINEARIZATION SYSTEM

NanoSemi, Inc., Waltham,...


1. A method for digital predistortion of multiband signals, the method comprising:receiving an input signal comprising multiple signal portions in different frequency bands, the input signal configured to be processed by a transmit chain of a power amplification system with the transmit chain comprising at least a power amplifier that produces output with non-linear distortions, wherein the non-linear distortions of the transmit chain are represented using a set of basis functions derived according to a single-band model of the non-linear distortions; and
performing digital predistortion on signal components derived from the multiple signal portions of the input signal using a reduced set of the basis functions that excludes at least some basis functions for at least some cross-terms resulting from a full expansion of the single-band model of the non-linear distortions applied to the multiple signal portions, to produce a digital predistorted signal provided to the transmit chain;
wherein performing the digital predistortion comprises computing digital predistortion coefficients to weigh the reduced set of basis functions, including deriving a first group of coefficients for a first group of the basis function terms operating on input values of the signal components, a second group of coefficients for a second group of basis function terms operating on normalized input values of the signal components, and a third group of coefficients for a third group of basis function terms operating on input values of combinations of the signal components.

US Pat. No. 11,115,066

MULTI-PURPOSE RECEIVER CHAIN FOR WIFI APPLICATIONS

Intel Corporation, Santa...


1. A WiFi transceiver comprising:a receive chain comprising a variable receive (Rx) filter circuit and a variable Rx analog-to-digital converter (ADC) circuit, wherein the receive chain is configured to:receive a receive signal during a receive mode of operation, having a receive bandwidth associated therewith; and
receive a transmit signal associated with a transmit chain of the transceiver during a transmit mode of operation, having a transmit bandwidth associated therewith; and

a control circuit configured to dynamically adapt a bandwidth of the variable Rx filter and the variable Rx ADC in the receive chain to one of the receive bandwidth and the transmit bandwidth, based on the mode of operation.

US Pat. No. 11,115,065

METHOD AND APPARATUS FOR DYNAMIC TUNING

NXP USA, Inc., Austin, T...


1. A communication device, comprising:a processing system including a processor; and
a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations, the operations comprising:during frequency division duplex (FDD) communication, adjusting a matching network including a tunable reactive element utilizing a weighted tuning state resulting in a tuning, wherein the weighted tuning state is determined from applying a first weighting factor to first, second, and third tuning states that are predetermined tuning states based on increasing performance in transmit, receive and duplex operation, respectively, wherein the first, second and third tuning states comprise sets of digital to analog converter values, and wherein the first weighting factor is based on an interpolation that utilizes digital to analog converter values of at least two of the first, second and third tuning states;
determining a weighted reference metric based on a second weighting factor, and first, second and third reference metrics, the first, second and third reference metrics selected from first, second and third groups of reference metrics, wherein the first, second and third groups of reference metrics are expected metrics based on the increasing performance in the transmit, receive and duplex operation, respectively;
responsive to the tuning, determining a first performance metric according to a first measurement associated with the FDD communication; and
responsive to a first determination that the first performance metric satisfies a first threshold according to a first comparison of the first performance metric to the weighted reference metric, continuing the tuning utilizing the weighted tuning state.


US Pat. No. 11,115,064

ERROR CORRECTION DECODER AND MEMORY SYSTEM HAVING THE SAME

SK hynix Inc., Icheon-si...


1. An error correction decoder for improving an error correction decoder performance using an iterative decoding scheme, comprising:a memory configured to store a hard decision value of a variable node;
a flipping function value generator configured to generate, in an i-th iteration, a first value based on a difference between a number of unsatisfied check nodes (UCNs) corresponding to the variable node and a number of satisfied check nodes (SCNs) corresponding to the variable node, and generate a flipping function value by selectively updating the first value based on a comparison of the first value to a reference value; and
a comparator configured to output, in the i-th iteration, a first signal indicating whether to flip or not flip the hard decision value of the variable node in the memory based on comparing the flipping function value to a flipping threshold value.

US Pat. No. 11,115,063

FLASH MEMORY CONTROLLER, STORAGE DEVICE AND READING METHOD

SILICON MOTION, INC., Jh...


1. A flash memory controller, configured to access a flash memory, the flash memory controller comprises:a read-only memory, configured to store a code;
a processor, configured to execute the code to control access to the flash memory; and
an error correction code unit, comprising an LDPC (low-density parity check) decoder, the LDPC decoder is configured to perform a decoding process, and the LDPC decoder comprises:a variable-node circuit, configured to generate a plurality of variable-node messages according to a plurality of channel values of a plurality of codeword segments of a first codeword, the variable-node circuit skips a plurality of first variable-node messages of the plurality of variable-node messages according to a decoding indication, and the variable-node circuit performs a variable-node calculation according to a plurality of second variable-node messages and a plurality of check-node messages, so as to update the plurality of second variable-node messages, wherein the plurality of second variable-node messages are the variable-node messages in the plurality of variable-node messages that are not the plurality of first variable-node messages, each of the codeword segments corresponds to multiple ones of the plurality of variable-node messages, and the plurality of first variable-node messages correspond to a codeword segment whose decoding status is passed;
a check-node circuit, configured to perform a check-node calculation according to the plurality of variable-node messages so as to generate and update the plurality of check-node messages;
a segment detection circuit, configured to detect each of the codeword segments according to the variable-node messages that correspond to each of the codeword segments, so as to generate and update the corresponding decoding status of each of the codeword segments;
a syndrome check circuit, configured to determine whether the first codeword is successfully decoded according to results of the check-node calculation; and
a control circuit, configured to check whether the decoding status of each of the codeword segments is passed, and to generate the decoding indication when it is found that the decoding status of one of the codeword segments is failed, the control circuit increases a recursive number by one when completing one iteration of the check-node calculation and one iteration of the variable-node calculation each time, and the control circuit enables the variable-node circuit to output a decoding result when the syndrome check circuit determines that the first codeword is successfully decoded.


US Pat. No. 11,115,062

MEMORY SYSTEM WITH ADAPTIVE THRESHOLD DECODING AND METHOD OF OPERATING SUCH MEMORY SYSTEM

SK hynix Inc., Gyeonggi-...


11. A method of decoding a codeword comprising a plurality of bits, wherein for a select one of the plurality of bits, which belongs to at least one component codeword of the codeword, the method comprising:performing an initial decision for the select bit;
initialize syndromes of each component codeword;
generate initial bit-flipping decision for the select bit, unsatisfied check (USC) information, and channel information by hard decoding;
bias the channel information of the select bit based on the degree of the select bit;
computing a reliability indicator of an initial decision, represented by at least one bit, as to whether to flip the select bit based on the initial decision and the biased channel information;
comparing the reliability indicator with an adaptive threshold, which is determined based on the degree of the select bit and the unsatisfied check (USC) information from the initial decision;
deciding whether to flip the select bit based on the comparing operation; and
updating the initial decision and syndromes of each component codeword to which the select bit belongs based on the comparing operation.

US Pat. No. 11,115,061

ERROR DETECTION

STMicroelectronics (Rouss...


1. A method, comprising writing a datum in memory by:splitting a binary word, representative of said datum and an error correcting or detecting code, into at least a first part and a second part; and
writing said first part at a logical address in a first memory circuit; and
writing said second part at said logical address in a second memory circuit, wherein said second memory circuit is different from said first memory circuit and is configured to store as many binary words as said first memory circuit;
wherein said error correcting or detecting code is dependent on both said datum and said logical address.

US Pat. No. 11,115,060

PARALLEL BIT INTERLEAVER

PANASONIC CORPORATION, O...


1. A bit interleaving method for interleaving bits of a codeword generated based on a low-density parity check coding scheme, a parity-check matrix of the low-density parity check coding scheme having a quasi-cyclic structure, the bit interleaving method comprising:applying a bit permutation process to the codeword made up of N cyclic blocks each consisting of Q bits, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits;
dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits; and
mapping each of the constellation words onto a modulated signal, wherein
N is not a multiple of M,
the bit permutation rule is a rule for applying column-row permutation of writing the Q bits in each of N?=N?X cyclic blocks of the N cyclic blocks in a row direction to a row among M rows of a matrix and reading in a column direction, where X is a remainder of N divided by M, and
X cyclic blocks include a cyclic block in a parity section of the codeword.

US Pat. No. 11,115,059

ENCODING CIRCUIT, DECODING CIRCUIT, ENCODING METHOD, DECODING METHOD, AND TRANSMITTING DEVICE

FUJITSU LIMITED, Kawasak...


1. An encoding circuit comprising:an allocator configured to allocate, to a plurality of bit strings, symbols that are among a plurality of symbols within a constellation of multilevel modulation and correspond to values of the plurality of bit strings within a frame;
a converter configured to convert values of each of bit strings among the plurality of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region among the plurality of symbols is larger;
a switch configured to switch, in a cycle of the frame, between a first time period in which a first error correction code to correct an error of the plurality of bit strings is inserted in the plurality of bit strings and a second time period in which the first error correction code is not inserted in the plurality of bit strings; and
a first insertor configured to generate the first error correction code from a second bit string among the plurality of bit strings in the second time period and inserts the first error correction code in two or more bit strings including the first bit string in the first time period in accordance with the switching by the switch.

US Pat. No. 11,115,058

CODING DEVICE, TRANSMITTER, DECODING DEVICE, AND RECEIVER

Mitsubishi Electric Corpo...


1. A coding device comprising:processing circuitry configured to:generate a parity of a first error-correcting code by coding, based on the first error-correcting code, each first data sequence existing in a direction different from a row direction of input data regarded as one matrix, and generate coded data by attaching the parity of the first error-correcting code to each first data sequence, thereby consequently expanding the matrix;
generate a parity of a second error-correcting code by coding, based on the second error-correcting code, each second data sequence existing in a row direction of the generated coded data, and generate a plurality of frames including, per frame, one data sequence existing in the row direction of the coded data, and a corresponding parity of the second error-correcting code; and
insert an identifier for identifying a top of the coded data in a first row of the coded data.


US Pat. No. 11,115,057

EFFICIENT ERASURE CODING OF MID-SIZE DATA OBJECTS

EMC IP HOLDING COMPANY LL...


1. A system, comprising:a processor, and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, the operations comprising:obtaining, in a node cluster data storage system, object data corresponding to an object to be protected with an erasure coding scheme;
determining that the object data is of a size that is to be protected without a preliminary protection scheme; and
storing the object based on the erasure coding scheme, comprising dividing the object data into object data fragments, performing erasure coding on the object data to obtain object coding fragments, and writing the object data fragments and the object coding fragments to a group of data structure fragments distributed in the node cluster data storage system,
wherein the group of data structure fragments are associated with a distributed chunk data structure in the node cluster data storage system, and wherein storing the object comprises writing the object data fragments to a same offset location within the distributed chunk data structure.


US Pat. No. 11,115,056

LOCATION SELECTION BASED ON ERASURE CODE TECHNIQUES

International Business Ma...


1. A system comprising:a disk drive comprising a plurality of storage disks implementing a Random Array of Independent Disks (RAID) storage device configuration, wherein:each storage disk of the plurality of storage disks in the disk drive includes at least an inner storage track and an outer storage track for storing data,
at least one storage disk in the plurality of storage disks includes a fast storage disk, and
at least one storage disk in the plurality of storage disks includes a slow storage disk,

a monitor module that:monitors data speed characteristics for each storage location of a plurality of storage locations positioned on each storage disk in the plurality of storage disks of the disk drive, and
determines a current data transfer speed for each storage location of the plurality of storage locations positioned on the plurality of storage disks based on the monitored data speed characteristics for each storage location, wherein:each storage location is positioned on a storage track of a storage disk comprising one of:the outer storage track positioned on any storage disk of the plurality of storage disks,
the inner storage track positioned on any storage disk of the plurality of storage disks,
any storage track positioned on the fast storage disk,
any storage track positioned on the slow storage disk,
the outer storage track positioned on the slow storage disk,
the inner storage track positioned on the slow storage disk,
the outer storage track positioned on the fast storage disk, and
the inner storage track positioned on the fast storage disk, and

storage locations positioned on the outer storage track of each storage disk include faster data transfer speeds than storage locations positioned on the inner storage track of the same storage disk, and

determines data transfer speed differences between each different storage location in the plurality of storage locations positioned on the plurality of storage disks of the disk drive;

a classification module that determines each erasure code technique of a plurality of erasure code techniques associated with each data chunk of a plurality of data chunks; and
a selection module that selects a storage location in the plurality of storage locations on the plurality of storage disks of the disk drive for storing each data chunk based on a correlation of the current data transfer speed of each storage location and an erasure code technique associated with each respective data chunk, wherein:the current data transfer speed of each storage location in the plurality of storage locations on the plurality of storage disks of the disk drive corresponds to a data transfer speed of a plurality of data transfer speeds,
each erasure code technique in the plurality of erasure code techniques is associated with one of the data transfer speeds in the plurality of data transfer speeds,
at least two erasure code techniques include different data transfer speeds in the plurality of data transfer speeds, and
the selected storage location is selected based on an intersection of the current data transfer speed determined for the storage location, the erasure code technique associated with a data chunk for storage at the selected storage location, and a data transfer speed difference between the selected storage location and at least one other storage location in the disk drive.


US Pat. No. 11,115,055

METHOD AND APPARATUS FOR ENCODING AND DECODING DATA IN MEMORY SYSTEM

SAMSUNG ELECTRONICS CO., ...


1. A decoding circuit for performing an error correction in a memory system, the decoding circuit comprising:a Bose-Chaudhuri-Hocquenghem (BCH) decoder comprising:a Syndrome stage for generating syndromes based on a BCH encoded word stored in the memory system;

a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients;
a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) circuit to generate error bits and iteration information, wherein the Chien stage includes a first FFT stage operating on the ELP coefficients and a counter, and
a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information output from the counter incremented for each iteration of the first FFT stage,
wherein the BCH decoder performs the error correction on data of the BCH encoded word using the reordered error bits.

US Pat. No. 11,115,054

POLAR CODE ENCODING METHOD AND APPARATUS

Huawei Technologies Co., ...


1. A method, comprising:obtaining, by a device, a first sequence corresponding to a required mother code length, wherein the first sequence is generated based on a basic sequence, and a length of the basic sequence is less than the mother code length;
obtaining, by the device, a to-be-encoded bit; and
performing, by the device, polar code encoding on the to-be-encoded bit using the first sequence, to obtain an encoded bit, wherein:the basic sequence comprises a second sequence whose length is N, the first sequence has a length of 2N and is obtained by sorting reliability values of the second sequence and reliability values of a third sequence in ascending order, sequence numbers of N polarized channels in the second sequence are arranged in a predetermined order, and the predetermined order is different from an order of polarization weights of the N polarized channels;
reliability values of the N polarized channels in the second sequence arranged in the predetermined order respectively correspond to polarization weight values of the N polarized channels that are arranged in ascending order, and indexes of polarized channels of the N polarized channels corresponding to the second sequence are 0, . . . , and 2N?1; and
reliability values of N polarized channels arranged in the predetermined order in the third sequence are obtained by adding a first difference to a respective polarization weight value of each polarized channel in the second sequence, and indexes of polarized channels of the N polarized channels corresponding to the third sequence are N, . . . , and 2N?1.


US Pat. No. 11,115,053

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 4096-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

ELECTRONICS AND TELECOMMU...


1. A method of transmitting a broadcast signal, comprising:storing a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15;
generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword;
storing the interleaved codeword corresponding to 4096-symbol mapping,
performing 4096-symbol mapping for generating a broadcast signal; and
transmitting the broadcast signal over a physical channel,
wherein the interleaving is performed using the following equation using permutation order:Yj=X?(j) 0?j
where X?(j) is the ?(j)th bit group, Yj is an interleaved j-th bit group, and ?(j) is a permutation order for bit group-based interleaving,
wherein the permutation order corresponds to an interleaving sequence represented by the followinginterleaving sequence={14 129 71 96 171 36 144 64 162 4 86 128 113 7 105 131 2 133 106 79 11 152 26 118 158 126 17 55 45 111 138 84 6 52 167 38 20 101 31 120 5 112 74 69 121 9 154 15 146 116 63 1 114 83 124 109 39 75 123 57 49 30 21 40 43 77 157 44 13 99 34 147 166 56 155 176 95 102 119 161 37 159 97 68 122 163 89 61 107 22 10 127 87 103 179 172 66 59 8 145 88 132 110 54 47 153 25 32 73 42 148 150 28 91 18 24 19 53 136 48 76 35 151 173 149 142 160 94 117 169 165 141 80 67 170 164 82 65 60 135 168 23 100 134 90 98 125 85 137 81 41 156 50 3 29 16 72 177 0 78 62 139 93 46 12 175 130 51 178 92 115 174 27 70 58 33 104 140 108 143},

wherein the interleaved codeword is generated by the interleaving using the interleaving sequence on the bit group basis before performing the 4096-symbol mapping so as to distribute burst errors occurring in the transmission signal transmitted over the physical channel.

US Pat. No. 11,115,052

INFORMATION PROCESSING METHOD AND COMMUNICATIONS APPARATUS

HUAWEI TECHNOLOGIES CO., ...


1. A method of channel encoding in a communications system, the method comprising:encoding, by a terminal of the communications system, an input sequence by using a low density parity check (LDPC) matrix to obtain a bit sequence D, wherein the input sequence is control information or data information to be sent from the terminal to a base station of the communications system, wherein a base matrix of the LDPC matrix is represented by a matrix of m rows and n columns, wherein each column corresponds to a group of Z continuous bits in the bit sequence D, and wherein both n and Z are integers greater than 0; obtaining, by the terminal, a bit sequence V by permuting groups of bits corresponding to at least two parity check columns in the bit sequence D, wherein the at least two parity check columns are at least two columns of a column (n?m) to a column (n?1) of the base matrix, wherein a group j of Z continuous bits in the bit sequence V are a group P(j) of Z continuous bits in the bit sequence D, and wherein j is an integer that is smaller than n and greater than or equal to 0; and
obtaining, by the terminal, an output bit sequence based on the bit sequence V.

US Pat. No. 11,115,051

SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES

INNOGRIT TECHNOLOGIES CO....


1. A method, comprising:performing a hard decision decoding on a codeword to generate check constraints satisfaction information by a hard decision decoder, the hard decision decoding being based on a parity check matrix for the codeword being represented in a bipartite graph with symbols in the codeword represented as bit nodes and parity check equations for the codeword represented as check nodes, and the check constrains satisfaction information including which parity check equations are satisfied and which parity check equations are unsatisfied;
sending the check constraints satisfaction information from the hard decision decoder to a soft decision decoder;
determining which check nodes are satisfied and which check nodes are unsatisfied based on which parity check equations are satisfied and which parity check equations are unsatisfied in the check constraints satisfaction information generated by the hard decision decoder;
scheduling a check node processing order based on which parity check equations are satisfied and which parity check equations are unsatisfied in the check constraints satisfaction information generated by the hard decision decoder by moving at least one unsatisfied check node that would be processed after at least one satisfied check node in a sequential order to be processed ahead of the at least one satisfied check node, the sequential order being an order of the parity check equations in the parity check matrix; and
performing a soft decision decoding by the soft decision decoder on the codeword to go over the parity check equations in the parity check matrix according to the check node processing order.

US Pat. No. 11,115,050

HARDWARE FRIENDLY DATA DECOMPRESSION

INNOGRIT TECHNOLOGIES CO....


1. A method, comprising:receiving encoded data to be decompressed;
obtaining a size “Stotal” of a total number of symbols in the encoded data, numbers of occurrences for distinct symbols in the encoded data, and a final state generated during an encoding process as a first state for decoding;
building a decoding table containing a row of the distinct symbols corresponding to L encoding states, a row of substitutes for numbers of bits to be recovered corresponding to the L encoding states and a row of substitutes for new states corresponding to the L encoding states, wherein L is equal to a sum of the numbers of occurrences for the distinct symbols;
decoding the encoded data using the decoding table including:obtaining a current symbol from the decoding table based on a current state X;
dynamically determining a current number of bits to be recovered from the encoded data and a new state X based on a corresponding substitute for number of bits to be recovered and a corresponding substitute for a new state from the decoding table for the current state X; and

outputting symbols recovered from the encoded data.

US Pat. No. 11,115,049

HARDWARE FRIENDLY DATA DECOMPRESSION

INNOGRIT TECHNOLOGIES CO....


1. A method, comprising:receiving encoded data to be decompressed;
obtaining a size “Stotal” of a total number of symbols in the encoded data, numbers of occurrences for distinct symbols in the encoded data, and a final state generated during an encoding process as a first state for decoding;
building a decoding table containing the distinct symbols corresponding to L encoding states, wherein L is equal to a sum of the numbers of occurrences for the distinct symbols;
decoding the encoded data using the decoding table including: obtaining a current symbol from the decoding table based on a current state X, dynamically determining a current number of bits to be recovered from the encoded data and a new state X; and
outputting symbols recovered from the encoded data.

US Pat. No. 11,115,046

CLOSED LOOP CONTROL IN A CAMERA MODULE

Cirrus Logic, Inc., Aust...


1. A system comprising:an output stage for driving a load at an output of the output stage;
a pulse-width modulation mode path configured to pre-drive the output stage in a first mode of operation;
a linear mode path configured to pre-drive the output stage in a second mode of operation; and
a loop filter, wherein an input of the loop filter is coupled to the output of the output stage and wherein an output of the loop filter is coupled to both of the pulse-width modulation mode path and the linear mode path;
wherein the pulse-width modulation mode path and the linear mode path are configured such that a first transfer function between the output of the loop filter and the output of the output stage through the pulse-width modulation mode path is substantially equivalent to a second transfer function between the output of the bop filter and the output of the output stage through the linear mode path,
such that an output of the loop filter after switching between the first mode of operation and the second mode of operation settles to approximately the same value as the output of the loop filter before switching between the first mode of operation and the second mode of operation.

US Pat. No. 11,115,045

ADAPTIVE ANALOG-TO-DIGITAL CONVERTER FOR PULSED SIGNALS BASED ON MULTI-BIT SIGMA-DELTA MODULATION

ARIZONA BOARD OF REGENTS ...


1. A delta sigma modulator comprising:a summation circuit configured to produce a difference signal between an analog input signal and an analog feedback signal;
at least one integrator operatively coupled to the summation circuit to integrate the difference signal;
a multi-bit quantizer operatively coupled to the at least one integrator to digitize the integrated signal to generate an N-bit digital output signal, N being an integer greater than 1; and
a negative feedback circuit operatively coupling the multi-bit quantizer to the summation circuit, the negative feedback circuit including a digital-to-analog converter arrangement for receiving the N-bit digital output signal and providing the analog feedback signal such that digital values of the N-bit digital output signal and values of the analog feedback encoded by the digital values have a non-linear relationship to one another.

US Pat. No. 11,115,044

LOOP DELAY COMPENSATION IN A DELTA-SIGMA MODULATOR

TEXAS INSTRUMENTS INCORPO...


1. A modulator, comprising:a first integrator having an input node and a first integrator output;
a first digital-to-analog converter (DAC) coupled to the first integrator output;
a second integrator having a second integrator input and a second integrator output, the second integrator input coupled to the first integrator output;
a comparator having a comparator input, and a comparator output, the comparator input coupled to the second integrator output; and
a second current DAC comprising:a current source device;
a first transistor having a first transistor control input and first and second current terminals, the first current terminal coupled to the current source device, and the second current terminal coupled to the second integrator output;
a second transistor having a second transistor control input and third and fourth current terminals, the third current terminal coupled to the current source device, and the fourth current terminal coupled to the second integrator output; and
a first capacitive device coupled to the first transistor control input and to both the fourth current terminal and the second integrator output.


US Pat. No. 11,115,043

DIGITAL-TO-ANALOG CONVERSION DEVICE AND DIGITAL-TO-ANALOG CONVERSION SYSTEM


1. A digital-to-analog conversion device, comprising:a main clock input for receiving a number of one or more main clock signals and providing at least two clock signals based on the received number of one or more main clock signals, wherein each of the at least two clock signals has a different clock frequency; and
multiple digital-to-analog conversion units, each digital-to-analog conversion unit comprising:at least two clock inputs for receiving the at least two clock signals provided by the main clock input;
a digital input for receiving a digital data signal;
an interpolator for interpolating the received digital data signal by a predetermined interpolation factor and outputting an interpolated digital data signal; and
a digital-to-analog core for receiving the interpolated digital data signal and converting the received interpolated digital data signal to an analog signal according to one of the clock signals received by the at least two clock inputs.


US Pat. No. 11,115,042

LOW PASS FILTER EMBEDDED DIGITAL-TO-ANALOG CONVERTER

Beken Corporation, Shang...


1. A circuit, comprising:a first switch coupled to a first node that is coupled to a fourth switch and a first parallel array of binary-weighted linear capacitors;
a second switch coupled to a first voltage of common mode and a second node that is coupled to the first parallel array and a third switch;
a positive input port of a second operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor;
a negative output port of the second operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch;
a fifth switch coupled to a fifth node that is coupled to a second parallel array of binary-weighted linear capacitors and an eighth switch;
a sixth switch coupled to the first voltage of common mode and a sixth node that is coupled to the second parallel array and a seventh switch;
a negative input port of the second operational amplifier coupled to a seventh node that is coupled to the seventh switch and a fourth capacitor; and
a positive output port of the second operational amplifier coupled to an eighth node that is coupled to the fourth capacitor and the eighth switch;
wherein the first parallel array and the second capacitor are in series; wherein the second parallel array and the fourth capacitor are in series; and wherein the first parallel array and second parallel array are in parallel with each other.

US Pat. No. 11,115,041

FILTER APPARATUS AND CONTROL METHOD

Infineon Technologies AG,...


1. A system comprising:an analog-to-digital converter configured to convert an analog signal generated by a digital sensor into a digital signal; and
a testing apparatus configured to be enabled after the analog-to-digital converter operates in a testing mode, wherein the testing apparatus comprises:a filter configured to receive the digital signal from the analog-to-digital converter, and apply a filtering process to the digital signal, wherein as a result of applying the filtering process, the digital signal having a first sample rate is converted into a result having a second sample rate lower than the first sample rate, and wherein in the filtering process, the filter keeps accumulating values of the digital signal until the number of clock cycles reaches a predetermined reference value;
a control circuit configured to terminate the filtering process after an output of the control circuit reaches the predetermined reference value; and
a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process.


US Pat. No. 11,115,040

ADC SLICER RECONFIGURATION FOR DIFFERENT CHANNEL INSERTION LOSS

eTopus Technology Inc., ...


1. A receiver comprising:a clock generator including a plurality of clock signal generators that generate a plurality of sampling clock signals having a plurality of sampling phases, each of the plurality of sampling clock signals having a corresponding one of the plurality of sampling phases; and
a plurality of time-interleaved analog-to-digital converters (ADC) that each sample an analog input signal at a corresponding one of the plurality of sampling phases to convert the analog signal into a digital sample, each of the plurality of time-interleaved ADCs including a plurality of sub-ADCs;
wherein each of the plurality of sub-ADCs of at least one of the plurality of time-interleaved ADCs includes a plurality of time-interleaved successive approximation (SAR) ADC slices that sample the analog input signal at a data rate of the receiver;
wherein responsive to the receiver being configured to operate at a first insertion loss mode from a plurality of insertion loss modes, a first set of the plurality of SAR ADC slices of at least one of the plurality of sub-ADCs is enabled to sample the analog input signal at the data rate of the receiver to generate the digital sample, wherein during the first insertion loss mode the receiver is configured to convert the analog signal into the digital sample such that the digital sample has a first insertion loss during the first insertion loss mode; and
wherein responsive to the receiver being configured to operate at a second insertion loss mode from the plurality of insertion loss modes that is different from the first insertion loss mode, a second set of the plurality of SAR ADC slices of the at least one of the plurality of sub-ADCs is enabled to sample the analog input signal at the data rate of the receiver to generate the digital sample, wherein during the second insertion loss mode the receiver is configured to convert the analog signal into the digital sample such that the digital sample has a second insertion loss during the second insertion loss mode and the second insertion loss is different from the first insertion loss, the second set of the plurality of SAR ADC slices including a second amount of SAR ADC slices that is different from a first amount of SAR ADC slices included in the first set of the plurality of SAR ADC slices.

US Pat. No. 11,115,038

METHOD FOR MANAGING THE STARTUP OF A PHASE-LOCKED LOOP AND CORRESPONDING INTEGRATED CIRCUIT

STMicroelectronics (Rouss...


1. A method for operating a phase-locked loop (PLL) circuit, comprising:delivering a reference signal for a phase comparator of the PLL circuit;
resetting a first divider of an output signal of a voltage-controlled oscillator of the PLL circuit at each first type signal edge of the reference signal;
outputting by the phase comparator, in response to the reference signal and a feedback signal derived from an output of said first divider, a control pulse at each second type signal edge of the reference signal; and
during startup, increasing a control voltage of the voltage-controlled oscillator in response to each control pulse by applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator;
after startup is complete, ceasing to apply the pre-charging current to the resistive capacitive filter in response to each control pulse.

US Pat. No. 11,115,037

SPUR CANCELATION IN PHASE-LOCKED LOOPS USING A RECONFIGURABLE DIGITAL-TO-TIME CONVERTER

Apple Inc., Cupertino, C...


1. An apparatus, comprising:an oscillator circuit configured to generate an oscillator signal;
a divider circuit configured to generate a plurality of divider output signals using the oscillator signal and a divisor, wherein a frequency of a given one of the plurality of divider output signals is a fractional quotient of a frequency of the oscillator signal;
a cancelation circuit configured to generate a feedback signal using a particular divider output signal, wherein a delay between the particular divider output signal and the feedback signal is based on an accumulated phase residue generated by the divider circuit; and
a comparator circuit configured to compare a reference signal to the feedback signal to generate a control signal; and
wherein the oscillator circuit is further configured to adjust the frequency of the oscillator signal using the control signal.

US Pat. No. 11,115,036

RESISTOR-CAPACITOR OSCILLATOR (RCO) WITH DIGITAL CALIBRATION AND QUANTIZATON NOISE REDUCTION

QUALCOMM INCORPORATED, S...


1. An apparatus, comprising:a switched capacitor havinga current source,
a first switching device,
a first capacitor coupled in series with the current source and the first switching device between a first voltage rail and a second voltage rail, and
a second switching device coupled in parallel with the first capacitor;

a low pass filter (LPF) including an input coupled to an output of the switched capacitor;
a reference voltage generator;
an integrator including a first input coupled to an output of the LPF and a second input coupled to an output of the reference voltage generator;
a voltage controlled oscillator (VCO) including an input coupled to an output of the integrator;
a first frequency divider including an input coupled to an output of the VCO; and
a switched capacitor driver including an input coupled an output of the first frequency divider, wherein the switched capacitor includes an input coupled to an output of the switched capacitor driver.

US Pat. No. 11,115,035

SEMICONDUCTOR DEVICES

MITSUBISHI HEAVY INDUSTRI...


1. A semiconductor device, comprising:first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively, for N being an odd number of three or more;
a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and
a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal,wherein the filter circuit comprises:
a first RS flipflop that has a reset terminal to which the majority clock signal or an inverted signal of the majority clock signal is provided; and
a first delay circuit that supplies a first delay signal to a set terminal of the first RS flipflop, the first delay signal being generated by delaying the majority clock signal,

wherein the output clock signal is generated in response to a signal output from a data output of the first RS flipflop.

US Pat. No. 11,115,034

SIGNAL DETECTION CIRCUIT AND SIGNAL DETECTION METHOD

Realtek Semiconductor Cor...


1. A signal detection circuit, comprising:a sampling circuit, configured to use a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal; and
a determination circuit, coupled to the sampling circuit, configured to refer to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip, wherein the chip comprises the signal detection circuit;
a clock signal generating circuit, configured to generate the plurality of clock signals having different phases according to a reference clock signal, wherein the clock signal generating circuit sequentially outputs the plurality of clock signals having different phases to the sampling circuit, for the sampling circuit to use only one of the plurality of clock signals to sample the input signal at a time.

US Pat. No. 11,115,033

SPEED-UP CHARGE PUMP AND PHASE-LOCKED LOOP AND METHOD FOR OPERATING THE SAME

UNITED MICROELECTRONICS C...


1. An electronic circuit, comprising:a speed-up charge pump, comprising:
a first charge pump, receiving an up signal and a down signal in digital form to produce a first voltage control signal at an output node;
at least one speed-up phase detector, comprising:a first circuit path to receive the up signal and delay the up signal by a predetermined delay as a delay up signal and operate the up signal and the delay up signal by AND logic into an auxiliary up signal unrelated to the down signal; and
a second circuit path to receive the down signal and delay the down signal by the predetermined delay as a delay down signal and operate the down signal and the delay down signal by AND logic into an auxiliary down signal unrelated to the up signal; and

at least one second charge pump, respectively receiving the auxiliary up and down signals to produce a second voltage control signal also at the output node.

US Pat. No. 11,115,032

PLL SYSTEM AND DEVICE WITH A LOW NOISE CHARGE PUMP


1. A phase locked loop system comprising:a phase frequency detector (PFD) providing a shifted UP pulse swinging between a first low voltage and a first high voltage; and
a first charge pump (CP) comprising a set of switching transistors and a set of constant gate bias transistors, in that the set of switching transistors are rated with a first breakdown voltage and a first switching speed, and the set of constant gate bias transistors are rated at a second breakdown voltage and a second switching speed, in that, the first breakdown voltage is substantially half the second breakdown voltage and the first switching speed is greater than the second switching speed,
wherein the PFD is coupled to the CP such that, the shifted UP pulse drives a first switching transistors in the set of switching transistors to provide a high voltage capable signal at an output terminal through a first constant bias transistor, in the set of constant gate bias transistors, that is biased for charge pump.

US Pat. No. 11,115,031

PHASE-LOCKED LOOP

Sony Semiconductor Soluti...


1. A phase-locked loop comprising:a SAR-ADC including a first capacitor and a second capacitor and configured to output a result of comparison between voltages generated from the first and second capacitors;
a current source that charges the first and second capacitors with current;
a first switch that is disposed between the first capacitor and the current source and that receives, as a first control signal, a phase difference between a first clock of a reference frequency and a second clock having a higher frequency than the first clock; and
a second switch that is disposed between the second capacitor and the current source and that receives, as a second control signal, the second clock.

US Pat. No. 11,115,030

METHOD AND CIRCUITS FOR CHARGE PUMP DEVICES OF PHASE-LOCKED LOOPS

Analog Bits Inc., Palo A...


1. A method to operate a charge pump comprising a p-channel source current network that includes more than one p-channel transistors and a p-channel current switch, and a n-channel sink current network that includes more than one n-channel transistors and a n-channel current switch, the method comprising:receiving, at the p-channel source current network, one or more p-bias inputs;
receiving, at the n-channel sink current network, one or more n-bias inputs;
establishing a baseline current that flows from a first p-channel transistor of the more than one p-channel transistors in the p-channel source current network and sinks to a first n-channel transistor of the more than one n-channel transistors in the n-channel sink current network, wherein the baseline current bypasses an output line; and
generating a voltage output on the output line by:
in response to the p-channel current switch being activated, drawing a first increment current from the first p-channel transistor, wherein the first increment current flows (i) through the p-channel current switch to the output line of the charge pump, and (ii) in parallel with respect to the baseline current, and wherein the first increment current is smaller than the baseline current that is present continuously both before and after the p-channel current switch is activated; and
in response to the n-channel current switch being activated, drawing a second increment current from the output line of the charge pump, wherein the second increment current flows (i) through the n-channel current switch to the first n-channel transistor, and (ii) in parallel with respect to the baseline current, and wherein the second increment current is smaller than the baseline current that is present continuously both before and after the n-channel current switch is activated.

US Pat. No. 11,115,029

INTEGRATED CIRCUIT DEVICE, OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE

Seiko Epson Corporation


1. An integrated circuit device comprising:a temperature sensor;
a heat generation source circuit serving as a heat generation source;
a pad for external coupling; and
a capacitor having a metal-insulator-metal (MIM) structure in which one electrode is electrically coupled to the pad for external coupling, wherein
the capacitor having the MIM structure and the temperature sensor overlap in a plan view orthogonal to a substrate on which a circuit element is formed.

US Pat. No. 11,115,028

OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE

SEIKO EPSON CORPORATION, ...


1. An oscillator comprising:a first resonator;
a second resonator;
a first oscillation circuit generating a first oscillation signal by oscillating the first resonator;
a second oscillation circuit generating a second oscillation signal that has frequency-temperature characteristics different from frequency-temperature characteristics of the first oscillation signal by oscillating the second resonator;
a clock signal generation circuit generating a clock signal with a frequency that is temperature compensated by temperature compensation data;
a storage unit storing information on a learned model that is machine-learned to output data corresponding to the temperature compensation data with respect to input data; and
a processing circuit obtaining the temperature compensation data by performing processing based on the information on the learned model with respect to the input data based on the first oscillation signal and the second oscillation signal,
wherein the processing circuit obtains frequency difference data representing a difference between a frequency of the first oscillation signal and a frequency of the second oscillation signal based on the first oscillation signal and the second oscillation signal, and performs processing based on the information on the learned model using the frequency difference data as the input data.

US Pat. No. 11,115,027

DIRECT CURRENT POWERED CLOCKLESS SUPERCONDUCTING LOGIC FAMILY USING DYNAMIC INTERNAL STATES

INTERNATIONAL BUSINESS MA...


1. An apparatus, comprising:a first circuit branch comprising a first Josephson junction arranged in series with a resistor;
a second circuit branch connected in parallel with the first circuit branch and comprising a second Josephson junction, wherein the first circuit branch is a dynamic circuit branch and wherein the second circuit branch is a static circuit branch;
a superconducting inductor connected in series with a parallel connection of the first circuit branch and the second circuit branch; and
an output port electrically biased by an energy-efficient rapid single flux quantum bias source comprised of a limiter Josephson Junction connected in series with a second inductor.

US Pat. No. 11,115,026

SYSTEMS AND METHODS FOR ROUTING DATA ACROSS REGIONS OF AN INTEGRATED CIRCUIT

Intel Corporation, Santa...


1. An integrated circuit comprising:a plurality of programmable logic regions;
a first plurality of routers, wherein each of the first plurality of routers is coupled to a respective programmable logic region of a first portion of the plurality of programmable logic regions, wherein each of the first portion of the plurality of programmable logic regions is disposed on an outer edge of the plurality of programmable logic regions; and
a second plurality of routers configured to communicatively couple to the first plurality of routers, wherein each of the second plurality of routers is coupled to a respective programmable logic region of a second portion of the plurality of programmable logic regions, wherein each of the second portion of the plurality of programmable logic regions is disposed adjacent to each of the first portion of the plurality of programmable logic regions is disposed on the outer edge of the plurality of programmable logic regions.

US Pat. No. 11,115,025

UNIVERSAL TRANSCEIVER CONTAINER

Intel Corporation, Santa...


1. A network adaptor, comprising:a plurality of physical coding sublayer (PCS) lanes;
a protocol intellectual property (IP) block configured to implement a first protocol;
a physical medium attachment (PMA) gasket circuitry configured to couple the PCS lanes to the protocol IP block;
an interconnect bus interface configured to provide connectivity between the network adaptor to an interconnect bus; and
a digital gasket circuitry configured to couple the protocol IP block to the interconnect bus interface.

US Pat. No. 11,115,024

INTEGRATED CIRCUIT, TEST METHOD FOR TESTING INTEGRATED CIRCUIT, AND ELECTRONIC DEVICE

KABUSHIKI KAISHA TOSHIBA,...


1. An integrated circuit comprising:a first logic circuit configured to first implement logic information; and
a first switch circuit configured to enable switching of wiring lines connected to the first logic circuit,
the first logic circuit comprising:
a first memory;
a first look-up table circuit having a first output terminal for outputting data stored in the first memory based on a first input signal;
a first selection circuit having a first input terminal to which the first output terminal is connected, a second input terminal that receives scan input data, and a second output terminal, the first selection circuit being configured to select one of the first input terminal and the second input terminal based on a scan enable signal and connect selected one of the first input terminal and the second input terminal to the second output terminal;
a first flip-flop having a third input terminal connected to the second output terminal and a third output terminal; and
a second selection circuit having a fourth input terminal connected to the third output terminal, a fifth input terminal connected to the first output terminal, and a fourth output terminal, the second selection circuit being configured to select one of the fourth input terminal and the fifth input terminal based on an enable signal and connect selected one of the fourth input terminal and the fifth input terminal to the fourth output terminal,
the first switch circuit performing the switching of the wiring lines in response to signals from the third output terminal and the fourth output terminal.

US Pat. No. 11,115,023

SYSTEMS AND METHODS FOR SIGNAL DISTRIBUTION

ZHEJIANG DAHUA TECHNOLOGY...


1. A system, comprising:at least one signal input circuit configured to receive target input signals from at least one sensor device;
at least one signal processing unit, each of the at least one signal processing unit including:at least one signal output circuit configured to output signals to a first electronic connection; and
at least one signal extraction circuit configured to obtain a reverse control signal from the first electronic connection;

at least one signal superimposing circuit configured to:
generate superimposed reverse control signals by superimposing the reverse control signal with other electronic signals, and
output the superimposed reverse control signal to the signal input circuit, and
a signal distributor connected to the at least one signal input circuit to distribute the target input signals to the at least one signal processing unit,
wherein each of the at least one signal processing unit further includes:at least one switch connected to the signal distributor, wherein the at least one switch includes:at least one input terminal connected to the signal distributor;
at least one output terminal connected to the at least one signal output circuit; and
at least one control terminal connected to the at least one signal extraction circuit.



US Pat. No. 11,115,022

SYSTEM AND METHOD FOR INTEGRATED CIRCUIT USAGE TRACKING CIRCUIT WITH FAST TRACKING TIME FOR HARDWARE SECURITY AND RE-CONFIGURABILITY

NORTHWESTERN UNIVERSITY, ...


1. A system, comprising:an aging accelerating circuit, the aging accelerating circuit to create a silicon marker during real-time operation to aid in determining a usage of a chip, wherein the aging accelerating circuit comprises a target aging transistor and supportive transistors, wherein the supportive transistors comprise transmission gates coupled to the target aging transistor, wherein, during a stress phase of the aging accelerating circuit, the transmission gates are configured to isolate the target aging transistor from the supportive transistors and the supportive transistors are configured to operate without overstress wherein the aging accelerating circuit transitions from the stress phase to a comparison phase, and enters a sleep phase after the comparison phase to provide aging protection to the aging accelerating circuit.

US Pat. No. 11,115,021

IMPEDANCE CALIBRATION CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...


1. An impedance calibration circuit comprising:a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor;
a second code generation circuit configured to:
form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and
generate a second code by using the second reference resistor; and
a target impedance code generation circuit configured to:
generate a target impedance code based on the first code, the second code, and a target impedance value, and
form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

US Pat. No. 11,115,019

DYNAMIC SHORT CIRCUIT PROTECTION

Ford Global Technologies,...


5. A test apparatus comprising:a pair of complementary-controlled insulated-gate bipolar transistors;
an inductor in parallel with one of the insulated-gate bipolar transistors; and
gate drive circuitry configured to, responsive to voltage across a parasitic inductance of the other of the insulated-gate bipolar transistors becoming zero during a short circuit event, disconnect a gate of the other of the insulated-gate bipolar transistors from a first resistor and connect the gate to a second resistor to alter a rate of discharge of the gate.

US Pat. No. 11,115,018

POWER TRANSISTOR OVERCURRENT PROTECTION CIRCUIT

SI EN TECHNOLOGY (XIAMEN)...


1. A power transistor overcurrent protection circuit, applied to a power transistor control circuit, the power transistor control circuit comprising a load and a controlled power transistor for controlling the load to work or not to work, the power transistor overcurrent protection circuit comprising:an overcurrent detection circuit, connected to the controlled power transistor; the overcurrent detection circuit being configured to detect whether there is an overcurrent flowing in the controlled power transistor; wherein if there is an overcurrent flowing in the controlled power transistor, an output terminal of the overcurrent detection circuit outputs an overcurrent signal; if there is no overcurrent flowing in the controlled power transistor, the output terminal of the overcurrent detection circuit outputs a normal signal;
a timing control circuit, connected to the output terminal of the overcurrent detection circuit; wherein when the timing control circuit is powered on, an output terminal of the timing control circuit outputs an ON signal; after the timing control circuit is powered on, the signal output from the output terminal of the timing control circuit is controlled according to the signal output from the output terminal of the overcurrent detection circuit; if the output terminal of the overcurrent detection circuit outputs the overcurrent signal, the output terminal of the timing control circuit continuously outputs an OFF signal within a set time and outputs the ON signal again after reaching the set time; if the output terminal of the overcurrent detection circuit outputs the normal signal, the output terminal of the timing control circuit keeps outputting the ON signal;
an enable control circuit, connected to the output terminal of the timing control circuit and a gate of the controlled power transistor; the enable control circuit being configured to control the controlled power transistor to be turned on or off, the enable control circuit being controlled by the signal output from the output terminal of the timing control circuit and an enable signal; wherein when the enable control circuit receives the OFF signal output from the timing control circuit, the enable control circuit turns off the controlled power transistor; when the enable control circuit receives the active enable signal and the ON signal output from the timing control circuit at the same time, the enable control circuit turns on the controlled power transistor;
wherein the timing control circuit is connected to the overcurrent detection circuit through a signal conversion circuit;
the overcurrent signal is a low-level signal, the normal signal is a high-level signal;
an input terminal of the signal conversion circuit is connected to the output terminal of the overcurrent detection circuit; the signal conversion circuit is configured to perform a level conversion on the signal output from the output terminal of the overcurrent detection circuit, the signal conversion circuit converts the high-level normal signal into a low-level hold signal to be output to an input terminal of the timing control circuit, the signal conversion circuit converts the low-level overcurrent signal into a high-level trigger signal to be output to the input terminal of the timing control circuit;
the input terminal of the timing control circuit is connected to an output terminal of the signal conversion circuit, after the timing control circuit is powered on, if the input terminal of the timing control circuit receives the hold signal, the output terminal of the timing control circuit keeps outputting the ON signal; if the signal received by the input terminal of the timing control circuit changes from the hold signal to the trigger signal, the output terminal of the timing control circuit continuously outputs the OFF signal within the set time and outputs the ON signal again after reaching the set time.

US Pat. No. 11,115,017

DRIVING APPARATUS AND SWITCHING APPARATUS

FUJI ELECTRIC CO., LTD., ...


1. A driving apparatus comprising:a gate driving circuit that turns off a first semiconductor element in response to receiving a signal for turning off the first semiconductor element included in the first semiconductor element and a second semiconductor element connected in series between a positive side power supply line and a negative side power supply line;
a measuring circuit that measures a parameter according to a voltage applied to the second semiconductor element;
a timing generating circuit that generates a first timing signal if the parameter satisfies a first condition during a time period in which the first semiconductor element is tuned off; and
a driving condition change circuit that, in response to the first timing signal, further decreases a changing speed of a gate voltage of the first semiconductor element than a reference speed during the time period in which the first semiconductor element is tuned off, wherein
the gate driving circuit turns off the first semiconductor element in also response to that the parameter satisfies a second condition during a time period in which the first semiconductor element is tuned on.

US Pat. No. 11,115,016

ELECTRONIC CIRCUIT WITH TWO VOLTAGE SUPPLY CIRCUITS

INFINEON TECHNOLOGIES AG,...


1. An electronic circuit comprising:an output, which is configured to be connected to a load; and
a first supply circuit and a second supply circuit, which are each connected to the output, and each comprise:
a supply input, which is configured to receive a respective input voltage;
a first circuit node;
a first electronic switch, which is connected between the output and the first circuit node;
a first rectifier element connected in parallel with the first electronic switch;
at least one second electronic switch, which is connected between the supply input and the first circuit node;
at least one second rectifier element, which is connected in parallel with the at least one second electronic switch, wherein the at least one second rectifier element and the first rectifier element are connected in antiseries with one another; and
a control circuit of at least one of the first and second supply circuits, wherein the control circuit is directly coupled to the first circuit node and coupled to the output, which is configured:
to activate the first electronic switch and the second electronic switch and
to receive a supply voltage from the first circuit node at a supply input.

US Pat. No. 11,115,015

DEVICE INCLUDING MULTI-MODE INPUT PAD

SKYWORKS SOLUTIONS, INC.,...


1. A circuit component having a multi-bit binary address, the multi-bit binary address determined from a voltage level applied to a single electrical contact of the circuit component, the circuit component configured to be assigned one of at least three unique multi-bit binary addresses and to select from among the at least three unique multi-bit binary addresses based on the voltage level, the multi-bit binary address assuming a first value responsive to the voltage level being a first voltage level, a second value responsive to the voltage level being a second voltage level, and a third value responsive to the voltage level being a floating voltage level between the first voltage level and the second voltage level, the circuit component further configured to be connected to a clock signal line and a data signal line in an electronic device along with at least two other substantially identical circuit components also configured to be connected to the clock signal line and the data signal line, each of the circuit component and the at least two other substantially identical circuit components having a unique multi-bit binary address selected from among the at least three unique multi-bit binary addresses.

US Pat. No. 11,115,014

DUTY CYCLE CORRECTION CIRCUIT

SHENZHEN GOODIX TECHNOLOG...


1. A duty cycle correction circuit, comprising:a first inverter comprising an input terminal and an output terminal, the input terminal of the first inverter being configured to receive a first signal, and the output terminal of the first inverter being configured to output a third signal, the third signal being an inverted signal of the first signal and having a first delay time relative to the first signal;
a first adjustment circuit comprising a first input terminal, a second input terminal, and an output terminal, the first input terminal of the first adjustment circuit being connected to the output terminal of the first inverter and configured to receive the third signal, and the output terminal of the first adjustment circuit being configured to output a first correction signal; and
a first delayer, an input terminal of the first delayer being configured to receive a second signal, a cycle length of the second signal being equal to a cycle length of the first signal and a phase of the second signal being different from a phase of the first signal by ½ of the cycle length, and an output terminal of the first delayer being connected to the second input terminal of the first adjustment circuit and configured to output a fourth signal to the first adjustment circuit, the fourth signal having the first delay time relative to the second signal;
wherein the first correction signal is at a high level when the third signal and the fourth signal are at the high level, and the first correction signal is at a low level when the third signal and the fourth signal are at the low level.

US Pat. No. 11,115,013

CIRCUIT ARRANGEMENT WITH CLOCK SHARING, AND CORRESPONDING METHOD

STMicroelectronics S.r.l....


1. A system comprising:a master circuit; and
a slave circuit configured to receive an external clock signal from the master circuit, the slave circuit comprising first and second peripheral circuits configured to receive respective first and second clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes for the first and second peripheral circuits, respectively, wherein the slave circuit comprises a logic circuit configured to generate a locking signal and provide the locking signal to the first peripheral circuit, the locking signal being supplied to the master circuit through an output terminal of the slave circuit, wherein the logic circuit is configured to generate the locking signal when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode of the two different timing modes before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode of the two different timing modes, the second timing mode being different from the first timing mode.

US Pat. No. 11,115,012

SOFTWARE-DEFINED PULSE ORCHESTRATION PLATFORM

Quantum Machines


1. A system comprising:a compiler operable to generate machine code from a program, wherein:the program comprises a pulse operation statement,
the pulse operation statement specifies a pulse to be generated,
the pulse operation statement specifies a target of the pulse, and
if loaded into a hardware circuit, the machine code configures the hardware circuit to generate the pulse and send the pulse to the target.


US Pat. No. 11,115,011

QUANTUM CONTROLLER ARCHITECTURE

Quantum Machines


1. A system comprising:a plurality of pulse generator circuits, wherein each pulse generator circuit of the plurality of pulse generator circuits is operable to generate one or more pulses;
a controlled element; and
a pulse management circuit operable to receive a definition of the controlled element and a definition of the one or more pulses, wherein the pulse management circuit is operable to configure, based on the definition of the controlled element and the definition of the one or more pulses, the plurality of pulse generator circuits to output the one or more pulses to the controlled element via a selection of one or more ports of the plurality of pulse generator circuits.

US Pat. No. 11,115,010

ENERGY LOADED DIELECTRICS, SYSTEMS INCLUDING ENERGY LOADED DIELECTRICS, AND METHODS FOR FABRICATION AND USE THEREOF

UNIVERSITY OF MARYLAND, C...


1. A method comprising:(a) selecting a waveform for each of one or more desired electromagnetic pulses (EMPs);
(b) providing a dielectric structure having a first shape and a loaded charge density spatial distribution therein, the dielectric structure being loaded with charge by irradiation with electrons, protons, or ions; and
(c) actuating the dielectric structure to discharge charge therein,
wherein (b) and (c) are such that the selected waveform for each of the desired one or more EMPs is generated, and
the actuating comprises introducing a spark or defect at a surface of the dielectric structure.

US Pat. No. 11,115,009

SEMICONDUCTOR INTEGRATED CIRCUIT

NUVOTON TECHNOLOGY CORPOR...


1. A semiconductor integrated circuit, comprising:a first flip-flop that includes a first input circuit, a first master latch that receives an output signal from the first input circuit, and a first slave latch that receives an output signal from the first master latch;
a second flip-flop that includes a second input circuit, a second master latch that receives an output signal from the second input circuit, and a second slave latch that receives an output signal from the second master latch; and
a clock generation circuit that provides a common clock signal to the first flip-flop and the second flip-flop, wherein
the first slave latch includes a first inverter, a first feedback inverter that receives an output signal from the first inverter, and a first switch that is connected between an input terminal of the first inverter and an output terminal of the first feedback inverter, and
the first flip-flop outputs a data output signal from the output terminal of the first feedback inverter to an outside of the semiconductor integrated circuit.

US Pat. No. 11,115,008

SINGLE EVENT UPSET-TOLERANT LATCH CIRCUIT AND FLIP-FLOP CIRCUIT

Japan Aerospace Explorati...


1. A single event upset-tolerant latch circuit configured such that four Dual Interlocked Storage Cell (DICE) elements are connected in series and in a loop configuration, each of the DICE elements being comprised of a p-type transistor and an n-type transistor, wherein a gate terminal in each one of the p-type and n-type transistors and a drain terminal in the other are mutually connected, each of the DICE elements having a first node Interconnecting between the gate terminal of the p-type transistor and the drain terminal of the n-type transistor, and a second node interconnecting between the drain terminal of the p-type transistor and the gate terminal of the n-type transistor, the single event upset-tolerant latch circuit comprising:a first DICE element comprised of a first p-type transistor (P1_1) and a first n-type transistor (N1_1), wherein a gate terminal in each one of the first p-type and n-type transistors and a drain terminal in the other are mutually connected;
a second DICE element comprised of a second p-type transistor (P2_1) and a second n-type transistor (N2_1), wherein a gate terminal in each one of the second p-type and n-type transistors and a drain terminal in the other are mutually connected;
a third DICE element comprised of a third p-type transistor (P3_1) and a third n-type transistor (N3_1), wherein a gate terminal in each one of the third p-type and n-type transistors and a drain terminal in the other are mutually connected; and
a fourth DICE element comprised of a fourth p-type transistor (P4_1) and a fourth n-type transistor (N4_1), wherein a gate terminal in each one of the fourth p-type and n-type transistors and a drain terminal in the other are mutually connected;
wherein:
a node interconnecting between a gate terminal of a p-type transistor comprised in the first DICE element and a drain terminal of an n-type transistor comprised in the first DICE element forms a first DICE element's first node;
a node interconnecting between a gate terminal of a p-type transistor comprised in the second DICE element and a drain terminal of an n-type transistor comprised in the second DICE element forms a second DICE element's first node;
a node interconnecting between a gate terminal of a p-type transistor comprised in the third DICE element and a drain terminal of an n-type transistor comprised in the third DICE element forms a third DICE element's first node;
a node interconnecting between a gate terminal of a p-type transistor comprised in the fourth DICE element and a drain terminal of an n-type transistor comprised in the fourth DICE element forms a fourth DICE element's first node;
a node interconnecting between a drain terminal of a p-type transistor comprised in the first DICE element and a gate terminal of an n-type transistor comprised in the first DICE element forms a first DICE element's second node;
a node interconnecting between a drain terminal of a p-type transistor comprised in the second DICE element and a gate terminal of an n-type transistor comprised in the second DICE element forms a second DICE element's second node;
a node interconnecting between a drain terminal of a p-type transistor comprised in the third DICE element and a gate terminal of an n-type transistor comprised in the third DICE element forms a third DICE element's second node; and
a node interconnecting between a drain terminal of a p-type transistor comprised in the fourth DICE element and a gate terminal of an n-type transistor comprised in the fourth DICE element forms a fourth DICE element's second node;
and wherein:
the first DICE element's first node is connected to the fourth DICE element's second node;
the second DICE element's first node is connected to the first DICE element's second node;
the third DICE element's first node is connected to the second DICE element's second node; and
the fourth DICE element's first node is connected to the third DICE element's second node;
and wherein:
the second DICE element's first node and the fourth DICE element's first node are connected, respectively, to a first data input part and a second data input part each configured such that a conduction state thereof is controlled by control of a clock; and
at least one of the first DICE element's second node, the second DICE element's second node, the third DICE element's second node and the fourth DICE element's second node is connected to a data output part;
and wherein:
each of the first p-type transistor (P1_1), the first n-type transistor (N1_1), the second p-type transistor (P2_1), the second n-type transistor (N2_1), the third p-type transistor (P3_1), the third n-type transistor (N3_1), the fourth p-type transistor (P4_1) and the fourth n-type transistor (N4_1) is configured such that three transistors for redundancy are added thereto at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel; and
each of the first data input part and the second data input part is made dually redundant.

US Pat. No. 11,115,007

METHODS AND APPARATUSES OF A TWO-PHASE FLIP-FLOP WITH SYMMETRICAL RISE AND FALL TIMES

Micron Technology, Inc., ...


1. An apparatus, comprising:a clock generator circuit comprising a two-phase flip-flop circuit configured to provide a first output signal and a second output signal, wherein the two-phase flip-flop circuit comprises a two-phase flip-flop coupled in series with a driver circuit, wherein the two-phase flip-flop is configured to provide, to the driver circuit, both a first driver control signal and a second driver control signal directly responsive to a same clock signal, wherein the first driver control signal and the second driver control signal are complementary, wherein first circuitry of the driver circuit is configured to provide the first output signal responsive to both of the first driver control signal and the second driver control signal, wherein second circuitry of the driver circuit is configured to provide the second output signal responsive to both of the first driver control signal and the second driver control signal, wherein the first output signal and the second output signal are complementary, wherein the first circuitry of the driver circuit comprises a pull-up passgate circuit configured to drive the first output signal to a logical high value responsive to the first and second control signals having first complementary values and a pull-down passgate circuit configured to drive the first output signal to a logical low value responsive to the first and second control signals having second complementary values, wherein the pull-up passgate circuit and the pull-down passgate circuit are each controlled by both of the first and second control signals.

US Pat. No. 11,115,006

INTERNAL LATCH CIRCUIT AND METHOD FOR GENERATING LATCH SIGNAL THEREOF

Integrated Silicon Soluti...


1. An internal latch circuit comprising:a first delay circuit receiving an input delay signal and an internal data strobe signal, and outputting a first internal input signal, wherein the input delay signal responds to a clock signal;
a second delay circuit coupled to the first delay circuit, the second delay circuit receiving the internal data strobe signal, and outputting a first reverse internal input signal;
a third delay circuit coupled to the second delay circuit, and receiving the internal data strobe signal and outputting a second internal input signal;
a fourth delay circuit coupled to the third delay circuit, and receiving the internal data strobe signal and outputting a second reverse internal input signal;
an internal latch signal generating circuit coupled to the first delay circuit, the second delay circuit, the third delay circuit, and the fourth delay circuit, and generating a first reverse pre-output signal according to the first internal input signal and the first reverse internal input signal, and generating a second reverse pre-output signal according to the second internal input signal and the second reverse internal input signal; and
a NAND gate coupled to the internal latch signal generating circuit, and generating an internal latch signal according to the first reverse pre-output signal and the second reverse pre-output signal.

US Pat. No. 11,115,005

RING VOLTAGE CONTROLLED OSCILLATOR (VCO) STARTUP HELPER CIRCUIT

Samsung Electronics Co., ...


1. A ring voltage controlled oscillator (VCO) circuit, comprising:a first stage including a first inverter, a second inverter, a third inverter and a fourth inverter, the first inverter of the first stage connected in parallel with the third and fourth inverters of the first stage and the second inverter of the first stage connected in parallel with the third and fourth inverters of the first stage;
a second stage connected in series with the first stage, the second stage including a first inverter, a second inverter, a third inverter and a fourth inverter, the first inverter of the second stage connected in parallel with the third and fourth inverters of the second stage and the second inverter of the second stage connected in parallel with the third and fourth inverters of the second stage;
a first biasing resistor directly connected to an input of the first inverter of the first stage and an output of the second inverter of the first stage, providing a resisting bias associated with a node of the second inverter of the first stage;
a second biasing resistor directly connected to an input of the second inverter of the first stage and an output of the first inverter of the first stage, providing a resisting bias associated with a node the first inverter of the first stage;
a third biasing resistor directly connected to an input of the first inverter of the second stage and an output of the second inverter of the second stage, providing a resisting bias associated with a node of the second inverter of the second stage; and
a fourth biasing resistor directly connected to an input of the second inverter of the second stage and an output of the first inverter of the second stage, providing a resisting bias associated with a node the first inverter of the second stage,
wherein the first and second inverter of the first stage are sized larger than the third and fourth inverter of the first stage, and
wherein the first and second inverter of the second stage are sized larger than the third and fourth inverter of the second stage.

US Pat. No. 11,115,004

FRACTIONAL DELAY FILTER FOR A DIGITAL SIGNAL PROCESSING SYSTEM


1. A processing element for implementation in a digital signal processing system, the processing element configured to:receive a first digital serial data stream comprising a plurality of samples of a radar signal;
convert the first digital serial data stream into a plurality of parallel data streams comprising time-ordered digital values;
store one or more of the digital values; and
weight each of the digital values consistent with a Farrow structured fractional delay filter using the plurality of digital values and one or more previously stored values to produce a plurality of filtered time-ordered digital values.

US Pat. No. 11,115,003

ACOUSTIC WAVE DEVICE, MULTIPLEXER, HIGH-FREQUENCY FRONT END CIRCUIT, AND COMMUNICATION APPARATUS

MURATA MANUFACTURING CO.,...


1. An acoustic wave device that is provided between a first terminal defining an antenna terminal and a second terminal different from the first terminal, the acoustic wave device comprising:a plurality of acoustic wave resonators; wherein
the plurality of acoustic wave resonators include:a plurality of series arm resonators provided on a first path connecting the first terminal and the second terminal; and
a plurality of parallel arm resonators provided on a plurality of second paths connecting a plurality of nodes on the first path and ground, respectively;

when an acoustic wave resonator that is electrically closest to the first terminal among the plurality of acoustic wave resonators is an antenna end resonator;the antenna end resonator is a first acoustic wave resonator; and
at least one acoustic wave resonator other than the antenna end resonator among the plurality of acoustic wave resonators is a second acoustic wave resonator;

each of the first acoustic wave resonator and the second acoustic wave resonator includes:a piezoelectric layer;
an IDT electrode provided on the piezoelectric layer and including a plurality of electrode fingers;
a high-acoustic-velocity layer located on a side opposite to the IDT electrode with the piezoelectric layer interposed therebetween and in which an acoustic velocity of a bulk wave propagating in the high-acoustic-velocity layer is higher than an acoustic velocity of an acoustic wave propagating in the piezoelectric layer; and
a low-acoustic-velocity film provided between the high-acoustic-velocity layer and the piezoelectric layer and in which an acoustic velocity of a bulk wave propagating in the low-acoustic-velocity film is lower than an acoustic velocity of a bulk wave propagating in the piezoelectric layer;

a thickness of the piezoelectric layer is equal to or less than about 3.5? where a wavelength of an acoustic wave, which is determined by an electrode finger cycle as a cycle of the plurality of electrode fingers of the IDT electrode, is ?;
a cut angle of the piezoelectric layer of the first acoustic wave resonator is within a range of about ?B±4° with reference to ?B (°) obtained by an equation (1) where the wavelength is ? (?m), a thickness of the IDT electrode is TIDT (?m), a specific gravity of the IDT electrode is ? (g/cm3), a duty ratio as a value obtained by dividing a width of the electrode fingers by a half value of the electrode finger cycle is Du, a thickness of the piezoelectric layer is TLT (?m), and a thickness of the low-acoustic-velocity film is TVL (?m);





anda cut angle of the piezoelectric layer of the second acoustic wave resonator has a larger difference from ?B (°) than the cut angle of the piezoelectric layer of the first acoustic wave resonator.

US Pat. No. 11,115,002

MULTIPLEXER, RADIO FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION DEVICE

MURATA MANUFACTURING CO.,...


1. A multiplexer comprising:a common terminal;
a first filter that is an acoustic wave filter electrically connected to the common terminal and that has a pass band; and
a second filter that is electrically connected to the common terminal and that has a pass band on a higher frequency side of the pass band of the first filter; wherein
the first filter includes:
a first input/output terminal;
a second input/output terminal;
a series arm circuit provided on a path connecting the first input/output terminal and the second input/output terminal; and
a parallel arm circuit electrically connected to a node on the path and ground;
in the parallel arm circuit or the series arm circuit, a frequency at which an impedance is locally minimum is defined as a resonant frequency, and a frequency at which an impedance is locally maximum is defined as an anti-resonant frequency, a frequency at which an impedance of a resonator is locally minimum is defined as a resonant frequency, and a frequency at which an impedance of the resonator is locally maximum is defined as an anti-resonant frequency, and the parallel arm circuit has a resonant frequency located on a lower frequency side of a frequency at a low frequency end of the pass band of the first filter;
the series arm circuit includes:
a first series arm resonator defined by an acoustic wave resonator having a resonant frequency in the pass band of the first filter; and
a second series arm resonator defined by an acoustic wave resonator that is electrically connected in parallel to the first series arm resonator and that has a resonant frequency located on a higher frequency side of a frequency at a high frequency end of the pass band of the first filter; and
the resonant frequency of the second series arm resonator is lower than a frequency at a low frequency end of the pass band of the second filter.

US Pat. No. 11,115,001

RECEIVING FILTER, MULTIPLEXER, AND COMMUNICATION APPARATUS

KYOCERA Corporation, Kyo...


1. A receiving filter comprisingan antenna terminal,
a reception terminal outputting signals from the antenna terminal,
a reception terminal wiring connected to the reception terminal,
a first filter of a longitudinally coupled double-mode type acoustic wave filter located in a signal path from the antenna terminal to the reception terminal,
a first reference potential terminal given a reference potential, and
a first reference potential wiring connected to the first reference potential terminal and to the first filter, wherein
a reception terminal conductor comprising the reception terminal and the reception terminal wiring and a first reference potential conductor comprising the first reference potential terminal and the first reference potential wiring are adjacent and capacitively coupled with respect to each other, further comprising
a piezoelectric substrate in which the antenna terminal, the reception terminal conductor, the first reference potential conductor, and the first filter are located on one surface, and
in a plan view of the surface, the first reference potential conductor extending so as to surround the reception terminal conductor together with the first filter.

US Pat. No. 11,114,999

FILTER INCLUDING ACOUSTIC WAVE RESONATOR

Samsung Electro-Mechanics...


1. A filter, comprising:series resonators disposed between an input terminal and an output terminal; and
shunt resonators disposed at different nodes between the input terminal and the output terminal,
wherein:a resonance frequency difference between at least one series resonator among the series resonators and each of the shunt resonators is narrower than an antiresonance frequency difference between the at least one series resonator and each of other series resonators among the series resonators; or
the resonance frequency difference between the at least one series resonator and each of the shunt resonators is narrower than a resonance frequency difference between the at least one series resonator and each of the other series resonators, and wherein an antiresonance frequency of the at least one series resonator is higher than an upper limit frequency of the filter.


US Pat. No. 11,114,998

TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATORS FOR HIGH POWER APPLICATIONS

Resonant Inc., Austin, T...


1. An acoustic resonator device comprising:a substrate having a surface;
a resonator comprising:a piezoelectric plate having front and back surfaces, the back surface attached to the surface of the substrate except for a portion of the piezoelectric plate forming a diaphragm that spans a cavity in the substrate;
an interdigital transducer (IDT) formed on the front surface of the piezoelectric plate such that interleaved fingers of the IDT are disposed on the diaphragm, the piezoelectric plate and the IDT configured such that a radio frequency signal applied to the IDT excites a shear primary acoustic mode in the diaphragm, wherein the IDT includes a busbar having a first portion overlapping the diaphragm and a second portion overlapping the substrate; and

conductive bumps electrically isolated from the resonator.

US Pat. No. 11,114,997

BULK-ACOUSTIC WAVE RESONATOR

Samsung Electro-Mechanics...


1. A bulk acoustic wave resonator comprising:a substrate;
a seed layer disposed on the substrate;
a first electrode disposed on the seed layer and comprising an aluminum alloy layer containing scandium (Sc);
a piezoelectric layer disposed on the first electrode and comprising a layer having only a cation (Al) polarity, wherein the piezoelectric layer comprises a first piezoelectric layer disposed on the first electrode and having only the cation (Al) polarity, an oxide layer disposed directly on the first piezoelectric layer, and a second piezoelectric layer disposed directly on the oxide layer and having an anion (N) polarity, wherein a ratio of a thickness of the first piezoelectric layer to a thickness of the second piezoelectric layer ranges from 0.11 to 0.59; and
a second electrode disposed on the second piezoelectric layer.

US Pat. No. 11,114,996

TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATORS WITH MOLYBDENUM CONDUCTORS

Resonant Inc., Austin, T...


1. An acoustic resonator device comprising:a single-crystal piezoelectric plate having front and back surfaces, a portion of the piezoelectric plate forming a diaphragm, wherein a thickness of the piezoelectric plate is greater than or equal to 300 nm and less than or equal to 500 nm; and
an interdigital transducer (IDT) formed on the front surface of the single-crystal piezoelectric plate such that interleaved fingers of the IDT are on the diaphragm, the piezoelectric plate and the IDT configured such that a radio frequency signal applied to the IDT excites a primary shear acoustic mode in the diaphragm, wherein the interleaved fingers of the IDT are substantially molybdenum, and wherein the diaphragm is contiguous with the piezoelectric plate around at least 50% of the IDT.

US Pat. No. 11,114,995

PIEZOELECTRIC COMPONENT

KYOCERA CORPORATION, Kyo...


1. A piezoelectric component, comprising:a substrate having a rectangular plate shape having a longitudinal direction and a width direction;
a pair of electrodes disposed on a first surface of the substrate so as to leave space therebetween which is located in a central region in the longitudinal direction of the substrate; and
a piezoelectric element both ends of which are fixed to the pair of electrodes, respectively,
the pair of electrodes each including a notch extending from a central region side and in the longitudinal direction of the substrate,
wherein the substrate includes a ground electrode at a central region of a second surface opposite to the first surface,
the pair of electrodes each includes a first area and a second area,
the first area is longer in the width direction of the substrate than the second area,
the second area extends from the first area toward the central region and in the longitudinal direction, and has a portion facing the ground electrode with the substrate interposed therebetween, and
the notch extends in the first area.

US Pat. No. 11,114,994

MULTILAYER FILTER INCLUDING A LOW INDUCTANCE VIA ASSEMBLY

AVX Corporation, Fountai...


1. A multilayer filter comprising:a dielectric layer having a top surface, a bottom surface, and a thickness in a Z-direction between the top surface and the bottom surface;
a conductive layer formed on the top surface of the dielectric layer;
a via assembly formed in the dielectric layer and connected to the conductive layer on the top surface of the dielectric layer, the via assembly extending to the bottom surface of the dielectric layer, the via assembly having a length in the Z-direction and a total cross-sectional area in an X-Y plane that is perpendicular to the Z-direction, and wherein the via assembly has an area-to-squared-length ratio that is greater than about 3.25, wherein the via assembly comprises a plurality of vias that are spaced apart by a spacing distance that is less than about 200 microns.

US Pat. No. 11,114,993

HIGH FREQUENCY MULTILAYER FILTER

AVX Corporation, Fountai...


1. A high frequency multilayer filter comprising:a plurality of dielectric layers;
a signal path having an input and an output; and
an inductor comprising a conductive layer formed over a first dielectric layer, and wherein the inductor is electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground, wherein the conductive layer of the inductor has an effective length between the first location and the second location that is less than about 2 mm; and
a capacitor comprising a first electrode and a second electrode that is separated from the first electrode by a second dielectric layer;
wherein the multilayer filter has a characteristic frequency that is greater than about 8 GHz.

US Pat. No. 11,114,992

MOTOR DRIVE WITH A FILTER INCLUDING A THREE-PHASE DIFFERENTIAL MODE REACTOR WITH COMMON MODE DAMPING

Schaffner EMV AG, Luterb...


1. Three-phase differential mode filter for a motor drive system having a first phase, a second phase, and a third phase, comprising for each one of the three phases a supply side input, a motor side input, a conductor between the supply side input and the motor side input for conducting a current of the motor drive between a supply and a motor, a connection point in the conductor, wherein the three-phase differential mode filter comprises three capacitors connected in a star point and/or delta connection with the connection points of the conductors of the first phase, second phase and third phase, wherein the three-phase differential mode filter comprises at least two of a first three-phase differential mode reactor between the supply side input and the connection point, a second three-phase differential mode reactor between the motor side input and the connection point, and a third three-phase differential mode reactor connected via a star point and/or delta connection with the connection points, wherein one of the at least two three-phase differential mode reactors is a common mode compensating three-phase differential mode reactor with:a first core element;
a second core element;
a third core element;
a first coil wound around the first core element for conducting the current of a first phase and for damping a differential mode noise currents in the first phase;
a second coil wound around the second core element for conducting the current of a second phase and for damping a differential mode noise currents in the second phase;
a third coil wound around the third core element for conducting the current of a third phase and for damping a differential mode noise currents in the third phase; and
wherein the common mode compensating three-phase differential mode reactor comprises an auxiliary coil wound such around the first core element, the second core element and the third core element that a common mode current in the first phase, the second phase and the third phase is induced in the auxiliary coil.

US Pat. No. 11,114,991

ANALOG FRONT-END CIRCUIT FOR CONDITIONING A SENSOR SIGNAL

International Business Ma...


1. An analog front-end (AFE) circuit for conditioning a sensor signal, the AFE circuit comprising:a first stage configured to amplify and filter the sensor signal, the first stage comprising a biquadratic filter comprising a first plurality of DC-coupled transconductance amplifiers;
a second stage configured to further amplify and filter the amplified sensor signal, and to compensate a direct current (DC) offset of the first stage, the second stage comprising a second plurality of AC-coupled transconductance amplifiers, wherein each transconductance amplifier of the first plurality of DC-coupled transconductance amplifiers and of the second plurality of AC-coupled transconductance amplifiers has a programmable transconductance and comprises a plurality of subthreshold-biased transistors; and
a circuit coupled to each stage of the first and second stages to perform calibration of each stage while each stage is actively processing the sensor signal.

US Pat. No. 11,114,990

APPARATUS AND METHOD OF POWER MANAGEMENT USING ENVELOPE STACKING

Anokiwave, Inc., San Die...


1. A reduced current RF power amplifier system comprising:a first RF amplifier for amplifying a first RF input signal and generating a first RF output signal;
a second RF amplifier for amplifying a second RF input signal and generating a second RF output signal; and
a stack/unstack controller including circuitry configured to switch the RF power amplifier system between a stacked mode in which said first and second RF amplifiers are coupled in a stacked configuration and an unstacked mode in which said first and second RF amplifiers are coupled in an unstacked configuration in response to one or more mode-control signals, the stacked configuration providing reduced current compared to the unstacked configuration.

US Pat. No. 11,114,989

POWER AMPLIFYING CIRCUIT

MURATA MANUFACTURING CO.,...


1. A power amplifying circuit comprising:a transistor configured to amplify a radio-frequency signal; and
a bypass capacitor section connected to a path that connects a collector end or a drain end of the transistor to a power supply terminal, wherein:
the bypass capacitor section comprises a first capacitor, a second capacitor, and a first switch circuit,
a first end of the first capacitor is connected to the power supply terminal, and a second end of the first capacitor is connected to a first end of the second capacitor and a first terminal of the first switch circuit,
a second end of the second capacitor is connected to ground,
a second terminal of the first switch circuit is connected to ground, and
the first switching circuit is configured to selectively cause connection of the second end of the first capacitor to ground.

US Pat. No. 11,114,988

DOHERTY AMPLIFIER CIRCUIT WITH INTEGRATED HARMONIC TERMINATION

Cree, Inc., Durham, NC (...


1. A Doherty amplifier operative to amplify an RF signal having a fundamental frequency, comprising:main and peak transistors arranged in parallel; and
a combined impedance inverter and harmonic termination circuit coupled between outputs of the main and peak transistors, and operative to present a a low impedance path to RF signal ground at a targeted harmonic of the fundamental frequency, without substantially interfering with the load modulation function of the impedance inverter at the fundamental frequency.

US Pat. No. 11,114,987

SWITCHABLE POWER AMPLIFICATION STRUCTURE

Qorvo US, Inc., Greensbo...


1. An apparatus comprising:a first power amplifier (PA) and a second PA;
a front switching structure coupled to a radio frequency (RF) input port, wherein:the front switching structure comprises a first front switch, a second front switch, a third front switch, a fourth front switch, a first front capacitor, a second front capacitor, a third front capacitor, and a front inductor;
the first front capacitor and the first front switch are coupled in series between the RF input port and an input terminal of the first PA, the second front capacitor and the second front switch are coupled in series between the RF input port and an input terminal of the second PA, the third front capacitor and the third front switch are coupled in series between the RF input port and ground, the fourth front switch is coupled between the RF input port and the input terminal of the first PA, and the front inductor is coupled between the RF input port and ground; and

a first end switching structure coupled to a first antenna port, wherein:the first PA and the second PA are parallel to each other, each of which is coupled between the front switching structure and the first end switching structure;
the front switching structure is configured to selectively couple the first PA and the second PA to the RF input port; and
the first end switching structure is configured to selectively couple the first PA and the second PA to the first antenna port.


US Pat. No. 11,114,986

CONSTANT LEVEL-SHIFT BUFFER AMPLIFIER CIRCUITS

Omni Design Technologies ...


1. A level shifting buffer amplifier, comprising:an input terminal and an output terminal
a first transistor;
a current source;
a variable resistance electrically coupled to the first transistor, wherein a resistance of the variable resistance is a function of a voltage at a control terminal; and
a second transistor electrically coupled to the first transistor, the current source providing negative feedback,
wherein the buffer amplifier provides a constant level shift between the input and the output terminals.

US Pat. No. 11,114,985

HIGH FREQUENCY AMPLIFIER

SUMITOMO ELECTRIC DEVICE ...


1. A high frequency amplifier comprising:an input terminal;
an output terminal;
a transistor configured to amplify an input high frequency signal applied to the input terminal;
a matching circuit for a fundamental of the input high frequency signal and a reflection circuit for a harmonic relative to the fundamental, the matching circuit and the reflection circuit being connected in series between the transistor and the output terminal;
an extraction circuit configured to extract a harmonic appearing at the output terminal;
a processing circuit configured to adjust a phase and intensity of the harmonic extracted by the extraction circuit; and
a multiplexing circuit configured to multiplex the harmonic processed by the processing circuit to the harmonic reflected by the reflection circuit and give the multiplexed harmonic to the transistor.

US Pat. No. 11,114,984

AUDIO DEVICE FOR REDUCING POP NOISE AND PROCESSING METHOD THEREOF

REALTEK SEMICONDUCTOR COR...


1. An audio device for reducing pop noise, adapted to compensate for a direct current (DC) offset value of an audio source signal and output the audio source signal to an audio playing device, the audio device comprising:a linear operation circuit for generating the DC offset value based on a linear equation, a temperature parameter, a slope parameter, and a constant, wherein the linear equation is:Y=M*X+C

wherein Y is the DC offset value, X is the temperature parameter, M is the slope parameter, and C is the constant;
an adder for processing an input signal and the DC offset value to generate a calibration signal;
a digital-to-analog circuit coupled to the adder, the digital-to-analog circuit being configured to convert the calibration signal in a digital form to the calibration signal in an analog form;
an amplification circuit coupled to the digital-to-analog circuit, the amplification circuit being configured to process the calibration signal in the analog form to output the audio source signal;
a temperature sensing circuit coupled to the linear operation circuit, the temperature sensing circuit generating the temperature parameter based on a temperature of the audio device and outputting the temperature parameter to the linear operation circuit;
a storage device coupled to the linear operation circuit, the storage device being configured to store the slope parameter and the constant and output the slope parameter and the constant to the linear operation circuit; and
a switch coupled to the amplification circuit, the switch being configured to control an output of the audio device, wherein when the switch is closed, the audio device outputs the audio source signal, and when the switch is opened, the audio device does not output the audio source signal.

US Pat. No. 11,114,983

AMPLIFIER AND IMAGE SENSOR DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...


1. An amplifier, comprising:a first capacitor connected between an input node and a floating node;
a second capacitor connected between the floating node and an output node;
an amplifying element connected between a power supply voltage and the output node, and configured to operate in response to a voltage level of the floating node;
a current bias source connected between the output node and a ground voltage;
a first reset switch connected between the floating node and an intermediate node, and configured to operate in response to a reset bias;
a second reset switch connected between the intermediate node and the output node, and configured to operate in response to the reset bias; and
a reset bias generator circuit configured to output the reset bias in response to a reset signal,
wherein the reset bias is one of a reset voltage of the intermediate node, the power supply voltage, and the ground voltage.

US Pat. No. 11,114,982

POWER AMPLIFIER CIRCUIT

MURATA MANUFACTURING CO. ...


1. A power amplifier circuit comprising:an amplifier transistor having a first terminal and a second terminal, wherein a power supply voltage that changes in accordance with an amplitude level of an input signal is supplied to the first terminal, the input signal and a bias current are supplied to the second terminal, and an amplified signal obtained by amplifying the input signal is output from the first terminal;
a bias circuit that outputs the bias current from an output terminal of the bias circuit in accordance with a reference current supplied to an input terminal of the bias circuit; and
a regulation circuit that generates a regulation current for regulating the bias current in accordance with a change in the power supply voltage,
wherein the regulation current is a current that increases with an increase in the power supply voltage and decreases with a decrease in the power supply voltage, and
wherein the regulation circuit extracts the regulation current from at least one of the reference current or the bias current.

US Pat. No. 11,114,981

DIFFERENTIAL AMPLIFIER

REALTEK SEMICONDUCTOR COR...


1. A differential amplifier, comprising:an input circuit configured to output input current to two output nodes according to voltage of a differential input signal and voltage of a bias node;
a detecting and controlling circuit configured to output compensative current to the two output nodes according to control bias voltage and the voltage of the bias node, wherein the voltage of the bias node and the compensative current correlate with the voltage of the differential input signal; and
an output circuit coupled to the two output nodes and configured to output a differential output signal according to a sum of the input current and the compensative current.

US Pat. No. 11,114,980

ENVELOPE TRACKING AMPLIFIER APPARATUS

Qorvo US, Inc., Greensbo...


1. An envelope tracking (ET) amplifier apparatus comprising:a plurality of first amplifier circuits comprising a plurality of first input stages and a plurality of first output stages, respectively, the plurality of first amplifier circuits configured to amplify a radio frequency (RF) signal based on at least one first ET voltage;
a plurality of second amplifier circuits comprising a plurality of second input stages and a plurality of second output stages, respectively, the plurality of second amplifier circuits configured to amplify the RF signal based on at least one second ET voltage; and
an ET integrated circuit (IC) (ETIC) comprising:a tracker circuit configured to generate a low-frequency current at a common port;
a plurality of amplifier ports coupled to the plurality of first amplifier circuits and the plurality of second amplifier circuits; and
a plurality of voltage circuits coupled between the common port and the plurality of amplifier ports, respectively, the plurality of voltage circuits configured to generate the at least one first ET voltage and the at least one second ET voltage based on a plurality of ET target voltages, respectively;

wherein a selected voltage circuit among the plurality of voltage circuits is configured to:generate a reference ET voltage based on a maximum ET target voltage among the plurality of ET target voltages; and
provide the reference ET voltage to the common port and a selected amplifier port coupled to the selected voltage circuit among the plurality of amplifier ports.


US Pat. No. 11,114,979

FREQUENCY DETECTOR

Silicon Integrated System...


1. A frequency detector, used for detecting a frequency difference of a signal to be tested from a first time point to a second time point, the frequency detector comprising:an alternating current coupled capacitor configured to receive the signal to be tested;
a rectifying circuit electrically connected to the alternating current coupled capacitor;
an analog-to-digital converter electrically connected to the rectifying circuit;
a control unit electrically connected to the analog-to-digital converter; and
a counter electrically connected to the rectifying circuit and the control unit,
wherein the control unit is configured to calculate the frequency difference of the signal to be tested from the first time point to the second time point according to outputs of the analog-to-digital converter and outputs of the counter.

US Pat. No. 11,114,978

VARIABLE REACTANCE APPARATUS FOR DYNAMIC GAIN SWITCHING OF TUNABLE OSCILLATOR

NXP B.V., San Jose, CA (...


1. A variable reactance apparatus, the apparatus comprising:a plurality of unit variable reactance structures connected in parallel, wherein each of the plurality of unit variable reactance structures comprises a respective one of a plurality of control input nodes; and
a control circuit operably coupled to the plurality of unit variable reactance structures and configured to selectively connect, based on one or more selection signals, each of the plurality of control input nodes to a respective signal from among a plurality of signals, wherein the plurality of signals comprises a first tuning signal and a second tuning signal,
wherein:the control circuit comprises a plurality of multiplexers; and
each of the plurality of multiplexers comprises one or more multiplexer select inputs connected to respective signals from among the one or more selection signals.


US Pat. No. 11,114,977

PHOTOVOLTAIC ARRAY FAULT DIAGNOSIS METHOD BASED ON RANDOM FOREST ALGORITHM

Jiangnan University, Wux...


1. A method for photovoltaic array fault diagnosis based on a random forest algorithm, comprising:determining typical operating states of a photovoltaic array during operation, the photovoltaic array comprising n branches, each branch comprising m photovoltaic modules, wherein m and n are positive integers, m?4 and n?4;
acquiring circuit parameter groups corresponding to each branch and a trunk in the photovoltaic array, respectively, when the photovoltaic array is in each typical operating state, each circuit parameter group comprising k circuit parameters, wherein k is a positive integer;
constructing a p-dimensional fault feature vector according to the acquired n+1 circuit parameter groups, where p=k*(n+1);
constructing a data sample set of the photovoltaic array according to the fault feature vector, and dividing the data sample set into a training sample set and a test sample set;
constructing a photovoltaic array fault diagnosis model based on the random forest algorithm by using the training sample set, and testing the photovoltaic array fault diagnosis model by using the test sample set, the photovoltaic array fault diagnosis model comprising s decision trees, wherein s?2, and s is a positive integer;
diagnosing a photovoltaic array to be diagnosed by using the tested photovoltaic array fault diagnosis model to obtain voting results of the s decision trees for each typical operating state; and
obtaining a fault diagnosis result of the photovoltaic array to be diagnosed according to the voting results for each typical operating state, the fault diagnosis result being used to indicate an operating state of each branch in the photovoltaic array;
wherein when n=2 and m=3, the typical operating states of the photovoltaic array comprise five categories, and a total of twelve subcategories, which are as follows:a first category is a normal operating state, and the first category comprises one subcategory, which is a state when each photovoltaic module in each branch of the photovoltaic array is in normal operation;
a second category is a short-circuit fault state, and the second category comprises three subcategories, which are a state when one photovoltaic module in one branch of the photovoltaic array is short-circuited, a state when two photovoltaic modules in one branch of the photovoltaic array are short-circuited, and a state when one photovoltaic module in each of two branches of the photovoltaic array is short-circuited, respectively;
a third category is an open-circuit fault state, and the third category comprises one subcategory, which is a state when one branch of the photovoltaic array is open-circuited;
a fourth category is a shadow fault state, and the fourth category comprises three subcategories, which are a state when one photovoltaic module in one branch of the photovoltaic array has a shadow, a state when one photovoltaic module in each of two branches of the photovoltaic array has a shadow, a state when one photovoltaic module in one branch of the photovoltaic array has a shadow and two photovoltaic modules in the other branch have shadows, and a state when two photovoltaic modules in each of two branches of the photovoltaic array have shadows, respectively; and
a fifth category is a hybrid fault state, and the fifth category comprises four subcategories, which are a state when one branch of the photovoltaic array is open-circuited and one photovoltaic module in the other branch has a shadow, a state when one photovoltaic module in one branch of the photovoltaic array is short-circuited and one photovoltaic module in the other branch has a shadow, a state when one photovoltaic module is short-circuited and one photovoltaic module has a shadow in each of two branches of the photovoltaic array, and a state when one photovoltaic module is short-circuited and two photovoltaic modules have shadows in each of two branches of the photovoltaic array, respectively.


US Pat. No. 11,114,976

MODULAR REMOVABLE BUILDING INTEGRATED THERMAL ELECTRIC ROOFING SYSTEM


1. A modular, removable roofing installation system for optimally capturing solar thermal energy, the modular, removable roofing installation system comprising:a plurality of removable solar panel modules, each solar panel module comprising a plurality of slate modules mounted on a plurality of metal battens, a plurality of inverters for converting DC electricity fed from the plurality of slate, modules to AC electricity, a thermal tubing containing liquid mounted beneath the plurality of slate modules on the plurality of metal battens, wherein the plurality of metal battens are mounted on a plurality of horizontal battens that are mounted onto a plurality of vertical battens, wherein each solar panel module comprises a roof-attaching latch mounted to a backing of the plurality of vertical battens, wherein the roof-attaching latch couples to a corresponding roof surface latch mounted to a roof to removably attach each solar panel module to the roof;
a plurality of metal fasteners, each metal fastener coupled to two adjacent removable solar panel modules of the plurality of removable solar panel modules;
a pump and thermal control unit comprising a circulation pump that is operatively connected to the thermal tubing for circulating the liquid through the thermal tubing;
a heat exchanger that is operatively connected to the thermal tubing for extracting the thermal energy, the heat exchanger being housed in a storage tank;
a heat pump connected to the heat exchanger for maintaining the temperature of the liquid in the storage tank to a certain threshold temperature;
whereby the plurality of slate modules and the thermal tubing operate simultaneously to generate electricity and domestic hot water respectively; and
wherein the system may be removed and re-installed on a second roof by disconnecting the pump and thermal control unit, disconnecting the thermal tubing from the heat exchanger and the circulation pump, and removing the plurality of removable solar panel modules.

US Pat. No. 11,114,975

SOLAR TRACKING SYSTEM

Varun Sachar, New Delhi ...


1. A dual axis solar tracker system (100), the system (100) comprising:a frame (102), the frame (102) having a frame side one (104),a frame side two (106), the frame side two (106) is parallel to the frame side one (104),
a first cross beam (124), the first crossbeam (124) is connected between the frame side two (106) and the frame side one (104) perpendicularly, and
a second cross beam (142), the second cross beam (142) is connected between the frame side two (106) and the frame side one (104), and is parallel to the first beam (124), and

an at least one frame side one bearing (108), the at least one frame side one bearing (108) is connected to the frame side one (104);
an at least one frame side two bearing (110), the at least one frame side two bearing (110) is connected to the frame side two (106) exactly opposite to the at least one frame side one bearing (108);
an at least one solar panel (112), the at least one solar panel (112) is coupled to the at least one frame side one bearing (108) on the frame side one (104) and further coupled to the at least one frame side two bearing (110) on the frame side two (106);
an upper beam (114), the upper beam (114) is below to the frame side one (102);
an at least one selectively flexible bracket (116), the at least one selectively flexible bracket (116) is connected between the upper beam (114) and the at least one frame side one bearing (108);
an at least one first supporting pillar (118);
an at least one second supporting pillar (140);
a lower beam (120), the lower beam (120) forms a perpendicular sliding pair with the at least one first supporting pillar (118) and the at least one second supporting (140);
an at least one first supporting pillar bearing (122), the at least one first supporting pillar bearing (122) is connected between the at least one first supporting pillar (118) and the first cross beam (124);
an at least one second supporting pillar bearing (144), the at least one second supporting pillar bearing (144) is connected between the at least one second supporting pillar (140) and the second cross beam (142);
an at least one first strut (126), the at least one first strut (126) is connected between the first cross beam (124) and the lower beam (120) through an at least one first spherical joint (128) and an at least one second spherical joint (130);
an at least one second strut (146), the at least one second strut (146) is connected between the second cross beam (142) and the lower beam (120) through an at least one third spherical joint (148) and an at least one fourth spherical joint (150);
an upper beam actuator (132), the upper beam actuator (132) is connected to the upper beam (114) at one end and further connected to the first cross beam (124) at the other end; and
a lower beam actuator (134), the lower beam actuator (134) is connected to the lower beam (120) at one end and connected to the at least one first supporting pillar (118) at the other end;
wherein, translation motion of the upper beam (114) is along the length of frame side one (104),
wherein, the plane of rotation of the at least one frame side one bearing (108) and the at least one frame side two bearing (110) is parallel to translation motion of the upper beam (114),
wherein, translation motion of the lower beam (120) is along the length of frame side two (106),
wherein, the plane of rotation of the first supporting pillar bearing (122) and the second supporting pillar bearing (144) is perpendicular to translation motion of the lower beam (120),
wherein, the at least one first spherical joint (128) connects one end of the at least one first strut (126) and the first cross beam (124) and the at least one second spherical joint (130) connects another opposite end of the at least one first strut (126) and the lower beam (120),
wherein, the at least one third spherical joint (148) connects one end of the at least one second strut (146) and the second cross beam (142) and the at least one fourth spherical joint (150) connects another opposite end of the at least one second strut (126) and the lower beam (120),
wherein, the system (100) is a four-bar linkage mechanism, such that the at least one first supporting pillar (118) and the at least one second supporting pillar (140) together act as the fixed link, the frame (102) acts as the rotating link and the lower beam (120) acts as the translating link and the at least one first strut (126) and the at least one second strut (126) together act as the fourth link connecting the frame (102) and the lower beam (120) and thus in the designed configuration, the translation of the lower beam (120) causes rotation of the frame (102).

US Pat. No. 11,114,974

SURFACE MOUNT ASSEMBLIES FOR A SOLAR PANEL SYSTEM

Sunrun South LLC, San Lu...


1. A surface mount assembly for mounting to a solar panel frame to an installation surface, comprising:a base configured with at least one aperture;
a track;
a plate configured with a raised portion, wherein the raised portion includes at least one aperture extending away from a surface of the raised portion; and
a fastener assembly configured for coupling the base to the track and comprised of a threaded track fastener, a threaded base fastener, and a spacer with one aperture having a first threaded end and a second threaded end, wherein the threaded track fastener extends from the track to threadably engage complementary threads of the first threaded end, and wherein the threaded base fastener extends through one base aperture and one plate aperture to threadably engage complementary threads of the second threaded end.

US Pat. No. 11,114,973

MOTOR CONTROL DEVICE, METHOD FOR CONTROLLING MOTOR CONTROL DEVICE, CONTROL PROGRAM, AND STORAGE MEDIUM

OMRON Corporation, Kyoto...


1. A motor control device, comprising:a plurality of input terminals to which an input-side external device is connected;
a plurality of function input terminals which are included in a main control section of the motor control device and which correspond to a plurality of functions of the motor control device, respectively; and
a terminal allocating section for setting, in accordance with selection by a user, which of the plurality of input terminals is to be allocated to each of the plurality of function input terminals,
the motor control device further comprising a timing control section which, with respect to each of at least one of the plurality of input terminals, in accordance with selection by the user, causes timing of supplying a first function input terminal with a signal having been supplied to said at least one input terminal to be different from timing of supplying a second function input terminal with the signal, the first function input terminal and the second function input terminal being included in the plurality of function input terminals and being different from each other.

US Pat. No. 11,114,972

SYSTEM, METHOD AND DEVICE FOR REFLECTED WAVE CANCELLATION

The Florida State Univers...


1. A method of mitigating overvoltage at terminals of a load caused by a reflected wave, the method comprising:receiving a signal from an inverter, wherein said inverter provides a voltage waveform to a load through a cable having a length; and
injecting two voltage pulses into the cable in each switching cycle, said one injected two voltage pulses corresponding to a leading edge of the inverter voltage waveform and another of the two injected voltage pulses corresponding to a trailing edge of the inverter voltage waveform, wherein the injected voltage pulse corresponding to the leading edge of the inverter voltage waveform has a first polarity, first width and first amplitude, wherein the signal results in the voltage pulse corresponding to the leading edge of the inverter voltage waveform breaking the leading edge of the inverter voltage waveform into a first two-step voltages, wherein a reflected voltage at the terminals of the load caused by a first step voltage of the first two-step voltages is substantially canceled by a reflected voltage caused by a second step voltage of the first two-step voltages, and
wherein the injected voltage pulse corresponding to the trailing edge of the inverter voltage waveform has a second polarity that is opposite the first polarity, a second width and a second amplitude, wherein the signal results in the voltage pulse corresponding to the trailing edge of the inverter voltage waveform breaking the trailing edge of the inverter voltage waveform into a second two-step voltages, wherein a reflected voltage at the terminals of the load caused by a first step voltage of the second two-step voltages is substantially canceled by a reflected voltage caused by a second step voltage of the second two-step voltages.

US Pat. No. 11,114,971

METHOD FOR CONTROLLING A DRIVE MOTOR OF AN ACTUATOR AS WELL AS DRIVE MOTOR OF AN ACTUATOR


1. A method for controlling a drive motor of an actuator for actuating a valve, the method comprising:supplying a power to the drive motor by pulse width modulated voltage controlled by a control frequency to adjust the actuator coupled to a valve into a desired position;
changing the control frequency such that a mixture of frequencies is produced;
repeating a fixed frequency sequence of the mixture of frequencies;
providing frequencies of the fixed frequency sequence for an integer number of periods, wherein the integer number of periods is in a range of 1 to 0.2×control frequency.

US Pat. No. 11,114,970

MOTOR DRIVER, HEAT PUMP SYSTEM AND REFRIGERATION AND AIR CONDITIONING EQUIPMENT USING MOTOR DRIVER

Mitsubishi Electric Corpo...


3. A motor driving device comprising:an inverter used for driving a motor and configured to apply an alternating-current voltage to the motor, wherein
the inverter drives, during start operation, a switching element of the inverter with a first PWM signal that is PWM modulated with a carrier frequency that is a first integer multiple of a frequency of the alternating-current voltage, and thereafter drives the switching element with a second PWM signal that is PWM modulated with a carrier frequency that is a second integer multiple of the frequency of the alternating-current voltage, the second integer being smaller than the first integer, and
voltage output by the inverter is controlled so that a peak value of current flowing through the motor is constant while rotation speed of the motor changes.

US Pat. No. 11,114,969

POWER CONVERTER, MOTOR DRIVING UNIT, AND ELECTRIC POWER STEERING DEVICE

NIDEC CORPORATION, Kyoto...


1. A power converter to convert power from a power supply into power supplied to a motor with n-phase windings where n is an integer of 2 or more, the power converter comprising:a first inverter connected to a first end of each of the n-phase windings of the motor and including n legs each including a low-side switching element and a high-side switching element;
a second inverter connected to a second end of each of the n-phase windings and including n legs each including a low-side switching element and a high-side switching element; and
a switching circuit including a first switching element to switch connection and disconnection between the first inverter and a ground and a second switching element to switch connection and disconnection between the first inverter and the power supply, the first switching element and the second switching element being structured to cut off a bidirectional current; wherein
in a state in which, in the first inverter, potentials at a first node in a high side, to which the n legs are connected, and a second node in a low side, to which the n legs are connected, are equal to each other, and potentials at first ends of two-phase windings of the n-phase windings are equal to each other, the two-phase windings are energized using two legs connected to the second ends of the two-phase windings of the n legs of the second inverter while performing switching operations on the first and second switching elements of the switching circuit at a predetermined duty ratio.

US Pat. No. 11,114,968

ROTATING ELECTRIC MACHINE DEVICE AND ROTATING ELECTRIC MACHINE DEVICE CONTROL METHOD

Mitsubishi Electric Corpo...


1. A rotating electric machine apparatus, comprising:a rotating electric machine including a rotor and a stator provided concentrically about a rotation shaft as an axis, one of the rotor and the stator being provided outside another thereof, the rotor being rotatable about the rotating shaft as the axis, the stator being fixed, any one of the rotor and the stator including an armature, another thereof including a field;
an inverter including an inverter circuit to drive the rotating electric machine, and an inverter controller to control the inverter circuit;
a detector including a resonance circuitry, which is mounted to an object to be measured of the rotating electric machine and has a resonance characteristic that changes depending on a change in a physical quantity of the object to be measured, and a first antenna to transmit the resonance characteristic; and
a detection processor to receive the resonance characteristic dependent on the change in the physical quantity in a form of a response radio wave from the first antenna as a response to a transmission radio wave transmitted from a second antenna, calculate a detection result corresponding to a current value of the physical quantity from the resonance characteristic, and compare whether the detection result is within a permissible range set in advance, to thereby detect whether the object to be measured is in an abnormal state,
wherein the inverter controller controls output of the inverter circuit so that the detection result falls within the permissible range when the inverter controller receives from the detection processor an abnormal state signal indicating that the abnormal state is detected.

US Pat. No. 11,114,967

CONTROLLER OF ROTARY AXIS

FANUC CORPORATION, Yaman...


1. A controller of a rotary axis that decelerates the rotary axis to a predetermined speed at a predetermined position, the controller comprising:a total movement command calculating unit that calculates a remaining movement amount S2 by subtracting a movement command M1 for each control cycle in every control cycle from a total movement amount S1 from a current position until the predetermined position, in a case in which a positioning request to decelerate the rotary axis to the predetermined speed at the predetermined position is issued;
a movement command calculating unit that calculates the movement command M1 for each control cycle from the remaining movement amount S2;
a storage unit that stores in advance data of a braking distance for each rotation number of the rotary axis, the data of the braking distance being based on a maximum torque characteristic with respect to a rotation number of a motor for driving the rotary axis, refers to the data of the braking distance, and provides a current braking distance S3 corresponding to a current rotation number of the rotary axis;
a deceleration command calculating unit that calculates a speed command V2 of the rotary axis on a basis of the remaining movement amount S2 and the current braking distance S3; and
a speed control unit that causes a speed of the motor to follow the speed command V2,
wherein the deceleration command calculating unit
calculates the speed command V2 to maintain the current rotation number of the rotary axis in a case in which a difference S4 between the remaining movement amount S2 and the current braking distance S3 is equal to or greater than a predetermined value, and
calculates the speed command V2 to start deceleration of the rotary axis in a case in which the difference S4 is less than the predetermined value.

US Pat. No. 11,114,966

DEVICE AND METHOD FOR DETERMINING ROTATION OF AN INDUCTION MACHINE

Danfoss Editron Oy, Lapp...


1. A device, wherein the device comprises a processing system implemented with one or more processor circuits configured to:control stator voltages of an induction machine to constitute a voltage space-vector having a fixed direction with respect to a stator of the induction machine,
control a length of the voltage space-vector to regulate stator currents of the induction machine to fulfill a condition that a current space-vector constituted by the stator currents has a pre-determined length, and
estimate at least one of the following based on a waveform of a q-component of the current space-vector: rotation speed of a rotor of the induction machine, a direction of rotation of the rotor,

wherein a d-component of the current space-vector is parallel with the voltage space-vector and the q-component of the current space-vector is perpendicular to the voltage space-vector.

US Pat. No. 11,114,965

MOTOR CONTROL MODULE, MOTOR CONTROL DEVICE, MOTOR CONTROL SYSTEM, AND MOTOR CONTROL METHOD

LG ELECTRONICS INC., Seo...


1. A motor control module for controlling a variable magnetic motor, the motor control module comprising:a current control unit configured to generate a current command to control a driving current applied to the motor according to an operating state of the motor; and
a signal generation unit configured to generate a control signal to be sent to an inverter to apply a current to the motor according to the current command,
wherein the current control unit is configured to generate the current command to apply an increasing or decreasing current to the motor for increasing or decreasing a magnetic flux in the motor at a predetermined application time point and is configured to control a magnetic force in the motor, and
wherein the current control unit is configured to:estimate a speed of the motor and the magnetic flux in the motor;
determine whether to increase or decrease the magnetic force in the motor based on the estimation of the speed and magnetic flux of the motor; and
generate the current command according to a result of the determination of whether to increase or decrease the magnetic force in the motor.


US Pat. No. 11,114,964

METHOD FOR DETERMINING A DIRECT-AXIS INDUCTANCE AND A QUADRATURE-AXIS INDUCTANCE OF AN ELECTRIC MACHINE, CORRESPONDING COMPUTER PROGRAM AND DEVICE

VALEO SYSTEMES DE CONTROL...


1. A method for determining a direct inductance and a quadrature inductance of an electrical machine, the method comprising:at least one testing step comprising:
controlling the electrical machine so that a stator of the electrical machine generates a magnetic field comprising:a first magnetic field rotating at a first rotation frequency, so as to rotationally drive a rotor of the electrical machine, and
a second magnetic field, called test magnetic field, that varies periodically at a second frequency, called test frequency,

measuring at least one portion of the phase currents flowing through the stator windings of the electrical machine during controlling of the electrical machine,
determining an amplitude spectrum of a given electrical quantity determined on the basis of at least one portion of the phase currents,
searching in the amplitude spectrum for at least, one peak present at a frequency that is dependent on the test frequency,
determining an amplitude of each peak found,
determining the direct inductance and the quadrature inductance from the amplitudes of two peaks found in the one or more testing steps.