US Pat. No. 10,511,370

METHOD FOR BEAM MANAGEMENT FOR WIRELESS COMMUNICATION SYSTEM WITH BEAMFORMING

MEDIATEK INC., Hsin-Chu ...

1. A method comprising:receiving reference signals over a plurality of TX beams from a base station by a user equipment (UE) in a beamforming wireless communication network, wherein each TX beam has a TX beam identifier;
performing measurements over the plurality of TX beams and determining a corresponding beam metric value;
grouping the plurality of TX beams into multiple beam groups, wherein the grouping is determined based on an association between each TX beam and a number of UE receive panels or UE antenna subarrays; and
reporting the beam value metrics of the plurality of TX beams in an order associated with each beam group, wherein each beam group is implicitly indicated by a number of TX beams per beam group, or explicitly indicated by a beam group identifier.

US Pat. No. 10,511,369

EXTENDING ASSOCIATION BEAMFORMING TRAINING

Intel Corporation, Santa...

1. An apparatus of a station comprising: memory; and processing circuitry coupled to the memory, the processing circuitry configured to:decode an enhanced directional multi-gigabit (EDMG) beacon comprising a multiplier field and a length field of an association beamforming training (A-BFT) interval;
determine a count of sector sweep (SSW) slots as equal to (a value of the multiplier field plus one) times a value of the length field of the A-BFT interval, wherein the count of SSW slots is equal to a count of original SSW slots plus a count of additional SSW slots, wherein the count of original SSW slots is equal to the value of the length field of the A-BFT interval and the count of the additional SSW slots is equal to (a value of the multiplier field)×(a value of the length field of the A-BFT interval);
select a SSW slot of the SSW slots of the count of SSW slots;
encode a SSW frame; and
configure the station to transmit the SSW frame during the selected SSW slot of the count of SSW slots.

US Pat. No. 10,511,368

METHOD OF TRANSMITTING AND RECEIVING SIGNAL IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR

LG Electronics Inc., Seo...

1. A method of transmitting and receiving a signal by a station (STA) in a wireless communication system, the method comprising:receiving a physical protocol data unit (PPDU); and
performing beamforming training based on a training (TRN) field of the PPDU,
wherein the PPDU further includes a legacy header (L-header) field, an enhanced directional multi-gigabit (EDMG) header field and a data field,
wherein a first length field included in the L-header field includes information on a length of the TRN field,
wherein the length of the TRN field is obtained from the end of the PPDU, and
wherein a second length field included in the L-header field includes information on a length of the data field,
wherein the length of the data field is obtained by subtracting the length of the TRN field from a length of the PPDU after the L-header field,
wherein the EDMG header field includes a third length field, and
wherein when the length of the TRN field is longer than a predetermined limit on the length of the TRN field, the first length field includes information that reflects the predetermined limit on the length of the TRN field, and the third length field includes information that reflects a remaining length of the TRN field.

US Pat. No. 10,511,367

CHANNEL STATE INFORMATION SENDING METHOD, CHANNEL STATE INFORMATION RECEIVING METHOD, AND DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A channel state information CSI receiving method, comprising:receiving, by a network device from a terminal device, a signal comprising channel state information (CSI), the CSI comprising a rank indicator (RI), indication information, and a second precoding matrix indicator PMI2;
obtaining, by the network device, the RI and the indication information based on the signal comprising the CSI;
obtaining, by the network device, the PMI2 based on the RI and the indication information; and
determining, by the network device, a precoding matrix W based on the rank indicator RI and the second precoding matrix indicator PMI2, wherein W comprises W=W1×W2, W is a matrix with Nt rows and L columns, W1 is a matrix with Nt rows and 2I columns, W2 is a matrix with 2I rows and L columns, Nt is a quantity of antenna ports, L is a rank indicated by the RI, Nt is greater than or equal to L, I is an integer greater than or equal to 1, an element at a location in an ith row and an lth column in W2 is Yi,l, i is an integer greater than or equal to zero and less than or equal to 2I?1, l is an integer greater than or equal to zero and less than or equal to L?1, Yi,l comprises Yi,l=Xi,l1×Xi,l2×Xi,l3, and Xi,l3 is a complex number with modulus 1; and
the indication information indicates that W2 comprises M Xi,l1 whose values are non-zero, the PMI2 indicates a parameter of W2, the parameter of W2 indicated by the PMI2 comprises all Xi,l1 in W2 and Xi,l2 and Xi,l3, which correspond to the M Xi,l1 whose values are non-zero in W2, and does not comprise Xi,l2 and Xi,l3 which correspond to Xi,l1 other than the M Xi,l1 whose values are non-zero in W2.

US Pat. No. 10,511,366

SIGNALING TRANSMISSION METHOD AND DEVICE FOR MULTIPLE-INPUT MULTIPLE-OUTPUT SYSTEM

ZTE CORPORATION, Shenzhe...

1. A signaling transmission method for a Multiple-Input Multiple-Output, MIMO, system, applied to a receiving network side, the method comprising:forming Channel-Related Information, CRI, about a combined channel according to CRI between all receiving antenna ports in a receiving network and a sending antenna port in a sending network; and
sending the CRI about the combined channel to the sending network;
wherein, the CRI comprises one or more of the following: channel information, Channel State Information, CSI, and a CSI Reference Signal, CSI-RS;
wherein forming CRI about a combined channel according to CRI between receiving antenna ports in a receiving network and a sending antenna port in a sending network comprises:
receiving, by the receiving antenna ports, the CSI-RS sent by the sending antenna port;
determining a receiving antenna port set corresponding to the CRI about the combined channel and a second-class node set corresponding to the receiving antenna port set according to the received CSI-RS;
determining CRI between the second-class node set and the sending antenna port as CRI about the second-class node set; and
forming the CRI about the combined channel according to the CRI about the second-class node set and the receiving antenna ports;
wherein the second-class node set comprises user equipment.

US Pat. No. 10,511,363

PRECODING FOR ADVANCED WIRELESS COMMUNICATION SYSTEMS

Samsung Electronics Co., ...

1. A base station (BS) comprising:a transceiver comprising an antenna array, the transceiver configured to measure a sound reference signal (SRS) from a user equipment (UE), using at least one portion of the antenna array; and
at least one processor configured to:
select at least one uplink (UL) beam vector, based on the SRS measurement, from a UL beam-codebook comprising a set of beam weight vectors;
determine at least one downlink (DL) beam vector corresponding to each of the selected at least one UL beam vector;
transmit a beamformed channel state information (CSI)-reference signal (RS) by applying the at least one DL beam vector to the antenna array;
receive a CSI feedback including a Precoding Matrix Index (PMI) from the UE, wherein the PMI is determined based on the beamformed CSI-RS; and
construct a precoding channel matrix for the UE based on the PMI and the at least one DL beam vector.

US Pat. No. 10,511,361

METHOD FOR DETERMINING A PRECODING MATRIX AND PRECODING MODULE

Intel Corporation, Santa...

1. A method for determining a precoding matrix for a multi-input multi-output (MIMO) transmitter based on a weighted minimum mean square error (MMSE) algorithm, the method comprising:identically transforming a first matrix expression into a second matrix expression using a processor circuit, wherein the first matrix expression comprises a matrix inversion operation of a quadratic matrix having a rank equal to a number of antennas of the MIMO transmitter and the second matrix expression comprises a matrix inversion operation of a quadratic matrix having a rank equal to a number of receivers scheduled for the MIMO transmitter, wherein the number of antennas of the MIMO transmitter is greater than the number of receivers scheduled for the MIMO transmitter; and
precoding a data stream for transmission using a precoding matrix according to the second matrix expression, wherein the precoded data stream comprises MIMO transmitter signals.

US Pat. No. 10,511,359

TRANSMISSION METHOD WITH DOUBLE DIRECTIVITY

1. Transmission method with double directivity comprising the following steps:a. the data stream is split into Nu sub-streams in (101);
b. the data bits associated to each of the Nu sub-streams are mapped by a modulator (102) into a symbol sequence of a given constellation (the constellation can be a M-QAM, M-PSK or Voronoi constellation) characterized by the ordered set ={S0, S1, . . . , SM?1}, where M is the number of constellation symbols, following the rule
(?n(??1),?n(??2), . . . ,?n(1),?n(0))sn?,
 with (?n(??1),?n(??2), . . . ,?n(1),?n(0)) denoting the binary representation of n with ?=log2(M) bits;
c. the polar mapper (103) decomposes the constellations symbols in Nm polar components, that are the result of the decomposition of signal sn into M components given by

 with (???1,i ???2,i . . . ?1,i ?0,i) denoting the binary representation of i, bn(m)=(?1)?n(m) denoting the polar representation of the bit ?n(m), bneq(i)=?m=0??1(bn(m))?m,i denoting the ith polar component of sn and Nm is the number of non-zero gi coefficients of the referred decomposition equation;
d. each of the Nm polar components is modulated as a BPSK signal in (104), whose output is a time continuous BPSK signal, being each of these Nm BPSK signal a serial representation of an OQPSK signal or a GMSK signal;
e. each of Nm resulting signals Is submitted to a phase shifter (105) and it is amplified by a nonlinear amplifier (106);
f. the Nm signals associated to each sub-stream are transmitted by an arrangement (108) of Nm×Nb antennas, arranged in Nm sets of Nb antenna elements or Nb sets of Nm antenna elements;
g. each arrangement (108) is composed by one or more sets of Nm antennas (109);
h. each arrangement (108) is composed by one or more sets of Nb antennas (110), to allow horizontal beams.

US Pat. No. 10,511,358

BEAMFORMING FOR A MULTI-USER MIMO GROUP

ARRIS Enterprises LLC, S...

1. A transmitting device, comprising an interface circuit configured to communicate, via connections, with receiving devices, wherein the interface circuit is configured to:provide, to one or more output nodes of the transmitting device, sounding packets to the receiving devices, wherein the receiving devices comprise a multi-user multiple-input multiple-output (MIMO) group;
receive, from one or more input nodes of the transmitting device, responses to the sounding packets from the receiving devices with beamforming information for the receiving devices;
dynamically select a subset of the receiving devices in the multi-user MIMO group by calculating beam-pattern settings for a set of antennas so that, when communicating with the subset of the receiving devices in the multi-user MIMO group, receiving devices in the subset are located on beams within beam patterns formed by the set of antennas while a remainder of the receiving devices in the multi-user MIMO group are located at exclusion zones in the beam patterns, wherein a beam pattern for a given receiving device provides a beam at a location of the given receiving device and provides exclusion zones at locations of the other receiving devices, and wherein the remainder of the receiving devices comprises at least a receiving device that is other than an access point; and
transmit, to the one or more output nodes, data to the subset of the receiving devices in the multi-user MIMO group based on the calculated beam-pattern settings, wherein the subset of the receiving devices comprises multiple receiving devices, wherein the data is communicated using a communication protocol that is different from a cellular-telephone communication protocol.

US Pat. No. 10,511,357

DETECTION SCHEME UTILIZING TRANSMITTER-SUPPLIED NON-LINEARITY DATA IN THE PRESENCE OF TRANSMITTER NON-LINEARITY

1. A system, comprising:a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
in response to activation of a non-linear device of a device operatively connected to a wireless transmitter, acquiring signal data pertaining to a characterization of a non-linear power response of the non-linear device; and
in response to establishing a wireless communication between the wireless transmitter and a receiving device, forwarding the signal data pertaining to the characterization of the non-linear response of the non-linear device to the receiving device, wherein the wireless transmitter comprises a wireless antenna element operative to communicate using wireless signals.

US Pat. No. 10,511,355

OPTIMIZED MULTI-BEAM ANTENNA ARRAY NETWORK WITH AN EXTENDED RADIO FREQUENCY RANGE

MOVANDI CORPORATION, New...

1. A system, comprising:a radio frequency (RF) transmitter device in an RF device network, wherein the RF transmitter device is configured to:
select one or more reflector devices from a plurality of reflector devices along a non-line-of-sight (NLOS) radio path based on a defined criteria; and
control the selected one or more reflector devices based on one or more conditions for transmission and reception of a plurality of beams of RF signals by the selected one or more reflector devices in the RF device network;
an RF receiver device configured to communicate with the selected one or more reflector devices in the RF device network;
a passive reflector device in the selected one or more reflector devices; and
an active reflector device in the selected one or more reflector devices,
wherein the active reflector device comprises at least two antenna arrays,
wherein the two antenna arrays comprise a first antenna array and a second antenna array,
wherein the first antenna array is configured to:
transmit a first set of beams of RF signals of the plurality of beams of RF signals to at least the RF transmitter device and the RF receiver device; and
transmit the first set of beams of RF signals of the plurality of beams of RF signals to the passive reflector device, and
wherein the second antenna array is configured to:
receive a second set of beams of RF signals of the plurality of beams of RF signals from at least the RF transmitter device and the RF receiver device; and
receive the second set of beams of RF signals of the plurality of beams of RF signals from the passive reflector device.

US Pat. No. 10,511,352

CQI REPORTING FOR MIMO TRANSMISSION IN A WIRELESS COMMUNICATION SYSTEM

QUALCOMM Incorporated, S...

1. A method for wireless communication, comprising:determining precoding control indicator (PCI) information and channel quality information at a user equipment (UE), wherein the channel quality information comprises a channel quality indicator (CQI) index for each of at least one transport block to be transmitted to the UE, wherein the CQI index for each transport block is selected based on an estimated Signal to Interference Noise Ratio (SINR) of the transport block, wherein the SINR for each transport block is estimated based on a transmit power per channelization code assigned to the transport block, the transmit power per channelization code to be used for a downlink data channel for carrying the at least one transport block;
jointly encoding the PCI information and the channel quality information to obtain coded data; and
sending the coded data from the UE to a base station.

US Pat. No. 10,511,350

ANTENNA DEVICE AND ELECTRONIC DEVICE

MURATA MANUFACTURING CO.,...

1. An antenna device comprising:a first coupling conductor that is connected to a power supply circuit;
a second coupling conductor that is at least magnetically coupled to the first coupling conductor;
a first capacitor that is connected in series to the second coupling conductor;
a second capacitor; and
a conductive member that includes an inductance component and that is connected in parallel to the second capacitor when viewed from a series circuit including the second coupling conductor and the first capacitor; wherein
a portion of or an entire closed loop including the second capacitor and the conductive member defines a magnetic-field radiating element; and
a capacitance of the first capacitor is smaller than a capacitance of the second capacitor.

US Pat. No. 10,511,349

CONNECTOR AND DEVICE FOR WIRELESS TRANSMISSION OF DATA AND POWER

KONINKLIJKE PHILIPS N.V.,...

1. A connector for wireless transmission of data and power between separate devices comprising such a connector of a system, in particular of a patient monitoring system, said separate devices comprising such a connector, said connector comprising:a data transmission unit arranged for transmitting data to and/or receiving data from another device of the system having a counterpart connector,
a magnetic coupling unit for transmitting power to and/or receiving power from another device of the system having a counterpart connector by use of inductive coupling,
a detection unit for detecting the strength of magnetic coupling between the magnetic coupling unit and a magnetic coupling unit of a counterpart connector, and
a control unit for using a near-field mode by switching the data transmission unit into a low-power mode and enabling the magnetic coupling unit to transmit power to and/or receive power from another device, if the detected magnetic coupling is above a first threshold and/or its increase is above a second threshold, and for using a far-field mode by switching the data transmission unit into a high-power mode and disabling the magnetic coupling unit, if the detected magnetic coupling is below a third threshold and/or its decrease is above a fourth threshold.

US Pat. No. 10,511,348

ELECTRONIC DEVICE AND METHOD FOR SHORT RANGE WIRELESS COMMUNICATION IN THE ELECTRONIC DEVICE

Samsung Electronics Co., ...

1. An electronic device comprising:a battery;
a first antenna;
a second antenna;
a short range wireless communication circuit; and
a controller,
wherein the controller is configured to control to:
receive, through the first antenna, wireless power for wireless charging of the battery from an external electronic device,
determine whether an event related to a cover is generated,
based on determining that the event related to the cover is generated, control a strength of the wireless power for the wireless charging of the battery, and
transmit, through the second antenna, information on the generated event to the cover for displaying the information on the generated event on the cover by using the short range wireless communication circuit connected with the cover, while receiving, through the first antenna, the wireless power of the controlled strength for the wireless charging of the battery.

US Pat. No. 10,511,345

DOWNSTREAM INTERFERENCE SUPPRESSION IN FULL-DUPLEX COMMUNICATIONS

Capacicom Ltd., Kfar Net...

1. A transceiver, comprising:a transmitter coupled to a coaxial network via multiple coupling devices, the transmitter configured to transmit to the coaxial network, via the multiple coupling devices, multiple respective transmit signals that are split from a common signal; and
a receiver, configured to:
receive, via the multiple coupling devices, multiple respective reception signals that are interfered by respective leakage signals caused by local leakage of the transmit signals in the transceiver;
generate from the multiple reception signals a combined reception signal having a suppressed level of the local leakage of the transmit signals, by combining the multiple reception signals with one another while a leakage signal in at least one of the reception signals has a reversed phase relative to the leakage signal in another of the reception signals; and
process the combined reception signal to recover data carried in the multiple reception signals.

US Pat. No. 10,511,344

TRANSCEIVER RESONANT RECEIVE SWITCH

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:an input port;
an output port; and
a resonant receive switch circuit coupled between the input port and the output port, said resonant receive switch circuit comprising a first switch, a second switch, a capacitor, and an input matching inductor, wherein (i) said input matching inductor is coupled between said input port and said output port, (ii) said capacitor is coupled in series with said first switch across said input matching inductor, (iii) said second switch is coupled between a circuit ground and a node formed by connection of said capacitor and said first switch, (iv) when said first switch and said second switch are in a non-conducting state, a signal at the input port is passed to the output port, and (v) when said first switch and said second switch are in a conducting state, the signal at the input port is prevented from reaching the output port.

US Pat. No. 10,511,339

CIRCUIT AND ELECTRONIC EQUIPMENT

NOVARS INC., Tokyo (JP)

1. A circuit with an external load, a power supply, and a power switch, the circuit comprising:a power switch detection unit that detects ON/OFF of the power switch;
a circuit cutoff/conduction unit that cuts or allows electrical connection between the external load and the power supply in accordance with a control signal; and
a control unit that generates the control signal in accordance with an RF signal received from an external information device via an antenna,
wherein the control unit changes an interval between communications with the external information device in accordance with ON/OFF of the power switch which is detected by the power switch detection unit, such that the communications are maintained on condition that the interval during the ON of the power switch is shorter than the interval during the OFF of the power switch.

US Pat. No. 10,511,338

NETWORK-AWARE ADJACENT CHANNEL INTERFERENCE REJECTION AND OUT OF BAND EMISSION SUPPRESSION

University of South Flori...

1. An adaptive windowing method for cellular communication networks, the method comprising:determining a network normalized received power (NNRP) for each of a plurality of links between a transmitter and a receiver in a cellular communication network;
determining a NNRP relative ranking for each of the plurality of links, wherein the NNRP relative ranking is based upon the NNRP of each of the plurality of links relative to the other plurality of links;
increasing transmitter windowing for each of the plurality of links having a higher NNRP relative ranking; and
increasing receiver windowing for each of the plurality of links having a lower NNRP relative ranking.

US Pat. No. 10,511,335

METHOD AND APPARATUS FOR ADJACENT BAND RF SIGNAL RECEPTION

GM GLOBAL TECHNOLOGY OPER...

1. A method comprising:receiving a first signal and a second signal via a first antenna;
amplifying the first signal and the second signal using a first amplifier;
coupling a first portion of the first signal and the second signal to a filter wherein the filter is operative to reduce the amplitude of the second signal to generate a first filtered signal, wherein the coupling is performed by a radio frequency coupler, wherein the radio frequency coupler is a 4 port radio frequency device;
amplifying the first filtered signal to generate an amplified first filtered signal using a second amplifier;
processing the amplified first filtered signal to generate a first data signal; and
coupling a second portion of the first signal and the second signal and processing the second portion to generate a second data signal.

US Pat. No. 10,511,334

ERROR CORRECTION CIRCUIT, OPERATING METHOD THEREOF AND DATA STORAGE DEVICE INCLUDING THE SAME

SK hynix Inc., Gyeonggi-...

1. An error correction circuit comprising:a control unit configured to receive a data chunk including a plurality of data blocks, each of the data blocks being included in a corresponding codeword of a first direction and a corresponding codeword of a second direction; and
a decoder configured to perform a decoding operation on a codeword selected by the control unit in the data chunk,
wherein the control unit selects a first codeword among codewords selected in the data chunk, and provides the first codeword to the decoder by performing a flip operation in a first data block included in the first codeword among data blocks selected in the data chunk,
wherein the control unit selects a second codeword among the selected codewords, and provides the second codeword to the decoder by performing a flip operation in a second data block included in the second codeword among the selected data blocks, and
wherein, when the decoding operation for the first codeword fails, the control unit selects the second data block to be included in different codewords from the first data block.

US Pat. No. 10,511,332

TRANSMITTING METHOD INCLUDING BIT GROUP INTERLEAVING

SAMSUNG ELECTRONICS CO., ...


US Pat. No. 10,511,316

METHOD OF LINEARIZING THE TRANSFER CHARACTERISTIC BY DYNAMIC ELEMENT MATCHING

ANALOG DEVICES GLOBAL UNL...

1. A residue-forming sampling digital to analog converter, the residue-forming sampling digital to analog converter being responsive to a digital word which comprises a first part and a second part, wherein the residue-forming sampling digital to analog converter comprises:a plurality of cooperating digital to analog converters arranged in parallel, wherein:
the plurality of cooperating digital to analog converters receive respective data words from a data word generator,
the data words comprise a shared portion and an additional portion;
the shared portion represents the first part of the digital word following shuffling by the data word generator, and
the additional portion encodes values belonging to the second part of the digital word.

US Pat. No. 10,511,287

ACOUSTIC WAVE FILTER INCLUDING TWO TYPES OF ACOUSTIC WAVE RESONATORS

Skyworks Solutions, Inc.,...

9. A multiplexer with acoustic wave filters, the multiplexer comprising:a first acoustic wave filter coupled to a common node, the first acoustic wave filter including acoustic wave resonators of a first type and a series acoustic wave resonator of a second type coupled between the acoustic wave resonators of the first type and the common node, the acoustic wave resonators of the first type being non-temperature compensated surface acoustic wave resonators and the series acoustic wave resonator of the second type being a temperature compensated surface acoustic wave resonator; and
three other acoustic wave filters coupled to the common node and each having a respective pass band, the series acoustic wave resonator of the second type having a higher quality factor in each of the respective passbands of the three other acoustic wave filters than the acoustic wave resonators of the first type.

US Pat. No. 10,511,248

STEPPING MOTOR, MOTOR DRIVE DEVICE AND TIME DISPLAY DEVICE

CASIO COMPUTER CO., LTD.,...

1. A stepping motor, comprising:a rotor which is two-pole magnetized in a radius direction;
a stator which is formed of a first member and is provided with a rotor receiving section for receiving the rotor;
a yoke which comprises a first side yoke and a second side yoke, both of which are formed of members different from each other and from the first member, and which are disposed on both sides of the stator at approximately bisymmetric positions; and
three coils which are magnetically connected with the stator,
wherein at least one of the three coils is an integrated coil which is integrally formed with the stator by winding a coil around a part of the stator, and a coil other than the integrated coil among the three coils is formed by winding a coil around a part of the yoke.

US Pat. No. 10,511,231

RECONSTRUCTIVE LINE MODULATED RESONANT CONVERTER

Flex Ltd., Singapore (SG...

1. A resonant power converter configured to receive as input a varying input voltage from an input voltage source and to output an output voltage, the resonant power converter comprising:a transformer having a primary winding and a secondary winding, wherein the secondary winding is coupled to an output of the resonant power converter;
a first switch comprising a first terminal, wherein the first terminal is coupled in series to the primary winding;
a second switch coupled in series to the first switch;
a first resonant tank coupled in series with a third switch, wherein the series coupled first resonant tank and third switch are coupled in parallel across the second switch;
a second resonant tank coupled in series with a fourth switch, wherein the series coupled second resonant tank and fourth switch are coupled in parallel across the series coupled first switch and second switch; and
a signal processing circuit coupled to the input voltage supply, to the first terminal of the first switch, and to each of the first switch, the second switch, the third switch, and the fourth switch, wherein the signal processing circuit is configured to sense the input voltage and a first terminal voltage, and to selectively drive each of the first switch, the second switch, the third switch, and the fourth switch according to the sensed input voltage and first terminal voltage.

US Pat. No. 10,511,225

LOW IQ HYSTERETIC-PWM AUTOMATED HYBRID CONTROL ARCHITECTURE FOR A SWITCHING CONVERTER

Dialog Semiconductor (UK)...

1. A DC-DC switching converter, with a low quiescent current (IQ) hysteretic-PWM automated hybrid control architecture, comprising:Pulse Width Modulation (PWM) logic configured to be used during a PWM mode; idle comparators, comprising an over voltage comparator and an under voltage comparator, at an output of said switching converter;
control logic, configured to switch from said PWM mode to a hysteretic mode, wherein said idle comparators are used, and said PWM logic is turned off, during said hysteretic mode; and
a skip comparator, configured to compare an error voltage, output from a gm amplifier, and a programmable skip voltage reference.

US Pat. No. 10,511,156

LIGHTNING CURRENT TRANSMISSION SYSTEM FOR WIND TURBINES

1. A lightning current transmission system between the blades (10) and a nacelle (13) of a wind turbine, comprising:a metal band (18) located at a root of each blade (10) that receives lightning currents from one or more blade lightning current conductors located inside of each blade (10);
a metal ring (12) located at the nacelle (13) that transmits lightning currents to one or more lightning current conductors to drive the lightning currents to earth;
a lightning current transmission element (33) for transmitting lightning currents from the metal band (18) of each blade (10) to the metal ring (12), comprising a conductive portion (35), an insulating portion (37), and supporting means (30) to be joined to a rotor hub (21);
wherein:
the metal band (18) of each blade (10) and the metal ring (12) are configured with protruding parts (61, 63) extended towards the lightning current transmission element (33);
the conductive portion (35) of the lightning current transmission element (33) comprises first and second receptors (47, 47?) mounted on a base plate (41) at different heights and oriented in a direction pointing, respectively, to the protruding parts (61, 63) of the metal band (18) and the metal ring (12);
the base plate (41) comprises a pair of slotted holes (43, 43?) disposed separately at different heights on the base plate (41) and a pair of circular holes (45, 45?), each circular hole of the pair of circular holes (45, 45?) being disposed next to a center of each slotted hole of the pair of slotted holes (43, 43?) of the base plate (41);
each of the receptors (47, 47?) comprises a slotted hole (49, 49?); and
each of the receptors (47, 47?) is mounted on the base plate (41) with a first fastener (51) positioned on each of the circular holes (45, 45?) of the base plate (41) and on an end of each of the slotted holes (49, 49?) of each of the receptors (47, 47?), and with a second fastener (53) positioned on each of the slotted holes (43, 43?) of the base plate (41) and on each slotted hole of the slotted holes (49, 49?) of the receptors (47, 47?).

US Pat. No. 10,511,145

GENERATION OF HIGH-POWER SPATIALLY-RESTRUCTURABLE SPECTRALLY-TUNABLE BEAMS IN A MULTI-ARM-CAVITY VECSEL-BASED LASER SYSTEM

Arizona Board of Regents ...

1. A laser source comprising:a laser cavity network including first and second spatially-distinct cavity arms and a collinear portion, wherein the first and second spatially-distinct cavity arms share the collinear portion,
at least one of the first and second cavity arms containing, intracavity,
a corresponding gain medium including one of (i) a VECSEL-based laser gain medium, (ii) a solid-state gain medium, and (iii) a fiber amplifier and configured to provide amplification of light at a corresponding wavelength;
a first optical system, disposed across an axis of the at least one of the first and second cavity arms, to either refract or reflect light incident thereon while transforming a transverse distribution of said light that has traversed it, and
a second optical system disposed across said axis and characterized by optical losses, at the corresponding wavelength, that are non-uniformly distributed across the second optical system, the second optical system disposed between the corresponding gain medium and the first optical system;
wherein said laser source is configured to maintain, in operation, intracavity generation of light at the corresponding wavelength, said light having
a first transverse mode distribution in a first portion of the laser cavity network between the gain medium and the second optical system,
a second transverse mode distribution in a second portion of the laser cavity network between the second and first optical systems, and
a third transverse mode distribution in a third portion of the laser cavity network, the third portion of the laser cavity network being a remaining portion of the laser cavity network;
wherein the first, second, and third transverse mode distributions are different from one another.

US Pat. No. 10,511,134

LASER SYSTEM FOR GENERATING LASER PULSE OF SUB-NANOSECOND DURATION

QUANTA SYSTEM S.P.A., Sa...

1. A laser system for generating a series of output laser pulses comprising a laser generator that supplies an injection pulse to an amplifier; said amplifier comprising: a gain medium enclosed between a first mirror and a second, output, mirror opposite to said first mirror; and an optical switch set in the proximity of said first mirror; said system being characterized in that: said amplifier is an unstable laser resonator, and said injection pulse is supplied to said laser resonator in synchronism with opening of said optical switch; and said series of output laser pulses comprises at least one pulse having a duration shorter than or equal to 2 ns and an energy higher than 100 mJ and at least three times higher than the energy of all other pulses of said series of output laser pulses; said system further comprising an automated control system capable of maintaining stationary conditions between said at least one pulse and all other pulses of said series of output laser pulses, controlling the gain of said amplifier;said laser system comprises a photodiode that supplies a signal proportional to said output laser pulses emitted by said unstable laser resonator; and
a processor modifies the gain of said laser resonator to reach a desired configuration by executing an algorithm to analyse treatment of noise, identify peaks wherein time and amplitude of the pulses acquired are measured and compare said signal proportional to said output laser pulses emitted by said unstable laser resonator with the desired configuration.

US Pat. No. 10,511,116

CONNECTOR

AutoNetworks Technologies...

1. A connector, comprising:a terminal fitting to be connected to a core of a cable;
a dielectric made of synthetic resin and formed from first and second half bodies that are configured to be united with one another and completely divided from one another in a direction intersecting an arrangement direction of the terminal fitting and the core connected to the terminal fitting, the first and second half bodies that are united being configured to sandwich the terminal fitting in a positioned state; and
a metal member that includes first and second shells assembled respectively with the first and second half bodies to cover outer surfaces of the respective first and second half bodies in a state where the half bodies are divided, the first and second shells being formed respectively with uniting first and second locking portions, wherein
the first shell and the second shell are held together by locking the uniting first locking portion and the uniting second locking portion to each other and thereby hold the first and second half bodies united with one another.

US Pat. No. 10,511,115

CONNECTOR WITH RETAINER

Sumitomo Wiring Systems, ...

1. A connector, comprising:a housing having a cavity with opposite side walls and configured such that a terminal fitting can be inserted at least partly into the cavity, a locking lance cantilevered forward in the housing at a position adjacent the cavity and a deflection space on a side of the locking lance opposite the cavity, the locking lance being deflectable toward the deflection space during insertion of the terminal fitting into the cavity and returning away from the deflection space so that a locking portion of the locking lance locks the terminal fitting that has been inserted into the cavity to a proper position, insertion spaces being defined on opposite lateral sides of the locking lance and between the locking lance and the side walls of the cavity; and
a front retainer to be mounted to the housing substantially from a front of the housing, the front retainer including a deflection restricting portion that is inserted into the deflection space when the terminal fitting has been inserted to the proper position in the cavity, and
the front retainer further including at least one rib configured to enter at least one of the insertion spaces lateral to the locking lance and between the locking lance and the side wall of the cavity for preventing lateral deflection of the locking lance and
the rib being disposed in a height range of the locking portion of the locking lance to be locked to the terminal fitting.

US Pat. No. 10,511,113

MODULAR PLUG PROVIDED WITH METAL SHIELDING COVER, AND COMMUNICATION CABLE

SHENZHEN QINTONG TECHNOLO...

1. A modular plug comprising:a modular plug body having an inner chamber and defining a first aperture in communication with the inner chamber, the modular plug body having a first end and an opposite second end, metal terminals being disposed at the first end, the second end defining an opening in communication with the inner chamber, the opening being configured to allow a cable to be inserted through the opening into the inner chamber; and
a metal shielding cover attached around the modular plug body, the metal shielding cover including at least one metal spring tab that is disposed corresponding to the first aperture and is capable of bending and deforming into the first aperture;
wherein the modular plug body comprises a plurality of body sidewalls cooperatively forming the inner chamber, and the first aperture is defined through one of the body sidewalls;
wherein a pressing resilient tab for snappingly connecting with a connector port is connected to another one of the body sidewalls, and the connector port is configured to receive and electrically connect with the modular plug;
wherein the modular plug body comprises four body sidewalls including a first body sidewall, a second body sidewall, a third body sidewall, and a fourth body sidewall, the four body sidewalls cooperatively forming the inner chamber, the first body sidewall positioned opposite to the third body sidewall, the second body sidewall positioned opposite to the fourth body sidewall, the first aperture is defined in the second body sidewall, the metal shielding cover defines a second aperture corresponding to the first aperture, and the pressing resilient tab is disposed on the fourth body sidewall;
wherein the metal shielding cover comprises a first cover sidewall, a second cover sidewall, and a third cover sidewall, the first cover sidewall and the third cover sidewall extend respectively from two opposite sides of the second cover sidewall, the second aperture is defined between the first cover sidewall and the third cover sidewall, and the at least one metal spring tab is rotatably connected to the first cover sidewall and/or the third cover sidewall; and
wherein the number of the at least one metal spring tab is two, and the two metal spring tabs are respectively connected to the first cover sidewall and the third cover sidewall.

US Pat. No. 10,511,112

MULTI-PORTION CONNECTOR FOR USE WITH DIFFERENTLY-SIZED CARDS

Futurewei Technologies, I...

1. An apparatus, comprising:a connector including a first portion and a second portion, the connector being configured to receive both a first card of a first size and a second card of a second size, wherein the first portion is moveable with respect to the second portion so as to configure the connector in a first orientation or a second orientation, the connector being configurable such that:
in the first orientation, the first portion of the connector is positioned for removably receiving the first card of the first size, or the second portion of the connector is positioned for removably receiving the second card of the second size; and
in the second orientation, the first card is stacked with the second card for being removably inserted in a device to permit electrical communication between the device and the first card when the first card is removably received in the first portion of the connector, and
wherein the connector is configured for being removed from the device without powering down the device.

US Pat. No. 10,511,111

CONDUCTOR CONNECTION STRUCTURE OF LAMINATED WIRING BODY

YAZAKI CORPORATION, Toky...

1. A conductor connection structure of a laminated wiring body comprising:a plurality of plate wiring members which are made of a conductive material and stacked to each other;
an insulating layer which is arranged between the vertically-adjacent plate wiring members to insulate the vertically-adjacent plate wiring members;
a connection portion which is provided in an upper surface of each of the plate wiring members on a way in an extending direction of the plate wiring members; anda leading-out portion configured to permit a mating connector to be electrically connected to the connection portion of a lower plate wiring member among the plurality of plate wiring member while avoiding an upper plate wiring member among the plurality of plate wiring member, the lower plate wiring member is arranged at a layer lower than the upper plate wiring member in the laminated wiring body,wherein each of the plate wiring members terminates at a front end, a rear end, a first lateral edge and a second lateral edge, the first and second lateral edges extend from the front end to the rear end, and
wherein each of the plate wiring members has a width that is measured from the first lateral edge to the second lateral edge, the width is uniform from the front end to the rear end.

US Pat. No. 10,511,110

ELECTRIC SWITCHBOARD TERMINAL BLOCK WITH MULTIPLE LABEL-HOLDER SEATS

MORSETTITALIA S.P.A., Mi...

1. An electric switchboard terminal block having a body (310) extending in a lengthwise longitudinal direction (X-X), widthwise transverse direction (Y-Y) and heightwise vertical direction (Z-Z), and comprising a front face (310a) and side flanks (310b) situated opposite each other in the longitudinal direction (X-X), each flank having a first seat (320) for housing a label (30), and a recess (330) arranged in a central position in the longitudinal direction (X-X), open in the vertical direction (Z-Z) on the front face (310a) of the terminal block and open, on the opposite side, towards an inside of the terminal block, wherein said recess (330) has at least one further seat (331;333) for housing at least one additional label (30), andwherein said recess (330) has a substantially trapezium-like vertical cross-section with a larger base open towards the front face (310a) and a smaller base open towards the inside of the terminal block; the recess also having opposite inclined faces (330a,330b) slanting from the outside toward the inside and from the flanks (310b) towards a central vertical axis (Z-Z).

US Pat. No. 10,511,109

SOCKET WITH LOCKING PARTS TO SECURE TO A RAIL

OMRON Corporation, Kyoto...

1. A socket, comprising:a housing configured to be held on a rail, which extends straight in a first direction and comprises a first side part and a second side part facing each other in a second direction that intersects the first direction,
wherein the housing comprises:
a first locking part disposed on one side of the rail in the second direction to be capable of locking the first side part in a third direction that intersects the first direction and the second direction;
a second locking part disposed on the other side of the rail in the second direction to be capable of locking the second side part in the third direction;
a third locking part disposed between the first locking part and the second locking part in the second direction to face the first locking part to be capable of locking the first side part of the rail in the third direction;
a fourth locking part disposed between the second locking part and the third locking part in the second direction to face the second locking part to be capable of locking the second side part of the rail in the third direction,
wherein the third locking part and the fourth locking part are arranged symmetrically with respect to a virtual straight line that passes through a center of the first locking part and the second locking part in the second direction and extends in the third direction; and
a protruding part disposed midway between the first locking part and the second locking part, and the third locking part and the fourth locking part are connected to the protruding part,
wherein the third locking part comprises:
a first plate spring part extending from the protruding part toward the first locking part, wherein a tip part close to the first locking part in an extending direction of the first plate spring part is bent, and
the fourth locking part comprises:
a second plate spring part extending from the protruding part toward the second locking part, wherein a tip part close to the second locking part in an extending direction of the second plate spring part is bent.

US Pat. No. 10,511,108

DUAL-WIRE CONNECTOR

DINKLE ENTERPRISE CO., LT...

1. A dual-wire connector (1), including:an insulation base (10), having a base plate (11) and an enclosing plate (12) extended from the base plate (11), wherein two insertion ports (121) are formed on the enclosing plate (12);
an electric conductive terminal (20), fastened on the base plate (11), and having a first lateral plate (211) and a second lateral plate (212);
a first electric conductive elastic sheet (30), having a fastening segment (31) and a clamping segment (33), wherein the fastening segment (31) is electrically connected to the electric conductive terminal (20), and the clamping segment (33) is formed at one side of the first lateral plate (211);
a second electric conductive elastic sheet (40), separately arranged with respect to the first electric conductive elastic sheet (30) and having a fastening segment (41) and a clamping segment (43), wherein the fastening segment (41) is electrically connected to the electric conductive terminal (20), and the clamping segment (43) is formed at one side of the second lateral plate (212); and
a pressing member (50), moveably connected to the base plate (11) and having insertion slots (53) corresponding the two insertion ports (121) and a pushing unit (52) formed at one side of the insertion slot (53), wherein through pressing the pressing member (50), the pushing units (52) are able to push and release the clamping segments (33, 43),
wherein a fastening block (14) connected to the base plate (11) is formed on the insulation base (10), two sides of the fastening block (14) are formed with an elastic sheet accommodating zone (15), and the first electric conductive elastic sheet (30) and the second electric conductive elastic sheet (40) are accommodated in the elastic sheet accommodating zones (15).

US Pat. No. 10,511,107

CONNECTOR AND SOCKET

OMRON Corporation, Kyoto...

1. A connector adapted to be housed inside a socket that comprises a first terminal connection part, which is capable of connecting a first terminal, and a second terminal connection part, which is capable of connecting a second terminal and electrically connected to the first terminal connection part, and the connector being disposed in a conduction path connected to the first terminal connection part and the second terminal connection part, the connector comprising:a body part adapted to be attached to the socket; and
a first connection part and a second connection part arranged side by side along a first direction and connected to the body part respectively,
wherein the first connection part comprises:
a first contact part and a second contact part disposed opposite to each other with a gap in a second direction that intersects the first direction, and
the second connection part comprises:
a third contact part and a fourth contact part disposed opposite to each other with a gap in the second direction,
wherein a shortest distance between the first contact part and the second contact part is set greater than a shortest distance between the third contact part and the fourth contact part.

US Pat. No. 10,511,106

POST-LESS COAXIAL CABLE CONNECTOR WITH COMPRESSION COLLAR

PCT International, Inc., ...

1. A coaxial cable connector comprising:an inner post having opposed front and rear ends;
a coupling nut having opposed front and rear ends, the coupling nut mounted on the inner post; and
a barrel having opposed front and rear ends, a plurality of compression bands formed in the barrel between the front and rear ends thereof, and a radially-contracted cuff at the front end of the barrel, the cuff of the barrel mounted on the inner post;
wherein the rear end of the inner post is proximate to the rear end of the coupling nut and extends to terminate just past the cuff of the barrel in an axial direction.

US Pat. No. 10,511,105

ELECTRIC WIRE WITH TERMINAL AND METHOD OF MANUFACTURING ELECTRIC WIRE WITH TERMINAL

YAZAKI CORPORATION, Mina...

1. A terminal-equipped electric wire, comprising:a terminal including a conductor bonding part and a sheath supporting part; and
an electric wire including a conductor formed of a plurality of strands and a sheath covering the conductor such that the conductor is exposed to a predetermined length, the conductor exposed from the sheath being bonded to the conductor bonding part, and the sheath being supported by the sheath supporting part and being fixed in the terminal,
wherein the sheath supporting part is in a state where there is no permanent distortion with respect to a state when the terminal is present alone.

US Pat. No. 10,511,104

SOLDERABLE ELECTRIC CONNECTION ELEMENT

1. A solderable electrical connection element formed by the steps of:fabricating a stamped and bent component from a metal material as an elongated surface element with a crimping portion and a soldering portion that is offset from the crimping portion in a longitudinal direction;
applying or attaching a solder depot to a surface side of the solder portion which is arranged in the surface plane of the crimping portion;
generating a crease by a bending process so that the soldering portion moves into a back to back position with a substantially flat surface of the crimping portion; and
soldering the connection element together with a conductive structure and performing a crimp attachment process of a respective connection cable in an known manner before or after tinning the soldering portion;
wherein the solderable electrical connection element comprises:
a crimping portion (1) for receiving a connection cable and a soldering portion (2) for bonding to a surface of an electrically conductive structure,
wherein the soldering portion (2) directly adjoins the crimping portion (1) or is offset from the crimping portion (1) by a transition portion (6), and
wherein a solder depot (20) is provided at or attachable at the soldering portion (2),
characterized in that a crease is configured in a section between the crimping portion and the soldering portion (1; 2) or in the transition portion (6) so that the crimping and soldering portion (1; 2) are arranged back to back,
wherein a free side of the soldering portion (2) receives the solder depot (20).

US Pat. No. 10,511,103

ANTENNA MODULE AND PORTABLE DEVICE HAVING SAME

AMOTECH CO., LTD., Inche...

1. An antenna module, comprising:a shielding sheet; and
a radiation pattern in which coils are alternately formed on an upper surface and a lower surface of the shielding sheet to be wound in a vertical direction of the shielding sheet,
wherein the antenna module is disposed between a back cover and a support board of a portable device, one side of the antenna module is collinearly disposed with a short side of the back cover, and the other side of the antenna module is collinearly disposed with a short side of the support board.

US Pat. No. 10,511,102

FEEDER CIRCUIT

Mitsubishi Electric Corpo...

1. A feeder circuit comprising:a first line having a first end and a second end;
a second line having a first end and a second end;
a third line having a first end and a second end;
a first combiner connected to the second end of the first line and the second end of the second line, and configured to combine signals output from both the second end of the first line and the second end of the second line;
a first coupling portion configured to electrically couple a portion of the first line and a portion of the third line to each other; and
a second coupling portion configured to electrically couple a portion of the second line and a portion of the third line to each other in a manner that allows a signal reaching the first combiner from the first end of the third line through the first coupling portion and a signal reaching the first combiner from the first end of the third line through the second coupling portion, to be cancelled out.

US Pat. No. 10,511,101

WIRELESS COMMUNICATION MODULE

MURATA MANUFACTURING CO.,...

1. A wireless communication module comprising:a dielectric substrate;
at least one first end-fire antenna arranged on the dielectric substrate, having directivity in a direction parallel with a surface of the dielectric substrate, and having polarization characteristics being parallel with a first direction; and
at least one patch antenna arranged on the dielectric substrate and provided with a first feed point and a second feed point, the first and second feed points being different from each other,
wherein when the patch antenna is fed from the first feed point, a radio wave having a polarization direction parallel with the first direction is excited, and when the patch antenna is fed from the second feed point, a radio wave having a polarization direction orthogonal to the first direction is excited.

US Pat. No. 10,511,100

INKJET PRINTED FLEXIBLE VAN ATTA ARRAY SENSOR

Georgia Tech Research Cor...

1. A radio-frequency responsive device, comprising:(a) a dielectric substrate having a first side and an opposite second side;
(b) a Van Atta array reflector printed on the first side of the dielectric substrate that reflects an incident signal at a predetermined radio frequency at an incident angle; and
(c) a conductive ground layer disposed adjacent the second side of the dielectric substrate,
wherein the Van Atta array comprises a plurality of linear antenna array pairs, each antenna array pair including two antenna arrays that are electrically coupled to each other and that are spaced apart from each other so that the antenna array pairs form a reflected beam in response to an incident signal that is emitted in a direction corresponding to a source of the incident signal, and
wherein each linear antenna array includes a plurality of patch antenna elements, each patch antenna element including a first port that is electrically coupled to a first wire and a second port, disposed orthogonally to the first port, that is electrically coupled to a second wire.

US Pat. No. 10,511,098

ANTENNAS

1. An antenna, comprising:a metal tube;
a coaxial cable disposed along a central axis of the metal tube; and
a variable-impedance transmission wire structure comprising a dielectric body and a metal part arranged along an axial direction of the coaxial cable,
wherein the metal tube comprises:
a first metal tube, a second metal tube and a third metal tube arranged along the axial direction of the coaxial cable,
wherein
a first dielectric body is disposed in the first metal tube,
a first metal part is disposed in the first metal tube or between the first metal tube and the second metal tube,
a second metal part or a second dielectric body is disposed in the second metal tube,
a third metal part is disposed in the second metal tube or the third metal tube,
and
a fourth metal part is disposed in the third metal tube.

US Pat. No. 10,511,097

NEAR-FIELD ANTENNAS FOR ACCUMULATING ENERGY AT A NEAR-FIELD DISTANCE WITH MINIMAL FAR-FIELD GAIN

Energous Corporation, Sa...

1. A near-field antenna for transmitting radio frequency (RF) power transmission signals, comprising:a conductive plate having opposing first and second planar surfaces and one or more cutouts extending through the conductive place from the first surface to the second surface;
an insulator; and
a feed element, separated from the first surface of the conductive plate by the insulator, configured to direct a plurality of RF power transmission signals towards the conductive plate,
wherein:
at least some of the RF power transmission signals of the plurality of RF power transmission signals radiate through the one or more cutouts and accumulate within a near-field distance of the conductive plate to create at least two distinct zones of accumulated RF energy at each of the one or more cutouts; and
the at least two distinct zones of accumulated RF energy at each of the one or more cutouts are defined based, at least in part, on: (i) a set of dimensions defining each of the one or more cutouts, and (ii) an arrangement of the one or more cutouts.

US Pat. No. 10,511,096

LOW COST DIELECTRIC FOR ELECTRICAL TRANSMISSION AND ANTENNA USING SAME

WAFER LLC, Hanover, NH (...

1. A transmission antenna for RF signal, comprising:a dielectric plate;
a plurality of radiating patches positioned on one surface of the dielectric plate;
a plurality of delay lines positioned on opposite surface of the dielectric plate, each one of the delay lines coupled to one of the plurality of radiating patches;
a variable dielectric constant (VDC) layer;
a plurality of conductive electrodes abutting the VDC layer, wherein each pair of conductive electrode of the plurality of conductive electrodes corresponds to one of the delay lines;
a ground plane having a plurality of windows, each aligned with one of the delay lines; and,
wherein the dielectric plate comprises a sandwich of at least one high-dielectric constant layer and one foam plate.

US Pat. No. 10,511,095

ANTENNA MODULE

WITS Co., Ltd., Gyeonggi...

1. An antenna module comprising:a coil part comprising a second antenna wiring formed on an insulating substrate in a spiral shape and a first antenna wiring disposed in an internal region of the second antenna wiring; and
a magnetic part comprising a first magnetic part disposed in the internal region of a first surface of the insulating substrate and a second magnetic part disposed on a second surface of the insulating substrate,
wherein the entirety of the first magnetic part is disposed in the internal region of the second antenna wiring, and
wherein the first magnetic part and the second magnetic part are disposed to face each other in the internal region of the first antenna wiring with the insulating substrate interposed therebetween.

US Pat. No. 10,511,094

ANTENNA ASSEMBLY FOR A COMMUNICATION SYSTEM

TE Connectivity Corporati...

1. A communication system comprising:an antenna assembly having an antenna element and a transmission line terminated to the antenna element, the antenna element having a substrate and a dual dipole antenna circuit including a low-band ground terminal, a low-band feed terminal, a high-band ground terminal and a high-band feed terminal, the transmission line having at least one feed line electrically connected to the dual dipole antenna circuit and at least one ground line electrically connected to the dual dipole antenna circuit; and
a housing holding the antenna assembly, the housing including an upper shell and a lower shell meeting at an interface, the upper shell having an inner end at the interface and the lower shell having an inner end at the interface, the upper shell including an upper strain relief component at the inner end of the upper shell, the lower shell including a lower strain relief component at the inner end of the lower shell aligned with the upper strain relief to receive the transmission line, the upper shell having an upper locating feature, the lower shell having a lower locating feature, the upper locating feature interfacing with the lower locating feature to locate the upper shell relative to the lower shell.

US Pat. No. 10,511,093

ACTIVE UHF/VHF ANTENNA

Ethertronics, Inc., San ...

1. An active antenna, comprising:a first substrate;
a first antenna element positioned on the first substrate adjacent to a ground plane, the first antenna element coupled to a first conductor at a first filter, the first antenna element further coupled to a second conductor at a second filter, the first antenna element configured for multiple resonances in the UHF and VHF bands;
a first parasitic element positioned adjacent to the first antenna element and the ground plane, wherein the first parasitic element is coupled to the ground plane at a first multi-port switch;
the first multi-port switch configured to open-circuit, short-circuit, or reactively load the first parasitic element;
the first multi-port switch coupled to a first processor, and the first processor configured to further couple with a television receiver circuit,
wherein the first processor is configured to receive channel selection information from the television receiver circuit, and using an algorithm resident in the first processor, determine an optimal mode of the active antenna, and communicate control signals to the first multi-port switch for configuring the active antenna in the optimal mode.

US Pat. No. 10,511,089

ANTENNA DEVICE AND ELECTRONIC APPARATUS

MURATA MANUFACTURING CO.,...

1. An antenna device comprising:a first system coil antenna including a first coil conductor wound around a first winding axis and a first coil opening surrounded by the first coil conductor; and
a second system coil antenna including a second coil conductor wound around a second winding axis extending in a second winding axis direction different from a first winding axis direction in which the first winding axis extends, and a second coil opening surrounded by the second coil conductor; wherein
when viewed from the first winding axis direction, the second coil conductor is positioned within a first region including the first coil conductor and the first coil opening;
the second coil conductor includes a first conductor section and a second conductor section on opposed sides of the second winding axis; and
the first conductor section or the second conductor section does not overlap with any other portion of the second coil conductor when viewed from the first winding axis direction.

US Pat. No. 10,511,085

SYSTEM FOR FASTENING A TELEMATIC MODULE TO THE ROOF OF A MOTOR VEHICLE

Magneti Marelli S.p.A., ...

1. A system for fastening a telematic module to a structure of a motor vehicle, in particular to the roof of a motor vehicle, comprising:a telematic module having a closed outer casing and containing at least one first connector for receiving signals and at least one electronic component for processing said signals; and
a block for supporting said module, which is to be fixed to said structure of the motor vehicle and is equipped with a second connector designed for connection to said first connector, wherein said first and second connectors have a configuration of a male-female type that defines a single direction of mutual connection for said first and second connectors;
at least one coupling element and a respective receiving seat, the former carried by said block and the latter carried by said module, or vice versa, which are to be coupled together as a result of a movement of said module and said supporting block towards one another in said direction;
wherein said coupling element comprises a lateral projection or recess, and wherein said supporting block or said module has a manually operable locking member, which carries an interference element and is mobile in a direction transverse to said single direction of connection, between an inactive position, in which said coupling element is allowed to fit into said seat, and an active position, in which said interference element engages said coupling element fitted into said seat at said lateral projection or recess, thus preventing extraction of said coupling element from said seat; and
wherein said locking member has on itself at least two localised surface features for identifying said active and inactive positions.

US Pat. No. 10,511,050

BATTERY STATE OF HEALTH ESTIMATION BY TRACKING ELECTRODE AND CYCLABLE LITHIUM CAPACITIES

SF Motors, Inc., Santa C...

1. A method for determining the health of a battery, comprising:determining an open circuit voltage (OCV) for a full battery;
estimating an electrode stoichiometry by fitting the full battery OCV using a half cell anode OCV and a half cell cathode OCV;
measuring, by a battery management system on a battery powered system, a plurality of full cell OCVs during the lifecycle of a first battery on the battery powered system, wherein each of the plurality of full cell OCVs are measured at a different state of charge (SOC) for the first battery;
determining, by the battery management system, an anode capacity, a cathode capacity, and a lithium ion capacity for the first battery based on the measured SOCs, the anode OCV, and the cathode OCV; and
analyzing, by the battery management system, the anode capacity, a cathode capacity, and the lithium ion capacity to predict a degradation source in the first battery.

US Pat. No. 10,511,041

METHOD OF CONTROLLING OPERATION OF FUEL CELL SYSTEM

Hyundai Motor Company, S...

1. A method of controlling operation of a fuel cell system that performs a regenerative operation according to respective states of a fuel cell stack, comprising steps of:diagnosing, by a controller, a water shortage state in a fuel cell stack based on degradation of cooling performance and deterioration of the fuel cell stack;
determining, by the controller, a diagnosis level of the fuel cell system based on the diagnosed water shortage state of the fuel cell stack;
performing, by the controller, the regenerative operation with an intensity of the regenerative operation which corresponds to the determined diagnosis level to prevent deterioration of the fuel cell stack by predicting deterioration of the fuel cell stack and to regenerate the fuel cell stack when the fuel cell stack is deteriorated; and
controlling, by the controller, a cooling system or a hydrogen/air supply system according to the regenerative operation,
wherein in the determining of the fuel cell system, a first state where the fuel cell stack is not deteriorated yet, but a water shortage due to degradation in cooling performance is predicted to occur is determined as Diagnosis Level 1,
wherein in the determining of the fuel cell system, a second state where the fuel cell stack is deteriorated due to a water shortage and where a heat value of the fuel cell stack is increased is determined as Diagnosis Level 2, wherein the higher diagnosis level means the greater water shortage severity,
wherein the deterioration of the fuel cell stack is determined based on a voltage-current curve of the fuel cell stack or an impedance or current interruption method with respect to the fuel cell stack,
wherein the regenerative operation includes a first regenerative operation for reducing an operating limit temperature of the fuel cell stack; a second regenerative operation for increasing an air pressure on the cathode side of the fuel cell stack or reducing an air stoichiometric ratio; and a third regenerative operation for reducing a hydrogen gas pressure on an anode side of the fuel cell stack or increasing a hydrogen stoichiometric ratio such that at least one regenerative operation among the first regenerative operation, the second regenerative operation, and the third regenerative operation is selected, and
wherein, in Diagnosis Level 1, the regenerative operation is performed while changing the intensity of the regenerative operation in a selected regenerative operation and in Diagnosis Level 2, the regenerative operation is performed with maximum intensity in the selected regenerative operation.

US Pat. No. 10,511,032

FUEL CELL WITH PURGE MANIFOLD

AUDI AG, Ingolstadt (DE)...

1. A fuel cell comprising:an electrode assembly including an electrolyte between an anode and a cathode for generating an electric current and byproduct water;
a porous plate adjacent the electrode assembly, the porous plate including reactant gas channels for delivering a reactant gas to the electrode assembly; and
a separator plate adjacent the porous plate such that the porous plate is between the electrode assembly and the separator plate, the separator plate including a reactant gas inlet manifold and a reactant gas outlet manifold in fluid connection with the reactant gas channels, and a purge manifold in fluid connection with the porous plate such that limiting flow of the reactant gas through the reactant gas outlet manifold and opening the purge manifold under a pressure of the reactant gas in the reactant gas channels drives the byproduct water through pores in the porous plate toward the purge manifold for removal from the fuel cell.

US Pat. No. 10,511,029

METHOD FOR MANUFACTURING CATALYST SUPPORT, CATALYST SUPPORT MANUFACTURED THEREBY, AND CATALYST FOR FUEL CELL INCLUDING THE SAME

HYUNDAI MOTOR COMPANY, S...

9. A catalyst support manufactured by a method comprising steps of:heat-treating a crystalline carbon support in a temperature range from 700° C. to 1100° C. under a vapor atmosphere to increase a specific surface area of the carbon support; and
applying a magnetic field to the increased specific surface area of the carbon support to remove an impurity,
wherein a strength of the magnetic field ranges from 3,000 G to 40,000 G.

US Pat. No. 10,511,018

CONDUCTIVE COATINGS FOR ACTIVE ELECTROCHEMICAL MATERIALS

Physical Sciences, Inc., ...

1. A method for producing a coated powder electrode, the method comprising:homogeneously mixing an electrochemically active material including electrochemically active particles with conductive particles 5-50 nm in size in a ratio determined by the surface area of the electrochemically active particles to localize the conductive particles about each electrochemically active Particle;
adding a polymer and mixing to secure the conductive particles about each electrochemically active particle;
adding a binder dispersed in a solvent to produce an electrode; and
the polymer not soluble in the solvent.

US Pat. No. 10,511,017

HOLLOW CARBON NANOSPHERE COMPOSITE BASED SECONDARY CELL ELECTRODES

The George Washington Uni...

1. An ion storage material comprising (a) a composite of hollow carbon nanosphere material and (b) a metal, a metalloid, an alloy, a compound thereof, or any combination of the foregoing;wherein the metal, metalloid, alloy, compound thereof, or any combination of the foregoing, is selected from the group consisting of As, Si, Ge, Ga, GaAs, Sn, Pb, Bi, Zn, Te, Sb, Al, In, Cd, Au, Ag, V, Mo, W, Nb, Ta, and Ti, and any combination of the foregoing, a chalcogenide thereof, a pnictide thereof, a halide thereof, a boride thereof, and any combination of the foregoing; and
wherein the metal, metalloid, alloy, a compound thereof, or any combination of the foregoing is located in interstices between the hollow carbon nanosphere material.

US Pat. No. 10,511,012

PROTECTIVE COATINGS FOR CONVERSION MATERIAL CATHODES

QuantumScape Corporation,...

1. An energy storage device comprising:a. an anode,
b. an electrolyte, and
c. a cathode comprising:
a plurality of coated electrochemically active material particles, each electrochemically active material particle comprising:
a core comprising a conversion material, and
a coating surrounding the core comprising the conversion material,
wherein the coating selectively isolates the conversion material from the electrolyte,
wherein the electrochemically active material particles have a capacity that is greater than 300 mAh/g;
wherein the coating has a median coating coverage surrounding the core comprising the conversion material that is at least 90% of the surface area of the core comprising the conversion material; and
wherein the core comprising the conversion material comprises conversion material in the charged state;
wherein the conversion material comprises a fluoride of a metal; and wherein the metal is iron, manganese, nickel, copper, or cobalt; wherein the coating surrounding the core comprises lithium oxides, lithium halides, lithium alloys, or combinations thereof.

US Pat. No. 10,511,010

NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

PANASONIC CORPORATION, O...

1. A nonaqueous electrolyte secondary battery comprising: a conductive outer case, an electrode body in the outer cane, a conductive seal plate closing an open end of the outer can, and an external terminal on the seal plate; anda current cutoff mechanism that is located on an electrical conduction pathway between the external terminal and the electrode body, the current cutoff mechanism cutting off electrical connection between the external terminal and the electrode body in response to an increase in an internal pressure in the battery,
wherein the current cutoff mechanism including a thin portion of the seal plate and a diaphragm that deforms to cut off the electrical connection between the external terminal and the electrode body in response to the increase in the internal pressure in the battery,
the electrode body and the seal plate electrically connected by a collector lead, and the diaphragm and the collector lead connected by the seal plate, and
the seal plate directly contacts the outer can.

US Pat. No. 10,511,007

NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SANYO Electric Co., Ltd.,...

1. A nonaqueous electrolyte secondary battery, comprising:a flat power generating element including
a positive electrode plate,
negative electrode plate, and
a separator that electrically isolates the positive electrode plate and the negative electrode plate from each other;
an outer package, inside of which the power generating element is disposed;
a sealing body that closes an opening of the outer package;
a positive electrode collector electrically connected to the positive electrode plate;
a negative electrode collector electrically connected to the negative electrode plate; and
nonaqueous electrolyte,
wherein at least one of the collectors between the positive electrode collector and the negative electrode collector includes a first-side base portion disposed near the sealing body, and a first-side lead portion disposed so as to be connected to one end portion of the first-side base portion and to extend towards the power generating element,
wherein the first-side lead portion includes a first-side power generating element joining portion joined to a lateral side of the power generating element, and a first-side inclined portion inclined with respect to a thickness direction of the power generating element from the first-side power generating element joining portion towards an outer side in the thickness direction, and
wherein a sum of a weight of the power generating element and a weight of the nonaqueous electrolyte contained in the power generating element is within a range of 200 g or more to 500 g or less, and
a value of d×cos ? is in a range of 4.6 mm or more to 10.8 mm or less,
where ? is, in the one of the collectors, an angle of inclination of the first-side inclined portion with respect to the thickness direction in a case in which the first-side inclined portion is inclined in the thickness direction from a portion facing a lateral surface of the power generating element in the thickness direction, and d is a length of the first-side inclined portion in a longitudinal direction, and
wherein the one of the collectors is a positive electrode collector, and
wherein the positive electrode collector is formed of aluminum or an aluminum alloy, a Young's Modulus is in a range of 65 G Pa or more to 75 G Pa or less, a geometrical moment of inertia of the first-side lead portion is in a range of 1.4×10?12 m4 or more to 6.2×10?12 m4 or less.

US Pat. No. 10,511,001

COMPACT BATTERY-BASED ENERGY STORAGE SYSTEMS

Sinexcel Inc., Rancho Cu...

1. A battery-based energy storage device comprising:a plurality of rechargeable battery packs;
a battery chamber configured to host the plurality of rechargeable battery packs;
an operation chamber separated from the battery chamber by at least an insulation board;
an energy storage inverter mounted on the operation chamber, wherein the energy storage inverter is configured to convert AC to DC when charging a rechargeable battery pack in the plurality of rechargeable battery packs and to convert DC to AC when providing power to an external device from a rechargeable battery pack in the plurality of rechargeable battery packs;
a battery control box mounted on the operation chamber and configured to control one or more operations of the plurality of rechargeable battery packs;
a first door rotatably mounted on the battery chamber;
a second door rotatably mounted on the battery chamber, wherein the first door and the second door open outward and are on opposite sides of the battery chamber;
a third door rotatably mounted on the operation chamber; and
an air conditioner mounted on the third door, wherein the insulation board includes a protruding portion that covers at least some space above the operation chamber, so as to create an airway path from the plurality of rechargeable battery packs to the air conditioner.

US Pat. No. 10,510,998

ELECTRODE FEEDTHRU HAVING PIN ATTACHED TO WIRE THEREIN AND METHOD OF MANUFACTURING

PACESETTER, INC., Sylmar...

1. A feedthru assembly for an electrolytic device, the feedthru assembly comprising:a ferrule having a bore, the bore having a reduced diameter portion forming a shoulder;
an electrode assembly positioned within the ferrule, the electrode assembly comprising:
an electrode wire including a first portion and a second portion; and
a crimp pin including a crimp terminal portion and a pin terminal portion, the crimp terminal portion being connected to the first portion of the electrode wire to form a connected portion of the electrode assembly, the connected portion being positioned within the bore of the ferrule, the second portion of the electrode wire extending out from the ferrule in a direction away from the crimp pin; and
an elastomer disposed in the bore of the ferrule between the ferrule and the electrode assembly, the elastomer electrically isolating the ferrule from the electrode assembly and encapsulating at least the connected portion of the electrode assembly, the shoulder of the ferrule extending into the elastomer.

US Pat. No. 10,510,997

FILM-COVERED BATTERY

Envision AESC Energy Devi...

1. A film-covered battery that houses, in a film covering material obtained by stacking a heat sealing layer, a barrier layer, and a protective layer, a battery element obtained by arranging positive and negative electrodes through separators and that has a sealing portion that seals a periphery of the film covering material housing the battery element, the sealing portion comprising: an agglomeration/sealing portion; and a first interface bonding portion having a bonding interface between portions of the film covering material, the first interface bonding portion being provided so as to be adjacent to the battery element housing portion side of the agglomeration/sealing portion, wherein a curved portion is formed in at least a part of a bonding boundary of the first interface bonding portion.

US Pat. No. 10,510,994

METHOD FOR MANUFACTURING ORGANIC DEVICE, AND ROLL

SUMITOMO CHEMICAL COMPANY...

1. A method of manufacturing an organic device using a belt-shaped flexible substrate in a continuously-conveyed manner, the substrate being provided with lead portions having a gas barrier property at a one end and another end in a longitudinal direction, the method comprising:a formation step of forming at least one of an electrode layer and an organic functional layer on the substrate in a region not provided with the lead portions;
a winding step of winding the substrate in a roll shape after the formation step; and
a storage step of storing the roll-shaped substrate after the winding step.

US Pat. No. 10,510,993

PRODUCTION METHOD FOR EL DEVICE

Sharp Kabushiki Kaisha, ...

1. A production method for an EL device including a base material, a TFT layer, and an EL layer;the production method comprising:
forming at least a portion of the base material from a first resin film obtained by curing a first solution applied and a second resin film obtained by curing a second solution applied,
wherein a viscosity of the first solution is made higher than a viscosity of the second solution,
the first solution and the second solution are applied by using a slit coater, and
the application of the first solution is performed by mixed application of a base solution having a lower viscosity than the first solution and a thickener.

US Pat. No. 10,510,991

MASK STRUCTURE FOR PIXEL LAYOUT OF OLED PANEL, OLED PANEL AND METHOD FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A mask structure for pixel layout of an OLED panel, comprising:a deposition mask patterned on a substrate and surrounding each pixel region, the deposition mask comprising a first deposition wall and a second deposition wall arranged oppositely in pairs in a first direction, a third deposition wall and a fourth deposition wall arranged oppositely in pairs in a second direction intersecting the first direction, as well as a fifth deposition wall and a sixth deposition wall arranged oppositely in pairs in the first direction,
wherein the pixel layout comprises a first sub-pixel region adjacent to the second deposition wall, a second sub-pixel region adjacent to the first deposition wall and a third sub-pixel region adjacent to the fourth deposition wall.

US Pat. No. 10,510,990

GROOVE STRUCTURE FOR PRINTING OLED DISPLAY AND MANUFACTURING METHOD FOR OLED DISPLAY

SHENZHEN CHINA STAR OPTOE...

1. A groove structure for printing OLED display, the groove is disposed on a substrate and comprises: a causeway, a groove surrounded and formed by the causeway;the causeway comprising: a first branch causeway layer, and a second branch causeway layer stacked on the first branch causeway layer;
an inclining inner peripheral surface of the groove formed by the first branch causeway layer forming a contact angle ranging from 10° to 45° with the HIL ink of the OLED, and an inclining inner peripheral surface of the groove formed by the second branch causeway layer forming a contact angle ranging from 30° to 60° with the HIL ink of the OLED, and an inclining inner peripheral surface of the groove formed by the second branch causeway layer forming a contact angle ranging from 10° to 45° with the HTL ink and the EML ink of the OLED.

US Pat. No. 10,510,988

ANTI-REFLECTION FILM AND FLEXIBLE DISPLAY DEVICE INCLUDING ANTI-REFLECTION FILM

WUHAN TIANMA MICRO-ELECTR...

1. An anti-reflection film, comprising:a linear polarization film stretched in a first stretching direction; and
a phase delay film stretched in a second stretching direction;
wherein when a light beam passes through the linear polarization film, the light beam is converted into a linear polarized light, and when the light beam passes through the phase delay film, the phase delay film changes a phase of the light beam,
wherein a first acute angle ? is formed between the first stretching direction and the second stretching direction, and
wherein the anti-reflection film has a folding axis, and a vertical line of the folding axis is located within the first acute angle ? in a plane of the anti-reflection film.

US Pat. No. 10,510,987

DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A method for manufacturing a display panel, comprising steps of:forming an encapsulation structure layer on a display motherboard to obtain a panel motherboard, the encapsulation structure layer comprising at least one encapsulation film layer, and the at least one encapsulation film layer overlying a surface of the display motherboard;
forming a cutting groove on the encapsulation structure layer along a cutting line of the panel motherboard;
filling the cutting groove with an isolation material, the isolation material having greater flexibility than the encapsulation film layer in contact with the isolation material; and
cutting the panel motherboard from the isolation material along the cutting line to obtain the display panel.

US Pat. No. 10,510,984

TRANSPARENT DISPLAY DEVICES AND METHODS OF MANUFACTURING TRANSPARENT DISPLAY DEVICES

Samsung Display Co., Ltd....

1. A transparent organic light emitting display device comprising:a transparent base substrate;
a semiconductor device disposed on the transparent base substrate;
a display structure electrically connected to the semiconductor device; and
a protection layer including an adhesion film containing a blue dye and a protection film disposed on the adhesion film, the protection film containing the blue dye;
wherein the blue dye is distributed in at least one of the adhesion film and the protection film to overlap the entire transparent base substrate, and
wherein the transparent base substrate is a colored polymer substrate having a yellow color.

US Pat. No. 10,510,982

DISPLAY SUBSTRATE, METHOD FOR FABRICATING THE SAME, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A display substrate, comprising functional films, wherein at least one of the functional films comprises a protrusion array on a side away from the display substrate, and wherein at least one protrusion portions of the protrusion array are configured to be embedded into a frame sealant between the display substrate and another display substrate, during assembling the display substrate with the another display substrate;wherein the protrusion array comprises protrusion sub-arrays, each of the protrusion sub-arrays comprises a flat portion, and the at least one protrusion portions are arranged on the flat portion;
wherein the functional films comprise a first functional film and a second functional film, the first functional film contacts the display substrate on a side, and contacts a side of the second functional film on the other side, the second functional film comprises the protrusion array on a side away from the display substrate, and the flat portion and the at least one protrusion portions are arranged on the first functional film;
wherein the functional films further comprise a third functional film, the third functional film covers the flat portion, a thickness of the third functional film is smaller than a thickness of the protrusion portions, the third functional film is provided with at least one via holes, and a top of the at least one protrusion portions passes through the via holes.

US Pat. No. 10,510,981

ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL, FABRICATION METHOD, AND ELECTRONIC APPARATUS

SHANGHAI TIANMA AM-OLED C...

1. An organic light-emitting diode (OLED) display panel, comprising:a substrate;
an organic light-emitting device comprising a first electrode, an organic light-emitting layer, and a second electrode, successively disposed on one side of the substrate, wherein the second electrode has a first side facing toward the substrate and an opposing side; and
a capping layer disposed on the opposing side of the second electrode,
wherein a material of the capping layer includes a compound of the following chemical formula (I):

 wherein:
L1, L2, L3, and L4 are independently selected from a hydrogen atom, a substituted or unsubstituted alkyl, a substituted or unsubstituted alkenyl, a substituted or unsubstituted alkynyl, and a substituted or unsubstituted phenyl, and a total quantity of benzene rings included in L1, L2, L3, and L4 is from 0 to 6; and
Y1, Y2, Y3, Y4, Y5, and Y6 include:
two selected from Y3, Y4, Y5, and Y6, each including one of the alkenyl and the alkynyl, and
a remaining of Y1, Y2, Y3, Y4, Y5, and Y6, being independently selected from a hydrogen atom, a substituted or unsubstituted alkyl, a substituted or unsubstituted alkenyl, and a substituted or unsubstituted alkynyl.

US Pat. No. 10,510,980

DISPLAY MODULE

Samsung Display Co., Ltd....

1. A display module comprising:a flat window member comprising a display area and a bezel area;
a display panel configured to produce an image, and comprising a display part for producing the image and overlapping the display area, and an edge part overlapping the bezel area and bent from the display part to extend away from the flat window member;
a dummy member on the display panel, and comprising:
a flat part overlapping the display part; and
a bending part overlapping the edge part; and
a protective frame accommodating the display panel and coupled to the flat window member,
wherein the edge part is bent in accordance with a first curvature from the display part, and
wherein the bending part is bent in accordance with the first curvature from the flat part.

US Pat. No. 10,510,977

COMPOUND, LIGHT-EMITTING MATERIAL, AND ORGANIC LIGHT-EMITTING DEVICE

KYULUX, INC., Fukuoka (J...

1. A compound having a structure represented by the following general formula (1):wherein:one or more of R1, R2, R3, R4, and R5 each independently represent a 9-carbazolyl group having a substituent at at least one of 1-position and 8-position, a 10-phenoxazyl group having a substituent at at least one of 1-position and 9-position or a 10-phenothiazyl group having a substituent at at least one of 1-position and 9-position, the balance thereof represents a hydrogen atom or a substituent, provided that the substituent excludes a 9-carbazolyl group having a substituent at at least one of 1-position and 8-position, a 10-phenoxazyl group having a substituent at at least one of 1-position and 9-position or a 10-phenothiazyl group having a substituent at at least one of 1-position and 9-position;
two to four of R1, R2, R3, R4, and R5 each independently represent a substituted or unsubstituted 9-carbozolyl group, a substituted or unsubstituted 10-phenoxazyl group or a substituted or unsubstituted 10-phenothiazyl group; and
R2 and R4 each independently represent a substituted or unsubstituted 9-carbazolyl group, a substituted or unsubstituted 10-phenoxazyl group or a substituted or unsubstituted 10-phenothiazyl group, and at least one of R1, R3 and R5 is a hydrogen atom, or alternatively R2 and R4 are a hydrogen atom; and
one or more of carbon atoms constituting ring skeletons of all of said respective 9-carbazolyl group, all of said respective 10-phenoxazyl group, and the 10-phenothiazyl group may be replaced by a nitrogen atom.

US Pat. No. 10,510,974

EMISSIVE DEVICES FOR DISPLAYS

Intel Corporation, Santa...

1. An emissive laser device comprising:an emission layer between a hole transport layer and an electron transport layer;
a first metasurface mirror adjacent to the electron transport layer; and
a second metasurface mirror adjacent to the hole transport layer, the first and second metasurface mirrors to sustain one or more resonant optical modes.

US Pat. No. 10,510,972

OLED DISPLAY PANEL AND A DISPLAY DEVICE COMPRISING THE SAME

SHANGHAI TIANMA AM-OLED C...

18. An OLED display panel, comprising:a first electrode, a second electrode, a light emitting layer disposed between the first electrode and the second electrode; and
a first functional layer and a second functional layer disposed on a first and a second sides of the light emitting layer respectively, wherein the first functional layer comprises at least one compound having a hole transport capability,
wherein the second functional layer comprises at least one compound having an electron transport capability;
wherein the light emitting layer comprises an organic light emitting compound;
wherein the light emitting layer is doped with a thermally activated delayed fluorescent material;
wherein a lowest triplet energy level of the organic light emitting compound (TH) is higher than a lowest singlet energy level of the thermally activated delayed fluorescent material (ST);
wherein the lowest triplet energy level of the compound having a hole transport capability (T1) and the lowest triplet energy level of the organic light emitting compound (TH) satisfy formula (I):
T1?TH>?0.2 eV  formula (I);
wherein the lowest triplet energy level of the compound having an electron transport capability (T2) and the lowest triplet energy level of the organic light emitting compound (TH) satisfy formula (II):
T2?TH>?0.2 eV  formula (II);
wherein that a third functional layer is disposed between the first electrode and the first functional layer, and the third functional layer comprises a hole transport compound having a structure of formula (K-1):
andwherein in formula (K-1), Rk1, Rk2, Rk3, Rk4, Rk5, and Rk6 are each independently any one selected from the group consisting of hydrogen, an unsubstituted phenyl, or a phenyl group having a C1-C6 alkyl substituent; Rk5 and Rk6 are each independently any one selected from the group consisting of hydrogen, an unsubstituted C1-C6 alkyl, fluorine or chlorine.

US Pat. No. 10,510,971

VAPOR-DEPOSITED NANOSCALE IONIC LIQUID GELS AS GATE INSULATORS FOR LOW-VOLTAGE HIGH-SPEED THIN FILM TRANSISTORS

Massachusetts Institute o...

1. A film comprising a crosslinked polymer and an ionic liquid, wherein the ionic liquid is dispersed in the crosslinked polymer; the crosslinked polymer comprises a plurality of residues of a monomer and a plurality of residues of a crosslinker; the film has a thickness of about 20 nm to about 1000 nm; and the film has a capacitance of about 1 ?F/cm2 to about 5 ?F/cm2 at a frequency of about 1 MHz.

US Pat. No. 10,510,970

OPPOSITE SUBSTRATE AND MANUFACTURING METHOD THEREOF, ORGANIC LIGHT-EMITTING DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An opposite substrate, comprising: a base substrate, an auxiliary electrode on the base substrate, a planarization layer on a side of the auxiliary electrode facing away from the base substrate, a spacer on a side of the planarization layer facing away from the base substrate, a conductive layer on a side of the spacer facing away from the base substrate, and black matrices located between the base substrate and the auxiliary electrode; wherein the conductive layer at least covers a surface of the spacer facing away from the base substrate, and the conductive layer is electrically connected with the auxiliary electrode through a via hole structure passing through the planarization layer.

US Pat. No. 10,510,968

ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES

UNIVERSAL DISPLAY CORPORA...

1. A compound having the formula Ir(LA)n(LB)3-n, having the structure:
wherein A1, A2, A6, A7, and A8 are carbon;
wherein A5 is nitrogen;
wherein X is O;
wherein R1, R2, R3, and R4 independently represent mono-, di-, tri-, tetra-substitution, or no substitution;
wherein any adjacent substitutions in R1, R2, R3, and R4 are optionally linked together to form a ring;
wherein R1, R2, R3, and R4 are independently selected from the group consisting of hydrogen, deuterium, alkyl, cycloalkyl, and combinations thereof; and
wherein n is an integer from 1 to 3.

US Pat. No. 10,510,967

ORGANIC COMPOUND, AND MIXTURE, FORMULATION AND ORGANIC DEVICE COMPRISING THE SAME

1. An organic compound having the following general structural formula (1):
wherein the symbols and signs used therein have the following meanings:
Ar1, Ar2, Ar3, Ar4 or Ar5 is the same or different in multiple occurrences, independently selected from the group consisting of an aromatic, heteroaromatic or nonaromatic ring system having 2 to 20 carbon atoms, and is optionally substituted with one or more R1 groups, wherein the R1 group in multiple occurrences is the same as or different from each other;
n is 3 or 4;
X, Y in each occurrence are the same or different doubly-bridging groups, each of X, Y is connected to Ar2 or Ar3 by a single bond or a double bond and is selected from the group consisting of: a single bond, N(R1), B(R1), C(R1)2, O, C?O, C?S, C?Te, C?NR1, Si(R1)2, C?C(R1)2, S, S?O, SO2, P?O, P?S, P?Se, P?Te, Se, Te, P(R1), and P(?O)R1, or a combination of any two, three or four thereof;
Z in each occurrence is the same or different triply-bridging group, wherein each Z is connected to Ar1 or Ar2 or Ar5 by a single bond or a double bond;
R1 in each occurrence is the same or different and independently selected from the group consisting of —H, —F, —Cl, Br, I, -D, —CN, —NO2, —CF3, B(OR2)2, Si(R2)3, straight chain alkane, alkane ether, alkane sulfide having 1 to 10 carbon atoms, branched alkane, cycloalkane, alkane ether having 3 to 10 carbon atoms; R1 is optionally substituted with one or more active groups R2, and wherein one or more non-adjacent methylene groups of R1 are optionally replaced by R2C?CR2, C?C, Si(R2)2, Ge(R2)2, Sn(R2)2, C?O, C?S, C?Se, C?N(R2), O, S, —COO—, or CONR2; one or more H atoms of R1 are optionally replaced by D, Cl, Br, I, CN or N2, or replaced by an aromatic amine group containing one or more reactive groups R2 or aromatic group and optionally substituted with a heteroaromatic ring, or replaced by an optionally substituted or unsubstituted carbazole;
R2 in each occurrence is the same or different and independently selected from H, D, aliphatic alkanes having 1 to 10 carbon atoms, aryl hydrocarbons, optionally substituted or unsubstituted aryl ring or heterocyclic aryl ring containing 5 to 10 carbon atoms;
at least one of X and Z is not identical to Y; and
the dotted line in the general structural formula (1) represents one bond between adjacent monomers in the organic compound.

US Pat. No. 10,510,965

COMPOSITION FOR FORMING ORGANIC SEMICONDUCTOR FILM, ORGANIC THIN FILM TRANSISTOR, ELECTRONIC PAPER, AND DISPLAY DEVICE

FUJIFILM Corporation, To...

1. A composition for forming an organic semiconductor film, comprising:an organic semiconductor material;
a phenolic reductant;
a polymer compound having a weight-average molecular weight of equal to or greater than 500,000;
a surfactant; and
an organic solvent having a standard boiling point of equal to or higher than 150° C.,
wherein a ratio of a content of the organic semiconductor material to a content of the polymer compound is 0.02 to 10 based on mass,
a ratio of a content of the phenolic reductant to the content of the polymer compound is 0.1 to 5 based on mass, and
a ratio of the content of the polymer compound to a content of the surfactant is 3 to 200 based on mass.

US Pat. No. 10,510,964

COMPOUND, ORGANIC ELECTROLUMINESCENCE DEVICE MATERIAL, ORGANIC ELECTROLUMINESCENCE DEVICE AND ELECTRONIC DEVICE

IDEMITSU KOSAN CO., LTD.,...

1. An organic electroluminescence device comprising:an anode;
a cathode opposed to the anode; and
an organic compound layer provided between the anode and the cathode, the organic compound layer comprising a compound according to formula (1):
where:one of X1 to X8 is a carbon atom bonded to a group according to formula (2);
the rest of X1 to X8 are CRx or a nitrogen atom;
Rx is not the group according to formula (2); and
each Rx is independently selected from the group consisting of:
a hydrogen atom,
a halogen atom,
a cyano group,
a nitro group,
a substituted or unsubstituted hydroxyl group,
a substituted or unsubstituted carboxyl group,
a substituted or unsubstituted sulfonyl group,
a substituted or unsubstituted boryl group,
a substituted or unsubstituted phosphino group,
a substituted or unsubstituted mercapto group,
a substituted or unsubstituted acyl group,
a substituted or unsubstituted amino group,
a substituted or unsubstituted silyl group,
a substituted or unsubstituted alkyl group having 1 to 30 carbon atoms,
a substituted or unsubstituted alkenyl group having 2 to 30 carbon atoms,
a substituted or unsubstituted alkynyl group having 2 to 30 carbon atoms,
a substituted or unsubstituted aralkyl group having 6 to 30 carbon atoms,
a substituted or unsubstituted aryl group having 6 to 40 ring carbon atoms, and
a substituted or unsubstituted heteroaryl group having 5 to 40 ring atoms; and
among X1 to X8, adjacent Rx of CRx are not bonded to each other;
where:b is an integer of 1 to 5;
c is an integer of 1 to 8;
Z is an oxygen atom, a sulfur atom, or a silicon atom;
when b is 2 to 5, Z are the same or different;
when Z is a silicon atom, R9 and R10 are bonded to the silicon atom, R9 and R10 each independently represent Rx as defined in formula (1), and R9 and R10 are optionally bonded to the structure according to formula (1);
when Z is a silicon atom, R9 and R10 are not bonded to each other to form a cyclic structure;
L is a single bond or a linking group;
the linking group is a substituted or unsubstituted, linear, branched or cyclic polyvalent aliphatic hydrocarbon group having 1 to 30 carbon atoms, a substituted or unsubstituted polyvalent aryl group having 6 to 40 ring carbon atoms, or a substituted or unsubstituted polyvalent heteroaryl group having 5 to 40 ring atoms;
the polyvalent heteroaryl group having 5 to 40 ring atoms for L comprises a substituted or unsubstituted polyvalent group derived from a phenanthroline ring according to formula (1);
when c is 2 to 8, plural L are the same or different;
one of Y1 to Y8 is a carbon atom bonded to L and a remainder of Y1 to Y8 are each independently CRY;
at least one RY is not a hydrogen atom;
each RY is independently selected from the group consisting of:
a hydrogen atom,
a halogen atom,
a cyano group,
a nitro group,
a substituted or unsubstituted hydroxyl group,
a substituted or unsubstituted carboxyl group,
a substituted or unsubstituted sulfonyl group,
a substituted or unsubstituted boryl group,
a substituted or unsubstituted phosphino group,
a substituted or unsubstituted mercapto group,
a substituted or unsubstituted acyl group,
a substituted or unsubstituted amino group,
a substituted or unsubstituted silyl group,
a substituted or unsubstituted alkyl group having 1 to 30 carbon atoms,
a substituted or unsubstituted alkenyl group having 2 to 30 carbon atoms,
a substituted or unsubstituted alkynyl group having 2 to 30 carbon atoms,
a substituted or unsubstituted aralkyl group having 6 to 30 carbon atoms,
a substituted or unsubstituted aryl group having 6 to 40 ring carbon atoms, and
a substituted or unsubstituted heteroaryl group having 5 to 40 ring atoms;
the substituted or unsubstituted aryl group having 6 to 40 ring carbon atoms for RY is a group selected from a phenyl group, naphthyl group, anthryl group, phenanthryl group, biphenyl group, terphenyl group, quaterphenyl group, fluoranthenyl group, triphenylenyl group, phenanthrenyl group, fluorenyl group, 9,9-dimethylfluorenyl group, spirofluorenyl group, benzo[c]phenanthrenyl group, benzo[a]triphenylenyl group, naphtho[1,2-c]phenanthrenyl group, naphtho[1,2-a]triphenylenyl group, dibenzo[a,c]triphenylenyl group, and benzo[b]fluoranthenyl group;
the heteroaryl group having 5 to 40 ring atoms for RY comprises a substituted or unsubstituted phenanthrolyl group derived from the phenanthroline ring of formula (1);
adjacent RY are bonded to each other to form a cyclic structure, or are not bonded to each other;
when X1 or X8 is a carbon atom bonded to the group according to formula (2), b is 1, Z is an oxygen atom, Y4 or Y5 is a carbon atom bonded to L, and c is 2, the L closer to the phenanthroline ring of formula (1) among two Ls is a divalent group other than an anthracene group;
when X1 or X8 is a carbon atom bonded to the group according to formula (2), b and c are 1, Z is an oxygen atom or a sulfur atom, Y3 is a carbon atom bonded to L, and L is a p-phenylene group, RY for Y4 is a group other than a phenyl group;
when X1 or X8 is a carbon atom bonded to the group according to formula (2), b and c are 1, Z is an oxygen atom or a sulfur atom, Y6 is a carbon atom bonded to L, and L is a p-phenylene group, RY for Y5 is a group other than a phenyl group;
when X1 is a carbon atom bonded to the group according to formula (2), Z is a silicon atom, Y3 is a carbon atom bonded to L, L is a single bond, RY for Y6 is bonded to the phenanthrolyl group as a heteroaryl group having 5 to 40 ring atoms with a single bond, the phenanthrolyl group is bonded to RY for Y6 at a position other than position 2;
when X4 or X5 is a carbon atom bonded to the group according to formula (2), Y2 is a carbon atom bonded to L, L is a single bond, and Z is an oxygen atom, RY for Y7 is a group other than a pyrenyl group; and
when X4 or X5 is a carbon atom bonded to the group according to formula (2), Y7 is a carbon atom bonded to L, L is a single bond, and Z is an oxygen atom, RY for Y2 is a group other than a pyrenyl group.

US Pat. No. 10,510,963

HETEROCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING ELEMENT COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A compound represented by the following Formula 1:
in Formula 1,
Ar1 and Ar2 are the same as each other, and a phenyl group, which is unsubstituted or substituted with one or more substituents selected from the group consisting of deuterium and an alkyl group; a biphenyl group, which is unsubstituted or substituted with one or more substituents selected from the group consisting of deuterium, an alkyl group, and an aryl group; a naphthyl group, which is unsubstituted or substituted with one or more substituents selected from the group consisting of deuterium, an alkyl group, and an aryl group; or a phenanthryl group, which is unsubstituted or substituted with one or more substituents selected from the group consisting of deuterium, an alkyl group, and an aryl group,
L is an unsubstituted phenylene; or an unsubstituted biphenylylene,
R1 and R2 are the same as or different from each other, and each independently an alkyl group; or an aryl group, which is unsubstituted or substituted with one or more substituents selected from the group consisting of deuterium, a halogen group, an alkyl group, and an alkoxy group,
R3 and R4 are the same as or different from each other, and each independently hydrogen; deuterium; or one or two separate fused benzene rings provided that two or more R3s or R4s combine with each other,
m is an integer of 1 to 5,
a is an integer of 0 to 3, and
b is an integer of 0 to 4, and
provided that m, a, and b are each 2 or more, the structures in the parenthesis are the same as or different from each other.

US Pat. No. 10,510,962

COMPOUND AND ORGANIC ELECTRONIC DEVICE USING THE SAME

SHANGHAI NICHEM FINE CHEM...

14. An organic electronic device, comprising a first electrode, a second electrode, and an organic layer disposed between the first electrode and the second electrode, wherein the organic layer comprises the compound as claimed in claim 1.

US Pat. No. 10,510,960

MATERIALS FOR ORGANIC ELECTROLUMINESCENT DEVICES

Merck Patent GmbH, Darms...

1. A compound of formula (1):
where the following applies to the symbols and indices used:
Ar1, Ar2is on each occurrence, identically or differently, an aromatic or heteroaromatic ring system having 5 to 60 C aromatic ring atoms, which may in each case also be substituted by one or more radicals R5, Ar1 and Ar2 here may also be connected to one another by a group E;
E is on each occurrence, identically or differently, a single bond, N(R5),O,S, C(R5)2, C(R5)2-C(R5)2, Si(R5)2 or B(R5);
R1, R2, R3, R4 are selected on each occurrence, identically or differently, from the group consisting of D, F, Cl, Br, I, CN, Si(R6)3, N(R6)2, a straight-chain alkyl, alkoxy or thioalkyl group having 1 to 40 C atoms or a branched or cyclic alkyl, alkoxy or thioalkyl group having 3 to 40 C atoms, each of which may be substituted by one or more radicals R6, where in each case one or more non-adjacent CH2 groups may be replaced by Si(R6)2, C?NR6, P(?O)(R6), SO, SO2, NR6, O, S or CONR6 and where one or more H atoms may be replaced by D, F, Cl, Br or I, an aromatic or heteroaromatic ring system having 5 to 60 aromatic ring atoms, which may in each case be substituted by one or more radicals R6, an aryloxy or heteroaryloxy group having 5 to 60 aromatic ring atoms, which may be substituted by one or more radicals R6, or an aralkyl or heteroaralkyl group having 5 to 60 aromatic ring atoms, which may in each case be substituted by one or more radicals R6;
R is selected on each occurrence, identically or differently, from the group consisting of D, F, Cl, Br, I, CN, Si(R6)3, a straight-chain alkyl, alkoxy or thioalkyl group having 1 to 40 C atoms or a branched or cyclic alkyl, alkoxy or thioalkyl group having 3 to 40 C atoms, each of which may be substituted by one or more radicals R6, where in each case one or more non-adjacent CH2 groups may be replaced by Si(R6)2, C?NR6, P(?O)(R6), SO, SO2, NR6, O, S or CONR6 and where one or more H atoms may be replaced by D, F, Cl, Br or I, an aromatic or heteroaromatic ring system having 5 to 60 aromatic ring atoms, which may in each case be substituted by one or more radicals R6, an aryloxy or heteroaryloxy group having 5 to 60 aromatic ring atoms, which may be substituted by one or more radicals R6, or an aralkyl or heteroaralkyl group having 5 to 60 aromatic ring atoms, which may in each case be substituted by one or more radicals R6, where two or more adjacent substituents R5 may optionally form a mono- or polycyclic ring system, which may be substituted by one or more radicals R6;
R5 is selected on each occurrence, identically or differently, from the group consisting of H, D, F, Cl, Br, I, CN, Si(R6)3, N(R6)2, a straight-chain alkyl, alkoxy or thioalkyl group having 1 to 40 C atoms or a branched or cyclic alkyl, alkoxy or thioalkyl group having 3 to 40 C atoms, each of which may be substituted by one or more radicals R6, where in each case one or more non-adjacent CH2 groups may be replaced by Si(R6)2, C?NR6, P(?O)(R6), SO, SO2, NR6, O, S or CONR6 and where one or more H atoms may be replaced by D, F, Cl, Br or I, an aromatic or heteroaromatic ring system having 5 to 60 aromatic ring atoms, which may in each case be substituted by one or more radicals R6, an aryloxy or heteroaryloxy group having 5 to 60 aromatic ring atoms, which may be substituted by one or more radicals R6, or an aralkyl or heteroaralkyl group having 5 to 60 aromatic ring atoms, which may in each case be substituted by one or more radicals R6, where two or more adjacent substituents R5 may optionally form a mono- or polycyclic ring system, which may be substituted by one or more radicals R6;
R6 is selected from the group consisting of H, D, F, an aliphatic hydrocarbon radical having 1 to 20 C atoms or an aromatic or heteroaromatic ring system having 5 to 30 C atoms, in which one or more H atoms may be replaced by D or F;
m is 0, 1, 2 or 3;
n is 0, 1, 2, 3 or 4;
p, q are, identically or differently, 0 or 1;
r, s are, identically or differently, 0, 1, 2, 3 or 4; where p +r ?4 and q +s ?4;
t is, on each occurrence, identically or differently, 0, 1, 2 or 3.

US Pat. No. 10,510,958

MASK FRAME, MASK AND METHOD FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A mask frame, comprising:a loop shaped frame body comprising an outer boundary and an inner boundary of the mask frame, the inner boundary defining a space for receiving a mask body;
wherein the mask frame comprises a forced side and a non-forced side, the forced side being subjected to a pulling force of the mask body, the non-forced side being free from the force of the mask body; and
wherein a width between the outer boundary of the forced side of the mask frame and the inner boundary corresponding to the outer boundary decreases gradually in a direction from a middle position on the forced side toward the non-forced side, and
wherein:
at least a section of the forced side is arc-shaped, and in the arc-shaped section, the width between the outer boundary of the forced side and the corresponding inner boundary is set to be proportional to deformation amounts of a hypothetical reference forced side under the same pulling force, wherein the hypothetical reference forced side has a constant width equal to a minimum width between the outer boundary and the corresponding inner boundary of the forced side of the mask, or
the forced side comprises a plurality of sections which have a constant width respectively, and the width between the outer boundary of each of the plurality of sections and the corresponding inner boundary is set to be proportional to deformation amounts at a position of the hypothetical reference forced side corresponding to a middle position of each of the plurality of sections under the same pulling force.

US Pat. No. 10,510,956

COUPLED QUANTUM DOT MEMRISTOR

Oxford University Innovat...

1. A quantum memristor, comprising:a first quantum dot (QD1) which is capacitively coupled to a second quantum dot (QD2),
a source electrode,
a drain electrode, and
a bath electrode,
wherein said source electrode and said drain electrode are coupled via quantum tunneling to QD1 and said bath electrode is coupled via quantum tunneling to QD2, and wherein QD2 is capacitively coupled to either the source electrode or the drain electrode.

US Pat. No. 10,510,954

PHASE CHANGE RANDOM ACCESS MEMORY DEVICE

Taiwan Semiconductor Manu...

1. A memory device, comprising:a first conductive column structure extending entirely through a first dielectric layer, wherein the first conductive column structure comprises a shell portion wrapping a core structure filled with a dielectric material and an end portion that is coupled to a first end of the shell portion and disposed below the core structure, wherein the shell portion comprises a conductive layer;
a first phase change material layer formed over the first dielectric layer, wherein a lower boundary of the first phase change material layer contacts at least a first portion of a second end of the shell portion, the second end being opposite the first end;
a second dielectric layer disposed above the first phase change material layer; and
a second conductive column structure extending through the second dielectric layer, wherein the second conductive column structure comprises a shell portion wrapping a core structure filled with a dielectric material and an end portion that is coupled to one end of the shell portion and disposed below the core structure,
wherein an upper boundary of the first phase change material layer contacts the end portion of the second conductive column.

US Pat. No. 10,510,950

MAGNETORESISTIVE MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A magnetoresistive memory device comprising:a first magnetic layer having a variable magnetization direction;
a second magnetic layer, a magnetization direction of the second magnetic layer being invariable;
a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer; and
a second nonmagnetic layer provided on the first magnetic layer, which is opposite the first nonmagnetic layer, wherein
the first magnetic layer having a stacked layer structure in which an amorphous magnetic material layer is sandwiched between crystalline magnetic material layers,
the magnetoresistive memory device further comprising
nonmagnetic material layers provided between one of the crystalline magnetic material layers and the amorphous magnetic material layer, and between the other crystalline magnetic layer and the amorphous magnetic material layer, respectively.

US Pat. No. 10,510,949

MAGNETIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A magnetic memory device, comprising:a metal-containing layer including a first portion, a second portion, a third portion located between the first portion and the second portion, a fourth portion located between the third portion and the second portion, and a fifth portion located between the third portion and the fourth portion;
a first magnetic layer separated from the third portion in a first direction crossing a second direction, the second direction being from the first portion toward the second portion;
a second magnetic layer provided between the first magnetic layer and a portion of the third portion;
a first intermediate layer including a portion provided between the first magnetic layer and the second magnetic layer, the first intermediate layer being nonmagnetic;
a third magnetic layer separated from the fourth portion in the first direction;
a fourth magnetic layer provided between the third magnetic layer and a portion of the fourth portion;
a second intermediate layer including a portion provided between the third magnetic layer and the fourth magnetic layer, the second intermediate layer being nonmagnetic; and
a controller electrically connected with the first portion, the second portion, and the fifth portion,
a length along a third direction of the third portion being longer than a length along the third direction of the second magnetic layer, the third direction crossing a plane including the first direction and the second direction,
the length along the third direction of the third portion being longer than a length along the third direction of the fifth portion,
the controller being configured to implement:
supplying a first current from the first portion toward the fifth portion, and a second current from the second portion toward the fifth portion; and
supplying a third current from the fifth portion toward the first portion, and a fourth current from the fifth portion toward the second portion.

US Pat. No. 10,510,948

MAGNETORESISTIVE EFFECT ELEMENT, MAGNETIC MEMORY, MAGNETIZATION ROTATION METHOD, AND SPIN CURRENT MAGNETIZATION ROTATIONAL ELEMENT

TDK CORPORATION, Tokyo (...

1. A spin current magnetization rotational type magnetoresistive element comprising:a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer; and
spin-orbit torque wiring which extends in a direction that intersects a stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer,
wherein an electric current that flows through the magnetoresistive effect element and an electric current that flows through the spin-orbit torque wiring merge or are distributed in a portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected, and
the spin-orbit torque wiring is composed of a pure spin current generation portion formed from a material that generates a pure spin current, and a low-resistance portion formed from a material having a smaller electrical resistance than the pure spin current generation portion, and at least a portion of the pure spin current generation portion contacts the second ferromagnetic metal layer.

US Pat. No. 10,510,947

SEMICONDUCTOR DEVICES WITH MAGNETIC REGIONS AND STRESSOR STRUCTURES

Micron Technology, Inc, ...

1. A semiconductor device, comprising:a magnetic region; and
a stressor structure adjacent the magnetic region and configured to vertically expand or vertically contract relative to the magnetic region, the stressor structure configured to exert a vertical stress upon the magnetic region and alter a magnetic anisotropy of the magnetic region when the stressor structure is subjected to a programming current.

US Pat. No. 10,510,946

MRAM CHIP MAGNETIC SHIELDING

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a magnetic random access memory (MRAM) chip comprising:providing a substrate having first and second surfaces, wherein the first surface is defined with a prime die region and the second surface of the substrate defines a back side of the MRAM chip;
forming an upper interlevel dielectric (ILD) layer over the first surface of the substrate, wherein the upper ILD layer comprises a plurality of ILD levels;
forming a magnetic storage element having a magnetic tunneling junction (MTJ) array with MTJ stack in the prime die region and in between adjacent ILD levels of the upper ILD layer;
forming a pad level over the magnetic storage element, wherein the pad level comprises a die bond/bump pad coupled to the magnetic storage element and the pad level defines a front side of the MRAM chip;
forming deep trenches surrounding or adjacent to the MTJ array within the prime die region, wherein the deep trenches extend from a top surface of the pad level and partially into a portion of the substrate;
forming a passivation layer covering the pad level and lining sidewalls and bottom of the deep trenches; and
forming a magnetic shield layer over at least a portion of the front side and sidewalls of the MRAM chip, wherein the magnetic shield layer covers at least a portion of the passivation layer over the pad level.

US Pat. No. 10,510,945

MAGNETOELASTICALLY ACTUATED MEMS DEVICE AND METHODS FOR ITS MANUFACTURE

1. An apparatus, comprising:a substrate; and
a microscale cantilever arm supported at a standoff distance from the substrate;
wherein said arm comprises a laminar magnetic actuator configured to bend the arm when subjected to a magnetic field; and wherein:
the laminar magnetic actuator comprises a film of magnetostrictive material;
the laminar magnetic actuator is a magnetic bimorph comprising a structural layer of copper underlying and adjacent to the film of magnetostrictive material;
the copper structural layer has a thickness in the range 0.5-20 ?m; and
the film of magnetostrictive material has a thickness in the range 0.5-5 ?m.

US Pat. No. 10,510,944

VIBRATION ACTUATOR REDUCED IN COST AND SIZE, AND ELECTRONIC DEVICE

Canon Kabushiki Kaisha, ...

1. A vibration actuator comprising:a vibration element which includes an electromechanical energy conversion element and an elastic body having a pair of contact portions; and
a driven element which is driven relatively to the vibration element in a first direction, the driven element including side surfaces formed respectively on two sides thereof,
wherein the pair of contact portions contact with the driven element in a third direction orthogonal to both of the first direction and a second direction which is a direction of a thickness of the electromechanical energy conversion element, and
wherein each of the contact portions includes a contact surface formed thereon such that a pair of the contact surfaces face the driven element, the contact surfaces respectively contacting the side surfaces of the driven element in the third direction and facing each other through the driven element.

US Pat. No. 10,510,943

STRUCTURE FOR AN ANTENNA CHIP FOR QUBIT ANNEALING

INTERNATIONAL BUSINESS MA...

1. A system, comprising:a superconducting qubit chip having a first qubit with a first Josephson junction and a first set of one or more capacitor pads;
a semiconductor chip positioned above the superconducting qubit chip;
a first radio frequency (RF) emitter on the semiconductor chip, comprising:
a first voltage-controlled oscillator; and
a first antenna driven by the first voltage-controlled oscillator; and
a microcontroller on the semiconductor chip and that signals the first voltage-controlled oscillator to generate a first electromagnetic wave, which the first antenna directs toward the first set of one or more capacitor pads of the first qubit, thereby annealing the first Josephson junction of the first qubit.

US Pat. No. 10,510,941

PROCESS FOR REALIZING A SYSTEM FOR RECOVERING HEAT, IN PARTICULAR BASED ON THE SEEBECK'S EFFECT, AND CORRESPONDING SYSTEM

STMICROELECTRONICS S.R.L....

1. A method of forming an integrated circuit, the method comprising:forming a plurality of thermocouples coupled in series by:
forming first metal segments comprising a first metal, each of the first metal segments having a L-shape, the first metal segments being separated by one of a plurality of gaps;
filling the plurality of gaps by depositing a dielectric layer;
forming a plurality of deep openings to expose a first contact region of each of the first metal segments;
forming a plurality of shallow openings to expose a second contact region of each of the first metal segments; and
forming second metal segments, comprising a second metal, over the dielectric layer, the second metal being a different type of metal than the first metal, wherein each of the second metal segments contacts one of the first contact region of the first metal segments through one of the plurality of deep openings and contacts one of the second contact region of the first metal segments through one of the plurality of shallow openings.

US Pat. No. 10,510,938

PACKAGE SUPPORT, FABRICATION METHOD AND LED PACKAGE

XIAMEN SANAN OPTOELECTRON...

1. A light-emitting diode (LED) package, comprising:a substrate with upper and lower surfaces, including:
a first metal block;
an electrically insulating region surrounding at least a portion of the first metal block;
a first LED chip mounted on the substrate and in electrical communication with the first metal block; and
an encapsulant covering at least an upper surface of the first LED chip;
wherein:
the substrate further includes a second metal block;
the electrically insulating region surrounds at least a portion of the second metal block;
the first and second metal blocks include front frames;
the encapsulant has a substantially flat upper surface and an arc shape at a side to thereby increase a light-emitting angle of the LED package; and
the electrically insulating region is between the first metal block and the second metal block and has an “I” or “H” shape.

US Pat. No. 10,510,934

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a plurality of light emitting elements each including an upper surface as a light extraction surface;
a light transmissive member having a plate shape and bonded to the upper surface of each of the plurality of light emitting elements, having an upper surface and a lower surface, and allowing light from the plurality of light emitting elements to be incident on the lower surface of the light transmissive member and be output from the upper surface of the light transmissive member; and
a light reflective member covering surfaces of the light transmissive member and lateral surfaces of the plurality of light emitting elements, the light reflective member defining an opening with the light transmissive member being provided within the opening so as to expose the upper surface of the light transmissive member, the light reflective member having a projection extending about an entire perimeter of the opening, the projection overlapping with a part of the light extraction surface of each light emitting element of the plurality of light emitting elements as viewed in a light extraction direction perpendicular to the light extraction surface of each light emitting element of the plurality of light emitting elements, the projection having a convex shape facing the part of the light extraction surface of each light emitting element of the plurality of light emitting elements in the light extraction direction,
wherein the upper surface area of the light transmissive member is smaller than a sum of the upper surface areas of the plurality of light emitting elements, and the lower surface area of the light transmissive member is larger than a sum of the upper surface areas of the plurality of light emitting elements.

US Pat. No. 10,510,931

SIDE-VIEW LIGHT EMITTING DIODE PACKAGE STRUCTURE

ADVANCED OPTOELECTRONIC T...

1. A side-view light emitting diode (LED) package structure comprising:two first electrodes being coplanar;
an LED chip mounted on and electrically connected to the first electrodes;
a package body encapsulating the first electrodes, the package body surrounding peripheral sides of the LED chip to define a light emitting region of the LED chip;
a cover layer filling in the light emitting region and covering the LED chip; and
two second electrodes positioned outside the package body and electrically connected to the first electrodes, wherein, along a plane parallel to the first electrodes, a surface area of the second electrodes being greater than a surface area of a portion of the first electrodes positioned in the light emitting region;
wherein a cross section of the package body parallel to the first electrodes comprises two longer sides and two shorter sides connected to each other, each second electrode comprises a connecting portion and an extension portions, each connecting portion is connected to one first electrode, each connecting portion extends from one shorter side towards a direction away from the package body, each extension portion comprises a first extension section and a second extension section, the first extension section extends from an end of the connecting portion facing away from the package body along a direction parallel to the shorter side, the second extension section extends from an end of the first extension section facing away from the connecting portion along a direction parallel to the longer side and towards the package body, the connecting portion, the extension portion, and the first electrodes are on the same plane.

US Pat. No. 10,510,930

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light-emitting device comprising:a package made of a metal material and defining a recess, the package comprising a side wall defining a side of the recess, wherein an opening of the recess is located at an upper side of the package;
a plurality of light-emitting elements disposed in the recess; and
a cover member disposed so as to close the opening of the recess, the cover member comprising:
a light-transmitting member having a primary surface,
a ceramic member having a loop-shape and having a first surface and a second surface opposite the first surface, the first surface being bonded to the primary surface of the light-transmitting member via a bonding material, and
a metal member having a loop-shape and comprising:
a first portion bonded to the second surface of the ceramic member,
a second portion located outward of the first portion in a plan view and joined to an upper surface of the side wall of the package, and
a third portion located between the first portion and second portion in the plan view, at which the metal member is not bonded to any other member, such that an empty space is located between the third portion of the metal member and the second surface of the ceramic member,
wherein the metal member and the ceramic member are bonded to each other via an intermediate member having a loop-shape interposed therebetween, the intermediate member being made of a metal material and having an outer edge that is located inward of an outer edge of the ceramic member in a plan view.

US Pat. No. 10,510,925

LIGHT-EMITTING DEVICE AND LIGHTING SYSTEM COMPRISING SAME

LG INNOTEK CO., LTD., Se...

1. A light emitting device comprising:a first conductive-type semiconductor layer;
an active layer on the first conductive-type semiconductor layer;
an electron blocking layer on the active layer; and
a second conductive-type semiconductor layer on the electrode blocking layer,
wherein the electron blocking layer comprises an InxAlyGa1-x-yN based superlattice layer (wherein 0?x<1, 0 wherein the InxAlyGa1-x-yN based superlattice layer includes a superlattice structure of an InxAlyGa1-x-yN layer/an InzGa1-zN layer (wherein 0?z?1),
wherein the InxAlyGa1-x-yN based superlattice layer has an indium (In) concentration in a range of 0.01 to 0.03, and
wherein the InxAlyGa1-x-yN based superlattice layer has an aluminum (Al) concentration in a range of 0.15 to 0.2.

US Pat. No. 10,510,923

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...

1. A method of manufacturing a display device, comprising:a first transferring step of transferring a plurality of LEDs disposed on a wafer onto a plurality of donors; and
a second transferring step of transferring the plurality of LEDs transferred onto the plurality of donors onto a display panel,
wherein in the second transferring step, an area where one of the plurality of donors overlaps the display panel partially overlaps an area where the other one of the plurality of donors overlaps the display panel,
wherein a plurality of first LEDs among the plurality of LEDs disposed on the wafer and a plurality of second LEDs among the plurality of LEDs disposed on the wafer are disposed in different rows or different columns on the wafer.

US Pat. No. 10,510,921

GRAPHENE DISPLAY

Shenzhen China Star Optoe...

1. A graphene display, comprising:a first transparent substrate and a second transparent substrate, wherein the first transparent substrate and the second transparent substrate are disposed oppositely;
a first graphene light-emitting unit and a second graphene light-emitting unit, wherein the first graphene light-emitting unit and the second graphene light-emitting unit are disposed in overlapping and located between the first transparent substrate and the second transparent substrate; and
a first insulation layer, a metal shield layer and a second insulation layer, wherein the first insulation layer, the metal shield layer, and the second insulation layer are disposed in overlapping and located between the first graphene light-emitting unit and the second graphene light-emitting unit;
wherein the first graphene light-emitting unit includes a first source electrode pattern and a first drain electrode pattern, the first source electrode pattern and the first drain electrode pattern are disposed on the first transparent substrate and disposed separately with each other, a first graphene light-emitting pattern electrically connected with the first source electrode pattern and the first drain electrode pattern and located between the first source electrode pattern and the first drain electrode pattern, a third insulation layer set on and covering the first graphene light-emitting pattern, and a first gate electrode pattern disposed at a side of the third insulation layer away from the first transparent substrate;
wherein the second graphene light-emitting unit includes a second source electrode pattern and a second drain electrode pattern, the second source electrode pattern and the second drain electrode pattern are disposed on the second transparent substrate and disposed separately with each other, a second graphene light-emitting pattern electrically connected with the second source electrode pattern and the second drain electrode pattern and located between the second source electrode pattern and the second drain electrode pattern, a fourth insulation layer set on and covering the second graphene light-emitting pattern, and a second gate electrode pattern disposed at a side of the fourth insulation layer away from the second transparent substrate; and
wherein the first insulation layer, the metal shield layer and the second insulation layer are located between the first gate electrode pattern and the second gate electrode pattern.

US Pat. No. 10,510,918

ENDOSCOPE IMAGING MODULE

FUJIKURA LTD., Tokyo (JP...

1. An endoscope comprising:an imaging device chip having a chip connection portion;
a tubular housing tube used in a scope tip portion of an endoscope;
a laminated substrate to which the imaging device chip is fixed, the laminated substrate having a first layer and a second layer provided on the first layer, the laminated substrate having a first substrate connection portion, and a second substrate connection portion, the laminated substrate being capable of bending near the first substrate connection portion and the second substrate connection portion when the laminated substrate is inserted into the housing tube;
a first lead wire connecting the first substrate connection portion and the chip connection portion;
a second lead wire connecting the second substrate connection portion and the chip connection portion;
a flexible and non-conductive resin covering an entirety of the first lead wire and an entirety of the second lead wire, the flexible and non-conductive resin covering the first substrate connection portion, the second substrate connection portion, and the chip connection portion; and
an imaging module comprising the laminated substrate provided with the imaging device chip thereon, the imaging module being inserted into the housing tube,
wherein the first substrate connection portion is provided on the first layer, wherein the second substrate connection portion is provided on the second layer, and wherein the first substrate connection portion and the second substrate connection portion are arranged at different positions along a longitudinal direction of the scope tip portion.

US Pat. No. 10,510,917

PORTABLE ELECTRONIC DEVICE, IMAGE-CAPTURING MODULE THEREOF AND CARRIER ASSEMBLY THEREOF

AZUREWAVE TECHNOLOGIES, I...

1. An image-capturing module, comprising:a circuit substrate having a top surface and a bottom surface;
an image-sensing chip electrically connected to the circuit substrate, wherein the image-sensing chip has an image-sensing area;
at least one electronic component disposed on the bottom surface of the circuit substrate and electrically connected to the circuit substrate;
a dispensing package disposed on the bottom surface of the circuit substrate to cover the at least one electronic component;
a lens assembly including a holder structure disposed on the top surface of the circuit substrate and a lens structure being held by the holder structure and corresponding to the image-sensing area; and
a filter element disposed on the image-sensing chip, and the filter element disposed in a through opening formed between the top surface and the bottom surface of the circuit substrate.

US Pat. No. 10,510,913

LIGHT REDIRECTING FILM USEFUL WITH SOLAR MODULES

3M INNOVATIVE PROPERTIES ...

1. A light redirecting film article comprising a light redirecting film having a length and a width, the length being longer than the width, wherein the light redirecting film defines an X-Y plane, wherein the length of the light redirecting film defines a longitudinal axis in the X direction, the light redirecting film comprising:a base layer;
an ordered arrangement of a plurality of microstructures projecting from the base layer;wherein each of the microstructures projects from the base layer in a Z direction,wherein the microstructures have an elongated shape that extends in the X-Y plane,wherein the elongated shape of each of the microstructures defines a primary axis for each of the microstructures in the X-Y plane;wherein the primary axis of a majority of the microstructures is oblique with respect to the longitudinal axis;wherein the longitudinal axis and the primary axis of at least one microstructure define a bias angle in the X-Y plane; andwherein the bias angle is within the range of 20 to 70 degrees or the range of ?20 to ?70 degrees; anda reflective layer over the microstructures opposite the base layer.

US Pat. No. 10,510,912

IMAGE SENSOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first semiconductor substrate having a pixel region;
a second semiconductor substrate;
a heat sink between the first semiconductor substrate and the second semiconductor substrate;
a thermal via extending through the first semiconductor substrate, wherein a semiconductor material of the first semiconductor substrate extends along a sidewall of the thermal via, and wherein the thermal via is in thermal contact with the heat sink; and
a connector in physical contact with the thermal via, the connector and the heat sink being disposed on opposing sides of the first semiconductor substrate.

US Pat. No. 10,510,911

CONTROL OF SURFACE PROPERTIES BY DEPOSITION OF PARTICLE MONOLAYERS

NANOCLEAR TECHNOLOGIES IN...

1. A method comprising:functionalizing a surface with a monolayer of a first functional group by contacting a first fluid to the surface;
removing an excess quantity of the first fluid once the monolayer of the first functional group is formed on the surface;
functionalizing a first plurality of particles with a second functional group by contacting a second fluid to the first plurality of particles, the second functional group chosen so as to attach to the first functional group;
removing an excess quantity of the second fluid once the second functional group has functionalized the first plurality of particles;
forming a first monolayer of particles on the surface, by contacting the functionalized first plurality of particles to the functionalized surface and attaching the first functional group to the second functional group;
functionalizing the first monolayer of particles with a monolayer of a third functional group by contacting a third fluid to the first monolayer of particles; and
removing an excess quantity of the third fluid once a monolayer of the third functional group is formed on first monolayer of particles,
wherein the particles of the first plurality of particles have lateral dimensions less than 100 micrometers.

US Pat. No. 10,510,910

IMAGE SENSOR WITH AN ABSORPTION ENHANCEMENT SEMICONDUCTOR LAYER

Taiwan Semiconductor Manu...

1. An image sensor comprising:a front-side semiconductor layer, an absorption enhancement semiconductor layer, and a back-side semiconductor layer that are stacked, wherein the absorption enhancement semiconductor layer is stacked between the front-side and back-side semiconductor layers, and wherein the absorption enhancement semiconductor layer has an energy bandgap less than that of the front-side semiconductor layer;
a plurality of protrusions defined by the back-side semiconductor layer; and
a photodetector defined by the front-side semiconductor layer, the absorption enhancement semiconductor layer, and the back-side semiconductor layer.

US Pat. No. 10,510,907

SOLAR PANEL

SUNPOWER CORPORATION, Sa...

1. A solar cell comprising:a silicon semiconductor diode structure having a front surface to be illuminated by light and a back surface;
a front surface metallization pattern comprising a plurality of straight front surface bus bars each having a long axis, the front surface bus bars arranged side-by-side with their long axes parallel and spaced apart from each other in a direction perpendicular to their long axes;
a rear surface metallization pattern comprising a plurality of straight rear surface bus bars each having a long axis, the rear surface bus bars arranged side-by-side with their long axes parallel and spaced apart from each other in a direction perpendicular to their long axes, and
a plurality of scribe lines cut into the back surface of the solar cell, each scribe line cut through a corresponding one of the rear surface bus bars parallel to the long axis of the rear surface bus bar into the silicon semiconductor diode structure;
wherein the long axes of the rear surface bus bars are oriented parallel to the long axes of the front surface bus bars, and each front surface bus bar partially, but not entirely, overlies a corresponding rear surface bus bar to overlap the corresponding rear surface bus bar in a direction perpendicular to the long axes of the front and rear surface bus bars.

US Pat. No. 10,510,906

MOS CAPACITOR, SEMICONDUCTOR FABRICATION METHOD AND MOS CAPACITOR CIRCUIT

TAIWAN SEMICONDUCTOR MANU...

1. A metal-oxide-semiconductor (MOS) capacitor circuit, comprising:a front-end-of-the-line (FEOL) field effect transistor (FET), comprising:
a source region and a drain region positioned in a semiconductor substrate;
a shallow trench isolation (STI) positioned in a first diffusion region only; and
a gate over the semiconductor substrate, the shallow trench isolation (STI) being laterally abutting the gate; and
a biasing circuit for providing bias to the FET;
wherein the source region and the drain region are positioned in the first diffusion region, the first diffusion region is positioned in a second diffusion region having a polarity opposite to a polarity of the first diffusion region; and
wherein the FET operates in an accumulation mode, and the biasing circuit supplies a first supply voltage to the first and second diffusion regions, and supplies a second supply voltage to the gate, wherein subtracting the first supply voltage from the second supply voltage is a negative value.

US Pat. No. 10,510,904

SEMICONDUCTOR DEVICE WITH BACKSIDE N-TYPE LAYER AT ACTIVE REGION/TERMINATION REGION BOUNDARY AND EXTENDING INTO ACTION REGION

Mitsubishi Electric Corpo...

1. A semiconductor device wherein a terminal region is disposed outside an active region, comprising:an n type drift layer having a front surface and a rear surface facing each other;
a p type anode layer formed on the front surface of the n type drift layer in the active region, an end portion of the p type anode layer along a horizontal direction coinciding with an end portion of the of the active region;
an n type buffer layer formed on the rear surface of the n type drift layer;
an n type cathode layer and a p type cathode layer formed side by side on a rear surface of the n type buffer layer;
an n type layer formed on the rear surface of the n type buffer layer in a boundary region between the active region and the terminal region side by side with the n type cathode layer and the p type cathode layer; and
a cathode electrode formed in the active region and forming an ohmic contact with the n type cathode layer and the p type cathode layer, wherein
a region at the front surface directly adjacent to the end portion of the p type anode layer is an n type region,
an extending distance of the n type layer to the active region side with the end portion of the active region as a starting point is represented by WGR1,
WGR1 satisfies 100 ?m?WGR1?500 ?m,
the n type layer is extended to the terminal region side, and
the p type cathode layer is continuously provided in the terminal region and located adjacent to an end portion on the terminal region side of the n type layer.

US Pat. No. 10,510,903

IMPACT IONIZATION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:forming a two-dimensional (2D) material layer over a substrate to form a channel structure;
forming source and drain contacts over the channel structure;
forming a charge-trapping layer with a first thickness over the channel structure to trap charge carriers, the charge-trapping layer comprising a first portion in contact with the source contact and a second portion separate from the first portion and in contact with the drain contact;
forming a gate dielectric layer over the charge-trapping layer; and
forming a gate electrode layer over the gate dielectric layer, wherein prior to forming the gate dielectric layer, removing the second portion of the charge-trapping layer to leave the first portion in contact with the source contact.

US Pat. No. 10,510,902

MEMORY DEVICES AND METHODS OF MANUFACTURE THEREOF

Taiwan Semiconductor Manu...

1. A method of manufacturing a memory device, the method comprising:patterning a substrate to form a first recess and a second recess using a first etching process;
patterning the substrate to form a third recess using a second etching process;
filling the first recess and the second recess with a dielectric material to form a first isolation region and a second isolation region, the first isolation region being interposed between a first region of the substrate and a second region of the substrate, the second isolation region interposed between the second region and a third region of the substrate, wherein the third recess is in the first region;
doping the substrate along sidewalls of the third recess;
doping the substrate in the third region;
forming source/drain regions in the second region;
forming a dielectric layer over the first region, the second region, and the third region; and
forming a conductive layer over the dielectric layer in the first region, the second region, and the third region of the substrate, wherein the conductive layer comprises a plate of a first capacitor in the first region, a gate of a transistor in the second region, and a plate of a second capacitor in the third region.

US Pat. No. 10,510,901

THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A thin film transistor, comprising a gate electrode, an active layer, a source electrode, and a drain electrode, wherein,the source electrode and the drain electrode each include a first conductive layer and a second conductive layer;
the first conductive layer is provided on the active layer and directly contacts the active layer;
in an etching liquid, an etching rate of a material of the first conductive layer is greater than an etching rate of a material of the active layer;
the second conductive layer is provided on a side, facing away from the active layer, of the first conductive layer and does not directly contact the active layer, wherein a conductivity of the second conductive layer is greater than a conductivity of the first conductive layer; and
the material of the first conductive layer comprises one or more of oxygen-doped zinc nitride, silicon-doped zinc oxide, germanium-doped zinc oxide, titanium-doped zinc oxide, hafnium-doped zinc oxide, yttrium-doped zinc oxide, zirconium-doped zinc oxide, and indium-doped cadmium oxide.

US Pat. No. 10,510,900

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate;
a gate line and a data line that are provided on the substrate and are insulated from each other;
a thin film transistor that is connected with the gate line and the data line; and
a pixel electrode that is connected with the thin film transistor,
wherein at least one of the gate line and the data line comprises:
a metal layer; and
a blocking layer that contacts the metal layer, and
wherein the blocking layer is formed of a metal oxide and comprises:
a first metal from a first group including molybdenum (Mo) and tungsten (W);
a second metal from a second group including vanadium (V), niobium (Nb), zirconium (Zr), and tantalum (Ta); and
oxygen (O), and
wherein a content of the second metal is about 3 to 10 wt % with respect to entire content of the blocking layer;
wherein the metal layer comprises a first layer that includes at least one of aluminum (Al) and copper (Cu); and
wherein the metal layer further comprises a second layer that is provided between the substrate and the first layer, and the second layer, the first layer, and the blocking layer are sequentially stacked on the substrate.

US Pat. No. 10,510,899

THIN FILM TRANSISTOR, THIN FILM TRANSISTOR MANUFACTURING METHOD AND LIQUID CRYSTAL DISPLAY PANEL

Wuhan China Star Optoelec...

1. A liquid crystal display panel comprising a thin film transistor, wherein the thin film transistor comprises:a substrate;
a gate layer disposed on the substrate;
an insulating layer covering the gate layer;
a semiconductor layer disposed on the insulating layer;
a conductor layer disposed on the semiconductor layer;
the semiconductor layer having a channel region, the channel region dividing the semiconductor layer into left and right portions, the conductor layer being formed on the left and right portions of the semiconductor layer to form a two-island structure;
a source and drain layer provided on the conductor layer and the insulating layer, and the conductor layer is provided between the source and drain layer and the semiconductor layer;
a conductive spacer disposed on a side surface of the semiconductor layer, wherein the conductive spacer is located at a layer same to the semiconductor layer, and between the semiconductor layer and the source and drain layer, such that the semiconductor layer is not directly contacted with the source and drain layer since the conductor layer and the conductive spacer are between the semiconductor layer and the source and drain layer; and
a passivation layer provided on the insulating layer, the source and drain layer and the semiconductor layer;
wherein the gate layer and the source and drain layer are metallic materials;
the insulating layer and the passivation layer are insulating materials.

US Pat. No. 10,510,897

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A method for manufacturing a semiconductor device, the method comprising:forming one or more dielectric layers on a substrate;
forming a dummy strip over the one or more dielectric layers, the dummy strip having a first portion interposed between a second portion and a third portion;
forming a first spacer on a first sidewall and a second spacer on a second sidewall of the dummy strip;
after forming the first spacer and the second spacer, removing the second portion and the third portion of the dummy strip;
after removing the second portion and the third portion, forming a first insulating structure and a second insulating structure between the first spacer and the second spacer, wherein the third portion of the dummy strip is interposed between the first insulating structure and the second insulating structure;
removing the dummy strip; and
forming a gate structure between the first spacer and the second spacer, wherein the gate structure is interposed between the first insulating structure and the second insulating structure.

US Pat. No. 10,510,896

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:forming an insulating structure over a substrate, wherein the substrate has a semiconductor fin separated from the insulating structure;
depositing a high-K dielectric layer over the semiconductor fin and a sidewall of the insulating structure facing the semiconductor fin;
etching a first portion of the high-K dielectric layer that extends substantially along the sidewall of the insulating structure, wherein a second portion of the high-K dielectric layer remains over the semiconductor fin; and
depositing a gate electrode over the second portion of the high-K dielectric layer.

US Pat. No. 10,510,894

ISOLATION STRUCTURE HAVING DIFFERENT DISTANCES TO ADJACENT FINFET DEVICES

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first FinFET device that includes a plurality of first fin structures that each extend in a first direction in a top view;
a second FinFET device that includes a plurality of second fin structures that each extend in the first direction in the top view, wherein the first FinFET device and the second FinFET device are different types of FinFET devices;
a first epitaxial structure grown on each of the first fin structures;
a second epitaxial structure grown on each of the second fin structures, wherein the first epitaxial structure is smaller than the second epitaxial structure;
a plurality of gate structures that each extend in a second direction in the top view, the second direction being different from the first direction, wherein each of the gate structures partially wraps around the first fin structures and the second fin structures; and
a dielectric structure that is disposed between the first FinFET device and the second FinFET device, wherein the dielectric structure cuts each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device, and wherein the dielectric structure is located closer to the first FinFET device than to the second FinFET device.

US Pat. No. 10,510,890

FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

10. A method for forming a fin-type field effect transistor, comprising:providing a semiconductor substrate;
forming a stop layer embedded within the semiconductor substrate;
etching the semiconductor substrate to form trenches penetrating through the stop layer and to define fins in the semiconductor substrate;
filling insulators in the trenches of the semiconductor substrate;
forming a stack structure over and across the fins and on the insulators;
etching the fins using the stack structure as a mask and using the stop layer as an etching stop layer to form recesses in the fins;
forming strained material portions in the recesses between the insulators and at two opposite sides of the stack structure; and
replacing the stack structure with a gate stack over and across the fins, between the strained material portions and on the insulators.

US Pat. No. 10,510,886

METHOD OF PROVIDING REACTED METAL SOURCE-DRAIN STRESSORS FOR TENSILE CHANNEL STRESS

Samsung Electronics Co., ...

1. A method for providing a source-drain stressor for a semiconductor device channel, the semiconductor device including a source region and a drain region, the method comprising:forming a first recess in the source region and a second recess in the drain region, an insulating layer covering the source and drain regions, the first recess extending through a first portion of the insulating layer above the source region, the second recess extending through a second portion of the insulating layer above the drain region;
providing an intimate mixture layer of materials A and B, a first portion of the intimate mixture layer residing in the first recess, a second portion of the intimate mixture layer residing in the second recess, the first portion of the intimate mixture layer having a first height and a first width, the second portion of the intimate mixture layer having a second height and a second width, the first height divided by the first width being a first aspect ratio greater than three, the second height divided by the second width being a second aspect ratio greater than three, a top surface of the first and second portions of the intimate mixture layer being free;
reacting the intimate mixture layer to form a reacted intimate mixture layer including a compound AxBy, the compound AxBy occupying a volume less than an original volume of a corresponding portion of the intimate mixture layer, the top surface of the first and second portions of the intimate mixture layer being free during at least a portion of the reacting the intimate mixture layer.

US Pat. No. 10,510,885

TRANSISTOR WITH ASYMMETRIC SOURCE/DRAIN OVERLAP

International Business Ma...

1. A method of fabricating an asymmetric field-effect transistor device, comprising:obtaining a structure including a semiconductor substrate having a first portion including a recess extending vertically therein, a second portion lacking a recess, and a channel region between the first and second portions, the recess being formed between a pair of dummy gates and including undercut portions extending beneath the dummy gates;
epitaxially growing an embedded source region within the recess in the first portion of the semiconductor substrate;
epitaxially growing a cladded drain region on the second portion of the semiconductor substrate, wherein the embedded source region and the cladded drain region are grown simultaneously;
depositing a gate dielectric layer over the channel region of the semiconductor substrate, and
forming a metal gate on the gate dielectric layer, wherein forming the metal gate includes replacing at least one of the dummy gates with the metal gate.

US Pat. No. 10,510,882

EMBEDDED JFETS FOR HIGH VOLTAGE APPLICATIONS

Taiwan Semiconductor Manu...

15. A device comprising:a semiconductor substrate; and
a Junction Field-Effect Transistor (JFET) formed at a surface region of the semiconductor substrate, wherein the JFET comprises:
a source region and a drain region of a first conductivity type;
a first conductive feature between the source region and the drain region;
a first plurality of current channels formed of semiconductor regions of a first conductivity type;
a first plurality of well regions of a second conductivity type opposite to the first conductivity type, wherein the first plurality of well regions are electrically connected to the first conductive feature, and are configured to receive voltages of the first conductive feature and to pinch off the first plurality of current channels;
a second current channel having portions lower than the first plurality of well regions;
a second conductive feature, wherein the source region and the first conductive feature are between the second conductive feature and the drain region; and
a second well region of the second conductivity type electrically connected to the second conductive feature, wherein the second well region is configured to receive voltages of the second conductive feature and to pinch off the second current channel.

US Pat. No. 10,510,880

TRENCH POWER MOSFET

Taiwan Semiconductor Manu...

1. A method comprising:forming a trench in a semiconductor region, wherein the semiconductor region is of a first conductivity type;
forming a conductive layer extending into the trench and on an edge of the trench;
forming a first dielectric layer on a bottom and sidewalls of the trench, wherein the first dielectric layer covers the conductive layer;
forming a field plate in the trench and over a bottom portion of the first dielectric layer;
forming a second dielectric layer over the field plate; and
forming a conductive region in the trench and over the second dielectric layer, wherein the conductive region is merged with the conductive layer to form a main gate.

US Pat. No. 10,510,878

SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME

Vanguard International Se...

1. A semiconductor device, comprising:a substrate, comprising trenches;
an isolation oxide layer, disposed in the trenches;
a shield polysilicon, disposed in the trenches and partially surrounded by the isolation oxide layer; and
an inter-poly oxide layer, disposed on the isolation oxide layer and on the shield polysilicon;
wherein the inter-poly oxide layer has a concave top surface; and
a first top surface portion of the isolation oxide layer adjacent to the sidewall of the shield polysilicon has a first curvature, and a second top surface portion of the isolation oxide layer adjacent to a sidewall of one of the trenches has a second curvature, wherein the first curvature is greater than the second curvature.

US Pat. No. 10,510,877

SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a source/drain region over the substrate;
a composite layer over the substrate, wherein the composite layer comprises:
a first sublayer comprising a first material;
a second sublayer comprising a second material stacked on the first sublayer, wherein a bandgap of the second material is larger than a bandgap of the first material; and
a third sublayer comprising the first material, wherein the second sublayer is between the first sublayer and the third sublayer; and
a plug through the composite layer, and electrically connected to the source/drain region, wherein the plug includes a first portion laterally adjoining the first sublayer, a second portion laterally adjoining the second sublayer, and a third portion laterally adjoining the third sublayer, a first width of the first portion and a third width of the third portion is smaller than a second width of the second portion, and the second portion of the plug has a substantially curved sidewall profile.

US Pat. No. 10,510,875

SOURCE AND DRAIN STRUCTURE WITH REDUCED CONTACT RESISTANCE AND ENHANCED MOBILITY

TAIWAN SEMICONDUCTOR MANU...

14. A method, comprising:forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions;
forming a first gate stack on the first fin active region and a second gate stack on the second fin active region;
depositing a dielectric layer on the first and second gate stacks;
performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch;
performing a first epitaxial growth to form a first source/drain feature on the first source/drain region;
performing a second recessing process to a second source/drain region of the second fin active region by a second dry etch;
performing a fin sidewall pull back (FSWPB) process to remove portions of the dielectric layer on the second fin active region; and
performing a second epitaxial growth to form a second source/drain feature on the second source/drain region, wherein the first dry etch recesses the first fin active region to a first depth; the second dry etch recesses the second fin active region to a second depth; and the second depth is less than the first depth.

US Pat. No. 10,510,871

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method, comprising:depositing a first layer on a substrate, the first layer including a first semiconductor material; and
growing a second layer on the first layer, the second layer including a second semiconductor material being different from the first semiconductor material and the first and second layers forming a first stack, wherein the first stack includes a first diffusion interface between the first layer and the second layer, wherein the first diffusion interface has a thickness that is greater than zero and less than or equal to 2 nanometers, wherein the depositing the first layer or the growing the second layer comprises using a first deposition process with a first precursor material, and wherein forming another one of the depositing the first layer or the growing the second layer comprises using a second deposition process with the first precursor material and a second precursor material.

US Pat. No. 10,510,870

TECHNIQUES FOR FORMING DEVICE HAVING ETCH-RESISTANT ISOLATION OXIDE

VARIAN SEMICONDUCTOR EQUI...

1. A method for forming a semiconductor device, comprising:providing a transistor structure, the transistor structure comprising a set of semiconductor fins and a set of gate structures, disposed on the set of semiconductor fins, wherein an isolation layer is disposed between the set of semiconductor fins and between the set of gate structures;
implanting ions into an exposed area of the isolation layer, wherein an altered portion of the isolation layer is formed in the exposed area, wherein an altered region of the set of semiconductor fins is formed in an exposed portion of the set of semiconductor fins; and
performing an epitaxial growth process on the set of semiconductor fins, the performing the epitaxial growth process further comprising performing a wet etch that etches the altered portion of the isolation layer at a first etch rate, and etches an unaltered portion of the isolation layer, not exposed to the ions, at a second etch rate, greater than the first etch rate.

US Pat. No. 10,510,867

FINFETS AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a fin protruding from a substrate;
a gate structure disposed on sidewalls and a top surface of the fin;
a spacer layer on sidewalls of the gate structure;
a source/drain region on the fin adjacent the gate structure;
an etch stop layer on sidewalls of the spacer layer and on the source/drain region, wherein a first portion of the etch stop layer on the sidewall of the spacer layer has a smaller density than a second portion of the etch stop layer on the source/drain region; and
an interlayer dielectric layer (ILD) over the etch stop layer.

US Pat. No. 10,510,866

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a fin structure;
a plurality of gates disposed with respect to the fin structure and comprising a first gate, a second gate, and a third gate, wherein the second gate is disposed between the first gate and the third gate, and a spacing between the first gate and the second gate is smaller than a spacing between the second gate and the third gate; and
wherein a foot portion of the first gate has a concave sidewall facing the second gate.

US Pat. No. 10,510,864

SEMICONDUCTOR DEVICE MANUFACTURING METHOD WITH REDUCED GATE ELECTRODE HEIGHT LOSS AND RELATED DEVICES

Semiconductor Manufacturi...

1. A semiconductor device manufacturing method, comprising:providing a semiconductor structure, wherein the semiconductor structure comprises:
a substrate;
at least one source region on the substrate;
an interlayer dielectric layer covering a portion of the source region, wherein the interlayer dielectric layer has a cavity on the source region; and
a pseudo gate insulation layer at a bottom of the cavity covering a portion of the source region,
wherein providing the semiconductor structure comprises:
providing an initial structure, wherein the initial structure comprises:
the substrate;
the at least one source region on the substrate;
a pseudo gate structure on the source region, wherein the pseudo gate structure comprises the pseudo gate insulation layer on the source region and a pseudo gate electrode on the pseudo gate insulation layer; and
the interlayer dielectric layer around the pseudo gate structure, wherein an upper surface of the interlayer dielectric layer is on a same horizontal level as an upper surface of the pseudo gate electrode; and
forming a barrier layer in the cavity, wherein an upper surface of the barrier layer is lower than a top position of the cavity;
forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion on the semiconductor structure;
removing the barrier layer;
removing the pseudo gate insulation layer to expose a portion of the source region; and
forming a gate structure on the exposed portion of the source region.

US Pat. No. 10,510,861

GASEOUS SPACER AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming a gate stack over a substrate;
depositing a first gate spacer on sidewalls of the gate stack;
epitaxially growing source/drain regions on opposite sides of the gate stack;
depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer, the gaseous spacer being disposed laterally between the source/drain regions and the gate stack; and
after depositing the second gate spacer, planarizing the first gate spacer and the gate stack such that top surfaces of the first gate spacer and the gate stack are level with one another.

US Pat. No. 10,510,860

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:forming a gate structure over a channel layer and an isolation insulating layer;
forming a first sidewall spacer layer on a side surface of the gate structure;
forming a sacrificial layer so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer;
forming a space between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer;
after the first sidewall spacer layer is removed, forming an air gap between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure;
removing the sacrificial layer; and
forming an interlayer dielectric layer.

US Pat. No. 10,510,858

METHOD TO IMPROVE HKMG CONTACT RESISTANCE

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising:a substrate;
a gate structure having a metal gate on the substrate; and
a contact member extending into the metal gate, the contact member including a first region on the metal gate and a second region on the first region, the first region having a cross-sectional size larger than a cross-sectional size of the second region,
wherein the gate structure comprises:
a gate dielectric layer on the substrate;
a first barrier layer on the gate dielectric layer;
a P-type work function layer on the first barrier layer;
a second barrier layer on the P-type work function layer; and
the metal gate on the second barrier layer.

US Pat. No. 10,510,857

THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor comprising:a substrate;
a source electrode on the substrate;
a first insulation pattern on the source electrode;
a drain electrode on the first insulation pattern; and
an active layer with one part on the first insulation pattern;
wherein the drain electrode and the one part of the active layer on the first insulation pattern are in an identical layer; and
wherein the source electrode is sandwiched between the substrate and the first insulation pattern;
wherein an orthographic projection of the first insulation pattern at the substrate is within an orthographic projection of the source electrode at the substrate;
wherein the drain electrode is on a top surface of the first insulation pattern; and the one part of the active layer is on the top surface of the first insulation pattern; wherein the drain electrode and the one part of the active layer on the top surface of the first insulation pattern are in an identical layer; and the top surface of the first insulation pattern is substantially parallel to a top surface of the substrate.

US Pat. No. 10,510,856

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:patterning a photoresist over a semiconductor substrate;
patterning the semiconductor substrate to form a first nanowire using the photoresist as a mask;
depositing a first contact pad in physical contact with both the semiconductor substrate and the first nanowire, the first nanowire extending through the first contact pad, a bottommost surface of the first contact pad being level with a bottommost surface of the first nanowire, the bottommost surface of the first contact pad and the bottommost surface of the first nanowire facing the semiconductor substrate;
forming a gate electrode around a channel region of the first nanowire after the depositing the first contact pad;
forming a first dielectric layer over and in physical contact with the gate electrode, a topmost surface of the first dielectric layer being below a topmost surface of the first nanowire;
forming a second dielectric layer over the first dielectric layer, the second dielectric layer being in physical contact with the gate electrode, a topmost surface of the second dielectric layer being level with the topmost surface of the first nanowire;
forming a second contact pad over the first nanowire; and
prior to the forming the gate electrode, forming a third dielectric layer, the forming the third dielectric layer comprising:
depositing a dielectric material;
performing a chemical mechanical planarization process; and
etching back the dielectric material.

US Pat. No. 10,510,854

SEMICONDUCTOR DEVICE HAVING GATE BODY AND INHIBITOR FILM BETWEEN CONDUCTIVE PRELAYER OVER GATE BODY AND CONDUCTIVE LAYER OVER INHIBITOR FILM

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a gate body over a substrate;
a conductive prelayer over the gate body;
an inhibitor film over the conductive prelayer; and
a conductive layer over the inhibitor film, wherein:
the inhibitor film is between a sidewall of the conductive prelayer and a sidewall of the conductive layer,
the conductive layer has a top portion width and a bottom portion width, and
the top portion width is greater than the bottom portion width.

US Pat. No. 10,510,853

FINFET WITH TWO FINS ON STI

Taiwan Semiconductor Manu...

1. A method of forming a fin field effect transistor (FinFET) device, the method comprising:forming a first fin, the first fin having a top surface, a first sidewall, and a second sidewall, the first sidewall facing a first isolation region and the second sidewall facing a second isolation region;
forming a mask on the top surface of the first fin;
recessing the first isolation region and the second isolation region to expose the first sidewall and the second sidewall;
epitaxially growing a second fin on the first sidewall and a third fin on the second sidewall, wherein
a first sidewall of the second fin contacts the first sidewall of the first fin,
a second sidewall of the second fin faces away from the first fin, the first sidewall of the second fin and the second sidewall of the second fin being on opposing sides of the second fin,
a first sidewall of the third fin contacts the second sidewall of the first fin, and
a second sidewall of the third fin faces away from the first fin, the first sidewall of the third fin and the second sidewall of the third fin being on opposing sides of the second fin;
recessing the first fin to expose the first sidewall of the second fin and the first sidewall of the third fin; and
forming a gate structure along the first sidewall of the second fin and the first sidewall of the third fin.

US Pat. No. 10,510,852

LOW-K FEATURE FORMATION PROCESSES AND STRUCTURES FORMED THEREBY

Taiwan Semiconductor Manu...

1. A method comprising:forming a low-k layer using an Atomic Layer Deposition (ALD) process, the ALD process comprising:
for a cycle, flowing a silicon-carbon source precursor having a chemical structure comprising at least one carbon atom bonded between two silicon atoms and wherein each chemical bond of the two silicon atoms that are not bonded to the at least one carbon atom is bonded to a halogen element, wherein the silicon-carbon source precursor further includes C(SiCl2)2; and
repeating the cycle a number of times.

US Pat. No. 10,510,851

LOW RESISTANCE CONTACT METHOD AND STRUCTURE

Taiwan Semiconductor Manu...

1. A method, comprising:forming an opening in an insulating layer between a first gate and a second gate, the opening exposing a contact area of a source/drain region;
cleaning the opening;
bombarding a bottom of the opening with a first material, thereby causing a chemical reaction between the first material and a top surface of the contact area;
depositing a metal layer in the opening;
depositing a capping layer over the metal layer;
creating a silicide at the top surface of the contact area, the silicide having a first depth, wherein an upper surface of the silicide includes a first concentration of the first material, wherein the first concentration of the first material in the silicide decreases by a first gradient to a second concentration of the first material at a second depth of the silicide, wherein the silicide has the second concentration from the second depth of the silicide to the first depth of the silicide, wherein the second depth is interposed between the top surface of the silicide and the first depth of the silicide;
after creating the silicide, depositing a metal plug in the opening.

US Pat. No. 10,510,850

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:epitaxially manufacturing a first source/drain region over a semiconductor substrate and adjacent to a first spacer over the semiconductor substrate, wherein the source/drain region has a different lattice constant than the semiconductor substrate, the first spacer adjacent to a gate electrode, wherein after the manufacturing the first source/drain region has a first surface facing the semiconductor substrate and a second facing opposite the first surface, the second surface extending from a first side of the first source/drain region to a second side of the first source/drain region opposite the first side, wherein both the first side and the second side face away from an interior of the first source/drain region the second surface being free from the first spacer;
forming an opening exposing the first source/drain region; and
implanting dopants into the first source/drain region and the first spacer after the forming the opening, wherein the implanting the dopants forms a first implantation region within the first spacer.

US Pat. No. 10,510,847

TRANSISTOR WITH SOURCE FIELD PLATES UNDER GATE RUNNER LAYERS

Texas Instruments Incorpo...

1. A device, comprising:a semiconductor substrate having a channel region;
a source contact layer contacting the a surface of the semiconductor substrate;
a gate layer above the channel region;
a source field plate defining an opening for accessing the gate layer; and
a gate runner layer above the source field plate, the gate runner layer accessing the gate layer through the opening.

US Pat. No. 10,510,845

METHOD FOR MANUFACTURING ELECTRODE OF SEMICONDUCTOR DEVICE

SILERGY SEMICONDUCTOR TEC...

17. A method for manufacturing an electrode of a semiconductor device, comprising:forming a first interlayer dielectric layer having a first opening on a first surface of a semiconductor substrate;
forming a first resist mask having a second opening on a surface of said first interlayer dielectric layer by exposure with a light source which provides an ultraviolet light, wherein said first opening and said second opening are connected to form a first stacked opening;
forming a first conductive layer on said first resist mask, wherein said first conductive layer comprises a first portion being located on a surface of said first resist mask and a second portion being located inside said first stacked opening;
removing said first resist mask, wherein said first portion of said first conductive layer is removed together with said first resist mask, and said second portion of said first conductive layer is retained as a first surface electrode;
forming a second interlayer dielectric layer having a third opening on a second surface of said semiconductor substrate, wherein said second surface is opposed to said first surface;
forming a third resist mask having a fourth opening on a surface of said second interlayer dielectric layer, wherein said third opening and said fourth opening are connected to form a second stacked opening;
forming a second conductive layer on said third resist mask, wherein said second conductive layer comprises a first portion being located on a surface of said third resist mask and a second portion being located inside said second stacked opening; and
removing said third resist mask, wherein said first portion of said second conductive layer is removed together with said third resist mask, and said second portion of said second conductive layer is retained as a second surface electrode,
wherein said second portion of said first conductive layer fills a portion of said second opening of said first resist mask.

US Pat. No. 10,510,844

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

Mitsubishi Electric Corpo...

1. A semiconductor device, comprising:a semiconductor substrate;
a first semiconductor layer of a first conductivity type, provided on a first main surface of the semiconductor substrate;
a plurality of first semiconductor regions selectively provided at upper layer parts of the first semiconductor layer, the plurality of first semiconductor regions having a second conductivity type;
a second semiconductor region selectively provided at an upper layer part of each of the first semiconductor regions, the second semiconductor region having a first conductivity type;
a second semiconductor layer provided on a JFET region corresponding to the first semiconductor layer between the first semiconductor regions, and configured to cover at least a part of the JFET region;
a third semiconductor layer provided on the second semiconductor layer;
a gate insulating film provided such that the first semiconductor regions and the third semiconductor layer are covered therewith;
a gate electrode provided on the gate insulating film;
an interlayer insulating film provided such that the gate insulating film and the gate electrode are covered therewith;
a contact hole penetrating through the gate insulating film and the interlayer insulating film, at least the second semiconductor region being exposed to a bottom part thereof;
a first main electrode provided on the interlayer insulating film, and configured to electrically connect to the second semiconductor region via the contact hole; and
a second main electrode provided on a second main surface of the semiconductor substrate,
the first semiconductor layer being configured of a silicon carbide semiconductor having a first band gap,
the second semiconductor layer being configured of a semiconductor having a second band gap being narrower than the first band gap, and
the third semiconductor layer being configured of a semiconductor having a third band gap being narrower than the second band gap.

US Pat. No. 10,510,842

SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS

GREENTHREAD, LLC, Dallas...

1. A semiconductor device, comprising:a substrate of a first doping type at a first doping level having first and second surfaces;
a first active region disposed adjacent the first surface of the substrate with a second doping type opposite in conductivity to the first doping type and within which transistors can be formed;
a second active region separate from the first active region disposed adjacent to the first active region and within which transistors can be formed;
transistors formed in at least one of the first active region or second active region; and
at least a portion of at least one of the first and second active regions having at least one graded dopant concentration to aid carrier movement from the first surface to the second surface of the substrate.

US Pat. No. 10,510,840

GAA FET WITH U-SHAPED CHANNEL

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a channel region, extending along a direction, that has a first U-shaped cross-section, the first U-shaped cross-section having a middle portion, a first extension extending up from a first end of the middle portion, and a second extension extending up from a second end of the middle portion;
a gate dielectric layer completely wrapping around the channel region to form a U-shaped structure having a second U-shaped cross-section that contains the first U-shaped cross-section; and
a gate electrode completely wrapping around the second U-shaped cross-section of the gate dielectric layer, wherein the gate electrode is interposed between the first extension and the second extension.

US Pat. No. 10,510,839

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:receiving a semiconductor substrate;
forming a dielectric layer over the semiconductor substrate;
forming a first semiconductive layer over the dielectric layer;
forming a plurality of dopants in a first portion of the first semiconductive layer over the dielectric layer;
removing a second portion of the first semiconductive layer to form a patterned first semiconductive layer over the dielectric layer, wherein a first sidewall profile of the first portion after the removing the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion; and
using the patterned first semiconductive layer as a mask to pattern the dielectric layer to form a hole in the dielectric layer, wherein a sidewall profile of the hole in the dielectric layer is controlled by the first sidewall profile of the first portion of the patterned first semiconductive layer.

US Pat. No. 10,510,837

SYSTEMS AND METHODS FOR FORMING NANOWIRES USING ANODIC OXIDATION

Taiwan Semiconductor Manu...

1. A structure comprising:a semiconductor substrate;
a protruding structure formed on the semiconductor substrate; and
a plurality of nanowires and one or more nano-vias formed in the protruding structure, the semiconductor substrate including a ridge section that extends under the protruding structure, the plurality of nanowires comprising a first nanowire and a second nanowire, the first nanowire of the plurality of nanowires being disposed closer to a major surface of the semiconductor substrate than the second nanowire of the plurality of nanowires, the second nanowire of the plurality of nanowires having a diameter greater than a diameter of the first nanowire of the plurality of nanowires.

US Pat. No. 10,510,836

GATE TRENCH DEVICE WITH OXYGEN INSERTED SI-LAYERS

Infineon Technologies Aus...

1. A semiconductor device, comprising:a gate trench extending into a Si substrate, the gate trench including a gate electrode and a gate dielectric separating the gate electrode from the Si substrate;
a body region in the Si substrate adjacent the gate trench, the body region including a channel region which extends along a sidewall of the gate trench;
a source region in the Si substrate above the body region;
a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region and a highly doped body contact region at a bottom of the contact trench; and
a diffusion barrier structure extending along at least part of the channel region and disposed between the channel region and the highly doped body contact region, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si.

US Pat. No. 10,510,834

HIGH-VOLTAGE SEMICONDUCTOR DEVICE HAVING A DOPED ISOLATION REGION BETWEEN A LEVEL SHIFT REGION AND A HIGH VOLTAGE REGION

Nuvoton Technology Corpor...

13. A semiconductor device, comprising:a substrate structure, comprising a semiconductor substrate having a first conductive type, wherein the substrate structure comprises:
a high side region;
a low side region separated from the high side region; and
a level shift region and an isolation region disposed between the high side region and the low side region, wherein the level shift region and the high side region are separated from each other by the isolation region;
an epitaxial layer disposed on the semiconductor substrate, wherein the epitaxial layer has a second conductive type different from the first conductive type; and
a doped isolation region, having the first conductive type and located in the isolation region, and the doped isolation region extended from a top surface of the substrate structure to a portion of the substrate structure, wherein the doped isolation region has a width decreased linearly from a top surface of the epitaxial layer to a bottom surface of the epitaxial layer, and wherein a first width of the doped isolation region close to the top surface of the substrate structure is greater than a second width of the doped isolation region close to the bottom surface of the substrate structure in a cross-sectional view,
wherein a first side wall and a second side wall of the doped isolation region near the top surface of the substrate structure are non-parallel with each other.

US Pat. No. 10,510,832

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

23. A semiconductor device comprising:a semiconductor substrate having a drift region of first conductivity type;
a dummy trench portion which is provided from an upper surface of the semiconductor substrate to the drift region and arranged extending in a predetermined extending direction;
a diode mesa portion provided in direct contact with the dummy trench portion in the semiconductor substrate perpendicular to the extending direction;
an accumulation region of first conductivity type which is provided in direct contact with the dummy trench portion and above the drift region in the diode mesa portion and has higher doping concentration than doping concentration of the drift region;
a base region of second conductivity type provided in direct contact with the dummy trench portion and above the accumulation region in the diode mesa portion;
an emitter region of first conductivity type provided between the base region and an upper surface of the semiconductor substrate in the diode mesa portion and has higher doping concentration than doping concentration of the drift region;
a contact region of second conductivity type provided between the base region and an upper surface of the semiconductor substrate in the diode mesa portion; and
an intermediate region of second conductivity type provided adjacent to the dummy trench portion and above the drift region in the diode mesa portion.

US Pat. No. 10,510,829

SECONDARY USE OF ASPECT RATIO TRAPPING TRENCHES AS RESISTOR STRUCTURES

International Business Ma...

1. A method for forming a semiconductor structure comprising:providing a substrate with an insulator pad overlying at least a top portion of the substrate;
forming a plurality of dielectric columns overlying at least one of the substrate and the insulator pad, wherein each dielectric column is separated from another dielectric column to form a corresponding plurality of aspect ratio trapping (ART) trenches, wherein the insulator pad forms a bottom portion of a first ART trench of the plurality of ART trenches, and wherein a portion of the substrate forms a bottom portion of a second ART trench of the plurality of ART trenches;
forming a III-V semiconductor material stack in the second ART trench; and
forming a first resistive region in the first ART trench, wherein the first resistive region is in contact with the insulator pad.

US Pat. No. 10,510,828

CAPACITOR WITH HIGH ASPECT RADIO SILICON CORES

Nano Henry, Inc., San Di...

1. A high aspect ratio capacitor comprising:a single-piece silicon (Si) substrate having a first surface and a second surface;
a plurality of at least three Si cores extending from the substrate first surface, each Si core have a height (CZ) and an equal spacing (SX) between adjacent Si cores by a spacing (SX), with a spacing aspect ratio (aSPACE) of CZ-to-SX of at least 5:1;
a dielectric layer conformally coating the Si cores;
an electrical conductor layer conformally coating the dielectric layer; and
an electrode formed on the substrate second surface, underlying the plurality of Si cores.

US Pat. No. 10,510,823

IMPEDANCE CIRCUIT WITH POLY-RESISTOR

MediaTek Inc., Hsin-Chu ...

1. An amplifier, comprising:a first operational amplifier;
a poly-resistor, having a first terminal, a second terminal, a first control terminal and a second control terminal, wherein the poly-resistor is coupled to an output of the first operational amplifier and wherein the poly-resistor comprises a plurality of sub-poly-resistors coupled in series;
a controller, providing a first control voltage to the first control terminal and a second control voltage to the second control terminal; and
a second operational amplifier that receives an inner voltage from a terminal connected between respective sub-poly resistors of the plurality of sub-poly-resistors,
wherein a resistance between the first terminal and the second terminal of the poly-resistor is set by the first control voltage and the second control voltage;
wherein the second control voltage is different from the first control voltage.

US Pat. No. 10,510,820

DISPLAY DEVICE AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...

1. A display device comprising:a pixel unit in which a plurality of pixel circuits each of which includes a light emitting element and a driving circuit configured to drive the light emitting element are arranged in a matrix form,
wherein, in a diffusion layer in which transistors included in the driving circuits of the pixel circuits are formed, an electricity supply region that is an active area for supplying an electric potential to a well is provided between mutually adjacent ones of the pixel circuits.

US Pat. No. 10,510,818

ORGANIC LIGHT EMITTING DISPLAY DEVICE

SHENZHEN CHINA STAR OPTOE...

1. An organic light emitting display device, comprising:an array substrate, comprising a pixel electrode and a metal connection electrode and an auxiliary electrode located around the pixel electrode, wherein the metal connection electrode is electrically connected to the auxiliary electrode through a recessed hole formed in the array substrate; the recessed hole is located above the auxiliary electrode and forms a first cavity and a second cavity communicating with each other, and the first cavity extends from an edge line of the second cavity away from the pixel electrode in a direction away from the pixel electrode;
a pixel definition layer disposed on the array substrate; wherein the pixel definition layer is respectively provided with corresponding grooves above the recessed hole and the pixel electrode of the array substrate;
an organic light emitting diode (OLED) semiconductor layer disposed on the array substrate and the pixel definition layer; wherein the OLED semiconductor layer further covers the pixel electrode and the metal connection electrode and extends into the first cavity of the recessed hole to achieve electrical connection with the auxiliary electrode; and
a cathode disposed on the OLED semiconductor layer; wherein the cathode further extends into the first cavity of the recessed hole to achieve electrical connection with the auxiliary electrode and is in a discontinuous connection state with the recessed hole as a breakpoint.

US Pat. No. 10,510,817

METHOD FOR MANUFACTURING OLED DISPLAY DEVICE, OLED DISPLAY DEVICE AND OLED DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing an OLED display device, comprising:forming a pixel-defining layer on a substrate to define a plurality of pixel regions, forming an organic film layer in each pixel region, determining at least one area to be compensated in the pixel region according to a surface shape of the organic film layer;
aligning an evaporation source, an opening of a mask and the pixel region, making each opening of the mask respectively correspond to the position of each area to be compensated;
forming an electron function layer in the area to be compensated by evaporation of the evaporation source, wherein the electron function layer is configured to compensate a surface shape of the organic film layer in the pixel region.

US Pat. No. 10,510,815

ACTIVE MATRIX ORGANIC LIGHT EMITTING DIODE BACK PLATE FOR DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing an AMOLED back plate, comprising:forming source and drain electrodes on a substrate having a light shielding layer and a buffer layer covering the light shielding layer formed thereon, by a patterning process, wherein the source and drain electrodes are on the buffer layer;
depositing an active layer film and a gate insulating layer film sequentially, and forming an active layer, a gate insulating layer and a second via hole by a patterning process, wherein the active layer covers at least a part of a s urface of the source and drain electrodes, the surface being at a side of the source and drain electrodes which is farther away from the substrate, and the gate insulating layer is on the active layer; and
forming a gate electrode and a transparent anode sequentially, wherein the transparent anode is arranged in a light emitting area and connected with one of the source and drain electrodes through the second via hole; and the gate electrode is on the gate insulating layer;
wherein the gate electrode is covered by a transparent conducting film, and the gate electrode is in direct contact with the transparent conducting film.

US Pat. No. 10,510,814

OLED DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An OLED display panel, comprising:a substrate;
a plurality of OLED light-emitting devices arranged on a side of the substrate;
a signal routing and a control device correspondingly connected with the OLED light-emitting devices;
an image sensor arranged on the other side or the same side of the substrate; and
a light shielding layer arranged between the image sensor and a film layer where the OLED light-emitting devices are located, the light shielding layer comprising at least one pinhole imaging region;
wherein an orthographic projection position of the pinhole imaging region on the substrate is arranged at a gap position between the OLED light-emitting devices, and is staggered from orthographic projection positions of light shielding parts in the signal routing and the control device on the substrate;
the image sensor is configured to acquire an image formed after an object above the OLED display panel passes through the pinhole imaging region;
the signal routing comprises a data line arranged between the film layer where the OLED light-emitting devices are located and the substrate;
the light shielding layer is arranged between the film layer where the OLED light-emitting devices are located and a film layer where the data line is located; and
the light shielding layer further comprises: a connecting through hole configured to connect a drain electrode in the film layer where the data line is located, or a pattern comprising the drain electrode with an anode in the OLED light-emitting device.

US Pat. No. 10,510,813

TRANSPARENT DISPLAY DEVICE

LG Display Co., Ltd., Se...

12. A transparent display device including a transmissive area and an emissive area comprising:a first display panel including a first pixel including a plurality of subpixels displaying an image and including a plurality of color filters disposed corresponding to the first pixel in the emissive area and extended to the transmissive area;
a second display panel including a second pixel, disposed on the first display panel, vertically overlapping the first display panel at the emissive area and the transmissive area, having a liquid crystal layer disposed only in the transmissive area of the first display panel, and configured to control an amount of light incident into the first display panel; and
a first anti-reflection part disposed on the first display panel and preventing light reflecting back to outside,
wherein the liquid crystal layer of the second display panel vertically overlaps the color filters extended to the transmissive area and does not vertically overlap the color filters in the emissive area, and
wherein the second pixel of the second display panel has the number of subpixels the same as the plurality of subpixels in the first pixel of the first display panel.

US Pat. No. 10,510,810

DISPLAY DEVICE INCLUDING ORGANIC LAYER INCLUDING PIGMENT OR DYE AND METHOD OF MANUFACTURING THEREOF

SAMSUNG DISPLAY CO. LTD.,...

1. A display device, in which a first pixel and a second pixel are defined, the display device comprising:a display panel comprising:
a base substrate; and
a light-emitting element disposed on the base substrate;
a color filter layer disposed over the display panel, wherein the color filter layer comprises a first color filter disposed in the first pixel and a second color filter disposed in the second pixel; and
a plurality of organic layers disposed over the display panel, wherein a plurality of pigments or dyes exhibiting different colors from each other is disposed in each of the plurality of organic layers,
wherein the first pixel displays a first color, and the second pixel displays a second color different from the first color, and
wherein the plurality of organic layers comprises a first organic layer integrally formed over the first pixel and the second pixel.

US Pat. No. 10,510,809

OLED DISPLAY

WUHAN CHINA STAR OPTOELEC...

1. An OLED display, comprising a substrate, a thin film transistor layer formed on the substrate, a blue light OLED formed on the thin film transistor layer, a cover plate located on the blue light OLED and laminated with the substrate and a color conversion layer formed at an inner side of the cover plate;the blue light OLED comprising an anode, a hole injection layer, a hole transporting layer, a blue light emitting layer, an electron transport layer, an electron injection layer and a cathode which are stacked up from bottom to top in order;
the color conversion layer comprising a plurality of red conversion units and green conversion units which are separately located;
blue light emitted by the blue light emitting layer being respectively converted into red light by the red conversion units to emit, converted into green light by the green conversion units to emit and emitted through the cover plate, directly to realize color display;
wherein both materials of the red conversion units and the green conversion units are organic metal halide perovskite materials;
wherein a material of the red conversion units is CH3NH3Pb(I0.9Br0.1)3, and a material of the green conversion units is CH3NH3PbBr3.

US Pat. No. 10,510,808

ORGANIC LIGHT-EMITTING STRUCTURE AND DISPLAY DEVICE

SHANGHAI TIANMA AM-OLED C...

1. An organic light-emitting structure, comprising:a first light-emitting unit,
a second light-emitting unit,
a third light-emitting unit, and
a fourth light-emitting unit,
wherein each of the first light-emitting unit, the second light-emitting unit, the third light-emitting unit, and the fourth light-emitting unit comprises a first electrode, a second electrode, and an organic laminated body placed between the first electrode and the second electrode; one of the first electrode and the second electrode is a translucent electrode; and the organic laminated body comprises a light-emitting layer; and at least one of the first light-emitting unit, the second light-emitting unit, the third light-emitting unit, and the fourth light-emitting unit is a fluorescent light-emitting unit,
wherein an emission wavelength of the first light-emitting unit, an emission wavelength of the second light-emitting unit, an emission wavelength of the third light-emitting unit, and an emission wavelength of the fourth light-emitting unit successively increase,
a thickness of the first light-emitting layer is in a range of 18 nm-22 nm, a thickness of the second light-emitting layer is in a range of 31.5 nm-38.5 nm, a thickness of the third light-emitting layer is in a range of 31.5 nm-38.5 nm, and a thickness of the fourth light-emitting layer is in a range of 36 nm-44 nm,
the organic laminated body further comprises a monochromic hole transmission layer stacked with the light-emitting layer, the light-emitting layer is closer to the translucent electrode than the monochromic hole transmission layer is;
the monochromic hole transmission layer of the first light-emitting unit is a first monochromic hole transmission layer, the monochromic hole transmission layer of the second light-emitting unit is a second monochromic hole transmission layer, the monochromic hole transmission layer of the third light-emitting unit is a third monochromic hole transmission layer, and the monochromic hole transmission layer of the fourth light-emitting unit is a fourth monochromic hole transmission layer;
the first monochromic hole transmission layer, the second monochromic hole transmission layer, the third monochromic hole transmission layer and the fourth monochromic hole transmission layer are made of different electron-resistant materials;
a thickness of the first monochromic hole transmission layer is in a range of 9 nm-11 nm, a thickness of the second monochromic hole transmission layer is in a range of 27 nm-33 nm, a thickness of the third monochromic hole transmission layer is in a range of 45 nm-55 nm, and a thickness of the fourth monochromic hole transmission layer is in a range of 63 nm-77 nm, and
the organic laminated body further comprises a common hole transmission layer, the common hole transmission layer is stacked on one side of the monochromic hole transmission layer away from the light-emitting layer, and the common hole transmission layer and the monochromic hole transmission layer are made of different materials.

US Pat. No. 10,510,806

LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting element comprising:an EL layer between an anode and a cathode,
wherein the EL layer has a structure where a first light-emitting layer, a second light-emitting layer, and a third light-emitting layer are stacked in this order from the anode side,
wherein light emitted from the first light-emitting layer and light emitted from the third light-emitting layer have the same color,
wherein a wavelength of each of the light emitted from the first light-emitting layer and the light emitted from the third light-emitting layer is longer than a wavelength of light emitted from the second light-emitting layer, and
wherein emission spectra of the light emitted from the first light-emitting layer and the light emitted from the third light-emitting layer each have a half width of greater than or equal to 5 nm and less than or equal to 120 nm and a peak wavelength at greater than or equal to 620 nm and less than or equal to 680 nm.

US Pat. No. 10,510,799

ABSORPTION ENHANCEMENT STRUCTURE FOR IMAGE SENSOR

Taiwan Semiconductor Manu...

15. An integrated chip, comprising:a substrate comprising a plurality of sidewalls defining a first protrusion and a second protrusion disposed along a first side of the substrate;
an image sensing element arranged within the substrate; and
wherein the first protrusion comprises a first sidewall having a first flat segment and the second protrusion comprises a second sidewall having a second flat segment, the first flat segment is coupled to the second flat segment by a horizontally extending surface of the substrate that is between the first protrusion and the second protrusion.

US Pat. No. 10,510,797

SEMICONDUCTOR IMAGE SENSOR

TAIWAN SEMICONDUCTOR MANU...

1. A back side illumination (BSI) image sensor comprising:a substrate comprising a front side and a back side opposite to the front side;
a plurality of pixel sensors disposed in the substrate, and each of the pixel sensors comprising a photo-sensing device and a plurality of micro structures disposed over the photo-sensing device on the back side of the substrate;
an isolation structure disposed in the substrate;
a plurality of color filters comprising a side wall disposed over the pixel sensors on the back side of the substrate;
a grid disposed over the backside of the substrate comprising a side wall in contact with the side wall of the color filter; and
a plurality of micro-lenses disposed over the color filter,wherein the micro structures and the photo-sensing device of one of the pixel sensors are isolated from the micro structures and the photo-sensing device of an adjacent pixel sensor by the isolation structure.

US Pat. No. 10,510,792

3DIC SEAL RING STRUCTURE AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate;
a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip comprising a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate;
a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, the first conductive feature having a first width in the plurality of first dielectric layers;
a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip, the first seal ring structure having the first width in the plurality of first dielectric layers, the first seal ring structure being electrically isolated from the first conductive feature, wherein a bottom surface of the first seal ring is disposed in the second semiconductor chip, and wherein a distance between a top surface of the first seal ring and the second semiconductor chip is less than a distance between a top surface of the first substrate and the second semiconductor chip; and
a second seal ring structure extending through the plurality of first dielectric layers, wherein the second seal ring structure is spaced apart from and electrically isolated from the first seal ring structure.

US Pat. No. 10,510,790

HIGH-K DIELECTRIC LINERS IN SHALLOW TRENCH ISOLATIONS

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, the method comprising:forming an opening extending from a top surface of a semiconductor substrate into the semiconductor substrate, the opening being entirely within a p-well of the semiconductor substrate;
depositing a metal oxide layer on sidewalls and a bottom of the opening, the metal oxide layer directly contacting the p-well;
after depositing the metal oxide layer, annealing the metal oxide layer;
after annealing the metal oxide layer, depositing a dielectric material over the metal oxide layer in the opening;
performing a planarization to remove excess portions of the dielectric material; and
forming a photo image sensor completely within the p-well of the semiconductor substrate, wherein the photo image sensor is configured to receive light, and convert the light to an electrical signal, wherein a sidewall of the metal oxide layer extends continuously from a top surface of the semiconductor substrate to a top surface of the dielectric material above the top surface of the semiconductor substrate.

US Pat. No. 10,510,788

SEMICONDUCTOR IMAGE SENSOR

TAIWAN SEMICONDUCTOR MANU...

9. A back side illumination (BSI) image sensor comprising:a substrate;
a pixel sensor; and
a hybrid isolation surrounding the pixel sensor in the substrate, and the hybrid isolation comprising:
a conductive structure;
a dielectric layer covering at least sidewalls of the conductive structure; and
a first insulating structure disposed in the substrate,
wherein the dielectric layer covers sidewalls and a bottom surface of the first insulating structure.