US Pat. No. 10,396,888

METHOD FOR FORWARD END-TO-END BEAMFORMING

VIASAT, INC., Carlsbad, ...

1. A method for end-to-end beamforming using an end-to-end relay, the method comprising:computing forward beam weights for a plurality of end-to-end forward multipath channels that couple a plurality of geographically-distributed access nodes with a user terminal in a forward user beam coverage area via a plurality of transponders of the end-to-end relay, each end-to-end forward multipath channel having multipath induced by the transponders;
generating a plurality of forward uplink signals by applying the forward beam weights to a forward beam signal, such that each forward uplink signal is unique to a respective one of the access nodes;
transmitting each forward uplink signal in a time-synchronized manner by its respective access node;
receiving a respective composite input forward signal by each of the plurality of transponders of the end-to-end relay from the plurality of access nodes, each respective composite input forward signal comprising a superposition of the plurality of forward uplink signals; and
transmitting a respective forward downlink signal corresponding to the respective composite input forward signal by each of the plurality of transponders, such that the forward downlink signals form a forward user beam.

US Pat. No. 10,396,887

CLIENT NODE DEVICE AND METHODS FOR USE THEREWITH

1. A client node device of a distributed antenna system comprising:a first wireless receiver configured to wirelessly receive first channel signals from a host node device of the distributed antenna system, the first channel signals including signals from at least two different communication networks and formatted according to at least two corresponding communication protocols;
an amplifier configured to amplify the first channel signals to generate amplified first channel signals;
a first wireless transmitter configured to wirelessly transmit the amplified first channel signals to an other client node device of the distributed antenna system;
a second wireless transmitter configured to wirelessly communicate free space wireless signals to at least one client device via an antenna, based on an analog signal processing of the amplified first channel signals; and
a channel selection filter configured to select two or more of the amplified first channel signals in a corresponding two or more frequency channels to wirelessly communicate with the at least one client device via the second wireless transmitter utilizing the two or more frequency channels, the channel selection filter operating to select the two or more of the amplified first channel signals in the corresponding two or more frequency channels in accordance with a spatial channel reuse scheme that is based on a physical location of the client node device and a plurality of other client node devices of the distributed antenna system operating in different physical locations, the plurality of other client node devices of the distributed antenna system including the other client node device, the two or more of the amplified first channel signals in the corresponding two or more frequency channels including the signals from the at least two different communication networks and formatted according to the at least two corresponding communication protocols and the channel selection filter operates by passing the two or more of the amplified first channel signals in the corresponding two or more frequency channels while filtering out or attenuating other ones of the amplified first channel signals.

US Pat. No. 10,396,885

DYNAMIC PARTITIONING OF MODULAR PHASED ARRAY ARCHITECTURES FOR MULTIPLE USES

INTEL CORPORATION, Santa...

1. A dynamically configurable modular antenna system comprising:a plurality of antenna modules, each of the antenna modules coupled with one of a plurality of radios and comprising an array of antenna elements coupled to one of a plurality radio frequency (RF) beamforming circuit, the plurality of RF beamforming circuits to adjust phase shifts associated with the antenna elements to generate antenna beams for the antenna modules;
a dynamic configuration unit comprising circuitry to receive an indication of a first usage for a first one of the plurality of antenna modules, and receive an indication of a second usage for a second one of the plurality of antenna modules; and
a main beamforming unit comprising circuitry coupled to the dynamic configuration unit and each of the antenna modules, the main beamforming unit to generate signal adjustments relative to the first one of the plurality of antenna modules to control a first antenna beam associated with the first one of the plurality of antenna modules based at least in part on the first usage, and generate signal adjustments relative to the second one of the plurality of antenna modules such that a second antenna beam associated with the second one of the plurality of antenna modules is generated based at least in part on the second usage, wherein the first usage and the second usage correspond to a first station and a second station, respectively, and
wherein the first one of the plurality of antenna modules to communicate first data with the first station via a first radio of the plurality of radios and utilizing a first orthogonal frequency division multiple access (OFDMA) framing, and the second one of the plurality of antenna modules to communicate second data with the second station via a second radio of the plurality of radios and utilizing a second OFDMA framing, and
wherein the first data and the second data are independent and unique from each other, the first OFDMA framing and the second OFDMA framing are independent from each other, and the first radio and the second radio are independent and unique from each other.

US Pat. No. 10,396,884

TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEIVING DEVICE AND RECEIVING METHOD

SUN PATENT TRUST, New Yo...

1. A transmission device to transmit OFDM symbols, comprising:a frame configuration circuit configured to generate a frame such that the frame includes subframes arranged in a time axis, the subframes each consisting of first to last OFDM symbols arranged in the time axis, one of the first OFDM symbol and the last OFDM symbol being a subframe boundary symbol, the first to last OFDM symbols including a first data symbol and a second data symbol that are provided between the first OFDM symbol and the last OFDM symbol in the time axis; and
a signal generation circuit connected to the frame configuration circuit to generate a transmission signal based on the frame, the transmission signal being transmitted through an antenna, the signal generation circuit comprising a pilot insertion circuit configured to insert pilots in the first to last OFDM symbols such that:
the first data symbol includes a first pilot corresponding to a first subcarrier, and the first data symbol does not include a second pilot corresponding to a second subcarrier;
the second data symbol includes the second pilot, and the second data symbol does not include the first pilot; and
the subframe boundary symbol includes pilots corresponding to the first subcarrier and the second subcarrier respectively.

US Pat. No. 10,396,883

TERRESTRIAL WIRELESS POSITIONING IN LICENSED AND UNLICENSED FREQUENCY BANDS

QUALCOMM Incorporated, S...

1. A method at a location server for positioning a user equipment (UE), comprising:receiving a first propagation time measurement and a first plurality of observed time difference of arrival (OTDOA) reference signal time difference (RSTD) measurements from a first UE at a first time;
receiving a second propagation time measurement and a second plurality of OTDOA RSTD measurements from a second UE at a second time, wherein the first propagation time measurement and the second propagation time measurement are for a same base station;
determining at least one real-time difference between a pair of base stations based on the first propagation time measurement, the second propagation time measurement, the first plurality of OTDOA RSTD measurements, and the second plurality of OTDOA RSTD measurements, wherein the pair of base stations is associated with the first plurality of OTDOA RSTD measurements and the second plurality of OTDOA RSTD measurements;
receiving a third plurality of OTDOA RSTD measurements from a third UE at a third time; and
determining a position of the third UE based at least in part on the at least one real-time difference between the pair of base stations.

US Pat. No. 10,396,882

TERMINAL DEVICE, BASE STATION DEVICE, COMMUNICATION METHOD, AND INTEGRATED CIRCUIT

SHARP KABUSHIKI KAISHA, ...

1. A terminal device comprising:receiving circuitry configured to receive, from a base station device, a bit sequence ; and
decoding circuitry configured to perform a Cyclic Redundancy Check (CRC) for the bit sequence , wherein
the bit sequence is given by:
ck=bk for k=0, 1, 2, . . . , A+7
c=(bk+Xrnti,k?A?8)mod 2 for k=A+8, A+9, A+10, . . . , A+23
is a Radio Network Temporary Identifier (RNTI),
the bk is given by:
bk=ak for k=0, 1, 2, . . . , A+L?1
bk=pk?A for k=A, A+1, A+2, . . . , A+L?1
a bit sequence is downlink control information,
A is a payload size of the downlink control information,
a bit sequence is parity bits for the CRC,
L is a number of the parity bits for the CRC, which is 24,
the decoding circuitry is further configured to detect the downlink control information, and
the receiving circuitry is further configured to perform a reception on a physical downlink shared channel scheduled by the downlink control information.

US Pat. No. 10,396,881

RACH DESIGN FOR BEAMFORMED COMMUNICATIONS

QUALCOMM Incorporated, S...

1. A method of wireless communication by a user equipment (UE), comprising:receiving a message from a base station during a random access channel (RACH) procedure;
determining beam information based on the received message during the RACH procedure; and
transmitting a second message to the base station during the RACH procedure that includes the determined beam information, wherein the message, received during the RACH procedure, comprises a value indicating a request for beam information during the RACH procedure, and wherein the second message is transmitted based on the request for beam information.

US Pat. No. 10,396,880

BEAM-FORMING SELECTION

TELEFONAKTIEBOLAGET LM ER...

1. A beam-forming selection method of a wireless communication access node adapted to establish a wireless communication link to a wireless communication device by beam-formed transmission using a beam-forming alternative selected from a plurality of beam-forming alternatives each corresponding to a direction emanating from the wireless communication access node, the method comprising:simultaneously transmitting two or more beacon signals having different respective predetermined content, wherein each beacon signal is transmitted using a respective one of the plurality of beam-forming alternatives and wherein the predetermined content of each beacon signal is associated with the direction corresponding to the respective beam-forming alternative;
receiving a beacon reading report from the wireless communication device, wherein the beacon reading report is indicative of a reception quality at the wireless communication device of the two or more beacon signals; and
selecting the beam-forming alternative for establishment of the wireless communication link based on the received beacon reading report,
wherein respective contents of the beacon signals are different from one another and are chosen such that a signal distance between the contents of beacon signals increases with increasing separation between the corresponding directions of the beacon signals or increases with decreasing separation between the corresponding directions of the beacon signals.

US Pat. No. 10,396,879

METHOD AND DEVICE IN UE AND BASE STATION USED FOR WIRELESS COMMUNICATION

SHANGHAI LANGBO COMMUNICA...

1. A method in a User Equipment (UE) for wireless communication, comprising:transmitting first information;
wherein the first information comprises at least the former two of {K first-type indexes, K1 first-type indexes, K first-type numerical values}, and the K1 first-type indexes are a subset of the K first-type indexes; the K first-type indexes are used for determining K antenna port groups respectively, and one antenna port group comprises a positive integer number of antenna ports; the UE can receive simultaneously radio signals coming from K1 antenna port groups, the K1 antenna port groups are a subset of the K antenna port groups, and the K1 first-type indexes are used for determining the K1 antenna port groups respectively; the K first-type numerical values are used for determining K channel qualities respectively, and the K channel qualities are one-to-one corresponding to the K antenna port groups; the K1 first-type indexes comprise at least one given first-type index, and a position of the given first-type index in the K first-type indexes is used for determining whether an antenna port group corresponding to the given first-type index belongs to the K1 antenna port groups; and the K is a positive integer greater than 1, and the K1 is a positive integer greater than 1 but not greater than the K.

US Pat. No. 10,396,878

CHANNEL CODING AND INTERLEAVING FOR CONTROL AND USER DATA IN THE PHYSICAL UPLINK SHARED CHANNEL

Intel IP Corporation, Sa...

1. A baseband apparatus for User Equipment (UE) for a cellular network, comprising one or more processors to:encode, for a Physical Uplink Shared Channel (PUSCH) of the cellular wireless network, control information including beam information (BI), the BI information including parameters relating to multi-antenna beamforming by the UE;
interleave the encoded control information with user data, the interleaving including:
writing the control information to a matrix in a time-first mapping order,
writing the user data to the matrix in a frequency-first mapping order, and
reading out the matrix to obtain an interleaved bit stream; and
output the interleaved bit stream for radio frequency processing and transmission via a radio channel.

US Pat. No. 10,396,877

METHOD FOR REPORTING CSI IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR

LG ELECTRONICS INC., Seo...

1. A method of reporting CSI (channel status information) by a user equipment (UE) to a base station in a wireless access system, the method comprising:receiving information on a first CSI process and a second CSI process, each of which contains two or more CSI-RS (channel status information-reference signal) resources, through an upper layer; and
transmitting a first CSI report according to one of the two or more CSI-RS resources contained in the first CSI process and a second CSI report according to one of the two or more CSI-RS resources contained in the second CSI process to the base station,
wherein, when the second CSI process is configured to have an RI value identical to an RI (rank indicator) of the first CSI process, the number of antenna ports of all CSI-RS resources contained in the first CSI process is identical to the number of antenna ports of all CSI-RS resources contained in the second CSI process.

US Pat. No. 10,396,876

PERIODIC CSI REPORTING METHOD PERFORMED BY TERMINAL IN WIRELESS COMMUNICATION SYSTEM AND TERMINAL USING THE METHOD

LG Electronics Inc., Seo...

1. A method for transmitting periodic channel state information (CSI) reporting in a wireless communication system, the method performed by a user equipment (UE) and comprising:selecting a first physical uplink control channel (PUCCH) format; and
transmitting multiple periodic CSI reports and a hybrid automatic repeat request (HARQ) ACK based on the first PUCCH format,
wherein the first PUCCH format is a PUCCH format supporting the multiple periodic CSI reports,
wherein when a number of cells, greater than a predetermined threshold, are configured for the UE by carrier aggregation, the first PUCCH format is selected, and
wherein a cell index of each of the multiple periodic CSI reports is included in a cyclic redundancy check (CRC).

US Pat. No. 10,396,875

CHANNEL STATE INFORMATION FEEDBACK AND RECEIVING METHOD AND DEVICE

CHINA ACADEMY OF TELECOMM...

1. A method for feeding back Channel State Information (CSI) by a User Equipment (UE), the method comprising:determining at least one set of CSI feedback configurations configured by a base station according to an indication of the base station, wherein each set of CSI feedback configurations comprises at least one CSI feedback configuration, and the CSI feedback configuration is a downlink signal configuration for downlink CSI measurement and feedback; and
reporting CSI obtained based upon a first CSI feedback configuration to the base station over a Physical Uplink Control Channel (PUCCH) or a Physical Uplink Shared Channel (PUSCH) upon determining that the CSI needs to be reported, wherein the first CSI feedback configuration is a CSI feedback configuration determined by the UE from a corresponding set of CSI feedback configurations according to most recently reported positional information of the CSI feedback configuration, or positional information of the CSI feedback configuration indicated by the base station.

US Pat. No. 10,396,874

PROACTIVE BEAMFORMING WHILE IN MOTION

AVAGO TECHNOLOGIES INTERN...

1. A device comprising:at least one processor configured to:
establish communication with a first base station via at least one first beam;
monitor motion of the device;
determine that the device is approaching a second base station based at least in part on the monitored motion of the device;
form at least one second beam in a direction of the second base station responsive to determining that the device is approaching the second base station while the communication is established with the first base station via the at least one first beam, the at least one second beam being initially formed with a null projected in a direction of the first base station;
establish communication with the second base station via the at least one second beam concurrently with the communication with the first base station via the at least one first beam, the at least one second beam being separate from the at least one first beam; and
terminate the at least one first beam with the first base station upon establishing communication with the second base station via the at least one second beam.

US Pat. No. 10,396,872

COMMUNICATION SYSTEM, RELAY APPARATUS, RECEIVING APPARATUS, RELAY METHOD, RECEIVING METHOD, RELAY PROGRAM, AND RECEIVING PROGRAM

NIPPON TELEGRAPH AND TELE...

2. A relay apparatus for relaying a first signal from a transmission apparatus to a receiving apparatus, the relay apparatus comprising:a first receiver that receives the first signal transmitted by the transmission apparatus;
a first memory that stores a first quantization code book, the first quantization code book showing, for each code book number, a relationship between a quantization parameter for quantizing a likelihood, and a likelihood quantization bit value showing a quantized likelihood;
at least one memory storing first instructions; and
at least one processor configured to execute the first instructions to:
estimate a reception signal to noise ratio (SNR) value from signal electric power of the received first signal and noise electric power,
select a code book number based on the estimated reception SNR value, the selected code book number corresponding to a reception SNR range, the reception SNR range having a range including the estimated reception SNR value,
perform soft demodulation on the received first signal to detect a likelihood of the received first signal,
refer the first quantization code book to obtain the relationship between the quantization parameter and the likelihood quantization bit value that corresponds to the selected code book number, and
adaptively quantize the detected likelihood by using the obtained relationship to obtain a likelihood quantization bit value for the detected likelihood; and
a transmitter that transmits, to the receiving apparatus, a second signal including the obtained likelihood quantization bit value and the selected code book number.

US Pat. No. 10,396,871

LAYER MAPPING SUBSET RESTRICTION FOR 5G WIRELESS COMMUNICATION SYSTEMS

1. A base station device, comprising:a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
receiving a channel state information report from a user equipment device;
determining a ranking of codeword to layer mapping combinations based on the channel state information report, wherein the codeword to layer mapping combinations indicate to which antenna of a multi-antenna transceiver of the user equipment device to map each codeword of a transmission; and
facilitating transmitting, to the user equipment device, bit map data representative of a bit map comprising the ranking, wherein the bit map comprises a group of rankings of codeword to layer mapping combinations for respective transmission ranks of the transmission, wherein the rankings of the group of rankings are in order of respective spectral efficiencies of the codeword to layer mapping combinations of the ranking.

US Pat. No. 10,396,870

SYSTEM AND METHOD FOR MULTIPLEXING CONTROL AND DATA CHANNELS IN A MULTIPLE INPUT, MULTIPLE OUTPUT COMMUNICATIONS SYSTEM

Futurewei Technologies, I...

8. An apparatus comprising:a non-transitory memory storage comprising instructions; and
a processor in communication with the non-transitory memory storage, wherein the processor executes the instructions to:
determine a rank-dependent offset value of at least one codeword; and
transmit a number of control modulation symbols for each of a plurality of multiple input, multiple output (MIMO) layers for a physical uplink shared channel (PUSCH) transmission in accordance with the rank-dependent offset value of the at least one codeword, the rank-dependent offset value being different for different rank values, the different rank values corresponding to different numbers of MIMO layers, each of the plurality MIMO layers including data and control information.

US Pat. No. 10,396,869

TRANSMISSION TECHNIQUES

British Broadcasting Corp...

1. A method of processing an OFDM MIMO signal in a system having at least two transmitters arranged to transmit an output signal pair, comprising operating a series of transformations on a pair of input signals so that each stream of the output signal pair contains decodable information from both streams of the input signal pair including:a carrier index dependent complex rotation of one signal relative to another using a first complex rotation angle;
a real 2×2 rotation matrix of a signal pair; and
a time dependent complex rotation of one signal relative to another, using a second complex rotation angle, wherein the second complex rotation angle is different from the first complex rotation angle.

US Pat. No. 10,396,868

CODEBOOK GENERATION SYSTEM AND ASSOCIATED METHODS

INTEL CORPORATION, Santa...

1. An apparatus, comprising:a processor circuit arranged to select a precoding matrix for a transmitter of a remote device based on channel conditions of a communication channel for a closed-loop multiple-input and multiple-output (MIMO) orthogonal frequency-division multiple access (OFDMA) system, the precoding matrix dynamically constructed by selection of one or more vectors from stored vector codebook and application of a transform to the one or more vectors by the processor circuit, and the transmitter of the remote device capable of utilizing multiple transmitter antennae (Nt) and multiple spatial channels (Ns).

US Pat. No. 10,396,867

REDUCED-COMPLEXITY DOWNLINK (DL) SIGNAL DEMODULATION USING RECIPROCITY REFERENCE SIGNALS FOR MIMO WIRELESS COMMUNICATION SYSTEMS

National Instruments Corp...

1. A method for reducing complexity of downlink signal demodulation in a multiuser (MU) multiple-input-multiple-output (MIMO) wireless communication system, the method comprising:acquiring, by a base station, uplink (UL) channel state information (CSI) of a MIMO channel between the base station and a user equipment (UE);
deriving, by the base station, downlink (DL) CSI from the UL CSI;
transmitting, by the base station, orthogonal frequency-division multiplexing (OFDM) radio subframes using MIMO pre-equalization based on the DL CSI;
performing, by the UE, downlink reciprocity correction of the OFDM subframes received from the base station using a single complex phasor estimate; and
performing, by the UE, downlink data demodulation of the downlink reciprocity corrected OFDM subframes without performing additional MIMO equalization;
wherein the MU MIMO wireless communication system comprises a plurality of UE;
wherein said using MIMO pre-equalization based on the DL CSI comprises:
precoding, by the base station, each OFDM subframe transmitted by the base station to cause each spatial stream at each UE of the plurality of UE to be seen as an effectively flat channel in frequency;
performing, by the base station, channel reciprocity compensation to attempt to cancel out an effect of non-reciprocal aspects of RF transmit and receive circuitry of the base station and the UE to achieve reciprocity of the uplink channel to the downlink channel; and
wherein the downlink reciprocity correction performed by the UE cancels out the effect of a remaining complex phasor component after the channel reciprocity compensation has been performed by the base station.

US Pat. No. 10,396,866

ADVANCED CSI REPORTING IN ADVANCED WIRELESS COMMUNICATION SYSTEMS

Samsung Electronics Co., ...

1. A user equipment (UE) for a channel state information (CSI) feedback in an advanced communication system, the UE comprising:a transceiver configured to receive, from a base station (BS), CSI configuration information to report a wideband periodic CSI including a pre-coding matrix indicator (PMI), a rank indicator (RI) and a relative power indicator (RPI) based on a codebook, wherein the PMI comprises a first PMI (i1) indicating a plurality of beams and a second PMI (i2) indicating a plurality of weights for linear combination of the plurality of beams, and the RPI indicates a power of weights assigned to the plurality of beams; and
at least one processor configured to determine, based on the CSI configuration information, the RI and the RPI,
wherein the transceiver is further configured to transmit, to the BS over an uplink channel, a first CSI feedback comprising the RI and the RPI in a first periodic reporting instance out of a plurality of periodic reporting instances.

US Pat. No. 10,396,865

SPECTRAL ANALYSIS SIGNAL IDENTIFICATION

CommScope Technologies LL...

9. A measurement receiver, comprising:a receiver having circuitry configured for capturing asynchronous digital signals from two or more ports of a telecommunications system at varying time intervals; and
a processor configured for executing a set of instructions stored in a memory for causing the measurement receiver to:
determine, for each of the asynchronous digital signals, a fast Fourier transform (FFT) spectrum;
determine an average FFT spectrum for each of the two or more ports;
identify a bandwidth of signals present in the average FFT spectrum for each of the two or more ports;
identify MIMO signals present in the bandwidth of signals by:
comparing the bandwidth of signals corresponding to a first port of the two or more ports and the bandwidth of signals corresponding to each of one or more remaining ports of the two or more ports; and
filtering out signals in the bandwidth of signals corresponding to the first port that do not overlap with any of the bandwidth of signals corresponding to any of the one or more remaining ports by more than a predetermined threshold; and
decode the MIMO signals.

US Pat. No. 10,396,864

REFERENCE SIGNALS, MEASUREMENTS, AND DEMODULATION ARCHITECTURES AND METHODS

Intel IP Corporation, Sa...

1. An architecture configured to be employed within one or more user equipments (UEs), the architecture comprising:a communications array configured to receive one or more reference signals of one or more reference signal ports of a subframe, wherein the reference signals are analog beamformed cell-specific reference signals associated with a combination of one or more cells and one or more beams; and
a control component configured to decode the received reference signals, determine radio resource management (RRM) measurements based on the decoded and received one or more reference signals, and perform analog beam tracking and demodulation based on the one or more received reference signals.

US Pat. No. 10,396,863

METHOD FOR DETERMINING PARAMETERS FOR CONFIGURING REGULARIZED ZERO-FORCING PRECODER

MITSUBISHI ELECTRIC CORPO...

1. A method for determining parameters for configuring a regularized zero-forcing precoder T applied to a plurality of n transmitters for transmitting data from the plurality of n transmitters to a plurality of K receivers via a Multiple-Input Multiple Output MIMO transmission channel in a wireless communication system, each transmitter having a quantity MTX of transmit antennas, each receiver having a single receive antenna, K?nMTX=M, characterized in that the method comprises a first phase comprising:obtaining long-term statistics about observations of the MIMO transmission channel as follows, for any and all j-th transmitter among the n transmitters and any and all k-th receiver among the K receivers:
?k(j), which is representative of a ratio between an average power of the MIMO channel from said j-th transmitter to said k-th receiver and an average power of an estimation noise in Channel State Information at Transmitter CSIT obtained, at said j-th transmitter, when estimating the MIMO channel from said j-th transmitter to said k-th receiver;
?k, which is a covariance matrix of the MIMO channel from said plurality of n transmitters toward said k-th receiver; and
?k(j,j?), which is representative of a correlation between qk(j) and qk(j?), wherein qk(j) is a whitened estimation noise, obtained at the j-th transmitter, in the CSIT of the MIMO channel between said j-th transmitter and said k-th receiver, and wherein qk(j?) is a whitened estimation noise, obtained at the j?-th transmitter, in the CSIT of the MIMO channel between said j?-th transmitter and said k-th receiver;
obtaining a power scaling factors vector ?* gathering power scaling factors ?j for any and all j-th transmitter among the n transmitters and meeting a power constraint P, by solving an optimization problem as a function of a signal to noise ratio asymptotic expression SINRko from a standpoint of each receiver as follows:

wherein Ej†?MTX×M is a matrix defined as follows:
Ej†=[0MTX×(j-1)MTX,IMTX,0MTX×(n-j)MTX]
wherein the notation IZ means an identity matrix or sub-matrix of size Z and the notation OZ×W means a null sub-matrix of size Z×W,
wherein the asymptotic expression SINRko of the signal to noise ratio from a standpoint of any k-th receiver among the K receivers is as follows:

wherein Iko is as follows:

wherein ?j,j?o is a function defined as follows:

wherein ?j is a regularization coefficient of the regularized zero-forcing precoder T,
wherein ?j,j?,k (with k=1, . . . , K) is a k-th entry of the vector ?j,j??K×1 such that:
(I?A?j,j?)?=b?j,j?
wherein A?j,j??K×K is a matrix having an entry at each index l, t equal to:

wherein b?j,j? is a vector having an entry at each index l equal to

and wherein ?j,k is defined as follows:

and in that the method further comprises a second phase, performed independently by any and all j-th transmitter of said plurality of n transmitters, comprising:
obtaining an estimation ?(j) of the MIMO transmission channel from a standpoint of each j-th transmitter of said plurality of n transmitters;
configuring the regularized zero-forcing precoder T as follows:

wherein Tj(j) represents the parameters of the regularized zero-forcing precoder T which are applied by said j-th transmitter,
and wherein ?(j) is a power normalization scalar defined as follows:
?(j)=?((?(j))†?(j)+M?jIM)?1(?(j))†?F2
wherein ?j results from execution of the first phase.

US Pat. No. 10,396,862

COOPERATIVE MULTI-NODE MIMO FOR ENHANCED DEVICE TO DEVICE COMMUNICATIONS

Eagle Technology, LLC, M...

1. A method for implementing cooperative multi-node multiple-input multiple-output (MIMO) enhanced device-to-device wireless communications, comprising:decoding in one or more second wireless communication devices a first message included in a first wireless transmission received from a first wireless communication device;
autonomously performing operations by the one or more second wireless communication devices to
selectively determine whether each of the one or more second wireless communication devices should facilitate the communications of the first wireless communication device, and
assist the first wireless communication device with respect to communication of the first message to a third wireless communication device by subsequently transmitting the first message using the one or more second wireless communication devices, when a determination is made that the one or more second wireless communication devices should facilitate the communications of the first wireless communication device;
wherein transmission of the first message by the one or more second wireless communication devices is performed synchronously with at least one retransmission of the first message by the first wireless communication device at a predetermined re-transmission time known to both the first wireless communication device and the one or more second wireless communication devices.

US Pat. No. 10,396,860

SYSTEM AND METHOD FOR AUTOMATED CALIBRATION OF WIRELESS IDENTIFICATION DEVICE LOCATION DETERMINATION EQUIPMENT

The Boeing Company, Chic...

1. A method comprising:receiving, via a plurality of wireless identification receivers at a first time, a first plurality of data transmissions from a plurality of wireless identification tags, wherein each wireless identification receiver of the plurality of wireless identification receivers is associated with a corresponding reception area of a plurality of reception areas, and wherein each reception area of the plurality of reception areas includes a corresponding wireless identification tag of the plurality of wireless identification tags;
responsive to a first wireless identification receiver of the plurality of wireless identification receivers receiving a first data transmission of the first plurality of data transmissions and a second data transmission of the first plurality of data transmissions, adjusting configuration parameters for the first wireless identification receiver to generate updated configuration parameters, wherein the first data transmission corresponds to a first wireless identification tag of the plurality of wireless identification tags, the first wireless identification tag corresponding to a first reception area of the plurality of reception areas, the first reception area corresponding to the first wireless identification receiver, and wherein the second data transmission corresponds to a second wireless identification tag of the plurality of wireless identification tags, the second wireless identification tag corresponding to a second reception area of the plurality of reception areas, the second reception area distinct from the first reception area;
receiving, via the plurality of wireless identification receivers at a second time, a second plurality of data transmissions from the plurality of wireless identification tags, wherein the first wireless identification receiver uses the updated configuration parameters while receiving the second plurality of data transmissions; and
responsive to the first wireless identification receiver receiving only a third data transmission of the second plurality of data transmissions, maintaining the updated configuration parameters, wherein the third data transmission corresponds to the first wireless identification tag.

US Pat. No. 10,396,859

APPARATUS FOR WIRELESSLY TRANSMITTING POWER AFTER CONFIRMING LOCATION OF RECEIVER AND METHOD THEREOF

UNIVERSITY-INDUSTRY COOPE...

1. An apparatus for wirelessly transmitting power, comprising:a beamformer configured to form beams with a first width and sequentially transmit the formed beams with the first width to different spaces that are physically separated from each other and at least partially overlap;
a reception part configured to receive reception power values corresponding to the transmitted beams with the first width;
a calculator configured to calculate a phase of the receiver using a plurality of high reception power values based on magnitudes of the received reception power values; and
an estimator configured to estimate a location of the receiver based on the calculated receiver phase,
wherein wireless power is transmitted to the estimated receiver location.

US Pat. No. 10,396,858

BI-STABLE DISPLAY TAG

Powercast Corporation, P...

1. An apparatus comprising:a display module;
a bi-stable display operatively coupled to the display module, the bi-stable display configured to display a first image at a first time;
a near-field communications (NFC) module including an NFC chip and a first coil operatively coupled to the display module, the NFC chip configured to be wirelessly powered by an external NFC power supply associated with an external NFC device via the first coil;
a harvester operatively coupled to the display module, the harvester including a second coil, the harvester configured to receive wireless power from the external NFC power supply via the second coil; and
a maximum power point tracking (MPPT) circuit operatively coupled to the display module,
the display module configured to receive, at a second time after the first time and in response to a near-field interaction with the external NFC device, (1) power from the external NFC power supply via the second coil and the MPPT circuit based on an output of the MPPT circuit and (2) a first signal from the NFC module indicative of a second image different from the first image, the first signal based on a second signal received by the first coil from the external NFC device,
the bi-stable display configured to display, in response to receiving a third signal indicative of an instruction from the display module, the second image at a third time after the second time.

US Pat. No. 10,396,857

DATA TRANSMISSION

Infineon Technologies AG,...

1. A method for data transmission, the method comprising:conveying electrical power from a first element to a second element via an electrical power supply line that is physically connected between the first element and the second element;
transmitting data from the second element to the first element by modulating a current conveyed via the electrical power supply line,wherein the first element is a chip, wherein the second element and the chip are connected via an communication interface.

US Pat. No. 10,396,856

SEMICONDUCTOR DEVICE

PEZY COMPUTING K.K., Chi...

1. A semiconductor device comprising:a first semiconductor chip that includes a transmission circuit input unit, a transmission circuit unit connected to the transmission circuit input unit, and a transmission unit connected to the transmission circuit unit ; and
a second semiconductor chip that is disposed on or below the first semiconductor chip and includes a reception unit, a reception circuit unit connected to the reception unit, and a reception circuit output unit connected to the reception circuit unit,
wherein the transmission unit and the reception unit communicate with each other in a non-contact manner,
a transmission circuit unit input signal having a predetermined transmission-side potential is input into the transmission circuit unit via the transmission circuit input unit, the transmission circuit unit outputs a transmission circuit unit output signal corresponding to the transmission circuit unit input signal, and the transmission circuit unit output signal is input as a reception circuit unit input signal to the reception circuit unit via the non-contact communication between the transmission unit and the reception unit,
the reception circuit unit outputs a reception circuit unit output signal corresponding to a voltage of the reception circuit unit input signal and having a predetermined reception-side potential, to the reception circuit output unit,
a ratio of the reception-side potential to the transmission-side potential is changed,
the transmission unit is a transmission coil,
the reception unit is a reception coil,
the reception coil is a variable turn number reception coil capable of changing a number of turns,
the reception circuit unit has a reception coil turn number control unit that changes the number of turns of the variable turn number reception coil, and
the reception coil turn number control unit changes the number of turns of the variable turn number reception coil to change the ratio of the reception-side potential to the transmission-side potential.

US Pat. No. 10,396,855

METHOD AND DEVICE FOR CAPACITIVE NEAR-FIELD COMMUNICATION IN MOBILE DEVICES

Semtech Corporation, Cam...

1. A method of transmitting data, including:providing a first mobile device including a first capacitive sensor;
providing a second mobile device including a second capacitive sensor;
reading a proximity value using the second capacitive sensor;
reducing a power level of an antenna of the second mobile device when the proximity value indicates a part of a human body within a proximity of the second mobile device;
disposing the first mobile device adjacent to the second mobile device;
switching a first sensing element of the first capacitive sensor between high impedance and being coupled to a first ground voltage node periodically to transmit a first data from the first mobile device to the second mobile device; and
reading the proximity value using the second capacitive sensor periodically with the first mobile device adjacent to the second mobile device to receive the first data from the first mobile device on the second mobile device.

US Pat. No. 10,396,854

SPUR ISOLATION IN A FIELDBUS NETWORK

Phoenix Contact Developme...

1. A device coupler capable of connecting a plurality of field devices to a network trunk of a two-wire fieldbus network of the type that transmits data signals and power over the two wires, the device coupler comprising:a trunk interface for connecting the device coupler to the network trunk and two or more spur isolation sets connected to the trunk interface in parallel with one another;
each spur isolation set comprising: an isolating element connected to the trunk interface and a set of two or more spur interfaces connected to the isolating element, the spur interfaces being connected in parallel with one another to the isolating element, the isolating element connecting the trunk interface and the spur interfaces together and galvanically isolating the trunk interface from the spur interfaces; and
in each spur isolation set: the isolating element comprises a respective transformer, the transformer comprising a first transformer winding connected to the trunk interface and a second transformer winding connected to the set of spur interfaces.

US Pat. No. 10,396,853

SURFACE WAVE CONVERTER

Telefonaktiebolaget LM Er...

1. A surface wave converter for transmitting electromagnetic surface wave signals via a surface wave conduit, the surface wave converter comprising:an input port configured to receive an input signal;
a plurality of waveguide adapters for mounting along a circumference of the surface wave conduit, wherein the plurality of waveguide adapters are configured to jointly excite a surface wave on the surface wave conduit based on the input signal; and
an interface configured to distribute the input signal received on the input port of the surface wave converter over the plurality of waveguide adapters via respective waveguide adapter ports; and
wherein the plurality of waveguide adapters are configured to electromagnetically match a transition between an electrical signal at the interface and a surface wave on the surface wave conduit.

US Pat. No. 10,396,852

LONG PREAMBLE AND DUTY CYCLE BASED COEXISTENCE MECHANISM FOR POWER LINE COMMUNICATION (PLC) NETWORKS

TEXAS INSTRUMENTS INCORPO...

1. A method for operating a first power line communication (PLC) device configured to transmit data frame on a PLC network in accordance with a first PLC protocol associated with a first PLC technology type, the method comprising:detecting, on a first channel of the PLC network, a first instance of a coexistence preamble sequence that is not followed by a native preamble of the first PLC device, wherein the coexistence preamble sequence includes a coexistence preamble that is common to the first PLC protocol and a second PLC protocol associated with a second PLC technology type that is different from the first PLC technology type, the coexistence preamble sequence includes one or more of the coexistence preambles, and the native preamble of the first PLC device is a preamble in accordance with the first PLC protocol;
in response to detecting the first instance of the coexistence preamble sequence that is not followed by the native preamble of the first PLC device, backing off the first channel of the PLC network for a back-off duration equal to N times a coexistence extended interframe spacing (cEIFS) time period, wherein N is an integer; and
when the back-off duration is reached, transmitting a second instance of the coexistence preamble onto the first channel of the PLC network.

US Pat. No. 10,396,851

EQUALIZATION PROCESSING CIRCUIT, DIGITAL RECEIVER, SIGNAL TRANSMITTING/RECEIVING SYSTEM, EQUALIZATION PROCESSING METHOD, AND DIGITAL RECEIVING METHOD

NEC CORPORATION, Tokyo (...

1. An equalization processing circuit, comprising:frequency domain equalizer configured to perform a frequency domain equalization on an inputted digital signal using an inputted frequency domain equalization coefficient;
time domain equalizer configured to perform a time domain equalization on the inputted digital signal using an inputted time domain equalization coefficient;
waveform distortion detector configured to detect a dynamic waveform distortion and a quasi-static waveform distortion of an equalized digital signal, the waveform distortion detector including a dynamic waveform distortion extractor configured to extract the dynamic waveform distortion from the equalized digital signal and a quasi-static waveform distortion extractor configured to extract the quasi-static waveform distortion from the equalized digital signal;
frequency domain equalization coefficient controller configured to calculate and output the frequency domain equalization coefficient based on the quasi-static waveform distortion extracted; and
time domain equalization coefficient controller configured to calculate and output the time domain equalization coefficient based on the dynamic waveform distortion extracted,
wherein the waveform distortion detector further includes a low frequency signal extractor configured to extract a low frequency signal from the equalized digital signal, and
wherein the quasi-static waveform distortion extractor is further configured to extract the quasi-static waveform distortion from the low frequency signal extracted.

US Pat. No. 10,396,850

MODULAR MICROWAVE BACKHAUL OUTDOOR UNIT

Maxlinear, Inc., Carlsba...

1. A system comprising:an on-chip transceiver operable to process a microwave communication signal to generate a first baseband signal, wherein the microwave communication signal spans multiple discontiguous channels;
auxiliary interface circuitry operable to receive one or more auxiliary signals; and
baseband processing circuitry operable to process the one or more auxiliary signals to generate one or more second baseband signals, wherein the baseband processing circuitry is operable to perform phase shifting and weighted combining of the first baseband signal and the second baseband signal to generate one or more third baseband signals.

US Pat. No. 10,396,849

NON-COHERENT ULTRA-WIDEBAND RECEIVER

Qatar University, Doha (...

1. A method of processing received ultra-wideband signals, comprising the steps of:receiving a non-coherent ultra-wideband signal having a plurality of pulses and a known transmission rate;
estimating a signal-to-noise ratio of the non-coherent ultra-wideband signal;
down-converting the received ultra-wideband signal to a lower frequency;
sampling the down-converted received ultra-wideband signal multiple times at regular time intervals within each of the pulses to obtain a set of time domain samples of voltage amplitude for each of the pulses of the non-coherent ultra-wideband signal;
sorting each of the time domain samples of each of the sets of time domain samples by the amplitude to form sets of sorted time domain samples, assigning a sorting index value to each of the samples according to position of the sample in the sorted set;
for each of the sorted sets, retrieving a secondary index value from a lookup table based on the known transmission rate and the estimated signal-to-noise ratio, the secondary index value corresponding to a number of samples in a sampling period exceeding the threshold value at the known transmission rate and estimated signal-to-noise ratio when a binary one is transmitted;
for each of the sorted sets, selecting a sorted time domain sample of the set of sorted time domain samples, the selected sorted time domain sample having a sorting index value equal to the secondary index value retrieved from the lookup table when the samples are sorted in order of descending magnitude, or a sorting index value equal to the number of samples in the set of sorted time domain samples less the secondary index value when the samples are sorted in order of increasing magnitude;
for each of the sorted sets, comparing the amplitude of the selected sorted time domain sample against a threshold value; and
for each of the sorted sets, outputting a binary value of one if the amplitude of the selected sorted time domain sample is greater than the threshold value, and outputting a binary value of zero if the amplitude of the selected sorted time domain sample is less than or equal to the threshold value.

US Pat. No. 10,396,847

RECEIVER ARCHITECTURE FOR LINEAR MODULATION BASED COMMUNICATION SYSTEMS

1. A Filter Bank Multicarrier frequency spread receiver for decoding a signal, said Filter Bank Multicarrier frequency spread receiver comprising a linear phase rotation module adapted to introduce a linear phase rotation to a time domain signal, a Discrete Fourier Transform unit, and a Finite Impulse Response digital filter, wherein coefficients of said Finite Impulse Response digital filter define a shift of a frequency response of a prototype filter of said Filter Bank Multicarrier frequency spread receiver, and wherein said introduced linear phase rotation is compensated by the frequency shift of said Finite Impulse Response digital filter wherein said frequency shift is equal to a reciprocal of a power of two or modulation sub carrier spacing.

US Pat. No. 10,396,846

ADAPTIVE DECODING OF SPREAD SPECTRUM SIGNALS USING MULTIPLE CORRELATOR PEAKS

Cisco Technology, Inc., ...

1. A method comprising:receiving time-offset, time-overlapping signals each including a pilot code that is the same across the signals, at least some of the signals each further including a user code occupying a time slot time-synchronized to a respective one of the pilot codes;
generating time-offset cross-correlation peaks for respective ones of the pilot codes, each cross-correlation peak indicating a respective one of the time slots;
generating for each of the time slots a respective projection vector including user code projections each indicative of whether a respective user code among known user codes is present;
selectively combining particular ones of the projection vectors into an aggregate projection vector of aggregate user code projections, such that the aggregate projection vector has a signal-to-noise ratio (SNR) greater than the projection vectors individually; and
selecting the user code from among the known user codes based on the aggregate user code projections of the aggregate projection vector.

US Pat. No. 10,396,845

SPLIT MICROWAVE BACKHAUL TRANSCEIVER ARCHITECTURE WITH COAXIAL INTERCONNECT

Maxlinear Asia Singapore ...

1. A communication system, comprising:a conversion module configured to convert a signal between a baseband (BB) and an intermediate frequency (IF);
a radio frequency (RF) phased array front-end module comprising a power divider network, the power divider network comprising a plurality of interpolated RF amplifiers;
a coaxial interconnect configured to connect the conversion module with the RF phased array front-end module; and
a dedicated omnidirectional communication path separate from the RF phased array front-end module,
wherein the conversion module is configured to generate a clock that is applied to a control radio associated with the RF phased array front-end module, wherein a high-temperature failure of the communication system causes the clock to be removed from the control radio and triggers the communication system to power down,
wherein the conversion module is configured to generate a calibration signal that is applied to the RF phased array front-end module via the coaxial interconnect, and
wherein the RF phased array front-end module comprises an active front-end (AFE) configured to reduce a deterioration of a signal associated with the communication over the coaxial interconnect.

US Pat. No. 10,396,844

METHOD AND APPARATUS FOR CONVERTING DC VOLTAGES AT THE TOP OF A TELECOMMUNICATIONS TOWER

CommScope Technologies LL...

1. An integrated power cable, comprising:a power cable having a first end and a second end, where the second end is configured to be on a mounting structure;
wherein the first end is configured to be electrically coupled to a DC power supply;
at least one DC-DC voltage converter having at least one input and at least one output;
wherein the second end is fixedly electrically and mechanically connected to the at least one input;
a first connector fixedly connected mechanically and electrically to the at least one output;
wherein the first connector is configured to be coupled to at least one radio; and
wherein the at least one DC-DC voltage converter is configured to provide lower voltage to the at least one radio having a voltage level lower than the voltage provided by the DC power supply to the at least one DC-DC voltage converter.

US Pat. No. 10,396,842

CASING FOR AN ELECTRONIC DEVICE

ADMIRAL TRADING LIMITED, ...

1. A casing for an electronic device, comprising a frame having:a first electrical port arranged to receive a removable solar panel member, and
a power storage module arranged for storing energy for use by the electrical device;
wherein the power storage module is arranged to receive energy from the solar panel member when the solar panel member is connected to the first electrical port, and the solar panel member comprises:
a body having one or more solar panels mounted thereon, and
an electrical connection portion reversibly connectable with the first electrical port.

US Pat. No. 10,396,841

SWIVEL CASE FOR PHONE

1. A phone case comprising:a case body comprising:
a phone side and a user side;
flexible attachment structure for securing a phone to said phone side;
at least one slot extending through said case body between said phone side and said user side, said at least one slot comprising an arcuate portion which defines a continuous opening with an arc of greater than 90°; and
a strap extending through said at least one slot and slidably movable within said slot whereby the case body can be rotated through an angle of about 90° relative to said strap when said strap is fastened to a user's fingers.

US Pat. No. 10,396,840

HIGH SPEED SHORT REACH INPUT/OUTPUT (I/O)

INTEL CORPORATION, Santa...

1. An apparatus comprising:a plurality of transmitter circuits on a first die;
a plurality of receiver circuits on a second die;
a plurality of conductive lines communicatively coupling the first die to the second die for the plurality of transmitter circuits to transmit data bits in parallel to the plurality of receiver circuits;
a termination circuit comprising a single shared capacitor, a plurality of termination resistors, and a plurality of reception buffers, each termination resistor corresponding to one of the plurality of conductive lines and one of the reception buffers having a first input and a second input and coupled to the single the shared capacitor, wherein each termination resistor corresponding to one of the reception buffers has a first end connected to the first input and a second end connected to the second input of the corresponding reception buffer and the single shared capacitor, wherein the single shared capacitor is to block direct current (DC) power from the parallel transmission of data bits on the conductive lines; and
a parallel coding block to encode data transmitted by the plurality of transmitter circuits via the plurality of conductive lines according to a DC balanced code.

US Pat. No. 10,396,839

ENHANCED RECEIVE SENSITIVITY FOR CONCURRENT COMMUNICATIONS

Intel IP Corporation, Sa...

1. A system using multiple communication technologies for communication comprising:a loopback receiver configured to estimate a receiver input attenuation based on noise from a transmit chain and receiver noise; and generate a noise signal based on the estimated receiver input attenuation; and
a noise remover configured to generate a wanted receive signal from the noise signal of the loopback receiver and a receive signal from a receiver.

US Pat. No. 10,396,837

ELECTRONIC DEVICE INCLUDING ANTENNA

Samsung Electronics Co., ...

1. An electronic device comprising:an antenna including a ground part, a feeding part, and a radiator;
a first switch interposed between the feeding part and the radiator; and
a second switch configured to electrically connect or disconnect one point of a first path to or from the radiator,
wherein a signal supplied through the feeding part is transmitted through the first path, a second path, or a third path that connects the feeding part to the radiator,
wherein the first switch is configured to change a connection state of the second path and the third path, and
wherein the third path includes a variable capacitor.

US Pat. No. 10,396,836

ELECTRONIC CIRCUIT WITH A RINGING SUPPRESSION CIRCUIT, NETWORK, AND METHOD FOR OPERATING THE ELECTRONIC CIRCUIT

Infineon Technologies AG,...

1. An electronic circuit, comprising:a transmitter with a first output configured to be connected to a first signal line of a signal bus, a second output configured to be connected to a second signal line of a signal bus, and an input configured to receive an input signal;
a ringing suppression circuit with a third output configured to be connected to the first signal line, and a fourth output configured to be connected to the second signal line,
wherein the transmitter is configured to operate in one of a first operating state or a second operating state dependent on the input signal,
wherein the ringing suppression circuit is configured to detect a change from the first operating state to the second operating state of the transmitter, and
wherein the ringing suppression circuit is configured to operate in a ringing suppression mode for a predefined first time period in response to detecting a change from the first operating state to the second operating state of the transmitter.

US Pat. No. 10,396,835

SYSTEM AND METHOD FOR REDUCING NOISE FROM TIME DIVISION MULTIPLEXING OF A CELLULAR COMMUNICATIONS TRANSMITTER

Apple Inc., Cupertino, C...

1. A mobile communications device comprising:a plurality of microphones;
energy detector circuits coupled to the plurality of microphones, the energy detector circuits configured to measure total energy in each of a plurality of audio signals received from the plurality of microphones and to measure energy from a repetition frequency of a time division multiplexing, when the mobile communications device is using cellular communication with time-division multiplexing; and
a microphone selection logic circuit configured to
identify one or more of the plurality of audio signals as affected by Time Division Multiple Access (TDMA) noise based on a ratio of the energy from the repetition frequency to the total energy when the mobile communications device is using cellular communication with time-division multiplexing, and
provide a control signal that indicates the audio signals affected by TDMA noise to one or more signal processing subsystems that receive signals from the plurality of microphones.

US Pat. No. 10,396,834

APPARATUS AND METHOD FOR ADAPTIVE COMMON MODE NOISE DECOMPOSITION AND TUNING

Intel Corporation, Santa...

1. An apparatus comprising:a first switch;
a second switch;
a first circuitry comprising a sample-and-hold apparatus which is coupled to the first and second switches, wherein the first and second switches are to couple to first and second outputs of a transmitter, respectively; and
a second circuitry coupled to an output of the first circuitry, wherein the second circuitry comprises an analyzer to receive a common mode signal from the output of the first circuitry.

US Pat. No. 10,396,833

ACTIVE HARMONIC FILTERS FOR INTEGRATED RADIO FREQUENCY AMPLIFIERS

Skyworks Solutions, Inc.,...

1. An active filter connectible to an amplifier for reducing harmonics of a signal being amplified thereby, the active filter comprising:a single port connectible to the amplifier;
a first differential amplifier circuit defining a first negative capacitance at a first predetermined operating frequency range and including a first pair of transistors and a second pair of transistors, each transistor in the first pair being connected to a respective one of the transistors in the second pair to define a corresponding inverting differential circuit segment and a non-inverting differential circuit segment, the inverting differential circuit segment and the non-inverting differential segment being interconnected with one or more passive circuit elements at corresponding circuit junctions, with at least one of the circuit junctions connected to the single port; and
a first tank circuit having a first port connectible to the amplifier and a second port connected to the single port, the first tank circuit together with the first negative capacitance of the first differential amplifier defining a first harmonic trap for reflecting the harmonics of the signal to block upstream passage thereof.

US Pat. No. 10,396,832

FILLING APPARATUS

Tatsuno Corporation, Tok...

1. A filling apparatus comprising a radio transmission section capable of transmitting vehicle information via radio transmission on a filling nozzle, the radio transmission section including an information processor operative to detect noise and filter the detected noise from transmissions made by the radio transmission section.

US Pat. No. 10,396,831

APPARATUS FOR CONVERTING BROAD BAND ELECTROMAGNETIC ENERGY TO NARROW BAND ELECTROMAGNETIC ENERGY

1. An apparatus for converting full spectrum sunlight, broad band, electromagnetic energy from a source to one or more narrow bands of electromagnetic energy, the apparatus comprising: a first device for converting broad band electromagnetic energy from a source, to electricity, the first device having a maximum electrical power output; a second device for converting electricity to one or more narrow bands of electromagnetic energy, having a maximum electrical power input; and a connector for directly connecting together the first device and the second device.

US Pat. No. 10,396,830

FRONT-END SYSTEMS WITH MULTIPLE LOOPBACKS AND A SHARED BACK SWITCH

Skyworks Solutions, Inc.,...

1. A front-end system comprising:an antenna port;
a first transmit port configured to receive a first transmit signal and electrically connected to the antenna port via a first transmit path;
a second transmit port configured to receive a second transmit signal and electrically connected to the antenna port via a second transmit path;
a receive port; and
a shared back switch common to a plurality of loopback paths of the front-end system, including a first loopback path from the first transmit port to the receive port, and a second loopback path from the second transmit port to the receive port.

US Pat. No. 10,396,829

TRANSFORMATION BASED FILTER FOR INTERPOLATION OR DECIMATION

TEXAS INTSTUMENTS INCORPO...

1. An electronic device comprising:an analog-to-digital converter coupled to receive an analog input signal and to provide a digital signal;
a digital down-converter, the digital down-converter comprising:
a digital decimation filter for decimating by M, the digital decimation filter comprising:
a first transformation circuit coupled to perform a first transformation on input values of the digital signal and to provide transformed input values, and
a filter block comprising a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric, the filter block being coupled to receive the transformed input values and to provide final outputs of the digital decimation filter.

US Pat. No. 10,396,828

VIRTUALIZED HARDWARE SUPPORT FOR MOBILE DEVICES

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:obtaining a request, for a physical hardware resource, from a container through a virtual hardware interface of a device hosting the container, wherein the container is supported by a virtualization layer, the request including priority information;
placing the request in a first data structure of a plurality of data structures based at least in part on the priority information, wherein the plurality of data structures are organized according to priority; and
processing the request according to its placement among the plurality of data structures.

US Pat. No. 10,396,827

DATA STORAGE DEVICE

SK hynix Inc., Gyeonggi-...

1. A data storage device comprising:a nonvolatile memory device configured to read and output a plurality of data chunks; and
a data processing block configured to perform decoding on the data chunks,
the data processing block comprising
a sequencer configured to generate a decoding information on the data chunks; and
a core circuit configured to perform normal decoding on a first data chunk among the data chunks based on the decoding information, and perform fast decoding on a second data chunk among the data chunks depending on whether a result of the normal decoding satisfies a fast decoding condition,
wherein the fast decoding requires a shorter execution time than the normal decoding.

US Pat. No. 10,396,826

SOFTWARE DEFINED NETWORK WITH SELECTABLE LOW LATENCY OR HIGH THROUGHPUT MODE

HUAWEI TECHNOLOGIES CO., ...

1. A method comprising:receiving a signal carrying a coded data block comprising a set of systematic code source bits and a set of parity bits of a systematic error correction code, the set of systematic code source bits including a plurality of error detection codewords, each error detection codeword including a set of source bits and a set of error detection bits;
performing a first signal processing on the received signal by:
processing the received signal to produce a set of soft bit decisions, the set of soft bit decisions including soft decisions for the set of systematic code source bits and for the set of parity bits;
performing error correction decoding of the set of soft bit decisions to determine decoded systematic code source bits including decoded source bits and decoded error detection bits for the plurality of error detection codewords;
in parallel with performing the first signal processing, performing a second signal processing on the received signal by:
for each error detection codeword:
processing the received signal to produce a set of hard bit decisions for the error detection codeword, the set of hard bit decisions including a received set of source bits and a received set of error detection bits;
re-encoding the received set of source bits to produce a set of error detection bits;
comparing the received set of error detection bits with the produced set of error detection bits;
determining the received set of source bits is reliable when the received error detection bits are the same as the produced set of error detection bits;
determining the received set of source bits is not reliable when the received error detection bits are not the same as the produced set of error detection bits;
outputting bits by:
outputting the received set of source bits without waiting for a final result of the first signal processing when the received set of source bits is determined to be reliable; and
outputting the decoded source bits after completing the first signal processing when the received set of source bits is determined not to be reliable.

US Pat. No. 10,396,825

MEMORY CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggo-...

1. An operation method of a memory controller, the method comprising:performing a first decoding operation to a message of an internal region included in a codeword received from a semiconductor memory device by using an internal parity; and
performing a second decoding operation to the internal region, to which the first decoding operation is performed, by using an outer parity of an outer region,
wherein the codeword includes the internal region in a matrix form and the outer parity generated by encoding one or more rows of the internal region, and
wherein the performing of the second decoding operation includes:
detecting one or more errors of symbols included in the encoded one or more rows of the internal region, to which the first decoding operation is performed, by using the outer parity of the outer region; and
flipping values of all symbols included in one or more columns, in which the error-detected symbols are included.

US Pat. No. 10,396,824

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

SONY CORPORATION, Tokyo ...

1. A transmitting device for generating a terrestrial digital television broadcast signal, the transmitting device decreasing a signal-to-noise power ratio per symbol for a selected bit error rate of the generated terrestrial digital television broadcast signal and/or expanding reception range of the terrestrial digital television broadcast signal at which the data is decodable by a receiving device for presentation to a user, the transmitting device comprising:circuitry configured to:
receive data to be transmitted in a terrestrial digital television broadcast signal;
perform low density parity check (LDPC) encoding by an LDPC encoder circuit on input bits of the received data according to a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15 to generate an LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the terrestrial digital television broadcast signal;
the LDPC code includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors,
the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,
the information matrix portion is represented by a parity check matrix initial value table, and
the parity check matrix initial value table, having each row indicating positions of elements ‘1’ in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity bits in the encoding, is as follows
3 394 1014 1214 1361 1477 1534 1660 1856 274 2987 2991 3124 3155
59 136 528 781 803 928 1293 1489 1944 2041 2200 2613 2690 2847
155 245 311 621 1114 1269 1281 1783 1995 2047 2672 2803 2885 3014
79 870 974 1326 1449 1531 2077 2317 2467 2627 2811 3083 3101 3132
4 582 660 902 1048 1482 1697 1744 1928 2628 2699 2728 3045 3104
175 395 429 1027 1061 1068 1154 1168 1175 2147 2359 2376 2613 2682
1388 2241 3118 3148
143 506 2067 3148
1594 2217 2705
398 988 2551
1149 2588 2654
678 2844 3115
1508 1547 1954
1199 1267 1710
2589 3163 3207
1 2583 2974
2766 2897 3166
929 1823 2742
1113 3007 3239
1753 2478 3127
0 509 1811
1672 2646 2984
965 1462 3230
3 1077 2917
1183 1316 1662
968 1593 3239
64 1996 2226
1442 2058 3181
513 973 1058
1263 3185 3229
681 1394 3017
419 2853 3217
3 2404 3175
2417 2792 2854
1879 2940 3235
647 1704 3060,
group-wise interleave the LDPC code word in units of bit groups of 360 bits to generate a group-wise interleaved LDPC code word:
wherein, in the group-wise interleaving, when an (i+1)-th bit group from a head of the generated LDPC code word is indicated by a bit group i, a sequence of bit groups 0 to 44 of the generated LDPC code word of 16200 bits is interleaved into a following sequence of bit groups
28, 21 10, 15, 8, 22, 26, 2, 14, 1, 27, 3, 39, 20, 34, 25, 12, 6, 7, 40, 30, 29, 38, 16, 43, 33, 4, 35, 9, 32, 5, 36, 0, 41, 37, 18, 17, 13, 24, 42, 31, 23, 19, 1, and 44;
map the group-wise interleaved LDPC code word to any one of 256 signal points in a modulation scheme in units of 8 bits;
perform interleaving in a time direction by time interleaving the mapped group-wise interleaved LDPC code word; and
transmit the digital television broadcast signal including the time-interleaved mapped group-wise interleaved LDPC code word in units of 8 bits.

US Pat. No. 10,396,823

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

ELECTRONICS AND TELECOMMU...

1. A bit interleaving method, comprising:storing a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15;
generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; and
outputting the interleaved codeword,
wherein the interleaving is performed using the following equation using a permutation order:
Xj=X?(j)0?j where X?(j) is a ?(j)th bit group, Yj is an interleaved j-th bit group, Ngroup is the number of bit groups, and ?(j) is the permutation order for the bit group-based interleaving,
wherein the permutation order corresponds to an interleaving sequence represented by the following interleaving sequence:
{7 11 4 38 19 25 2 43 15 26 18 14 9 29 44 32 0 5 35 10 1 12 6 36 21 33 37 34 3 31 20 16 40 23 41 22 30 39 13 24 17 42 28 8 27}, and
wherein the interleaving sequence is for a case where 64-symbol mapping is employed and the interleaved codeword interleaved by the interleaving sequence distributes burst errors occurring in a physical channel for a transmission signal corresponding to the interleaved codeword, the transmission signal being transmitted over the physical channel to a reception device.

US Pat. No. 10,396,822

TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A television (TV) broadcast signal transmitting apparatus for transmitting TV broadcast data, the apparatus comprising:an encoder configured to encode input bits to generate parity bits based on a low density parity check (LDPC) code, wherein the input bits are based on the TV broadcast data;
an interleaver configured to split a codeword comprising the input bits and the parity bits into bit groups, interleave the bit groups using an interleaving order, write bits of the interleaved bit groups in a plurality of columns, each of the plurality of columns comprising a first part and a second part, and read the written bits from the plurality of columns;
a mapper configured to map the read bits onto constellation points using one of quadrature phase-shift keying (QPSK), 16-quadrature amplitude modulation (QAM), 64-QAM, and 256-QAM; and
a signal generator configured to generate a TV broadcast signal based on the constellation points using orthogonal frequency division multiplexing (OFDM) scheme; and
a transmitter configured to transmit the TV broadcast signal to a receiver.
wherein the interleaving order is obtained based on a code rate of the LDPC code and a code length of the LDPC code,
wherein the code length of the codeword is 16200,
wherein a first bit group of the interleaved bit groups is interleaved in the first part and a second bit group of the interleaved bit groups is interleaved in the second part, and
wherein bits of the first bit group are written only in a single column and bits of the second bit group are divided and written in at least two columns.

US Pat. No. 10,396,821

GENERATING HAMMING WEIGHTS FOR DATA

Seagate Technologies LLC,...

1. A system, comprising:a persistent storage medium; and
a controller operable to soft read a data bit from the persistent storage medium a plurality of times by changing a read voltage level for the data bit with each read, to generate a plurality of soft read bits for the data bit based on the soft reads, to perform a logical operation on the soft read bits, and to generate a Hamming weight for the data bit based on the logical operation, the Hamming weight having fewer bits than the soft read bits, the controller being further operable to correct the data bit with the Hamming weight.

US Pat. No. 10,396,820

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 3/15 CODE RATE

ELECTRONICS AND TELECOMMU...


US Pat. No. 10,396,819

TRANSMITTER APPARATUS AND BIT INTERLEAVING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...


US Pat. No. 10,396,818

TRANSMITTER AND SEGMENTATION METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A transmitting apparatus which is operable in a mode among a plurality of modes, the transmitting apparatus comprising:at least one hardware processor configured to:
segment input bits into one or more blocks based on a size of the input bits and a segmentation reference value, wherein the segmentation reference value is determined by the mode among the plurality of modes,
encode bits of the one or more blocks to generate parity bits based on a low density parity check (LDPC) code having a code rate of the mode and a code length of the mode, and
if the mode is a first mode among the plurality of modes, perform a repetition on at least a portion of the generated parity bits,
if the mode is a second mode among the plurality of modes, skip the repetition, and
calculate a number of parity bits to be punctured and puncture the generated parity bits based on the calculated number, and
a transmitter configured to, if the mode is the first mode, transmit a signal which is generated based on the input bits, the repeated parity bits and remaining parity bits after puncturing, and if the mode is the second mode, transmit a signal which is generated based on the input bits and remaining parity bits after puncturing,
wherein a length of a block is determined based on the segmentation reference value,
wherein the block is one of the one or more blocks,
wherein a first code rate of the first mode and a second code rate of the second mode are equal,
wherein a first code length of the first mode and a second code length of the second mode are same, and
wherein a first segmentation reference value of the first mode is less than a second segmentation reference value of the second mode.

US Pat. No. 10,396,817

PRIORI INFORMATION BASED POST-PROCESSING IN LOW-DENSITY PARITY-CHECK CODE DECODERS

Seagate Technology LLC, ...

1. A memory storage system, comprising:a processor;
memory connected to the processor;
a data storage element connected to the processor; and
non-transitory computer executable program code embodied in the memory, configured to execute on the processor,
wherein the computer executable program code is configured to:
receive a low-density parity-check encoded codeword;
identify one or more variable nodes associated with one or more unsatisfied check nodes in the codeword;
identify all backtracking nodes also belonging to a trapping set of a low-density parity-check code associated with the codeword;
select one of the backtracking nodes based on a probability that each of the one or more variable nodes belongs to a trapping set;
flip a log-likelihood ratio associated with the selected backtracking node;
saturate a magnitude of the log-likelihood ratio associated with the selected backtracking node; and
decode the codeword based on the erased log-likelihood ratios.

US Pat. No. 10,396,815

RFDAC (RF (RADIO FREQUENCY) DAC (DIGITAL-TO-ANALOG CONVERTER)) WITH IMPROVED EFFICIENCY AND OUTPUT POWER

Intel Corporation, Santa...

1. A Digital-to-Analog Converter (DAC), comprising:a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, comprising:
a first DAC stage, wherein the first DAC stage is associated with a first predetermined voltage of the plurality of predetermined voltages, wherein the first DAC stage is configured to receive a digital signal at the first predetermined voltage when the first predetermined voltage is a selected predetermined voltage of the plurality of predetermined voltages, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein the first DAC stage is further configured to generate a first analog signal based on the digital signal received at the first DAC stage when the first predetermined voltage is the selected predetermined voltage; and
a second DAC stage, wherein the second DAC stage is associated with a second predetermined voltage of the plurality of predetermined voltages, wherein the second DAC stage is configured to receive the digital signal at the second predetermined voltage when the second predetermined voltage is the selected predetermined voltage, and wherein the second DAC stage is further configured to generate a second analog signal based on the digital signal received at the second DAC stage when the second predetermined voltage is the selected predetermined voltage.

US Pat. No. 10,396,814

REFERENCE VOLTAGE CONTROL CIRCUIT FOR A TWO-STEP FLASH ANALOG-TO-DIGITAL CONVERTER

TEXAS INSTRUMENTS INCORPO...

1. A flash analog-to-digital converter (ADC), comprising:a zero crossing comparator configured to compare an input analog voltage to a zero reference voltage;
a flash converter comprising a plurality of comparators, wherein each of the plurality of comparators receives a comparator reference voltage and wherein each of the plurality of comparators is configured to compare the input analog voltage to each of the plurality of comparators reference voltages respectively; and
a reference voltage control circuit configured to:
responsive to an output signal from the zero crossing comparator, selectively switch a first reference voltage and a second reference voltage to a first reference node and a second reference node of the flash converter; and
switch the second reference voltage to the first reference node and to the second reference node after receipt by the flash converter of an edge of a clock to cause the flash converter to begin using voltages on the first and second reference nodes and the input analog voltage to generate a flash converter output;
wherein the comparator reference voltage for each comparator in the plurality of comparators is generated based on voltages on the first and second reference nodes.

US Pat. No. 10,396,813

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER

1. Analog-to-digital converter comprising:an input terminal receiving a voltage to be converted, the voltage to be converted being comprised in a conversion range bounded by a first voltage and a second voltage,
an amplifier having a first input terminal and an output terminal forming an analog output terminal of the converter,
a first switch connecting the input terminal of the amplifier and the output terminal of the amplifier,
first, second, third and fourth connections connected in parallel to the input terminal of the amplifier, each connection respectively comprising first, second, third and fourth capacitors having a first terminal connected to the first input terminal of the amplifier,
a second switch connecting a second terminal of the first capacitor to the output terminal of the amplifier,
a first comparator receiving the voltage to be converted and at least one first comparison voltage and configured to perform comparison between the voltage to be converted and the at least one first comparison voltage, and to deliver, on a first digital output, a first digital value on at least a first bit representative of said comparison,
a second comparator receiving a first intermediate voltage and at least a second comparison voltage and configured to perform comparison between the first intermediate voltage and the at least one second comparison voltage, and to deliver, on a second digital output, a second digital value on at least a second bit representative of said comparison,
a voltage source configured to:
apply the voltage to be converted on a second terminal of the first, second, third and fourth capacitors during a first period,
apply a first reference voltage on the second terminal of the second capacitor during a second and third periods, the first reference voltage being representative of the first digital value,
apply the first reference voltage on the second terminal of the third capacitor during the third period,
apply a second reference voltage on the second terminal of the fourth capacitor during the third period, the second reference voltage being representative of the second digital value,
a control circuit configured to calculate, by means of the amplifier and the second switch,
the first intermediate voltage from the voltage to be converted, from the first digital value and from said first voltage and second voltage,
a second intermediate voltage from the voltage to be converted, from the first and second digital values and from said first voltage and second voltage.

US Pat. No. 10,396,811

TEMPERATURE COMPENSATION FOR REFERENCE VOLTAGES IN AN ANALOG-TO-DIGITAL CONVERTER

GLOBALFOUNDRIES Inc., Gr...

1. A circuit comprising:a global reference circuit including a first current mirror having an input and an output, a first super source follower (SSF) circuit having an input coupled to the output of the first current mirror and an output, a first adjustment circuit coupled to the input of the first SSF circuit, and an operational amplifier including a non-inverting input coupled by a feedback loop to the output of the first SSF circuit, an inverting input coupled to a global constant reference voltage, and an output coupled to the input of the first current mirror; and
a plurality of successive approximation register (SAR) local slices, each SAR local slice including a second current mirror having an input coupled to the output of the operational amplifier and an output, a second super source follower (SSF) circuit having an input coupled to the output of the second current mirror, and a second adjustment circuit coupled to the input of the second SSF circuit.

US Pat. No. 10,396,810

QUANTUM INTERFERENCE DEVICE, ATOMIC OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT

Seiko Epson Corporation, ...

1. A quantum interference device comprising:an atomic cell that has alkali metal atoms disposed therewithin;
a light source that emits light for exciting the alkali metal atoms in the atomic cell;
a light detector that detects the light transmitted through the atomic cell;
a package that defines an internal space and houses at least the light source; and
a reflective portion provided between an inner surface of the package and the light source, and that has reflectance to an electromagnetic wave having a wavelength of 4 ?m, wherein the reflectance of the reflective portion is greater than or equal to 50%,
wherein the reflective portion is provided on an outer surface of the light source.

US Pat. No. 10,396,809

ATOMIC CELL, ATOMIC CELL MANUFACTURING METHOD, QUANTUM INTERFERENCE DEVICE, ATOMIC OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE

SEIKO EPSON CORPORATION, ...

1. An atomic cell, which is filled with an alkali metal therein comprising:a first coating layer that coats an inner wall and is formed from a first molecule;
a second coating layer that coats the first coating layer and is formed from a second molecule having a nonpolar group and a functional group that undergoes an elimination reaction with the first molecule; and
a third coating layer that coats the second coating layer and is formed from a nonpolar third molecule,
wherein the first molecule is a metal oxide that does not undergo a substitution reaction with the alkali metal.

US Pat. No. 10,396,808

FRACTIONAL-N PHASE LOCK LOOP APPARATUS AND METHOD USING MULTI-ELEMENT FRACTIONAL DIVIDERS

Board of Regents, The Uni...

1. A frequency synthesizing circuit configured to synthesize an output signal, having an output frequency, from an input reference signal having an input reference frequency, wherein the output frequency has a multiplication factor to the input reference frequency, the frequency synthesizing circuit comprising:a first set of one or more divider circuits, each configured to fractionally divide, in a feedback loop of a phase lock loop circuit, the output signal to generate a first fractional frequency signal, the first fractional frequency signal having a first frequency;
a second set of one or more divider circuits, each configured to fractionally divide, in the feedback loop of the phase lock loop circuit, the output signal to generate a second fractional frequency signal, the second fractional frequency signal having a second frequency, wherein the first frequency is not the same as the second frequency, and wherein the fractional frequency signals of the first and second sets of divider circuits are selectively combined to generate the output signal; and
a selector circuit coupled to each of the plurality of divider circuit, the selector circuit configured to generate one or more modulated selection signals to the first and second sets of divider circuits for selection of the output thereof, wherein the modulated selection signals are scrambled by a dynamic element matching circuit to produce an average distribution of the selection of each of the divider circuits of the first and second sets of divider circuits that are the same.

US Pat. No. 10,396,806

VOLTAGE REGULATOR BASED LOOP FILTER FOR LOOP CIRCUIT AND LOOP FILTERING METHOD

M31 TECHNOLOGY CORPORATIO...

1. A filter circuit, comprising:an amplifier circuit, having a first input terminal, a second input terminal and an output terminal, the amplifier circuit configured to output a first output signal from the output terminal according to a first voltage signal at the first input terminal and a second voltage signal at the second input terminal;
a resistor-capacitor (RC) network, coupled to the first input terminal, the RC network configured to produce the first voltage signal at least in response to a first current signal applied to the first input terminal; and
a first voltage follower, coupled to the output terminal, the first voltage follower configured to receive the first output signal, and generate a first filtered signal in response to the first output signal;
wherein the RC network is further coupled to the first voltage follower, and is configured to produce the first voltage signal in response to the first current signal and the first output signal.

US Pat. No. 10,396,805

WIDE CAPTURE RANGE REFERENCE-LESS FREQUENCY DETECTOR

Futurewei Technologies, I...

1. A frequency detector circuit, comprising:a sampling circuit configured to generate a frequency control signal and a switch circuit control signal based on a frequency difference between a clock signal frequency and input data rate of an input signal; and
a voltage-to-current converter circuit coupled to the sampling circuit and configured to convert the frequency control signal to a frequency control current signal based on the switch circuit control signal, the voltage-to-current converter circuit comprising an output switching circuit with a plurality of transistor pairs, the plurality of transistor pairs controlled by the switch circuit control signal.

US Pat. No. 10,396,804

CIRCUIT DEVICE, PHYSICAL QUANTITY MEASUREMENT DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

Seiko Epson Corporation, ...

1. A circuit device comprising:a first circuit having a first delay locked loop (DLL) circuit having a plurality of delay elements, and adapted to delay a first signal;
a second circuit having a second DLL circuit having a plurality of delay elements, and adapted to delay a second signal; and
a comparator array section, which has a plurality of phase comparators arranged in a matrix, to which a first delayed signal group from the first circuit and a second delayed signal group from the second circuit are input, and which outputs a digital signal corresponding to a time difference in transition timing between the first signal and the second signal, wherein, to output the digital signal, the comparator array section is configured to separately compare each of a plurality of delayed signals in the first delayed signal group to each of a plurality of delayed signals in the second delayed signal group.

US Pat. No. 10,396,803

CLOCK AND DATA RECOVERY OF SUB-RATE DATA

Marvell International Ltd...

1. A clock and data recovery (CDR) circuit comprising:a phase detector configured to detect phase of a data input signal based on a first clock pair and a second clock pair;
a controller configured to adjust a phase of the first clock pair, based on an output of the phase detector, to align an edge of the first clock pair to an edge of the data input signal, the controller further configured to:
1) in a first mode, adjust a phase of the second clock pair, based on an output of the phase detector, to align an edge of the second clock signal to a quadrature phase of the data input signal; and
2) in a second mode corresponding to the data signal being a sub-rate data signal, shift a first clock of the second clock pair toward a quadrature phase of the data signal; and
a masking circuit configured to selectively mask data bits clocked by a second clock of the second clock pair based on an indication of the first and second mode.

US Pat. No. 10,396,802

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:an oscillation circuit including a plurality of logic gates of various driving forces, the plurality of logic gates being formed by transistors and coupled in series;
a frequency counter that measures an oscillation frequency of the oscillation circuit;
a comparator that compares the oscillation frequency of the oscillation circuit measured by the frequency counter with a predetermined value; and
a control circuit that determines degradation of the semiconductor device based on a difference between the predetermined value and the measured oscillation frequency,
wherein the predetermined value is an initial value of the oscillation frequency measured by the frequency counter.

US Pat. No. 10,396,801

FOUR SPIN COUPLERS FOR QUANTUM INFORMATION PROCESSING

Massachusetts Institute o...

1. A circuit for coupling a plurality of flux qubits, the circuit comprising:a spin qubit, magnetically biased at its degeneracy point; and
a flux transformer, magnetically unbiased and inductively coupled to the spin qubit;
wherein when the flux transformer is inductively coupled to the plurality of flux qubits, a measurement of the energy of the system has one of two values depending upon a total parity of the plurality of flux qubits.

US Pat. No. 10,396,800

COMPENSATION MEMORY (CM) FOR POWER APPLICATION

AnDAPT, Inc., San Jose, ...

1. A programmable logic device (PLD) comprising:a memory block including one or more lookup tables storing pre-populated data, one or more registers, and one or more adders;
a programmable fabric; and
a signal wrapper configured to provide signals between the memory block and the programmable fabric,
wherein the memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals,
wherein the pre-populated data stored in the one or more lookup tables is programmably changed by programming the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper, and
wherein the output signals of the memory block are generated by loading the looked-up data to the one or more registers, and sequentially adding the data loaded in the one or more registers using the one or more adders.

US Pat. No. 10,396,799

CIRCUIT FOR AND METHOD OF ACCESSING MEMORY ELEMENTS IN AN INTEGRATED CIRCUIT DEVICE

XILINX, INC., San Jose, ...

1. A circuit for accessing memory elements in an integrated circuit device, the circuit comprising:a first plurality of memory elements;
first line drivers, each of the first line drivers configured to provide a signal to a memory element of the first plurality of memory elements;
first line driver buffers configured to control the signals provided by the first line drivers to the first plurality of memory elements, wherein each line driver buffer of the first line driver buffers is configured to receive power, and each line driver of the first line drivers drives a plurality of line driver buffers of the first line driver buffers;
wherein, for each line driver of the first line drivers, a switch of a first plurality of switches is coupled between the line driver and the plurality of line driver buffers driven by the line driver;
a second plurality of memory elements;
second line drivers, each of the second line drivers configured to provide a signal to a memory element of the second plurality of memory elements;
second line driver buffers configured to control the signals provided by the second line drivers to the second plurality of memory elements, wherein each line driver buffer of the second line driver buffers is configured to receive power, and each line driver of the second line drivers drives a plurality of line driver buffers of the second line driver buffers;
wherein, for each line driver of the second line drivers, a switch of a second plurality of switches is coupled between the line driver and the plurality of line driver buffers driven by the line driver;
wherein power provided to the first line driver buffers is disabled during a configuration of the second memory cells; and
wherein power provided to the second line driver buffers is disabled during a configuration of the first memory cells.

US Pat. No. 10,396,798

RECONFIGURABLE CIRCUIT

NEC CORPORATION, Tokyo (...

9. A reconfigurable circuit comprising:first and second wires; and
two or more paths that are active at different times and that are configured to couple said first wire to said second wire,
wherein each path includes:
a first non-volatile resistive switch, whose first terminal is connected to said first wire;
a first transistor whose drain terminal is connected to a second terminal of said first non-volatile resistive switch;
a second transistor whose source terminal is connected to a second terminal of said first non-volatile resistive switch;
a second non-volatile resistive switch whose first terminal is connected to a drain terminal of said second transistor and whose second terminal is connected to said second wire; and
a 2-input AND circuit whose output is connected to a gate terminal of said first transistor,
wherein a time control signal is supplied to both a first data input of said 2-input AND circuit and a gate terminal of said second transistor, and a write control signal is supplied to a second data input of said 2-input AND circuit.

US Pat. No. 10,396,797

RECONFIGURABLE PROCESSOR AND OPERATION METHOD THEREFOR

Samsung Electronics Co., ...

1. A reconfigurable processor comprising:a configurable memory configured to receive a task execution instruction from a control processor;
a first reconfigurable array that includes a first set of function units configured to receive configuration information from the configurable memory based on the received task execution instruction;
a second reconfigurable array that includes a second set of function units configured to receive the configuration information from the configurable memory based on the received task execution instruction; and
an array synchronizer configured to transmit, to the configurable memory, a signal for stopping transmission of the configuration information until the first reconfigurable array and the second reconfigurable array acquire data from an external shared data memory,
wherein the first reconfigurable array executes a task, based on the configuration information, by using the first set of function units in a period of time, and
wherein the second reconfigurable array executes the task, based on the configuration information, by using the second set of function units in the period of time.

US Pat. No. 10,396,796

CIRCUIT, SYSTEM AND METHOD FOR THIN-FILM TRANSISTOR LOGIC GATES

1. A unipolar inverter circuit for thin-film transistor circuits comprising:a driving voltage input;
an input signal input;
a base voltage input;
a first stage comprising a first unipolar inverter circuit connected between the driving voltage input and the base voltage input and driven by an input signal received by the input signal input;
a capacitor coupled to the output of the first stage at a node A; and
a second stage comprising:
a second unipolar inverter circuit connected between the driving voltage input and the base voltage input, wherein the second unipolar inverter circuit comprises a second stage load transistor and a second stage driving transistor, wherein a gate of the second stage load transistor is connected to the capacitor at a node B rather than to the driving voltage input; and
a clamping transistor connected between the driving voltage and the node B for controlling a voltage across the capacitor, wherein the clamping transistor gate is connected to the driving voltage; and
an output provided between the second stage load transistor and the second stage driving transistor,
wherein the capacitor enables charge injection to the gate of the second stage load transistor to allow at least 90% of full voltage swing of the output voltage at the output based on the input signal.

US Pat. No. 10,396,795

BOOSTED HIGH-SPEED LEVEL SHIFTER

Micron Technology, Inc., ...

1. An apparatus, comprising:a level shifter configured to convert an input signal having a first voltage swing from a non-negative voltage to a positive voltage into an output signal having a second voltage swing that is greater than the first voltage swing, the level shifter comprising:
a driver circuit configured to generate a drive signal based at least in part on the input signal, the drive signal having a third voltage swing that is greater than the first voltage swing, wherein the third voltage swing is from a negative voltage to the positive voltage; and
a first pull-up transistor configured to drive the output signal when the input signal is in a first state, wherein the drive signal drives a gate of the first pull-up transistor; and
a second pull-up transistor configured to drive the output signal when the input signal is in a second state, wherein the input signal drives a gate of the second pull-up transistor.

US Pat. No. 10,396,794

CURRENT MODE LOGIC DRIVER WITH LEVEL SHIFTER

TEXAS INSTRUMENTS INCORPO...

1. A driver circuit, comprising:a first termination resistor;
a distributed amplifier comprising a plurality of pairs of input transistors and comprising inductors coupled between each pair of input transistors; and
a distributed current-mode level shifter coupled to the first termination resistor and including:
a first plurality of inductors coupled in series between the first termination resistor and the distributed amplifier; and
a first plurality of capacitive devices, each capacitive device coupled to a power supply node and to a node interconnecting two of the series-coupled inductors.

US Pat. No. 10,396,793

LEVEL SHIFT CIRCUIT

LAPIS Semiconductor Co., ...

1. A level shift circuit comprising:a constant-current generation unit configured to generate a constant current on a basis of a high power supply voltage and a low power supply voltage;
a current mirror unit configured to flow said constant current through a first line and a second line; and
a level shift unit configured to receive a first input signal and a second input signal being inputted, the first input signal being changed in signal level to a high logic having a potential level of said low power supply voltage and a low logic level having a potential level of a ground potential,
the second input signal being a phase-inverted signal of said first input signal,
the level shift unit being configured to produce a first output signal and a second output signal that are acquired by shifting the signal level at said high logic level of said first input signal and said second input signal from said potential level of said low power supply voltage to a potential level of said high power supply voltage,
the level shift unit being further configured to output said first output signal from a second node on said second line and output said second output signal from a first node on said first line, wherein
said constant-current generation unit includes:
a current adjustment transistor to which said low power supply voltage is applied, the current adjustment transistor being configured to vary a value of said constant current depending on a variation in said low power supply voltage;
first to nth transistors (n is 2 or 3) of a first conductivity type that are connected in series to said high power supply voltage; and
at least one resistor element connected between said nth transistor and said current adjustment transistor;
said first to nth transistors constitute an n-stage current mirror circuit with each gate terminal connected to said current mirror unit; and
said current adjustment transistor is a transistor of a second conductivity type opposite in conductivity type to said first conductivity type, and has a source terminal connected to the ground potential and a gate terminal to which said low power supply voltage is applied.

US Pat. No. 10,396,792

BIDIRECTIONAL ANALOG MULTIPLEXER

STMicroelectronics (Greno...

1. A bidirectional switching circuit coupled between an input and an output, wherein the bidirectional switching circuit comprises:a transistor switch circuit controllable in an on state and an off state, and
a control circuit coupled to the input and to the output and that receives a supply voltage and is configured to reduce leakage currents of the transistor switch circuit when in the off state, and further configured to make the transistor switch circuit operate in a bidirectional manner irrespective of voltages present at the corresponding input and output by applying a gate voltage for controlling the transistor switch circuit in the on state, said gate voltage being equal to a sum of a highest of the voltages present at the input and at the output and a threshold voltage of a diode and less than the supply voltage.

US Pat. No. 10,396,791

OUTPUT DRIVER COMPRISING MOS SWITCHES WITH ADJUSTABLE BACK BIASING

1. A hearing instrument comprising:an audio transducer and an output driver for driving the audio transducer, wherein the output driver of the hearing instrument comprises:
a positive supply voltage rail and a negative supply voltage rail;
a first half-bridge driver comprising a first PMOS transistor and a first NMOS transistor connected in series between the positive and the negative supply voltage rails to form a first driver output;
a bias voltage generator configured to provide a first back bias voltage and a second back bias voltage;
a first body terminal connected to a body of the first PMOS transistor for receipt of the first back bias voltage; and
a second body terminal connected to a body of the first NMOS transistor for receipt of the second back bias voltage;
wherein the bias voltage generator is configured to adjust the first back bias voltage, the second back bias voltage, or both, to control on-resistance of the first PMOS transistor and/or on-resistance of the first NMOS transistor.

US Pat. No. 10,396,790

STATE CONTROL OF A DIGITAL LOGIC CIRCUIT WITHIN AN INTEGRATED CIRCUIT DURING LOW POWER MODE

NXP USA, Inc., Austin, T...

1. An integrated circuit, comprising:a digital logic circuit;
a multiplexer (MUX) having a first data input, a second data input, a control input, and an output, wherein the output is coupled to an input of the digital logic circuit, the second data input is coupled to receive a high frequency clock signal;
a very low frequency (VLF) clock configured to provide a VLF clock signal when enabled, wherein the VLF clock signal has a lower frequency than a frequency of the high frequency clock signal; and
a counter coupled to receive the VLF clock signal and configured to toggle an output of the counter upon counting a predetermined number of cycles of the VLF clock signal, wherein the output of the counter is coupled to the first data input of the MUX,
wherein the MUX is configured to provide the first data input as the output of the MUX during a low power mode, and otherwise to provide the second data input as the output of the MUX, and wherein, during interruption of the low power mode, the counter is configured to maintain a same count value until low power mode is re-entered.

US Pat. No. 10,396,789

POWER GATING CONTROL CIRCUIT

SK hynix Inc., Icheon-si...

1. A power gating control circuit comprising:a logic circuit block including logic gates, the logic circuit block configured to cut off power to the logic gates in response to a power down signal, and perform an originally intended function with the logic gates using a fuse signal provided from an external device in a normal mode; and
a transmission control circuit configured to generate the power down signal in response to a standby signal, and block the fuse signal from being applied to the logic circuit block in response to the standby signal.

US Pat. No. 10,396,788

LOW POWER MULTILEVEL DRIVER

KANDOU LABS, S.A., Lausa...

1. An apparatus comprising:a plurality of transmission lines having a length of up to 2 millimeters between first and second chips in a multi-chip package, each transmission line of the plurality of transmission lines connecting a respective multi-level driver of a plurality of multi-level drivers in the first chip to a voltage termination node in the second chip via a respective termination impedance element of a plurality of termination impedance elements and configured to carry a respective symbol of a balanced vector signaling codeword of a vector signaling code, the vector signaling code comprising codewords that have equal symbol values on at least two transmission lines of the plurality of transmission lines; and
each multi-level driver of the plurality of multi-level drivers configured to generate the respective symbol of the balanced vector signaling codeword by driving a line voltage of a respective transmission line of the plurality of transmission lines above or below a termination voltage of the voltage termination node by selectively enabling groups of current sources or current sinks, respectively, that responsively generate current through the respective termination impedance element, the selectively enabled groups of current sources or current sinks having an output impedance that is not matched to a characteristic impedance of the respective transmission line.

US Pat. No. 10,396,786

KEY INPUT APPARATUS

TDK Corporation, Tokyo (...

1. An input apparatus comprising:a moving part capable of moving up and down through a pressing operation;
a first substrate including a first surface, which is positioned on the moving part side, and a second surface, which is opposite to the first surface, wherein the first substrate supports the moving part and is movable up and down along with the moving part;
a second substrate provided between the moving part and the first substrate in the direction of the up-and-down movement of the moving part, wherein the second substrate includes a first surface positioned on the first substrate side and a second surface opposite the first surface;
a magnetic field generation unit;
a magnetic sensor unit, which includes a magnetic detection element that detects a magnetic field generated from the magnetic field generation unit; and
a magnetic unit comprising a magnetic material;
wherein the magnetic sensor unit and the magnetic unit are provided on one of the first surface of the first substrate and the first surface of the second substrate, and the magnetic field generation unit is provided on the other of the first surface of the first substrate and the first surface of the second substrate, opposite to the magnetic unit,
the magnetism sensing direction of the magnetic detection element is a direction roughly orthogonal to the direction of the up-and-down movement of the moving part; and
the magnetic field generation unit is capable of generating a magnetic field in a direction roughly orthogonal to the direction of the up-and-down movement of the moving part and the magnetism sensing direction of the magnetic detection element.

US Pat. No. 10,396,785

REDUCTION OF CAPACITIVE TOUCH SENSE ELECTRODE SAMPLE VALUE CHANGE WHEN ELECTRODE SCAN PERIOD IS CHANGED

NXP USA, Inc., Austin, T...

1. A capacitive sensor system, comprising:an analog-to-digital converter (ADC);
a capacitive sensor device comprising:
a first capacitor comprising a capacitive touch sense electrode coupled to measure capacitance voltages at the capacitive touch sense electrode using a configurable electrode scan rate;
a first supply voltage;
a first switch operable to couple the capacitive touch sense electrode to the first supply voltage during a first mode and the ADC during a second mode;
a second capacitor;
a second supply voltage different than the first supply voltage;
a second switch operable to couple the second capacitor to the second supply voltage during the first mode and to an open circuit during the second mode;
a resistive element including a first terminal coupled between the first capacitor and the first switch, and a second terminal coupled between the second capacitor and the second switch; and
a controller configured to selectively sample capacitance voltage measurements at the capacitive touch sense electrode with the analog-to-digital converter when there is a change in the configurable electrode scan rate by repetitively sampling a first plurality of capacitance voltage measurements from the capacitive touch sense electrode over a plurality of sequential electrode scan cycles and then discarding a predetermined number of the first plurality of capacitance voltage measurements to generate a second plurality of capacitance voltage measurements from the analog-to-digital converter.

US Pat. No. 10,396,784

PRESSURE-SENSITIVE CAPACITIVE MEASUREMENT DEVICE AND METHOD FOR TOUCH-SENSITIVE AND CONTACTLESS INTERFACES

QUICKSTEP TECHNOLOGIES LL...

1. A capacitive measurement device, comprising:a support plate made from a dielectric material, with a resilient material coupled to the support plate and configured for fixing the support plate onto a display referenced to a ground potential,
first active electrodes made from an electrically conductive material, arranged on a first face of said support plate opposite the display and configured to receive a first potential different from the ground potential, wherein each of a plurality of the first active electrodes formed on a central area of the support plate are configurable for individually detecting an approach or contact of one or more objects of interest,
an electronic capacitive measurement amplifier configured for allowing data on the approach or contact of the one or more objects of interest to be obtained by measurements of capacitive coupling with said first active electrodes, and
second active electrodes made from an electrically conductive material, arranged on a second face of said support plate toward the display and configured to receive a second potential, the second active electrodes selectively connectable to said electronic capacitive measurement amplifier so as to allow measurements of one or both of a displacement and deformation of said support plate to be obtained by measurement of capacitive coupling between said second active electrodes and said display,
wherein the electronic capacitive measurement amplifier is configurable for receiving a guard potential at a first input,
wherein the electronic capacitive measurement amplifier is selectively couplable to the first active electrodes at a second input for generating the first potential, or to the second active electrodes at the second input for generating the second potential, and
wherein the first and second potentials are referenced to the guard potential through the electronic capacitive measurement amplifier.

US Pat. No. 10,396,783

OPTICAL MODULE, MANUFACTURING METHOD THEREOF AND ELECTRONIC APPARATUS

ADVANCED SEMICONDUCTOR EN...

1. An optical module, comprising:a substrate;
a lid disposed on a surface of the substrate, the lid defining a first opening, a second opening and a third opening, wherein the second opening is between the first opening and the third opening;
at least one light-emitting component disposed on the surface of the substrate and in the first opening;
at least one first sensor disposed on the surface of the substrate and in the second opening
at least one second sensor disposed on the surface of the substrate and in the third opening;
a first encapsulant disposed in the first opening and covering upper and side surfaces of the at least one light-emitting component, wherein the first encapsulant is separated from a first sidewall of the first opening by a space; and
a third encapsulant disposed in the second opening and covering upper and side surfaces of the at least one first sensor, wherein the third encapsulant contacts a second sidewall of the second opening.

US Pat. No. 10,396,781

HIGH SPEED SWITCHING SOLID STATE RELAY CIRCUIT

QM Power, Inc., Kansas C...

1. A high speed switching circuit, comprising:a bridge rectifier to receive voltage inputs;
an optical isolator to receive a logic input signal and generate an output signal based on the logic input signal;
a field effect transistor (FET) with a source connected to a negative output of the bridge rectifier, a drain connected to a positive output of the bridge rectifier through a load, and a gate driven by the output signal of the optical isolator;
first and second resistors connecting the voltage inputs to the gate of the FET through first and second diodes, wherein the first and second resistors and the first and second diodes limit current flowing to the gate of the FET; and
a Zener diode connected to the gate of the FET to limit voltage to the gate of the FET below a maximum voltage rating of the FET.

US Pat. No. 10,396,780

HIGH FREQUENCY PHASE SHIFTER USING LIMITED GROUND PLANE TRANSITION AND SWITCHING ARRANGEMENT

pSemi Corporation, San D...

1. An electronic arrangement comprising:a first electronic block;
a signal input and a signal output; and
a switching arrangement comprising:
a first inner signal conductor, a first outer signal conductor and a second outer signal conductor;
a second inner signal conductor, a third outer signal conductor and a fourth outer signal conductor;
a switching matrix;
wherein:
(a) the first electronic block is configured to receive a single-ended input signal from the signal input and generate a first differential signal;
(b) the switching arrangement is configured to receive the first differential signal and to exhibit:
(i) a through state, wherein the switching matrix is configured to connect the first inner signal conductor to the second inner signal conductor, the first outer conductor to the third outer conductor and the second outer conductor to the fourth outer conductor, thereby configuring the switching arrangement to pass the first differential signal through; and
(ii) a changeover state, wherein the switching matrix is configured to connect the first inner signal conductor to both the third outer signal conductor and the fourth outer conductor, and to connect the second inner signal conductor to both the first outer signal conductor and the second outer signal conductor, thereby configuring the switching arrangement to generate a second differential signal being the first differential signal with a phase shift.

US Pat. No. 10,396,779

GROUND SWITCHING FOR SPEAKER CURRENT SENSE

TEXAS INSTRUMENTS INCORPO...

1. A circuit, comprising:a pair of high side transistors coupled to a power supply node;
a pair of low side transistors coupled to the pair of high side transistors;
a first sense resistor coupled to one of the low side transistors at a first sense node;
a second sense resistor coupled to another of the low side transistors at a second sense node, wherein the first and second sense resistors are coupled together at a ground node;
a first switch network coupled to the first sense resistor;
a second switch network coupled to the second sense resistor;
a first pair of switches configured to selectively provide a potential of the ground node or a potential of the first sense node as a ground potential to the first switch network; and
a second pair of switches configured to selectively provide the potential of the ground node or a potential of the second sense node as a ground potential to the second switch network.

US Pat. No. 10,396,778

METHOD FOR POWER GATING FOR WIDE DYNAMIC VOLTAGE RANGE OPERATION

Apple Inc., Cupertino, C...

1. An apparatus, comprising:a circuit block coupled to a local power node, wherein the circuit block includes a plurality of rows of circuit cells; and
a power gating circuit coupled between the local power node and a global power supply, wherein the power gating circuit is configured to isolate the local power node from the global power supply based on an isolation signal, and wherein the power gating circuit includes:
a first plurality of first switching devices that have a first threshold voltage; and
a second plurality of second switching devices that have a second threshold voltage, different from the first threshold voltage;
wherein the first plurality of first switching devices and the second plurality of second switching devices are coupled to respective ones of a plurality of wires, each wire conducting power to a corresponding row of the plurality of rows of circuit cells;
a first power strap coupled to the plurality of wires; and
a second power strap coupled to the plurality of wires, wherein at least a portion of the circuit cells in each of the plurality of rows is between the first power strap and the second power strap.

US Pat. No. 10,396,777

ORING CIRCUIT

DELTA ELECTRONICS (THAILA...

1. An ORing circuit comprising:an input port for receiving an input voltage;
an output port for outputting an output voltage;
an ORing FET (field effect transistor) electrically connected between the input port and the output port and comprising a source, a gate and a drain, wherein the source of the ORing FET is electrically connected with the input port, and the drain of the ORing FET is electrically connected with the output port;
a comparing circuit electrically connected with the input port and the gate of the ORing FET;
a first transistor comprising a first terminal, a second terminal and a third terminal, wherein the first terminal is directly connected with the input port and the source of the ORing FET, and the third terminal is electrically connected with the gate of the ORing FET; and
a second transistor comprising a fourth terminal, a fifth terminal and a sixth terminal, wherein the fourth terminal is electrically connected with the output port and the drain of the ORing FET, the fifth terminal is directly connected to the sixth terminal, and the sixth terminal is electrically connected with the second terminal of the first transistor.

US Pat. No. 10,396,776

DRIVE VOLTAGE BOOSTER

Apple Inc., Cupertino, C...

1. A gate driver with voltage boosting capabilities for generating a gating signal at an output of the gate driver from an input signal received at an input of the gate driver, the gate driver comprising:a charge pump, the charge pump comprising a capacitor and a plurality of switches;
wherein responsive to a low value of an input signal, the capacitor is bypassed by the plurality of switches as to allow the input signal to drive the output directly, and
wherein responsive to a high value of the input signal, the capacitor is coupled in series with the input signal by the plurality of switches to drive the output with a boosted value with respect to the input signal.

US Pat. No. 10,396,775

SEMICONDUCTOR DEVICE FOR HIGH-VOLTAGE CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a semiconductor layer of a first conductivity type;
first and second semiconductor regions of a second conductivity type, which are disposed in a front surface layer of the semiconductor layer or on the semiconductor layer and have first and second parasitic diodes formed between the semiconductor layer and the first and second semiconductor regions respectively;
a control circuit disposed in the first semiconductor region;
a gate driver circuit disposed in a front surface layer of the second semiconductor region;
a first diode that is disposed in a surge current path formed by a negative surge voltage and passing through the second parasitic diode, and that has reverse characteristics to a surge current; and
a level shift circuit that outputs, to the gate driver circuit, a first gate control signal that is output from the control circuit.

US Pat. No. 10,396,774

INTELLIGENT POWER MODULE OPERABLE TO BE DRIVEN BY NEGATIVE GATE VOLTAGE

Hestia Power Inc., Hsinc...

1. An intelligent power component module operable to be driven by a negative gate voltage, comprising:an upper bridge circuit, comprising a first driving unit and a first wide bandgap semiconductor power unit electrically connected to the first driving unit, the first wide bandgap semiconductor power unit having a first drain terminal, a first gate terminal and a first source terminal;
a lower bridge circuit, comprising a second driving unit and a second wide bandgap semiconductor power unit electrically connected to the second driving unit, the second wide bandgap semiconductor power unit having a second drain terminal electrically connected to the first source terminal of the first wide bandgap semiconductor power unit, a second gate terminal and a second source terminal;
a first adjustment unit, comprising a first resistor electrically connected to the first driving unit and a first Zener diode electrically connected to the first resistor, the first Zener diode electrically connected to a first output node between the first source terminal of the first wide bandgap semiconductor unit and the second drain terminal of the second wide bandgap semiconductor power unit, and a first high side of the first driving unit; and
a second adjustment unit, comprising a second resistor electrically connected to the second driving unit and a second Zener diode, the second Zener diode electrically connected to the second source terminal of the second wide bandgap semiconductor power unit and a first low side of the second driving unit;
wherein, voltage levels of the first driving unit and the second driving unit are provided with respective shift voltages by the first adjustment unit and the second adjustment unit and are adjusted, such that the first wide bandgap semiconductor power unit and the second wide bandgap semiconductor power unit, in a driven state, is each provided with a driving voltage level alternating between a positive voltage and a negative voltage.

US Pat. No. 10,396,773

CIRCUIT AND A METHOD FOR DRIVING ELECTRICAL LOADS

EGGTRONIC ENGINEERING S.R...

1. An electrical circuit (100), comprising at least:an electric load to be driven (105)
a generator (110) of an electric current waveform, and
a passive filter (150) connected in input to the generator (110) and in output to the electric load (105) to be driven, wherein the passive filter (150) is tuned for generating an electric current waveform resulting from a conditioning of one or more harmonics of the electric current waveforms in input,
wherein the load (105) to be driven comprises a drive terminal of an active switch, and
wherein the passive filter (150) is a resonant reactive filter comprising inductors and capacitors,
characterized in that the passive filter (150) is tuned for amplifying the first harmonic of the electric current waveform with a multiplication factor, completely or nearly completely damping the second harmonic, and amplifying the third harmonic with an amplification factor equal to one third of the multiplication factor of the first harmonic,
wherein the generator (110) of the current waveform comprises:
a generator (115) of direct electric current,
a switching circuit (125) able to convert the direct electric current into an electric current waveform,
wherein the switching circuit (125) comprises at least:
an active switch (135)
a driver (140) for generating an electrical driver signal able to switch the active switch (135) on and off,
wherein the switching circuit (125) comprises an inductance (130) connected in series between the generator (115) of direct electric current and the active switch (135), the passive filter (150) having an input terminal connected with an electrical node interposed between the inductance (130) and the active switch (135), and
wherein the passive filter (150) comprises a plurality of electrical modules (195) including at least a first electrical module and a second electrical module, wherein the first electrical module comprises at least:
a first electric branch (200) branching from the input terminal,
a second electric branch (205) connecting an output terminal of the first electric branch (200) with a reference potential,
a capacitance (225) comprised in the second electric branch (205),
an inductance (215) comprised in the first electric branch (200), and
an inductance (230) comprised in the second electric branch (205), and wherein the second electrical module comprises at least:
a first electric branch (200) connected to the output terminal of the first electric branch (200) of the first electrical module,
a second electric branch (205) connecting an output terminal of the first electric branch (200) of the second electrical module with a reference potential,
a capacitance (225) comprised in the second electric branch (205) of the second electrical module, and
an inductance (215) comprised in the first electric branch (200) of the second electric module, and
an inductance (230) comprised in the second electric branch (205) of the second electric module.

US Pat. No. 10,396,771

VOLTAGE SUPPLY CIRCUITS AND CONTROLLING METHODS THEREFOR

MediaTek Inc., Hsin-Chu ...

1. A voltage supply circuit for generating a loading current at an output node, the voltage supply circuit comprising:a plurality of inductors coupled to the output node, each having an inductance value, wherein:
inductance values of first and second inductors of the plurality of inductors are greater than an inductance value of a third inductor of the plurality of inductors,
the first inductor is driven by a first signal, and
the second inductor is driven by a phase-shifted version of the first signal; and
a plurality of driver circuits to drive the plurality of inductors, respectively, wherein:
at least one driver circuit is enabled to generate the loading current lower than a current threshold at which another of the plurality of driver circuits is enabled, and
the third inductor is driven by the first signal and the phase-shifted version of the first signal when its respective driver circuit is enabled.

US Pat. No. 10,396,770

ACTIVE TRIAC TRIGGERING CIRCUIT

Ademco Inc., Golden Vall...

1. A power supply unit for a heating, ventilation and air conditioning thermostat, comprising:a first terminal for connection to a line of a power source;
a second terminal for connection to a load;
a bypass circuit having an input connected to the first terminal;
a triac having an input connected to the first terminal;
a stealing circuit having an input connected to an output of the bypass circuit and having an output connected to the second terminal;
a power steal module having an input connected to an output of the triac; and
a drive circuit having an output connected to a second input of the power steal module.

US Pat. No. 10,396,769

APPARATUS AND METHOD FOR CLOCK SIGNAL FREQUENCY DIVISION USING SELF-RESETTING, LOW POWER, LINEAR FEEDBACK SHIFT REGISTER (LFSR)

QUALCOMM Incorporated, S...

1. An apparatus, comprising:a first logic gate;
a set of cascaded flip-flops, wherein each of the flip-flops includes first and second data inputs, a data output, a clock input, and a select input, wherein the first data input of one of the set of cascaded flip-flops is coupled to an output of the first logic gate, wherein at least two data outputs of the set of cascaded flip-flops are coupled to at least two inputs of the first logic gate, respectively, wherein the select inputs of the set of cascaded flip-flops are configured to receive a first control signal, and wherein the second data inputs are configured to receive logic values of an initial valid state of a sequence;
wherein the set of cascaded flip-flops are configured to:
generate distinct valid states of the sequence at their respective data outputs in response to a first clock signal applied to the clock inputs of the set of cascaded flip-flops and the first control signal being deasserted; and
generate the initial valid state of the sequence at their respective data outputs in response to the first clock signal and the first control signal being asserted;
an invalid-state elimination circuit configured to:
detect an invalid state at the data outputs of the set of cascaded flip-flops; and
control the set of cascaded flip-flops to produce one of the distinct valid states at their data outputs in response to detecting the invalid state and the first clock signal; and
an end-of-sequence control circuit configured to:
generate the asserted first control signal in response to detecting one of the states of the sequence, and
generate the deasserted first control signal in response to not detecting the one of the states of the sequence.

US Pat. No. 10,396,768

CIRCUITS WITH LOW-PASS FILTERS AND DIFFERENTIAL AMPLIFIERS

TEXAS INSTRUMENTS INCORPO...

1. A circuit comprising:a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port;
a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port;
a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port; and
a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters;
the first differential amplifier comprising a capacitor, the capacitor of the first differential amplifier comprising a first terminal coupled to the first input port of the first differential amplifier and a second terminal coupled to the output port of the first differential amplifier.

US Pat. No. 10,396,767

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprisingan input determination circuit including:
a comparator that is driven based on a first reference potential and includes an input voltage terminal and a reference voltage terminal;
a reference voltage generation circuit that inputs a reference voltage that is generated from a connection point between a constant current source and a resistor to the reference voltage terminal of the comparator, the constant current source and the resistor being interposed between a second reference potential that is separated from the first reference potential and a third potential that is higher than the first reference potential and the second reference potential; and
a first low pass filter that is interposed between a signal input system that is connected to the input voltage terminal of the comparator and the second reference potential.

US Pat. No. 10,396,766

PARASITIC CAPACITANCE CANCELLATION USING DUMMY TRANSISTORS

TEXAS INSTRUMENTS INCORPO...

1. An apparatus, comprising:a plurality of first transistors coupled to a first input terminal and a first output terminal;
a plurality of second transistors coupled to a second input terminal and a second output terminal;
a plurality of first dummy transistors coupled to the first input terminal and the second output terminal; and
a plurality of second dummy transistors coupled to the second input terminal and the first output terminal;
wherein the plurality of first transistors share a first interdigitated n-type doped region with the plurality of first dummy transistors;
wherein the plurality of first transistors share a second interdigitated n-type doped region with the plurality of second dummy transistors;
wherein the plurality of second transistors share a third interdigitated n-type doped region with the plurality of second dummy transistors; and
wherein the plurality of second transistors share a fourth interdigitated n-type doped region with the plurality of first dummy transistors.

US Pat. No. 10,396,765

POWER AMPLIFYING APPARATUS WITH SPURIOUS SIGNAL REDUCTION FUNCTION

Samsung Electro-Mechanics...

1. A power amplifying apparatus, comprising:a power circuit configured to generate operating power;
a random pulse generation circuit configured to receive the operating power and to generate a pulse width modulation signal of which a pulse width is randomly changed over time based on an input radio frequency (RF) signal; and
a charge pump circuit configured to receive the operating power and to randomly perform a switching operation based on the pulse width modulation signal,
wherein the random pulse generation circuit comprises a rectifier configured to rectify the input RF signal to provide an envelope voltage having an envelope level of the RF signal.

US Pat. No. 10,396,764

HIGH-VOLTAGE PULSE GENERATOR

1. A high-voltage pulse generator, comprising:a plurality of stages and a current return electrode to ground connected in series, with each stage among the plurality of stages comprising at least one energy storage element connected in series with a spark gap, wherein
each spark gap is distributed on an axis,
odd-numbered energy storage elements are arranged on a first side of the axis,
even-numbered energy storage elements are arranged on a second side of the axis,
a circuit formed by the plurality of stages and the current return electrode has a reduced inductance during a discharge phase of the high-voltage pulse generator, with respect to another generator comprising the same components arranged along a conventional architecture, and
a dielectric film is arranged between the current return electrode and the circuit formed by the plurality of stages.

US Pat. No. 10,396,763

CURRENT-CONTROLLED CMOS LOGIC FAMILY

Avago Technologies Intern...

1. An apparatus comprising:an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (CMOS) logic;
CMOS circuitry, within the integrated circuitry, configured to:
receive a plurality of signals; and
process the plurality of signals to generate another plurality of signals; and
CMOS circuitry, within the integrated circuitry, configured to:
receive the another plurality of signals from the CMOS circuitry; and
process the another plurality of signals to generate a signal.

US Pat. No. 10,396,762

FLIP-FLOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

FUJITSU LIMITED, Kawasak...

1. A flip-flop circuit comprising:a data capture circuit that captures data based on a clock;
a data hold circuit that holds an output of the data capture circuit based on the clock; and
a timing control circuit that controls coupling between the output of the data capture circuit and the data hold circuit based on the clock;
when the data capture circuit captures new data based on the clock, the timing control circuit performing control so as to temporarily interrupt the coupling between the output of the data capture circuit and the data hold circuit, wherein the data capture circuit includes
a first transistor of a first conductivity type and a second transistor of a second conductivity type different from the first conductivity type, the first transistor and the second transistor being arranged in series with each other between a first power supply line and a second power supply line and receiving the data by gates of the first transistor and the second transistor, and a third transistor of the second conductivity type, the third transistor being coupled between the first transistor and the second transistor and receiving the clock by a gate of the third transistor,
a clock delay circuit that delays the clock,
a fourth transistor of the first conductivity type, the fourth transistor receiving the clock delayed by the clock delay circuit and being disposed between the first power supply line and a first node to which the first transistor and the third transistor are coupled, and
a fifth transistor of the first conductivity type and a sixth transistor of the second conductivity type, the fifth transistor and the sixth transistor being arranged in series with each other between the first power supply line and the second power supply line and receiving the clock by gates of the fifth transistor and the sixth transistor, and a seventh transistor of the first conductivity type, the seventh transistor being coupled between the fifth transistor and the sixth transistor and receiving a signal of the first node by a gate of the seventh transistor.

US Pat. No. 10,396,761

FLIP-FLOP

Samsung Electronics Co., ...

1. A flip-flop comprising:a first node charging circuit configured to charge a first node with inverted input data;
a second node charging circuit configured to charge a second node with input data;
a first n-channel metal oxide semiconductor (NMOS) transistor including a first terminal connected to the first node, a second terminal, and a gate terminal;
a second NMOS transistor including a first terminal connected to the second terminal of the first NMOS transistor, a second terminal connected to a low power voltage, and a gate terminal;
a third NMOS transistor including a first terminal connected to the first node, a second terminal, and a gate terminal connected to the second node;
a fourth NMOS transistor including a first terminal connected to the second node, a second terminal, and a gate terminal;
a fifth NMOS transistor including a first terminal connected to the second terminal of the fourth NMOS transistor, a second terminal connected to the low power voltage, and a gate terminal;
a sixth NMOS transistor including a first terminal connected to the second node, a second terminal, and a gate terminal connected to the first node;
a seventh NMOS transistor including a first terminal connected to the second terminal of the third NMOS transistor, a second terminal connected to a sixth node, and a gate terminal configured to receive a clock signal; and
an eighth NMOS transistor including a first terminal connected to the second terminal of the sixth NMOS transistor, a second terminal connected to a fifth node, and a gate terminal configured to receive the clock signal,
said flip-flop being configured to latch the input data at rising edges of the clock signal, and output the latched input data as output data.

US Pat. No. 10,396,760

DIFFERENTIAL PAIR CONTACT RESISTANCE ASYMMETRY COMPENSATION SYSTEM

Dell Poducts L.P., Round...

1. A differential pair contact resistance asymmetry compensation system, comprising:a board;
a differential trace pair that is provided on the board;
a receiver device that is coupled to the differential trace pair via a receiver device connector interface; and
a transmitter device that is coupled to the differential trace pair via a transmitter device connector interface, wherein the transmitter device is configured to:
transmit, to the receiver device via the differential trace pair, a contact resistance compensation data stream;
adjust an impedance provided by the transmitter device to compensate for a contact resistance asymmetry in the transmitter device connector interface; and
determine that differential trace pair signal transmission capabilities for the differential trace pair in transmitting the contact resistance compensation data stream have improved in response to the adjustment of the impedance provided by the transmitter device and, in response, set the impedance provided by the transmitter device.

US Pat. No. 10,396,759

FILTER AND MULTIPLEXER

TAIYO YUDEN CO., LTD., T...

1. A filter comprising:a first substrate;
a first piezoelectric thin film resonator and a second piezoelectric thin film resonator located on a lower surface of the first substrate, each of the first piezoelectric thin film resonator and the second piezoelectric thin film resonator including a piezoelectric film, and a first electrode and a second electrode facing each other across the piezoelectric film, a crystal orientation from the first electrode to the second electrode of the piezoelectric film of the first piezoelectric thin film resonator being identical to that of the second piezoelectric thin film resonator in a resonance region where the first electrode and the second electrode face each other across the piezoelectric film, the first electrodes of the first piezoelectric thin film resonator and the second piezoelectric thin film resonator connecting to each other in a connection region between the resonance regions, the second electrodes of the first piezoelectric thin film resonator and the second piezoelectric thin film resonator failing to connect to each other in the connection region, and an area of the resonance region of the first piezoelectric thin film resonator being approximately equal to that of the second piezoelectric thin film resonator,
a second substrate, the first substrate being mounted on an upper surface of the second substrate so that the upper surface faces the lower surface of the first substrate across an air gap; and
a ground pattern that is located on the upper surface of the second substrate, and does not overlap with the first electrode located in the resonance regions of the first piezoelectric thin film resonator and the second piezoelectric thin film resonator and the connection region in plan view.

US Pat. No. 10,396,758

ELASTIC WAVE DEVICE, HIGH-FREQUENCY FRONT END CIRCUIT, AND COMMUNICATION APPARATUS

Murata Manufacturing Co.,...

1. An elastic wave device comprising:an antenna terminal that is connected to an antenna;
a first band pass filter that is connected to the antenna terminal and has a first pass band;
a second band pass filter that is connected to the antenna terminal and has a second pass band which is different from the first pass band; and
a matching circuit that is connected to the antenna terminal; wherein
the first and second band pass filters are indirectly connected to the antenna terminal with the matching circuit interposed and connected between the antenna terminal and the first and second band pass filters;
each of the first band pass filter and the second band pass filter includes:
a piezoelectric substrate that includes a first main surface and a second main surface which face each other;
an interdigital transducer electrode that is provided on the first main surface of the piezoelectric substrate and includes a first electrode layer containing molybdenum as a main component; and
a dielectric film that is provided on the first main surface of the piezoelectric substrate and covers the interdigital transducer electrode; wherein
the piezoelectric substrate is made of lithium niobate;
the dielectric film is made of silicon oxide;
the elastic wave device has a structure that causes Rayleigh waves to propagate through the piezoelectric substrate; and
a duty ratio of the interdigital transducer electrode is equal to or more than about 0.55 and less than or equal to about 0.75; and
a frequency interval between the first pass band and the second pass band is about 10 MHz or more.

US Pat. No. 10,396,757

ACOUSTIC WAVE DEVICE

TAIYO YUDEN CO., LTD., T...

1. An acoustic wave device comprising:a first piezoelectric substrate;
a plurality of first IDTs that are located on a first surface of the first piezoelectric substrate, each of the plurality of first IDTs including a plurality of first electrode fingers;
a second piezoelectric substrate that is located above the first surface; and
a plurality of second IDTs that are located on a second surface of the second piezoelectric substrate, each of the plurality of second IDTs including a plurality of second electrode fingers, the second surface of the second piezoelectric substrate facing the first surface across an air gap,
wherein:
extension directions of the plurality of first electrodes of the plurality of first IDTs are parallel to each other and extend in a first extension direction;
extension directions of the plurality of second electrodes of the plurality of second IDTs are parallel to each other and extend in a second extension direction; and
the first extension direction is non-parallel to the second extension direction.

US Pat. No. 10,396,755

RESONATOR HAVING FRAME AND METHOD OF MANUFACTURING THE SAME

Samsung Electro-Mechanics...

1. A resonator, comprising:a resonating portion comprising a first electrode, a second electrode, and a piezoelectric layer disposed between the first electrode and the second electrode;
a frame provided at an outer edge of the resonating portion, a portion of the frame covering an outer end portion of the second electrode; and
a connection portion disposed on an upper surface of the frame.

US Pat. No. 10,396,754

RESONATOR DEVICE, ELECTRONIC DEVICE, AND MOVING OBJECT

Seiko Epson Corporation, ...

1. A resonator device comprising:a substrate having first and second principal surfaces opposite to each other, the second principal surface having a recess therein so that the substrate has a ledge on the second principal surface;
a resonator element mounted on the first principal surface of the substrate;
a thermo-sensitive element mounted in the recess of the second principal surface of the substrate via a bonding material; and
a plurality of electrode terminals disposed on the ledge of the second principal surface of the substrate, the plurality of electrode terminals being connected to one of the resonator element and the thermo-sensitive element,
wherein a first distance in a first direction perpendicular to the first principal surface from a mounting surface of one of the plurality of electrode terminals to an outer surface of the thermo-sensitive element is at least 0.05 mm,
a second distance in the first direction from the mounting surface of one of the plurality of electrode terminals to a first inner surface of the recess, on which the thermo-sensitive element is mounted, is less than 0.3 mm, and
the outer surface of the thermo-sensitive element that is free from the bonding material is exposed to an inner space of the recess.

US Pat. No. 10,396,753

STACKED WAFER-LEVEL PACKAGING DEVICES

Skyworks Solutions, Inc.,...

1. A wireless device comprising:a transceiver configured to generate a radio-frequency (RF) signal;
a front-end module (FEM) in communication with the transceiver, the front-end module including a packaging substrate configured to receive a plurality of components, the front-end module further including a stacked assembly implemented on the packaging substrate, the stacked assembly including a first wafer-level packaging (WLP) device having a radio-frequency shield, the stacked assembly further including a second wafer-level packaging device having a radio-frequency shield, the second wafer-level packaging device positioned over the first wafer-level packaging device such that the radio-frequency shield of the second wafer-level packaging device is electrically connected to the radio-frequency shield of the first wafer-level packaging device; and
an antenna in communication with the front-end module, the antenna configured to transmit an amplified radio-frequency signal.

US Pat. No. 10,396,752

MEMS DEVICE

MURATA MANUFACTURING CO.,...

1. A MEMS device comprising:a substrate;
a frame disposed on the substrate;
a plate including a piezoelectric layer and a pair of electrode films disposed on opposing surfaces of the piezoelectric layer, respectively, with the pair of electrodes including an upper electrode and a lower electrode closer to the substrate than the upper electrode;
a pair of holding portions disposed on opposing sides of the plate and anchoring the plate to the frame;
an insulating layer disposed on the plate; and
a resistive film disposed on the insulating layer on a region of the insulating layer that extends along a straight line between the holding portions, such that the insulating layer electrically insulates the resistive film and at least one electrode film of the pair of electrode films,
wherein the insulating layer is disposed between the resistive film and the upper electrode of the pair of electrodes.

US Pat. No. 10,396,751

ACOUSTIC WAVE FILTER DEVICE

Samsung Electro-Mechanics...

1. An acoustic wave filter device comprising:a lower electrode disposed between a substrate and a piezoelectric layer;
an upper electrode disposed on the piezoelectric layer, and comprising a first frame portion, a second frame portion, an extension portion disposed between the first frame portion and the second frame portion, and an end portion extending from the second frame portion; and
an insulating layer disposed on an upper surface of the first frame portion, an upper surface of the second frame portion, an upper surface of the extension portion, and an upper surface of the end portion,
wherein the insulating layer exposes portions of a side surface and the upper surface of the first frame portion.

US Pat. No. 10,396,750

RADIO FREQUENCY TRANSMITTER HAVING IMPROVED RECEIVE BAND REJECTION FUNCTION

Samsung Electro-Mechanics...

1. A radio frequency transmitter, comprising:a transmit circuit configured to generate a transmit signal;
a receive band rejection filter comprising a capacitor and an inductor resonating with each other to reject a receive frequency band from the transmit signal, wherein a ratio value of a capacitance value of the capacitor to an inductance value of the inductor is within a predetermined range; and
a power amplifying circuit configured to amplify the transmit signal through the receive band rejection filter.

US Pat. No. 10,396,749

RADIO-FREQUENCY MODULE

MURATA MANUFACTURING CO.,...

1. A radio-frequency module utilizing carrier aggregation in which communication is performed by simultaneously using at least two frequency bands selected from a plurality of frequency bands having different frequencies, the radio-frequency module comprising:a switch circuit that includes one input terminal and three or more output terminals and that simultaneously connects the input terminal and each of two or more output terminals selected from the three or more output terminals;
a plurality of signal paths that propagate signals of corresponding frequency bands of the plurality of frequency bands and that are connected to the three or more output terminals in a one-to-one correspondence;
a filter element provided in each of the plurality of signal paths; and
a variable matching circuit provided in at least one of the plurality of signal paths, a circuit state of the variable matching circuit being changed in accordance with a combination of two or more signal paths simultaneously connected to the input terminal among the plurality of signal paths; wherein
the switch circuit outputs a control signal indicating a connection relationship between the input terminal and the three or more output terminals; and
the circuit state of the variable matching circuit is changed based on the control signal.

US Pat. No. 10,396,748

LINEAR, LOW NOISE, HIGH Q AND WIDELY TUNABLE NOTCH FILTER

AVAGO TECHNOLOGIES INTERN...

1. A notch filter circuit, the circuit comprising:one or more first reactive elements coupled between a first filter node and a first node; and
a multi-branch circuit coupled between the first node and a second node,
wherein:
the multi-branch circuit comprise multiple parallel branches,
a branch of the multi-branch circuit comprises at least a switch coupled to a variable capacitor, and
capacitance values of variable capacitors of the multi-branch circuit are configured to be adjusted via multiple consecutive clock pulses to allow tuning a notch frequency of the notch filter circuit.

US Pat. No. 10,396,747

TEMPERATURE COMPENSATED OSCILLATION CIRCUIT, OSCILLATOR, ELECTRONIC APPARATUS, VEHICLE, AND METHOD OF MANUFACTURING OSCILLATOR

Seiko Epson Corporation, ...

1. A temperature compensated oscillation circuit comprising:an oscillation circuit that oscillates a resonator;
a first terminal that is connected to the oscillation circuit and receives an output signal of the resonator;
a second terminal separate from the first terminal;
a fractional N-PLL circuit that multiplies frequency of an oscillation signal which is output by the oscillation circuit, based on a frequency division ratio which is input;
a temperature measurement unit that measures temperature; and
a storage unit that stores a temperature correction table for correcting frequency temperature characteristics of the oscillation signal,
a control unit configured to set an update mode for updating the temperature correction table; and
a temperature correction table updating unit configured to update the temperature correction table in the update mode based on an output signal of the fractional N-PLL circuit and a reference clock signal which is input from the second terminal,
wherein the frequency division ratio of the fractional N-PLL circuit is set based on a measurement value obtained by the temperature measurement unit and the temperature correction table.

US Pat. No. 10,396,746

METHOD OF FORMING AN INTEGRATED RESONATOR WITH A MASS BIAS

TEXAS INSTRUMENTS INCORPO...

1. A method of forming a piezoelectric resonator with an acoustic Bragg reflector, comprising:depositing alternating dielectric layers of lower and higher acoustic impedance materials over a substrate;
depositing a first resonator electrode over the alternating dielectric layers; depositing a piezoelectric layer over the first resonator electrode; depositing a second resonator electrode over the piezoelectric layer;
depositing a mass bias over first and second resonator electrodes such that the mass bias is electrically insulated from the first and second resonator electrodes; and
depositing first and second contact pads concurrently with depositing the mass bias and of a same material as the mass bias, the first contact pad making electrical contact to the first electrode and the second contact pad making electrical contact with the second electrode.

US Pat. No. 10,396,744

SYSTEMS AND METHODS FOR IDENTIFYING AND REMEDIATING SOUND MASKING

iZotope, Inc., Cambridge...

1. A method comprising acts of:(A) receiving a multi-track audio recording comprising a plurality of tracks synchronized over a time interval, a first track of the plurality of tracks corresponding to a first audio recording of the multi-track audio recording, a second track of the plurality of tracks corresponding to a second audio recording of the multi-track audio recording, the first track and the second track comprising sound produced by different instruments;
(B) determining a loudness of the first audio recording at each of a plurality of frequencies during a particular time period of the time interval;
(C) determining a loudness of the second audio recording at each of the plurality of frequencies during the particular time period;
(D) determining a partial loudness of the first audio recording at a first frequency of the plurality of frequencies during the particular time period, based at least in part on the loudness of the second audio recording, at the first frequency during the particular time period, determined in the act (C);
(E) determining a loudness loss for the first audio recording at the first frequency during the particular time period based at least in part on the partial loudness determined in the act (D); and
(F) creating a processed multi-track audio recording by applying one or more measures to the multi-track audio recording received in the act (A), based upon the loudness loss determined in the act (E).

US Pat. No. 10,396,742

RECEIVER AND NOISE SQUELCH CONTROL METHOD

JVC KENWOOD CORPORATION, ...

1. A receiver comprising:a noise squelch processor configured to generate a noise level decreasing from an initial value to a predetermined convergence value by integrating, by an integrator composed of a low-pass filter, a rectified signal obtained by extracting and rectifying a signal outside a band of a voice in a detection signal, obtained by detecting a reception signal to determine whether a voice signal is to be muted or unmuted by comparing the noise level and a threshold value with each other, and to generate a noise squelch determination signal;
a carrier detector configured to generate a carrier determination signal indicating whether or not the reception signal is present based on a signal strength of the reception signal;
an audio controller configured to supply a voice signal generated based on the detection signal to a speaker;
an audio mute determiner configured to instruct the audio controller to mute the voice signal when the noise squelch determination signal indicates that the voice signal is to be muted; and
an integrator controller configured to control the integrator to set a cutoff frequency of the integrator to a second cutoff frequency higher than a first cutoff frequency at first timing when the carrier detector generates a carrier determination signal indicating that the reception signal is present, and to switch the cutoff frequency of the integrator from the second cutoff frequency to the first cutoff frequency at second timing after an elapse of a predetermined period from the first timing.

US Pat. No. 10,396,741

HEADSET WITH PROGRAMMABLE MICROPHONE MODES

Voyetra Turtle Beach, Inc...

1. A system for processing audio signals, the system comprising:a headset comprising:
a speaker;
a beamforming microphone configured to sense an ambient sound level near the headset of sounds external to the headset; and
an audio processing unit that configures the headset in one of a plurality of modes by configuring a beam pattern of the beamforming microphone comprising a plurality of microphone elements, said mode configuration based on at least the sensed ambient sound level, wherein the headset is configured in a wider quiet mode beam pattern when the sensed ambient sound level is below a level of sound from a user of the headset and in a narrower loud mode when the sensed ambient sound level is above the level of sound from the user of the headset.

US Pat. No. 10,396,739

METHODS AND APPARATUS FOR ADJUSTING A LEVEL OF AN AUDIO SIGNAL

Dolby Laboratories Licens...

1. A method for adjusting a level of an audio signal in an audio processing apparatus, the method comprising:dividing an audio signal into a plurality of frequency bands;
obtaining modification parameters for at least one of the plurality of frequency bands, the modification parameters comprising filter coefficients and amplitude scale factors, each of the amplitude scale factors respectively operating in a frequency band of the plurality of frequency bands;
deriving gain factors for at least one of the plurality of frequency bands, the gain factors determined based on the amplitude scale factors;
smoothing the gain factors, wherein the smoothing of the gain factors is optional;
determining a level of noise from noise compensation factors;
applying the gain factors to at least one of the frequency bands to generate gain adjusted frequency bands;
adjusting the level of noise based on the gain adjusted frequency bands;
filtering at least one of the frequency bands with a filter generated with the filter coefficients, wherein the filter coefficients are applied to time-varying filters; and
synthesizing the plurality of frequency bands to generate an output audio signal;
wherein the gain factors are both time and frequency varying.

US Pat. No. 10,396,738

METHODS AND APPARATUS FOR ADJUSTING A LEVEL OF AN AUDIO SIGNAL

Dolby Laboratories Licens...

1. A method for adjusting a level of an audio signal in an audio processing apparatus, the method comprising:dividing an audio signal into a plurality of frequency bands;
obtaining modification parameters for at least one of the plurality of frequency bands, the modification parameters comprising filter coefficients and amplitude scale factors, each of the amplitude scale factors respectively operating in a frequency band of the plurality of frequency bands and each amplitude scale factor representing an average energy over the frequency band and a time segment;
deriving gain factors for at least one of the plurality of frequency bands, the gain factors determined based on the amplitude scale factors;
smoothing the gain factors, wherein the smoothing of the gain factors is optional;
determining a level of noise from noise compensation factors;
applying the gain factors to at least one of the frequency bands to generate gain adjusted frequency bands;
adjusting the level of noise based on the gain adjusted frequency bands;
filtering at least one of the frequency bands with a filter generated with the filter coefficients; and
synthesizing the plurality of frequency bands to generate an output audio signal;
wherein the gain factors are both time and frequency varying.

US Pat. No. 10,396,737

WIDE DYNAMIC RANGE AMPLIFIER SYSTEM

SKYWORKS SOLUTIONS, INC.,...

1. A broadband amplifier assembly having a signal input and a signal output, comprising:a fixed gain amplifier having an input and an output, the input coupled to the signal input;
an adjustable attenuator having an input and an output, the input of the adjustable attenuator being coupled to the output of the fixed gain amplifier;
a variable gain amplifier having an input coupled to the output of the adjustable attenuator and an output coupled to the signal output, the variable gain amplifier having a substantially constant input-referred linearity across a range of gain levels; and
a controller coupled to the fixed gain amplifier, the adjustable attenuator, and the variable gain amplifier and configured to control an amount of attenuation provided by the adjustable attenuator and an amount of gain provided by the variable gain amplifier to maintain a substantially constant input-referred linearity across a range of output power levels provided by a combination of the fixed gain amplifier, the adjustable attenuator, and the variable gain amplifier.

US Pat. No. 10,396,736

ATTENUATOR DEVICE IN A RADIO FREQUENCY TRANSMISSION STAGE

5. A transmission device comprising:a transmit stage configured to deliver a transmission signal on an input-output node of an antenna and comprising a power transistor having a current path coupled to the input-output node and configured to amplify a signal to be transmitted with the antenna, and
a receive stage configured to receive with the antenna a reception signal on the input-output node and comprising an attenuator circuit for attenuating the reception signal, wherein the attenuator circuit comprises the power transistor and a control circuit configured to place the power transistor in a triode mode.

US Pat. No. 10,396,735

AMPLIFIER SYSTEM WITH DIGITAL SWITCHED ATTENUATOR

SKYWORKS SOLUTIONS, INC.,...

1. A broadband amplifier assembly having a signal input and a signal output, comprising:a fixed gain amplifier having an input and an output, the input coupled to the signal input;
an adjustable attenuator having an input and an output, the input of the adjustable attenuator being coupled to the output of the fixed gain amplifier, the adjustable attenuator having a plurality of attenuation cells directly coupled in series between the input and the output of the adjustable attenuator, the adjustable attenuator having an attenuation mode of operation, a bypass mode of operation, and an isolation mode of operation; and
a power amplifier having an input and an output, the input of the power amplifier being coupled to the output of the adjustable attenuator and the output of the power amplifier being coupled to the signal output.

US Pat. No. 10,396,734

DIFFERENTIAL TRANSIMPEDANCE AMPLIFIER

1. A differential transimpedance amplifier, comprising:a common gate amplifier configured to receive an electrical signal from an input node; and
a common source amplifier configured to have a feedback resistor and receive the electrical signal form the input node,
wherein an output signal of the common gate amplifier and an output signal of the common source amplifier form a differential signal pair, and
wherein the common gate amplifier and the common source amplifier each includes a load having a transformer which removes an effect of parasitic capacitance.

US Pat. No. 10,396,733

SUPERCONDUCTING SIGNAL AMPLIFIER

PSIQUANTUM CORP., Palo A...

1. A system, comprising:a first circuit that includes a plurality of superconducting wires connected in parallel with one another, the plurality of superconducting wires including:
a first superconducting wire with a corresponding first threshold superconducting current; and
a second superconducting wire;
a second circuit connected in parallel to the first circuit;
a first current source coupled to the first superconducting wire and configured to selectively supply a first current; and
a second current source coupled to a combination of the first circuit and the second circuit and configured to supply a second current such that the plurality of superconducting wires operate in a superconducting state;
wherein the second superconducting wire is longer than the first superconducting wire, and
wherein a combination of the first current and the second current exceeds the first threshold superconducting current.

US Pat. No. 10,396,732

AMPLIFICATION OF FREQUENCY MULTIPLEXED MICROWAVE SIGNALS USING CASCADING MULTI-PATH INTERFEROMETRIC JOSEPHSON DIRECTIONAL AMPLIFIERS WITH NONOVERLAPPING BANDWIDTHS

INTERNATIONAL BUSINESS MA...

2. A cascading microwave directional amplifier (cascade) comprising:a set of Josephson devices, each Josephson device in the set having a corresponding operating bandwidth of microwave frequencies, wherein different operating bandwidths have different corresponding center frequencies; and
a series coupling between first Josephson device from the set and an nth Josephson device from the set, wherein the series coupling causes
the first Josephson device to amplify a signal of a first frequency from a frequency multiplexed microwave signal (multiplexed signal) and propagate without amplification a signal of an nth frequency from the multiplexed signal in a first signal flow direction through the series coupling, and
the nth Josephson device to amplify the signal of the nth frequency and propagate without amplification the signal of the first frequency from the multiplexed signal in the first signal flow direction through the series.

US Pat. No. 10,396,731

SELECTIVE AMPLIFICATION OF FREQUENCY MULTIPLEXED MICROWAVE SIGNALS USING CASCADING MULTI-PATH INTERFEROMETRIC JOSEPHSON DIRECTIONAL AMPLIFIERS WITH NONOVERLAPPING BANDWIDTHS

INTERNATIONAL BUSINESS MA...

1. A cascading selective microwave directional amplifier (cascade) comprising:a set of Josephson devices, each Josephson device in the set having a corresponding operating bandwidth of microwave frequencies, wherein different operating bandwidths have different corresponding center frequencies; and
a series coupling between first Josephson device from the set and an nth Josephson device from the set, wherein the series coupling causes the first Josephson device to amplify a signal of a first frequency from a frequency multiplexed microwave signal (multiplexed signal) in a first signal flow direction through the series coupling and the nth Josephson device to amplify a signal of an nth frequency in a second signal flow direction through the series, wherein the second signal flow direction is opposite of the first signal flow direction.

US Pat. No. 10,396,730

METHOD OF OPERATING DIGITAL-TO-ANALOG PROCESSING CHAINS, CORRESPONDING DEVICE, APPARATUS AND COMPUTER PROGRAM PRODUCT

STMICROELECTRONICS S.R.L....

1. A method, comprising:generating, by a processing chain, an analog output signal from a digital input signal;
generating a first digital signal based on the analog output signal, the first digital signal being indicative of a period of time an amplitude of the analog output signal is within a finite range of values;
determining, by a parameter estimation circuit comprising a feedforward path, the feedforward path having an input end and an output end, at least one parameter of the processing chain based on the digital input signal and the first digital signal, wherein the at least one parameter is generated at the output end of the feedforward path, and wherein determining the at least one parameter comprises:
providing the digital input signal as an input signal to the input end of the feedforward path; and
providing the first digital signal as an input signal to a logical operation located between the input end of the feedforward path and the output end of the feedforward path;
generating a second digital signal based on the at least one parameter and the digital input signal; and
comparing the first digital signal and the second digital signal.

US Pat. No. 10,396,729

DIFFERENTIAL CIRCUIT AND OPERATIONAL AMPLIFIER

FUJI ELECTRIC CO., LTD., ...

1. A differential circuit comprising:a first MOS transistor and a second MOS transistor that constitute a differential pair;
a determination unit to determine a level of a determination target signal that is based on at least one of differential inputs being input to a gate of the first MOS transistor and a gate of the second MOS transistor; and
a voltage changing unit to change a back gate voltage that is supplied to both back gates of the first MOS transistor and the second MOS transistor according to a determination result of the determination unit.

US Pat. No. 10,396,728

WIRELESS ELECTRIC POWER TRANSMITTER

Samsung Electronics Co., ...

1. A wireless power transmitter for transmitting power for charging a wireless power receiver, the wireless power transmitter comprising:an amplifier configured to amplify power and generate an alternating current (AC) power; and
a transmitting coil configured to wirelessly transmit power based on the generated AC power,
wherein the amplifier comprises:
a first transistor of which a first end is connected to ground and a second transistor of which a first end is connected to ground;
a capacitor of which a first end is connected to a second end of the first transistor, wherein a second end of the capacitor is connected to a second end of the second transistor, and the second end of the capacitor is connected to a first end of the transmitting coil; and
a coil of which a first end is connected to the first end of the capacitor, wherein a second end of the coil is connected to a second end of the transmitting coil.

US Pat. No. 10,396,727

LC NETWORK FOR A POWER AMPLIFIER WITH SELECTABLE IMPEDANCE

CREE, INC., Durham, NC (...

1. An amplifier circuit comprising:a radio-frequency (RF) amplifier comprising an input terminal and an output terminal, wherein the RF amplifier is configured to amplify, across a wideband frequency range, an RF signal applied to the RF amplifier input terminal so as to generate an amplified RF signal at the RF amplifier output terminal;
a first impedance matching network directly electrically connected to the RF amplifier output terminal, the first impedance matching network operative to adjust an output impedance of the RF amplifier, and comprising:
a first reactive circuit connected between the RF amplifier output terminal and ground, the first reactive circuit having a substantially fixed impedance;
a second reactive circuit; and
a first switching device configured to couple the second reactive circuit to the first reactive circuit in an ON state, and to decouple the second reactive circuit from the first reactive circuit in an OFF state.

US Pat. No. 10,396,726

PREAMPLIFIER FOR MUSICAL INSTRUMENTS

ZOOM CORPORATION, Tokyo ...

1. A preamplifier for musical instruments, comprising:an operational amplifier configured to amplify an inputted analog audio signal;
a variable resistor configured to change an amplification factor of the operational amplifier by manually operating an operation unit;
an A/D converter configured to convert the amplified analog audio signal to a digital audio signal; and
an arithmetic processing unit configured to digital-signal process the digital audio signal, wherein
the variable resistor is provided with a detection mechanism configured to output a detection signal in accordance with an amount of operation of the operation unit, and
the arithmetic processing unit is configured to implement, based on a value of the detection signal, a first digital gain process configured to amplify the digital audio signal and/or a second digital gain process configured to attenuate the digital audio signal.

US Pat. No. 10,396,724

AMPLIFIER WITH COMMON MODE LOOP AND CHOP

Semiconductor Components ...

1. A system comprising:a fully differential amplifier circuit including a first amplifier, a first feedback path, and a second feedback path, the first feedback path providing a feedback path from a positive output of the first amplifier to a negative input of the first amplifier and the second feedback path providing a feedback path from a negative output of the first amplifier to a positive input of the first amplifier;
a chopper clock circuit configured to output a chopper clock signal at a variable duty cycle; and
a common mode loop circuit including a second amplifier and chopper switches, the common mode loop circuit configured to provide a local feedback loop for the first amplifier, the chopper switches configured to receive the chopper clock signal from the chopper clock circuit and configured to control a current flow into the positive input of the first amplifier and into the negative input of the first amplifier.

US Pat. No. 10,396,723

MULTIRATE, ITERATIVE, MEMORY POLYNOMIAL BASED MODELING AND PRE-DISTORTION OF HIGH BANDWIDTH POWER AMPLIFIERS

Northrop Grumman Systems ...

1. A method for pre-distorting a digital signal in a digital communications system, said method comprising:converting digital bits to be transmitted to a series of symbols defining the bits;
providing the symbols to a pulse shaping filter (PSF) that provides samples of the symbols at a predetermined sample rate;
providing the filtered samples to a pre-distorter that pre-distorts the samples, wherein pre-distorting the samples includes providing a non-linear transformation of the samples that is defined by pre-distorter taps, wherein pre-distorting the filtered samples in the pre-distorter includes incorporating pre-equalization into the pre-distorter taps; and
providing the pre-distorted samples to a power amplifier to be amplified and transmitted, wherein pre-distorting the samples includes modeling the power amplifier and associated transmitter components using a degree three memory polynomial, and wherein modeling the power amplifier includes modeling the power amplifier as a memoryless nonlinearity sandwiched between two linear time-invariant (LTI) filters and that the pre-equalization includes providing an estimate of at least one of the LTI filters and then inverting the estimate.

US Pat. No. 10,396,721

DISTORTION COMPENSATION CIRCUIT

MITSUBISHI ELECTRIC CORPO...

6. A distortion compensation circuit comprising:a distributor distributing an input signal to a first transmission line and a second transmission line;
a low-range open stub disposed on the first transmission line, having characteristics to attenuate, among input high-frequency signals being two waves, an amplitude of a signal in a low-frequency range by a set value or more with respect to an amplitude of a signal in a high-frequency range;
a first linearizer connected to the low-range open stub;
a first phase shifter connected to the first linearizer;
a high-range open stub disposed on the second transmission line, having characteristics to attenuate, among the input high-frequency signals being two waves, an amplitude of a signal in a high-frequency range by a set value or more with respect to an amplitude of a signal in a low-frequency range;
a second linearizer connected to the high-range open stub;
a second phase shifter connected to the second linearizer; and
a synthesizer synthesizing a signal from the first transmission line passed through the low-range open stub, the first linearizer, and the first phase shifter and a signal from the second transmission line passed through the high-range open stub, the second linearizer, and the second phase shifter.

US Pat. No. 10,396,720

HIGH-FREQUENCY AMPLIFIER APPARATUSES

1. A high-frequency amplifier apparatus comprising:two transistors, each having a first terminal and a second terminal that is connected to a ground connection point, wherein the two transistors are embodied alike and are arranged on a multi-layered circuit board that comprises a plurality of upper layers above a lowermost layer; and
a power transformer having a primary winding and a secondary winding, wherein the primary winding is connected to the first terminals of the two transistors;
wherein the primary winding and the secondary winding of the power transformer are each designed as planar conductor paths that are arranged in different layers of the plurality of upper layers of the multi-layered circuit board, and
wherein the lowermost layer of the multi-layered circuit board is a metal layer that is used as a reference ground.

US Pat. No. 10,396,719

INTEGRATED CIRCUIT DEVICE

Sumitomo Electric Industr...

1. An integrated circuit device comprising:a differential circuit including
a pair of differential input terminals,
an amplifier circuit including a pair of differential input nodes, one node of the pair of differential input nodes being electrically connected to one terminal of the pair of differential input terminals and another node of the pair of differential input nodes being electrically connected to another terminal of the pair of differential input terminals,
a first supply terminal configured to be supplied a first voltage from outside,
a second supply terminal configured to be supplied a second voltage lower than the first voltage from the outside,
a common terminal,
a first resistive element having one end and another end, the one end of the first resistive element being electrically connected to the one terminal of the pair of differential input terminals and the another end of the first resistive element being electrically connected to the common terminal,
a second resistive element having one end and another end, the one end of the second resistive element being electrically connected to the first supply terminal and the other end of the second resistive element being electrically connected to the common terminal, and
a third resistive element having one end and another end, the one end of the third resistive element being electrically connected to the one terminal of the pair of differential input terminals and the other end of the third resistive element being electrically connected to the second supply terminal;
a bonding wire; and
a capacitor having one end and another end, the another end of the capacitor being electrically connected to the common terminal by the bonding wire and the one end of the capacitor being electrically connected to the second supply terminal.

US Pat. No. 10,396,718

BIAS CONTROL CIRCUIT AND POWER AMPLIFICATION MODULE

MURATA MANUFACTURING CO.,...

1. A bias control circuit comprising:a reference voltage circuit that generates a reference voltage;
a resistor;
a reference voltage buffer circuit that applies the reference voltage to a second end of the resistor;
a constant current generating circuit that generates a constant current and that supplies the constant current to the second end of the resistor, the constant current being based on the reference voltage and driving the reference voltage buffer circuit; and
a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit based on a voltage at a first end of the resistor, wherein:
the reference voltage buffer circuit includes an operational amplifier and a P-channel MOSFET,
the reference voltage is applied to a first input terminal of the operational amplifier,
a second input terminal of the operational amplifier and a source of the P-channel MOSFET are connected to the second end of the resistor, and
an output terminal of the operational amplifier is connected to a gate of the P-channel MOSFET.

US Pat. No. 10,396,717

POWER CONTROL METHOD, DEVICE AND COMMUNICATION TERMINAL FOR RADIO FREQUENCY POWER AMPLIFIER

BEIJING VANCHIP TECHNOLOG...

1. A power control device, comprising: a first linear regulator module, a voltage sensing module, and a second linear regulator module, whereinthe first linear regulator module, used to read a supply voltage signal and a power control signal, and generate an amplified signal having a linear relationship with the power control signal;
the voltage sensing module, used to generate a controllable current according to the amplified signal and saturation degree information of a pass element in the first linear regulator module, and convert the controllable current into a voltage; and
the second linear regulator module, used to perform linear voltage regulation on the voltage and generate a base control voltage.

US Pat. No. 10,396,716

MODULATED SUPPLY AMPLIFIER WITH ADJUSTABLE INPUT PARAMETER CONFIGURATION

Avago Technologies Intern...

6. A device comprising:a modulated supply (MS) power amplifier;
a first output circuit configured to provide a power supply voltage that is varied responsive to MS information indicative of an envelope of an input signal to the MS power amplifier;
a second output circuit configured to provide a gate voltage that is varied responsive to the MS information, the gate voltage and the power supply voltage being generated in parallel;
a first digital-to-analog converter coupled to the first output circuit, the first digital-to-analog converter configured to generate the power supply voltage responsive to the MS information; and
a second digital-to-analog converter coupled to the second output circuit, the second digital-to-analog converter configured to generate the gate voltage responsive to the MS information.

US Pat. No. 10,396,715

HIGH POWER RADIO-FREQUENCY SWITCHING TOPOLOGY AND METHOD

SKYWORKS SOLUTIONS, INC.,...

1. A radio-frequency circuit comprising:a series of transistors including at least a first transistor and a second transistor and each having at least a source, a gate, and a drain;
an input path coupled to the source of the first transistor and an output path coupled to the drain of the second transistor; and
a plurality of direct current bias networks including a first direct current bias network coupled to the gate of the first transistor, a second direct current bias network coupled to the gate of the second transistor, and a third direct current bias network coupled to the drain of the first transistor and the source of the second transistor, each of the plurality of direct current bias networks being configured to directly bias the series of transistors to direct a radio-frequency signal through the series of transistors.

US Pat. No. 10,396,714

RECONFIGURABLE LOW-NOISE AMPLIFIER (LNA)

Qorvo US, Inc., Greensbo...

1. A reconfigurable low-noise amplifier (LNA) comprising:amplifier circuitry having a gate terminal coupled to an input terminal, a source terminal coupled to a fixed voltage node, and a drain terminal, wherein the amplifier circuitry comprises field-effect transistor (FET) devices coupled in a cascode configuration between the drain terminal and the source terminal; and
a gamma inverting network (GIN) coupled between the input terminal and the fixed voltage node, wherein the GIN comprises:
a first switch configured to disable the GIN during operation at first frequencies within a lower frequency band and to enable the GIN during operation at second frequencies within a higher frequency band, which is higher than the lower frequency band; and
a first inductor and a first capacitor coupled in series through the first switch such that current flow is enabled through the first inductor when the first switch is in an on-state and current flow is disabled through the first inductor when the first switch is in an off-state.

US Pat. No. 10,396,713

ENVELOPE-TRACKING CURRENT BIAS CIRCUIT WITH OFFSET CANCELLATION FUNCTION

Samsung Electro-Mechanics...

1. An envelope-tracking current bias circuit comprising:a first rectifying circuit configured to detect an envelope of an input signal, and provide an envelope detection signal comprising a first direct current (DC) offset voltage;
a second rectifying circuit configured to provide a second DC offset voltage corresponding to the first DC offset voltage; and
a first arithmetic circuit configured to provide an envelope signal in which the first DC offset voltage is reduced through subtraction between the envelope detection signal and the second DC offset voltage.

US Pat. No. 10,396,712

TRANSFORMER FEED-BACK QUADRATURE VOLTAGE CONTROLLED OSCILLATOR FOR CORRECTING DYNAMIC PHASE ERROR AND COMMUNICATION APPARATUS USING THE SAME

NATIONAL CHUNG SHAN INSTI...

1. A transformer feed-back quadrature voltage controlled oscillator (QVCO), comprising:a first VCO;
a second VCO; and
a dynamic phase error correction circuit, having a plurality of coupling capacitors connected between the first and second VCOs, wherein the capacitances of the coupling capacitors are varied according to a digital control signal to correct a phase error of local oscillating (LO) signals of quadrature phases output by the first and second VCOs;wherein the transformer feed-back QCVO is formed by a first half circuit and a second half circuit, wherein each of the first and second half circuit comprises:a first coupling capacitor;
a second coupling capacitor;
an induction inductor;
a NMOS transistor;
a PMOS transistor; and
a frequency tuning circuit, a first end thereof is connected to a first end of the induction inductor, a drain of the PMOS transistor and a gate of the NMOS transistor, and a second end thereof is connected to a second end of the induction inductor, a drain of the NMOS transistor and a gate of the PMOS transistor;wherein the induction inductors of the first and second half circuit form a transformer, a body of the PMOS transistor of the first half circuit is connected to a source of the PMOS transistor of the second half circuit through the first coupling capacitor of the first half circuit, a body of the NMOS transistor of the first half circuit is connected to a source of the NMOS transistor of the second half circuit through the second coupling capacitor of the first half circuit, a body of the PMOS transistor of the second half circuit is connected to a source of the NMOS transistor of the first half circuit through the first coupling capacitor of the second half circuit, a body of the NMOS transistor of the second half circuit is connected to a source of the PMOS transistor of the first half circuit through the second coupling capacitor of the second half circuit, the drains of the PMOS transistors and the NMOS transistors are used to output the LO signals of quadrature phases, and a LO frequency is determined by a frequency tuning voltage applied to the frequency tuning circuit based upon a frequency-voltage curve;wherein the first and second coupling capacitors of the first and second half circuits are the variable coupling capacitors of the dynamic phase error correction circuit, so as to form the dynamic phase error correction circuit, the NMOS transistor, the PMOS transistor and the induction inductor of the first half circuit form the first VCO, and the PMOS transistor and the induction inductor of the second half circuit form the second VCO.

US Pat. No. 10,396,711

INTEGRATED CIRCUITS HAVING ON-CHIP INDUCTORS WITH LOW COMMON MODE COUPLING EFFECT

Zgmicro Wuxi Corporation,...

1. An integrated circuit, comprising:a first circuit, operating at a first frequency, including a first inductor; and
a second circuit, including a second inductor, provided to process an input signal, the second inductor including a first terminal, a second terminal, an intermediate terminal, and an intermediate node, wherein a first wire is formed between the first terminal and the intermediate node, a second wire is formed between the second terminal and the intermediate node, the first wire and the second wire, forming a coil with one or more turns, cross at a certain point on different layers, an intermediate tap is coupled between the intermediate node and the intermediate terminal, and the first and second terminals, and the intermediate terminal being located on one side of the coil and adjacent to each other, and
wherein when a current flows from the first terminal of the second inductor to the intermediate terminal of the second inductor and a current flows from the second terminal of the second inductor to the intermediate terminal of the second inductor, or when a current flows from the intermediate terminal of the second inductor to the first terminal of the second inductor and a current flows from the intermediate terminal of the second inductor to the second terminal of the second inductor, intermediate tap are cancelled out substantially by each other.

US Pat. No. 10,396,705

ROOFTOP MOUNTING SYSTEM FOR FLEXIBLE PHOTOVOLTAIC MODULES

Global Solar Energy, Inc....

1. A system for mounting flexible photovoltaic (PV) modules on a roof, the system comprising:a first elongate mounting bracket including a base configured to be coupled to a first rib of a ribbed rooftop and a first flange extending parallel to the base to define a first channel, such that a distal end of the first flange is spaced from the base;
a flexible PV module having a second elongate mounting bracket oriented along a central longitudinal axis of the flexible PV module, the second elongate mounting bracket including an upper plate secured to the flexible PV module and a second flange extending parallel to the upper plate to define a second channel, such that a distal end of the second flange is spaced from the upper plate;
a plurality of standoffs configured to be coupled to a lower face of the flexible PV module, the plurality of standoffs collectively configured to prevent contact between lateral edges of the PV module and the rooftop; and
a first ridge cap configured to be affixed to a second rib of the rooftop and a second ridge cap configured to be affixed to a third rib of the rooftop;
wherein each of the first and second ridge caps includes at least one side wing configured to abut a top face of the flexible PV module;
wherein the system is transitionable between (a) a roof-mounted configuration, in which the second elongate mounting bracket is coupled to the first elongate mounting bracket, the first flange being received by the second channel and the second flange being received by the first channel, and (b) an unmounted configuration, in which the second elongate mounting bracket is decoupled from the first elongate mounting bracket and the flexible PV module is separated from the rooftop; and
wherein when the system is in the roof-mounted configuration, the lateral edges of the module are disposed closer to the roof than the central longitudinal axis of the module, with a first lateral edge of the module overlapped by the first ridge cap in a laterally sliding fit and a second lateral edge of the module overlapped by the second ridge cap in a laterally sliding fit.

US Pat. No. 10,396,701

MOTOR CONTROL DEVICE, BLOWING DEVICE, AND CLEANER

NIDEC CORPORATION, Kyoto...

1. A motor control device of a brushless DC motor, the motor control device comprising:voltage acquisition circuitry that acquires a drive voltage of the motor;
rotational speed acquisition circuitry that acquires a rotational speed of the motor;
setting circuitry that sets a rotational speed instruction value of the motor according to an instruction input from outside;
calculation circuitry that calculates a rotational speed threshold value of the motor according to the rotational speed instruction value;
change circuitry that changes the rotational speed instruction value in a case where the rotational speed acquired by the rotational speed acquisition circuitry exceeds the rotational speed threshold value; and
storage circuitry that stores reference data used to calculate the rotational speed threshold value; wherein
the reference data includes at least three types of reference value sets each including a reference drive voltage value, a reference rotational speed instruction value, and a reference rotational speed threshold value; and
the calculation circuitry performs a proportional calculation based on a current drive voltage value which is acquired by the voltage acquisition circuitry, a current rotational speed instruction value which is set by the setting circuitry, and the reference value set to calculate the rotational speed threshold value.

US Pat. No. 10,396,700

MULTI-MOTOR SYSTEM, FREEZER COMPRISING THE SAME, AND METHODS FOR CONTROLLING THEREOF

ZHONGSHAN BROAD-OCEAN MOT...

1. A multi-motor system, comprising an air inlet, an air outlet, and a plurality of electronically commutated motors (ECMs), wherein:each electronically commutated motor (ECM) comprises a motor controller and a motor body;
the motor controller comprises a control circuit board; the control circuit board is provided with a microprocessor and a unit for detecting an operation parameter of the ECM
the ECMs comprise a main ECM, and a plurality of subordinate ECMs;
the main ECM is connected to the subordinate ECMs via wire or wireless communication;
the microprocessor of the motor controller of the main ECM is connected to a first temperature detection unit and a second temperature detection unit; the first temperature detection unit and the second temperature detection unit are respectively disposed on the air inlet and the air outlet outside of the main ECM to detect a temperature T1 at the air inlet and a temperature T2 at the air outlet; the microprocessor automatically selects an operation parameter of the main ECM in accordance with a temperature difference between the temperature T1 and the temperature T2; and
in operation, the main ECM informs each subordinate ECM of the temperature T1 and the temperature T2, and each subordinate ECM selects an operation parameter of the subordinate ECM in accordance with the temperature T1 and the temperature T2; or, the main ECM sets up operation parameters for each subordinate ECM in accordance with the temperature T1 and the temperature T2, and orders each subordinate ECM to operate according to preset operation parameters.

US Pat. No. 10,396,695

METHOD FOR PROTECTING AN ELECTRICAL POWER SYSTEM

General Electric Company,...

1. An electrical power system connected to a power grid, comprising:at least one cluster of electrical power subsystems, each of the electrical power subsystems comprising a power converter electrically coupled to a generator having a generator rotor and a generator stator, each of the electrical power subsystems defining a stator power path and a converter power path for providing power to the power grid, each of the electrical power subsystems further comprising a partial power transformer within the converter power path;
a subsystem switch configured with each of the electrical power subsystems;
a cluster transformer connecting each cluster of electrical power subsystems to the power grid;
a cluster switch communicatively coupled to the cluster transformer; and,
a controller communicatively coupled to each of the plurality of electrical power subsystems, the controller configured to perform one or more operations, the operations comprising:
monitoring the electrical power system for faults; and,
if a fault is detected in the stator power path of one of the electrical power subsystems, sending, via one of the subsystem switches or the power converters, a block signal to the cluster switch, the block signal comprising a signal that instructs the cluster switch to not trip in response to the fault being detected.

US Pat. No. 10,396,693

METHOD OF CONTROLLING CONSTANT CURRENT OF BRUSHLESS DC MOTOR AND CONTROLLER OF BRUSHLESS DC MOTOR USING THE SAME

LG Electronics Inc., Seo...

1. A method for controlling a brushless direct current (BLDC) motor, the method comprising:receiving a constant current from an output port of the BLDC motor;
comparing the constant current to a reference current;
based on the comparison of the constant current to the reference current, providing at least one speed command to a rotational speed control unit, wherein providing the at least one speed command comprises:
based on the comparison revealing that the constant current is smaller than the reference current, providing a first speed command to the rotational speed control unit, the first command being configured to increase a speed of the BLDC motor,
based on the comparison revealing that the constant current is larger than the reference current, providing a second speed command to the rotational speed control unit, the second command being configured to decrease a speed of the BLDC motor, and
based on the comparison revealing that the constant current is the same as the reference current, providing a third speed command to the rotational speed control unit, the third command being configured to maintain a speed of the BLDC motor; and
based on the at least one speed command, controlling, by the rotational speed control unit, a speed of the BLDC motor.

US Pat. No. 10,396,683

MODULAR MULTILEVEL CONVERTER

HYOSUNG HEAVY INDSTRIES C...

1. A Modular Multilevel Converter (MMC) comprising:multiple sub-modules connected in series with each other; and
a controller for controlling on/off switching of the multiple sub-modules,
wherein the multiple sub-modules include N sub-modules, which participate in operation of the MMC, and M redundant submodules, which participate in the operation of the MMC in place of at least one N sub-modules when the at least one N sub-modules fail,
wherein the controller switches on a sub-module, among the N+M sub-modules to which carrier signals are assigned, if a carrier signal assigned thereto is equal to or higher than a preset reference signal, and switches off the sub-module if the carrier signal assigned thereto is lower than the preset reference signal, and
wherein a range from a top to a rest position of each of the carrier signals of the N+M sub-modules is not balanced with a range from a bottom to the rest position thereof.

US Pat. No. 10,396,682

METHOD FOR OPERATING AN ELECTRICAL NETWORK

Dr. Ing. h.c. F. Porsche ...

1. A multilevel converter configured to be arranged in an electrical network, wherein the electrical network comprises a first subnetwork and a second subnetwork, wherein the two subnetworks are configured to be connected to one another via at least one transformer and are configured to be DC isolated from one another by said transformer, wherein a primary side of the at least one transformer having a first number of turns is configured to be assigned to the first subnetwork and a secondary side of the at least one transformer having a second number of turns is configured to be assigned to the second subnetwork, wherein the multilevel converter is configured to be arranged in the first subnetwork, the multilevel converter comprising:a plurality of single modules, wherein each single module has an electrical energy store, wherein the multilevel converter is configured to provide at least one first AC voltage and to modulate it with at least one second AC voltage, wherein accordingly at least one AC voltage resulting therefrom is provided to the at least one transformer and is transformed by the at least one transformer into at least one outgoing AC voltage and is provided to the second subnetwork; and
at least one associated additional energy store configured to provide the at east one second AC voltage.

US Pat. No. 10,396,681

MULTILEVEL INVERTERS WITH INCREASED NUMBER OF OUTPUT STEPS

King Abdulaziz University...

1. A power conversion system comprising:a multilevel inverter circuitry configured to
(a) arrange Nsource DC voltage sources in series between a positive terminal of a first one of the Nsource DC voltage source and a negative terminal of a last one of the Nsource DC voltage sources;
(b) connect at least Nsource?1 controlled switching devices to the Nsource DC voltage sources to ensure at least one of the at least Nsource?1 controlled switching devices is connected between any two adjacent DC voltage sources, to form an electrical path between the positive terminal of the first one of the Nsource DC voltage source and the negative terminal of the last one of the Nsource DC voltage source;
(c) connect at least another Nsource?1 controlled switching devices to the Nsource DC voltage sources to ensure at least one controlled switching device is connected between the negative terminal of the last one of the Nsource DC voltage sources and the negative terminal of any one of the other Nsource?1 DC voltage sources;
(d) provide at least another three controlled switching devices wherein at least one of at least another three controlled switching devices is connected between a positive terminal of the first one of the Nsource DC voltage source and a positive terminal of the second one of the NsourceDC voltage source, and at least two of the at least another three controlled switching devices are connected in series across the positive terminal and negative terminal of the first one of the Nsource DC voltage source; and
(e) connect an H-bridge circuit comprising at least four controlled switching devices between a negative terminal of the last DC voltage source and any common terminal of the controlled switching devices connected in series across the positive terminal and the negative terminal of the first of the at least Nsource?1 DC voltage source, to drive a current in both positive and negative directions to a load,
wherein a voltage levels provided by the others Nsource?1 DC voltage sources is twice a voltage level provided by the first one of the Nsource DC voltage sources, and
wherein a total number of a voltage levels Nstep provided by the Nsource DC voltage sources is determined according to Nstep=4Nsource?1.

US Pat. No. 10,396,679

RECTIFICATION CIRCUIT WITH TRANSISTOR CHANNEL AND DIODE CHANNEL

OSRAM SYLVANIA Inc., Wil...

1. A rectifying circuit, comprising:a first channel circuit to rectify a first input signal using a transistor, the transistor operatively coupled between an input of the first channel circuit and a node;
a comparator circuit operatively coupled with the transistor of the first channel circuit, the comparator circuit to control the transistor based on a difference between a representative voltage of the first input signal and a representative voltage of the node; and
a second channel circuit to rectify a second input signal using a diode, the diode operatively coupled between an input of the second channel circuit and the node;
wherein the transistor is a first transistor and the comparator circuit is operatively coupled with the first transistor by way of a second transistor, wherein the first transistor is controlled by the second transistor, and the second transistor is controlled by the comparator circuit.

US Pat. No. 10,396,674

FLYBACK POWER CONVERTER CIRCUIT AND PRIMARY SIDE CONTROLLER CIRCUIT THEREOF

RICHTEK TECHNOLOGY CORPOR...

1. A flyback power converter circuit, comprising:a transformer, having a primary side winding for receiving an input voltage; a secondary side winding for generating an output voltage; and an auxiliary winding for generating an auxiliary voltage and providing a controller supply voltage;
a primary side switch, coupled to the primary side winding and configured to operably control the primary side winding;
a high voltage (HV) start-up switch, wherein a current inflow terminal of the HV start-up switch is coupled to an input voltage related signal, and a current outflow terminal of the HV start-up switch is coupled to the controller supply voltage, wherein the input voltage related signal relates to the input voltage;
a protection sensing circuit, configured to operably sense a system temperature or an input signal to generate a protection sensing signal; and
a primary side controller circuit, which is located at a primary side of the transformer and powered by the controller supply voltage, and is configured to operably generate a switch control signal to control the primary side switch; the primary side controller circuit including:
a multi-function pin, which is coupled to a control terminal of the HV start-up switch and is coupled to the protection control circuit, wherein the multi-function pin is configured to operably control the HV start-up switch for start-up operation during a start-up stage and configured to operably receive the protection sensing signal after the start-up stage, wherein the start-up stage corresponds to a time period when the controller supply voltage does not exceed the start-up voltage threshold;
a high voltage (HV) start-up circuit, coupled to the control terminal of the HV start-up switch through the multi-function pin, wherein during the start-up stage, the HV start-up circuit controls the HV start-up switch to be ON, and after the start-up stage, the HV start-up circuit controls the HV start-up switch to be OFF; and
a protection control circuit, configured to operably receive the protection sensing signal through the multi-function pin, wherein after the start-up stage, the protection control circuit performs the protection operation according to whether the protection sensing signal exceeds a protection threshold.

US Pat. No. 10,396,669

POWER CONVERTER MEASURING THE AVERAGE RECTIFIED PRIMARY CURRENT

Russell Jacques, Hertfor...

1. A method of controlling a resonant power converter having a transformer, the transformer having a primary input winding and a secondary output winding, the method comprising:measuring the average full wave rectified alternating current through a resistor coupled in series with the primary input winding, using an active rectifier to full-wave rectify the voltage across the resistor;
comparing the measured average full wave rectified current to a reference level; and
controlling the switching frequency of the resonant power converter based on the difference between the average current and the reference level.

US Pat. No. 10,396,668

POWER CONVERTER

TOYOTA JIDOSHA KABUSHIKI ...

1. A power converter comprising:power conversion circuits connected in parallel; and
a cutoff switch provided in each of the power conversion circuits, the cutoff switch configured to cut off connection of corresponding one of the power conversion circuits from other power conversion circuit,
wherein the cutoff switches of the power conversion circuits are housed in a first module.

US Pat. No. 10,396,666

SYSTEMS AND METHODS FOR ADJUSTING ONE OR MORE THRESHOLDS IN POWER CONVERTERS

On-Bright Electronics (Sh...

1. A system controller for a power converter, the system controller comprising:a first current controller configured to receive a first input signal and generate a first output signal based at least in part on the first input signal;
a second current controller configured to receive a compensation signal and a second input signal and generate a second output signal based at least in part on the second input signal; and
a drive signal generator configured to receive the first output signal and the second output signal, generate a first drive signal based at least in part on the first output signal and the second output signal, and generate a second drive signal based at least in part on the first output signal and the second output signal;
wherein:
the first current controller is configured to, in response to the first input signal becoming equal to or larger than a first threshold, change the first output signal from a first logic level to a second logic level; and
the second current controller is configured to, in response to the second input signal becoming equal to or smaller than a second threshold, change the second output signal from the first logic level to the second logic level;
wherein the drive signal generator is configured to:
in response to the first output signal being at the first logic level and the second output signal being at the second logic level, generate, with or without a first delay, the first drive signal at a third logic level; and
in response to the first output signal being at the second logic level and the second output signal being at the first logic level, generate, with or without a second delay, the first drive signal at a fourth logic level, the fourth logic level being different from the third logic level;
wherein the second current controller is further configured to, under a continuous-conduction-mode,
in response to the compensation signal increasing in magnitude, increase the second threshold in magnitude; and
in response to the compensation signal decreasing in magnitude, decrease the second threshold in magnitude.

US Pat. No. 10,396,664

REDUNDANT POWER SUPPLY CONTROL CIRCUIT

PEGATRON CORPORATION, Ta...

1. A redundant power supply control circuit for providing a power to a load, comprising:a power isolating circuit, configured to receive at least one of a first power from a first power device and a second power from a second power device and configured to isolate the first power from the second power, wherein
when the first power is provided, the power isolating circuit outputs the first power as a main power and isolates the second power from the load, and when the first power is not provided, the power isolating circuit outputs the second power to the load; and
a soft start circuit, coupled to the power isolating circuit to receive the main power and being enabled after receiving the main power, so as to output the main power to the load,
wherein the power isolating circuit comprises:
a first isolating circuit, configured to receive the first power from the first power device and coupled to the soft start circuit, wherein
when the first power is provided, the first isolating circuit outputs the first power as the main power, and when the first power is not provided, the first isolating circuit disconnects a current path between the soft start circuit and the first power device,
wherein the first isolating circuit comprises:
a first switch circuit, having a first terminal configured to receive the first power, and a second terminal coupled to the soft start circuit; and
a first control circuit, having an input terminal configured to receive the first power, and an output terminal coupled to a control terminal of the first switch circuit to control turning-on and turning-off of the first switch circuit, wherein
when the first power is provided, the first control circuit generates a first switch signal to turn on the first switch circuit, or otherwise, the first control circuit generates the first switch signal to turn off the first switch circuit,
wherein the first switch circuit comprises:
a first P-type metal oxide semiconductor field effect transistor (P-type MOSFET), having a drain terminal coupled to the first terminal of the first switch circuit, and a source terminal coupled to the second terminal of the first switch circuit, wherein a parasitic diode is between the drain terminal and the source terminal of the first P-type MOSFET,
wherein the first control circuit comprises:
a first voltage dividing circuit, coupled between the input terminal of the first control circuit and a ground terminal and configured to divide a voltage of the first power to generate a second switch signal; and
a first regulating triode, having an anode terminal coupled to the ground terminal, a cathode terminal coupled to the output terminal of the first control circuit, and a control terminal configured to receive the second switch signal.

US Pat. No. 10,396,658

POWER SUPPLY PROTECTION CIRCUIT AND METHOD

JOULWATT TECHNOLOGY (HANG...

1. A power supply protection method for applying a power supply protection circuit,wherein the power supply protection circuit comprises a current control unit, a voltage feedback unit, and a current pull-up unit; the voltage feedback unit is connected to the current control unit, the voltage feedback unit obtains a feedback voltage of an output voltage and feeds back the feedback voltage to the current control unit, and the current control unit uses the feedback voltage to control the current control unit to regulate an output current; and
the current pull-up unit is connected to a feedback terminal of the voltage feedback unit, and the current pull-up unit provides the voltage feedback unit with a pull-up current to determine whether the feedback terminal of the voltage feedback unit is short-circuited,
the power supply protection circuit further comprising a regulating unit, an input terminal of the regulating unit being connected to the feedback terminal of the voltage feedback unit, and the regulating unit regulating the pull-up current of the current pull-up unit according to the feedback voltage, so as to determine whether the feedback terminal of the voltage feedback unit is short-circuited,
the regulating unit comprises a first operational amplifier, a first input terminal of the first operational amplifier receives a first reference signal, a second input terminal is connected to the feedback voltage, and an output terminal of the first operational amplifier is connected to the current pull-up unit, and
a first input terminal of the current control unit is connected to a second reference signal, and a voltage of the first reference signal is smaller than a voltage of the second reference signal,
wherein the power supply protection method comprises the following steps:
comparing the feedback voltage with the first reference signal;
if the feedback voltage is greater than the first reference signal, the regulating unit outputting a voltage lower than a lowest driving voltage of the current pull-up unit, and the current pull-up unit being disabled to provide the pull-up current;
if the feedback voltage is smaller than the first reference signal, the regulating unit outputting a voltage higher than the lowest driving voltage of the current pull-up unit, and the current pull-up unit providing the voltage feedback unit with the pull-up current according to the output voltage of the regulating unit;
determining a type of a short circuit according to a value of the output voltage of the regulating unit or the pull-up current; and
if the output voltage of the regulating unit reaches a maximum driving voltage or the pull-up current reaches a maximum pull-up current, the feedback terminal of the voltage feedback unit being short-circuited; otherwise, a load being short-circuited.