US Pat. No. 10,250,379

CLOCK RECOVERY DEVICE WITH SWITCHABLE TRANSIENT NON-LINEAR PHASE ADJUSTER

MICROSEMI SEMICONDUCTOR U...

1. A clock recovery device for recovering a master clock over a packet network from incoming synchronization packets, comprising:a controlled oscillator for generating an output clock;
a frequency locked loop for generating a control input for said controlled oscillator, said frequency locked loop being responsive to pure offset information obtained from said incoming synchronization packets;
a transient phase adjuster for extracting information from said incoming synchronization packets taking into account transit delays to effect fast frequency adjustment of said control input and to provide a phase adjustment input to said frequency locked loop, said transient phase adjuster being responsive to activate and de-activate commands;
a secondary phase path selectable in response to de-activation of said transient phase adjuster to provide a phase correction to said control input derived from said pure offset information; and
a multiplexer responsive to a select input to select a zero input for said secondary phase path when said transient phase adjuster is active and to select said pure offset information as an input to said secondary phase path when said transient phase adjuster is de-activated.

US Pat. No. 10,250,378

BASE STATION APPARATUS AND METHOD FOR CONTROLLING BASE STATION APPARATUS

NEC CORPORATION, Minato-...

1. A base station apparatus comprising:a radio equipment control that generates a first baseband signal including first data;
a first microwave apparatus that modulates the first baseband signal to a first microwave and transmits the first microwave by radio;
a second microwave apparatus that demodulates the received first microwave to the first baseband signal, then extracts a first clock from a cycle of the first data included in the first baseband signal, imports the first baseband signal in synchronization with the first clock, and plays back the first data; and
a radio equipment that modulates the first data played back by the second microwave apparatus to a first high-frequency signal,
wherein the second microwave apparatus outputs first dummy data instead of the played back first data when a frequency fluctuation amount of the first clock exceeds a predetermined range.

US Pat. No. 10,250,377

DEVICE AND METHOD FOR SUPPORTING CLOCK TRANSFER OF MULTIPLE CLOCK DOMAINS

HUAWEI TECHNOLOGIES CO., ...

1. A device for supporting clock transfer of a plurality of clock domains, comprising:an ith phase frequency detector in N phase frequency detectors configured to:
receive a clock signal from a clock source coupled to the ith phase frequency detector; and
send ith phase difference information between a common reference clock signal and the clock signal to an ith filter in N filters corresponding to the ith phase frequency detector;
the ith filter being configured to:
receive the ith phase difference information from the ith phase frequency detector;
convert the ith phase difference information into ith frequency difference information; and
send the ith frequency difference information to an ith clock reconstructor in N clock reconstructors corresponding to the ith filter; and
the ith clock reconstructor being configured to:
receive the ith frequency difference information from the ith filter;
reconstruct an ith network timing clock in the device according to the common reference clock signal and the ith frequency difference information; and
send the ith network timing clock to an ith clock domain interface in N clock domain interfaces, the N phase frequency detectors respectively coupled to N clock sources, at least two clock sources of the N clock sources do not comprising a same clock source, the N clock domain interfaces comprising a one-to-one correspondence with the N phase frequency detectors, the N filters and the N clock reconstructors, the N comprising an integer greater than or equal to two, and the i comprising an integer satisfying a condition 1?i?N.

US Pat. No. 10,250,376

CLOCK SUSTAIN IN THE ABSENCE OF A REFERENCE CLOCK IN A COMMUNICATION SYSTEM

ANALOG DEVICES, INC., No...

1. A slave node transceiver for low latency communication, comprising:upstream transceiver circuitry to receive a signal transmitted over a bus from an upstream device;
clock circuitry to generate a clock signal at the slave node transceiver based on sync portions of the signal, wherein timing of the receipt and provision of signals over the bus by the slave node transceiver is based on the clock signal;
peripheral device communication circuitry to provide output signals to one or more peripheral devices; and
sustain circuitry to determine that a predetermined number of sync portions have not been received in a predetermined time interval, and in response to the determination, cause the attenuation of the output signals.

US Pat. No. 10,250,375

CLOCK SYNCHRONIZATION

QUALCOMM Incorporated, S...

1. An apparatus comprising:a first circuit configured to:
generate a clock inhibit signal; and
generate a first clock divider reference signal and a second clock divider reference signal, wherein the first clock divider reference signal is phase offset with respect to the second clock divider reference signal and at least one cycle of the first clock divider reference signal and the second clock divider reference signal is inhibited when the clock inhibit signal is asserted; and
a second circuit configured to:
receive the first clock divider reference signal and the second clock divider reference signal;
select a clock signal from one of the first clock divider reference signal or the second clock divider reference signal based on a clock select signal; and
divide the selected clock signal in frequency to generate a divided clock signal, wherein the divided clock signal is based, at least in part, on the clock inhibit signal.

US Pat. No. 10,250,374

HARQ OPERATION WHEN TDD CELL AND FDD CELL ARE INCLUDED IN CARRIER AGGREGATION

LG ELECTRONICS INC., Seo...

1. A method for performing a hybrid automatic retransmit request (HARQ) operation, the method performed by a user equipment (UE) and comprising:determining, by the UE, a physical uplink control channel (PUCCH) format to be used,
wherein the UE is configured with a carrier aggregation (CA) including at least one time division duplex (TDD)-based cell and at least one frequency division duplex (FDD)-based cell,
wherein the at least one TDD-based cell is configured as a primary cell,
wherein the at least one FDD-based cell is configured as a secondary cell;
determining a number of HARQ ACK/NACK bits to be transmitted using the determined PUCCH format; and
generating and transmitting a PUCCH signal using the PUCCH format,
wherein a maximum number of cells included in the CA is limited such that the determined number of HARQ ACK/NACK bits does not exceed a maximum number of bits allowed in the PUCCH format if an uplink-downlink (UL-DL) configuration of the at least one TDD-based cell corresponding to the primary cell corresponds to one of UL-DL configurations 2, 3 or 4, and if the at least one FDD-based cell is configured as the secondary cell.

US Pat. No. 10,250,373

SEQUENCE GENERATION AND TRANSMISSION METHOD BASED ON TIME AND FREQUENCY DOMAIN TRANSMISSION UNIT

LG Electronics Inc., Seo...

1. A method of transmitting, by a user equipment including a processor and a transmitter, control information to a base station in a wireless communication system, the method comprising:determining, by the processor, an information symbol s representing an acknowledgement (ACK)/negative acknowledgement (NACK), for an Automatic Repeat Request (ARQ)-based protocol, that is to be transmitted to the base station;
determining, by the processor, a frequency direction sequence c(k)={c(0), c(1), . . . , c(Nk?1)} having a length Nk that corresponds to a number of subcarriers included in a resource block allocated for an uplink control channel;
generating, by the processor, Nk information symbols s(k) that correspond to a product of the information symbol s with the frequency direction sequence c(k), where s(k)=s*c(k), for k=0, . . . , Nk?1;
determining, by the processor, a time direction sequence x(n)={x(0), x(1), . . . , x(Nn?1)} having a length Nn, that corresponds to a number of orthogonal frequency division multiplexing (OFDM) symbols allocated for transmission of the ACK/NACK in a transmission time interval on the uplink control channel;
generating, by the processor, Nk*Nn information symbols s(k, n) that correspond to a product of the Nk information symbols s(k) with the time direction sequence x(n), where s(k, n)=s(k)*x(n), for n=0, . . . , Nn?1;
mapping, by the processor, the Nk*Nn information symbols s(k,n) to Nk*Nn frequency-time resources, respectively, that are provided by Nk subcarriers in a frequency domain and Nn OFDM symbols in a time domain; and
transmitting, by the transmitter to the base station, the Nk*Nn information symbols s(k, n) using the Nk*Nn frequency-time resources through the uplink control channel in the transmission time interval.

US Pat. No. 10,250,372

COMPONENT CARRIER (DE)ACTIVATION IN COMMUNICATION SYSTEMS USING CARRIER AGGREGATION

Sun Patent Trust, New Yo...

1. A communication apparatus comprising:a receiver which, in operation, receives a MAC control element including bits which indicate an activation/deactivation status of each of at least one secondary component carrier added to a primary component carrier, which is always activated, each of the at least one secondary component carrier corresponding to one of the bits that indicates whether the secondary component carrier should be activated or deactivated, wherein the MAC control element includes trigger bits which indicate activation/deactivation of sounding reference signal (SRS) transmission, and when any one of the bits indicates that its corresponding secondary component carrier should be activated, the SRS transmission on the corresponding secondary component carrier is triggered according to the trigger bits;
control circuitry which, in operation, activates or deactivates each of the at least one secondary component carrier according to the received MAC control element; and
a transmitter which, in operation, starts an SRS transmission on the activated secondary component carrier(s).

US Pat. No. 10,250,371

DMRS SIGNAL TRANSMISSION METHOD AND APPARATUS

Huawei Technologies Co., ...

1. A signal transmission method, comprising:determining, by a base station, a first parameter value of a user data resource element (RE), an initial parameter value of a demodulation reference signal resource element (DMRS RE), and a compensation parameter value of the DMRS RE, wherein the user data RE is used to carry user data, the first parameter value is used to indicate that the base station transmits the user data using the first parameter value, and the DMRS RE is used to carry a demodulation reference signal (DMRS); the first parameter value comprises a first amplitude value, the initial parameter value comprises an initial amplitude value, and the compensation parameter value comprises an amplitude compensation value;
determining, by the base station according to the initial parameter value and the compensation parameter value, a second parameter value required for transmitting the DMRS; and
transmitting, by the base station, the DMRS, the user data, and the compensation parameter value to user equipment, to enable the user equipment to compute, according to the compensation parameter value and a preset initial parameter value, the DMRS transmitted by the base station using the second parameter value, and to enable the user equipment to obtain a DMRS RE channel estimation value according to the received DMRS and the computed DMRS, and to enable the user equipment to perform interpolation filtering on the DMRS RE channel estimation value to obtain channel information of the user data RE, and further to enable the user equipment to demodulate the user data according to the channel information of the user data RE;
wherein the determining, by a base station, a first parameter value of a user data resource element (RE), an initial parameter value of a demodulation reference signal resource element (DMRS RE), and a compensation parameter value of the DMRS RE, comprises:
determining, by the base station, the first parameter value of the user data RE, the initial parameter value of the DMRS RE, and the compensation parameter value of the DMRS RE according to network configuration information of the base station, wherein the network configuration information comprises a channel estimation algorithm of the user equipment.

US Pat. No. 10,250,370

FRAME STRUCTURE FOR A PHYSICAL CONTROL CHANNEL

Huawei Technologies Co., ...

1. A method for operating an access point comprising:communicating a frame between the access point and at least one station (STA), the frame including at least a first preamble, a first payload, a second preamble, and a second payload, the first preamble including at least a legacy short training field (STF), the second preamble including at least a first STF, the legacy STF being orthogonal to the first STF.

US Pat. No. 10,250,369

BEAM SWITCHING AND RECOVERY

QUALCOMM Incorporated, S...

1. A method of wireless communication for a first device, comprising:transmitting a beam switch message (BSM) to a second device via a first beam set, the BSM including a command to switch from communication via the first beam set to communication via a second beam set at a switch time;
when a response message to the BSM is unreceived, monitoring for communications from the second device via both the second beam set and the first beam set after the switch time; and
in response to the monitoring: maintaining the first beam set for communication with the second device if a message on the first beam set is received from the second device after the switch time; or maintaining the second beam set for communication with the second device if a message on the second beam set is received from the second device.

US Pat. No. 10,250,368

METHOD FOR CONTROLLING UPLINK TRANSMISSION POWER AND WIRELESS DEVICE USING SAME

LG ELECTRONICS INC., Seo...

1. A method for uplink transmission in a wireless communication system, the method comprising:determining, by a user equipment (UE), whether a first uplink signal to be transmitted toward a first cell belonging to a first timing advance group (TAG) at an nth subframe overlaps a second uplink signal to be transmitted toward a second cell belonging to a second TAG at an (n+1)st subframe;
dropping, by the UE. the first uplink signal at the nth subframe, if a total transmission power including the first and second uplink signals exceeds a maximum transmit power, where n is an integer?1; and
transmitting the second uplink signal without the first uplink signal.

US Pat. No. 10,250,367

UPLINK MIMO STBC COMMUNICATION METHOD IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS FOR SAME

LG Electronics Inc., Seo...

9. A user equipment (UE) in a wireless communication system supporting multi-antenna, the UE comprising:a transmitter; and
a processor, operatively coupled to the transmitter,
wherein the processor:
maps first demodulation reference signals (DMRSs) for a first antenna port to a first Orthogonal Frequency Division Multiplexing (OFDM) symbol having a lowest OFDM symbol index in a subframe, wherein the first OFDM symbol is used for Automatic Gain Control (AGC),
maps second DMRSs for a second antenna port to a second OFDM symbol different from the first OFDM symbol,
maps data received from a plurality of antenna ports to one or more OFDM symbols of the subframe other than the first and second OFDM symbols according to a Space-Time Block Code (STBC) scheme,
controls the transmitter to transmit the subframe using a resource allocated for uplink,
wherein, when the one or more OFDM symbols is an odd number of symbols, the second DMRSs for the second antenna port are additionally mapped to a third OFDM symbol among the one or more OFDM symbols, and
wherein the first and second antenna ports are included in the plurality of antenna ports.

US Pat. No. 10,250,366

METHOD FOR TRANSMITTING AND RECEIVING REFERENCE SIGNAL IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR

LG ELECTRONICS INC., Seo...

1. A method for transmitting, by a base station, a demodulation reference signal (DMRS) in a wireless communication system, the method comprising:generating a sequence of the DMRS;
mapping the sequence of the DMRS into resource elements of each of layers; and
transmitting the sequence of the DMRS mapped into the resource elements through antenna ports related to the layers,
wherein when a number of the layers exceeds a predetermined number, the sequence of the DMRS is mapped into the resource elements based on a pattern on at least two bundled consecutive resource blocks, and the layers are allocated to antenna port groups alternately, and
wherein when the number of the layers does not exceed the predetermined number, the layers are allocated to the antenna ports sequentially based on antenna port indexes.

US Pat. No. 10,250,365

SYSTEMS AND METHODS FOR SIGNAL CLASSIFICATION

Intel Corporation, Santa...

21. A wireless apparatus, comprising:at least one memory storing computer-executable instructions; and
at least one processor to access the at least one memory, wherein the at least one processor is to execute the computer-executable instructions to:
receive a high efficiency (HE) packet having a physical layer (PHY) preamble, the PHY preamble including a legacy short training field (L-STF), a legacy long training field (L-LTF) immediately following the L-STF, a legacy signal field (L-SIG) immediately following the L-LTF, a repeated signal field (RL-SIG) immediately following the L-SIG, a high efficiency signal field (HE-SIG) immediately following the RL-SIG, a high efficiency short training field (HE-STF) immediately following the HE-SIG, a high efficiency long training field (HE-LTF) immediately following the HE-STF, wherein:
the L-SIG includes a rate field and a length field;
the HE-SIG includes a first high efficiency signal symbol (HE-SIG-1) and a second high efficiency signal symbol (HE-SIG-2);
the RL-SIG is a repetition of the L-SIG; and
a value of the length field of the L-SIG is not divisible by three;
identify the packet as a HE packet based on determining the repetition and based on determining that the value of the length field is not divisible by three.

US Pat. No. 10,250,364

CHANNEL MEASUREMENTS SUPPORTING COORDINATED MULTI-POINT OPERATION

Nokia Corporation, Espoo...

1. A method, comprising:assigning a first set of channel state information reference signal resources to individual ones of a plurality of transmission points that are located within a cell and assigning a second set of channel state information reference signal resources to individual ones of the plurality of transmission points located within the cell, where the first set is equal to or smaller than the second set;
signaling information that describes at least one of the first and the second sets of the channel state information reference signal resources to a user equipment;
receiving a channel state information report from the user equipment, the channel state information report comprising information that describes a measurement made by the user equipment of at least one of the plurality of transmission points using a configuration based on the first set of channel state information reference signal resources, and alternatively the second set of channel state information reference signal resources, and alternatively both the first set of channel state information reference signal resources and the second set of channel state information reference signal resources, where the measurement made using the second set of channel state information reference signal resources is a simplified measurement occurring less frequently than a measurement corresponding to the first set of channel state information reference signal resources, where the simplified measurement is simplified compared to the measurement corresponding to the first set of channel state information reference signal resources; and
triggering the user equipment to make the measurement.

US Pat. No. 10,250,363

COMMUNICATION SYSTEM WITH EXPANDABLE CAPACITY

ENTROPIC COMMUNICATIONS, ...

1. A method, comprising:determining traffic conditions on a network;
depending on the traffic conditions, adjusting bit loading on a legacy channel and at least one of newly added channels of the network to maintain legacy node operability in the network,
wherein newly added channels are added without a frequency gap, and
wherein adjusting the bit loading comprises:
operating the legacy channel at a full order of modulation; estimating an imbalance based on a probe;
lowering the bit loading of the legacy channel to operate at a lowered order of modulation; and
increasing the bit loading of the newly added channels.

US Pat. No. 10,250,362

METHOD AND APPARATUS FOR NON-ORTHOGONAL ACCESS IN LTE SYSTEMS

InterDigital Patent Holdi...

1. A method implemented in a User Equipment (UE) for transmitting payload data to a wireless network asynchronously, the method comprising:generating payload data for uplink transmission to the network;
selecting between transmitting the payload data to the network on a synchronous physical uplink channel or on an asynchronous physical uplink channel; and
transmitting the payload data on the selected physical channel;
wherein the synchronous physical uplink shared channel is a channel on which a timing alignment procedure is performed prior to transmitting the payload data and the asynchronous physical uplink channel is a channel on which a timing alignment procedure is not performed prior to transmitting the payload data.

US Pat. No. 10,250,361

METHOD AND APPARATUS FOR TRANSMITTING DATA UNIT COMPRISING GUARD INTERVALS HAVING DIFFERENT LENGTHS

LG ELECTRONICS INC., Seo...

1. A method for transmitting a data unit in a wireless local area network (WLAN) system, the method comprising:generating, by a transmission station (STA), a PHY protocol data unit (PPDU); and
transmitting, by the transmission STA, the PPDU to a plurality of reception STAs,
wherein the PPDU sequentially includes a legacy-signal (L-SIG) field, a high efficiency signal A (HE-SIG A) field, a HE-SIG B field, and a training field,
wherein the L-SIG field is generated based on a first inverse fast Fourier transform (IFFT) size and transmitted on a first orthogonal frequency division multiplexing (OFDM) symbol, wherein a first symbol duration of the first OFDM symbol includes a first guard interval (GI) duration determined based on the first IFFT size and a first valid symbol duration determined based on the first IFFT size,
wherein the HE-SIG A field is generated based on the first IFFT size and transmitted on a second OFDM symbol, wherein a second symbol duration of the second OFDM symbol includes a second GI duration which is integer times longer than the first GI duration and the first valid symbol duration,
wherein the HE-SIG B field is generated based on the first IFFT size and transmitted on a third OFDM symbol, wherein a third symbol duration of the third OFDM symbol includes the second GI duration and the first valid symbol duration,
wherein the training field is generated based on a second IFFT size and transmitted on a fourth OFDM symbol, wherein a fourth symbol duration of a fourth OFDM symbol includes a third guard interval (GI) duration determined based on the second IFFT size and a second valid symbol duration determined based on the second IFFT size, and
wherein the second IFFT size is integer times larger than the first IFFT size.

US Pat. No. 10,250,360

METHODS AND DEVICES FOR SUB-BLOCK DECODING DATA SIGNALS

INSTITUT MINES-TELECOM, ...

1. A decoder for decoding a signal received through a transmission channel in a communication system, said signal comprising a vector of information symbols, wherein the decoder comprises:a processing unit configured to determine at least one candidate set of division parameters and to perform a division of said vector of information symbols into a set of sub-vectors in association with each candidate set of division parameters, each pair of sub-vectors being associated with a division metric;
a selection unit configured to select one of said candidate sets of division parameters according to a selection criterion depending on said division metric; and
a decoding unit configured to determine at least one estimate of each sub-vector associated with said selected set of division parameters by applying a symbol estimation algorithm,wherein the decoder is configured to determine at least one estimate of the vector of information symbols from said at least one estimate of each sub-vector of information symbols.

US Pat. No. 10,250,359

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A mapping method of a transmitting apparatus, comprising:encoding, using at least one hardware processor, input bits to generate parity bits based on a low density parity check (LDPC) code;
interleaving, using at least one hardware processor, a codeword comprising the input bits and the parity bits; and
mapping, using at least one hardware processor, bits of the interleaved codeword onto constellation points for 256-quadrature amplitude modulation (QAM),
wherein the constellation points comprise constellation points as represented in a list below:
0.0899+0.1337i
0.0910+0.1377i
0.0873+0.3862i
0.0883+0.3873i
0.1115+0.1442i
0.1135+0.1472i
0.2067+0.3591i
0.1975+0.3621i
0.1048+0.7533i
0.1770+0.7412i
0.1022+0.5904i
0.1191+0.5890i
0.4264+0.6230i
0.3650+0.6689i
0.3254+0.5153i
0.2959+0.5302i
0.3256+0.0768i
0.3266+0.0870i
0.4721+0.0994i
0.4721+0.1206i
0.2927+0.1267i
0.2947+0.1296i
0.3823+0.2592i
0.3944+0.2521i
0.7755+0.1118i
0.7513+0.2154i
0.6591+0.1033i
0.6446+0.1737i
0.5906+0.4930i
0.6538+0.4155i
0.4981+0.3921i
0.5373+0.3586i
0.1630+1.6621i
0.4720+1.5898i
0.1268+1.3488i
0.3752+1.2961i
1.0398+1.2991i
0.7733+1.4772i
0.8380+1.0552i
0.6242+1.2081i
0.1103+0.9397i
0.2415+0.9155i
0.1118+1.1163i
0.3079+1.0866i
0.5647+0.7638i
0.4385+0.8433i
0.6846+0.8841i
0.5165+1.0034i
1.6489+0.1630i
1.5848+0.4983i
1.3437+0.1389i
1.2850+0.4025i
1.2728+1.0661i
1.4509+0.7925i
1.0249+0.8794i
1.1758+0.6545i
0.9629+0.1113i
0.9226+0.2849i
1.1062+0.1118i
1.0674+0.3393i
0.7234+0.6223i
0.8211+0.4860i
0.8457+0.7260i
0.9640+0.5518i.

US Pat. No. 10,250,358

TRANSMITTER AND RECEIVER FOR TRANSMITTING BASIC CODEWORD PORTION AND AUXILIARY CODEWORD PORTION OF A CODEWORD IN DIFFERENT FRAMES

SATURN LICENSING LLC, Ne...

1. A receiver for receiving data, comprising:circuitry configured to:receive a receiver input data stream segmented into frames, including a first frame and a second frame;
extract a basic codeword portion of a codeword from the first frame and extract an auxiliary codeword portion of the codeword from the second frame, the basic codeword portion being generated from one or more input data words according to a first coding scheme, and the auxiliary codeword portion being generated from the one or more input data words according to a second coding scheme;
buffer the auxiliary codeword portion;
perform a first error correction process on the basic codeword portion according to at least the first coding scheme to generate one or more output data words of at least one output data stream that correspond to the one or more input data words;
when a result of the first error correction process is erroneous, perform a second error correction process on the basic codeword portion and the auxiliary codeword portion according to at least the second coding scheme to generate the one or more output data words; and
output the at least one output data stream that includes the one or more output data words; wherein the first frame includes one or more first preamble symbols followed by one or more first data symbols, and the second frame includes one or more second preamble symbols followed by one or more second data symbols.

US Pat. No. 10,250,357

APPARATUS FOR TRANSMITTING AND RECEIVING A SIGNAL AND METHOD FOR TRANSMITTING AND RECEIVING A SIGNAL

LG ELECTRONICS INC., Seo...

1. A method for transmitting a signal, the method comprising:encoding data for forward error correction to generate first data and second data based on different code rates;
interleaving the first data and the second data, respectively;
demultiplexing the interleaved first data and the interleaved second data, respectively,
wherein the interleaved first data and the interleaved second data are reordered to demultiplexed first data and demultiplexed second data, respectively, based on different symbol mapping methods and the different code rates;
mapping the demultiplexed first data into mapped first data based on a first symbol mapping method of the different symbol mapping methods, and mapping the demultiplexed second data into mapped second data based on a second symbol mapping method of the different symbol mapping methods;
building a signal frame including physical layer pipe (PLP) data that carries the mapped first data and the mapped second data,
wherein the PLP data includes a combination of the mapped first data and the mapped second data which are generated based on the different symbol mapping methods and the different code rates, and
wherein the mapped first data and the mapped second data are combined with different power levels;
modulating the signal frame according to an orthogonal frequency division multiplexing (OFDM) scheme; and
transmitting the modulated signal frame.

US Pat. No. 10,250,356

NOTIFICATION METHOD AND APPARATUS FOR CHANNEL QUALITY INDICATOR AND MODULATION AND CODING SCHEME

Huawei Technologies Co., ...

1. A notification method for a channel quality indicator (CQI) comprising:acquiring a first CQI index according to an acquired first CQI table; and
sending the first CQI index to a base station,
wherein the first CQI table comprises:
multiple entries in which modulation schemes are higher than 64 quadrature amplitude modulation (QAM);
multiple entries in a second CQI table and in which modulation schemes are quadrature phase shift keying (QPSK); and
all entries that are in the second CQI table and in which modulation schemes are 16QAM;
wherein the second CQI table comprises 6 entries in which the modulation schemes are QPSK, the 6 entries are associated with CQI indices 1 to 6, respectively, and entries associated with CQI indices 3, 4, 5, and 6 in the second CQI table are entries in which code rates are highest in the 6 entries;
wherein a combination formed by the multiple entries in which the modulation schemes are QPSK in the first CQI table, is neither a combination of the entries associated with CQI indices 4, 5 and 6 in the second CQI table, nor a combination of the entries associated with CQI indices 3, 4, 5 and 6 in the second CQI table; and
wherein modulation schemes in entries in the second CQI table comprise only QPSK, 16QAM, and 64QAM, and a value range of a CQI index in the first CQI table is the same as a value range of a CQI index in the second CQI table.

US Pat. No. 10,250,355

APPARATUS, SYSTEM AND METHOD OF MULTI-USER WIRELESS COMMUNICATION

Intel IP Corporation, Sa...

12. A method to be performed at a wireless device including:processing an Extended Directional Multigigabit (EDMG) Multi-User (MU) Physical Layer Convergence Protocol Data Unit (PPDU) for a MU transmission, the PPDU comprising a header portion and a data portion, the data portion including a plurality of Media Access Control (MAC) Protocol Data Units (MPDUs) in a plurality of Spatial Streams (SSs) and addressed to a plurality of wireless stations (STAB), wherein:
the header portion indicates a modulation scheme for the MU transmission, the modulation scheme including a Single Carrier (SC) modulation scheme or an Orthogonal Frequency Division Multiplexing (OFDM) modulation scheme;
the header portion includes a legacy header, and a non-legacy header following the legacy header, the non-legacy header including a first non-legacy header EDMG-Header A, and a second non-legacy header EDMG-Header B, the EDMG-Header B indicating a plurality of Modulation and Coding Schemes (MCSs) on a per SS basis;
determining from the header portion whether the modulation scheme for the MU transmission is a SC modulation or an OFDM modulation;
using a decoding chain based on the modulation scheme to demodulate the MU transmission; and
demodulating the SSs according to the MCSs.

US Pat. No. 10,250,354

SYSTEMS AND METHODS FOR WAVEFORM SELECTION AND ADAPTATION

Huawei Technologies Co., ...

1. A method for data transmission, the method comprising:receiving, by a first user equipment (UE) from a transmit point (TP), an indication dynamically indicating a first waveform of at least two waveforms to use for a first data transmission; and
transmitting, by the first UE to the TP, the first data transmission using the first waveform over an uplink channel in accordance with grant based transmission of two transmission selections, the grant based transmission requiring the first UE to receive a resource grant for the first data transmission from the TP prior to transmitting the first data transmission over the uplink channel, wherein the at least two waveforms further include a second waveform that is different than the first waveform, the second waveform for transmitting a second data transmission over the uplink channel, and the two transmission selections comprising grant less transmission, the grant less transmission allowing the first UE to transmit the second data transmission over the uplink channel without receiving a resource grant for the second data transmission from the TP prior to transmitting the second data transmission over the uplink channel, wherein the uplink channel is a set of time frequency resources for carrying data transmissions from one or more UEs to the TP.

US Pat. No. 10,250,353

ELECTROMAGNETIC SIGNAL TRANSPORT AND DISTRIBUTION SYSTEMS

PERFECTVISION MANUFACTURI...

1. A signal transport and distribution system serving users with internet and satellite television services comprising:in a multi-dwelling building, a DBS end, a dispatch block, and a user end;
the dispatch block interconnecting the DBS end and the user end;
an internet service provider passive optical network interconnected with the dispatch block via an OLT;
in the dispatch block a switch for receiving DBS signals via plural coaxial cables interconnected with a DBS low noise block;
the switch configured to simultaneously deliver multiple channels of multimedia content at a switch coaxial output port in response to requests received from a plurality of set top boxes;
a splitter that uses y output ports to couple the switch coaxial output to each of y dispatch block transceivers;
in each of y dwelling units a dwelling unit transceiver having a coaxial port and two optical ports;
a coaxial cable interconnecting the transceiver and a single or multiple tuner set top box;
an optical cable interconnecting the transceiver and an ONU; and,
for each dispatch block transceiver, a single mode fiber optic cable interconnecting the transceiver with a respective dwelling unit transceiver;
wherein dwelling units simultaneously receive content of their choice as requested via their respective set top boxes and simultaneously exchange data with a public network.

US Pat. No. 10,250,352

OPTICAL RECEIVER AND METHOD OF MONITORING OPTICAL POWER OF OPTICAL SIGNAL INPUT THERETO

SUMITOMO ELECTRIC INDUSTR...

1. An optical receiver that receives a wavelength-multiplexed optical signal multiplexing two or more optical signals having wavelengths different from each other, the optical receiver comprising:an optical receiver module including two or more photodiodes and a switch, the photodiodes converting the optical signals into photocurrents, the switch sequentially selecting the photocurrents for output by the optical receiver;
a current-to-voltage converter that includes a resistive element having variable resistance, the resistive element causing voltage drops corresponding to the photocurrents output from the optical receiver and flowing therein; and
a controller that controls the switch to sequentially select the photocurrents to evaluate power of the optical signals by the voltage drops, and that sets the variable resistance to one of a first resistance and a second resistance, the second resistance being 10 to 15 times greater than the first resistance,
wherein the current-to-voltage converter converts the photocurrents by the second resistance of the resistive element when at least one of the voltage drops generated by the first resistance is less than a preset voltage, and
wherein, when the current-to-voltage converter once sets the variable resistance of the resistive element to the second resistance for one of the photocurrents, the current-to-voltage converter generates the voltage drops by setting the variable resistance in the second resistance for the rest of the photocurrents.

US Pat. No. 10,250,351

EFFICIENT NETWORK UTILIZATION USING OPTICALLY SWITCHED SUPERCHANNELS

Futurewei Technologies, I...

1. A method for constructing an optical network, the method comprising:connecting each node of a set of nodes of a plurality of nodes in an optical network to an all optical switching central node via a set of optical superchannels, the optical network having one or more processors in communication with one or more memory storages to execute operations to manage configuration of the optical network and to route and assign spectrum for the set of optical superchannels of the optical network, wherein each of the optical superchannels includes a set of service bandwidth subchannels and each optical superchannel has a bounded data rate, and each node of the set of nodes includes one or more transponders to implement the optical superchannels connected to the node and a processor with associated memory to process the subchannels of the connected optical superchannel and control the one or more transponders to respond to traffic requests; and
wherein the all optical switching central node is configured with one or more wavelength selective switches to perform spectrum selective switching among the subchannels of these optical superchannels at the all optical switching central node.

US Pat. No. 10,250,350

OPTICAL SWITCH, OPTICAL ADD-DROP MULTIPLEXER, COMMUNICATION NETWORK NODE AND COMMUNICATION NETWORK

Telefonaktiebolaget LM Er...

1. An optical switch comprising:a plurality of input ports each arranged to receive optical signals from a different one of a plurality of directions;
a plurality of output ports each arranged to output optical signals to the different one of the plurality of directions;
a plurality of drop ports;
a plurality of add ports;
a first switch array arranged to receive from a first said input port optical signals at a plurality of wavelengths, the first switch array comprising a plurality of switch elements each arranged to selectively direct optical signals at a different one of said plurality of wavelengths to a different one of the plurality of drop ports;
a plurality of optical filters each arranged to receive the optical signals having wavelengths that are not selectively dropped by the plurality of switch elements of the first switch array and passed through the first switch array, each optical filter arranged to transmit to a respective one of the output ports optical signals at different ones of said wavelengths passed through the first switch array; and
a second switch array arranged to receive from the other said input ports optical signals at some of said plurality of wavelengths, the second switch array comprising a plurality of switch elements each arranged to selectively add optical signals received from a different one of the plurality of add ports at a different one of others of said plurality of wavelengths.

US Pat. No. 10,250,349

COORDINATED INTERFERENCE CANCELLATION IN WIRELESS NETWORK

Nokia Solutions and Netwo...

1. A method comprising:receiving, by a user device, a first signal including a first user device-specific signal from a base station and one or more interfering signals, the first user device-specific signal being received based on a first modulation and coding scheme (MCS);
determining, by the user device, whether the user device can perform interference cancellation for the one or more interfering signals, based at least in part on whether the user device can decode the one or more interfering signals;
sending, by the user device to the base station, an interference cancellation feedback message including at least, for each of the one or more interfering signals, an interference cancellation capability indication that indicates whether or not the user device can perform interference cancellation for the interfering signal;
receiving an updated MCS, wherein the updated MCS is based, at least in part, on the interference cancellation feedback message; and
receiving, by the user device based on the updated MCS, a second signal including at least a second user device-specific signal in which at least one of a signal muting or an interference cancellation is performed for at least one of the interfering signals.

US Pat. No. 10,250,348

OPTICAL TRANSPORT SYSTEM AND RESOURCE OPTIMIZATION METHOD

NIPPON TELEGRAPH AND TELE...

1. An optical transport system comprising:a time-multiplexing processing unit that time-multiplexes a plurality of client signals and accommodates the client signals in any of a plurality of time slots included in one transport frame;
a time slot control unit that determines, when the time-multiplexing processing unit time-multiplexes the plurality of client signals, which of the plurality of time slots each of the client signals is to be accommodated in;
a transport frame generation unit that divides the transport frame in which the plurality of client signals are accommodated into a plurality of transmission signals;
a plurality of subcarrier transmission units that are provided for the transmission signals and convert the plurality of transmission signals which are electric signals into optical signals using different optical carriers, and transmit the converted optical signals;
a plurality of subcarrier reception units that are provided corresponding to the plurality of subcarrier transmission units and receive the optical signals transmitted from the corresponding subcarrier transmission units, and convert the optical signals into reception signals;
a transport frame termination unit that combines the reception signals converted by the plurality of subcarrier reception units to restore the transport frame;
a time-demultiplexing processing unit that time-demultiplexes the transport frame restored by the transport frame termination unit to be separated into the plurality of client signals; and
a power source control unit that controls supply of electric power to the plurality of subcarrier transmission units and the plurality of subcarrier reception units,
wherein when a value obtained by calculating (the number of used subcarriers)?((the number of time slots to which the plurality of client signals are allocated)/(the number of time slots per subcarrier)) is equal to or greater than 1, the time slot control unit determines a new allocation that accommodates the plurality of client signals sequentially from a time slot corresponding to any one of a plurality of subcarriers without proving an empty time slot, notifies the time-multiplexing processing unit and the time-demultiplexing processing unit of the new allocation, and causes the power source control unit to stop the supply of electric power to a subcarrier transmission unit and a subcarrier reception unit that transmit and receive an optical signal to which the client signals are not allocated.

US Pat. No. 10,250,347

ROUTING-EFFICIENT TIME DIVISION MULTIPLEXING (TDM) DATA PATH CIRCUITRY

ALTERA CORPORATION, San ...

1. Time division multiplexing (TDM) circuitry, comprising:a first rotary multiplexer circuit configured to receive N-bit wide data in accordance to a time division multiple access (TDMA), wherein the N-bit wide data comprises multiple sets of M-bit wide data, and wherein the first rotary multiplexer circuit is configured to:
receive a first set of M-bit wide data, a second set of M-bit wide data, and a third set of M-bit wide data of the multiple sets of M-bit wide data;
rotate the second set of M-bit wide data by a first shifting factor to generate a corresponding second rotated set of M-bit wide data;
rotate the third set of M-bit wide data by a second shifting factor to generate a corresponding third rotated set of M-bit wide data; and
a memory circuit coupled to the first rotary multiplexer circuit, wherein the memory circuit is configured to store the first set of M-bit wide data, the second rotated set of M-bit wide data, and the third rotated set of M-bit wide data.

US Pat. No. 10,250,346

PILOT SIGNAL IN AN FDMA COMMUNICATION SYSTEM

Apple Inc., Cupertino, C...

1. A single carrier frequency division multiple access (SC-FDMA) transmitter included in a subscriber unit of a cellular communications system, the SC-FDMA transmitter comprising:signal processing circuitry, comprising:
a pilot sequence generator configured to generate a serial pilot sequence;
a serial-to-parallel converter configured to convert the serial pilot sequence to a parallel pilot sequence; and
a SC-FDMA modulator configured to modulate an input sequence, wherein the SC-FDMA modulator is a multi-carrier modulation block configured to generate at least a subset of a plurality of orthogonal subcarriers, wherein the input sequence comprises the parallel pilot sequence, wherein the parallel pilot sequence is mapped to the at least a subset of the plurality of subcarriers, wherein the parallel pilot sequence is reused by a plurality of different SC-FDMA transmitters_corresponding to a plurality of subscriber units, and wherein the parallel pilot sequence is mapped to different respective subcarriers of the plurality of subcarriers by the plurality of different SC-FDMA transmitters to estimate respective channels between the respective SC-FDMA transmitters and a common receiver using the same parallel pilot sequence for the plurality of different SC-FDMA transmitters, wherein output of the SC-FDMA modulator includes an added cyclic prefix, and wherein the SC-FDMA modulator is further configured to provide the output to a transmitter block for transmission.

US Pat. No. 10,250,345

METHOD AND APPARATUS FOR DISTRIBUTION OF MEDIA CONTENT VIA MULTIPLE ACCESS TECHNOLOGIES

1. A method comprising:providing to a first satellite receiver system, at a first location of a plurality of locations, a satellite signal including media content, wherein the first satellite receiver system is configured to be in operative communication with a first wireless transceiver at the first location;
providing by the first satellite receiver system to the first wireless transceiver, based upon the satellite signal, a first media content bearing signal, wherein the first media content bearing signal comprises the media content;
selecting, as a target wireless transceiver, one of a second wireless transceiver at a second location of the plurality of locations and a third wireless transceiver at a third location of the plurality of locations; and
providing by the first wireless transceiver to the target wireless transceiver that is configured to be in operative communication with the first wireless transceiver, based upon the first media content bearing signal, a second media content bearing signal, wherein the second media content bearing signal comprises the media content and wherein the second media content bearing signal is communicated wirelessly from the first wireless transceiver to the target wireless transceiver,
wherein the selecting is based upon:
a first available bandwidth of the second wireless transceiver to forward the media content to a fourth wireless transceiver located at one of the plurality of locations; and
a second available bandwidth of the third wireless transceiver to forward the media content to the fourth wireless transceiver.

US Pat. No. 10,250,344

BROADCAST OF AUDIO DATA BASED ON INPUT BROADCAST SIGNALS STORED DURING A DETECTED ANOMALY PERIOD BY LIGHTNING ENERGY

Kabushiki Kaisha Toshiba,...

1. A broadcast continuation assistance device, comprising:a memory that stores broadcast audio data corresponding to input broadcast audio signals in a chronological order; and
an output unit that receives an anomaly detection signal during an anomaly detection period, reads, from the memory, the broadcast audio data corresponding to the broadcast audio signals stored in the memory during the anomaly detected period by lightning energy, and transmits, as radio signals, the broadcast audio signals corresponding to the read broadcast audio data after an anomaly is resolved.

US Pat. No. 10,250,343

TECHNIQUE FOR MEASURING REFERENCE SIGNAL RECEIVED POWER

Telefonaktiebolaget LM Er...

1. A method of measuring Reference Signal Received Power (RSRP) based on Cell-specific Reference Signals (CRSs) provided by cells of a mobile telecommunications network, wherein the CRSs of at least two of the cells overlap in time and frequency, the method comprising:determining a time offset for sub-frames received from the at least two cells;
receiving the overlapping CRSs for a group of sub-carriers;
estimating a coarse channel state for each of the at least two cells by multiplying the received overlapping CRSs with a function of phase-shifted CRSs, wherein the phase-shifted CRSs of different sub-carriers in the group include a phase-shift that corresponds to the determined time offset; and
measuring the RSRP for each of the at least two cells based on the estimated coarse channel state.

US Pat. No. 10,250,342

SYSTEM FOR MEASURING RECEPTION PERFORMANCE OF WIRELESS TERMINAL AND METHOD OF MEASUREMENT

ANRITSU CORPORATION, Kan...

1. A wireless terminal reception performance measurement system comprising;a measurement antenna having a known directional characteristic, which is fixed at a predetermined position in a measuring space in which entrance of a radio wave from outside and internal reflection of the radio wave are suppressed;
a terminal holding rotation mechanism that, within the measuring space, uses a point spaced from a phase center of the measurement antenna by a predetermined distance as a standard point, holds a wireless terminal that is a measurement target, in a vicinity of the standard point, and rotates the held wireless terminal centering around the standard point within a region where a distance condition of far field measurement is satisfied from the measurement antenna;
a transmission unit that supplies a measurement signal to the measurement antenna;
a response monitoring unit that monitors a response to the measurement signal received through a terminal antenna by the wireless terminal which is held in the terminal holding rotation mechanism;
a reception performance acquisition unit that rotates the wireless terminal from a standard position by controlling the terminal holding rotation mechanism and acquires a reception performance of the terminal holding rotation mechanism from a response attained at each rotation angle in the response monitoring unit and from a power of the measurement signal input to the terminal antenna of the wireless terminal;
an antenna position input unit through which a position of the terminal antenna in a case where the wireless terminal is disposed in the standard position in the measuring space, is input;
an error information output unit that outputs an angle error at each rotation angle of the wireless terminal, which indicates a deviation between a direction of the standard point and a direction of the terminal antenna, when viewed from the phase center of the measurement antenna, a propagation loss error in a free space at each rotation angle of the wireless terminal, which occurs due to a difference between a distance from the phase center of the measurement antenna to the standard point and a distance to the terminal antenna, and a gain error of the measurement antenna at each rotation angle of the wireless terminal, which is determined by the angle error and the directional characteristic of the measurement antenna, based on the input position of the terminal antenna; and
a correction unit that corrects a power of the measurement signal that is supplied from the transmission unit to the measurement antenna according to the propagation loss error and the gain error that are output from the error information output unit, when the reception performance acquisition unit obtains the reception performance of the wireless terminal, and along with this, corrects the reception performance for the rotation angle acquired by the measurement signal having the corrected power, with the angle error, and obtains the reception performance in a case where it is assumed that the terminal antenna is rotated at a position of the standard point.

US Pat. No. 10,250,341

MONITORING APPARATUS, WIRELESS COMMUNICATION SYSTEM, FAILURE FACTOR DECIDING METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM HAVING PROGRAM STORED THEREON

NEC CORPORATION, Minato-...

1. A monitoring apparatus comprising:at least one memory storing instructions, and
at least one processor configured to execute the instructions to:
obtain a history related to a received signal level of one or more first receivers and a received signal level of one or more second receivers in a predetermined period from a wireless communication apparatus including the first receiver and the second receiver, the history indicating at least information related to a maximum value and a minimum value of the received signal level of the first receiver and a maximum value and a minimum value of the received signal level of the second receiver in the predetermined period; and
decide a factor of a failure that has occurred in the wireless communication apparatus based on a correlation coefficient between the maximum value of the received signal level of the first receiver and the maximum value of the received signal level of the second receiver, and a correlation coefficient between the minimum value of the received signal level of the first receiver and the minimum value of the received signal level of the second receiver.

US Pat. No. 10,250,340

WIRELESS RELAY DIRECTIONAL TESTING

Sprint Communications Com...

1. A method of operating a wireless relay comprising a wireless access point and Relay Equipment (RE) to perform Radio Frequency (RF) testing at geographic azimuths, the method comprising:the wireless access point wirelessly exchanging user data with wireless user devices;
the wireless access point and the RE exchanging the user data;
the RE wirelessly exchanging the user data with a wireless communication network;
the RE wirelessly receiving a directional Radio Frequency (RF) test instruction indicating one or more of the geographic azimuths, wherein the directional RF test instruction comprises detecting RF signal strength at a specified date and time, and wherein at least a portion of the directional RF test instruction is wirelessly received by the RE in a Radio Resource Control (RRC) message;
the RE performing a directional RF test at the one or more geographic azimuths based on the directional RF test instruction; and
the RE transferring RF test results for the one or more geographic azimuths to the wireless communication network.

US Pat. No. 10,250,339

INTEGRATED CIRCUIT CALIBRATION ARCHITECTURE

pSemi Corporation, San D...

1. A radio frequency (RF) integrated circuit including:(a) a primary RF transmission path;
(b) a primary RF reception path;
(c) at least one RF transceiver front-end circuit, each selectively connectable to the primary RF transmission path and the primary RF reception path; and
(d) at least one switchable internal calibration path selectively configurable between the primary RF transmission path and the primary RF reception path to convey, in a calibration mode, a test signal from the primary RF transmission path to the primary RF reception path through at least a portion of at least one RF transceiver front-end circuit undergoing calibration;
wherein at least one RF transceiver front-end circuit includes at least one of a phase-attenuation core or an input/output circuit.

US Pat. No. 10,250,337

SYSTEM AND METHOD FOR PROVIDING UNDERWATER MEDIA CAPTURE

WAHOO TECHNOLOGIES, LLC, ...

1. A method comprising:receiving, via a bridge system comprising a first adapter and a second adapter, a service set identifier and a password of a capture device;
discovering the capture device via the first adapter and the second adapter of the bridge system;
based on a comparison of a first signal-to-noise ratio between the first adapter and the capture device with a second signal-to-noise ratio between the second adapter and the capture device, assigning one of the first adapter and the second adapter as a host adapter in the bridge system to communicate with the capture device; and
forwarding IP packets received from the capture device, via the bridge system, to a client device, wherein the bridge system rewrites MAC addresses associated with the client device and the capture device in XID tables prior to receiving the IP packets from the capture device at the host adapter and forwarding the IP packets from the bridge system to the client device.

US Pat. No. 10,250,336

OPTICAL IDENTIFICATION BEACON

Triad National Security, ...

1. A beacon device, comprising:a laser configured to emit laser light;
a pattern generator and pulse driver that are configured to control the laser to emit the laser light in accordance with a pattern of a beacon signal, and
a diffuser configured to diffuse the emitted laser light; and
an optical detection system configured to receive the diffused laser light emitted from the laser beacon, wherein
the beacon signal comprises an m-of-n code unique identifier of the beacon device that is at least a predetermined Hamming distance from any other unique identifier for other beacon devices, and
m is a number of pulses of the emitted laser light that are emitted over a predetermined time period.

US Pat. No. 10,250,335

PHOTONIC INTEGRATED CHIP DEVICE HAVING A COMMON OPTICAL EDGE INTERFACE

RANOVUS INC., Ottawa, On...

1. A device comprising:a photonic integrated circuit (PIC) chip comprising:
an optical circuit; and
an electrical interface configured to receive electrical signals for controlling the optical circuit; and,
a common optical interface side of the PIC chip comprising: at least one input configured to receive light into the PIC chip to the optical circuit; and at least one output configured to convey at least one optical signal from the optical circuit out of the PIC chip,
the electrical interface located on one or more electrical interface sides of the PIC chip different from the common optical interface side, wherein the electrical interface side of the PIC chip is opposite the common optical interface side.

US Pat. No. 10,250,334

OPTICAL RECEIVER MODULE AND OPTICAL MODULE

Oclaro Japan, Inc., Kana...

1. An optical receiver module comprising:a plurality of light-receiving elements, each having a first electrode and a second electrode to which a bias is applied, configured to convert input optical signals into electric signals and output the electric signals from the first electrodes; and
a carrier having a plurality of wiring patterns, each electrically connecting to a respective light-receiving element of the plurality of light-receiving elements, that support the plurality of light-receiving elements so that the first electrodes and the second electrodes face the wiring patterns,
wherein each of the wiring patterns includes a first wiring line electrically connecting to the first electrode and a second wiring line electrically connecting to the second electrode of the respective light-receiving element,
the second wiring line has a high resistance portion having a higher resistance value than other portions at least in a position overlapping with the respective light-receiving element connected thereto, the high resistance portion and the other portions of the second wiring line being connected in series, and
the second wiring line has a low resistance portion having a lower resistance value than the high resistance portion at least in a position not overlapping with any of the plurality of light-receiving elements.

US Pat. No. 10,250,333

OPTICAL COMMUNICATION SYSTEM AND OPTICAL TRANSMITTER

Oclaro Japan, Inc., Kana...

1. An optical communication system, comprising:an optical transmitter section comprising:
a single-side band modulation circuit configured to subject a double-side band modulated signal to transformation using single-side band modulation to generate a single-side band modulated signal; and
an optical modulator configured to output an optical modulated signal based on the single-side band modulated signal generated by the single-side band modulation circuit; and
an optical receiver section configured to receive the optical modulated signal output by the optical transmitter section, and to directly detect an intensity of the optical modulated signal to generate a received signal,
wherein the optical receiver section comprises a compensation circuit configured to compensate an intensity of the received signal so that the intensity of the received signal becomes closer to an intensity of the double-side band modulated signal.

US Pat. No. 10,250,332

VCSEL BASED OPTICAL LINKS IN BURST MODE

International Business Ma...

1. A method for optical communications, comprising:in an optical communication device comprising a transmitter including a light-emitting device, applying a bias current to the light-emitting device; and
transmitting a pulse as an input to the light-emitting device before transmitting a preamble signal or data signal to the light-emitting device, wherein the pulse has a voltage equal to or greater than a highest voltage of the preamble signal or data signal;
wherein a time for an optical output of the light-emitting device to reach full amplitude when the pulse is transmitted is reduced compared to a time for an optical output of the light-emitting device to reach full amplitude when the pulse is not transmitted.

US Pat. No. 10,250,331

SUBSCRIBER DEVICE AND LIGHT RECEIVING METHOD

NIPPON TELEGRAPH AND TELE...

1. A subscriber device comprising:a demultiplexer configured to demultiplex input wavelength-multiplexed light into a plurality of light signals for each wavelength;
a plurality of light receivers configured to receive each of the plurality of light signals obtained through demultiplexing by the demultiplexer and to convert the light signals into electrical signals;
a plurality of limiting amplifiers configured to amplify each of the plurality of electrical signals output from the plurality of light receivers; and
a plurality of signal selection units configured to select a plurality of signals to be received from among a plurality of amplified signals output from the plurality of limiting amplifiers,
wherein at least one of the plurality signal selection units is configured to extract a frame including a desired service from among frames included in the plurality of amplified signals on a basis of identification information included in each of the frames.

US Pat. No. 10,250,330

FLEXIBLE SIGNAL DISTRIBUTION ASSISTED BY TUNABLE OPTICAL CARRIER MODULATING A DESIRED SIGNAL

1. A switch device configured to accept a data modulated RF signal and output the data modulated RF signal, or a frequency converted version of the data modulated RF signal, at only one of N outputs of the switch device at any given time, where N is an integer that is greater than or equal to two, the switch device comprising:a tunable laser operable to emit an optical signal having a peak wavelength;
a controller configured to control the tunable laser to cause the peak wavelength of the optical signal emitted by the tunable laser to be one of N different wavelengths;
an electro-optical modulator (EOM) including
a first input configured to receive the data modulated RF signal accepted by the switch device,
a second input configured to receive an optical signal produced using the tunable laser, and
an output configured to output an optical data signal that has been modulated to include the data modulated RF signal,
wherein a peak wavelength of the optical data signal that is output by the EOM is one of the N different wavelengths, based on how the controller controls the tunable laser;
a wavelength-division multiplexing (WDM) demultiplexer including an input and N outputs,
wherein the input of the WDM demultiplexer is configured to receive the optical data signal that is output by the EOM, and
wherein at any given time the optical data signal that is received at the input of the WDM demultiplexer will be output at only one of the N outputs of the WDM demultiplexer based on the peak wavelength of the optical data signal, which is based on how the controller controls the tunable laser; and
N photodetectors, each of which is optically coupled to a respective one of the N outputs of the WDM demultiplexer, and each of which provides or is electrically coupled to one of the N outputs of the switch device;
wherein at any given time the data modulated RF signal that is accepted by the switch device, or a frequency converted version of the data modulated RF signal that is accepted by the switch device, will be output by only one of the N photodetectors based on how the controller controls the tunable laser.

US Pat. No. 10,250,329

LED LIGHT FIXTURE

Federal Law Enforcement D...

1. An LED light fixture comprising:a plurality of optical transceivers, each of said plurality of optical transceivers comprising at least one location identifier, each of said plurality of optical transceivers further comprising:
a plurality of light emitting diodes, at least one photodetector, and a camera or a microphone, said plurality of light emitting diodes generating light having a wavelength in the visible spectrum, said light comprising a plurality of flashes of light, said flashes of light being at a frequency which is not observable to the unaided eyes of an individual; and
a processor in communication with each of said plurality of optical transceivers and said plurality of light emitting diodes, said processor communicating with one of said plurality of optical transceivers, said processor being constructed and arranged to regulate said plurality of flashes of light to transmit at least one transmitted signal, said at least one transmitted signal comprising said at least one location identifier and said at least one transmitted signal being embedded within said light, and said at least one photodetector of another of said plurality of optical transceivers being constructed and arranged for receipt of said at least one transmitted signal, said processor changing said light between a cool white color and a warm yellow color.

US Pat. No. 10,250,328

POSITIONING SYSTEM BASED ON VISIBLE LIGHT COMMUNICATIONS

GENERAL ELECTRIC COMPANY,...

9. A position tracking system, comprising:one or more location beacons;
one or more beacon receiver systems configured to be disposed on an object, and wherein each of the one or more beacon receiver systems comprises:
a motion sensor to collect motion data of the object;
a plurality of photodetectors configured to receive signals from the one or more location beacons;
an analog-to-digital convertor to convert analog signals received by the plurality of photodetectors to digital signals;
a memory;
a processor configured to execute instructions stored on the memory comprising instructions for receiving signals collected by the plurality of photodetectors; converting the received signals to digital signals; processing the digital signals; and computing a location of the object based on an analysis of combination of the digital signals and the motion data of the object, wherein the analog-to-digital converter, the memory, and the processor are on a single integrated circuit chip; and
wherein the one or more beacon receiver systems comprise a plurality of analog multiplexer integrated circuits configured to select and sample one photodetector from the plurality of photodetectors at a time.

US Pat. No. 10,250,327

ILLUMINATION SYSTEM AND CONTROL METHOD THEREOF

LG ELECTRONICS INC., Seo...

1. A method performed at a terminal having a display and a camera, the method comprising:executing an application program for recognizing identification information of an illumination device;
displaying, on the display, an execution screen of the application when the application is executed, wherein the execution screen includes a button for switching an operation mode of the illumination device;
switching an operation mode of the illumination device from a first mode to a second mode according to a user input applied to the button of the displayed execution screen, wherein the illumination device blinks based on an on/off control signal while the first mode is selected, and the illumination device performs visible light communication to transmit binary data while the second mode is selected;
obtaining at predetermined periods, via the camera, an image of the illumination device to obtain a plurality of images, wherein the plurality of images are obtained while the illumination device is performing visible light communication;
generating binary data according to each of the plurality of images;
sampling a predetermined number of the binary data;
determining final binary data based on a result of the sampling; and
storing the final binary data as the identification information of the illumination device.

US Pat. No. 10,250,326

EMBEDDED APPARATUS TO MONITOR SIMULATED BRILLOUIN SCATTERING FROM RAMAN AMPLIFIER IN FIBER OPTICS TRANSMISSION SYSTEM

Ciena Corporation, Hanov...

1. An apparatus to monitor pump stability in a fiber optics transmission system, comprising:an optical pump source configured to transmit a signal in the fiber optics transmission system;
an optical amplifier configured to receive the signal and to amplify the signal based thereon; and
a monitoring circuit configured to compare reflection coefficients associated with one or more back reflections from the fiber optics transmission system during a detection window to a threshold to determine whether the one or more back reflections during the detection window indicate a stimulated Brillouin scattering (SBS) event undesirably caused by the optical pump source, a normal condition, or excessive back reflections that trigger at least one remedial action, wherein the detection window is a time period that is a value between 10 ?s and 100 ms,
wherein the SBS event is detected based on the one or more reflection coefficients being above the threshold during less than all of the detection window, and the excessive back reflections are detected based on the one or more reflection coefficients being above the threshold during all of the detection window.

US Pat. No. 10,250,325

NETWORK SWITCHING SYSTEM

IPSECURES CORPORATION, T...

1. A network switching system applied to an in-line device, the in-line device including a hardware unit built in the in-line device, an operating system running in the in-line device and at least one application running in the operating system, the in-line device being connected to a switch, the switch further being connected to a first network device and a second network device respectively to switch network channels between the first and second network devices, the network switching system including:a first detector for detecting an operating voltage of the hardware unit and for outputting a first trigger signal when it detects that the operating voltage of the hardware unit is abnormal;
a second detector for detecting an operating status of the operating system and for outputting a second trigger signal when it detects that the operating status of the operating system is abnormal;
a third detector including a monitoring program running in the operating system, for detecting an operating status of the application, wherein when it detects that the operating status of the application is abnormal, the third detector outputs a third trigger signal; and
a controller connected to the switch, wherein the switch is in a normal mode by default, making the first and second network devices communicate with each other through the in-line device, and wherein when the controller receives any of the first, second and third trigger signals, it controls the switch to switch from the normal mode to a bypass mode, allowing the first and second network devices to communicate without the in-line device so as to ensure normal communication between the first and second network devices when the in-line device operates abnormally.

US Pat. No. 10,250,324

OPTICAL TIME-DOMAIN REFLECTOMETER INTEROPERABLE TRUNK SWITCH

Ciena Corporation, Hanov...

1. An optical trunk switch supporting an Optical Time-Domain Reflectometer (OTDR), the optical trunk switch comprising:a transmit switch configured to provide an input signal to one or more of a primary fiber path and a standby fiber path;
a receive switch configured to provide an output signal from one of the primary fiber path and the standby fiber path; and
an integrated OTDR system in a same housing as the transmit switch and the receive switch, wherein the integrated OTDR system has an OTDR connection to one or more of the transmit switch and the receive switch, wherein the integrated OTDR system is configured to provide one or more OTDR signals to monitor an inactive path of the primary fiber path and the standby fiber, based on configuration of the transmit switch and the receive switch.

US Pat. No. 10,250,323

DEVICE AND METHOD FOR MONITORING OPTICAL FIBRE LINK

TELEFONAKTIEBOLAGET L M E...

1. A method of monitoring an optical fibre link, comprising:generating a monitoring signal used for monitoring the optical fibre link, the monitoring signal being sinusoidally frequency-swept over at least one set of selected frequencies;
combining the monitoring signal with a data signal to be transmitted over the optical fibre link, the combined signal including the monitoring signal in a separate subcarrier band than the data signal;
detecting, at an optical receiver, backscattering of the monitoring signal from the combined signal that is transmitted over the optical fibre link;
performing vector voltmeter detection of the backscattering, using the monitoring signal as a reference, wherein a measured amplitude and phase of the backscattering are detected;
detecting a change in characteristic of the measured amplitude and phase, the detecting of the change in characteristic including determining an Inverse Fast Fourier Transform (IFFT) corresponding to the backscattering;
generating a piecewise linear curve corresponding to the IFFT; and
determining, based on the piecewise linear curve, at least one location along the optical fibre link where the monitoring signal is modified, and signal loss at the at least one location.

US Pat. No. 10,250,322

TRANSMISSION SYSTEM, TRANSMISSION DEVICE, AND TRANSMISSION METHOD

FUJITSU LIMITED, Kawasak...

1. A transmission system comprising:a first device having a configuration and configured to perform as first one of:
a first communication device,
a first transmission device coupled to a work path and including a first interface configured to receive a first signal from the work path, a second interface coupled to the first communication device and a first processor configured to control the first interface and the second interface, and
a second transmission device coupled to a protection path in a redundant configuration with respect to the work path and including a third interface configured to receive a second signal from the protection path, a fourth interface coupled to the first communication device and a second processor configured to control the third interface and the fourth interface;
a second device having the same configuration as the first device and configured to perform as second one which is included in the first communication device, the first transmission device and the second transmission device and is different from the first one; and
a third device having the same configuration as the first device and configured to perform as third one which is included in the first communication device, the first transmission device and the second transmission device and is different from the first one and the second one,
wherein a third processor provided in the first communication device, when detecting switching information from the first transmission device, notifies the first transmission device of first switching notification information and notifies the second transmission device of second switching notification information,
the first processor stops relaying the first signal to the first communication device in response to the first switching notification information from the first communication device,
the second processor starts to relay the second signal to the first communication device in response to the second switching notification information from the first communication device,
the first device, the second device and the third device include respective setting tables indicating a kind of devices including the first communication device, the first transmission device and the second transmission device, and each processor of the first device, the second device and the third device determines the respective devices perform as which one of the first communication device, the first transmission device and the second transmission device based on the respective setting tables.

US Pat. No. 10,250,321

SATELLITE COMMUNICATIONS NETWORKING

Iridium Satellite LLC, M...

1. A method for routing transmissions in a satellite communications network, comprising:detecting a problem with a particular crosslink between a first satellite and a second satellite of a satellite communications network, the satellite communications network including multiple satellites individual ones of which are configured to establish one or more inter-satellite, wireless communications crosslinks with one or more corresponding others of the multiple satellites for transmitting transmissions;
in response to detecting the problem with the particular crosslink between the first satellite and the second satellite, distributing notifications of the problem with the particular crosslink between the first satellite and the second satellite to other ones of the satellites, including a third satellite of the multiple satellites;
identifying a desired destination within the satellite communications network to which to transmit a transmission from the third satellite; and
determining, based on the notification of the problem with the particular crosslink between the first satellite and the second satellite that was distributed to the third satellite, a route through a set of satellites of the satellite communications network and one or more corresponding inter-satellite wireless communications crosslinks between individual ones of the set of satellites along which to route the transmission from the third satellite to the destination.

US Pat. No. 10,250,320

SATELLITE SIGNAL STRENGTH INDICATION AND REFLECTION DETECTION

Hughes Network Systems, L...

1. A telecommunications terminal comprising:a memory; and
a processor programmed to execute instructions stored in the memory, the instructions including:
determining an estimate of a link attenuation of a first communication link while receiving a channel; and
applying the estimate of the link attenuation to a second communication link after transitioning to the second communication link,
wherein the estimate of the link attenuation is determined by determining a first maximum signal strength associated with the first communication link, measuring a first signal strength of a first signal transmitted over the first communication link, and estimating the link attenuation based at least in part on the first maximum signal strength and the first signal strength.

US Pat. No. 10,250,319

TASK TRANSFER AMONG SATELLITE DEVICES

Vector Launcy Inc., Tucs...

1. A satellite device, comprising:communication interface; and
a virtualized execution system configured to:
receive task information via the communication interface from at least a further device related to execution of one or more software payloads by the satellite further device; and
execute one or more virtual nodes to at least capture and process sensor data collected from one or more sensors systems present on the satellite device based at least on the task information.

US Pat. No. 10,250,318

PROCESS AND MACHINE FOR AIRCRAFT ALTITUDE CONTROL

The Boeing Company, Chic...

1. A process for pilotlessly flying, an aircraft certified for flight by a pilot, at a specified altitude, the process comprising:setting a fixed barometric pressure in an altimeter in the aircraft, forming a fixed altimeter setting;
receiving an assigned altitude for the aircraft to fly;
receiving a barometric pressure for a location of the aircraft;
determining a differential between a height above mean sea level indicated on an altimeter using the barometric pressure for the location of the aircraft and a height above mean sea level indicated on an altimeter using the fixed altimeter setting;
modifying, using the differential, a flight planned altitude for the aircraft, and creating a pilotless altitude; and
flying the aircraft at the assigned altitude via directing the aircraft to fly at the pilotless altitude indicating on the altimeter in the aircraft.

US Pat. No. 10,250,317

FULL-DUPLEX COMMUNICATION METHOD FOR MULTI-HOP WIRELESS NETWORK

GWANGJU INSTITUTE OF SCIE...

1. A full-duplex communication method for a multi-hop wireless network including a source end for transmitting data, a destination end as a destination of the data and at least one relay for connecting the source end and the destination end wirelessly, the full-duplex communication method comprising:sending a transmission request from the source end to the destination end through the at least one relay in forward order;
sending a transmission confirmation from the destination end to the source end through passing by the at least one relay in reverse order in response to the transmission request and the at least one relay entering a ready state; and
transmitting the data from the source end to the destination end through the at least one relay using a full-duplex scheme after receiving the transmission confirmation,
wherein, upon transmitting the data, the at least one relay cancels self-interference and intra-flow interference from a received signal using a first cancellation signal for cancelling the self-interference acquired upon sending the transmission request in the forward order and a second cancellation signal for cancelling the intra-flow interference acquired upon sending the transmission confirmation in the reverse order.

US Pat. No. 10,250,316

FULL-DUPLEX RELAY COMMUNICATION METHOD USING ENERGY HARVESTING, FULL-DUPLEX RELAY COMMUNICATION SYSTEM BASED ON ENERGY-HARVESTING, RELAY NODE DEVICE, AND SOURCE NODE DEVICE

1. A full-duplex relay communication method, comprising:receiving, by a relay node, first information signals transmitted from a source node and second information signals transmitted from a destination node;
harvesting, by the relay node, energy using energy signals transmitted from the source node while bi-directionally relaying the first information signals and the second information signals;
receiving, by the source node, information signals transmitted by the relay node;
receiving, by the destination node, information signals relayed by the relay node; and
removing, by the destination node, a returned signal among the second information signals from the received information signals relayed by the relay node,
wherein the source node, the relay node, and the destination node communicate in a full-duplex mode.

US Pat. No. 10,250,315

SYSTEM AND METHOD FOR INTER-BASIC SERVICE SET COMMUNICATIONS

FUTUREWEI TECHNOLOGIES, I...

1. A method for multiple association, the method comprising:associating, by an associated station, with a first access point (AP) in a primary basic service set (BSS);
associating, by the associated station, with a second AP in a secondary BSS;
informing, by the associated station, the first and second APs of an inter-BSS relaying capability of the associated station; and
relaying, by the associated station, data between the first AP and the second AP.

US Pat. No. 10,250,314

MULTI-WAY DIVERSITY RECEIVER WITH MULTIPLE SYNTHESIZERS IN A CARRIER AGGREGATION TRANSCEIVER

QUALCOMM Incorporated, S...

1. A wireless reception diversity circuit, comprising:three or more receive paths configured to process received signals; and
two or more frequency synthesizing circuits comprising at least a pair of the frequency synthesizing circuits configured to generate local oscillating signals having a same frequency and each having a voltage-controlled oscillator (VCO), at least one of the frequency synthesizing circuits of the at least the pair of the frequency synthesizing circuits being configured to downconvert the received signals for two of the three or more receive paths.

US Pat. No. 10,250,313

METHOD AND APPARATUS FOR COVARIANCE MATRIX FEEDBACK IN ADVANCED WIRELESS COMMUNICATION SYSTEMS

Samsung Electronics Co., ...

1. A user equipment (UE) for channel state information (CSI) feedback, the UE comprising:a transceiver configured to receive, from a base station (BS), CSI feedback configuration information to report a covariance matrix indicator (CMI) indicating a N×N channel covariance matrix (K) associated with a downlink channel matrix, wherein N is a number of antenna ports at the BS; and
a processor operably connected to the transceiver, the processor configured to identity the CMI that indicates a set of L basis vectors {ai}, i=0, 1, 2, . . . , L?1, each comprising a dimension N×1, and a set of L2 coefficients, {ci,j}, i,j=0, 1, 2, . . . , L?1, and that represent the covariance matrix (K) as a weighted linear sum K=?i=0L-1?j=0L-1ci,jaiajH, wherein L?N and H denotes a Hermitian transpose,
wherein the transceiver is further configured to transmit, to the BS, the CSI feedback including the identified CMI over an uplink channel.

US Pat. No. 10,250,312

METHODS AND SYSTEMS FOR MULTI-USER BEAMFORMING

HUAWEI TECHNOLOGIES CANAD...

1. A method for simultaneous transmission between a transmitter and a plurality of receivers, the method comprising:at the transmitter, receiving information identifying respective preferred transmission sectors for transmission from the transmitter to each receiver;
at the transmitter, transmitting a first multi-user simultaneous transmission to a first set of two or more receivers, the first set of receivers being selected for the first set by identifying that the preferred transmission sectors for transmission to the first set of receivers are included in a first virtual grouping of two or more transmission sectors, the two or more transmission sectors belonging to the first virtual grouping being defined by the transmitter; and
at the transmitter, transmitting a second multi-user simultaneous transmission to a second set of two or more receivers, the second set of receivers being selected for the second set by identifying that the preferred transmission sectors for transmission to the second set of receivers are included in a second virtual grouping, the second virtual grouping having at least one transmission sector not included in the first virtual grouping.

US Pat. No. 10,250,311

METHOD AND SYSTEM FOR MIMO COMMUNICATION

NEC CORPORATION, Tokyo (...

6. A method of generating a precoder for use in a MIMO (Multiple-Input Multiple-Output) system when communicating with a UE (User Equipment), the method comprising:receiving, from the UE, channel information relating to a channel on which data is transmitted;
decomposing the channel information into components representing a transmission component and a signal strength component;
generating the precoder according to the transmission component and the signal strength component;
determining a power allocation matrix according to the signal strength component, wherein the precoder is further generated according to the power allocation matrix,
wherein the power allocation matrix is determined according to the signal strength component and a Lagrange multiplier, and
wherein the power allocation matrix D is determined according to the following equation

where A comprises singular values of the singular value decomposition, ? is the Lagrange multiplier and the sign ( )+means that if ( )<0 then assign ( )=0.

US Pat. No. 10,250,310

CODEBOOK CONSTRUCTION

NEC Corporation, Tokyo (...

1. A base station comprising:a reception interface configured to receive, from a user equipment (UE), a first parameter related to precoding matrix indicator (PMI), and a second parameter related to rank indicator (RI);
a transmission interface configured to transmit, to the UE, a data which the data is precoded by using one of plurality of precoding matrices, based on the first parameter and the second parameter;
wherein the transmission interface comprises 4 transmit antenna (4TX);
wherein the plurality of precoding matrices are included in a first 1-layer, a second 1-layer, a first 2-layer, a second 2-layer, 3-layer, and 4-layer codebooks for 4TX transmission, which each precoding matrix in the first 1-layer and the first 2-layer codebooks is specified by a first index and a second index.

US Pat. No. 10,250,309

SYSTEM AND METHOD FOR DOWNLINK CHANNEL ESTIMATION IN MASSIVE MULTIPLE-INPUT-MULTIPLE-OUTPUT (MIMO)

Huawei Technologies, Co.,...

1. A method for massive multiple-input-multiple-output (MIMO) channel estimation, the method comprising:precoding, by a base station, a training reference signal according to a transformation matrix, the transformation matrix mapping a generic dictionary to a non-generic dictionary, the generic dictionary associated with a reference antenna geometry, the non-generic dictionary associated with an antenna geometry of a MIMO antenna array of the base station, the non-generic dictionary transforming a downlink channel between the MIMO antenna array and a user equipment (UE) into a sparse representation, the sparse representation of the downlink channel having non-zero coefficients interspersed between zero coefficients;
transmitting, by the base station, the precoded training reference signal over the MIMO antenna array of the base station to the UE;
receiving, by the base station, a sparse channel estimate from the UE, the sparse channel estimate being an estimate of the sparse representation of the downlink channel; and
processing, by the base station, the received sparse channel estimate in accordance with the transformation matrix to obtain a complex channel estimate, the complex channel estimate being an estimate of the downlink channel.

US Pat. No. 10,250,308

PRECODER STRUCTURE FOR MIMO PRECODING

TELEFONAKTIEBOLAGET LM ER...

1. A method in a wireless communication transceiver, wherein another transceiver precodes transmissions to the transceiver based at least in part on the transceiver sending channel state information to the other transceiver that includes precoder information and wherein the method is characterized by:selecting entries from one or more codebooks as a selected conversion precoder and a selected tuning precoder, or as a selected overall precoder corresponding to a selected conversion precoder and a selected tuning precoder; and
transmitting indications of the selected entries as said precoder information included in the channel state information;
wherein the one or more codebooks include entries comprising NTQ different conversion precoders, NT being a number of transmit antenna ports and Q being an integer value, and entries comprising a number of corresponding tuning precoders, or include entries comprising a plurality of overall precoders, with each overall precoder comprising a product of a conversion precoder and a tuning precoder; and
wherein each said conversion precoder out of said NTQ different entries comprises a block diagonal matrix in which each block comprises a discrete Fourier transform (DFT)-based antenna-subgroup precoder that corresponds to a subgroup of NT transmit antenna ports at the transceiver and provides NTQ different DFT based beams for the corresponding subgroup, where the NTQ different conversion precoders, together with one or more of the tuning precoders, correspond to a set of NTQ different overall precoders, wherein each overall precoder represents a size-NT DFT-based beam over the NT transmit antenna ports,
wherein said one or more codebooks includes conversion and tuning precoders or corresponding overall precoders for multiple transmission ranks, and
wherein for transmission rank r>2
the tuning precoder has 2[r/2] rows and r columns, where r is the transmission rank;
all non-zero elements of the tuning precoder are constant modulus;
every column of the tuning precoder has exactly two non-zero elements;
every row of the tuning precoder has exactly two non-zero elements; and
two columns of the tuning precoder having non-zero elements in the same two rows are orthogonal to each other.

US Pat. No. 10,250,307

METHOD FOR SETTING COOPERATION PARAMETERS OF COMMUNICATION SYSTEM, COMPUTER PROGRAM THEREOF, INFORMATION STORAGE MEANS THEREOF, AND COMMUNICATION SYSTEM INCLUDING PLURALITY OF NODE DEVICES

MITSUBISHI ELECTRIC CORPO...

1. A method for setting cooperation parameters of a communication system, the communication system including a plurality of node devices directly interconnected by a link or indirectly interconnected by links via a server, the node devices being adapted to be respectively configured according to said cooperation parameters, said cooperation parameters having an impact on an environment of the communication system, said environment being represented by measurable random variables, a figure of merit relative to performance of the communication system regarding said environment having to be optimized for determining said cooperation parameters, characterised in that the method includes a cooperation phase comprising the following steps:gathering measurements data representative of measurements of the random variables performed at different locations within the communication system;
determining said cooperation parameters such that said cooperation parameters lead to an optimized figure of merit relative to the performance of the communication system regarding said environment, on the basis of the obtained measurements; and
providing said cooperation parameters, or information representative thereof, within the communication system;
and, at least one interconnecting link between node devices of the communication system implying quantization operations for gathering said measurements data and/or for providing said cooperation parameters or the information representative thereof, each quantization operation relying on implementing a codebook associated with the link on which said quantization operation applies, the method includes beforehand a pre-processing phase comprising the following steps:
obtaining statistics data relative to a probability distribution of said random variables; and
determining every codebook on the basis of the figure of merit and of the probability distribution of said random variables, such that the figure of merit is statistically optimized according to the obtained statistics data.

US Pat. No. 10,250,306

METHOD AND APPARATUS FOR DETERMINING PARAMETERS AND CONDITIONS FOR LINE OF SIGHT MIMO COMMUNICATION

Motorola Mobility LLC, C...

1. A method comprising:transmitting, by a transmitter, reference symbols from a regularly spaced subset of a set of transmitting device antenna elements of the transmitter with elements spanning one or more spatial dimensions; and
signaling transmit antenna element spacings in each dimension that can be used by the transmitter for data transmission, where the transmit antenna element spacings are signaled in the form of ratios to the spacing of transmitting device antenna elements that were used for the transmitted references symbols.

US Pat. No. 10,250,305

METHOD AND SYSTEM FOR INDICATING TRANSMISSION PARAMETER

ZTE Corporation, Shenzhe...

1. A method for indicating a transmission parameter, comprising:when multi-user multi-input multi-output (MIMO) data are transmitted, using a newly-added indication signaling in a downlink control information format to indicate joint encoded parameters;
wherein, when a value of the newly-added indication signaling for a case that a single transport block is enabled, is same with a value of the newly-added indication signaling for a case that two transport blocks are enabled, the joint encoded parameters are different, the same value of the newly-added indication signaling refers to different settings on the following one or more joint encoded parameters comprising:
a number of transmitted layers,
scrambling identity (SCID),
antenna port,
spreading code information,
reference signal information;
wherein, when a single transport block is enabled, for part of values of the newly-added indication signaling, the scrambling identity as one of the joint encoded parameter is encoded; when two transport blocks are enabled, for part of the values of the newly-added indication signaling, the scrambling identity as one of the joint encoded parameter is encoded.

US Pat. No. 10,250,304

METHOD OF TRANSMITTING AND RECEIVING FRAME FOR UPLINK MULTI-USER MULTIPLE-INPUT AND MULTIPLE-OUTPUT (UL MU-MIMO) COMMUNICATION

ELECTRONIC AND TELECOMMUN...

1. A method for transmitting an uplink physical layer protocol data unit (PPDU) by a station (STA) in a wireless local area network, the method comprising:receiving, by the STA from an access point (AP), a first frame soliciting immediate response from one or more STAs including the STA; and
transmitting, by the STA to the AP, a second frame in the uplink PPDU,
wherein the first frame includes length information which is commonly applied to one or more frames including the second frame transmitted from the one or more STAs including the STA.

US Pat. No. 10,250,303

SYSTEM AND SELECTING METHOD FOR FLEXIBLE ALLOCATIONS OF ANTENNA SUB-ARRAYS IN MULTIPLE INPUT MULTIPLE OUTPUT SYSTEMS

NATIONAL TAIWAN UNIVERSIT...

1. A signal processing and transmission/reception system, comprising:a transmission end, comprising:
a precoder, for encoding a data signal by using a signal processing method to output a plurality of first electrical signals relating to an antenna sub-array combination, wherein the antenna sub-array combination is with a plurality of polarization direction combinations; and
a first selection circuit of multiple input ports and antenna sub-arrays combination, comprising:
an input port;
a plurality of first digital signal processing modules, each is electrically connected to the precoder through the input port;
a first analog front end (AFE) and radio frequency (RF) chain, each is electrically connected to one of the first digital signal processing modules, wherein each of the first digital signal processing modules and each of the AFE and RF chain form a plurality of first chain lines turned on according to the first electrical signals;
a plurality of first multiplexing circuits, each is electrically connected to the first AFE and RF chain according to the first electrical signals; and
a plurality of first antenna sub-arrays, each is electrically connected to one of the first multiplexing circuits, the first antenna sub-arrays is set by the number of first chains turned on and the number of first multiplexing circuits connected to form the antenna sub-array combination, and transmitting a wireless signal, comprising:
a plurality of first phase shifters;
a plurality of first power amplifiers; and
a plurality of first antenna ends;
a reception end, comprising:
a second selection circuit of multiple output ports and antenna sub-arrays combination, comprising:
a plurality of second antenna sub-arrays, for receiving the wireless signal to form the antenna sub-array combination by a number of second chains turned on and a number of second multiplexing circuits connected, and generating a plurality of second electrical signals, comprising:
a plurality of second antenna ends;
a plurality of second power amplifiers; and
a plurality of second phase shifters;
the second multiplexing circuits, each is electrically connected to one of the second antenna sub-arrays;
a second AFE and RF chain, each is electrically connected to any number of the second multiplexing circuits, according to the wireless signal;
a plurality of second digital signal processing modules, each is electrically connected to the second AFE and RF chain, wherein each of the second digital signal processing modules and each of the second AFE and RF chain form the second chain lines turned on according to the wireless signal;
and
an output port; and
an equalizer, which is electrically connected to the second digital signal processing modules through the output port, for combing the plurality of second electrical signals by using the signal processing method, and outputting the data signal.

US Pat. No. 10,250,302

METHOD FOR TRANSMITTING REFERENCE SIGNAL FOR CHANNEL MEASUREMENT IN MULTI-ANTENNA WIRELESS COMMUNICATION SYSTEM, AND APPARATUS THEREFOR

LG ELECTRONICS INC., Seo...

1. A method for transmitting demodulation reference signals (DMRSs) by an evolved Node B (eNB) in a wireless communication system supporting multiple antennas composed of a plurality of horizontal domain antennas and a plurality of vertical domain antenna, the method comprising:grouping total N antennas to Ng grouped antennas,
where N and Ng are positive integers and N>Ng>0;
mapping each of Ng grouped antennas to DMRS ports;
transmitting DMRSs to a user equipment (UE) based on the DMRS ports; and
receiving, from the UE, feedback on channel measurement information based on the DMRSs,
wherein when Ng is 4 or less, a large delay cyclic delay diversity (CDD) precoding is used for the DMRS ports, and
wherein when Ng is more than 4, the large delay CDD precoding is used for the NG groups configured by dividing the DMRS ports, and the same precoding is used between antennas belonging to each of the NG groups.

US Pat. No. 10,250,301

NETWORK OF ELECTRONIC DEVICES ASSEMBLED ON A FLEXIBLE SUPPORT AND COMMUNICATION METHOD

STMicroelectronics S.r.l....

1. An article, comprising:a garment; and
a network formed on the garment which comprises:
a main node comprising a main wired antenna;
at least one intermediate node comprising an intermediate wired antenna configured to be magnetically coupled to a respective electronic device for that intermediate node;
an electrical line electrically coupling the main node to the at least one intermediate node;
at least one electronic device magnetically coupled to the intermediate wired antenna; and
a power supply unit magnetically coupled to the main node via the main wired antenna;
wherein the main wired antenna comprises:
a main conductive loop coupled to the electrical line and having a forward stretch and a return stretch formed on the garment;
a secondary conductive loop arranged between the forward stretch and the return stretch so as to form first and second fringing capacitors in series;
wherein the first and second fringing capacitors define, within the main conductive loop, a parallel LC circuit forming a resonant antenna facilitating transfer of energy from the power supply unit to the main node.

US Pat. No. 10,250,300

WIRELESS CONDITION MONITORING SENSOR WITH NEAR FIELD COMMUNICATION INSECTION HARDWARE

1. A system comprising:a condition monitoring sensor comprising a first near field communication transponder and a memory, the condition monitoring sensor being affixed to and monitoring conditions of a mechanical system, the condition monitoring sensor storing a unique sensor identifier within the first near field communication transponder or the memory; and
an inspection device comprising a second near field communication transponder,
wherein an electronic coupling of the first and second near field communications is implemented based on a tapping operation between the condition monitoring sensor and the inspection device,
wherein the inspection device executes a query to the condition monitoring sensor via the electronic coupling to procure the unique sensor identifier, and
wherein the inspection device executes an inspection operation in response to procuring the unique sensor identifier from the condition monitoring sensor.

US Pat. No. 10,250,299

MOBILE PHONE WALLET

STMicroelectronics (Tours...

1. A case, comprising:a first portion configured to receive a first device having a first contactless communication antenna;
a second portion coupled to the first portion, the second portion including:
a first housing configured to receive a second device having a second contactless communication antenna; and
a third contactless communication antenna configured to couple with the second device;
wherein the first portion includes a fourth contactless communication antenna configured to couple with the received second device, the fourth contactless communication antenna being electrically connected to the third contactless communication antenna such that the second device harvests power from transmissions made by the first device using its first contactless communication antenna.

US Pat. No. 10,250,298

METHOD AND SYSTEM OF COMMUNICATING PERSONAL HEALTH DATA IN A NEAR FIELD COMMUNICATION ENVIRONMENT

Samsung Electronics Co., ...

1. A method for transmitting and receiving data by a Near Field Communication (NFC) manager in a NFC environment, the method comprising:reading, by a processor of the NFC manager, a first NFC Data Exchange Format (NDEF) message from a NFC tag embedded in a NFC agent;
checking, by the processor, a direction flag in a control field of the first NDEF message; and
when the direction flag of the first NDEF message indicates that the first NDEF message is directed to the NFC manger, writing, by the processor, a second NDEF message in which the direction flag indicates that the second NDEF message is directed to the NFC agent.

US Pat. No. 10,250,297

SYSTEM AND METHOD OF PROVIDING A SERVICE USING A NEAR FIELD COMMUNICATION TAG

Samsung Electronics Co., ...

1. A device which receives one or more services based at least in part on applications installed in the device, comprising:a first communication unit which receives tag information from a near field communication (NFC) tag;
a second communication unit which communicates with a server; and
a processor configured to:
in response to detecting an NFC tag within a near field communication range, receive, from the NFC tag via the first communication unit, tag information comprising a location value of the NFC tag;
check which application is being executed in the device when the NFC tag is detected;
provide, via the second communication unit, the server with a request for one or more services corresponding to the NFC tag and the checked application being executed in the device, wherein the request comprises the tag information and information regarding the checked application being executed in the device; and
receive, from the server via the second communication unit, service data for one or more services (i) selected, by the server, based on the tag information and (ii) matched, by the server, to the checked application being executed in the device using a preset service table.

US Pat. No. 10,250,296

COMMUNICATION DEVICE

Brother Kogyo Kabushiki K...

1. A communication device configured to communicate target data that is a target of communication with an external device according to a Near Field Communication (NFC) scheme, the communication device comprising:an NFC interface configured to execute NFC scheme communication;
a processor; and
a memory configured to store a computer program,
wherein, according to the computer program, the processor is configured to execute:
a first establishing step that communicates a first establishing command with the external device via the NFC interface so as to establish a first communication link between the communication device and the external device,
the first communication link being a communication link for each of the communication device and the external device to communicate according to a P2P-mode of the NFC scheme;
a first communicating step that communicates first target data with the external device via the NFC interface by using the first communication link;
a disconnecting step that disconnects the first communication link after communicating the first target data with the external device;
a second establishing step that communicates a second establishing command with the external device via the NFC interface after disconnecting the first communication link, so as to establish a second communication link between the communication device and the external device; and
a second communicating step that communicates second target data with the external device via the NFC interface by using the second communication link, the second target data being data generated by processing the first target data,
wherein in a first case where the first establishing command is sent to the external device in the first establishing step, the disconnecting step includes a step that sends a disconnecting command for disconnecting the first communication link to the external device via the NFC interface, so as to receive a response command responsive to the disconnecting command from the external device via the NFC interface.

US Pat. No. 10,250,295

NETWORK FIELDBUS POWER SUPPLY

EATON INTELLIGENT POWER L...

1. An apparatus comprising:a voltage dropper section configured to:
receive an input voltage and a communication signal at an input of the voltage dropper section,
regulate the input voltage, and
provide the regulated input voltage and the communication signal on an output of the voltage dropper section; and
an overvoltage switch section connected in parallel with the voltage dropper section wherein the overvoltage switch section being connected in parallel with the voltage dropper section comprises an input of the overvoltage switch section being connected to the output of the voltage dropper section, the overvoltage switch section being configured to;
receive, on the input of the overvoltage switch section, the regulated input voltage and the communication signal,
monitor the regulated input voltage provided from the voltage dropper section, and
remove the regulated input voltage and the communication signal from an output of the overvoltage switch section when the monitored regulated input voltage from the voltage dropper section exceeds a specified maximum wherein the overvoltage switch section being configured to remove the regulated input voltage and the communication signal comprises the overvoltage switch section being configured to use a control element connected to a shunt voltage regulator device connected across the output of the overvoltage switch section.

US Pat. No. 10,250,294

DATA RECOVERY OF DATA SYMBOLS

10. A method implemented by a substation circuit of a power line communication (PLC) system in which the substation circuit is situated remote from respective facilities at which a plurality of PLC endpoints are configured, the substation circuit being configured and arranged to share information, in the form of different data blocks respectively representing different aspects of the information, with the plurality of PLC endpoints via power lines which are power-coupled to the plurality of PLC endpoints, the method comprising:sharing the information with the plurality of PLC endpoints by transmitting, over the power lines, one of the different data blocks over a plurality of different communication channels;
over the power lines, receiving a first signal representing a transmitted one of the different data blocks over a first one of the plurality of different communication channels and receiving a second signal also representing the transmitted one of the different data blocks over a second one of the plurality of different communication channels, wherein at least one endpoint of the plurality of PLC endpoints is configured and arranged to: in a first mode, transmit the one of the different data blocks to at least one data processing apparatus by transmitting a single data block over a single one of the plurality of different communication channels, and in a second mode, transmit the one of the different data blocks to the at least one data processing apparatus by transmitting the one of the different data blocks over at least the first and second ones of the plurality of different communication channels; and
discerning information carried by said one of the different data blocks, as a function of signal and noise indications associated with the first signal and the second signal by combining energy from the first and second signals and converting the combined energy to output data representing said one of the different data blocks.

US Pat. No. 10,250,293

METHOD AND APPARATUS FOR PROVIDING SECURITY USING NETWORK TRAFFIC ADJUSTMENTS

1. A first waveguide system comprising:a processing system including a processor; and
a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations, the operations comprising:
obtaining a data tag associated with first data and second data, wherein the first data and the second data are directed to a recipient device;
generating first electromagnetic waves that contain the first data, the second data and the data tag; and
sending the first electromagnetic waves to a second waveguide system via a transmission medium and a dielectric coupler,
wherein the first electromagnetic waves propagate along the transmission medium, wherein the transmission medium comprises an external surface, and wherein the first electromagnetic waves propagate along the transmission medium without requiring an electrical return path,
wherein the data tag facilitates transmission of the first data by the second waveguide system according to a first network path, and
wherein the data tag facilitates transmission of the second data by the second waveguide system according to a second network path.

US Pat. No. 10,250,292

OPTICAL RAKE RECEIVER USING AN ETALON DETECTOR

RAYTHEON COMPANY, Waltha...

1. An optical communication method, the method comprising:receiving an optical signal by an optical resonator to provide an intensity modulated signal indicative of a modulation of the optical signal;
providing the intensity modulated signal to a selected channel receiver of a plurality of channel receivers;
recovering, by the selected channel receiver, from the intensity modulated signal, a multipath version of a transmitted signal embedded in the modulation of the optical signal, to provide a recovered signal; and
combining the recovered signal with an output of at least one other of the plurality of channel receivers to provide a combined output signal.

US Pat. No. 10,250,291

NOISE DISTRIBUTION SHAPING FOR SIGNALS, PARTICULARLY CDMA SIGNALS

AIRBUS DS GMBH, Taufkirc...

1. A method for noise distribution shaping for signals, the method comprising the acts of:generating a blanking control signal by comparing a received signal with at least one blanking threshold;
adapting the received signal by adding an offset value depending on an amplitude of the received signal; and
modifying the noise distribution of the received signal by applying blanking of the received signal under control of the blanking control signal,
wherein the amplitude of the received signal is calculated based on the estimated power Pest of the received signal and the offset value is calculated from the calculated amplitude of the received signal by multiplying a square root of the estimated power Pest with a predefined scaling factor ?,
wherein the predefined scaling factor ? is positive or negative, constant or time dependent, or a sign of the predefined scaling factor ? is changeable over time as function of the received signal.

US Pat. No. 10,250,290

FRONT END SWITCHING CIRCUITRY FOR CARRIER AGGREGATION

Qorvo US, Inc., Greensbo...

19. Radio frequency (RF) front-end circuitry comprising:a first multiple throw solid-state transistor switch (MTSTS) having a first pole port, a second pole port, a first set of throw ports, and a second set of throw ports, wherein the first MTSTS is configured to selectively couple the first pole port to any one of the first set of throw ports and to selectively couple the second pole port to any one of the second set of throw ports;
a second MTSTS having a third pole port, a third set of throw ports, a fourth pole port, and a fourth set of throw ports, wherein the second MTSTS is configured to selectively couple the third pole port to any one of the third set of throw ports and to selectively couple the fourth pole port to any one of the fourth set of throw ports;
a first diplexer having a first low band port configured to pass low band frequencies below 1 GHz and a first high band port configured to pass high band frequencies greater than or equal to 1 GHz, wherein the first low band port is coupled to the first pole port and the first high band port is coupled to the third pole port;
a second diplexer having a second low band port configured to pass low band frequencies below 1 GHz and a second high band port configured to pass high band frequencies greater than or equal to 1 GHz, wherein the second low band port is coupled to the second pole port and the second high band port is coupled to the fourth pole port;
microelectromechanical systems (MEMS) switching circuitry coupled to at least one of the first set of throw ports, the second set of throw ports, the third set of throw ports, and the fourth set of throw ports, wherein the MEMS switching circuitry is configured to selectively couple each one of a first plurality of RF ports to the at least one of the first set of throw ports, the second set of throw ports, the third set of throw ports, and the fourth set of throw ports; and
a control circuit comprising:
a transistor slave subcontroller coupled to the first MTSTS and the second MTSTS;
a MEMS slave subcontroller coupled to the MEMS switching circuitry; and
a master subcontroller coupled to the transistor slave subcontroller and the MEMS slave subcontroller;
the control circuit configured to operate the RF front end circuitry such that:
a first RF transmission signal and a second RF transmission signal provided at different ones of the first set of throw ports, the second set of throw ports, the third set of throw ports, the fourth set of throw ports, and the first plurality of RF ports are separately provided to different ones of the first diplexer and the second diplexer such that the first RF transmission signal and the second RF transmission signal may be simultaneously transmitted; and
a first RF receive signal from the first diplexer and a second RF receive signal from the second diplexer are separately provided to different ones of the first set of throw ports, the second set of throw ports, the third set of throw ports, the fourth set of throw ports, and the first plurality of RF ports such that the first RF receive signal and the second RF receive signal are simultaneously received.

US Pat. No. 10,250,289

ELECTRONIC DEVICE ANTENNAS WITH GROUND ISOLATION

Apple Inc., Cupertino, C...

1. An electronic device having front and rear faces, comprising:a metal housing;
a display cover layer coupled to the metal housing on the front face;
at least one electrical component layer adjacent to the display cover layer;
a system-in-package device having at least first and second grounding solder pads; and
a plurality of metal brackets including:
a first bracket that is coupled between the first grounding solder pad and the metal housing and that forms a grounding path between the first grounding solder pad and the housing; and
a second bracket that is coupled between the second grounding solder pad and the metal housing without forming a grounding path between the second grounding solder pad and the housing.

US Pat. No. 10,250,288

APPARATUS AND METHOD FOR A HAND WEARABLE ELECTRONIC DEVICE

1. An electronic device for positioning on a back-side of a human hand on a space on the back-side of hand, the space called opisthenar, wherein the space is bounded on one side by the wrist joint and on the other side by finger joints, comprising:the electronic device has a proximal edge and a distal edge, wherein the device is configured to be positioned on the back-side of the human hand, with the proximal edge at least a first distance away from the wrist joint that does not obstruct free movement of the wrist joint, and the distal end at least a second distance away from the finger joints that does not obstruct free movement of the finger joints;
the device has a top side and a bottom side, the top side of the device has a display screen, and wherein the bottom side of the device is curved with a curvature that substantially matches a transverse curvature of the back-side of the human hand for being positioned on the space on the back-side of the human hand;
the bottom side of the device has positioned thereon a removable substrate, wherein the removable substrate is for protecting veins on the back of the hand from a weight of the device; and
the bottom side of the device has an attachment mechanism that affixes to a wear-mechanism, wherein the wear mechanism secures the electronic device to the back-side of the hand.

US Pat. No. 10,250,287

DEVICE FOR REFLECTING, DEFLECTING, AND/OR ABSORBING ELECTROMATNETIC RADIATION EMITTED FROM AN ELECTRONIC DEVICE AND METHOD THEREFOR

Rowtan Technologies, LLC,...

1. A device used with a mobile electronic device, the device comprising:a metallic plate configured to be disposed between the mobile electronic device and a cover, wherein the metallic plate has a coating, and whereby the device deflects electromagnetic radio frequency (RF) radiation away from the user of the mobile electronic device.

US Pat. No. 10,250,286

WIRELESS COMMUNICATION APPARATUS AND ELECTRONIC APPARATUS

CANON KABUSHIKI KAISHA, ...

1. A wireless communication apparatus, comprising:an antenna comprising:
an antenna element having one end portion that is opened; and
a ground conductor to be used as a ground, to which another end portion of the antenna element is connected;
a wireless device connected to the antenna; and
a blocking member, which is arranged so as to be opposed to the antenna, is configured to block an electromagnetic wave radiated from the antenna element, and is not electrically connected to the ground conductor,
wherein the blocking member is arranged so as to, in a plan view from the blocking member side in a direction toward the antenna, avoid overlapping at least the one end portion of the antenna element and overlap the another end portion of the antenna element.

US Pat. No. 10,250,285

APPARATUS AND METHOD FOR A COMMUNICATION NETWORK

Nokia Technologies Oy, E...

1. An apparatus comprising:an exterior housing, said exterior housing comprising an aperture;
a first reader enclosed within said exterior housing, said first reader being for reading a first insertable integrated circuit for identifying a user in a first communications network, said first insertable integrated circuit being disposed beneath a power source within said exterior housing, and thereby not being removable from said exterior housing without powering down said apparatus;
a second reader in said exterior housing accessible through said aperture, said second reader being for reading a second user-insertable integrated circuit for identifying the user in the first communications network or in a second communications network, said second reader being able to detect a removal of said second user-insertable integrated circuit therefrom;
at least one processor; and
at least one memory comprising computer program code, the at least one memory and the computer program code configured, with the at least one processor, to cause the apparatus to perform the following:
detect a removal of the second user-insertable integrated circuit from the second reader through said aperture;
generate a control signal in response to detection of the removal; and
carry out a communication function in the first communication network in response to the generated control signal using the first insertable integrated circuit, said first insertable integrated circuit remaining powered when said second user-insertable integrated circuit is removed from the second reader through said aperture.

US Pat. No. 10,250,284

RECEIVING CIRCUIT OF WIRELESS COMMUNICATION SYSTEM AND METHOD OF RECEIVING RF SIGNAL

REALTEK SEMICONDUCTOR COR...

1. A receiving circuit of a wireless communication system, the receiving circuit configured to receive a radio frequency (RF) signal including a data signal and an interference signal and amplify the RF signal according to an analog gain, the receiving circuit comprising:a low noise amplifier (LNA) configured to generate a first gain according to a first bias signal and amplifying the RF signal using the first gain to generate an amplified RF signal;
an RF power detection circuit coupled to an output of the LNA and configured to detect the amplified RF signal in an RF band to generate a control signal corresponding to the power of the amplified RF signal, the control signal being an analog signal;
an LNA bias circuit coupled to the LNA and the RF power detection circuit and configured to provide the first bias signal to the LNA according to the control signal;
a mixer coupled to the LNA and configured to down-convert the amplified RF signal to generate a down-converted radio frequency (RF) signal; and
a filter circuit coupled to the mixer and configured to filter out the interference signal from the down-converted RF signal and output the data signal;
wherein the mixer is a passive mixer without signal amplifying functions, and the analog gain is substantially proportional to the first gain.

US Pat. No. 10,250,283

DIGITAL FREQUENCY LOCKED LOOP FOR WIDEBAND COMMUNICATIONS CHANNELS REQUIRING EXTREME DOPPLER COMPENSATION AND LOW SIGNAL TO NOISE RATIO

The United States of Amer...

1. An apparatus comprising:a frequency detector comprising:
a Fast Fourier Transform processor receiving a complex baseband RF input signal and outputting at least one positive frequency bin output and at least one negative frequency bin output;
a first accumulator receiving directly or indirectly the at least one positive frequency bin output and outputting a positive frequency band energy estimate;
a second accumulator receiving directly or indirectly the at least one negatively frequency bin output and outputting a negative frequency band energy estimate; and
a subtractor receiving the positive frequency band energy estimate and the negative frequency band energy estimate and outputting an instantaneous frequency error estimate representing a difference between the positive frequency band energy estimate and the negative frequency band energy estimate.

US Pat. No. 10,250,282

STRUCTURE FOR RADIOFREQUENCY APPLICATIONS

Soitec, Bernin (FR)

1. A structure for radiofrequency applications, comprising:a semiconducting supporting substrate; and
a trapping layer arranged on the supporting substrate, the trapping layer comprising polycrystalline silicon including 1% to 20% of carbon;
wherein the trapping layer comprises a defect density greater than a predetermined defect density, the predetermined defect density being the defect density for which the electrical resistivity of the trapping layer is greater than or equal to 10,000 ohm·cm over a temperature range extending from ?20° C. to 120° C.

US Pat. No. 10,250,281

ECC DECODER HAVING ADJUSTABLE PARAMETERS

SanDisk Technologies LLC,...

1. A device comprising:a non-volatile memory; and
a controller, the controller connected to the non-volatile memory, the controller comprising an electronic processor that when executing instructions configures the controller to:
generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory, the traffic type indicator having a first value responsive to the one or more read requests corresponding to a first traffic type and having a second value responsive to the one or more read requests corresponding to a second traffic type; and
designate one or more decode parameter values based on the traffic type indicator to improve performance of a decoding process of the controller.

US Pat. No. 10,250,280

METHOD AND APPARATUS OF A FULLY-PIPELINED LAYERED LDPC DECODER

TensorCom, Inc., Culver ...

1. An apparatus, comprising:a plurality of processors arranged in a pipeline structure and configured to operate on a plurality of layers of data, each layer comprising a plurality of groups of data symbols received from a noisy transmission medium; and
a memory comprising an input coupled to an output of a last processor in the pipeline structure, and an output coupled to an input of a first processor in the pipeline structure, the memory comprising read and write logical structures configured to perform multiplexor and de-multiplexor operations, comprising:
for each group in each layer, applying a stored data set read from the memory to the first processor in the pipeline structure;
producing a calculation of a log-likelihood ratio (LLR) of the data symbols at the output of the last processor; and
storing the LLR in the memory; and
operating at least one processor in the pipeline structure to process a next layer before a current layer is completed, wherein a stored data set in the next layer comprises a portion of the LLR calculation produced from a layer previous to the current layer thereby providing for non-blocking check-node-update scheduling.

US Pat. No. 10,250,279

CIRCUITS AND METHODS FOR WRITING AND READING DATA

Infineon Technologies AG,...

1. A writing circuit for writing write data into a memory, comprising:an evaluator configured for providing an error handling code on the basis of the write data,
a modifier configured for providing modified extended write data,wherein the modifier is configured to reversibly modify extended write data comprising both the write data and the error handling code by applying a mathematical operation or a Boolean operation to the extended write data and address information related to a writing address in order to provide the modified extended write data, anda writer configured for writing the modified extended write data in a position of the memory defined by a writing address.

US Pat. No. 10,250,278

COMPRESSION OF A SET OF INTEGERS

INTEL CORPORATION, Santa...

1. An apparatus comprising:a memory;
an interface to receive a list information element via an input stream, the list information element to include indications of a plurality of integers; and
logic, at least a portion of which is implemented in hardware comprising a circuit coupled with the memory, the logic to:
determine a range of the plurality of integers;
generate a compressed list information element;
add an indication of the range to the compressed list information element;
recursively subdivide the range into one or more sub-ranges;
add, for each of the one or more sub-ranges, an indication of the one or more sub-ranges to the compressed list information element; and
store the compressed list information element in the memory.

US Pat. No. 10,250,277

SAR-TYPE ANALOG-DIGITAL CONVERTER USING RESIDUE INTEGRATION

POSTECH ACADEMY-INDUSTRY ...

1. A successive approximation register (SAR)-type analog-digital converter (ADC) using residue integration, comprising:a coarse/fine SAR conversion unit configured to receive an analog input voltage and convert the received voltage into an MSB digital signal in a coarse SAR conversion mode, and receive a feedback voltage and convert the received voltage into an LSB digital signal in a fine SAR conversion mode;
a residue integration unit configured to repeatedly amplify a residual voltage with a predetermined gain by a predetermined number of times and output the amplified voltage as a final target multiple, the residual voltage corresponding to a voltage difference between the analog input voltage and an analog voltage obtained by converting the digital signal into an analog signal; and
a digital signal output unit configured to add up a coarse SAR conversion result supplied from the coarse/fine SAR conversion unit, a result of a delta-signal modulation (DSM) loop installed in the residue integration unit, and a fine SAR conversion result supplied from the coarse/fine SAR conversion unit, and output a digital code of the corresponding bit.

US Pat. No. 10,250,276

SEGMENTED DIGITAL-TO-ANALOG CONVERTER

TEXAS INSTRUMENTS INCORPO...

1. A segmented digital-to-analog converter (DAC) circuit to generate an analog output signal that represents a value of a K-bit digital input signal, the digital input signal including a first subword having an integer number M bits including a most significant bit of the digital input signal, a second subword having an integer number I bits of the digital input signal, and a third subword having an integer number L bits including a least significant bit of the digital input signal, where M, I and L are each greater than 1, and where K=M+I+L, the segmented DAC circuit comprising:a resistor DAC to convert the first subword to a first analog output signal that represents a value of the first subword, the resistor DAC including:
a first converter output to provide the first analog output signal,
a resistive voltage divider with an input to receive a reference voltage signal, a plurality of resistors, and a plurality of tap nodes, and
a first switching circuit, including a plurality of switches individually connected between a corresponding one of the tap nodes and the input of the resistive voltage divider, the individual switches operative to selectively connect the corresponding one of the tap nodes with the input of the resistive voltage divider based on a corresponding bit of the first subword;
an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal; and
a Sigma Delta modulator (SDM) to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of the second and third subwords, where N is less than I+L.

US Pat. No. 10,250,275

DIGITAL VOLTAGE SAMPLING

HEWLETT PACKARD ENTERPRIS...

1. A voltage sampling method, comprising:producing a sampled voltage from an output of an electronic device by a coupler coupled to a first set of resistors and a second set of resistors;
dividing, by a voltage divider, the sampled voltage into a fine sampled voltage and a coarse sampled voltage, the fine sampled voltage provided by an output of a differential amplifier coupled across the first set of resistors;
converting, by a first analog-to digital converter coupled to the output of the differential amplifier, the fine sampled voltage to a first digital value that represents the fine sampled voltage;
converting, by a second analog-to-digital converter coupled to at least one of resistors among a set of second resisters, the coarse sampled voltage to a second digital value that represents the coarse sampled voltage; and
producing a third digital value by combining the first digital value with the second digital value, the third digital value representing the sampled voltage.

US Pat. No. 10,250,274

SAMPLE AND HOLD DEVICE

MELEXIS TECHNOLOGIES NV, ...

1. A sample and hold system, for capturing and reading a trace of at least one input signal,the sample and hold system comprising a readout device, a controller, an array of segments, each segment comprising a plurality of unit cells and a dummy unit cell, and access switches for controlling the access to the unit cells and the dummy unit cells, wherein at least part or all of the access switches are segment switches which are present between the segments and the readout device,
wherein the controller is adapted for controlling the sample and hold system,
such that during an acquisition phase a trace of samples is taken from the input signal and held in the unit cells and such that during a readout phase the samples held in the unit cells or in the dummy unit cells are read out by the readout device,
wherein the controller is adapted for controlling the sample and hold system,
such that the dummy unit cells are sampled in a period when there is no input signal,
and such that after configuring the segment switches to connect a segment to the reading device, the dummy unit cell, is the first cell which is read out by the readout device resulting in a readout value wherein the sample and hold system is adapted for ignoring the readout value of the dummy unit cells during further processing.

US Pat. No. 10,250,273

BAND SPECIFIC INTERLEAVING MISMATCH COMPENSATION IN RF ADCS

Texas Instruments Incorpo...

1. An integrated circuit chip, comprising:an interleaved analog-to-digital converter (ADC), comprising a plurality of ADCs configured to sample an analog signal, the interleaved ADC configured to convert the analog signal into an interleaved analog-to-digital signal (IADC signal); and
an interleaving calibration circuit coupled to the interleaved ADC, the interleaving calibration circuit configured to:
receive the IADC signal from the interleaved ADC;
generate a mismatch profile estimate corresponding to a plurality of spurious signals, to generate one or more mismatch profile estimates;
in response to determining that a first mismatch profile falls in at least one of a plurality of frequency bands of interest, generate a set of model parameters based on the mismatch profile estimate.

US Pat. No. 10,250,272

LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS)

MAXLINEAR, INC., Carlsba...

1. A system, comprising:a digital-to-analog converter (DAC) that comprises:
an encoder that generates a multi-bit output based on a multi-bit input, wherein:
the multi-bit input comprises one or more bits from an input to the DAC; and
a number of bits in the multi-bit input is two or more and a number of bits in the multi-bit output is greater than the number of bits in the multi-bit input;
a plurality of first converter elements, wherein each first converter element generates an output according to a single bit of the multi-bit output of the encoder;
one or more second converter elements, wherein:
each second converter element generates an output according to a single bit; and
at least one second converter element receives at least one remaining bit in the input to the DAC that is not included in the multi-bit input to the encoder; and
a combiner that generates a combined output based on combining outputs from the plurality of first converter elements and outputs from the one or more second converter elements.

US Pat. No. 10,250,271

QUANTUM COMPUTATION APPARATUS AND QUANTUM COMPUTATION METHOD

Kabushiki Kaisha Toshiba,...

1. A quantum computation apparatus comprising:a plurality of quantum nonlinear oscillators each of which implements superposition of distinguishable quantum states by bifurcating one quantum state via a quantum adiabatic change controlled by a bifurcation parameter, and which couple with each other by nondissipative coupling;
a controller configured to individually control the bifurcation parameters of the quantum nonlinear oscillators; and
a measuring device configured to measure outputs from the quantum nonlinear oscillators.

US Pat. No. 10,250,270

FRACTIONAL CLOCK GENERATOR WITH RAMP CONTROL INCLUDING FIXED TIME INTERVAL AND COARSE/FINE FREQUENCY CHANGE STEPS

QUALCOMM Incorporated, S...

1. A method, comprising:generating an index of edge positions of an input clock signal;
generating an output clock signal based on a current divider ratio and the index;
generating a first signal based on a selected duration for a frequency change step of the output clock signal;
synchronizing the generation of the first signal with the generation of the index, wherein synchronizing the generation of the first signal with the generation of the index, comprises:
generating a second signal indicating an end of a sequence of edges of the output clock signal at substantially the same time as the generation of the index; and
generating the first signal based on the second signal;
generating a fourth signal indicating the end of the frequency change step based on the first and second signals; and
determining the current divider ratio.

US Pat. No. 10,250,269

OSCILLATOR SYSTEM

NXP B.V., Eindhoven (NL)...

1. An oscillator system comprising:a voltage controlled oscillator circuit including an input to receive an input voltage and an output to provide an oscillation signal, the input voltage controls a frequency of the oscillation signal;
a frequency to voltage circuit, the frequency to voltage circuit including an input to receive the oscillation signal, the frequency to voltage circuit including an output for producing a voltage dependent on a frequency of the oscillation signal;
a comparison circuit including an amplifier, the amplifier includes an inverting input, a non inverting input, and an output, during a sampling phase of the comparison circuit, the non inverting input receives a reference voltage and the inverting input is coupled at least via a first switch to the output of the amplifier and is coupled to a first capacitor wherein a voltage of the output of the amplifier is sampled by the first capacitor, wherein during a comparison phase of the comparison circuit, the first switch is open and the non inverting amplifier receives a voltage generated by the output of the frequency to voltage circuit and the inverting input is coupled to the first capacitor, wherein the voltage of the output of the amplifier is provided to the input of the voltage controlled oscillator circuit during the comparison phase.

US Pat. No. 10,250,268

PLL CIRCUIT

NIHON DEMPA KOGYO CO., LT...

1. A PLL circuit, comprising:a voltage control oscillator that outputs an oscillation signal based on a control voltage;
a frequency difference detector that detects a frequency difference between a reference signal and the oscillation signal, the frequency difference detector outputting a first control value based on the frequency difference which is detected;
a phase difference detector that detects a phase difference between the reference signal and the oscillation signal, the phase difference detector outputting a second control value based on the phase difference which is detected; and
an outputter that outputs the control voltage, based on the first control value and the second control value, to the voltage control oscillator while the second control value does not exceed a predetermined range, the outputter outputting the control voltage, based on a corrected value obtained by correcting the first control value and the second control value, to the voltage control oscillator while the second control value exceeds a predetermined range.

US Pat. No. 10,250,267

DIFFERENTIAL PHASE-FREQUENCY DETECTOR

International Business Ma...

1. A phase-frequency detector (PFD) electrically coupled to a charge pump of a phase-locked-loop (PLL), the PFD comprising:a first differential latch electrically coupled to the charge pump, the first differential latch configured to, in response to receiving a differential pair of reference clock signals and a differential pair of reset signals, drive a differential pair of increment signals to the charge pump, the increment signals being in the form of voltage swings to a first and a second power rail;
a second differential latch electrically coupled to the charge pump, the second differential latch configured to, in response to receiving a differential pair of feedback clock signals and the differential pair of reset signals, drive a differential pair of decrement signals to the charge pump, the decrement signals being in the form of voltage swings to a first and a second power rail; and
a differential AND gate electrically coupled to the first differential latch and further electrically coupled to the second differential latch, the differential AND gate having two inputs and an output, and producing a logic true output if and only if both inputs are logic true, the differential AND gate configured to, in response to receiving a true value from the differential pair of increment signals from the first differential latch and further in response to receiving a true value from the differential pair of decrement signals from the second differential latch, drive the differential pair of reset signals to the first differential latch and further drive the differential pair of reset signals to the second differential latch, the reset signals being in the form of voltage swings to a first and a second power rail.

US Pat. No. 10,250,266

OSCILLATOR CALIBRATION SYSTEM

NXP B.V., Eindhoven (NL)...

1. A method for tuning an oscillator circuit, the method comprising:comparing, with a comparison circuit, an output of a first oscillator circuit with an output of a second oscillator circuit to generate a comparison value, the comparison value based on a frequency of the output of the first oscillator circuit and a frequency of the output of the second oscillator circuit;
comparing the comparison value with a sampled value stored in memory, wherein the sampled value was generated from a comparison with the comparison circuit of an output of the second oscillator circuit with an external clock signal;
providing a tune value to the first oscillator circuit to tune the frequency of the output the first oscillator circuit, the tune value based on the comparing the comparison value with the sampled value.

US Pat. No. 10,250,265

SINGLE-LOCK DELAY LOCKED LOOP WITH CYCLE COUNTER AND METHOD THEREFOR

Everspin Technologies, In...

1. A method for operating a delay locked loop having a first end and a second end, comprising:providing a clock signal to the first end of the delay locked loop, wherein the clock signal is a periodic signal that includes a plurality of cycles;
detecting that the delay locked loop has locked to the clock signal;
after detecting that the delay locked loop has locked, omitting an omitted cycle of the plurality of cycles of the clock signal as the clock signal is provided to the delay locked loop at the first end;
detecting the omitted cycle of the plurality of cycles at a location within the delay locked loop; and
determining a number of cycles of the clock signal in a delay of at least a portion the delay locked loop, wherein the number of clock cycles in the delay corresponds to a number of clock cycles that transpired while the omitted cycle of the plurality of cycles propagates from the first end of the delay locked loop to the location within the delay locked loop.

US Pat. No. 10,250,264

MULTIPLYING DELAY-LOCKED LOOP USING SAMPLING TIME-TO-DIGITAL CONVERTER

Marvell World Trade Ltd.,...

1. A multiplying delay-locked loop circuit, comprising:a delay chain including a plurality of variable delay circuits connected in series and having a delay chain output; and
a feedback loop including circuitry for deriving, from feedback signals supplied by the delay chain, a digital control signal representing magnitude and sign of phase offset in the delay chain output, for controlling delay in ones of the variable delay circuits in the plurality of variable delay circuits, the circuitry for deriving a digital control signal comprising a sampling time-to-digital converter configured to operate on a time delay between inputs to generate the digital control signal as an output.

US Pat. No. 10,250,263

REPLICA CASCODE BIAS VOLTAGE-CONTROLLED OSCILLATORS

Lattice Semiconductor Cor...

1. A voltage oscillator comprising:a voltage-to-current converter configured to generate a control current responsive to receiving a control voltage, the voltage-to-current converter comprising a first transistor and a second transistor, a drain of the first transistor coupled to a source of the second transistor and a gate of the second transistor biased by a bias voltage;
a current controlled oscillator coupled to the voltage-to-current converter to receive the control current and to generate a periodic output signal having a frequency corresponding to the control current; and
a bias voltage generation circuit coupled to the voltage-to-current converter, the bias voltage generation circuit comprising a replica bias circuit configured to generate a replica voltage corresponding to a voltage at the source of the second transistor.

US Pat. No. 10,250,262

INTEGRATED CIRCUIT INCLUDING AN ARRAY OF LOGIC TILES, EACH LOGIC TILE INCLUDING A CONFIGURABLE SWITCH INTERCONNECT NETWORK

Flex Logix Technologies, ...

1. An integrated circuit comprising:a field programmable gate array including:
a plurality of logic tiles, wherein each logic tile (i) is physically adjacent to at least one other logic tile of the plurality of logic tiles and (ii) includes:
a configurable switch interconnect network, wherein the configurable switch interconnect network includes a plurality of switches electrically interconnected and arranged into a plurality of switch matrices, wherein the plurality of switch matrices are arranged into a plurality of stages including:
at least two stages of switch matrices, configured in a hierarchical network, and
a mesh stage of switch matrices, directly connected to the hierarchical network, wherein each switch matrix of the mesh stage includes an output that is directly connected to an input of a plurality of different switch matrices of the mesh stage, and
wherein the mesh stage of switch matrices of each logic tile of the plurality of logic tile is directly connected to at least one mesh stage of switch matrices of at least one other logic tile of the plurality of the logic tiles.

US Pat. No. 10,250,261

SIGNAL TRANSMITTING CIRCUIT

SK hynix Inc., Gyeonggi-...

1. A signal transmitting circuit comprising:a logic gate suitable for transmitting a signal, and operated by a first supply voltage;
a pre-driver circuit suitable for generating a pull-up control signal and a pull-down control signal in response to the transmitted signal, wherein a second supply voltage having a level greater than the target level of the first supply voltage is used to generate the pull-up control signal and the pull-down control signal;
a first NMOS transistor suitable for pulling up an output node using the first supply voltage, in response to the pull-up control signal;
a second NMOS transistor suitable for pulling down the output node using a pull-down voltage, in response to the pull-down control signal; and
an initialization circuit suitable for initializing the pull-up control signal and the pull-down control signal when the level of the first supply voltage is less than a reference value, before a power-up signal is enabled.

US Pat. No. 10,250,260

DATA COMMUNICATION SYSTEM AND SEMICONDUCTOR DEVICE

SEIKO EPSON CORPORATION, ...

1. A data communication system comprising:a clock signal line for transmitting a clock signal;
a data signal line for transmitting data;
a first data communication circuit for outputting a clock signal to the clock signal line, and receiving input of data from the data signal line, or outputting data as open drain output or open collector output to the data signal line;
a second data communication circuit for receiving input of a clock signal from the clock signal line, and receiving input of data from the data signal line, or outputting data as open drain output or open collector output to the data signal line;
a first pull-up resistor connected between the data signal line and a wiring of a power supply potential on a higher potential side;
a second pull-up resistor for selectively pulling up the data signal line, wherein one end of the second pull-up resistor is connected to the data signal line; and
a pull-up control circuit that is connected to the second pull-up resistor, wherein when a power supply potential on the higher potential side is supplied, the pull-up control circuit outputs a pull-up control signal at a high level to the other end of the second pull-up resistor at least in response to a clock signal.

US Pat. No. 10,250,259

DEVICE AND METHOD FOR DIGITAL SIGNAL TRANSMISSION

Synaptics Japan GK, Toky...

1. A digital signal transmission apparatus, comprising:transmitter circuitry configured to output first and second digital transmission signals complementary to each other; and
receiver circuitry comprising:
AND circuitry configured to output a first output signal having a logical value based on a product of a logical value of the first digital transmission signal and a logical value complementary to a logical value of the second digital transmission signal;
OR circuitry configured to output a second output signal having a logical value based on a sum of a logical value complementary to the logical value of the first digital transmission signal and the logical value of the second digital transmission signal; and
XOR circuitry configured to output a third output signal having a logical value of an exclusive logical sum of the first and second output signals.

US Pat. No. 10,250,258

DEVICE AND METHOD FOR DETECTING SEMICONDUCTOR SUBSTRATE THICKNESS

NXP B.V., Eindhoven (NL)...

1. An Integrated Circuit (IC) device, the IC device comprising:a semiconductor substrate;
a charge emitter embedded in the semiconductor substrate and configured to produce an electrical charge in the semiconductor substrate;
a charge sensor embedded in the semiconductor substrate and configured to generate a response signal in response to the electrical charge produced in the semiconductor substrate, wherein a magnitude of the response signal depends on a thickness of the semiconductor substrate; and
wherein the charge sensor comprises a diode.

US Pat. No. 10,250,257

DIGITAL CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR

MIE Fujitsu Semiconductor...

1. A logic circuit, comprising:first and second transistors of different conductivity types having controllable current paths coupled between an input node and an output node, the first and second transistors arranged in parallel to one another between the input node and the output node, the first and second transistors receive complementary signals at their gates, respectively;
wherein each of the first and second transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed fully over a relatively highly doped screening layer formed fully over and in contact with a doped body region.

US Pat. No. 10,250,256

SYSTEM AND METHOD FOR IDENTIFYING OBJECTS USING CAPACITIVE SENSING TECHNOLOGY

Horizon Group USA, Inc., ...

1. A system for identifying a plurality of objects using capacitive sensing, the system comprising:a sensing array, wherein:
the sensing array includes a capacitive sensor pad; and
each of the plurality of objects includes at least one conductive surface; and
a microcontroller, wherein the microcontroller is configured to identify each of the plurality of objects based on at least one capacitance detected between each of the plurality of objects and the capacitive sensor pad, wherein each of the plurality of objects are identified with a ternary code, wherein (i) a first ternary code level is associated with a conductive surface including a surface area larger than a surface area of the capacitive sensor pad and (ii) a second ternary code level is associated with a conductive surface including a surface area smaller than the surface area of the capacitive sensor pad.

US Pat. No. 10,250,255

SEMICONDUCTOR DEVICE AND CIRCUIT ARRANGEMENT USING THE SAME

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate of a first conductivity type;
an epitaxial layer of the first conductivity type in contact with a surface of the semiconductor substrate;
first and second regions determined with a certain distance in the epitaxial layer;
a first switching element that is formed in the first region and is electrically coupled to the semiconductor substrate;
a second switching element that is formed in the second region and is electrically coupled to the semiconductor substrate so as to be coupled in series to the first switching element,
the first switching element including:
a first electrode formed in a first trench via a first insulating film, the first trench being formed over the epitaxial layer;
a first-impurity-region first part of the second conductivity type in the epitaxial layer, the first-impurity-region first part being formed with a first thickness in contact with the first insulating film at a smaller depth than a bottom of the first trench; and
a second-impurity-region first part of the first conductivity type in the epitaxial layer, the second-impurity-region first part being formed in contact with the first-impurity-region first part at a smaller depth than the first-impurity-region first part,
the second switching element including:
a second electrode formed in a second trench via a second insulating film, the second trench being formed over the epitaxial layer;
a first-impurity-region second part of the second conductivity type in the epitaxial layer, the first-impurity-region second part being formed with a second thickness in contact with the second insulating film at a smaller depth than a bottom of the second trench;
a second-impurity-region second part of the first conductivity type in the epitaxial layer, the second-impurity-region second part being formed in contact with the first-impurity-region second part at a smaller depth than the first-impurity-region second part; and
columns of the second conductivity type, the columns being extended from the first-impurity-region second part toward the semiconductor substrate and away from both the second insulating film and the second electrode.

US Pat. No. 10,250,254

SYSTEM FOR CONTROLLING POWER DEVICE

LSIS CO., LTD., Anyang-s...

1. A system for controlling a power device, comprising:one or more power elements;
one or more drive modules configured to provide a drive signal with respect to the one or more power elements through a signal line; and
an upper level controller configured to transmit a control signal with respect to the one or more drive modules through a signal line,
wherein each of the one or more drive modules is provided with a first wireless module,
wherein the upper level controller is provided with a second wireless module corresponding to the first wireless module,
wherein each of the one or more drive modules is configured to transmit state information of the one or more power elements and the one or more drive modules to the second wireless module through the first wireless module,
wherein the upper level controller is configured to transmit a control signal corresponding to the state information to the first wireless module through the second wireless module,
wherein each of the one or more drive modules is configured to transmit an error feedback signal with respect to a state of the one or more power elements and a state of the one or more drive modules to the upper level controller, and generate the drive signal with respect to the one or more power elements being directly connected thereto.

US Pat. No. 10,250,253

METHOD AND APPARATUS FOR A BROWN OUT DETECTOR

TEXAS INSTRUMENTS INCORPO...

1. A detector comprising:a pre-charge circuit configured to receive a supply voltage;
a pre-charged comparator coupled to the pre-charge circuit and configured to receive the supply voltage and configured to generate a transition signal at a transition node;
a diode connected transistor configured to receive the supply voltage;
a capacitor coupled to the diode connected transistor; and
an inverter coupled to the diode connected transistor, the inverter having an input coupled to the transition node, and being configured to generate an enable signal when the supply voltage is below a threshold voltage.

US Pat. No. 10,250,252

CONTROL CIRCUIT AND METHOD THEREFOR

SEMICONDUCTOR COMPONENTS ...

1. A control circuit for a power supply comprising:the control circuit configured to operate a switching signal at a frequency to switch a power switch and to regulate an output voltage to a target value;
an oscillator configured to form an oscillator signal at the frequency, and to cause the switching signal to switch at the frequency; and
a first circuit configured to control the frequency of the oscillator signal to step-wise increase during a start-up sequence initiated by the control circuit wherein a time interval of each increase is greater than a period of the switching signal and wherein the control circuit terminates increasing the frequency in response to regulating the output voltage to the target value.

US Pat. No. 10,250,251

RF SENSOR IN STACKED TRANSISTORS

INFINEON TECHNOLOGIES AG,...

1. An RF switch comprising:a plurality of series-coupled RF switch cells coupled between an RF input and ground;
a first transistor comprising a first current node coupled to a first load resistor, a second current node coupled to ground, and a control node coupled to a first internal switch node associated with one of the plurality of series-coupled RF switch cells; and
a first filter having an input coupled to the first current node of the first transistor and an output configured for providing a DC voltage corresponding to the RF power present at the first internal switch node.

US Pat. No. 10,250,250

BOOTSTRAPPED SWITCHING CIRCUIT

ANALOG DEVICES, INC., No...

1. A bootstrapped switching circuit with accelerated turn on, comprising:a sampling switch to receive a voltage input signal and a gate voltage;
a bootstrapped voltage generator comprising a positive feedback loop, wherein the positive feedback loop is activated by a clock signal to generate the gate voltage for turning on the sampling switch, and the positive feedback loop comprises: an output transistor to output the gate voltage of the sampling switch, and an input transistor to receive the voltage input signal and to be driven by the gate voltage as positive feedback; and
a jump start circuit to turn on the output transistor, and to cease turning on the output transistor after a limited period of time during a startup of the positive feedback loop to allow the positive feedback loop to continue assisting the output transistor in generating the gate voltage for turning on the sampling switch.

US Pat. No. 10,250,249

RECUPERATIVE GATE DRIVE CIRCUIT AND METHOD

Bel Power Solutions Inc.,...

1. A gate driving circuit for a switching element having a parasitic input capacitance, the circuit comprising:a controller configured to generate driver control signals;
a power source;
a gate driver coupled to each of the controller and the power source, and configured to generate gate drive signals to the switching element, said gate drive signals corresponding to control signals from the controller,
wherein the gate drive signals comprise a first burst pulse signal, a driving pulse signal following the first burst pulse signal, and a second burst pulse signal following the driving pulse signal.

US Pat. No. 10,250,248

SYNCHRONOUS CLOCK GENERATION USING AN INTERPOLATOR

TEXAS INSTRUMENTS INCORPO...

1. A method, comprising:receiving a device clock signal;
generating a synchronization (SYSREF) clock signal at least partially according to the device clock signal;
generating a shifted clock signal at least partially according to the device clock signal;
sampling, by a latch, the SYSREF clock signal using the shifted clock signal; and
outputting the sampled SYSREF clock signal.

US Pat. No. 10,250,247

SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor;
a second transistor;
a third transistor; and
a load,
wherein each of a drain of the first transistor and a drain of the second transistor is electrically connected to the load,
wherein each of a source of the first transistor and a source of the second transistor is electrically connected to a drain of the third transistor,
wherein the first transistor and the second transistor each comprise a backgate,
wherein a gate of the first transistor is supplied with a first potential,
wherein a gate of the second transistor is supplied with a second potential,
wherein a gate of the third transistor is supplied with a fourth potential,
wherein a source of the third transistor is supplied with a fifth potential,
wherein the backgate of the first transistor is supplied with a sixth potential,
wherein the first potential and the second potential are lower than the fifth potential,
wherein the sixth potential is higher than the fifth potential,
wherein the semiconductor device is configured to compare the first potential and the second potential, and
wherein the semiconductor device is configured to generate a third potential based on a comparison result.

US Pat. No. 10,250,246

PROGRAMMABLE NEUROMORPHIC DEVICE

Syntron Systems Inc., Br...

1. A first logic element in an array effective to generate an output state signal, wherein the array includes at least the first logic element, a second logic element configured to be in communication with the first logic element, a third logic element configured to be in communication with the first logic element, a first switching element to be in communication with the first logic element, and a second switching element to be in communication with the first switching element, the first logic element comprising:an input circuit configured to:
receive a first input state signal from the second logic element;
receive a second input state signal from the third logic element;
receive a third input state signal from the first switching element;
determine a sum based on the first, second, and third input state signals;
a comparator circuit configured to be in communication with the input circuit, the comparator circuit being configured to:
receive the sum from the input circuit;
compare the sum with a threshold;
generate an intermediate signal based on the comparison of the sum with the threshold;
a state machine configured to be in communication with the comparator circuit, the state machine being configured to:
identify a current state of the first logic element;
receive the intermediate signal from the comparator circuit;
generate an output state signal based on the intermediate signal and based on a current state of the first logic element, wherein the output state signal is effective to indicate a subsequent state of the first logic element; and
a first switch circuit configured to be in communication with the state machine and the first switch element, the first switch element being configured to:
send and receive the output state signal to and from the first switch circuit;
receive a switch state signal from the second switch element, wherein the switch state signal is effective to indicate that the second switch element is permitted to accept the output state signal; and
in response to receipt of the switch state signal, send the output state signal to the second switch element, and in response to receipt of the output state signal from the second switch element, send the output state signal to the first switch circuit.

US Pat. No. 10,250,245

INPUT DEVICE WHICH OUTPUTS A SIGNAL HAVING A LEVEL CORRESPONDING TO A STATE IN WHICH A VOLTAGE VALUE OF AN INPUT SIGNAL IS HIGHER OR LOWER THAN A THRESHOLD VALUE

THINE ELECTRONICS, INC., ...

1. An input device comprising:a first reference terminal set at a first reference voltage;
a second reference terminal set at a second reference voltage;
a single signal input terminal configured to receive an input signal;
a signal output terminal configured to output a signal having a level corresponding to a state in which a voltage value of the input signal is higher or lower than a predetermined threshold value;
a first MOS transistor having a drain directly connected to the first reference terminal, a gate electrically connected to the single signal input terminal, and a source;
a second MOS transistor having a drain electrically connected to the first reference terminal, a gate directly connected to the first reference terminal, and a source;
a first resistor having one end directly connected to the source of the first MOS transistor, and the other end electrically connected to a first node;
a second resistor having one end directly connected to the source of the second MOS transistor, and the other end electrically connected to a second node;
a third resistor having one end electrically connected to the first node, and the other end electrically connected to the second reference terminal;
a fourth resistor having one end electrically connected to the second node, and the other end electrically connected to the second reference terminal; and
a comparator circuit having a first input terminal electrically connected to the first node and set at the same voltage as the first node, a second input terminal electrically connected to the second node and set at the same voltage as the second node, and an output terminal, which is the signal output terminal, configured to output a signal having a level corresponding to a state in which a voltage of the first input terminal is higher or lower than a voltage of the second input terminal.

US Pat. No. 10,250,244

MINIMUM PULSE-WIDTH ASSURANCE

Silanna Asia Pte Ltd, Si...

1. A method for assuring a minimum pulse-width using a minimum pulse-width assurance circuit, the method comprising:receiving a first signal at a first input of a first logic circuit, wherein the first input of the first logic circuit is coupled to an input of the minimum pulse-width assurance circuit;
receiving, at a second input of the first logic circuit, a second signal from a first one-shot circuit;
receiving, at a first input of a second logic circuit, a third signal from the first logic circuit, wherein the third signal is based on the first signal and the second signal;
receiving, at a second input of the second logic circuit, a fourth signal from a second one-shot circuit;
receiving, at an input of a minimum pulse-width filter circuit, a fifth signal from the second logic circuit, wherein the fifth signal is based on the third signal and the fourth signal, and wherein an output of the minimum pulse-width filter circuit is communicatively coupled to an output of the minimum pulse-width assurance circuit;
receiving, at an input of the first one-shot circuit and at an input of the second one-shot circuit, a sixth signal from the minimum pulse-width filter circuit, wherein the sixth signal is generated based on a pulse width of the fifth signal;
receiving, at the second input of the first logic circuit, a seventh signal from the first one-shot circuit, wherein the seventh signal is based on a signal transition of the sixth signal; and
receiving, at the second input of the second logic circuit, an eighth signal from the second one-shot circuit, wherein the eighth signal is based on the signal transition of the sixth signal.

US Pat. No. 10,250,243

ASYNCHRONOUS CLOCK SIGNAL GENERATOR AND SEMICONDUCTOR DEVICE FOR CORRECTING MULTI-PHASE SIGNALS USING ASYNCHRONOUS CLOCK SIGNAL

SK HYNIX INC., Icheon (K...

1. A semiconductor device comprising:a first delay circuit configured to adjust delay amounts of multi-phase input signals to output multi-phase signals;
a clock generator circuit configured to output a clock signal that is not synchronized with an input signal, the input signal corresponding to one of the multi-phase signals;
a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals, and to sample the pulse signal according to the clock signal; and
a controller circuit configured to output a delay control signal for controlling the delay amounts of the multi-phase input signals and controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.

US Pat. No. 10,250,242

ARBITRARY DELAY BUFFER

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a delay generator configured to provide both or select between (i) a digital delay combined with an analog delay of an input signal and (ii) the analog delay without the digital delay of the input signal.

US Pat. No. 10,250,241

ASYNCHRONOUS OUTPUT PROTOCOL

Infineon Technologies AG,...

1. An apparatus for outputting a protocol pulse based on a speed signal representing speed of an object, the apparatus comprising:a zero-crossing circuit configured to output the protocol pulse at a zero-crossing or hysteresis crossing of the speed signal; and
a delay circuit coupled to the output of the zero-crossing circuit and configured to delay the protocol pulse,
wherein a first edge of the protocol pulse is asynchronous with a clock, and a second edge of the protocol pulse is synchronous with the clock.

US Pat. No. 10,250,240

INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO CHANGE A CLOCK SIGNAL FREQUENCY WHILE A DATA SIGNAL IS VALID

Rambus Inc., Sunnyvale, ...

1. A method, comprising:receiving, at a memory controller, memory commands in a first sequence order;
determining, by the memory controller, a second sequence order for sending the memory commands to a memory device;
determining, by the memory controller, a frequency of a clock signal for sending the memory commands to the memory device; and
sending, by the memory controller, the memory commands to the memory device in the second sequence order by using the clock signal.

US Pat. No. 10,250,239

MULTI-ZONE LIGHTING SYSTEM AND METHOD INCORPORATING COMPACT RF FEED-THROUGH FILTER FOR MRI SCAN ROOMS

PDC Facilities, Inc., Ha...

1. A multi-zone power supply, comprising:a plurality of current sources, wherein the plurality of current sources is located outside a magnetic resonance imaging (MRI) scan room;
a plurality of light emitting diodes (LEDs) coupled to the plurality of current sources, wherein the plurality of LEDs are located within the MRI scan room;
a radio frequency interference (RFI) filter, wherein the RFI filter is located on an interior wall of the MRI scan room; and
a plurality of cables connecting the plurality of current sources to the plurality of LEDs through the RFI filter.

US Pat. No. 10,250,238

SIGNAL CALCULATOR

SEMICONDUCTOR COMPONENTS ...

1. A time divider comprising:a first switch configured to perform a switching operation according to a first signal and a second switch configured to perform a switching operation according to a second signal, wherein the first signal represents a first time and the second signal represents a second time;
a first capacitor coupled to one end of the first switch and to one end of the second switch; and
a comparison part configured to generate an output based on a period for a charged voltage to reach a second voltage that corresponds to the second time, wherein the charged voltage is increased according to a first current based on a first voltage that corresponds to the first time.

US Pat. No. 10,250,237

ELECTRONIC LATCH CIRCUIT AND A GENERIC MULTI-PHASE SIGNAL GENERATOR

TELEFONAKTIEBOLAGET LM ER...

1. An electronic latch circuit, comprising:an output circuit comprising a first output, a second output, and a third output;
an input circuit comprising a first input, a second input, and a clock signal input;
wherein the electronic latch circuit comprises only five transistors;
wherein the input circuit comprises:
a first Metal Oxide Semiconductor (MOS) transistor with a gate connected to the first input, a source connected to a first voltage potential, and a drain connected to a first node of the output circuit;
a second MOS transistor with a gate connected to the second input, a source connected to the first voltage potential, and a drain connected to a second node of the output circuit; and
a third MOS transistor with a gate connected to the clock signal input, a source connected to a second voltage potential, and a drain connected to a third node of the output circuit;
wherein the output circuit comprises:
a fourth MOS transistor with a drain connected to the first node, a gate connected to the second node, and a source connected to the third node; and
a fifth MOS transistor with a drain connected to the second node, a gate connected to the first node, and a source connected to the third node;
wherein the first output is connected to the first node, the second output is connected to the second node, and the third output is connected to the third node;
wherein the electronic latch circuit is configured to change state based on input signals at the inputs of the input circuit and a present state of the output circuit.

US Pat. No. 10,250,236

ENERGY EFFICIENT, ROBUST DIFFERENTIAL MODE D-FLIP-FLOP

Arizona Board of Regents ...

1. A sequential state element (SSE) comprising:a differential sense amplifier comprising a first amplifier branch having a first output node, a second amplifier branch having a second output node, a first switchable discharge path, and a second switchable discharge path wherein:
the differential sense amplifier is configured to receive a clock signal that oscillates between a first clock state and a second clock state and wherein while the clock signal is in the first clock state, the first amplifier branch is configured to charge the first output node and the second amplifier branch is configured to charge the second output node such that a differential logical output is in a precharge state;
the first amplifier branch and the second amplifier branch are cross coupled such that the first amplifier branch is configured to generate a first logical output of the differential logical output at the first output node and such that the second amplifier branch is configured to generate a second logical output of the differential logical output at the second output node;
the first switchable discharge path is operable to receive the first logical output as feedback from the first amplifier branch; the first switchable discharge path is configured to be opened and closed in accordance with the first logical output wherein the first switchable discharge path is connected to the first amplifier branch so as to discharge the first output node when the first switchable discharge path is closed; and
the second switchable discharge path is operable to receive the second logical output as feedback from the second amplifier branch, the second switchable discharge path is configured to be opened and closed in accordance with the second logical output wherein the second switchable discharge path is connected to the second amplifier branch so as to discharge the second output node when the second switchable discharge path is closed; and
a latch configured to receive the differential logical output and generate a data output in accordance with the differential logical output.

US Pat. No. 10,250,235

FULL-WAVE CHARGE PUMP WITH LOW-VOLTAGE STARTUP

The Regents of The Univer...

1. A charge pump, comprising:a charge pump circuit comprised of transistor pairs arranged in stages, wherein the charge pump circuit is configured to receive an AC input signal and generate a DC output voltage whose magnitude is larger than magnitude of the AC input signal;
an energy storage device configured to receive and store voltage from the charge pump circuit; and
a switching circuit powered by the AC input signal while voltage stored by the energy storage device is below threshold voltage of the transistors in the charge pump circuit and interfaced with control terminals of the transistors in the charge pump circuit and, in response to leakage current through the transistors in the charge pump circuit resulting from the AC input signal to the charge pump circuit, switches on and off the transistors in the charge pump circuit while voltage stored by the energy storage device is below the threshold voltage of the transistors in the charge pump circuit.

US Pat. No. 10,250,234

SIGNAL GENERATION AND WAVEFORM SHAPING

ARM Limited, Cambridge (...

1. Apparatus comprising:a plurality of switched inductor arrangements connected in parallel to generate a combined output signal; and
control circuitry to selectively enable each of the plurality of switched inductor arrangements, an enabled switched inductor arrangement comprising a switched inductor arrangement which is contributing current to the combined output signal,
wherein the control circuitry is configured to vary the number of enabled switched inductor arrangements to define an arbitrarily shaped waveform from the combined output signal,
wherein the arbitrarily shaped waveform is selectable from a plurality of waveform shapes, the plurality of waveform shapes comprising a sine wave and at least one other waveform shape.

US Pat. No. 10,250,233

METHOD FOR COMPENSATING EFFECTS OF SUBSTRATE STRESSES IN SEMICONDUCTOR DEVICES, AND CORRESPONDING DEVICE

STMicroelectronics S.r.l....

1. A semiconductor device including a substrate with a first portion and a second portion, the semiconductor device including:at least one first deformation stress sensor coupled with said first portion of the substrate of the semiconductor device, said at least one first deformation stress sensor providing a first stress signal;
at least one second deformation stress sensor coupled with said second portion of the substrate of the semiconductor device, said at least one second deformation stress sensor providing a second stress signal;
a processing circuit coupled with said at least one first deformation stress sensor and said at least one second deformation stress sensor and configured for:
processing said first stress signal and said second stress signal and producing at least one compensation signal as a function of said first stress signal and said second stress signal;
applying said at least one compensation signal to the first stress signal to compensate for variations induced by stresses in the substrate of the semiconductor device.

US Pat. No. 10,250,232

SYSTEMS AND METHODS FOR CYCLOSTATIONARY FEATURE ELIMINATION

Harris Global Communicati...

1. A method for removing dither introduced into a transmitted radio frequency (RF) signal, comprising:receiving, by a receiver, the transmitted RF signal;
converting, by the receiver, the transmitted RF signal into a discrete-time intermediate frequency (IF) signal comprising a sequence of samples, where at least a first sample of said samples has a first sample duration different than a second sample duration of at least a second sample of said samples; and
performing operations by a sub-sample dither removal device of the receiver to modify a sample timing of the discrete-time IF signal by decreasing or increasing the first sample duration of the first sample using a digital signal processing technique in a digital domain;
wherein the first sample duration of the first sample is increased or decreased by a first amount different than a second amount by which a third sample of said samples duration of a third sample is increased or decreased.

US Pat. No. 10,250,231

ACOUSTIC WAVE DEVICE

TAIYO YUDEN CO., LTD., T...

1. An acoustic wave device comprising:a support substrate;
a first piezoelectric substrate bonded to a first principal surface of the support substrate, the first piezoelectric substrate being a single crystal substrate,
a first acoustic wave resonator located on an opposite surface of the first piezoelectric substrate from a surface to which the support substrate is bonded, the first acoustic wave resonator including an IDT;
a second piezoelectric substrate bonded to a second principal surface of the support substrate opposite from the first principal surface, the second piezoelectric substrate being a single crystal substrate; and
a second acoustic wave resonator located on an opposite surface of the second piezoelectric substrate from a surface to which the support substrate is bonded, the second acoustic wave resonator including an IDT,
wherein the first piezoelectric substrate is a rotated Y-cut X-propagation lithium tantalate substrate or a rotated Y-cut X-propagation lithium niobate substrate,
the second piezoelectric substrate is a rotated Y-cut X-propagation lithium tantalate substrate or a rotated Y-cut X-propagation lithium niobate substrate, and
an X-axis orientation of a crystal orientation of the first piezoelectric substrate and an X-axis orientation of a crystal orientation of the second piezoelectric substrate are oriented in different directions.

US Pat. No. 10,250,230

FILTER AND MULTIPLEXER

TAIYO YUDEN CO., LTD., T...

1. A filter comprising:a piezoelectric substrate;
one or more series resonators that are located on the piezoelectric substrate and are connected in series between an input terminal and an output terminal;
at least one series resonator that is connected between a first node and a second node, and is included in the one or more series resonators, the first node and the second node being located between the input terminal and the output terminal; and
a cancel line that is connected in parallel with the at least one series resonator between the first node and the second node, and cancels a signal outside a passband propagating through the at least one series resonator from the first node to the second node,
wherein:
each of the one or more series resonators includes a pair of comb-shaped electrodes not being grounded and a pair of reflectors sandwiching the pair of comb-shaped electrodes in alignment direction of electrode fingers of the pair of comb-shaped electrodes and are adjacent to the pair of comb-shaped electrodes; and
in each of at least one of the at least one series resonator, one reflector, which is located closer to the cancel line, of the pair of reflectors is grounded and another reflector of the pair of reflectors is not grounded.

US Pat. No. 10,250,229

ELASTIC WAVE APPARATUS

MURATA MANUFACTURING CO.,...

1. An elastic wave apparatus comprising:a mounting substrate; and
an elastic wave filter chip that is mounted on the mounting substrate; wherein
the elastic wave filter chip includes first and second bandpass filters, the first bandpass filter being a ladder bandpass filter including series arm resonators and parallel arm resonators each of which is defined by an elastic wave resonator;
the mounting substrate includes an inductor which is connected between at least one of the parallel arm resonators and a ground potential, a signal wiring which is provided at a different height position from the inductor in the mounting substrate and is connected to the first bandpass filter, and a ground wiring which is provided at an intermediate height position of the mounting substrate between the inductor and the signal wiring; and
when the mounting substrate is viewed from a side of a surface on which the elastic wave filter chip is mounted, at least a portion of the inductor overlaps with the signal wiring and a wiring missing portion in which a portion of the ground wiring is absent from the ground wiring is located in the overlapped portion.

US Pat. No. 10,250,228

BULK ACOUSTIC WAVE RESONATOR WITH A MASS ADJUSTMENT STRUCTURE AND ITS APPLICATION TO BULK ACOUSTIC WAVE FILTER

WIN SEMICONDUCTORS CORP.,...

11. A bulk acoustic wave filter comprising:a plural of bulk acoustic wave resonators formed on a substrate, wherein each of said plural of bulk acoustic wave resonators comprises:
a supporting layer formed on said substrate, wherein said supporting layer has a cavity, said cavity has a top-inner surface;
a lower metal layer formed on a top surface of said supporting layer;
a piezoelectric layer formed on said lower metal layer; and
an upper metal layer formed on said piezoelectric layer, wherein an acoustic wave resonance region is defined by a fully overlapping region of projections of said upper metal layer, said piezoelectric layer, said lower metal layer, said supporting layer and said cavity;
wherein said acoustic wave resonance region is divided into a peripheral region and a central region;
wherein at least two of said plural of bulk acoustic wave resonators have a mass adjustment structure respectively, wherein said mass adjustment structure has one of the following Geometrical Configurations:
Geometrical Configuration I: said mass adjustment structure comprises a peripheral mass adjustment structure, wherein said peripheral mass adjustment structure is formed on said top-inner surface within said peripheral region; and wherein said peripheral mass adjustment structure has a thickness and a width;
Geometrical Configuration II: said mass adjustment structure comprises a central mass adjustment structure and a peripheral mass adjustment structure; wherein said central mass adjustment structure is formed on said top-inner surface within said central region; wherein
said peripheral mass adjustment structure is formed on said top-inner surface within said peripheral region; wherein said central mass adjustment structure has a thickness; wherein
said peripheral mass adjustment structure has a thickness and a width; and wherein said thickness of said peripheral mass adjustment structure is unequal to said thickness of said central mass adjustment structure;
Geometrical Configuration III: said mass adjustment structure comprises a central mass adjustment structure and a first peripheral mass adjustment sub-structure; wherein said central mass adjustment structure is formed on said top-inner surface within said central region; wherein said peripheral region is divided into a first peripheral sub-region and a second peripheral sub-region; wherein said second peripheral sub-region is between said central region and said first peripheral sub-region; wherein said first peripheral mass adjustment sub-structure is formed on said top-inner surface within said first peripheral sub-region;
wherein said first peripheral mass adjustment sub-structure has a thickness and a width; and wherein said central mass adjustment structure has a thickness;
Geometrical Configuration IV: said mass adjustment structure comprises a central mass adjustment structure, a first peripheral mass adjustment sub-structure and a second peripheral mass adjustment sub-structure; wherein said central mass adjustment structure is formed on said top-inner surface within said central region; wherein said peripheral region is divided into a first peripheral sub-region and a second peripheral sub-region; wherein said second peripheral sub-region is between said central region and said first peripheral sub-region;
wherein said first peripheral mass adjustment sub-structure is formed on said top inner surface within said first peripheral sub-region; wherein said second peripheral mass adjustment sub-structure is formed on said top-inner surface within said second peripheral sub-region; wherein said first peripheral mass adjustment sub-structure has a thickness and
a width; wherein said second peripheral mass adjustment sub-structure has a thickness and a width; wherein said central mass adjustment structure has a thickness; wherein said thickness of said second peripheral mass adjustment sub-structure is unequal to said thickness of said first peripheral mass adjustment sub-structure; and wherein said thickness of said second peripheral mass adjustment sub-structure is unequal to said thickness of said central mass adjustment structure;
Geometrical Configuration V: said mass adjustment structure comprises a second peripheral mass adjustment sub-structure; wherein said peripheral region is divided into a first peripheral sub-region and a second peripheral sub-region; wherein said second peripheral sub-region is between said central region and said first peripheral sub-region;
wherein said second peripheral mass adjustment sub-structure is formed on said top-inner surface within said second peripheral sub-region; and wherein said second peripheral mass adjustment sub-structure has a thickness and a width;
Geometrical Configuration VI: said mass adjustment structure comprises a central mass adjustment structure and a second peripheral mass adjustment sub-structure; wherein
said central mass adjustment structure is formed on said top-inner surface within said central region; wherein said peripheral region is divided into a first peripheral sub-region and a second peripheral sub-region; wherein said second peripheral sub-region is between said central region and said first peripheral sub-region; wherein said second peripheral mass adjustment sub-structure is formed on said top-inner surface within said second peripheral sub-region; wherein said second peripheral mass adjustment sub-structure has a thickness and a width; wherein said central mass adjustment structure has a thickness; and wherein said thickness of said second peripheral mass adjustment sub-structure is unequal to said thickness of said central mass adjustment structure; and
Geometrical Configuration VII: said mass adjustment structure comprises a first peripheral mass adjustment sub-structure and a second peripheral mass adjustment substructure;
wherein said peripheral region is divided into a first peripheral sub-region and a second peripheral sub-region; wherein said second peripheral sub-region is between said central region and said first peripheral sub-region; wherein said first peripheral mass adjustment sub-structure is formed on said top-inner surface within said first peripheral sub-region;
wherein said second peripheral mass adjustment sub-structure is formed on said top inner surface within said second peripheral sub-region; wherein said first peripheral mass adjustment sub-structure has a thickness and a width; wherein said second peripheral mass adjustment sub-structure has a thickness and a width; and wherein said thickness of said second peripheral mass adjustment sub-structure is unequal to said thickness of said first peripheral mass adjustment sub-structure; and
wherein at least two of said mass adjustment structures have non-identical Geometrical Configurations.

US Pat. No. 10,250,227

FREQUENCY-VARIABLE FILTER

MURATA MANUFACTURING CO.,...

1. A frequency-variable filter, comprising:a first input-output terminal;
a second input-output terminal;
a filter unit, connected to between the first input-output terminal and the second input-output terminal, including a frequency-variable resonance circuit, the frequency-variable resonance circuit including a piezoelectric resonator and a first variable capacitor connected to the piezoelectric resonator;
a first matching circuit connected between the first input-output terminal and the filter unit, and
a second matching circuit connected between the second input-output terminal and the filter unit,
wherein the first matching circuit comprises a first circuit element and a second circuit element, and
the first circuit element is one of a capacitor and an inductor,
the second circuit element is the other of the capacitor and the inductor,
the first matching circuit and the second matching circuit each have a pattern in which circuit elements are arranged symmetrically with respect to the filter unit, and wherein the first matching circuit and the second matching circuit include a circuit comprising:
the inductor connected between the transmission line and ground, and
the capacitor connected between the transmission line and ground.

US Pat. No. 10,250,226

ELASTIC WAVE DEVICE, HIGH-FREQUENCY FRONT END CIRCUIT, AND COMMUNICATION APPARATUS

MURATA MANUFACTURING CO.,...

1. An elastic wave device comprising:a piezoelectric substrate;
an IDT electrode including a first electrode layer which is provided on the piezoelectric substrate and contains Pt as a main component and a second electrode layer which is laminated on the first electrode layer and contains Cu as a main component; and
a dielectric film that is provided on the piezoelectric substrate and covers the IDT electrode; wherein
the piezoelectric substrate is made of lithium niobate;
the dielectric film is made of silicon oxide;
the elastic wave device uses Rayleigh waves propagating along the piezoelectric substrate; and
when a wavelength defined by an electrode finger pitch of the IDT electrode is ?, and a film thickness of the first electrode layer and a film thickness of the second electrode layer, which are normalized by the wavelength ?, are hPt/?(%) and hCu/?(%), respectively, an equation is satisfied:
hPt/???0.4×hCu/?+0.8.

US Pat. No. 10,250,225

AT-CUT CRYSTAL ELEMENT, CRYSTAL RESONATOR AND CRYSTAL UNIT

NIHON DEMPA KOGYO CO., LT...

1. An AT-cut crystal element, comprisinga crystal element having two side surfaces, which are Z?-surfaces, intersecting with a Z?-axis of a crystallographic axis of a crystal, wherein
at least one of the two side surfaces is constituted of three surfaces, which are a first surface, a second surface and a third surface, and the first surface, the second surface and the third surface meeting following conditions (a) to (e):
(a) the first surface, the second surface and the third surface intersect with one another in this order;
(b) the first surface is a surface equivalent to a surface formed by rotating an X-Z?-surface, as a principal surface of the crystal element, expressed by the crystallographic axis of the crystal of the crystal element by 4°±3.5° about an X-axis of the crystal as a rotation axis;
(c) the second surface is a surface equivalent to a surface formed by rotating the principal surface by ?57.5°±3.5° about the X-axis of the crystal as the rotation axis;
(d) the third surface is a surface equivalent to a surface formed by rotating the principal surface by ?42°±3.5° about the X-axis of the crystal as the rotation axis; and
(e) expressing an angle which is the angle close to 4° of the first surface as ?1, a length of the first surface along a Z?-direction of the crystal as D, a thickness of a part of the crystal element having the principal surface as t, and M=D/t, and a conversion percentage from a thickness twist vibration to a surface-shear vibration of the crystal element as fn (M, (?1)), where, n=1 or 2, the ?1 and the M are set such that the conversion percentage fn (M, (?1)) becomes a predetermined value Th or less.

US Pat. No. 10,250,224

PIEZOELECTRIC VIBRATING PIECE AND PIEZOELECTRIC DEVICE

NIHON DEMPA KOGYO CO., LT...

1. A piezoelectric vibrating piece, comprising:a vibrating piece body, including a vibrator; and
at least a pair of excitation electrodes, being formed on a front surface and a back surface of the vibrator, respectively,
wherein the vibrating piece body is a doubly rotated quartz-crystal vibrating piece cut out parallel to an X?-Z? surface, the X?-Z? surface being rotated around a Z-axis of a crystallographic axis of a crystal and further rotated around an X?-axis; and
the pair of excitation electrodes are collocated in a Z??-axis direction determined by an X??-axis, the X??-axis being defined by counterclockwise rotation from a +X?-axis direction around a Y?-axis by 260° to 300°, the pair of excitation electrodes being disposed inclined with respect to an Y?-axis direction.

US Pat. No. 10,250,223

ACOUSTIC WAVE DEVICE

TAIYO YUDEN CO., LTD., T...

1. An acoustic wave device comprising:a first substrate that includes a support substrate and a piezoelectric substrate bonded on an upper surface of the support substrate, and includes a first acoustic wave element located on an upper surface of the piezoelectric substrate;
a ring-shaped metal layer located in a region that surrounds the first acoustic wave element and in which the piezoelectric substrate is not located;
a second substrate that is flip-chip mounted on an upper surface of the first substrate and includes a functional element located on a lower surface of the second substrate; and
a metallic member that is located on an upper surface of the ring-shaped metal layer, surrounds the second substrate in plan view, is not located between the first substrate and the second substrate, and seals the first acoustic wave element and the functional element so that the first acoustic wave element and the functional element are located across an air gap,
wherein a side surface of the ring-shaped metal layer makes contact with a side surface of the piezoelectric substrate.

US Pat. No. 10,250,222

ELECTRONIC DEVICE

TAIYO YUDEN CO., LTD., T...

11. An electronic device comprising:a first substrate including a first functional element located on an upper surface of the first substrate;
a second substrate that is flip-chip mounted on the upper surface of the first substrate through a bump, and includes a second functional element located on a lower surface of the second substrate; and
a sealing member that is located on the upper surface of the first substrate, surrounds the second substrate in plan view, is not located between the first substrate and the second substrate, seals the first functional element and the second functional element so that the first functional element and the second functional element are located across an air gap;
a terminal located on a lower surface of the first substrate; and
a wiring line connecting the terminal and the first functional element, and located on a side surface of the first substrate, wherein
the first substrate is a lithium tantalate substrate or a lithium niobate substrate, and
the first functional element includes an IDT located on an upper surface of the lithium tantalate substrate or the lithium niobate substrate.

US Pat. No. 10,250,221

ELASTIC WAVE DEVICE

MURATA MANUFACTURING CO.,...

1. An elastic wave device comprising:a piezoelectric substrate including first and second main surfaces which oppose each other and first and second side portions which oppose each other on the first main surface, a direction of a polarization axis of the piezoelectric substrate being inclined with respect to a direction normal to the first main surface;
first and second interdigital transducer electrodes that are disposed on the first main surface of the piezoelectric substrate and that each include first and second busbars which oppose each other, a plurality of first electrode fingers, and a plurality of second electrode fingers, one end of each of the plurality of first electrode fingers being connected to the first busbar, one end of each of the plurality of second electrode fingers being connected to the second busbar; and
a plurality of electrode lands that are disposed on the first main surface of the piezoelectric substrate and that are each electrically connected to a corresponding one of the first and second interdigital transducer electrodes; wherein
the first and second side portions of the piezoelectric substrate extend in a direction perpendicular or substantially perpendicular to the direction of the polarization axis and to the direction normal to the first main surface, and a length of the piezoelectric substrate along the direction of the polarization axis at the first side portion is shorter than a length of the piezoelectric substrate along the direction of the polarization axis at the second side portion;
the first interdigital transducer electrode is located at a position closer to the first side portion than the second interdigital transducer electrode in an extending direction of the plurality of first and second electrode fingers of the first interdigital transducer electrode; and
the plurality of electrode lands include a first electrode land and a second electrode land, the first electrode land being connected to the first busbar of the first interdigital transducer electrode without having the second interdigital transducer electrode interposed therebetween, the second electrode land being different from the first electrode land and being at a same potential as the first busbar of the first interdigital transducer electrode.

US Pat. No. 10,250,220

ELASTIC WAVE DEVICE, ELECTRONIC COMPONENT, AND METHOD FOR MANUFACTURING ELASTIC WAVE DEVICE

MURATA MANUFACTURING CO.,...

1. An elastic wave device comprising:a piezoelectric substrate;
an IDT electrode disposed on the piezoelectric substrate;
a pad disposed on the piezoelectric substrate;
wiring which is disposed on the piezoelectric substrate and which connects the IDT electrode to the pad;
a first dielectric layer disposed on the piezoelectric substrate so as to cover at least a portion of the IDT electrode and not cover the wiring and the pad;
an under bump metal disposed on the pad; and
a second dielectric layer disposed above the piezoelectric substrate so as to cover a portion of the pad, the wiring, and the first dielectric layer and not cover the under bump metal; wherein
at least a portion of the IDT electrode includes a first electrically conductive film;
at least a portion of the wiring includes a multilayer body including the first electrically conductive film and a second electrically conductive film stacked on the first electrically conductive film;
at least a portion of the pad includes the second electrically conductive film;
the second electrically conductive film is covered by the under bump metal and the second dielectric layer; and
the under bump metal is in contact with the second electrically conductive film, and covers a portion of the second dielectric layer.

US Pat. No. 10,250,219

ACOUSTIC WAVE DEVICE

TAIYO YUDEN CO., LTD., T...

1. An acoustic wave device comprising:a first substrate that includes a first acoustic wave filter located on an upper surface of the first substrate;
a second substrate that is flip-chip mounted on the upper surface of the first substrate through a bump, and includes a second acoustic wave filter on a lower surface of the second substrate, the lower surface of the second substrate facing the upper surface of the first substrate across an air gap; and
a shield electrode that is only supported by the upper surface of the first substrate among the upper surface of the first substrate and the lower surface of the second substrate, and is located between at least a part of the first acoustic wave filter and at least a part of the second acoustic wave filter through the air gap.

US Pat. No. 10,250,218

PIEZOELECTRIC THIN FILM RESONATOR AND FILTER

TAIYO YUDEN CO., LTD., T...

1. A piezoelectric thin film resonator comprising:a substrate;
a lower electrode and an upper electrode located on the substrate; and
a piezoelectric film, at least a part of the piezoelectric film being sandwiched between the upper electrode and the lower electrode, the piezoelectric film including a discontinuous portion in which the piezoelectric film discontinues in at least a part of a region surrounding a center region that includes a center of a resonance region where the upper electrode and the lower electrode face each other across the at least a part of the piezoelectric film,
wherein the discontinuous portion is located from a tip of the lower electrode and is not located in a region other than the tip of the lower electrode among the region surrounding the center region,
wherein an air gap is located under the lower electrode, and
wherein the discontinuous portion is located in a region in which an edge portion of the lower electrode substantially coincides with an edge portion of the air gap.

US Pat. No. 10,250,217

METHOD FOR IMPEDANCE MATCHING OF PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A method for impedance matching of a plasma processing apparatus,wherein the plasma processing apparatus comprises:
a chamber main body;
a first electrode and a second electrode which are arranged such that a space within the chamber main body is provided therebetween;
a first high frequency power supply configured to output a first high frequency power for plasma generation, the first high frequency power having a first basic frequency;
a second high frequency power supply configured to output a second high frequency power for ion attraction, the second high frequency power having a second basic frequency lower than the first basic frequency;
a first power feed line configured to electrically connect the first electrode or the second electrode to the first high frequency power supply;
a second power feed line configured to electrically connect the second electrode to the second high frequency power supply;
a first matching device configured to adjust an impedance at a load side of the first high frequency power supply; and
a second matching device configured to adjust an impedance at a load side of the second high frequency power supply,
wherein the first high frequency power supply is configured to selectively output, as the first high frequency power, one of:
a first continuous wave having the first basic frequency;
a first modulated wave generated by modulating a level of a continuous wave having the first basic frequency through a first modulation in which a level of a continuous wave is modulated such that a level in one period between two periods alternately repeated at a modulation frequency is set to be higher than a level in the other period between the two periods; and
a first double-modulated wave generated by modulating a level of a continuous wave having the first basic frequency through a second modulation in which a level of a continuous wave is modulated such that a level in a period during which one period between two periods alternately repeated at a first modulation frequency and one period between two periods alternately repeated at a second modulation frequency lower than the first modulation frequency are overlapped is set to be higher than levels in the other period between the two periods alternately repeated at the first modulation frequency and the other period between the two periods alternately repeated at the second modulation frequency,
wherein the second high frequency power supply is configured to selectively output, as the second high frequency power, one of:
a second continuous wave having the second basic frequency;
a second modulated wave generated by modulating a level of a continuous wave having the second basic frequency through the first modulation; and
a second double-modulated wave generated by modulating a level of a continuous wave having the second basic frequency through the second modulation,
wherein the method comprises:
performing an averaging processing in which a first average value of the impedance at the load side of the first high frequency power supply or a first average value group including an average value of voltages and an average value of currents on the first power feed line is calculated, and a second average value of the impedance at the load side of the second high frequency power supply or a second average value group including an average value of voltages and an average value of currents on the second power feed line is calculated;
calculating a first moving average value and a second moving average value, the first moving average value being a moving average value of the impedance at the load side of the first high frequency power supply and being calculated from a preset number of the first average values or a preset number of the first average value groups obtained by the performing of the averaging processing, and the second moving average value being a moving average value of the impedance at the load side of the second high frequency power supply and being calculated from a preset number of the second average values or a preset number of the second average value groups obtained by the performing of the averaging processing; and
adjusting a variable reactance element of the first matching device and a variable reactance element of the second matching device such that the first moving average value and the second moving average value respectively approximate to matching points,
wherein, in the performing of the averaging processing,
if a lowest modulation frequency used in generation of the first high frequency power and the second high frequency power is used only in the generation of the high frequency power output from one of the first high frequency power supply and the second high frequency power supply,
the first average value and the second average value are obtained by calculating an average value of the impedance at the load side of the one high frequency power supply at multiple time points in the one period between the two periods alternately repeated at the lowest modulation frequency and, also, by calculating an average value of the impedance at the load side of the other high frequency power supply at multiple time points in both of the two periods alternately repeated at the lowest modulation frequency, or
the first average value group and the second average value group are obtained by calculating an average value of the currents and an average value of the voltages on one power feed line used for transmission of the high frequency power from the one high frequency power supply between the first power feed line and the second power feed line at multiple time points in the one period between the two periods alternately repeated at the lowest modulation frequency and, also, by calculating an average value of the currents and an average value of the voltages on the other power feed line at multiple time points in both of the two periods alternately repeated at the lowest modulation frequency, and
if the lowest modulation frequency used in the generation of the first high frequency power and the second high frequency power is commonly used in the generation of both the first high frequency power and the second high frequency power,
the first average value is calculated from the impedance at the load side of the first high frequency power supply at multiple time points in the one period between the two periods within a modulation cycle of the first high frequency power defined by the lowest modulation frequency, and the second average value is calculated from the impedance at the load side of the second high frequency power supply at multiple time points in the one period between the two periods within a modulation cycle of the second high frequency power defined by the lowest modulation frequency, or
the first average value group is calculated from the voltage and the current on the first power feed line at multiple times points in the one period between the two periods within the modulation cycle of the first high frequency power defined by the lowest modulation frequency, and the second average value group is calculated from the voltage and the current on the second power feed line at multiple time points in the one period between the two periods within the modulation cycle of the second high frequency power defined by the lowest modulation frequency.

US Pat. No. 10,250,216

MULTISTAGE MATCHING NETWORK AND RELATED TECHNIQUES

The Regents of the Univer...

1. A multistage matching network comprising:a first stage providing an input stage of the matching network, the first stage comprising a pair of matching network input terminals, a pair of first stage output terminals, and at least two first stage reactive components disposed between the pair of matching network input terminals and the pair of first stage output terminals, the first stage comprising a near-resistive input impedance; and
a second stage providing an output stage of the matching network, the second stage comprising a pair of second stage input terminals coupled to the pair of first stage output terminals, a pair of matching network output terminals, and at least two second stage reactive components disposed between the pair of second stage input terminals and the pair of matching network output terminals, the second stage comprising a complex input impedance and a near-resistive load impedance.

US Pat. No. 10,250,215

ELECTRONIC CIRCUIT AND METHOD FOR MOUNTING ELECTRONIC CIRCUIT

NEC CORPORATION, Tokyo (...

1. An electronic circuit comprising:a capacitor and a three-terminal capacitor that are connected to a power supply terminal of a circuit component and a power supply, and are connected in parallel to each other between the power supply and ground; and
a resistor that is connected in series between the ground and a ground terminal of the three-terminal capacitor and the capacitor.

US Pat. No. 10,250,214

FILTER DEVICE, MULTIPLEXER, RADIO-FREQUENCY FRONT END CIRCUIT, AND COMMUNICATION DEVICE

MURATA MANUFACTURING CO.,...

1. A filter device comprising:a first series arm resonator and a second series arm resonator electrically connected in series between a first terminal and a second terminal, the first series arm resonator being located on a side closer to the first terminal, the second series arm resonator being located on a side closer to the second terminal;
a parallel arm resonator electrically connected between a ground and a series arm between the first series arm resonator and the second series arm resonator;
a first inductor electrically connected in parallel to the first series arm resonator and the second series arm resonator; and
a matching circuit electrically connected between the second series arm resonator and the second terminal or between the first series arm resonator and the first terminal; wherein
the first series arm resonator, the second series arm resonator, and the parallel arm resonator define a pass band of a bandpass filter;
the first series arm resonator, the second series arm resonator, and the first inductor define an LC resonant circuit;
respective anti-resonant frequencies of each of the first series arm resonator and the second series arm resonator and a resonant frequency of the parallel arm resonator are located in a pass band of the LC resonant circuit; and
a resonant frequency of the LC resonant circuit is lower than the resonant frequency of the parallel arm resonator.

US Pat. No. 10,250,213

INTEGRATED CALIBRATION CIRCUIT AND A METHOD FOR CALIBRATION OF A FILTER CIRCUIT

NXP USA, Inx., Austin, T...

1. A calibration circuit for calibrating a RC circuit of an integrated circuit the calibration circuit comprising:a filter arrangement comprising at least one tuneable filter configured to filter an input signal having a predetermined frequency wherein the tuneable filter comprises at least two tuneable resistor elements;
a saturation detector configured to detect saturation and non-saturation of the tuneable filter by comparing a comparison voltage with the signal voltage of the filtered input signal;
a calibration control logic configured to provide an incrementing counter signal and a decrementing counter signal;
wherein the calibration circuit is further configured to:
set the comparison voltage to a first threshold voltage;
provide iteratively an incrementing counter signal to the tuneable filter until saturation is detected;
after saturation is detected, reducing the comparison voltage to a predetermined second threshold voltage which is by a predetermined value lower than the first threshold voltage; and
provide then iteratively a decrementing counter signal to the tuneable filter until non-saturation is detected.

US Pat. No. 10,250,212

RADIO FREQUENCY DEVICE

Infineon Technologies AG,...

1. A radio frequency device, comprising:a radio frequency circuit including a terminal and configured to generate an output signal;
a network coupled to the terminal, the network comprising a series connection of at least two inductors; and
connections between the at least two inductors forming the series connection being exclusive between the at least two inductors,
wherein an equivalent resonance frequency of the series connection is equal to or greater than 1 GHz and is greater than a frequency of the output signal provided at an output of the radio frequency circuit.

US Pat. No. 10,250,211

BETA EQUALIZATION TO REDUCE NON-LINEAR DISTORTIONS OF BIPOLAR TRANSISTOR AMPLIFIERS

TEXAS INSTRUMENTS INCORPO...

1. An output stage circuit of an amplifier comprising:a first set of output transistors configured to couple to a load of the amplifier and produce a portion of an output signal Vout of the output stage circuit;
a second set of output transistors configured to couple the load of the amplifier and produce another portion of the output signal Vout;
an auxiliary buffer circuit directly connected to base nodes of a first subset of the first set of output transistors; and
a bias circuit coupled to base nodes of a second subset of the first set of output transistors, base nodes of the second set of output transistors, and the auxiliary buffer circuit,
wherein the base nodes of second subset and the base nodes of the second set of output transistors are coupled to one or more input terminals that provide an input signal from a previous stage circuit of the output stage circuit.

US Pat. No. 10,250,210

CIRCUIT AND METHOD FOR A HIGH COMMON MODE REJECTION AMPLIFIER BY USING A DIGITALLY CONTROLLED GAIN TRIM CIRCUIT

Dialog Semiconductor (UK)...

1. A differential amplifier with high common mode rejection, comprising:resistors in both paths of said differential amplifier wherein said differential amplifier comprises a pair of said resistors in each of its feedback paths; and
a varistor in a T-network between said both said feedback paths, to provide gain trimming; andwherein said varistor is connected between each pair of said resistors.

US Pat. No. 10,250,209

POWER AMPLIFICATION MODULE

MURATA MANUGACTURING CO.,...

1. A power amplification module that supports a plurality of communication systems, the power amplification module comprising:two power amplifiers, wherein, based on a control signal outputted from a control circuit, the control signal indicating a communication system selected from among the plurality of communication systems, either:
one of the two power amplifiers operates by itself, or
the two power amplifiers operate in parallel with each other; and
a phase correction circuit that, when the two power amplifiers operate in parallel, is connected between outputs of the two power amplifiers and is configured to remove a phase difference between output signals of the two power amplifiers.

US Pat. No. 10,250,208

AMPLIFIER CIRCUIT, CORRESPONDING SYSTEM AND DEVICE

STMicroelectronics S.r.l....

1. A circuit, including:a first input node and a second input node that are configured to differentially receive a sensing signal,
a first output node and a second output node,
a first amplifier stage having a first input coupled to the first input node, an output coupled to the first output node, and a second input,
a second amplifier stage having a first input coupled to the second input node, a second input, and an output coupled to the second output node, the first and second amplifiers being configured to produce a differential output signal between the first output node and the second output node and a common mode signal at both the first and second output nodes,
a voltage divider set between the first output node and the second output node, and having an intermediate tap node, and
a feedback stage coupled to the tap node of the voltage divider, the second input of the first amplifier stage, and the second input of the second amplifier stage, wherein the feedback stage is sensitive to the common mode signal at the output nodes.

US Pat. No. 10,250,207

METHOD AND SYSTEM FOR A FEEDBACK TRANSIMPEDANCE AMPLIFIER WITH SUB-40KHZ LOW-FREQUENCY CUTOFF

Luxtera, Inc., Carlsbad,...

1. A system for processing electrical signals, the system comprising:an amplifier circuit having coupling capacitors, a gain stage, and feedback paths comprising source followers and feedback resistors, wherein:
said feedback paths are coupled to first terminals of said coupling capacitors;
second terminals of said coupling capacitors are coupled to inputs of said gain stage;
said gain stage amplifies electrical signals received via said coupling capacitors; and
gate terminals of said source followers are coupled to output terminals of said gain stage.

US Pat. No. 10,250,206

VOLTAGE DETECTION CIRCUIT

DENSO CORPORATION, Kariy...

1. A voltage detection circuit of a differential configuration for sampling voltages of two input nodes and detecting a differential voltage between sampled voltages, the voltage detection circuit comprising:two detection capacitors paired in a differential configuration;
a first detection switch formed of a P-channel type MOS transistor for opening and closing a path between one of the two detection capacitors and one of the two input nodes;
a second detection switch formed of an N-channel type MOS transistor for opening and closing a path between an other of the two capacitors and an other of the two input nodes;
a third detection switch formed of at least one of a P-channel type MOS transistor and an N-channel type MOS transistor for opening and closing a path between the two detection capacitors;
a driving part for driving the first detection switch and the second detection switch complementarily to the third detection switch such that the first detection switch and the second detection switch are turned on and off when the third detection switch is turned off and on, respectively;
a minimum selector for selecting a lower one of the voltages of the two input nodes and applying a selected voltage as a substrate potential of the N-channel type MOS transistor; and
a maximum selector for selecting a higher one of the voltages of the two input nodes and applying a selected voltage as a substrate potential of the P-channel type MOS transistor.

US Pat. No. 10,250,205

POWER AMPLIFYING DEVICE

HITACHI KOKUSAI ELECTRIC ...

1. An outphasing power amplifying device including a full-bridge class-D power amplifier, comprising:a switching signal generating circuit configured to generate a switching pulse signal for switching the class-D power amplifier from two types of sinusoidal wave generated based on an amplitude and a phase of a modulated wave to be transmitted,
wherein the switching signal generating circuit includes:
a sin calculation unit and a cos calculation unit which are configured to convert phase information of the two types of sinusoidal wave into a quadrature format;
a DA converter configured to convert the quadrature-format phase information from each of the sin calculation unit and the cos calculation unit into an analogue signal;
a first filter configured to remove an aliasing component from the analogue signal inputted from the DA converter;
an analogue quadrature modulator configured to generate a sinusoidal wave from the analogue signals inputted from the first filter by using a local signal;
a second filter configured to allow a predetermined radio frequency and a component in the vicinity thereof in the sinusoidal wave inputted from the analogue quadrature modulator to pass therethrough; and
a comparator configured to convert the sinusoidal wave inputted from the second filter into a switching pulse signal by comparison with a reference voltage.

US Pat. No. 10,250,204

POWER AMPLIFICATION DEVICE AND TELEVISION SIGNAL TRANSMISSION SYSTEM

NEC CORPORATION, Tokyo (...

1. A power amplification device comprising:an amplifying unit provided with a plurality of groups of amplifier circuits that amplifies the power of a radio frequency (RF) signal, the plurality of groups of amplifier circuits each including a predetermined number of the amplifier circuits, the amplifying unit being not provided with a circuit that combines RF signals; and
a combining unit including first combiners that are provided in association with the groups, combine RF signals output from the amplifier circuits belonging to the corresponding group, and output the RF signal after combining, and a second combiner that combines the RF signals output from each first combiner and outputs the RF signal after combining,
wherein each first combiner is a combiner usable for an RF signal in a specific frequency band,
the amplifying unit is housed by a first housing and the combining unit is housed by a second housing which is separate from the first housing, and the amplifying unit is configured to be attachable to and detachable from the combining unit,
each amplifier circuit provided in the amplifying unit is a field effect transistor (FET),
the amplifying unit is configurable by one or more control voltages to perform amplification in classes AB, B and/or C, and
the amplification in classes AB, B, and/or C is compatible with a type of the first combiner, thereby permitting a same amplifying unit to be used with two different types of combining units.