US Pat. No. 10,116,426

METHODS AND SYSTEMS FOR FULL DUPLEX WIRELESS COMMUNICATIONS

The Regents fo the Univer...

1. A method useful for full duplex radio communications, comprising:transmitting a training signal by a node in a radio network;
extracting a waveform from a version of the training signal obtained from a receive chain of the node;
generating a cancellation signal using the waveform;
applying the cancellation signal to the receive chain of the node; and
iteratively:
transmitting the training signal, at increased power compared to prior transmissions of the training signal, by the node in the radio network,
extracting a further waveform from a version of the training signal transmitted at increasing power obtained from the receive chain of the node,
generating a further cancellation signal using the further waveform and the cancellation signal, and
applying the further cancellation signal to the receive chain of the node.

US Pat. No. 10,116,425

DIPLEXED ANTENNA WITH SEMI-INDEPENDENT TILT

CommScope Technologies LL...

1. An antenna configured to operate in at least two radio frequency (RF) bands including a first RF band and a second RF band, the antenna comprising:a first coarse phase shifter and a second coarse phase shifter, wherein the first coarse phase shifter is independently adjustable from the second coarse phase shifter, and wherein the first coarse phase shifter is configured to provide a first contribution on a first tilt associated with the first RF band, and wherein the second coarse phase shifter is configured to provide a second contribution on a second tilt associated with the second RF band;
a first diplexer, a second diplexer, and a third diplexer, wherein each of the first diplexer, the second diplexer, and the third diplexer is coupled to the first coarse phase shifter and to the second coarse phase shifter;
a first fine phase shifter coupled to the first diplexer;
a second fine phase shifter coupled to the second diplexer; and
a third fine phase shifter coupled to the third diplexer,
wherein the first fine phase shifter, the second fine phase shifter, and the third fine phase shifter are coupled to one or more radiating elements.

US Pat. No. 10,116,424

METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING DATA

SAMSUNG ELECTRONICS CO., ...

1. A method of transmitting data, performed by a first transceiver, the method comprising:generating parity data segments comprising restoration information for restoring a first source data;
transmitting data segments of the first source data and at least one first parity data segment among the parity data segments to a second transceiver;
receiving from the second transceiver a first control signal for requesting to prevent transmitting a second parity data segment among the parity data segments, when the first source data is obtained by the second receiver based on the transmitted data segments and the at least one first parity data segment;
preventing the transmission of the second parity data segment according to the received first control signal; and
transmitting data segments of a second source data and at least one second parity data segment comprising restoration information for restoring the second source data.

US Pat. No. 10,116,423

INTER-CARRIER MODULATION

The University Court of t...

1. A method of communicating information in a plurality of carrier waves, the method comprising the steps of:dividing the information into at least a first information portion and a second information portion, wherein the information portions are non-overlapping series of binary bits;
modulating a plurality of domain resources to encode the first information portion using an index or grammar which indicates a modulation type for the plurality of domain resources; and
encoding the second information portion by modulation of domain resources on respective carrier waves belonging to a subset of the plurality of domain resources used to encode the first information portion, and combines the encoded first and second information portions to recreate the information in the plurality of carrier waves,
wherein:
modulation of the plurality of domain resources to encode the first information portion comprises a first information encoding scheme for allocating at least two different modulation types for encoding information to the plurality of domain resources with which the first information portion is to be encoded;
each of the at least two different modulation types and their allocation represents or encodes a different part or subset of the first information portion;
the plurality of domain resources comprise domain resources of two or more domains; and
selecting the first information encoding scheme, for determining the allocation of the at least two different modulation types amongst the plurality of domain resources, by analyzing the first information portion and determining a quantitative value indicative of the available bandwidth for encoding remaining information portions, that maximizes the available bandwidth for the remaining information portions.

US Pat. No. 10,116,422

MANAGING CROSS-CARRIER SCHEDULING IN CARRIER AGGREGATION WITH EPDCCH IN LTE

QUALCOMM Incorporated, S...

28. An apparatus for wireless communication at a user equipment, comprising:a memory; and
at least one processor coupled to the memory and configured to:
receive a control signaling indicating that a carrier indication information is enabled, wherein the control signaling indicating that the carrier indication information is enabled comprises a common control signal for both a first type of control channel and a second type of control channel, the common control signal indicating that the carrier indication information is enabled for both the first type of control channel and the second type of control channel;
receive a first component carrier and a second component carrier, the first component carrier comprising:
a subframe including one of:
a first control channel configured to schedule resources for at least one of the first component carrier or the second component carrier, wherein the first control channel is the first type of control channel, and
a second control channel configured to schedule resources for at least one of the first component carrier or the second component carrier, wherein the second control channel is the second type of control channel, and
the carrier indication information having a value and positioned in a first type of control channel or the second type of control channel, wherein when the value comprises a first value, the carrier indication information identifies that the first type of control channel or the second type of control channel schedules the resources on the first component carrier, and when the value comprises a second value, the carrier indication information identifies that the first type of control channel or the second type of control channel schedules the resources on the second component carrier; and
process the subframe, according to the value of the carrier indication information, based on the first control channel or second control channel.

US Pat. No. 10,116,421

METHOD FOR PERFORMING WIRELESS SWITCHING

InterDigital Technology C...

1. A wireless user terminal comprising:a receiver array configured to receive a plurality of orthogonal frequency division multiplexing (OFDM) signals on at least one downlink carrier frequency, wherein each of the plurality of OFDM signals includes assignment information that includes carrier frequency assignment information indicating a downlink carrier frequency,
the receiver array is further configured to receive a plurality of downlink signals each associated with a respective OFDM signal of the plurality of OFDM signals, wherein each downlink signal is received on the downlink carrier frequency indicated in the respective OFDM signal and using a downlink beam, wherein the downlink carrier frequency and the downlink beam dynamically change over the plurality of downlink signals; and
a controller configured to dynamically change the downlink carrier frequency of the receiver array for receiving the plurality of downlink signals based on the assignment information provided in the plurality of OFDM signals, wherein the plurality of downlink signals have different downlink beams.

US Pat. No. 10,116,420

ERROR RETRANSMISSION MECHANISM-COMPRISED METHODS, APPARATUSES AND SYSTEMS FOR TRANSMITTING AND RECEIVING VISIBLE LIGHT SIGNAL

KUANG-CHI INTELLIGENT PHO...

1. An error retransmission mechanism-comprised method for transmitting a visible light signal, comprising the following steps:during transmission of a visible light signal, when a photonic key executes signal transmission on an error sensitive level each time, reading, by the photonic key, an execution duration of the photonic key;
comparing the execution duration with a signal duration range;
when the execution duration does not fall within the signal duration range, performing, by the photonic key, signal retransmission; and
when the execution duration falls within the signal duration range, continuing, by the photonic key, signal transmission;
wherein the error sensitive level refers to a level having an abnormal duration that causes an identification error at a receive end.

US Pat. No. 10,116,419

METHOD AND APPARATUS FOR DETERMINING FORWARD ERROR CORRECTION FRAME BOUNDARY, AND DECODING SYSTEM

Huawei Technologies Co., ...

1. A method comprising:receiving data, by a frame boundary determining circuit, wherein the data comprises N+P consecutive symbols having a first symbol as a starting point, wherein N is a quantity of symbols in a forward error correction (FEC) frame, N is a positive integer multiple of P, and N is greater than P, wherein a first data block comprises N consecutive symbols having a first starting point of the first symbol, wherein the first data block is in the N+P consecutive symbols, wherein a second data block comprises N consecutive symbols having a second starting point of a second symbol, wherein the second data block is in the N+P consecutive symbols, and wherein an offset of the second symbol relative to the first symbol is P symbols;
obtaining s parameter values corresponding to the first data block;
determining a first iterative item and a second iterative item of the second data block, wherein the first iterative item of the second data block is obtained according to first P consecutive symbols in the first data block, and the second iterative item of the second data block is obtained according to last P consecutive symbols in the second data block;
determining, according to the s parameter values corresponding to the first data block, and the first iterative item and the second iterative item of the second data block, s parameter values corresponding to the second data block;
determining, according to the s parameter values corresponding to the second data block, whether the second symbol is a frame boundary of an FEC frame; and
in response to the determining that the second symbol is a frame boundary of the FEC frame, performing decoding.

US Pat. No. 10,116,418

JOINT FOUNTAIN CODING AND NETWORK CODING FOR LOSS-TOLERANT INFORMATION SPREADING

UNIVERSITY OF FLORIDA RES...

1. A network system for increasing data throughput and decreasing transmission delay from a source node to a sink node via a relay node, the network system comprising:a source node configured to encode a plurality of data packets using rateless coding and transmit the plurality of data packets;
a relay node configured to:
receive at least one of the plurality of data packets from the source node, and
responsive to receiving a sufficient quantity of the plurality of data packets, regenerate, re-encode, and relay the plurality of data packets, wherein the relay node (1) uses intra-session network coding to re-encode a first set of data packets from the sufficient quantity of the plurality of data packets in the same batch of the same session, and (2) uses inter-session network coding to re-encode a second set of data packets from the sufficient quantity of the plurality of data packets destined to different next-hop nodes; and
a sink node configured to:
receive one or more of the plurality of data packets from the relay node, and
responsive to receiving the sufficient quantity of the plurality of data packets, regenerate and decode the plurality of data packets, wherein the sufficient quantity of the plurality of data packets comprises mixed data packets from at least two different flows.

US Pat. No. 10,116,417

NONLINEAR MIMO-OFDM DETECTOR

NXP USA, Inc., Austin, T...

1. A nonlinear multiple input, multiple output orthogonal frequency-division multiplexing (MIMO-OFDM) detector comprising:a vector arithmetic unit configured to sequentially compute first metrics corresponding to a first current tree level of a first search tree and second metrics corresponding to a second current tree level of a second search tree; and
a sorting and indexing unit configured to sort the first metrics and the second metrics sequentially received from the vector arithmetic unit and configured to sequentially provide first indices of lowest first metrics and second indices of lowest second metrics to the vector arithmetic unit, the lowest first metrics being first inputs to the vector arithmetic unit for a first next tree level of the first search tree and the lowest second metrics being second inputs to the vector arithmetic unit for a second next tree level of the second search tree,
wherein the vector arithmetic unit and the sorting and indexing unit are coupled in a pipeline that computes the second metrics concurrently with sorting and indexing of the first metrics, and
wherein the first search tree corresponds to a first subcarrier of an OFDM symbol.

US Pat. No. 10,116,416

APPARATUS FOR TRANSMITTING AND RECEIVING A SIGNAL AND METHOD OF TRANSMITTING AND RECEIVING A SIGNAL

LG ELECTRONICS INC., Seo...

1. A transmitter for transmitting at least one broadcast signal having Physical Layer Pipe (PLP) data, the transmitter comprising:a Bose-Chadhuri-Hocquenghem (BCH) encoder to BCH encode the PLP data;
a Low Density Parity Check (LDPC) encoder to LDPC encode the BCH encoded PLP data and output Forward Error Correction Frames (FECFrames);
a bit interleaver to bit interleave data in the FECFrames;
a mapper to map the bit interleaved data in the FECFrames onto constellations;
an outer encoder to outer encode signaling information;
a zero-padding module to insert zeros into the outer encoded signaling information;
an inner encoder to inner encode the zero-inserted signaling information;
a parity puncturing module to puncture parity bits of the inner encoded signaling information;
a zero-removing module to remove the inserted zeros from the signaling information on which the parity puncturing is performed;
a time-interleaver to perform time-interleaving the mapped data based on a skip operation, wherein the time-interleaver writes the mapped data into an interleaving block and reads out the written data from the interleaving block excluding cells which are skipped according to the skip operation, wherein the time-interleaving is performed by calculating positions for cells having the mapped data and the cells to be skipped based on a row index and a column index;
a frame builder to build a signal frame including preamble symbols and data symbols, wherein the preamble symbols include the zero-removed signaling information for the time interleaved data and the data symbols include the time interleaved data; and
a modulator to modulate data in the signal frame by an Orthogonal Frequency Division Multiplexing (OFDM) scheme, wherein the signaling information includes channel bonding information for the at least one broadcast signal.

US Pat. No. 10,116,415

TRANSMISSION DEVICE, RECEIVING DEVICE, TRANSMISSION METHOD, AND RECEIVING METHOD

CANON KABUSHIKI KAISHA, ...

1. A transmission device, comprising:one or more processors;
a memory having stored thereon instructions which, when executed by the one or more processors, cause the transmission device to:
generate restoration data packets for restoration of lost data packets by using first data packets, which are data packets forming transmission data and which are transmitted as data packets of a first data stream, and second data packets, which are data packets forming the transmission data and which are transmitted as data packets of a second data stream different from the first data stream; and
a transmitter configured to transmit to a receiving device the first data packets as data packets of the first data stream, transmit to the receiving device the second data packets as data packets of the second data stream, and transmit to the receiving device the restoration data packets generated using the first data packets and the second data packet,
wherein the transmission data includes data of a base layer to be used for displaying by the receiving device an image having a first resolution, and data of an enhancement layer to be used together with the data of the base layer for displaying by the receiving device an image having a second resolution that is higher than the first resolution, and
wherein the transmitter is configured to transmit to the receiving device the data of the base layer as the data packets of the first data stream, and transmit to the receiving device the data of the enhancement layer as the data packets of the second data stream.

US Pat. No. 10,116,414

METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING CHANNEL STATUS INFORMATION (CSI) FOR SUPPORTING 256QAM IN WIRELESS ACCESS SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for receiving Channel Status Information (CSI) in a wireless access system, the method performed by an evolved Node B (eNB) and comprising:transmitting a radio resource control (RRC) signal including Channel Quality Indication (CQI) table information configuring a second CQI table to a second CSI subset;
transmitting a first Physical Downlink Shared Channel (PDSCH) on a first CSI subset and a second PDSCH on the second CSI subset; and
receiving first CSI including a first CQI index associated with the first PDSCH and second CSI including a second CQI index associated with the second PDSCH,
wherein the first CQI index is selected from a first CQI table for supporting up to a 64 Quadrature Amplitude Modulation (QAM) scheme, and the second CQI index is selected from the second CQI table for supporting up to a 256 QAM scheme,
wherein CQI indices 12 to 15 of the first CQI table are used for the 64 QAM scheme and CQI indices 12 to 15 of the second CQI table are used for the 256 QAM scheme, and
wherein a total number of CQI indexes of each of the first and the second CQI tables is the same, and a size of the first CQI table and a size of the second CQI table are 4 bits.

US Pat. No. 10,116,413

DETERMINING A HIGH DATA RATE FOR BACKCHANNEL COMMUNICATIONS FOR INITIALIZATION OF HIGH-SPEED NETWORKS

Intel Corporation, Santa...

1. A network controller, comprising:modulation circuitry to determine a first modulated high rate (HR) bit sequence, the first modulated HR bit sequence including a first low rate (LR) bit stream modulated onto a first HR bit sequence and the first LR bit stream including at least first backchannel information;
physical interface (PHY) circuitry including transmitter circuitry to transmit the first modulated HR bit sequence to a link partner over a channel link;
link speed cycling circuitry to, upon initialization of the PHY circuitry, cause the transmitter circuitry to transmit the first modulated HR bit sequence to the link partner over the channel link using at least one high rate link speed; and
equalization presets cycling circuitry to apply at least one equalization preset setting to the transmitter circuitry based in part on the first modulated HR bit sequence while the transmitter circuitry is transmitting the first modulated HR bit sequence to the link partner.

US Pat. No. 10,116,412

APPARATUS AND METHOD FOR RATE CONTROL IN MOBILE COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. An apparatus for a link adaptation (LA) in a wireless communication system, the apparatus comprising:at least one processor configured to:
determine whether to maintain an offset based on whether a previous code rate of a previous frame is one of a minimum value and a maximum value or not, whether the offset used to determine the previous code rate provides an increase in a code rate, and whether the previous frame is received, and
if it is determined that the offset is to be maintained, determine a current channel quality by applying the maintained offset to a previous channel quality for the previous code rate; and
at least one transceiver configured to transmit/receive a current frame according to a current code rate corresponding to the current channel quality.

US Pat. No. 10,116,411

FREQUENCY AGILE ANTI-JAM DATA LINK

Northrop Grumman Systems ...

1. A method for transmitting signals through the atmosphere, said method comprising:sending messages to an intended recipient on a data link at an operating frequency that is close enough to an atmospheric absorption band to cause attenuation of the messages; and
controlling the operating frequency of the data link relative to the absorption band to increase or decrease the attenuation of the messages in the atmosphere in a manner that increases or decreases the signal-to-noise ratio of the messages received by the intended recipient so that the intended recipient of the messages does receive the messages, but unintended recipients of the messages that are farther away from a transmit location of the messages than the intended recipient do not receive the message, wherein controlling the operating frequency of the data link relative to the absorption band includes changing the operating frequency depending on an altitude of the transmit location of the messages, a distance of the intended recipient from the transmit location, and a distance of the unintended recipients from the transmit location.

US Pat. No. 10,116,410

OPTICAL TRANSMITTERS AND RECEIVERS USING POLARIZATION MULTIPLEXING

Telefonaktiebolaget LM Er...

1. An optical transmitter, comprising:a laser having an output;
an optical beam splitter having an input coupled to the output of the laser and two outputs configured so as to produce first and second optical signals;
first and second optical intensity modulators having respective inputs coupled to the outputs of the optical beam splitter and configured to impress multi-level intensity modulation on the first and second optical signals, respectively, based on respective first and second information streams;
a phase modulator coupled in line with the second optical intensity modulator and configured to impress a multi-level phase modulation on the second optical signal, using a multi-level phase modulation signal derived from a third information stream; and
an optical beam combiner having first and second inputs coupled to receive the intensity-modulated first optical signal and the intensity-and-phase-modulated second optical signal, respectively, and configured to combine the intensity-modulated first optical signal and the intensity-and-phase-modulated second optical signal to produce a polarization-multiplexed optical signal for transmission;wherein the optical transmitter is configured so that the intensity-modulated first optical signal and the intensity-and-phase-modulated second optical signal in the polarization-multiplexed optical signal have first and second optical states of polarization, respectively.

US Pat. No. 10,116,409

POLARIZATION DIVERSITY WITH PORTABLE DEVICES VIA WAVEFRONT MUXING TECHNIQUES

SPATIAL DIGITAL SYSTEMS, ...

1. A system comprising:N antennas to receive N input wireless signals that occupy channels configured for at least two different instances of a first polarization, N being an integer greater than 1; and
N wavefront multiplexing (WFM) processors configured to operate on the N received input wireless signals to produce N output signals using a conversion matrix such that the N output signals correspond to a second polarization different from the first polarization,
wherein each of the N processors calculates a corresponding one of the N output signals as a linear combination of the N received input wireless signals using a row in the conversion matrix.

US Pat. No. 10,116,408

APPARATUS AND METHOD FOR DISTRIBUTED COMPENSATION OF NARROW OPTICAL FILTERING EFFECTS IN AN OPTICAL NETWORK

1. A reconfigurable optical add-drop multiplexer comprising:a wavelength selective switch to receive input at a sole input and transmit output; and
an optical equalizer, coupled to the sole input of the wavelength selective switch, to pre-equalize a spectral shape of a signal of each channel of an optical signal input to the sole input of the wavelength selective switch, by adjusting a frequency strength of each channel based on optical filtering effects caused by the wavelength selective switch and a plurality of wavelength routing devices downstream of the optical equalizer and along a transmission link to mitigate the optical filtering effects and reduce noise degradation of the optical equalizer.

US Pat. No. 10,116,407

SYSTEM AND METHOD FOR IMPROVING NARROWBAND INTERFERENCE PERFORMANCE

Texas Instruments Incorpo...

1. A orthogonal frequency division multiplexing (OFDM) receiver, comprising:a processor; and
a non-transitory computer readable storage medium storing a program for execution by the processor, the program including instructions to:
receive a signal over a communication channel;
detect a narrowband interferer in a block of samples of the signal in the communication channel;
align a frequency of the narrowband interferer to a center of a subcarrier frequency of the communication channel, to generate an offset signal, introducing inter-carrier interference (ICI) to the offset signal; and
remove the subcarrier frequency from the offset signal, to generate an interferer erased offset signal.

US Pat. No. 10,116,406

METHOD AND APPARATUS FOR REDUCING INTER-CELL INTERFERENCE

1. A method comprising:identifying, for a cluster of wireless cells comprising a plurality of wireless cells, a first wireless cell that is a most interfered wireless cell of the cluster of wireless cells by comparing a hybrid automatic repeat request (HARQ) success rate to a threshold value;
identifying, for a plurality of radio resources available to the first wireless cell, one or more most interfered radio resources of the plurality of radio resources;
identifying one or more user equipment (UE) associated with the one or more most interfered radio resources for the first wireless cell;
identifying at least one UE associated with the one or more most interfered radio resources for the first wireless cell as a cell edge UE based, at least in part, on at least one of a time adjustment (TA) value and a received signal strength power (RSSP) value associated with the at least one UE;
identifying at least one other UE associated with the one or more most interfered radio resources;
determining whether the at least one other UE is one of:
a cell edge UE served by a second wireless cell of the cluster of wireless cells, wherein the second wireless cell is not identified in a neighbor list of the first wireless cell; or
a cell core UE served by a second wireless cell of the cluster of wireless cells, wherein the second wireless cell is identified in a neighbor list of the first wireless cell but no inter-cell interference coordination is provided for the cell core UE,
wherein the at least one other UE is determined to be a cell edge UE or a cell core UE based, at least in part, on at least one of TA value and a RSSP value associated with the at least one other UE;
including the second wireless cell in the neighbor list of the first wireless cell if the at least one other UE is determined to be a cell edge UE for the second wireless cell that is not identified in the neighbor list of the first wireless cell;
falsely identifying the at least one other UE as a cell edge UE if the at least one other UE is determined to be a cell core UE for the second wireless cell that is identified in the neighbor list of the first wireless cell;
determining if the first wireless cell remains the most interfered wireless cell of the cluster of wireless cells by comparing the hybrid automatic repeat request (HARQ) success rate of the first wireless cell to the predetermined threshold; and
issuing an error message based on the determination that the first wireless cell remains the most interfered wireless cell of the cluster of wireless cells.

US Pat. No. 10,116,405

APPARATUS AND METHOD FOR INTERFERENCE CANCELLATION IN COMMUNICATION SYSTEMS

1. A method, comprising:determining, by a processing system comprising a processor, an interference based on a group of interference signals received at a receiver from a group of transmitters, wherein the determining the interference is based on channel gains that are estimated for the group of transmitters, and wherein a portion of the interference is self-interference generated from transmitting and receiving at a same time; and
determining, by the processing system, whether or not the interference satisfies a threshold range of an analog-to-digital converter of the receiver for each of the group of transmitters,
wherein an analog time domain cancellation is performed responsive to a determination that the interference does not satisfy the threshold range, and
wherein a digital time domain cancellation is performed responsive to a determination that the interference satisfies the threshold range.

US Pat. No. 10,116,403

OTN ADAPTATION FOR SUPPORT OF SUBRATE GRANULARITY AND FLEXIBILITY AND FOR DISTRIBUTION ACROSS MULTIPLE MODEM ENGINES

Ciena Corporation, Hanov...

1. A method for Optical Transport Network (OTN) line side adaptation to provide sub-rate granularity and distribution, the method comprising:subsequent to receiving an OTN signal, segmenting the OTN signal into N flows of cells with associated identifiers, based on tributary slots of the OTN signal, wherein N?0, wherein, when N>0, the cells only include allocated payload from the OTN signal, and wherein, when N=0, the cells only include overhead; and
switching the cells, with a scheduler, to one or more line side modems such that the one or more line side modems only transmit on one or more line side allocated tributary slots when N>0 and overhead only without payload when N=0, wherein a rate of the one or more line side modems is independent from a rate of the OTN signal.

US Pat. No. 10,116,402

SYSTEM AND METHOD FOR OPERATING MODE SELF-ADAPTATION

Huawei Technologies Co., ...

1. A method for controller operations, the method comprising:collecting performance information about a communications system comprising a plurality of communications controllers;
determining a performance indicator from the performance information;
automatically switching an operating mode of the communications system from a first operating mode to a second operating mode in response to determining that the performance indicator meets a performance threshold, wherein the first operating mode comprises a non-inter-cell interference coordination (non-ICIC) mode, and wherein the second operating mode comprises an ICIC mode;
determining a frequency reuse mode for a first subset of communications controllers of the plurality of communications controllers in response to determining that the performance indicator meets the performance threshold;
applying the frequency reuse mode to the first subset of communications controllers; and
removing the frequency reuse mode from the first subset of communications controllers in response to a performance change being less than an expected threshold, the performance change being measured after applying the frequency reuse mode to the first subset of communications controllers.

US Pat. No. 10,116,401

ELECTROMAGNETIC RADIO INTERFERENCE MEASUREMENT DEVICE, ELECTROMAGNETIC RADIO INTERFERENCE MEASUREMENT METHOD, AND ELECTROMAGNETIC RADIO INTERFERENCE MEASUREMENT-PROGRAM RECORDING MEDIUM

NEC CORPORATION, Minato-...

1. An electromagnetic radio interference measurement device that measures an electromagnetic near-field emitted from a measurement object and evaluates electromagnetic interference, the device comprising:mask setting unit that converts a predetermined communication performance value permitted in a desired communication system or a modulation method that is arbitrarily designated into an amplitude probability distribution mask and setting a converted amplitude probability distribution mask as a permissible level;
acquisition unit that acquires time-series measurement data of electromagnetic radio interference emitted from the measurement object in connection with a measurement position coordinate;
amplitude probability distribution calculation unit that calculates amplitude probability distribution of the electromagnetic radio interference for each measurement position coordinate based on the time-series measurement data;
determination unit that determines a magnitude relation between the amplitude probability distribution mask and the amplitude probability distribution for each measurement position coordinate and outputting as a determination result;
mapping process unit that acquires a mapping result in which the determination result is reflected in a space corresponding to the measurement object, and
output unit that outputs the mapping result.

US Pat. No. 10,116,400

OPTICAL SIGNAL FREQUENCY CALIBRATION METHOD AND DEVICE

Huawei Technologies Co., ...

1. An optical signal frequency calibration method, comprising:receiving a first optical signal that experiences a frequency offset and that is generated by a laser in a transmitter of an access node;
receiving a reference optical signal sent by a local oscillator, wherein the reference optical signal is obtained after a receiver of the access node performs, by using a received second optical signal sent by a primary node, frequency calibration on a third optical signal generated by the local oscillator;
calculating a difference between a specified frequency difference and a frequency difference between the reference optical signal and the first optical signal; and
performing frequency calibration on the first optical signal according to the difference, modulating to-be-sent uplink data by using the calibrated first optical signal, and sending the modulated uplink data to the primary node.

US Pat. No. 10,116,399

CIRCUIT ARRANGEMENT FOR RF LOOPBACK

SnapTrack, Inc., San Die...

1. A frontend circuit of a mobile communication device comprising:a transceiver unit comprising a transmitter device, a receiver device and a testing and tuning receiver device, wherein the testing and tuning receiver device is separate from the transmitter device and the receiver device;
a switching device coupled to the transceiver unit, the switching device including a terminal configured to be coupled to an antenna device; and
a control device coupled to the switching device, the control device being configured to operate the frontend circuit in a first mode of operation and in a second mode of operation,
wherein, in the first mode of operation, the switching device is configured by the control device such that a first signal path is routed from the transmitter device of the transceiver unit, through a first switch of the switching device, to a node and from the node back to the testing and tuning receiver device of the transceiver unit in a feedback loop through a second switch of the switching device, wherein the switching device is configured to selectively couple the node to the terminal through a third switch of the switching device, wherein the first switch, the second switch, and the third switch are different switches,
wherein, in the second mode of operation, the switching device is configured by the control device such that a second signal path is routed from the transmitter device of the transceiver unit via the switching device to the terminal or the second signal path is routed from the terminal via the switching device to the transceiver unit, and
wherein the testing and tuning receiver device is configured to receive a radio frequency signal via the first signal path and to measure a strength of the radio frequency signal.

US Pat. No. 10,116,398

SYSTEM FOR TESTING EFFICACY OF ELECTROMAGNETIC SHIELDING AND METHOD

HON HAI PRECISION INDUSTR...

1. A system for testing efficacy of electromagnetic shielding comprising:a radio frequency anechoic housing;
a testing device positioned in the radio frequency anechoic housing, the testing device comprising:
an antennal substrate comprising at least one antenna;
a signal source connecting to one of the at least one antenna to send a frequency field;
a receiving antenna;
a receiver for receiving a first frequency field through the receiving antenna; and
a shielding shell;
wherein when the antennal substrate and the signal source is positioned in the shielding shell and the shielding shell is positioned in the radio frequency anechoic housing, a receiver receives a second frequency field through the receiving antenna, a shielding efficacy value is obtained according to the first frequency field and the second shielding efficacy value, and a determination of whether the shielding shell meets requirement is obtained according to the shielding efficacy value.

US Pat. No. 10,116,397

TEST SEQUENCES USING UNIVERSAL TESTING SYSTEM

Contec, LLC, Schenectady...

1. A testing system for testing a plurality of devices, the testing system comprising:a plurality of test station slots, wherein:
each test station slot of the plurality of test station slots is configured to receive and connect to a corresponding wireless device of a plurality of wireless devices to be tested; and
each test station slot of the plurality of test station slots is configured to use a shared wireless frequency channel for performing one or more wireless tests on each test station slot's corresponding installed wireless device to be tested; and
at least one resource control server, wherein:
the at least one resource control server is configured to lock the shared wireless frequency channel;
a respective test station slot of the plurality of test station slots sends a request to the at least one resource control server for a lock on the respective test station slot's shared wireless frequency channel when the respective test station slot needs to perform a wireless test on the respective test station slot's corresponding installed wireless device to be tested; and
the at least one resource control server is configured to grant the request for the lock on the respective test station slot's shared wireless frequency channel based on a predetermined set of criteria.

US Pat. No. 10,116,396

MILLIMETER-WAVE SOURCELESS RECEIVER

HUAWEI TECHNOLOGIES CANAD...

1. A receiver comprising:a planar antenna array including at least three antennas, each antenna being configured for simultaneously receiving a local oscillator (LO) signal from a near field region and a radio frequency (RF) signal from a far field region;
each antenna being coupled to a respective quasi-optical mixer, each quasi-optical mixer including only passive components and outputting a respective intermediate frequency (IF) signal;
at least two six-port demodulators, each six-port demodulator receiving a respective different pair of IF signals as input and outputting signals representing baseband power of the respective pair of IF signals, each six-port demodulator including only passive components; and
a processor coupled to receive output from the six-port demodulators, the processor being configured to calculate direction of arrival (DoA) for the LO signal and the RF signal using the output from the six-port demodulators.

US Pat. No. 10,116,395

PHOTONIC MICROWAVE MIXING APPARATUS AND METHOD THEREOF

National Chung Cheng Univ...

1. A photonic microwave mixing apparatus, comprising:an optical input, wherein the optical input is an optical signal carrying a frequency-to-be-converted microwave signal;
an optical output, wherein the optical output is an optical signal carrying a frequency-converted microwave signal; and
a photonic microwave mixing module to convert the optical input into the optical output, wherein the photonic microwave mixing module comprises a microwave mixing laser to generate a nonlinear wave-mixing optical signal, and wherein an optical power and a carrier frequency of the optical input are adjusted so as to place the microwave mixing laser in period-one nonlinear dynamics and to achieve frequency unlocking between the modulation sidebands of the optical input and the oscillation sidebands of the period-one nonlinear dynamics.

US Pat. No. 10,116,394

OPTICAL PAIRING

11. A system that receives data encoded as an optical signal, the system comprising:an optical receiver on a first device that receives an optical signal; and
a processor on the first device that decodes a sequence of data symbols from the optical signal and determines that the sequence of data symbols represents a security authentication code that establishes a secure data transfer connection between the first device and a second device;
wherein one of the two devices is an integrated solar panel having a controller;
wherein:
the optical receiver is further configured to receive the optical signal as an optical signal containing a plurality of frequency elements that are each modulated in intensity, with each combination of intensities lasting for a predetermined time duration,
the processor is further configured to:
determine that state transitions in the optical signal between each combination of intensities correspond to permutations of the data symbol sequence as defined by a mapping of data symbols to permutation rules; and
decode the sequence of data symbols by mapping a plurality of modulation state transitions in light output to a corresponding plurality of data symbols;
wherein the processor is further configured to:
update a probabilistic calculation for both new and previously received linear transformations to include the population of newer linear transformations and to exclude linear transformations older than a defined threshold.

US Pat. No. 10,116,393

DRIVER MODULE FOR MACH ZEHNDER MODULATOR

INPHI CORPORATION, Santa...

1. A method of driving a dual-channel modulator in a silicon-photonics communication system, the method comprising:coupling the dual-channel modulator with an electrical data interface;
configuring two differential pairs of inputs per channel respectively to receive two digital differential pair signals from the electrical data interface;
coupling a Digital-to-Analog Convertor (DAC) per channel to the two differential pairs of inputs to convert the two digital differential pair signals to a single analog differential pair PAM signal at a differential pair output with two single ended swing voltages respectively being outputted to two near ends of two waveguides of a traveling wave modulator associated with the channel and terminated at corresponding two far ends with a pair of matched resistors; and
configuring a control block including internal voltage/current signal generators to receive control signals from the DAC for providing a dither signal to assist modulation control per channel.

US Pat. No. 10,116,392

CARRIER SUPPRESSED MULTI-LEVEL PULSE AMPLITUDE MODULATION

FUJITSU LIMITED, Kawasak...

1. A method for carrier suppressed multi-level pulse amplitude modulation, the method comprising:receiving input data for transmission over an optical network;
mapping the input data for M multi-levels of pulse amplitude modulation to generate modulation data, the modulation data including symbols at one of the M multi-levels that represent the input data according to a scaling, wherein the modulation data specify an alternating phase of 0 degrees and 180 degrees respectively for each successive symbol;
applying the modulation data to an optical modulator to pulse amplitude modulate the modulation data onto an optical wavelength to generate an output optical signal for transmission over the optical network.

US Pat. No. 10,116,391

OFF QUADRATURE MACH-ZEHNDER MODULATOR BIASING

INPHI CORPORATION, Santa...

1. A method for operating an off-quadrature modulation system, the method comprising:selecting an input value for performing an optical modulation process by an optical modulator;
providing a lookup table, the lookup table comprising an array of n sine values based on a plurality of n dither frequencies, the lookup table further comprising an array of n cosine values based on the plurality of n dither frequencies;
obtaining n measured values of outputs generated by the optical modulator corresponding to the plurality of n dither frequencies;
determining a first sum using the n measured values;
calculating an array of n in-phase values using the array of n sine values and corresponding n measured values;
calculating an array of n quadrature values using the array of n cosine values and the corresponding n measured values;
determining a second sum using the array of n in-phase values and the array of n quadrature values;
calculating a ratio between the first sum and the second sum; and
adjusting the input value using the ratio as a target of a control loop to stabilize the optical modulator.

US Pat. No. 10,116,390

HYBRID DIRECT-MODULATED/EXTERNAL MODULATION OPTICAL TRANSCEIVER

Maxlinear, Inc., Carlsba...

1. A system for optical communications, comprising:a predistortion module operable to modify an input digital signal to produce a digital predistorted signal;
a transmit optical subsystem operable to generate an optical signal from the digital predistorted signal, wherein the optical signal generated from the digital predistorted signal comprises an amplitude shift according to the modification;
a feedback subsystem operable to determine one or more characteristics of the optical signal, the feedback subsystem being operable to control the modification applied to the input digital signal by the predistortion module according to the one or more characteristics of the optical signal; and
an external modulator operable to modulate the optical signal, the amplitude of a modulated optical signal produced by the external modulator being controlled by the feedback subsystem to counteract the amplitude shift of the optical signal.

US Pat. No. 10,116,389

OPTICAL TRANSCEIVER

Telefonaktiebolaget LM Er...

1. A transceiver, comprising:a receive part configured to receive and detect a first signal carried on an optical carrier, wherein the signal is in a first part of a RF spectrum;
a modulator configured to modulate the same optical carrier with a second signal in a second part of the RF spectrum; and
a transmit part configured to transmit the optical carrier modulated with the second signal, wherein the first part of the RF spectrum is separate to the second part of the RF spectrum,
wherein an inter-symbol interference is introduced in the first signal and the second signal as transmitted to reduce bandwidths occupied by the first signal and the second signal, wherein the inter-symbol interference is recovered at the receive part, and
wherein the first signal and/or the second signal is a spectrally compressed binary signal that comprises a maximum frequency of the higher frequency of the first signal and the second signal which is equal or lower than bit rates of the first signal and the second signal.

US Pat. No. 10,116,388

APPARATUS FOR MEASURING A FILTERING CHARACTERISTIC, PRE-EQUALIZER AND COMMUNICATION EQUIPMENT

FUJITSU LIMITED, Kawasak...

1. An apparatus for measuring a filtering characteristic, including:processor circuitry configured to:
one of determine a first part of a filtering characteristic of a receiving end and determine a first part of a joint response of the filtering characteristic of a transmitting end and the filtering characteristic of the receiving end, in a spectrum of a first receiving signal obtained after a first measurement signal and a second measurement signal pass through respective filtering modules, according to a nonoverlapped spectral part of the first measurement signal and the second measurement signal;
one of determine a second part of the filtering characteristic of the receiving end in a spectrum of a second receiving signal obtained after a third measurement signal and the second measurement signal pass through respective filtering modules, according to a nonoverlapped spectral part of the third measurement signal and the second measurement signal and determine a second part of the joint response of the filtering characteristic of the transmitting end and the filtering characteristic of the receiving end, in the spectrum of the second receiving signal obtained after a fourth measurement signal and the first measurement signal pass through respective filtering modules, according to a nonoverlapped spectral part of the fourth measurement signal and the first measurement signal; and
one of determine the filtering characteristic of the receiving end according to the first part of the filtering characteristic and the second part of the filtering characteristic and determine the joint response of the filtering characteristic of the transmitting end and the filtering characteristic of the receiving end according to the first part of the joint response and the second part of the joint response;
wherein, the filtering modules through which the first measurement signal and the third measurement signal pass include a transmitting end filtering module and a receiving end filtering module, a filtering module through which the second measurement signal and the fourth measurement signal pass include the transmitting end filtering module, spectral ranges of the first measurement signal and the second measurement signal are different, and one of frequencies of the third measurement signal and the first measurement signal are complementary and frequencies of the fourth measurement signal and the second measurement signal are complementary;
and frequency complementarity denotes that spectral ranges of two measurement signals cover all a measurement range of the filtering characteristic, and the two measurement signals have an overlapped frequency point; and the first measurement signal, the second measurement signal, the third measurement signal and the fourth measurement signal are continuous signals.

US Pat. No. 10,116,387

CONTROL DEVICE, OPTICAL TRANSMISSION SYSTEM, AND METHOD FOR CONTROLLING OPTICAL TRANSMISSION SYSTEM

FUJITSU LIMITED, Kawasak...

1. A control device for controlling a first transmission device and a second transmission device, the control device comprising:a memory; and
a processor coupled to the memory, the processor configured to:
set a first wavelength path between the first transmission device and the second transmission device;
select a monitoring wavelength path for a monitoring wavelength from established wavelength paths allocated on a transmission line between the first transmission device and the second transmission device; and
subtract a consideration value from a lower limit value of a signal quality of the monitoring wavelength path such that an allowable lower limit value of the signal quality of the monitoring wavelength path is calculated, thereby monitoring the signal quality of the monitoring wavelength path, the consideration value being obtained by multiplying a number of spans within the monitoring wavelength path to a noise increase amount of the monitoring wavelength caused by the first wavelength path; and
increase power of the first wavelength path, based on the signal quality of the monitoring wavelength path.

US Pat. No. 10,116,386

METHODS FOR DETERMINING RECEIVER COUPLING EFFICIENCY, LINK MARGIN, AND LINK TOPOLOGY IN ACTIVE OPTICAL CABLES

SAMTEC, INC., New Albany...

1. A method of determining link topology of a communication system including channels connecting corresponding transmitters and receivers, each of the channels including a light source, a photodetector optically connected to the light source, and a transimpedance amplifier connected to an output of the photodetector, wherein the transimpedance amplifier squelches its output when optical power detected by the photodetector is below a threshold optical power, the method comprising:selecting a pattern of optical powers of the light sources in a test transmitter to be either above the threshold optical power or below the threshold optical power; and
determining which receiver is connected to the test transmitter by matching a pattern of squelched and non-squelched transimpedance amplifier outputs in the receiver with the pattern of optical powers of the light sources in the test transmitter.

US Pat. No. 10,116,385

SYSTEM AND METHOD FOR PILOT DATA DETECTION USING CORRELATION PEAK TRACKING

Huawei Technologies Co., ...

1. A method for detecting pilot data comprising:receiving an optical signal from an optical channel, the optical signal comprising a pilot signal, the pilot signal carrying the pilot data;
detecting, by an optical-to-electrical converter, the pilot signal in the optical signal; and
performing operations on the pilot signal including:
(i) for a bit of the pilot data: performing correlation operations on the pilot signal over a first set of frequency values and at a plurality of phases to produce a first set of correlation values, and obtaining from the first set of correlation values an initial maximum correlation peak for use in pilot data detection; and
(ii) for each bit of subsequent bits of the pilot data: performing correlation operations on the pilot signal over a second set of frequency values and at a plurality of phases to produce a second set of correlation values, and obtaining a subsequent maximum correlation peak from the second set of correlation values for use in the pilot data detection, wherein the subsequent maximum correlation peak is selected from correlation values, in the second set of correlation values, that were produced for phases within a window around and encompassing a phase of the initial maximum correlation peak.

US Pat. No. 10,116,384

REMOTE PROGRAMMING AND TROUBLESHOOTING OF PLUGGABLE OPTICAL TRANSCEIVERS

Integra Optics, Inc., La...

1. A method for remotely programming an optical pluggable module (OPM), the method performed by a computing device remote from the OPM, the method comprising:connecting to a network-enabled programmer, wherein the network-enabled programmer has an OPM coupled to the network-enabled programmer;
retrieving an OPM configuration from the OPM that is coupled to the network-enabled programmer;
performing a remote diagnostics process on the OPM;
downloading a configuration from the remote computing device to the network-enabled programmer; and
programming, via the network-enabled programmer, the configuration into the coupled OPM, wherein the programming the configuration includes selecting an OPM platform or selecting an optical channel.

US Pat. No. 10,116,383

OUTPHASING AMPLIFIER

NXP B.V., Eindhoven (NL)...

1. An outphasing amplifier having:a first branch arranged to receive and process a first branch signal, the first branch signal being phase modulated, with constant amplitude envelope; and
a second branch arranged to receive and process a second branch signal, the second branch signal being phase modulated, with constant amplitude envelope, and at least a portion of the second branch signal anti-phase from the first branch signal,
wherein each branch includes:
circuitry arranged to successively process the respective branch signal to reduce the energy in sidebands of the respective branch signal away from the central frequency to generate a filtered magnitude signal, while retaining the phase information in the respective branch signal from an unfiltered signal until a threshold is met;
the circuitry arranged to generate a filtered and re-asserted branch signal from the filtered magnitude signal and the phase information; and
an amplifier arranged to amplify the filtered and re-asserted branch signal.

US Pat. No. 10,116,382

AD HOC HIGH FREQUENCY NETWORK

Rockwell Collins, Inc., ...

1. A communication device, comprising:a time source configured to provide timing information for the communication device, the timing information being synchronized with other communication devices participating in a same network the communication device is configured to participate in; and
one or more processors in communication with the time source, the one or more processors configured to facilitate beyond line of sight reflective communications between the communication device and another communication device participating in the same network, wherein the beyond line of sight reflective communications are carried out in a time synchronized manner and in accordance with a time division multiple access (TDMA) based waveform that supports time slots, wherein the one or more processors are further configured to periodically broadcast a location update message on all frequencies specified in a frequency pick list, the location update message includes information regarding the communication device and information regarding direct connection neighbors of the communication device.

US Pat. No. 10,116,381

SYSTEMS AND METHODS FOR FIXED SATELLITE SERVICE PROTECTION USING REAL-TIME MEASUREMENT

Cable Television Laborato...

1. A system for protecting a fixed satellite service site, comprising:at least one earth station;
a first beacon detector disposed within close proximity to the at least one earth station;
a central server in operable communication with the fixed satellite service site and the first beacon detector;
an access point configured to request authorization from the central server for resource allocation; and
a beacon transmitter disposed within close proximity to the access point, and configured to transmit a beacon signal to one or more of the central server and the first beacon detector, wherein the beacon signal uniquely identifies the access point.

US Pat. No. 10,116,380

SATELLITE PROCESSOR OPERATING SYSTEM

Kythera Software, Inc., ...

1. A computer-implemented method performed by a satellite communications system, the method comprising:receiving, by a system manager at a virtual hub server and from an application module that includes software algorithms that implement a software function, a request to register the software function of the application module with the system manager, wherein registering the software function of the application module with the system manager enables software algorithms in the application module to be later called upon to generate a beam plan and wherein the request describes one or more inputs to the software function, one or more outputs of the software function that are used to generate a beam plan for a satellite, and one or more capabilities that the satellite must have for the software function to be used;
in response to receiving the request to register the software function of the application with the system manager, determining, by the system manager at the virtual hub server, one or more capabilities of the satellite;
determining, by the system manager at the virtual hub server, whether the determined one or more capabilities of the satellite satisfy the described one or more capabilities that the satellite must have for the software function that the software algorithms of the application module implement to be used with the satellite;
in response to determining that the determined one or more capabilities of the satellite satisfy the described one or more capabilities that the satellite must have for the software function that the software algorithms of the application module implement to be used with the satellite, (i) providing, by the system manager at the virtual hub server, to a client an indication that the software function of the application is available to be used with the satellite and a description of the one or more inputs to the software function and (ii) registering, by the system manager at the virtual hub server, the software function of the application module as available for use with the satellite where the registration of the software function enables the software algorithms included in the application module to be later called upon by the client to generate the beam plan;
receiving, by the system manager at the virtual hub server, a request from the client to generate the beam plan for the satellite that where the request both (i) indicates that the software function that was indicated to the client as available to be used with the satellite is to be used in the generation of the beam plan and (ii) indicates values for the one or more inputs to the software function;
in response to receiving the request from the client to generate the beam plan for the satellite using the software function that was indicated to the client as available to be used with the satellite, determining by the system manager at the virtual hub server, that the software function of the application module is registered as available for use with the satellite;
in response to determining that the software function of the application module is registered as available for use with the satellite, obtaining, by the system manager at the virtual hub server, the beam plan for the satellite using the one or more outputs of the software function in response to providing to the software function the values for the one or more inputs to the software function indicated in the request from the client to generate the beam plan; and
transmitting, by the system manager at the virtual hub server, the beam plan to the satellite.

US Pat. No. 10,116,379

SCHEDULING BEAMS OF A SATELITE ANTENNA

Aireon LLC, McLean, VA (...

1. A computer-implemented method for scheduling beams of an antenna on board a satellite for receiving Automatic Dependent Surveillance Broadcast (ADS-B messages) during a defined time period comprising:for each beam of the antenna, calculating a beam score based, at least in part, on the expected gain of the beam during the defined time period;
determining a number of beams of the antenna having non-zero beam scores during the defined time period;
comparing the number of beams of the antenna having non-zero beam scores during the defined time period to a threshold value;
determining, based on having compared the number of beams of the antenna having non-zero beam scores during the defined time period to the threshold value, that the number of beams of the antenna having non-zero beam scores during the defined time period is less than the threshold value;
as a consequence of having determined that the number of beams of the antenna having non-zero beam scores during the defined time period is less than the threshold value:
accessing a set of beam weights for each of multiple different candidate beam patterns, each set of beam weights having a weight corresponding to each of the antenna's beams;
for each set of weights:
multiplying individual beam weights by corresponding beam scores for beams of the antenna during the defined time period, and
generating a candidate beam pattern score by calculating a sum of the products of the beam weights and corresponding beam scores;
comparing the candidate beam pattern scores for the different candidate beam patterns;
selecting, based on having compared the candidate beam pattern scores for the different candidate beam patterns, a particular one of the candidate beam patterns; and
scheduling the selected beam pattern for the beams of the antenna for the defined time period.

US Pat. No. 10,116,378

SYSTEMS AND METHOD OF AUTOMATICALLY GENERATED RADIO CALLS

HONEYWELL INTERNATIONAL I...

1. A method in an aircraft computing system for facilitating communication between a flight crew and an external communication facility (ECF), the method comprising:mining aircraft data by an aircraft computing system for indicators for a plurality of pre-defined, non-emergency conditions from an aircraft interface to flight desk equipment;
detecting from the mined aircraft data, by the aircraft computing system, a predefined, non-emergency condition requiring communication from the flight crew to the ECF;
automatically generating and displaying a computer-generated message on an aircraft cockpit display responsive to detecting the condition;
providing a selection option for transmitting the message to the ECF; and
transmitting the message to the ECF in accordance with the option selected.

US Pat. No. 10,116,377

DYNAMIC FORWARD ERROR CORRECTION BYPASS IN A DIGITAL COMMUNICATIONS SYSTEM

Google LLC, Mountain Vie...

1. A method of improving communications, comprising:receiving a first packet at a gateway communicatively coupled to an end terminal through an unmanned air vehicle (UAV), wherein a first wireless link communicatively couples the gateway to the UAV, and a second wireless link communicatively couples the UAV to the end terminal;
determining, with one or more processors, a signal quality on at least the first link between the gateway and the UAV in a first direction;
when the signal quality exceeds a first predetermined threshold:
encoding, at the gateway, the first received packet for processing by the end terminal;
tagging the first received packet with an indicator to bypass forward error correction (FEC) at the UAV;
monitoring, with the one or more processors at the gateway, the signal quality on at least the first link;
comparing the monitored signal quality to a second threshold lower than the first threshold; and
when the monitored signal quality falls below the second threshold lower, encoding, at the gateway, the first received packets for processing by the UAV.

US Pat. No. 10,116,376

METHOD AND SYSTEM FOR RELAYING TELECOMMUNICATIONS SIGNALS

KATHREIN-WERKE KG, Rosen...

1. A system for relaying telecommunication signals, comprising:a central hub connectable to one or more base stations;
a plurality of remote units for relaying the telecommunication signals; and
a plurality of expansion units digitally connected to the central hub and connect-able to the plurality of remote units,
wherein at least one of the plurality of expansion units is provided with a plurality of coverage area modules, wherein one or more of the plurality of remote units is connected to a selected one of the plurality of coverage area modules, the selected one of the coverage area modules being adapted to relay same signals to the connected one or more of the plurality of remote units,
wherein a connection between the plurality of expansion hubs and the plurality of remote units is reconfigurable, and so that at least one of the remote units may be connected from a first selected one of the coverage area modules, to a second selected one of the coverage area modules.

US Pat. No. 10,116,375

LINK ACQUISITION IN WIRELESS COMMUNICATION SYSTEMS

Facebook, Inc., Menlo Pa...

1. A node for use in a wireless communication network, wherein the node comprises:a transceiver that transmits and receives packet data on a wireless communication frequency;
a plurality of antennas with which radio frequency signals are transmitted and received at the node;
a beamformer with which a transmit and receive direction can be changed by the node; and
a processor that is configured to execute instructions to identify one or more transmit and receive beamforming direction pairs between the node and a responder node in a point-to-point wireless communication network, wherein each transmit and receive beamforming direction pair includes a transmit beamforming direction of the node and a receive beamforming direction of the responder node, and wherein the receive beamforming direction is set by delaying and summing receive signals to direct a listening direction of the responder node by:
asynchronously transmitting training packets for a number of times in each of a number of transmit beamforming directions;
receiving an indication that the responder node has asynchronously detected a training packet and is synchronized to the node; and
once the node and the responder node are synchronized,
synchronously transmitting training packets from the node for a number of times in each of a number of possible transmit beamforming directions;
listening for feedback from the responder node that indicates that a training packet was received on a particular receive beamforming direction and listening direction of the responder node; and
using a transmit and receive beamforming direction pair with which a training packet was received by the responder node to transmit data packets to the responder node.

US Pat. No. 10,116,374

RECEIVER WITH NON-COHERENT MATCHED FILTER

Aieron LLC, McLean, VA (...

1. A receiver for receiving 1090 MHz Mode S Extended Squitter (“ES”) ADS-B messages comprising:an analog-to-digital converter configured to convert a received analog signal into a digital representation of the received signal;
a carrier detection module configured to determine if a spectral component within a range of 1090 MHz is present within a portion of the digital representation of the received signal;
a cross-correlation module configured to:
calculate, responsive to a determination by the carrier detection module that a spectral component within the range of 1090 MHz is present within the portion of the digital representation of the received signal, a measure of the cross-correlation between the portion of the digital representation of the received signal and a reference signal representing an expected pulse pattern for a specific portion of a 1090 MHz Mode S ES ADS-B message, the calculated measure of the cross-correlation representing a first measure of the likelihood that the digital representation of the received signal includes a 1090 MHz Mode S ES ADS-B message, and
determine if the first measure of the likelihood that the digital representation of the received signal includes a 1090 MHz Mode S ES ADS-B message satisfies a first condition;
a signal estimator module configured to generate, responsive to a determination that the first measure satisfies the first condition, an estimate of a portion of a 1090 MHz Mode S ES ADS-B message potentially included in the digital representation of the received signal corresponding to the portion of the digital representation of the received signal;
a screening module configured to:
generate a feature vector representing n?2 features of the estimate of the portion of the 1090 MHz Mode S ES ADS-B potentially included in the digital representation of the received signal,
project the feature vector into a corresponding n-dimensional feature space,
determine, based on the projection of the feature vector into the feature space, a second measure of the likelihood that the digital representation of the received signal includes a 1090 MHz Mode S ES ADS-B message, and
determine if the second measure of the likelihood that the digital representation of the received signal includes a 1090 MHz Mode S ES ADS-B message satisfies a second condition; and
a non-coherent matched filter configured to recover, responsive to a determination that the second measure satisfies the second condition, a 1090 MHz Mode S ES ADS-B message from the digital representation of the received signal.

US Pat. No. 10,116,373

DYNAMICALLY ADJUSTING VERTICAL BEAMFORMING WEIGHTS

Sprint Communications Com...

14. A dynamic vertical beamforming system for dynamically adjusting vertical beamforming weights to influence a width of a beam emitted from an antenna, the dynamic vertical beamforming system comprising:a processor; and
one or more computer storage hardware devices storing computer-usable instructions that, when used by the processor, cause the processor to:
determine that a quantity of user devices having a line of sight to the antenna is above a threshold of user devices, at least a portion of the user devices being vertically separated from others of the user devices;
determine, based on quality information sent from the user devices, current radio frequency (RF) conditions between the antenna and the user devices;
if the current RF conditions are below a minimum threshold, adjusting phase and amplitude components of the vertical beamforming weight; and
if the current RF conditions are above the minimum threshold and below a maximum threshold, adjusting the phase component of the vertical beamforming weight and not adjusting the amplitude component of the vertical beamforming weight.

US Pat. No. 10,116,372

INTERLEAVED TRAINING AND LIMITED FEEDBACK FOR MULTIPLE-ANTENNA SYSTEMS

The Regents of the Univer...

1. A method for improving wireless communication in a system having multiple transmitting antennas comprising:training one of a multiplicity of transmitting antennas of a transmitter;
feeding back channel state information (CSI) from a receiver to the one of the multiplicity of transmitting antennas;
improving the ability of the transmitter to transmit data to the receiver using the feedback CSI from the receiver; and
repeating training, feeding back CSI, and improving the ability of the transmitter to transmit data according to feedback CSI on another one of the multiplicity of transmitting antennas in a one-by-one interleaved fashion.

US Pat. No. 10,116,371

METHOD FOR REPORTING CHANNEL STATE INFORMATION IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR

LG Electronics Inc., Seo...

1. A method of reporting channel state information (CSI) by a user equipment (UE) in a wireless communication system, the method comprising:receiving, from a base station, a radio resource control (RRC) message containing one CSI-reference signal (CSI-RS) configuration including a pattern of antenna port virtualization which is changed in accordance with a predetermined period;
receiving, via different subframes respectively, a first CSI-RS from a first subset and a second CSI-RS from a second subset among a plurality of physical antenna elements of the base station based on the one CSI-RS configuration;
obtaining a total channel matrix by matching a first partial channel corresponding to the first subset and a second partial channel corresponding to the second subset using a phase value for a specific antenna element which is commonly included in both the first subset and the second subset;
obtaining a right singular matrix by performing singular value decomposition on the total channel matrix;
performing quantization on the right singular matrix, and
transmitting a CSI report including the quantized right singular matrix for the total channel matrix.

US Pat. No. 10,116,370

RADIO COMMUNICATION CONTROL METHOD AND RADIO COMMUNICATION SYSTEM

NTT DOCOMO, INC., Tokyo ...

1. A radio communication control method in a radio communication system, comprisinga transmitter device provided with
a precoder configured to carry out precoding by using a precoding matrix,
a transmit beamformer configured to carry out transmit beamforming, in which variation in phase and amplitude corresponding to a transmit beamforming (BF) weight matrix is imparted to signals after precoding has been executed, and
a number NT of transmission antennas for transmitting the signals subjected to the transmit beamforming, and
a receiver device provided with
a number NR of reception antennas for receiving signals that have been transmitted from the transmitter device and propagated through a space,
a receive beamformer configured to carry out receive beamforming, in which variation in phase and amplitude corresponding to a receive BF weight matrix is imparted to the signals received by the plurality of reception antennas, and
a postcoder configured to carry out, by using a postcoding matrix, postcoding on the signals that have been subjected to the analog receive beamforming,
the method comprising:
generating a receive BF output vector having a number NR of receive BF output components, by a number LR of receive beamforming circuits provided in the receive beamformer carrying out receive beamforming (NR/LR) times with respect to a received signal vector received by the number NR of the reception antennas;
calculating reception power for each of the NR receive BF output components; and
selecting the LR receive BF output components in decreasing order of reception power, and determining a suitable receive BF weight matrix including LR reception orthogonal BF weight vectors corresponding to the selected receive BF output components.

US Pat. No. 10,116,369

COMMUNICATION DEVICE AND METHOD PROVIDING BEAMFORMING FOR TWO OR MORE TRANSMISSION CHANNELS

SONY CORPORATION, Tokyo ...

1. A communication device comprising:circuitry configured to
obtain multicast precoding information from at least first beamforming information for a first transmission channel and second beamforming information for a second transmission channel, the first beamforming information and the second beamforming information being obtained from a first receiver and a second receiver, respectively, the first transmission channel being between the communication device and the first receiver, and the second transmission channel being between the communication device and the second receiver;
beamform at least one signal using the multicast precoding information to obtain at least two precoded signals; and
multicast transmission signals derived from the at least two precoded signals through the at least first and second transmission channels,
wherein the circuitry is configured to perform spot beamforming on the transmission signals, and
each of the at least first and second beamforming information contains a minimum information for a specific precoder matrix for a unicast transmission through the respective transmission channel and a corresponding SNR (signal-to-noise ratio) information.

US Pat. No. 10,116,368

COMMUNICATION UNIT, INTEGRATED CIRCUIT AND METHOD FOR GENERATING A PLURALITY OF SECTORED BEAMS

Analog Devices Global, H...

1. A communication unit for generating a plurality of sectored beams, the communication unit comprising:a plurality of antenna element feeds arranged to couple to a plurality of antenna elements of an antenna array, wherein an individual antenna element feed of the plurality of antenna element feeds is configured to provide a transmit signal associated with two sectors;
a plurality of transmitters operably coupled to the plurality of antenna element feeds; wherein a transmitter of the plurality of transmitters is configured to receive a first signal associated with a first sector and a second signal associated with a second sector, the two sectors comprising the first sector and the second sector, and the transmitter comprises:
beamformer logic arranged to apply independent beamform weights on the first signal and the second signal of the transmitter to generate a weighted first signal and a weighted second signal, respectively, wherein each of the independent beamform weights is allocated on a per sector basis; and
a signal combiner arranged to combine the weighted first signal and the weighted second signal to produce a combined signal such that the combined signal supports sectored beams for the two sectors, wherein an output of the signal combiner is operably coupled to the individual antenna element feed, and
wherein the beamformer logic is configured to apply a calibration correction coefficient so as to calibrate an amplitude and a phase of the combined signal.

US Pat. No. 10,116,367

METHOD AND SYSTEM FOR MULTIPLE-HOP RELAYED DIRECTIONAL WIRELESS COMMUNICATION

SONY CORPORATION, Tokyo ...

1. An apparatus for wireless communication between stations (STAs) using directional transmission/reception, comprising:(a) a wireless communication station (STA) configured for mm-wave communication, in which said STA, and nearby STA instances of the apparatus are configured for performing sector sweep and feedback signaling to exchange antenna sector information;
(b) a transmitter of said wireless communication station (STA) configured for generating directional radio transmissions to other wireless radio communication devices which are in range;
(c) a receiver of said wireless communication station (STA) configured for receiving radio transmissions from other wireless radio communication devices;
(d) a computer processor coupled to said transmitter and said receiver for controlling communications between itself and other wireless radio communication devices;
(e) a non-transitory computer-readable memory storing instructions executable by the computer processor;
(f) wherein said instructions, when executed by the computer processor, perform steps comprising:
(i) exchanging quantized channel gain, or path loss, information of each antenna sector with one or more neighboring stations;
(ii) recording received quantized channel gain information from communication with neighboring stations;
(iii) generating route discovery messages to neighboring stations when establishing a multiple hop routing path from an originating station to a destination station; and
(iv) processing received route discovery messages by (A) determining link metrics with a neighboring station that generated the route discovery message, (B) considering interference impact when determining transmit antenna sector to a neighboring station as a potential next hop in the routing path; (C) propagating the route discovery message to a neighbor station if the station is not the destination station;
(v) wherein channel time utilization and impact to ongoing traffic at neighboring stations are utilized in determining interference impact when establishing the multiple hop routing path.

US Pat. No. 10,116,366

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

LG ELECTRONICS INC., Seo...


updating a kth parity bit by summing with a (k?1)th parity bit in the parity bits.

US Pat. No. 10,116,365

WIRELESS COMMUNICATION DEVICE AND WIRELESS COMMUNICATION METHOD

SONY CORPORATION, Tokyo ...

1. A wireless communication apparatus which participates in wireless communication involving an antenna array, comprising:processing circuitry configured to
receive, from a target communication apparatus for the wireless communication apparatus, a signal including antenna array geometry information of the target communication apparatus and receive a training sequence signal;
determine geometry configuration of the antenna array of the target communication apparatus based on the signal;
estimate channel characteristic of a channel from the target communication apparatus to the wireless communication apparatus based on the training sequence signal; and
determine, based on the geometry configuration of the antenna array of the target communication apparatus and channel estimation result, channel feedback information indicating the channel characteristic of the channel from the target communication apparatus to the wireless communication apparatus,
wherein the antenna array geometry information indicates at least one of positional relationship among antenna elements in the antenna array, spacing between the antenna elements, and antenna polarization direction.

US Pat. No. 10,116,364

METHOD FOR DETERMINING RANK INDICATION RI BIT NUMBER, BASE STATION, AND TERMINAL

Huawei Technologies Co., ...

1. A method, comprising:obtaining, by an apparatus, configuration information from a base station; and
selecting, by the apparatus, a current maximum number of multi-input multi-output (MIMO) layers according to band combination and the obtained configuration information, wherein the current maximum number of the MIMO layers is a maximum value of the supported MIMO layers for one frequency band that appears at least two times in the band combination;
wherein the band combination is a combination of frequency bands which indicates MIMO capabilities of the apparatus, and each of the MIMO capabilities represents a maximum number of supported MIMO layers of the apparatus in each of the frequency bands of the band combination.

US Pat. No. 10,116,363

METHOD AND APPARATUS FOR DETERMINING PRECODING MATRIX INDICATOR, USER EQUIPMENT, AND BASE STATION

HUAWEI TECHNOLOGIES CO., ...

1. A method for determining a precoding matrix indicator (PMI), comprising:receiving, by a user equipment, a reference signal sent by a base station; and
determining, by the user equipment, the PMI according to the reference signal, wherein the PMI corresponds to a precoding matrix W, and the precoding matrix W satisfies a second condition or a third condition;
sending, by the user equipment, the PMI to the base station; wherein
the second condition is that the precoding matrix W comprises one or more column vectors of a block diagonal matrix W1, or the precoding matrix W is obtained by performing weighted combination on one or more column vectors of a block diagonal matrix W1, wherein W1=diag{X1, . . . , XNB}, and NB?1, wherein at least one block matrix X is a product X=DV of a matrix D and a matrix V, and X?{X1, X2, . . . , XNB}; the matrix D is a diagonal matrix, D=?·diag{u1, u2, . . . , un, un*, un-1*, . . . , u1*}, ? is a complex factor, a complex number ui* is a conjugate complex number of a complex number ui, i=1, . . . , n, and n is determined by a quantity of antenna ports; and the matrix V is a constant modulus matrix; and
the third condition is that the precoding matrix W comprises one or more column vectors of a block diagonal matrix W1, or the precoding matrix W is obtained by performing weighted combination on one or more column vectors of a block diagonal matrix W1, wherein W1=diag{X1, . . . , XNB}, and NB?1, wherein at least one block matrix X is a Kronecker product of a matrix A and a matrix B, X=A?B, and X?{X1, X2, . . . , XNB}; the matrix A or the matrix B is a product of a matrix D and a matrix V; the matrix D is a diagonal matrix, D=?·diag{u1, u2, . . . , un, un*, un-1*, . . . u1*}, ? is a complex factor, a complex number ui* is a conjugate complex number of a complex number ui, i=1, . . . , n, and n is a quantity of rows of the matrix A or the matrix B; and the matrix V is a constant modulus matrix;
wherein in the second condition or the third condition, the precoding matrix W satisfies W=W1W2, wherein the matrix W2 is used to select one or more column vectors of the matrix W1; or is used to perform weighted combination on one or more column vectors of the W1 to obtain the precoding matrix W.

US Pat. No. 10,116,362

PARAMETRIC GENERATING METHOD FOR ZCZ SEQUENCE SET

ZTE Wavetone Science and ...

1. A parametric generating method for a ZCZ sequence set, comprising the following steps:(1) determining a zero correlation zone (ZCZ) sequence set to be generated, wherein the ZCZ sequence set to be generated is determined as Z(N, Q, Z), N represents a length of the ZCZ sequence, Q represents a number of the ZCZ sequences, Z represents a length of a zero correlation zone, and they meet the following relation:
N=QKL  (formula 1)
wherein K?2 represents a number of iterations, and L represents an initial sequence length;
(2) determining a limited symbol set according to the types of symbols contained in the ZCZ sequence;
(3) determining an initial non-periodic orthogonal complementary sequence set according to the ZCZ sequence set to be generated and the limited symbol set;
(4) constructing a discrete Fourier transformation (DFT) matrix by using elements in the limited symbol set based on the size of the ZCZ sequence set;
(5) constructing a unitary matrix by using the elements in the limited symbol set based on the size of the ZCZ sequence set and the number of iterations;
(6) constructing a coefficient matrix composed of any elements in the limited symbol set based on the number of the ZCZ sequence sets and the number of iterations; and
(7) using the columns of the coefficient matrix respectively as the coefficients of each sequence in the ZCZ sequence set, finally generating different ZCZ sequence sets by using a method of zero filling the tails of weighted coefficients in two iterative combination modes.

US Pat. No. 10,116,361

METHODS FOR UPLINK MULTIUSER SIGNALING AND TRANSMISSION

NEWRACOM, INC., Irvine, ...

1. A method implemented by an Access Point (AP) in a Wireless Local Area Network (WLAN) to initiate an uplink (UL) multi-user (MU) simultaneous transmission, the method comprising:generating a trigger frame that initiates the UL MU simultaneous transmission, wherein the trigger frame includes (1) a UL MU Physical Layer Convergence Protocol (PLCP) Protocol Data Unit (PPDU) attributes field to indicate attributes pertaining to a UL MU PPDU transmitted to the AP during the UL MU simultaneous transmission that are common to a plurality of stations (STAs) that are scheduled to participate in the UL MU simultaneous transmission and (2) a STA Physical Layer Service Data Unit (PSDU) attributes field for a particular STA from the plurality of STAs to indicate attributes pertaining to the UL MU PPDU that are specific to the particular STA,
wherein the UL MU PPDU attributes field includes a guard interval subfield to indicate a guard interval that the plurality of STAs are to apply to one or more portions of the UL MU PPDU and wherein the STA PSDU attributes field for the particular STA includes an assignment subfield to indicate a transmission resource unit that the particular STA is to use to transmit a set of Media Access Control (MAC) Protocol Data Units (MPDUs) within the UL MU PPDU to the AP during the UL MU simultaneous transmission; and
transmitting the trigger frame through a wireless medium.

US Pat. No. 10,116,360

METHOD AND APPARATUS FOR UPLINK MULTI-USER TRANSMISSION IN A HIGH EFFICIENCY WIRELESS LAN

Newracom, Inc., Lake For...

1. A method for performing a frame exchange sequence including an uplink multi-user (UL MU) transmission by an access point (AP) in a wireless local area network, the method comprising:acquiring a transmission opportunity (TXOP) for initiating the frame exchange sequence;
determining whether a time required for the frame exchange sequence that excludes a control response frame exceeds a TXOP limit;
transmitting a trigger frame to one or more stations (STAs) when the time required for the frame exchange sequence was determined not to exceed the TXOP limit; and
when the time required for the frame exchange sequence was determined to exceed the TXOP limit:
adjusting a duration value of the UL MU transmission included in the trigger frame to meet the TXOP limit; and
transmitting the trigger frame with the adjusted duration value of the UL MU transmission to the one or more STAs.

US Pat. No. 10,116,359

EXPLICIT BEAMFORMING IN A HIGH EFFICIENCY WIRELESS LOCAL AREA NETWORK

Marvell World Trade Ltd.,...

1. A method for beamforming training, the method comprising:receiving, at a first communication device from a second communication device via a communication channel, a plurality of training signals;
determining, at the first communication device based on the plurality of training signals, a plurality of channel matrices corresponding to a plurality of orthogonal frequency division multiplexing (OFDM) tones;
generating, at the first communication device based on the plurality of channel matrices, feedback information for the plurality of OFDM tones, the feedback information including (i) steering matrix information for the plurality of OFDM tones and (ii) additional phase information corresponding to respective ones of the plurality of OFDM tones, the additional phase information for reducing phase discontinuity across the OFDM tones in steered transmissions that are to be subsequently transmitted from the second communication device to the first communication device, wherein the additional phase information corresponding to a particular OFDM tone of the plurality of OFDM tones is determined based on only a particular channel matrix of the plurality of channel matrices, the particular channel matrix corresponding to the particular OFDM tone; and
transmitting the feedback information from the first communication device to the second communication device, the feedback information to be used by the second communication device to
construct, based on the steering matrix information included in the feedback information, a plurality of steering matrices corresponding to the plurality of OFDM tones, wherein the plurality of OFDM tones are spaced according to a first tone spacing corresponding to a first number of OFDM tones in an OFDM symbol,
compensate, using the additional phase information included in the feedback information, the plurality of steering matrices to reduce phase discontinuities between the OFDM tones, and
steer, using the compensated steering matrices, at least one transmission via the communication channel from the second communication device to the first communication device, wherein steering the at least one transmission includes using the compensated steering matrices to steer at least one OFDM symbol that corresponds to a second tone spacing corresponding to a second number of OFDM tones, wherein (i) the second tone spacing is smaller than the first tone spacing and (ii) the second number of OFDM tones is greater than the first number of OFDM tones.

US Pat. No. 10,116,357

SYSTEM AND METHOD FOR MULTIPLE POINT TRANSMISSION IN A COMMUNICATIONS SYSTEM

FUTUREWEI TECHNOLOGIES, I...

1. A method for multiple point transmission operation for a user equipment (UE), the method comprising:informing, by a first transmission point to a second transmission point, to modify a bearer configuration associated with a bearer, the bearer split by a first packet data convergence protocol (PDCP) entity of the first transmission point and transferred by the first PDCP entity to a radio link control (RLC) entity of the second transmission point without going through any PDCP entity of the second transmission point, with the first PDCP entity operating at a PDCP layer and the RLC entity operating at an RLC layer; and
receiving, by the first transmission point from the second transmission point, a response indicating a modified configuration associated with the bearer.

US Pat. No. 10,116,356

SYSTEM AND METHOD FOR OPERATING A MICROPLATE READER

Molecular Devices (Austri...

1. A microplate reader comprising:a housing;
a first NFC reader/writer;
a filter tray positioning device;
a filter tray, wherein a filter tray has an NFC tag disposed thereon;
a first optical filter disposed in the filter tray, wherein the first optical filter has disposed adjacent thereto a first filter NFC tag on the filter tray; and
a controller, wherein the controller receives information about an assay protocol to be undertaken, wherein the assay protocol specifies a filter to be used;
wherein the first NFC reader/writer reads first filter information stored in the first filter NFC tag, the controller directs the first NFC reader/writer to store the first filter information in the filter tray NFC tag, and the controller enables operation of the microplate reader to undertake the assay protocol only if the first filter information indicates that the first optical filter is in accordance with the filter specified by the assay protocol.

US Pat. No. 10,116,355

POWER SUPPLY APPARATUS, POWER RECEIVING APPARATUS, AND CONTROL METHOD THEREOF

Canon Kabushiki Kaisha, ...

1. A power supply apparatus which can supply power to a power receiving apparatus in a non-contact manner, the power supply apparatus comprising:a power supply unit configured to output power to the power receiving apparatus in a non-contact manner;
a first communication unit configured to communicate with the power receiving apparatus through a first communication scheme;
a second communication unit configured to communicate with the power receiving apparatus through a second communication scheme, wherein a range in which the second communication unit can communicate is broader than a range in which the first communication unit can communicate; and
a control unit configured to transmit a request signal requesting first device information to the power receiving apparatus using the first communication unit, and output first power from the power supply unit after a response signal responding to the request signal is received from the power receiving apparatus;
wherein the control unit receives second device information from the, power receiving apparatus using the second communication unit and compares the second device information and the first device information,
wherein, in a case where both of the second device information and the first device information indicate the same power receiving apparatus, the control unit controls the power supply unit to output second power and continue communication with the power receiving apparatus via the second communication unit,
wherein, in a case where both of the second device information and the first device information do not indicate the same power receiving apparatus, the control unit controls the power supply unit to stop communication with the power receiving apparatus via the second communication unit.

US Pat. No. 10,116,354

HARVEST TAG DESIGN AND SYSTEMS

VIETAGZ, LLC, Sarasota, ...

1. An energy harvesting system comprising:(a) a harvesting tag comprising an antenna tuned for both solo performance and paired performance with at least one NFC tag and turned to operate within an electromagnetic field, wherein the antenna comprises an inductive coil and the electromagnetic field is a first inductive field generated by a NFC-enabled portable electronic device;
(b) a secondary hardware module adapted to receive an energy signal from the harvesting tag and generate an output, wherein
(i) the output is a first content type when the harvesting tag is not coupled with the at least one NFC tag,
(ii) the output is a second content type when the harvesting tag is coupled with the at least one NFC tag,
(iii) the secondary hardware module comprises a electroluminescent material,
(iv) the at least one NFC tag is configured to generate a second inductive field in response to the first inductive field, and
(v) the system further comprises software-controlled hardware that is coupled to the harvesting tag, wherein the software-controlled hardware is configured to control the energy signal from the harvesting tag to the electroluminescent material such that: (A) the energy signal has a first pattern when the harvesting tag is within the first inductive field generated by the NFC-enabled portable electronic device and not within the second inductive field generated by the at least one NFC tag, and (B) the energy signal has a second pattern when the harvesting tag is within the first inductive field and within the second inductive field.

US Pat. No. 10,116,353

CONTACTLESS COMMUNICATION DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME

Samsung Electronics Co., ...

1. A contactless communication device, comprising:a transceiver configured to generate an antenna voltage based on a first electromagnetic wave received from a contactless communication reader; and
a contactless communication chip configured to,
generate a reference clock signal based on the antenna voltage, when the contactless communication chip operates in a card mode in response to a magnitude of the antenna voltage increasing to a card mode threshold,
adjust, while operating in the card mode, a trimming value stored in a register, a frequency of an internal clock signal being adjusted based on the trimming value,
generate the internal clock signal based on the trimming value such that a frequency of the internal clock signal is same as a frequency of the first electromagnetic wave, when the contactless communication chip switches from the card mode to a reader mode in response to the magnitude of the antenna voltage decreasing to a reader mode threshold, and
communicate, while the contactless communication chip operates in the reader mode, with a contactless communication card by emitting, via the transceiver, a second electromagnetic wave based on the internal clock signal.

US Pat. No. 10,116,352

COMMUNICATION SYSTEM, TRANSMISSION DEVICE, AND RECEPTION DEVICE

Mitsubishi Electric Corpo...

1. A communication system comprising:a transmission device configured to transmit data by control of current passing through a current loop, the current loop comprising a signal line and a common line connected in series; and
a reception device connected to the transmission device by the signal line, the common line, and a power line, and configured to receive the data by detection of current passing through the current loop,
wherein at least one of the transmission device or the reception device comprises a direct current power supply configured to
generate a direct current for serial communication from an alternating current power supplied from an alternating current power supply through the power line and the common line, and
supply the generated direct current through the current loop, and
wherein at least one of the transmission device or the reception device comprises an adjuster configured to adjust an impedance between the signal line and the common line based on a voltage between the signal line and the common line, and
the adjuster is a circuit connected to the signal line and the common line and configured to pass a current having a value equal to or lower than a reference current value from the signal line to the common line based on the voltage between the signal line and the common line.

US Pat. No. 10,116,351

POLLUTION DETECTION CIRCUIT FOR DATA LINES AND METHOD THEREOF

SEMICONDUCTOR COMPONENTS ...

1. A pollution detection circuit for data lines, comprising: an impedance detector configured for coupling to at least one data terminal and detecting an impedance of said data terminal for detecting the pollution at said data terminal or said data lines; a sample and hold circuit, of the impedance detector, to store a value of a signal on the at east one data terminal as a stored signal; the impedance detector configured to apply a detection current to the at least one data terminal to form a detection signal wherein the pollution is confirmed in response to a difference less than a threshold value between the stored signal and the detection signal.

US Pat. No. 10,116,350

CHANNEL ESTIMATION

Lantiq Deutschland GmbH, ...

1. A method, comprising:defining channel estimation sequences based on values of +1, ?1 and 0, and
using the channel estimation sequences for channel estimation in a communication system using a plurality of communication connections,
wherein the channel estimation sequences comprise a plurality of orthogonal sequences which are constructed based on inner orthogonal sequences and outer orthogonal sequences, and
wherein the channel estimation sequences are constructed such that the inner orthogonal sequences are used for estimating crosstalk between communication connections assigned to a same distribution point of said communication system, and wherein the outer orthogonal sequences are usable for estimating crosstalk between communication connections associated with different distribution points.

US Pat. No. 10,116,349

SYSTEM AND METHOD FOR TIME DIVISION DUPLEXED MULTIPLEXING IN TRANSMISSION-RECEPTION POINT TO TRANSMISSION-RECEPTION POINT CONNECTIVITY

Futurewei Technologies, I...

1. A method for operating a transmission-reception point (TRP), the method comprising:transmitting, by a first TRP, a first backhaul signal to a plurality of TRPs in accordance with a first backhaul frame configuration using a plurality of beams in a first backhaul communication mode of a plurality of backhaul communication modes, the plurality of beams comprising a full set of communication beams of the first TRP, the first backhaul frame configuration indicating an arrangement of subframes in a frame used in the first backhaul signal;
receiving, by the first TRP, a second backhaul signal from a first subset of the plurality of TRPs in accordance with a second backhaul frame configuration using a first subset of the plurality of beams in a second backhaul communication mode of the plurality of backhaul communication modes, the first subset of the plurality of beams being less than the full set of communication beams of the first TRP, the second backhaul frame configuration indicating an arrangement of subframes in a frame used in the second backhaul signal; and
receiving, by the first TRP, a third backhaul signal from a second subset of the plurality of TRPs in accordance with a third backhaul frame configuration using a second subset of the plurality of beams in a third backhaul communication mode of the plurality of backhaul communication modes, the second subset of the plurality of beams being mutually exclusive from the first subset of the plurality of beams, the second subset of the plurality of TRPs being mutually exclusive from the first subset of the plurality of TRPs, the third backhaul frame configuration indicating an arrangement of subframes in a frame used in the third backhaul signal.

US Pat. No. 10,116,348

HIGH-FREQUENCY POWER AMPLIFYING MODULE AND COMMUNICATION APPARATUS

MURATA MANUFACTURING CO.,...

1. A high-frequency power amplifying module for a communication device that simultaneously transmits and receives radio frequency signals in a first communication band and a second communication band, the high-frequency power amplifying module comprising:a first high-frequency power amplifier that amplifies radio frequency signals in the first communication band, the first high-frequency power amplifier comprising a second transmission filter configured to attenuate a transmission frequency of the second communication band; and
a second high-frequency power amplifier that amplifies radio frequency signals in the second communication band, the second high-frequency power amplifier comprising a first transmission filter, a second upstream amplifier, and a second downstream amplifier,
wherein the first communication band and the second communication band produce intermodulation distortion due to the transmission frequency of the first communication band and a transmission frequency of the second communication band, the intermodulation distortion having a frequency within a reception frequency band of the second communication band,
wherein the first transmission filter is configured to attenuate the transmission frequency of the first communication band,
wherein the second upstream amplifier amplifies a transmission signal in the second communication band,
wherein the first transmission filter is disposed between the second upstream amplifier and the second downstream amplifier,
wherein the second downstream amplifier amplifies a signal having passed through the first transmission filter,
wherein the first transmission filter, the second upstream amplifier, and the second downstream amplifier are mounted on a single board, and
wherein the first transmission filter and the second transmission filter are formed as a single high-frequency power amplifying module that is different from a high-frequency circuit that is coupled to the high-frequency power amplifying module.

US Pat. No. 10,116,347

LOSSLESS SWITCH FOR RADIO FREQUENCY FRONT-END MODULE

Coolstar Technology, Inc....

1. An integrated front-end module (FEM), comprising:at least one power amplifier (PA) coupled to an antenna without inclusion of a switching element in a transmit signal path in the FEM between an output of the PA and the antenna;
at least one shunt transistor connected to an input of the at least one PA;
at least a first low-noise amplifier (LNA); and
a switching circuit coupled in a receive signal path of the FEM between the antenna and an input of the first LNA, the switching circuit being configured in a first mode to activate the at least one shunt transistor to thereby disable the PA and to connect the input of the first LNA to the antenna for receiving signals from the antenna, the switching circuit being configured in a second mode to disconnect the input of the first LNA from the antenna and to deactivate the at least one shunt transistor to thereby enable the PA for transmitting signals to the antenna.

US Pat. No. 10,116,346

ELECTRONIC DEVICE AND ANTENNA USING COMPONENTS OF ELECTRONIC DEVICE

Samsung Electronics Co., ...

1. An electronic device comprising:a housing;
a circuit board positioned inside the housing; and
an antenna radiator positioned inside the housing,
wherein the antenna radiator is fed from the circuit board, and comprises a plurality of conductive components, each of the plurality of conductive components being disposed on a portion of a respective one of a plurality of electronic components of the electronic device, and the plurality of conductive components being connected by at least one connection component,
wherein at least one of the conductive components includes a ground area that is configured to connect to a supporting unit for supporting a Flexible Printed Circuit (FPC) corresponding to the at least one connection component.

US Pat. No. 10,116,345

MULTIFUNCTIONAL PHONE CASE

1. A multifunctional electronic device case comprising:a poly-articulated hinge having opposed first and second ends, the poly-articulated hinge comprising a plurality of articulated hinge segments sequentially coupled together;
a body coupled to the first end of the poly-articulated hinge, wherein the body receives an electronic device;
a cover coupled to the second end of the poly-articulated hinge; and
a lens coupled to the cover, wherein rotating the cover with respect to the body positions the lens with respect to an electronic device screen, wherein the position of the lens with respect to the electronic device screen is self-maintaining in response to friction between the articulated hinge segments.

US Pat. No. 10,116,344

CONTROLLING DEVICE HAVING MULTIPLE USER INTERFACES

Universal Electronics Inc...

1. A controlling device, comprising:a user interface providing a plurality of function keys, each of the plurality of function keys being operable to cause a transmission of a command for commanding an operating function of each of the plurality of appliances; and
a first light source for illuminating a first set of the plurality of function keys of the user interface in a first color;
a second light source for illuminating a second set of the plurality function keys of the user interface in a second color that is visibly distinct from the first color while the first light source is illuminating the first set of the plurality of function keys of the user interface in the first color;
wherein the second set of the plurality of function keys of the user interface is different than the first set of the plurality of function keys of the user interface and wherein activation of a one of the first set of the plurality of function keys of the user interface illuminated in the first color will cause the controlling device to transmit a first command using a first communication protocol for commanding an operating function of a first one of the plurality of appliances and activation of a one of the second set of the plurality of function keys of the user interface illuminated in the second color will cause the controlling device to transmit a second command using a second communication protocol, different than the first protocol, for commanding an operating function of a second one of the plurality of appliances which is distinct from the first one of the plurality of appliances.

US Pat. No. 10,116,343

MULTI-MIXER SYSTEM AND METHOD FOR REDUCING INTERFERENCE WITHIN MULTI-MIXER SYSTEM

MEDIATEK INC., Hsin-Chu ...

1. A multi-mixer system, comprising:an amplifier module, for receiving signals from at least an antenna to generate at least a first radio frequency (RF) input signal and a second RF input signal; and
a first channel coupled to the amplifier module, wherein the first channel comprises a first mixer and a first interference reduction circuit configured between the amplifier module and the first mixer, and the first channel is used to receive the first RF input signal to generate a first mixed signal; and
a second channel coupled to the amplifier module, wherein the second channel is used to receive the second RF input signal to generate a second mixed signal, the second channel comprises a first sub-channel and a second sub-channel, the first sub-channel comprises a second mixer and a second interference reduction circuit configured between the amplifier module and the second mixer, and the second sub-channel comprises a third mixer;
wherein only one of the first sub-channel and the second sub-channel is enabled to generate the second mixed signal, and when an oscillating signal used by the second mixer or the third mixer satisfies a specific condition, the first sub-channel is enabled to generate the second mixed signal, and the second sub-channel is disabled; and when the oscillating signal used by the second mixer or the third mixer does not satisfy the specific condition, the first sub-channel is disabled, and the second sub-channel is enabled to generate the second mixed signal.

US Pat. No. 10,116,342

APPARATUS AND METHOD FOR CONTROLLING SIGNAL GAIN IN WIRELESS TRANSMITTER

Samsung Electronics Co., ...

1. An apparatus for a transmitter, the apparatus comprising:a plurality of mixers respectively coupled with a baseband processor providing a baseband signal;
a plurality of variable gain amplifiers (VGAs) respectively coupled with the plurality of mixers;
a plurality of local oscillators (LOs) respectively coupled with the plurality of mixers, the plurality of LOs comprising a first LO for a gain greater than a first threshold and a second LO for a gain lower than a second threshold which is greater than the first threshold;
an antenna operatively coupled to each of the plurality of VGAs; and
a controller configured to, if a required gain of the transmitter is greater than the first threshold and is lower than the second threshold,
identify a signal path from a first signal path for a high performance mode and a second signal path for a low power consumption mode among a plurality of signal paths, each of the plurality of signal paths comprising each of the plurality of mixers, each of the plurality of VGAs, and each of the plurality of LOs, respectively,
wherein the antenna is configured to transmit an output signal generated by using the identified signal path from the baseband signal,
wherein the first signal path corresponds to the required gain and the first LO in the first signal path is configured to consume a first current quantity, and
wherein the second signal path corresponds to the required gain and the second LO in the second signal path is configured to consume a second current quantity less than the first current quantity.

US Pat. No. 10,116,341

POLAR TRANSMITTER WITH JOINED MODULATOR

Intel IP Corporation, Sa...

1. An apparatus including a polar transmitter joined with a modulator, and operable to transmit a signal over a wireless channel, the apparatus comprising:a circuit configured to, based on a type of modulator, a type of combiner and a channel frequency:
generate first and second streams of data from received data, each stream having at least some portion of the received data that is distinct from data included in the other stream, the type of combiner comprising a multiplicative or an additive combiner, and
generate a first analog signal based on the first stream and a supply voltage based on the second stream; and
an amplifier, coupled to the circuit, and configured to generate a Radio Frequency (RF) signal based on the supply voltage and the type of combiner.

US Pat. No. 10,116,340

WIDEBAND LOW DISTORTION POWER AMPLIFIER

TEXAS INSTRUMENTS INCORPO...

1. A circuit comprising:a frequency oscillator for generating a fundamental signal frequency;
a frequency divider coupled to the frequency oscillator and configured to divide the fundamental signal frequency to generate one or more phases of the fundamental signal frequency;
a power amplifier coupled to the frequency divider, respective amplifier stages of the power amplifier configured to receive the fundamental signal frequency and the one or more phases; and
an output coupled to the respective amplifier stages of the power amplifier.

US Pat. No. 10,116,339

DETECTING POWER OF INDIVIDUAL CARRIER OF AGGREGATED CARRIER

Skyworks Solutions, Inc.,...

1. A power amplifier system comprising:power amplifiers each associated with a separate carrier, the power amplifiers including a first power amplifier and a second power amplifier, and the separate carriers including a first carrier associated with the first power amplifier and a second carrier associated with the second power amplifier;
a transmission node configured to provide a carrier aggregated signal for transmission, the carrier aggregated signal including an aggregation of the separate carriers associated with the power amplifiers;
a directional coupler configured to provide an indication of radio frequency power of the first carrier; and
a feedback control circuit coupled between the directional coupler and the first power amplifier, the feedback control circuit configured to adjust a power associated with the first power amplifier based on the indication of radio frequency power of the first carrier, and feedback control circuit further configured to adjust a second power associated with the second power amplifier based on an indication of radio frequency power of the second carrier.

US Pat. No. 10,116,338

MEASURING TRANSDUCER SUPPLY UNIT, SYSTEM FOR USE IN AUTOMATION TECHNOLOGY, AND METHOD FOR OPERATING SUCH A SYSTEM

4. A system for use in automation technology, that comprises at least the following:a superordinate unit;
at least one field unit;
a measuring transducer supply unit for use in automation technology;
a first two-wire line, which connects said measuring transducer supply unit with said at least one filed unit;
a second two-wire line, which connects said measuring transducer supply unit with said superordinate unit;
a superordinate unit that is connected through said measuring transducer supply unit to a field unit via a two-wire line; and
a mobile terminal having a unit that corresponds to said radio module for said wireless communications connection, wherein:
said measuring transducer supply unit comprises at least: one switch; one radio module; and one circuit;
said radio module can be activated and de-activated by said switch; said circuit realizes the conversion of signals between signals of two-wire lines and signals of said radio unit, so that the minimum of one field unit that is connected to the measuring transducer supply unit via said first two-wire line can be operated by means of said radio module using a wireless communications connection; and
so that said at least one field unit can be operated via said mobile terminal by means of said wireless communications connection between said measuring transducer supply unit and said mobile terminal by means of the connection between said measuring transducer supply unit and said at least one field unit via said first two-wire line.

US Pat. No. 10,116,337

DECODING METHOD FOR CONVOLUTIONALLY CODED SIGNAL

MSTAR SEMICONDUCTOR, INC....

1. A decoding method for a convolutionally coded signal of a communication system pre-storing recursion state metrics for decoding sub-trellises resulting in accelerating iteration loop convergence and reducing bit error rates, the convolutionally coded signal comprising a trellis with steps, the decoding method comprising:determining a plurality of first sub-trellises from the trellis, and determining a corresponding step for each of the first sub-trellises, each corresponding step represented by a corresponding dividing line in the trellis, each dividing line distinct from the boundaries of all the first sub-trellises;
decoding the first sub-trellises to generate a plurality of state metrics;
storing a first record containing the plurality of state metrics generated prior to and subsequent to the corresponding steps;
determining a plurality of second sub-trellises from the trellis, the boundaries of each of the second sub-trellises being distinct and non-aligned with the boundaries of each of the first sub-trellises; and
decoding the second sub-trellises by utilizing the first record as an initial condition of the second sub-trellises.

US Pat. No. 10,116,336

ERROR CORRECTING CODE ADJUSTMENT FOR A DATA STORAGE DEVICE

SanDisk Technologies LLC,...

1. A data storage device comprising:a non-volatile memory; and
a controller coupled to the non-volatile memory, the controller configured to:
initiate a read operation to access information of a codeword stored in a word line on a silicon substrate of the non-volatile memory, the codeword comprising a user data portion and an error correcting code (ECC) portion, wherein the controller includes an ECC distributor configured to statistically distribute positions of ECC portions of codewords relative to positions of user data portions;
generate, during a decoding process associated with the read operation, a modified ECC portion corresponding to the user data portion in response to an error rate associated with the information satisfying a threshold; and
write at least one bit of the modified ECC portion to a location at the non-volatile memory, wherein a physical position of the location relative to the user data portion is set to substantially equally program storage elements at the non-volatile memory based on the statistically distributed positions of ECC portions of codewords relative to positions of user data portions.

US Pat. No. 10,116,335

DATA PROCESSING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A data processing method for encoding data stored in a rewritable non-volatile memory module, and the data processing method comprising:receiving first write data;
performing, by a first stage encoding circuit, a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data so as to generate first transition data;
performing, by a second stage encoding circuit, a second stage encoding operation of the LDPC code on the first transition data so as to generate a first error correcting code (ECC), wherein the first ECC and the first write data is stored into the rewritable non-volatile memory module;
receiving second write data;
synchronously performing, by the first stage encoding circuit, the first stage encoding operation of the LDPC code on the second write data during a time period when the second stage encoding operation of the LDPC code on the first transition data is performed by the second stage encoding circuit; and
controlling a transmission path between the first stage encoding circuit and the second stage encoding circuit by a multiplexer,
wherein the first stage encoding operation is an encoding operation related to a first part of a parity check matrix, and the second stage encoding operation is an encoding operation related to a second part of the parity check matrix.

US Pat. No. 10,116,334

REED-SOLOMON CODE ENCODER AND DECODER

XILINX, INC., San Jose, ...

1. An integrated circuit (IC), comprising:an encoder circuit includes:
an encoding input configured to receive an input message including one or more data symbols, each data symbol having a data symbol width of N bits, wherein N is a positive integer;
an encoding unit configured to perform Reed-Solomon encoding to the one or more data symbols to generate one or more coding symbols, wherein the Reed-Solomon encoding uses a Galois field having an order that is less than 2N, the encoding unit comprising a first Galois field arithmetic operator configured to perform multiplication operations and division operations on field elements of the Galois field by retrieving pre-computed values from a storage; and
an encoding output configured to provide a coded message including the one or more data symbols and the one or more coding symbols,
wherein the order of the Galois field is equal to 2M,
wherein M is greater than two and less than N,
wherein the storage comprises:
a multiplication lookup table to store pre-computed values for the multiplication operations; and
a division lookup table to store pre-computed values for the division operations;
wherein each of the multiplication lookup table and the division lookup table has a size of less than M*2M*2 bits.

US Pat. No. 10,116,333

DECODER WITH PARALLEL DECODING PATHS

SANDISK TECHNOLOGIES LLC,...

1. A device comprising:a memory configured to store syndromes;
a first data processing unit coupled to the memory and configured to process a first value corresponding to a first symbol of data to be decoded;
a second data processing unit coupled to the memory and configured to process a second value corresponding to a second symbol of the data;
syndrome aggregation circuitry coupled to the first data processing unit and to the second data processing unit, the syndrome aggregation circuitry configured to combine syndrome update results of the first data processing unit and the second data processing unit; and
a variable group selector circuit configured to select a first variable node to be processed at the first data processing unit and a second variable node to be concurrently processed at the second data processing unit.

US Pat. No. 10,116,332

METHOD FOR CONFIGURING CIRCULAR BUFFER INCLUDING OUTER CODE PARITY AND APPARATUS THEREFOR

LG ELECTRONICS INC., Seo...

1. A method for configuring a circular buffer in a wireless communication system, the method performed by a user equipment (UE) and comprising:generating a code block comprising a payload, a first outer code parity, and a second outer code parity from an input signal based on an outer code in a higher layer;
generating a codeword from the code block based on an inner code in a physical layer; and
configuring a circular buffer comprising the codeword and one or more second outer code parities,
wherein the first outer code parity is generated based on a first portion of the payload,
wherein the one or more second outer code parities, to which an encoding is not applied in the physical layer, are generated based on a second portion of the payload,
wherein at least a part of the second portion is different from the first portion,
wherein the codeword comprises the payload, the first outer code parity, and an inner code parity generated from at least a part of the code block based on the inner code, and
wherein a number of the one or more second outer code parities in the circular buffer is determined according to a maximum size of the codeword or an amount of resources for transmission.

US Pat. No. 10,116,331

DATA TRANSMITTING AND RECEIVING APPARATUS HAVING IMPROVED LOW-DENSITY PARITY-CHECK (LDPC) ENCODING, DECODING AND TRANSMISSION RATE

Electronics and Telecommu...

1. A data transmitting apparatus, comprising:a low-density parity-check (LDPC) encoder configured to perform, on data to be transmitted by a faster-than-Nyquist method (FTN), LDPC encoding using a first matrix having a first degree less than a preset reference degree and a second matrix of a single diagonal matrix;
a symbol mapper configured to perform symbol mapping on information bits and a parity bits of data LDPC encoded, independently, by performing interleaving on the information bits and the parity bits using different interleavers and applying differential encoding to a part of codeword of information and a codeword of the parity bits; and
an accelerator configured to accelerate an output signal from the different interleavers by a transmission rate based on the FTN method,
wherein each degree is a value based on the number of 1's elements of a matrix, and
wherein the preset reference degree is according to degree distribution of each LDPC code rate defined in DVB-S2 standard.

US Pat. No. 10,116,330

DYNAMIC DATA COMPRESSION SELECTION

ORACLE INTERNATIONAL CORP...

19. A system for data compression including:one or more data processors; and
a non-transitory computer readable storage medium containing instructions which when executed on the one or more data processors, cause the one or more data processors to perform actions including:
receiving uncompressed source data from a data storage device, the uncompressed source data comprising a plurality of uncompressed data chunks;
determining, at a first time, a first number of threads to employ to compress the uncompressed source data;
identifying, based at least in part on the first number of, a first compression technique from a plurality of compression techniques to use to compress one or more first uncompressed data chunks of the plurality of uncompressed data chunks;
compressing, via one or more threads, the one or more first uncompressed data chunks using the first compression technique to produce one or more first compressed data chunks, a first quantity of the one or more threads being equal to the first number of threads;
routing the one or more first compressed data chunks to a data target over a network; and
at each second time of one or more second times:
determining, at the second time, a next number of threads to employ to compress the uncompressed source data, the next number of threads being different than the first number of threads;
identifying, based at least in part on the next number of threads, a next compression technique from the plurality of compression techniques to use to compress one or more next uncompressed data chunks of the plurality of uncompressed data chunks, wherein, for each of at least one second time of the one or more second times, the next compression technique is different than the first compression technique;
compressing, via at least one thread, the one or more next uncompressed data chunks of the plurality of uncompressed data chunks using the next compression technique to produce one or more next compressed data chunks, a quantity of the at least one thread being equal to the next number of threads; and
routing the one or more next compressed data chunks to the data target over the network.

US Pat. No. 10,116,329

METHOD AND SYSTEM FOR COMPRESSION BASED TIERING

EMC IP HOLDING COMPANY LL...

1. A method comprising:evaluating a level of activity of a data set, wherein the evaluating the level of activity for a data set comprises evaluating a first lower level of activity for a first data set; and evaluating a second higher level of activity for a second data set;
selecting a compression algorithm according to the level of activity of the data set, wherein the selecting the compression algorithm according to the level of activity of the data set comprises selecting a first compression algorithm having a first higher compression ratio according to the first lower level of activity of the first data set; and selecting a second compression algorithm having a second lower compression ratio according to the second higher level of activity of the second data set;
compressing data of the data set according to the selected compression algorithm; and
storing the compressed data in a data storage system.

US Pat. No. 10,116,328

ENCODERS, DECODERS AND METHODS UTILIZING MODE SYMBOLS

Gurulogic Microsystems Oy...

1. An encoder for encoding input data to generate corresponding encoded data, characterized in that:the encoder is configured to:
(a) analyze the input data to identify at least one mode symbol therein;
(b) generate data values of at least a first type and a second typefrom the input data, wherein the data values of the first type include non-mode symbols, and the data values of the second type include runs of the at least one mode symbol, wherein the at least one mode symbol is a symbol that occurs most often in the input data and the non-mode symbols are symbols other than the at least one mode symbol, wherein the runs of the at least one mode symbol are indicative of occurrences of the at least one mode symbol before or after the non-mode symbols within the input data;
(c) generate information that is indicative of a count of the non-mode symbols in the input data and information that is indicative of the at least one mode symbol; and
(d) assemble or encode the information that is indicative of the at least one mode symbol, the information that is indicative of the count of the non-mode symbols, the data values of the first type including the non-mode symbols and the data values of the second type including the runs of the at least one mode symbol, to generate the encoded data.

US Pat. No. 10,116,327

TECHNOLOGIES FOR EFFICIENTLY COMPRESSING DATA WITH MULTIPLE HASH TABLES

Intel Corporation, Santa...

1. A compute device comprising:one or more processors; and
a memory having stored therein a plurality of instructions that, when executed by the one or more processors, cause the compute device to:
produce, for each of multiple string prefixes of different string prefix sizes, an associated hash, wherein each string prefix defines a set of consecutive symbols in a string that starts at a present position in an input stream of symbols; and
write, to a different hash table for each string prefix size, a pointer to the present position in association with the associated hash, wherein each hash is usable as an index into an associated hash table to provide the present position of the string.

US Pat. No. 10,116,326

SEMI-EXHAUSTIVE RECURSIVE BLOCK DECODING METHOD AND DEVICE

INSTITUT MINES-TELECOM, ...

1. A decoder for decoding a signal received through a transmission channel in a communication system, said signal carrying information symbols selected from a given set of values and being associated with a signal vector, said transmission channel being represented by a channel matrix, wherein said decoder comprises:a sub-block division unit configured to divide the signal vector into a set of sub-vectors in correspondence with a division of a matrix related to said channel matrix;
a candidate set estimation unit for recursively determining candidate estimates of sub-blocks of the transmitted signal corresponding to said sub-vectors, each estimate of a given sub-block being determined from at least one candidate estimate of the previously processed sub-blocks,
wherein said candidate set estimation unit is configured to determine a set of candidate estimates for at least one sub-block of the transmitted signal by applying at least one iteration of a decoding algorithm using the estimates determined for the previously processed sub-blocks, the number of candidate estimates determined for said sub-block being inferior to the cardinal of said given set of values, the decoder further comprising a signal estimation unit for calculating an estimate of the transmitted signal from said candidate estimates determined for said sub-blocks.

US Pat. No. 10,116,325

DATA COMPRESSION/DECOMPRESSION DEVICE

Clarion Co., Ltd., Saita...

1. A data decompression device that decompresses compressed data including a plurality of compressed fixed-length records, comprising:a processor; and
a memory coupled to the processor;
wherein the compressed data includes a result acquired by dividing compression object data in units of a compression object block size and compressing the compression object data of each of a plurality of compression object blocks;
wherein the compression object block size is determined based upon a size of one of the plurality of compressed fixed-length records and specification information of the data decompression device, where
the specification information of the data decompression device includes a capacity of a cache memory of the data decompression device or a capacity of a main storage the data decompression device uses, and
the cache memory or the main storage is controlled not to replace contents therein during a decompression process of all columns of compressed columnar data of the plurality of compressed fixed-length records included in one compression object block;
wherein one or more compression object blocks are acquired based upon the compressed data; and
wherein the processor is programmed to decompress each of a plurality of columns of compressed columnar data of the plurality of compressed fixed-length records included in the one or more compression object blocks and restore the plurality of compressed fixed-length records.

US Pat. No. 10,116,324

HIGH-LINEARITY SIGMA-DELTA CONVERTER

TRIXELL, Moirans (FR)

1. A sigma-delta converter comprising:a sigma-delta modulator suitable for supplying a series of binary samples representative of an analogue input signal to be digitized, a delivery of a binary sample of the series of binary samples being performed on completion of a cycle of operation of the modulator, a conversion phase comprising a number of cycles necessary to produce a digital converter output value,
the modulator comprising at least one analogue filter receiving an internal analogue signal derived from the analogue input signal, in which a first predetermined law defines that a contribution to the at least one analogue filter of the analogue signal internal to a given cycle is smaller than a contribution to the analogue filter of the analogue signal internal as a function of a rank of a cycle in the conversion phase, the rank of the cycle varying from 1 to the number of cycles, the first law specifying a contribution to the analogue filter to a preceding cycle.

US Pat. No. 10,116,323

ANALOG-TO-DIGITAL CONVERTER

MEDIATEK INC., Hsin-Chu ...

1. An analog-to-digital converter (ADC) converting an input signal to an output signal; the ADC comprising:a main circuit for: scaling the input signal by a first factor, filtering an error signal by a loop filter, and forming a combined signal combining the scaled input signal and the filtered error signal; and
a comparator coupled to the main circuit, for quantizing the combined signal to provide the output signal;
wherein the error signal reflects a difference between the combined signal and the output signal;
the loop filter comprises a first delay unit and at least a loop scaling unit, for delaying and scaling the error signal by a second factor; and
a sum of the first factor and the second factor equals one.

US Pat. No. 10,116,322

RAIL ADAPTIVE DITHER

Raytheon Company, Waltha...

1. A method of converting an analog input signal to a linearized digital representation of the analog input signal, comprising:comparing a measure of the analog input signal to a threshold associated with a maximum dynamic range of a quantizer;
dynamically varying a maximum amplitude of a random, analog dither signal for perturbing quantization of the analog input signal in response to the comparison;
combining the dynamically varied dither signal and the analog input signal to obtain a dithered input signal; and
converting with the quantizer the dithered input signal into the linearized digital representation of the analog input signal.

US Pat. No. 10,116,321

INBUILT THRESHOLD COMPARATOR

TEXAS INSTRUMENTS INCORPO...

1. A comparator comprising:a first input stage coupled to a first signal input and a first reference input, the first input stage coupled between a first node and a second node;
wherein the first input stage comprises:
a first transistor coupled between the first node and the second node, the gate of the first transistor being coupled to the first signal input; and
a second transistor coupled between the first node and the second node, the gate of the second transistor coupled to one of the first reference input;
a second input stage coupled to a second signal input and a second reference input, the second input stage coupled between a third node and the second node;
an output stage for generating at least one output signal in response to signals at the first and second signal inputs;
first switching circuitry coupled between the first node and the output stage, the first switching circuitry for coupling the first node to a fourth node in response to a reset signal;
second switching circuitry coupled between the third node and the output stage, the second switching circuitry for coupling the third node to a fifth node in response to the reset signal; and
a threshold voltage wherein the threshold voltage is proportional to a first value multiplied by a second value wherein the first value is equal to a width of the first transistor divided by a width of the second transistor and the second value is equal to a voltage of the first reference input minus a voltage of the second reference input.

US Pat. No. 10,116,320

PHOTOELECTRIC CONVERSION APPARATUS AND IMAGE CAPTURING SYSTEM

Canon Kabushiki Kaisha, ...

1. A photoelectric conversion apparatus comprising:a pixel configured to output a pixel signal;
and
an analog-to-digital (AD) converter configured to perform AD conversion by comparing a ramp signal with the pixel signal, wherein
the photoelectric conversion apparatus has a first operation mode where an imaging sensitivity level is a first sensitivity level and a second operation mode where the imaging sensitivity level is a second sensitivity level different from the first sensitivity level,
in the first operation mode, the AD converter performs, in a case where the pixel signal is in a first signal level, AD conversion on the pixel signal using a first ramp signal having a first slope, and
the AD converter performs, in a case where the pixel signal is in a second signal level having an amplitude greater than an amplitude of the first signal level, AD conversion on the pixel signal using a second ramp signal having a second slope greater than the first slope,
in the second operation mode,
the AD converter performs, in a case where the pixel signal is in a third signal level, AD conversion on the pixel signal using a third ramp signal having a third slope, and
the AD converter performs, in a case where the pixel signal is in a fourth signal level having an amplitude greater than an amplitude of the third signal level, AD conversion on the pixel signal using a fourth ramp signal having a fourth slope greater than the third slope, and
the fourth slope differs from the first slope and the second slope.

US Pat. No. 10,116,319

RESISTIVE INTERPOLATION FOR AN AMPLIFIER ARRAY

TEXAS INSTRUMENTS INCORPO...

1. A circuit including a resistive interpolator, comprising:an input terminal to receive an input value;
an amplifier array, including
an amplifier stage with M amplifiers (M?2), each coupled to the input terminal to receive the input value;
a resistor interpolator configured to provide an interpolation order N (N?2), and including
an input row and at least a second row, each row comprising multiple interpolation resistors connected in series at nodes,
the input row including M driven nodes connected to a respective amplifier, and (N?1) interpolation nodes intermediate each of adjacent driven nodes, and
the input row connected in parallel to the second row, with at least some of the interpolation nodes of the first row connected to corresponding interpolation nodes of the second row;
the resistor interpolator including at least one multi-row interpolation cell, comprising:
in the input row, a driven node connected to first and second interpolation resistors connected between the driven node and respective adjacent first and second interpolation nodes;
in the second row, third and fourth interpolation resistors connected between respective third and fourth interpolation nodes and an intermediate fifth interpolation node;
the first and second interpolation nodes of the input row connected respectively to the third and fourth interpolation nodes of the second row.

US Pat. No. 10,116,318

METHOD AND SYSTEM FOR ASYNCHRONOUS CLOCK GENERATION FOR SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (SAR ADC)

Infinera Corporation, Su...

1. An analog-to-digital converter (ADC) comprising:a comparator;
a first logic gate, operatively coupled to the comparator, to generate a first output signal based on an output of the comparator;
a second logic gate, operatively coupled to the first logic gate, to generate a second output signal indicative of timing reference of bit conversion;
a first memory element, operatively coupled to the second logic gate, to generate a third output signal indicative of a current state of a bit that is input for the second logic gate;
a second memory element, operatively coupled to the second logic gate, to generate a plurality of next state bits,
wherein the second logic gate determines the second output signal based on the first output signal and the third output signal,
a third logic gate, operatively coupled to the comparator and the first logic gate, to generate an asynchronous comparator clock signal that controls a precharge operation and an evaluation operation of the comparator; and
a digital-to-analog converter (DAC), operatively coupled to the comparator and the second memory element, to generate a reference voltage based on the plurality of next state bits,
wherein the third output signal is determined based on an inverse signal of the asynchronous comparator clock signal.

US Pat. No. 10,116,317

SIGNAL GENERATOR WITH SELF-CALIBRATION

Iowa State University Res...

1. A signal generator comprising:a main digital-to-analog converter (DAC) providing a main DAC output signal with main DAC distortion;
a calibration DAC providing a calibration DAC output signal, which includes information about the main DAC distortion;
a summing buffer structure configured to sum the main DAC output signal and the calibration DAC output signal and provide a summing output signal, which corrects at least a portion of the main DAC distortion;
a two-path filter structure including a first filter path and a second filter path, wherein:
when the first filter path is conducted, the two-path structure is configured to provide a first filter output signal based on the summing output signal; and
when the second filter path is conducted, the two-path structure is configured to provide a second filter output signal based on the summing output signal;
an analog-to-digital converter (ADC) providing a first ADC output signal based on the first filter output signal and providing a second ADC output signal based on the second filter output signal; and
a control system coupled between the ADC and the calibration DAC, wherein:
the control system is configured to provide a calibration DAC input signal to the calibration DAC to update the calibration DAC output signal, wherein the updated calibration DAC output signal includes updated information about the main DAC distortion; and
the calibration DAC input signal is calculated from the first ADC output signal and the second ADC output signal.

US Pat. No. 10,116,316

RECEIVER WITH SIGNAL PROCESSOR TO ADAPTIVELY UPDATE WEIGHTS TO SEPARATE LARGER AND SMALLER COMPONENTS

SPATIAL DIGITAL SYSTEMS, ...

16. A method comprising:applying a first complex weight to a first signal so as to generate a second signal, the first signal having larger and smaller components;
approximating a first value of a sample of the first signal into a second value corresponding to the larger component;
updating the first complex weight using correlation between the second signal and the second value;
approximating the second signal into a third signal; and
aligning a phase of the smaller component in the first signal with a phase of the third signal so as to generate a fourth signal.

US Pat. No. 10,116,315

SYSTEM-ON-A-CHIP CLOCK PHASE MANAGEMENT USING FRACTIONAL-N PLLS

QUALCOMM Incorporated, S...

1. A fractional-N phase-locked loop (PLL), comprising:a phase control circuit configured to begin a phase accumulation responsive to an identified edge of a reference clock signal, wherein the phase control circuit is configured to receive a trigger signal that identifies the identified edge of the reference clock signal;
a feedback divider configured to divide an output clock signal by an integer divisor that is adjusted responsive to the phase accumulation to form a divided feedback clock signal; and
an oscillator configured to drive the output clock signal at an output frequency responsive to a control signal so that the output clock signal is phase aligned with the reference clock signal.

US Pat. No. 10,116,314

MULTI-MODE FREQUENCY DIVIDER

NVIDIA Corporation, Sant...

1. A device comprising a frequency divider, the device comprising:first circuitry;
second circuitry coupled to the first circuitry, wherein the second circuitry is selectively enabled using a control signal and wherein the second circuitry receives a signal from the first circuitry when the second circuitry is enabled; and
third circuitry coupled to the first circuitry and the second circuitry, wherein the third circuitry receives signals from the first circuitry and also receives signals from the second circuitry when the second circuitry is enabled, wherein the first circuitry and the third circuitry comprise a divide-by-two frequency divider when the second circuitry is not enabled, wherein the first circuitry, the second circuitry, and the third circuitry comprise a divide-by-three frequency divider when the second circuitry is enabled, and wherein the third circuitry comprises a plurality of resistors and capacitors, wherein capacitances of the capacitors are programmable.

US Pat. No. 10,116,313

APPARATUS AND METHOD TO MITIGATE PHASE AND FREQUENCY MODULATION DUE TO INDUCTIVE COUPLING

Intel Corporation, Santa...

1. An apparatus comprising:a first clocking source having a first divider;
a second clocking source having a second divider, wherein the first and second clocking sources are close enough in proximity to one another such that they are inductively coupled to one another; and
calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code to adjust at least one divider ratio of the first or second dividers according to the monitored clock signals; and
a sigma-delta modulator to receive the at least one calibration code from the calibration logic, wherein the at least one calibration code is generated according to the monitored clock signals.

US Pat. No. 10,116,312

CONFIGURABLE GATE ARRAY BASED ON THREE-DIMENSIONAL WRITABLE MEMORY

HangZhou HaiCun Informati...

1. A configurable gate array, comprising:at least a configurable logic element formed on a semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library; and
at least a configurable computing element, wherein said configurable computing element comprises a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, said first 3D-W array is electrically programmable and can be loaded with a first look-up table (LUT) for a first math function.

US Pat. No. 10,116,311

EMBEDDED FPGA WITH MULTIPLE CONFIGURABLE FLEXIBLE LOGIC BLOCKS INSTANTIATED AND INTERCONNECTED BY ABUTMENT

1. An embedded field programmable gate array comprising:a plurality of abuttable, configurable and programmable logic blocks (ACLBs), the plurality of ACLBs comprising at least a plurality of sets of ACLBs, each set of ACLBs being of a different defined functional block, each the plurality of ACLBs being interconnected with adjacent ACLBs by abutment and selective pin placement to connect at least an out pin to at least an adjacent in pin.

US Pat. No. 10,116,310

LEVEL SHIFT CIRCUIT, INTEGRATED CIRCUIT, AND POWER SEMICONDUCTOR MODULE

Mitsubishi Electric Corpo...

1. A level shift circuit, comprising:a primary circuit that outputs, in response to a received input signal, a first signal with a first reference potential;
a level shift main circuit that converts a reference potential of said first signal received from said primary circuit, from said first reference potential to a second reference potential to output a second signal with said second reference potential;
a secondary circuit that generates, in response to said input signal, an output signal with said second reference potential by using said second signal received from said level shift main circuit; and
at least one rectifying element circuit provided between said primary circuit and said secondary circuit, at least one of said primary circuit and said secondary circuit including at least one detection circuit that detects a change in a current flowing through said rectifying element circuit to determine whether a potential corresponding to said second reference potential is lower than or equal to a potential corresponding to said first reference potential.

US Pat. No. 10,116,309

CMOS OUTPUT CIRCUIT

Rohm Co., Ltd., Kyoto (J...

1. A CMOS output circuit comprising:a first P-MOSFET having a source connected to a power supply terminal, a drain connected to an output terminal, and a back gate connected to a first potential terminal;
a first N-MOSEFET having a drain connected to the output terminal, a source connected to a ground terminal, and a back gate connected to a second potential terminal;
a first potential switching portion arranged to switch whether to connect the first potential terminal to the power supply terminal or to the output terminal;
a second potential switching portion arranged to switch whether to connect the second potential terminal to the ground terminal or to the output terminal;
a first gate switching portion arranged to switch whether or not to short-circuit the gate of the first P-MOSFET to the first potential terminal;
a second gate switching portion arranged to switch whether or not to short-circuit the gate of the first N-MOSFET to the second potential terminal;
a first driver arranged to drive the gate of the first P-MOSFET in accordance with a first input signal;
a second driver arranged to drive the gate of the first N-MOSFET in accordance with a second input signal; and
a control portion arranged to control individual portions of the circuit when turning off both the first P-MOSFET and the first N-MOSFET, so as to connect the first potential terminal to one of the power supply terminal and the output terminal, which has a higher potential, to connect the second potential terminal to one of the ground terminal and the output terminal, which has a lower potential, to short-circuit the gate of the first P-MOSFET to the first potential terminal, and to short-circuit the gate of the first N-MOSFET to the second potential terminal.

US Pat. No. 10,116,308

ROTATION OPERATION DEVICE

DENSO CORPORATION, Kariy...

1. A rotation operation device comprising:a rotation operation section having a cylindrical shape and rotationally operable by an operator around an axis of the cylindrical shape;
a plurality of recessed and projecting sections arranged on an axial end surface or a peripheral surface of the rotation operation section and having recesses and projections in a circumferential direction of the rotation operation section;
a conductive section made of a conductive material, having a protruding section protruding toward each of the recessed and projecting sections and an elastic section that biases the protruding section by elasticity to each of the recessed and projecting sections, and movable in a recess-and-projection direction by each of the recessed and projecting sections when the rotation operation section rotates;
an electrode section disposed so as to face the conductive section and changing a capacitance in accordance with a movement of the conductive section; and
a detecting section detecting the change in the capacitance, wherein:
three or more sets of combination of the recessed and projecting sections, the conductive section, and the electrode section are provided;
the conductive section in each set is moved in turn by a respective recessed and projecting section in the recess-and-projection direction at a different timing with regular intervals; and
the detecting section detects a rotation direction and a rotation quantity of the rotation operation section by means of a combination pattern of the change in the capacitance provided by the electrode section,
wherein the recessed and projecting sections, the conductive section, and the electrode section in each set of the combination are arranged in a concentric manner.

US Pat. No. 10,116,307

LOW POWER CAPACITIVE SENSOR BUTTON

Cypress Semiconductor Cor...

1. An apparatus comprising:a timer circuit configured to generate a repetitive trigger signal having a first frequency;
an oscillator configured to generate a clock signal having a second frequency;
a sensing circuitry block coupled with the timer circuit and the oscillator and configured to, in response to the repetitive trigger signal, detect a change in capacitance associated with an object proximate to a capacitive sensor button by applying an excitation signal to the capacitive sensor button during a measurement period; and
a wake logic coupled with the sensing circuitry block, the wake logic configured to transition a processing unit from a first power consumption state to a second power consumption state in response to the sensing circuitry block detecting the change in capacitance associated with the object proximate to the capacitive sensor button.

US Pat. No. 10,116,306

TOUCH AND FORCE SENSITIVE ROCKER SWITCH

Apple Inc., Cupertino, C...

5. A portable electronic device, comprising:a housing that defines an interior volume, the housing comprising a sidewall that includes a through hole;
a button aligned with the through hole, the button comprising a surface;
a capacitive sensor positioned in the interior volume and at least partially covered by the button; and
a force sensor positioned in the interior volume and at least partially covered by the button, wherein the button is configured to accept i) a touch input to the surface that is detected by the capacitive sensor, and ii) a force touch input that is determined by the force sensor.

US Pat. No. 10,116,305

SEMICONDUCTOR DEVICE FOR DISPLAY DRIVER IC STRUCTURE

Magnachip Semiconductor, ...

1. A semiconductor device, comprising:a first transistor, a second transistor, and a third transistor formed on a semiconductor substrate, wherein
the first transistor comprises
a first gate insulator having a first thickness,
a first source region and a first drain region,
a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and
a first gate electrode,
the second transistor comprises
a second gate insulator having a second thickness that is thinner than the first thickness,
a second source region and a second drain region,
a pair of drift regions that encompass the second source region and the second drain region respectively, and
a second gate electrode, and
the third transistor comprises
a third gate insulator having the first thickness,
a third source region and a third drain region, and
a pair of drift regions that encompass the third source region and the third drain region respectively, and
a third gate electrode.

US Pat. No. 10,116,304

GATE TRANSISTOR CONTROL CIRCUIT

1. A device for controlling a first control gate transistor, comprising:a second transistor and a third transistor series-connected between first and second terminals of application of a power supply voltage, the junction point of these transistors being connected to the gate of the first transistor,
a terminal of application of a digital control signal;
a circuit for generating an analog signal according to variations of the power supply voltage; and
for each of the second and third transistors, a circuit of selection of a control signal of the first transistor representative of said digital signal or of said analog signal, wherein the selection circuit selects a signal among said digital control signal and said analog signal such that one of the second and third transistors is controlled in a linear state while the other one of the second and third transistors is controlled in a saturated state.

US Pat. No. 10,116,303

PARALLEL DEVICES HAVING BALANCED SWITCHING CURRENT AND POWER

VIRGINIA TECH INTELLECTUA...

1. A system comprising:a power source that provides electrical power;
two driving transistors disposed in parallel and receiving electrical power from the power source, wherein each of the two driving transistors includes a gate terminal, a source connection, and a kelvin source connection; and
a control voltage source having a first terminal and a second terminal, wherein:
the control voltage source provides a control signal to the two driving transistors to activate the two driving transistors,
the first terminal is connected to the gate terminal of a first of the two driving transistors via a common inductor and a first inductor,
the first terminal is connected to the gate terminal of a second of the two driving transistors via the common inductor and a second inductor, and
the second terminal is connected to the kelvin source connections of the two driving transistors;
wherein the kelvin source connections of the two driving transistors are inductively coupled.

US Pat. No. 10,116,302

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device, comprising:a low-side terminal having a low-side potential;
a high-side terminal having a high-side potential different from the low-side potential;
a main output terminal having an intermediate potential;
a low-side switching element being provided between the main output terminal and the low-side terminal;
a low-side drive circuit which drives the low-side switching element and operates using the low-side potential as a reference potential and using a supply potential regulated by an offset voltage from the low-side potential as a power source potential;
a high-side switching element being provided between the main output terminal and the high-side terminal;
a high-side drive circuit which drives the high-side switching element and operates using the intermediate potential as a reference potential and using a floating potential regulated by an offset voltage from the intermediate potential as a power source potential;
a detection circuit using the intermediate potential as a reference potential and detecting condition information of the high-side switching element, thereby outputting a detection signal;
a conversion circuit using the intermediate potential as a reference potential and outputting a conversion signal corresponding to the detection signal from the detection circuit, and
a signal transmission circuit outputting a signal corresponding to the conversion signal from the conversion circuit as a voltage signal using the low-side potential as a reference potential, wherein
the signal transmission circuit includes:
a first point to which the intermediate potential is applied;
a second point to which a referred potential between the low-side potential and the high-side potential is applied, the referred potential being different from the low-side potential and the high-side potential;
a signal switching element having a first end connected to the first point and a second end, and being switched in accordance with the conversion signal; and
a diode being provided between the second point and the second end of the signal switching element and having a direction with which a forward current can flow by a voltage between the first point and the second point in a case where the intermediate potential is the low-side potential.

US Pat. No. 10,116,301

CROSS-COUPLED, NARROW PULSE, HIGH VOLTAGE LEVEL SHIFTING CIRCUIT WITH VOLTAGE DOMAIN COMMON MODE REJECTION

INFINEON TECHNOLOGIES AME...

6. A circuit, comprising:a high side circuit, including:
current mirrors configured to generate mirrored currents that mirror a set signal and a reset signal that are generated in response to a set pulse and a reset pulse;
a cross coupled current mode cancellation circuit connected to the current mirrors, wherein the cross coupled current mode cancellation circuit is configured to attenuate at least a portion of a slew current from a first one of the mirrored currents to generate an adjusted first signal, and to generate a first voltage at a resistor according to the adjusted first signal; and
a high side driver configured to provide a high output signal according to activation to the first voltage.

US Pat. No. 10,116,300

SWITCHING COMPONENT, IN PARTICULAR DOMESTIC-APPLIANCE SWITCHING COMPONENT

1. A switching component, comprising:a main driver that applies an electrical signal to a plurality of driver circuits;
a series circuit of a plurality of field effect transistors;
each driver circuit is associated with one of the plurality of field effect transistors, each driver circuit having at least one switching element, which short circuits two control contacts of the associated field effect transistor in at least one operating state to simultaneously switch off each of the associated field effect transistors.

US Pat. No. 10,116,299

POWER-ON RESET CIRCUIT

SEMICONDUCTOR MANUFACTURI...

1. A power-on-reset circuit comprising:an execution circuit comprising a first input terminal, a second input terminal, and a first output terminal, the first input terminal directly connected to a power supply voltage, a voltage at the second input terminal having a low level at an initial state, and a voltage at the first output terminal having a low level, wherein the voltage at the first output terminal transitions from the low level to a high level when the power supply voltage at the first input terminal and the voltage at the second input terminal are not less than a predetermined voltage; and
a control circuit comprising a third input terminal connected to the first output terminal, a fourth input terminal connected to the first input terminal, and a second output terminal connected to the second input terminal, wherein the voltage at the second input terminal transitions from the low level to the high level when a difference between the power supply voltage at the first input terminal and the voltage at the first output terminal is greater than a predetermined voltage difference,
wherein the execution circuit comprises a NAND gate having a first input terminal directly connected to the first input terminal of the execution circuit, a gate connected to the second input terminal of the execution circuit, a drain connected to the output terminal of the NAND gate, a source connected in series with a reverse-biased diode circuit to the power supply voltage, and a substrate connected to the power supply voltage.

US Pat. No. 10,116,298

APPARATUS WITH MAIN TRANSISTOR-BASED SWITCH AND ON-STATE LINEARIZATION NETWORK

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a main transistor-based switch having a first end node and a second end node comprising an N number of main field effect transistors (FETs) each having a first terminal, a second terminal, and a gate terminal and stacked in series such that the first terminal of a first main FET of the N number of main FETs is coupled to the first end node and the second terminal of an Nth main FET of the N number of main FETs is coupled to the second end node, wherein N is a finite number greater than one;
an ON-state linearization network that is coupled between the first end node and the second end node of the main transistor-based switch and configured to:
receive a monitored signal that corresponds to a signal across the first end node and the second end node;
cancel at least a portion of non-linear distortion generated by the main transistor-based switch when the main transistor-based switch is in an ON-state based on the monitored signal, wherein a control signal applied to a control input of the ON-state linearization network causes the ON-state linearization network to activate when the main transistor-based switch is in the ON-state and to deactivate the ON-state linearization network when the main transistor-based switch is an OFF-state; and
a first non-linear distortion cancellation (NDC) FET having a first NDC terminal coupled to the first terminal of the first main FET and a second NDC terminal coupled to the second terminal of the first main FET, and an NDC gate terminal coupled to both the control input and the second terminal of the Nth main FET; and
a control system having an output coupled to the control input and configured to provide the control signal.

US Pat. No. 10,116,297

DC-COUPLED HIGH-VOLTAGE LEVEL SHIFTER

pSemi Corporation, San D...

1. A control circuit configured to control a high voltage device capable of withstanding a voltage higher than a first voltage (VIN), the control circuit comprising:low voltage transistor devices configured to operate between a first switching voltage (SW) and a second switching voltage (Vdd2+SW);
a first terminal configured to carry the first switching voltage, the first switching voltage switching between a reference voltage and the first voltage;
a second terminal configured to carry the second switching voltage as a function of the first switching voltage, the second switching voltage substantially corresponding to a sum of the first switching voltage and a second voltage (Vdd2) substantially lower than the first voltage;
input nodes configured to receive input timing control pulse signals;
a parallel resistive-capacitive coupling, coupled to the input nodes, configured to receive the input timing control pulse signals and transmit edge information and DC level information of the input timing control pulse signals to the low voltage transistor devices; and
an output node configured to provide an output timing control signal at a voltage higher than the first switching voltage for control of the high voltage device, the output timing control signal being based on the transmitted edge information and DC level information of the input timing control pulse signals through the parallel resistive-capacitive coupling.

US Pat. No. 10,116,296

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ELECTRONIC DEVICE

RENESAS ELECTRONICS CORPO...

1. An electronic device comprising:a power semiconductor device;
a first semiconductor integrated circuit device driving the power semiconductor device; and
a second semiconductor integrated circuit device controlling the first semiconductor integrated circuit device,
wherein the power semiconductor device comprises:
a terminal outputting drive current; and
a terminal outputting sense current,
wherein the first semiconductor integrated circuit device comprises:
a drive circuit driving the power semiconductor device;
an overcurrent detection circuit detecting overcurrent on the basis of the sense current; and
a temperature detection circuit detecting temperature of the power semiconductor device, and
wherein the second semiconductor integrated circuit device comprises:
a storage device storing a temperature characteristic of a current mirror ratio of the power semiconductor device;
a temperature detecting unit calculating temperature on the basis of an output of the temperature detection circuit; and
an overcurrent detection control unit controlling the overcurrent detection circuit on the basis of the temperature detected by the temperature detecting unit and the temperature characteristic of the current mirror ratio stored in the storage device.

US Pat. No. 10,116,295

VOLTAGE COMPARING CIRCUIT AND VOLTAGE COMPARING METHOD

PixArt Imaging Inc., Hsi...

1. A voltage comparing circuit, comprising:a comparator, comprising a first comparing terminal and a second comparing terminal;
a time interval computing unit;
a switch module, coupled to the first comparing terminal and the second comparing terminal, comprising a reference voltage terminal coupled to a reference voltage source, and comprising a first input terminal and a second input terminal;
a first current source, comprising a first charging terminal coupled to the first input terminal and the second input terminal;
a first capacitor, coupled to the first current source at the first charging terminal; and
a capacitance adjusting unit, coupled to the first capacitor.

US Pat. No. 10,116,294

HIGH-RESOLUTION FET VDS ZERO-VOLT-CROSSING TIMING DETECTION SCHEME IN A WIRELESS POWER TRANSFER SYSTEM

Texas Instruments Incorpo...

1. A control module for controlling a field-effect transistor having a gate, a drain and a source, the control module comprising:a comparator operable to receive the drain-to-source voltage of the transistor and compare it to a threshold voltage, the comparator comprising a clock input operable to receive a gate voltage of the transistor, wherein said received gate voltage is used to latch a result of said comparison to an output of the comparator; and
control circuitry operable to receive said comparator output and to perform a control function with respect to the transistor based on the value of the comparator output.

US Pat. No. 10,116,293

INPUT BUFFER CIRCUIT

SK hynix Inc., Icheon-si...

1. An input buffer circuit comprising:a first buffer configured to buffer a command address received based on a selection signal;
a second buffer configured to buffer the command address based on the selection signal, and have characteristics different from those of the first buffer; and
a variable delay matching circuit configured to delay an output signal of the first buffer and an output signal of the second buffer, and control a delay time in different ways according to the selection signal.

US Pat. No. 10,116,292

IGBT GATE DRIVING CIRCUIT

Renesas Electronics Corpo...

1. A semiconductor device comprising:a gate line connected to a gate terminal of a power device including a first terminal, a second terminal, and the gate terminal;
a plurality of first constant-current circuits connected between the gate line and a power supply line;
a plurality of second constant-current circuits connected between the gate line and a ground line;
a constant-current circuit selecting circuit configured to select a constant-current circuit to be activated from among the plurality of first constant-current circuits and the plurality of second constant-current circuits and output an activation instruction signal to the selected constant-current circuit;
a first comparator configured to change a level of a first voltage detection signal from a first logical level to a second logical level when a voltage at the gate terminal becomes higher than a first threshold voltage;
a second comparator configured to change a level of a second voltage detection signal from the first logical level to the second logical level when the voltage at the gate terminal becomes higher than a second threshold voltage; and
a gate mode setting circuit configured to control an on/off-state of the constant-current circuit selected by the constant-current circuit selecting circuit based on a gate control signal for controlling an on/off-state of the power device, the activation instruction signal, the first voltage detection signal, and the second voltage detection signal,
wherein the gate mode setting circuit controls the on/off-state of the constant-current circuit selected by the constant-current circuit selecting circuit in a first period in which the first and second voltage detection signals have different logical levels,
the gate mode setting circuit controls the on/off-state of the constant-current circuit selected by the constant-current circuit selecting circuit in a second period in which the first and second voltage detection signals have the same logical level and
the gate mode setting circuit increases a number of constant-current circuits controlled in an on-state in the second period compared to a number of constant-current circuits controlled in an on-state in the first period.

US Pat. No. 10,116,291

REVERSE CURRENT PROTECTION CIRCUIT

TEXAS INSTRUMENTS INCORPO...

1. A power interface subsystem for a battery-powered electronic system, comprising:a power transistor having: a source/drain path coupled between a battery terminal and an accessory terminal; and a gate; and
a reverse current protection circuit including:
an input differential amplifier stage, including first and second input legs, the first leg coupled to the battery terminal, the second leg coupled to the accessory terminal, the first leg including first and second transistors with their source/drain paths connected in series, the second leg including third and fourth transistors with their source/drain paths connected in series, and the first and third transistors having gates connected together at the drain of the second transistor;
first and second load devices coupled to the first and second input legs, respectively;
an offset voltage source, coupled to the input differential amplifier stage to cause an offset of a selected polarity between the first and second input legs;
a replica bias leg including: a replica load device; and first and second replica transistors having their source/drain paths connected in series between the battery terminal and the replica load device, the drain of the second replica transistor connected to gates of the first and second replica transistors and to gates of the second and fourth transistors; and
gate control circuitry coupled to apply a gate voltage to the power transistor responsive to a voltage at an output node at the second load device.

US Pat. No. 10,116,290

RF FRONTEND HAVING A WIDEBAND MM WAVE FREQUENCY DOUBLER

SPEEDLINK TECHNOLOGY INC....

1. A radio frequency (RF) integrated circuit, comprising:a RF transceiver to transmit and receive RF signals;
a frequency synthesizer coupled to the RF transceiver to perform frequency synthesis,
wherein the frequency synthesizer includes:
a local oscillator (LO) to generate a LO signal,
a frequency doubler circuit coupled to the LO to double a frequency of the LO signal, the frequency doubler circuit including:
a first field effect transistor having a first gate, a first source, and a first drain; and
a second field effect transistor having a second gate, a second source, and a second drain, wherein the first gate of the first field effect transistor and the second source of the second field effect transistor are driven by an input signal in a first phase, wherein the first source of the first field effect transistor and the second gate of the second field effect transistor are driven by the input signal in a second phase, wherein the first field effect transistor and the second field effect transistor are caused to switch based on the first phase and the second phase of the input signal respectively to generate an output signal at the first drain and the second drain having a frequency that is approximately double of the input signal.

US Pat. No. 10,116,289

SIGNAL PROCESSING CIRCUIT FOR MITIGATING PULLING EFFECT AND ASSOCIATED METHOD

MediaTek Inc., Hsin-Chu ...

1. A transmitter, comprising:a first mixer, arranged to upconvert a first input signal with an oscillation signal to generate a first output signal, wherein the oscillation signal is generated by dividing a frequency of a reference clock with a frequency dividing factor;
a first amplifier, coupled to the first mixer, the first amplifier arranged to amplify the first output signal and generate an amplified output signal at an output terminal of the first amplifier; and
a pulling effect mitigation circuit, coupled to the output terminal of the first amplifier, the pulling effect mitigation circuit arranged to generate a compensation signal, to the output terminal for reducing at least an Nth harmonic of the amplified output signal, the pulling effect mitigation circuit comprising:
a first phase shifting circuit, configured to shift a phase of the first input signal and output a phase shifted first input signal, the phase shifted first input signal having a different phase from that of the first input signal;
a second phase shifting circuit, configured to shift a phase of the oscillation signal to produce a phase shifted oscillation signal, the phase shifted oscillation signal having a different phase from that of the oscillation signal; and
a second mixer, coupled to the first phase shifting circuit, configured to mix the phase shifted first input signal with the phase shifted oscillation signal to generate a second output signal, wherein a frequency of the phase shifted oscillation signal is equal to a frequency of the oscillation signal, and wherein a sum of the phase shifts produced by the first and second phase shifting circuits is 90 degrees;
wherein a value of N is equal to the frequency dividing factor, such that the compensation signal reduces at least the Nth harmonic of the amplifier output signal to prevent the amplified output signal from affecting the frequency of the oscillation signal.

US Pat. No. 10,116,288

REDUCED OVERHEAD ON DIGITAL SIGNAL PROCESSING FOR MOTOR DRIVE APPLICATIONS

HAMILTON SUNDSTRAND CORPO...

1. A monostable multivibrator communicatively coupled to a host device and an external analog-to-digital converter, the monostable multivibrator configured to:receive a chip select signal from the host device, the chip select signal going low to trigger the monostable multivibrator to provide the monostable pulse; and
generate, in response to the chip select signal, a conversion start signal to the external analog-to-digital converter, the conversion start signal comprising the monostable pulse provided by the monostable multivibrator to the external analog-to-digital converter; and
control a pulse width of the monostable pulse by a resistor-capacitor circuit of the monostable multivibrator.

US Pat. No. 10,116,287

SWITCHED CURRENT CONTROL MODULE AND METHOD THEREFOR

NXP USA, Inc., Austin, T...

1. A switched current control module comprising:a hysteretic control component arranged to receive a high threshold value signal, a low threshold value signal and an indication of a current flow through a load, and to output a switched current control signal based on a comparison of the current flow indication to the high and low threshold value signals;
a threshold generator component arranged to generate the high and low threshold value signals based on a base threshold value and a hysteretic excursion value;
a base threshold value generator component arranged to receive the current flow indication and a setpoint value, to determine an average current error value for the current flow through the load based on the received indication of current flow through the load and the setpoint value, and to generate the base threshold value signal based on the determined average current error value; and
a hysteretic excursion value generator component arranged to receive an indication of a switching frequency of the switched current control signal output by the hysteretic control component, and to generate the hysteretic excursion value signal based on the indicated switching frequency of the switched current control signal.

US Pat. No. 10,116,286

REFERENCE CLOCK SIGNAL GENERATORS AND METHODS FOR GENERATING A REFERENCE CLOCK SIGNAL

Agency for Science, Techn...

1. A method for generating a reference clock signal, the method comprising:discharging a capacitive element to a discharged state, when a reset signal has a predetermined reset state;
charging the capacitive element from the discharged state to a first voltage, when a charge signal has a predetermined charge state;
comparing the first voltage to a zero voltage, when a compare signal has a predetermined compare state;
generating a second voltage based on the comparing of the first voltage to the zero voltage;
generating a clock signal based on the second voltage, using an oscillator; and
generating each of the reset signal, the charge signal and the compare signal, based on the clock signal.

US Pat. No. 10,116,285

INTEGRATION OF A REPLICA CIRCUIT AND A TRANSFORMER ABOVE A DIELECTRIC SUBSTRATE

QUALCOMM Incorporated, S...

1. A method comprising:forming a replica circuit above a surface of a glass-type material of a single dielectric substrate, wherein the replica circuit comprises a thin-film transistor (TFT) configured to function as a variable capacitor or a variable resistor;
forming a first inductor structure of a transformer above the surface of the glass-type material of the single dielectric substrate;
forming a second inductor structure of the transformer, the second inductor structure formed using a metal layer deposited above the first inductor structure; and
using the metal layer, forming one or more of a gate electrode of a transistor, a source electrode of the transistor, or a drain electrode of the transistor,
wherein the transformer is coupled to the replica circuit, and wherein the transformer is configured to facilitate an impedance match between the replica circuit and an antenna.

US Pat. No. 10,116,284

BRANCHING DEVICE

MURATA MANUFACTURING CO.,...

1. A branching device comprising:a switch including a common terminal, a first individual terminal, and a second individual terminal;
a fixed filter circuit connected to the first individual terminal and having a fixed pass band; and
a tunable filter circuit connected to the second individual terminal and having a tunable pass band, wherein
the fixed filter circuit includes a plurality of filters having different pass bands,
the pass bands of the plurality of filters correspond to frequency bands used in carrier aggregation,
if carrier aggregation is carried out, the common terminal is connected to the fixed filter circuit through the first individual terminal, and
if carrier aggregation is not carried out, the common terminal is connected to the tunable filter circuit through the second individual terminal.

US Pat. No. 10,116,283

DUAL PASSBAND RADIO FREQUENCY FILTER AND COMMUNICATIONS DEVICE

Resonant Inc., Santa Bar...

1. A communications device, comprising:a multi-band filter having a lower pass-band and an upper pass-band separated by an intervening stop-band, comprising:
a first plurality of acoustic wave resonators including two or more first-network shunt resonators and two or more first-network series resonators coupled to form a first ladder network; and
a second plurality of acoustic wave resonators forming a second ladder network, the first and second ladder networks coupled in series between a first port and a second port, wherein
the two or more first-network shunt resonators have respective motional resonance frequencies below a lower edge of the lower passband to provide transmission zeros below the lower edge of the lower pass-band and the two or more first-network series resonators have respective anti-resonance frequencies above an upper edge of the upper passband to provide transmission zeros above the upper edge of the upper pass-band, and
the second ladder network is configured to provide transmission zeros at frequencies within the intervening stop-band.

US Pat. No. 10,116,282

MULTI-FUNCTION FREQUENCY CONTROL DEVICE

RAKON LIMITED, Auckland ...

1. A frequency control device, constructed as a single component, comprising at least three thermally coupled elements: a first resonating element whose resonant frequency is within the HF band or higher, a second resonating element whose resonant frequency is within the LF band or lower, and a temperature sensing element, and wherein, in addition to facilitating the generation of high frequency and low frequency signals, the said resonating elements allow, when used in conjunction with the said temperature sensing element, for high resolution determination of the said device's temperature.

US Pat. No. 10,116,281

POWER COMBINER/DIVIDER USING MUTUAL INDUCTANCE

Samsung Electronics Co., ...

1. A power divider circuit using a mutual inductance, comprising:a first primary inducing element having a first terminal connected with a first output port and a second terminal connected with a second primary inducing element;
the second primary inducing element having a first terminal connected with a second output port and a second terminal connected with the first primary inducing element and magnetically and mutually coupled with the first primary inducing element;
a first sub inducing element having a first terminal connected with an input port and a second terminal connected with the second terminal of the first primary inducing element and the second terminal of the second primary inducing element; and
an isolation network connected between the first output port and the second output port, wherein the first sub inducing element is magnetically and mutually coupled with each of the first primary inducing element and the second primary inducing element.

US Pat. No. 10,116,280

COIL COMPONENT

SAMSUNG ELECTRO-MECHANICS...

9. A coil component comprising:a body including first and second filter parts overlaying each other and a main surface of a substrate, and spaced apart from each other in a thickness direction orthogonal to the main surface of the substrate,
wherein:
each filter part of the first and second filter parts includes upper and lower coils disposed in the body to overlay each other and spaced apart from each other in the thickness direction,
one of the upper and lower coils of the first filter part is electrically connected in series with one of the upper and lower coils of the second filter part such that a first current flowing in the one coil of the first filter part produces a magnetic flux having a direction opposite to a magnetic flux produced by the first current flowing through the series connected one coil of the second filter part,
another of the upper and lower coils of the first filter part is electrically connected in series with another of the upper and lower coils of the second filter part such that a second current flowing in the other coil of the first filter part produces a magnetic flux having a direction opposite to a magnetic flux produced by the second current flowing through the series connected other coil of the second filter part, and
a distance between the coil windings in each of the upper and lower coils of the first filter part is smaller than a distance between the coil windings in each of the upper and lower coils of the second filter part.

US Pat. No. 10,116,279

IMPEDANCE MATCHING FOR INDUCTIVE POWER TRANSFER SYSTEMS

Apple Inc., Cupertino, C...

1. An electromagnetic induction power transfer apparatus comprising:an inductive power transmitter, comprising:
a power supply with an active state and an inactive state, configured to switch between the active state and the inactive state at a selectable duty cycle; and
a power-transmitting inductor coupled to the power supply; and
an inductive power receiver, comprising:
a power-receiving inductor, positioned inductively proximate the power-transmitting inductor;
a programmable load; and
an impedance controller coupled to the power receiving inductor and configured to increase or decrease an electrical impedance of the inductive power receiver in response to a change in a power requirement of the programmable load, the impedance controller comprising a synchronous bridge rectifier comprising:
an oscillator having a controllable duty cycle; and
a plurality of switches, each switchable at least in part in response a voltage polarity of the power-receiving inductor and a voltage magnitude of the oscillator.

US Pat. No. 10,116,278

ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. An electronic component comprising:a substrate;
a capacitor lower electrode disposed on the substrate;
a purely inorganic dielectric layer disposed on the substrate to cover the capacitor lower electrode;
a capacitor upper electrode disposed directly on the purely inorganic dielectric layer and facing the capacitor lower electrode via the purely inorganic dielectric layer; and
a coil electrically connected to the capacitor lower electrode or the capacitor upper electrode, wherein
a portion of the purely inorganic dielectric layer covers an upper surface of the capacitor lower electrode and extends over an edge of the capacitor lower electrode and downward along a side of the capacitor lower electrode, an upper surface of an entirety of the portion is flat.

US Pat. No. 10,116,277

RADIO FREQUENCY POWER AMPLIFIER

NATIONAL CHI NAN UNIVERSI...

1. A radio frequency (RF) power amplifier comprising:a number (N) of amplifying stages, each receiving a respective RF input signal and outputting a respective RF output signal, where N?1;
when N?2, said amplifying stages being cascaded, and the respective RF output signal outputted by an nth one of said amplifying stages serving as the respective RF input signal received by an (n+1)th one of said amplifying stages, where 1?n?(N?1);
each of first to Mth ones of said amplifying stages including
a first amplifying module receiving a first RF to-be-amplified signal, and performing power amplification on the first RF to-be-amplified signal to generate the respective RF output signal and an RF inverted signal that is anti-phase with the first RF to-be-amplified signal,
an input module coupled to said first amplifying module, and receiving the respective RF input signal, and
a feedback module coupled to said first amplifying module and said input module, and receiving the respective RF output signal from said first amplifying module, said feedback module cooperating with said input module to provide, based on the respective RF input signal and the respective RF output signal, the first RF to-be-amplified signal for said first amplifying module, said feedback module cooperating with said first amplifying module to form a positive feedback loop that provides a loop gain which is less than one, a portion of the first RF to-be-amplified signal that is contributed by the respective RF output signal being anti-phase with the RF inverted signal,
where 1?M?N;
for each of said first to Mth ones of said amplifying stages, said first amplifying module including:
a transistor having a first terminal that provides the RF inverted signal, a second terminal that is grounded, and a control terminal that is coupled to said input module and said feedback module for receiving the first RF to-be-amplified signal therefrom;
a first inductor having a first terminal that is coupled to said feedback module and that provides the respective RF output signal, and a second terminal that is coupled to said first terminal of said transistor; and
a second inductor having a first terminal that is used to receive a supply voltage, and a second terminal that is coupled to said first terminal of said first inductor.

US Pat. No. 10,116,276

POWER AMPLIFIER CIRCUIT

National Chi Nan Universi...

1. A radio frequency (RF) power amplifier circuit comprising:a power divider disposed to receive an RF input signal, and configured to divide the RF input signal into more than three RF division signals;
a plurality of power amplification circuits coupled to said power divider for respectively receiving the RF division signals, each of said power amplification circuits being configured to perform power amplification on a respective one of the RF division signals, and to output a respective one of amplified RF division signals; and
a power combiner coupled to said power amplification circuits for receiving the amplified RF division signals, and configured to combine the amplified RF division signals into an RF output signal;
wherein one of said power divider and said power combiner has a first microstrip structure,
said RF power amplifier circuit further comprising a first impedance conversion circuit that has
a first terminal coupled to said one of said power divider and said power combiner that has said first microstrip structure, and
a second terminal that is disposed to receive the RF input signal when said first terminal is coupled to said power divider, and that is disposed to output the RF output signal when said first terminal is coupled to said power combiner,
said first impedance conversion circuit being configured to permit transmission of one of the RF input signal and the RF output signal between said first and second terminals thereof, and being configured such that a first conversion impedance, which is an impedance seen into said first impedance conversion circuit from said first terminal, matches an impedance seen into said one of said power divider and said power combiner from said first terminal; and
wherein said first microstrip structure has a physical length associated with the first conversion impedance,
said RF power amplifier circuit satisfying:

where:
N represents a number of the RF division signals,
?TE represents an equivalent electrical length of said first microstrip structure,
YTE represents an equivalent characteristic transconductance of said first microstrip structure,
? represents an angular frequency of the RF input signal,
?T represents the physical length of said first microstrip structure,
ZL represents the first conversion impedance;
RL represents a real part of ZL,
LL represents an imaginary part of ZL,
Zx represents an impedance seen into said first microstrip structure from a terminal of said first microstrip structure to which one of said power amplification circuits is coupled,
Rx represents a real part of Zx,
Lx represents an imaginary part of Zx, and
? represents a wavelength of the RF input signal.

US Pat. No. 10,116,275

PHYSICAL QUANTITY DETECTION CIRCUIT, PHYSICAL QUANTITY DETECTION DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

Seiko Epson Corporation, ...

1. A physical quantity detection circuit comprising:a switched capacitor filter circuit having a first sample-and-hold circuit adapted to sample and hold a first signal, which is based on an output signal of a physical quantity detection element, an amplifier circuit to which an output signal of the first sample-and-hold circuit is input, and a first switched capacitor circuit to which a first output signal of the amplifier circuit is input, wherein an output signal of the first switched capacitor circuit is input to the amplifier circuit; and
an A/D conversion circuit adapted to perform an A/D conversion on an output signal of the switched capacitor filter circuit,
wherein the A/D conversion circuit performs the A/D conversion on a plurality of signals including an output signal of the switched capacitor filter circuit in a time-sharing manner.

US Pat. No. 10,116,274

PROCESS-COMPENSATED HBT POWER AMPLIFIER BIAS CIRCUITS AND METHODS

Skyworks Solutions, Inc.,...

1. A system for biasing a power amplifier, the system comprising:a power amplifier circuit including a transistor, the transistor including a stack of layers formed on a semiconductor;
an integrated resistor formed as a layer stack device including a plurality of differently doped layers on the semiconductor that includes the transistor, the integrated resistor configured to sense a beta parameter of the power amplifier circuit, the beta parameter dependent on characteristics of the semiconductor and corresponding to a direct current gain; and
a biasing circuit configured to bias the transistor of the power amplifier circuit based at least in part on a measurement of the beta parameter sensed by the integrated resistor.

US Pat. No. 10,116,273

CURRENT REUSE FIELD EFFECT TRANSISTOR AMPLIFIER

Mitsubishi Electric Corpo...

1. A current reuse field effect transistor amplifier comprising:a first field effect transistor including a first gate to which a radio frequency (RF) signal is input, a first source, and a first drain;
a first resistor connected between the first source and a terminal for grounding;
a second field effect transistor including a second source, a second gate connected to the first drain, and a second drain that is connected to a terminal for power supply and outputs the RF signal;
a second resistor connected between the second source and the second gate;
a third field effect transistor including a third source, a third drain connected to the terminal for power supply, and a third gate connected to the terminal for grounding;
a fourth field effect transistor including a fourth source, a fourth drain, and a fourth gate connected to the third source;
one or a plurality of diodes connected in series between the fourth source and the terminal for grounding;
a third resistor connected between the terminal for power supply and the fourth drain; and
a fourth resistor connected between the fourth drain and the first gate,whereinthe first to the fourth field effect transistors are each a depletion mode field effect transistor.

US Pat. No. 10,116,272

VARIABLE IMPEDANCE MATCH AND VARIABLE HARMONIC TERMINATIONS FOR DIFFERENT MODES AND FREQUENCY BANDS

pSemi Corporation, San D...

1. An arrangement configured to receive and amplify a first signal, the arrangement comprising:an amplifier having an amplifier output terminal, wherein, during operation of the arrangement, the amplifier generates a second signal by amplifying the first signal;
a first harmonic termination arrangement comprising a first set of one or more harmonic terminations operatively connected in series;
a second harmonic termination arrangement comprising a second set of one or more harmonic terminations operatively connected in series; and
a switching arrangement;
wherein:
the switching arrangement is configured to selectively provide a conduction path of the second signal through one of the first set and the second set of one or more harmonic terminations operatively connected in series; and
each of the first set and the second set of one or more harmonic terminations is configured to resonate at a corresponding harmonic resonant frequency.

US Pat. No. 10,116,271

CURRENT-TO-VOLTAGE CONVERTER, AMPLIFIER INPUT STAGE AND CORRESPONDING AMPLIFIER

Devialet, Paris (FR)

1. A current-to-voltage converter, the input current having a variable component, the converter comprising:an input for the current to be converted;
an output for the converted voltage;
a current-to-voltage conversion resistance connected to the output and to a reference potential;
a processing circuit comprising:
a voltage source;
a main branch comprising at least one transistor whose gate is connected to the voltage source and at least one current source connected in series with the transistor, the input being connected to the output via the transistor;
a twin circuit comprising:
a voltage source that is identical to the voltage source of the processing circuit;
a twin branch that is identical to the main branch of the processing circuit;
a voltage follower that is connected at the input to the main branch of the processing circuit and connected at the output to the twin branch of the twin circuit, and
current reinjection means for reinjecting the current at the output of the follower into the main branch of the processing circuit, wherein the voltage follower comprises a first output for conveying a current to the twin circuit and a second output for reinjecting a current, equal to the current originating from the first output, into the main branch of the processing circuit, the converter being fabricated on a substrate.

US Pat. No. 10,116,270

TUNABLE POWER AMPLIFIER WITH WIDE FREQUENCY RANGE

TEXAS INSTRUMENTS INCORPO...

1. A circuit comprising:an amplifier to amplify an input signal and generate an output signal; and
a tuning network to tune a frequency response of the amplifier, the tuning network comprising at least one tunable microelectromechanical system (MEMS) capacitor, the at least one tunable MEMS capacitor comprising a MEMS superstructure disposed over a control structure, the control structure being arranged to control the MEMS superstructure and tune a capacitance of the at least one tunable MEMS capacitor, the control structure comprising an electrode, and the MEMS superstructure comprising at least one substantially planar membrane positioned parallel to the electrode.

US Pat. No. 10,116,269

DIFFERENTIAL AMPLIFIER WITH EXTENDED BANDWIDTH AND THD REDUCTION

INPHI CORPORATION, Santa...

1. A system comprising:an amplifier device comprising:
a first transistor comprising a first base terminal and a first collector terminal, the first base terminal being coupled to a first input;
a second transistor comprising a second base terminal and a second collector terminal, the second terminal base being coupled to a second input;
a first peaking inductor coupled to the first collector terminal;
a second peaking inductor coupled to the second collector terminal;
a third transistor comprising a third base terminal and a first emitter terminal, the first emitter terminal being coupled to the first peaking inductor;
a fourth transistor comprising a fourth base terminal and a second emitter terminal, the second emitter terminal being coupled to the second peaking inductor; and
a degeneration resistor coupled to the third base terminal and the fourth base terminal; and
a output proportional to an input, and the output coupled to the amplifier device.

US Pat. No. 10,116,268

OPERATIONAL AMPLIFIER

Analog Devices Global, H...

1. An amplifier circuit that generates an output voltage comprising a relatively constant offset voltage, the amplifier circuit comprising:an output stage configured to generate the output voltage;
first and second differential input stages coupled to the output stage, wherein the first differential input stage includes a pair of first input transistors and the second differential input stage includes a pair of second input transistors complementary in type to the first input transistors;
a switching network configured to couple a differential input signal to the first differential input stage and a reference voltage to the second differential input stage in response to a control signal having a first state, and to couple the differential input signal to the second differential input stage and the reference voltage to the first differential input stage in response to the control signal having a second state; and
a comparator configured to generate the control signal based on comparing a signal level of the differential input signal to a threshold signal.

US Pat. No. 10,116,267

SINGLE-ENDED AMPLIFIER CIRCUIT WITH IMPROVED CHOPPER CONFIGURATION

STMicroelectronics S.r.l....

1. An amplifier circuit, comprising:an input stage, of a differential type, coupled to a first differential input and to a second differential input between which, in use, a differential input voltage is present;
a converter stage coupled to said input stage and configured to convert said differential input voltage into a single-ended converted voltage;
an output stage coupled to said converter stage and configured to generate, starting from said single-ended converted voltage, an output voltage on a single output;
a biasing stage, operatively coupled to said input stage and to said output stage for supplying a biasing current; and
a chopper module configured to reduce a contribution of offset and noise associated to said output voltage, wherein said chopper module includes:
an input chopper stage coupled to said input stage;
a converter chopper stage coupled to said converter stage and configured to generate said single-ended converted voltage; and
a biasing chopper stage coupled to said biasing stage and configured to generate said biasing current.

US Pat. No. 10,116,266

DOHERTY AMPLIFIER

KABUSHIKI KAISHA TOSHIBA,...

1. A method for determining circuit parameters of a Doherty amplifier comprising: an input terminal; an output terminal; a splitter connected to the input terminal, the splitter having first and second outputs; a combiner connected to the output terminal, the combiner having first and second inputs; a carrier amplifier including a first input-side two-port network connected to the first output of the splitter, a first amplifier connected to an output of the first input-side two-port network, and a first output-side two-port network connected between an output of the first amplifier and the first input of the combiner; and a peak amplifier including a second input-side two-port network connected to the second output of the splitter, a second amplifier connected to the output of the second input-side two-port network, and a second output-side two-port network connected between an output of the second amplifier and the second input of the combiner,wherein the method comprises:
determining circuit parameters of the output-side two-port network of the carrier amplifier and the output-side two-port network of the peak amplifier so that the combiner is a parallel-connected load type having a parallel connection of the output-side two-port network of the carrier amplifier and the output-side two-port network of the peak amplifier for the output terminal at the combining point, and that a load admittance at the combining point is expressed using a complex number;
wherein if the load admittance at the combining point is YL?, the circuit parameters of the output-side two-port network from the current source end of the carrier amplifier up to the combining point are Fc (Ac, Cc, Cc, Dc), the circuit parameters of the output-side two-port network from the current source end of the peak amplifier up to the combining point are Fp (Ap, Bp, Cp, Dp), the load resistance of the carrier amplifier in the state in which it is not backed off is Roptc, the load resistance of the peak amplifier in the state in which it is not backed off is Roptp, m=1+Roptc/Roptp, and the phase difference between the phase of the current source of the carrier amplifier and the phase of the current source of the peak amplifier is ?, within a transmission frequency band, the relationships:
(Ac×Dp+Bc×Cp+Bc×Dp×YL?)/(Cc×Dp+Cp×Dc+Dc×Dp×YL?)=m×Roptc  (1)
?c/(Cc×Dp+Cp×Dc+Dc×Dp×YL?)=?Roptc×ej×?  (2)
?p/(Cc×Dp+Cp×Dc+Dc×Dp×YL?)=Roptc×e?j×?  (3)
(Ap×Dc+Bp×Cc+Bp×Dc×YL?)/(Cc×Dp+Cp×Dc+Dc×Dp×YL?)=0  (4)
are satisfied, wherein ?c=Ac×Dc?Bc×Cc and ?p=Ap×Dp?Bp×Cp.

US Pat. No. 10,116,265

MODULAR AND SCALABLE POWER AMPLIFIER SYSTEM

Telefonaktiebolaget LM Er...

1. A modular power amplifier system for receiving an input signal and providing output signals with scalable output power, wherein the modular power amplifier system comprises:a plurality of amplifier modules, each amplifier module comprises an input port and an output port, and wherein the plurality of amplifier modules are arranged into a number of sections comprising:
a first section which comprises a first amplifier module, among the plurality of amplifier modules, configured to receive the input signal within a first amplitude range and provide an output signal having a first output power;
a second section which comprises a second amplifier module, among the plurality of amplifier modules, configured to receive the input signal within a second amplitude range and provide an output signal having a second output power; and
an i-th section which comprises multiple amplifier modules, among the plurality of amplifier modules, each being configured to receive the input signal within a certain amplitude range and provide an output signal having a certain output power, and wherein
the output signal of the first amplifier module is combined with the output signal of the second amplifier module and the output signal of each amplifier module in the -th section is split and each split output signal is combined with the respective output signal of the amplifier modules in the i-th section, wherein i=3, 4, . . . .

US Pat. No. 10,116,264

CALIBRATING A POWER AMPLIFIER SUCH AS IN A REMOTE UNIT IN A WIRELESS DISTRIBUTION SYSTEM (WDS)

Corning Optical Communica...

1. A power amplifier calibration circuit, comprising:a power amplifier comprising a signal input, a signal output, a first bias signal input, and a second bias signal input, wherein the power amplifier is configured to:
receive an input signal having a first power at the signal input;
receive a first bias signal at the first bias signal input;
receive a second bias signal at the second bias signal input;
amplify the input signal to generate an output signal having a second power higher than the first power at the signal output; and
control a first power amplifier performance parameter and a second power amplifier performance parameter in the output signal based on the first bias signal and the second bias signal; and
a control circuit configured to:
provide a plurality of bias signal combinations to the power amplifier, wherein each of the plurality of bias signal combinations comprises a respective first bias signal and a respective second bias signal to be provided to the first bias signal input and the second bias signal input of the power amplifier, respectively;
receive a plurality of performance indication signals comprising a plurality of measurements corresponding to the plurality of bias signal combinations, respectively, wherein each of the plurality of measurements comprises the first power amplifier performance parameter and the second power amplifier performance parameter;
rank the plurality of measurements based on a predefined ranking criteria; and
determine a selected bias signal combination among the plurality of bias signal combinations corresponding to a selected ranked measurement among the plurality of measurements.

US Pat. No. 10,116,263

METHOD AND DEVICE FOR TIA OVERLOAD CONTROL IN LOW POWER APPLICATIONS

INPHI CORPORATION, Santa...

1. A transimpedance amplifier (TIA) device comprising:a semiconductor substrate;
a TIA configured on the semiconductor substrate, the TIA comprising an input terminal and an output terminal; and
an overload buffer module coupled to the input terminal of the TIA, the overload buffer module comprising:
a variable current source having an input and an output, and
a biased buffer diode coupled to the output of the variable current source;
wherein the biased buffer diode is coupled to a ground node; and
wherein the variable current source is configured as a control source to replicate a DC signal at the output.

US Pat. No. 10,116,262

FRONT-END AMPLIFIER CIRCUITS FOR BIOMEDICAL ELECTRONICS

WINBOND ELECTRONICS CORP....

1. A front-end amplifier circuit for receiving a biological signal, comprising:a signal channel, amplifying the biological signal to generate a detection current, wherein the signal channel comprises:
a capacitive-coupled transconductance amplifier, amplifying the biological signal with a transconductance gain to generate a first current; and
a band-pass filtering amplifier, filtering noise in the first current outside a bandwidth and amplifying the first current with a first current gain to generate a second current;
a programmable-gain amplifier, amplifying the second current with a second current gain to generate the detection current on a programmable-gain output node, wherein the second current gain is programmable; and
an offset cancellation circuit, configured to cancel output offset currents of the capacitive-coupled transconductance amplifier, the band-pass filtering amplifier, and the programmable-gain amplifier.

US Pat. No. 10,116,261

OSCILLATOR CIRCUIT

KABUSHIKI KAISHA TOSHIBA,...

1. An oscillator circuit comprising:a resonant circuit; and
first and second negative-resistance circuits,
wherein each of the first and second negative-resistance circuits includes a first power-supply terminal, a second power-supply terminal, an input terminal and an output terminal, and the first and second negative-resistance circuits are connected in series between a first power supply and a second power supply at the first and second power-supply terminals, and connected parallel to the resonance circuit at the input and output terminals, and
wherein each of the first and second negative-resistance circuits comprises a first transistor of a first conductivity type which includes a first current path and a first gate electrode, the first current path of the first transistor being located between the first power supply terminal and the second power supply terminal, and
an intermediate voltage is supplied to the first gate electrode of the first transistor, the intermediate voltage is a voltage between a voltage at the first power supply terminal and a voltage at the second power supply terminal.

US Pat. No. 10,116,260

VCO SELECTION AND AMPLITUDE MANAGEMENT USING CENTER TAP INDUCTOR

International Business Ma...

1. An apparatus comprising:a first voltage controlled oscillator (VCO) that includes a first inductor, a first varactor, a first transistor, and a second transistor, wherein the first inductor is coupled to the first varactor, the first transistor and the second transistor; wherein the first inductor includes a first center tap connection; and wherein a center tap voltage at the first center tap connection affects an oscillation of the first VCO;
a second VCO that includes a second inductor having a second center tap connection, a pair of transistors coupled to the second inductor, and a second varactor;
an operational amplifier, wherein an output of the operational amplifier is coupled to the first center tap connection of the first inductor;
a first multiplexer receiving an output from the operational amplifier, the first multiplexer coupled to the first and second center tap connections; and
a second multiplexer providing an input to the operational amplifier, the second multiplexer coupled to the first and second center tap connections,
wherein a selection signal is used to select between the second VCO and the first VCO.

US Pat. No. 10,116,259

INDUCTOR-ENCLOSED VOLTAGE-CONTROLLED OSCILLATORS

QUALCOMM Incorporated, S...

1. A frequency synthesizer, comprising:a first voltage-controlled oscillator (VCO) circuit comprising a first inductor; and
a second VCO circuit comprising a second inductor, wherein at least a portion of the first VCO circuit is disposed inside a loop of the second inductor, wherein at least a portion of the second VCO circuit is disposed inside a loop of the first inductor, wherein the portion of the first VCO circuit comprises a negative active transconductance circuit and a varactor of the first VCO circuit, and wherein the portion of the second VCO circuit comprises a negative active transconductance circuit and a varactor of the second VCO circuit.

US Pat. No. 10,116,258

TEMPERATURE-STAGED THERMAL ENERGY STORAGE ENABLING LOW THERMAL EXERGY LOSS REFLUX BOILING IN FULL SPECTRUM SOLAR ENERGY SYSTEMS

CALIFORNIA INSTITUTE OF T...

1. A structure comprising:a photovoltaic module;
a reflux boiling chamber configured to store thermal energy, the reflux boiling chamber comprising a plurality of temperature staged thermal energy storage materials, each temperature staged thermal energy storage material comprising a porous phase change material and configured to operate at a different temperature range than the other temperature staged thermal energy storage materials in the plurality of temperature staged thermal energy storage materials, the reflux boiling chamber further configured to contain a working fluid;
a thermoacoustic heat engine;
an alternator connected to the thermoacoustic heat engine; and
a solar concentrator configured to concentrate sunlight towards the photovoltaic module and the reflux boiling chamber,
wherein the reflux boiling chamber is further configured to transfer the thermal energy to the thermoacoustic heat engine through the working fluid by cycling the working fluid between a liquid phase and a vapor phase.

US Pat. No. 10,116,257

ENHANCED SOLAR PANELS, LIQUID DELIVERY SYSTEMS AND ASSOCIATED PROCESSES FOR SOLAR ENERGY SYSTEMS

Accurate Solar Power, LLC...

1. A liquid distribution system for a power generation system comprising a plurality of solar panels, comprising:a server;
a delivery mechanism for distributing a liquid over the outer surface of at least a portion of the solar panels;
a liquid delivery controller associated with the delivery mechanism; and
a plurality of panel controllers, wherein each of the panel controllers is associated with a corresponding solar panel and is configured to track one or more operating parameters for the corresponding solar panel, and to send a data signal to the server, wherein the data signal corresponds to the tracked parameters;
wherein the server is configured to monitor temperature of one or more of the solar panels based upon the received data signals, and to send a control signal to the liquid delivery controller when the monitored temperature exceeds a temperature setpoint; and
wherein the liquid delivery controller is configured to activate the delivery mechanism in response to the control signal.

US Pat. No. 10,116,256

PHOTOVOLTAIC MODULES WITH CORNER JUNCTION BOXES AND ARRAY OF THE SAME

SolarCity Corporation, S...

1. A photovoltaic array, comprising:a plurality of photovoltaic modules arranged in an array, each photovoltaic module having a positive-voltage junction box being positioned at a first corner of an underside of the photovoltaic module and a negative-voltage junction box being positioned at a second corner on the underside of the photovoltaic module;
wherein each photovoltaic module comprises:
a plurality of photovoltaic cells arranged within a frame and located on an upper side of the photovoltaic module;
the positive-voltage junction box being electrically connected to the plurality of photovoltaic cells by a first electrical ribbon;
the negative-voltage junction box being electrically connected to the plurality of photovoltaic cells by a second electrical ribbon; and
the positive-voltage junction box and the negative-voltage junction box being directly electrically connected to each other by an electrical conduit;
wherein the array comprises a first row of photovoltaic modules electrically connected to each other and each photovoltaic module of the first row being oriented in a first direction; and
wherein the array comprises a second row of photovoltaic modules electrically connected to each other and each photovoltaic module of the second row being oriented in a second direction that is 180° opposite relative to the first direction, and wherein one photovoltaic module of the first row is electrically connected to one photovoltaic module of the second row.

US Pat. No. 10,116,255

CLEANING SYSTEM FOR SOLAR PANELS

SOLAR MAID OF NORTHERN AR...

1. An apparatus for cleaning a solar panel, the apparatus comprising:a brush body having a width approximately equal to the solar panel;
a plurality of brush heads each attached to the brush body and having bristles extending away from the brush body, the bristles of each of the plurality of brush heads cooperating to form a contact plane where the bristles contact the solar panel;
a fluid manifold attached to the brush body, the fluid manifold comprising one or more pipes interconnecting a plurality of bulkheads, the plurality of bulkheads comprising:
a hose bulkhead that connects to a hose to establish fluid communication between the fluid manifold and a fluid supply; and
a plurality of nozzle bulkheads in fluid communication with the hose bulkhead; and
a plurality of nozzles each connected to one of the plurality of nozzle bulkheads such that each nozzle bulkhead has attached thereto:
a corresponding forward-facing nozzle of the plurality of nozzles, the corresponding forward-facing nozzle extending beyond a front edge of the brush body and emitting pressurized fluid onto the solar panel; and
a corresponding rear-facing nozzle of the plurality of nozzles, the corresponding rear-facing nozzle extending beyond a rear edge of the brush body and emitting pressurized fluid onto the solar panel.

US Pat. No. 10,116,254

SOLAR-POWERED VENDING MACHINE AND RELATED APPARATUS AND METHODS

1. A solar-powered vending machine comprising:a vending machine; and
a photovoltaic (PV) panel assembly connected to the vending machine having a top and a plurality of sides extending downwardly therefrom, the PV panel assembly including:
a panel subassembly having a plurality of foldably interconnected PV panels to expand to a deployed width greater than a vending machine width and collapse to a stowed width less than or approximately equal to the vending machine width; and
a mounting subassembly connecting the panel subassembly to the vending machine and supporting the plurality of foldably interconnected PV panels for movement between a deployed position, in which the plurality of foldably interconnected PV panels are supported above the top of the vending machine unfolded to the deployed width for sun exposure, and a stowed position, in which the plurality of foldably interconnected PV panels extend downwardly adjacent one of the sides of the vending machine folded to the stowed width;
wherein, in the deployed position, at least one of the plurality of foldably interconnected PV panels is supported directly above the top of the vending machine;
wherein the mounting subassembly comprises at least one first mounting arm and at least one second mounting arm extending between the vending machine and the panel subassembly;
wherein the at least one first mounting arm includes a pair of first mounting arms and the at least one second mounting arm includes a pair of second mounting arms; and
wherein respective machine ends of each of the pair of first mounting arms are pivotably mounted to the top of the vending machine about a first pivot axis, and respective machine ends of each of the pair of second mounting arms are pivotably mounted about a second pivot axis to the one of the sides of the vending machine down which the plurality of foldably interconnected PV panels extend in the stowed position.

US Pat. No. 10,116,253

SOLAR POWER GENERATING DEVICE

LG INNOTEK CO., LTD., Se...

1. A solar power generating device comprising:solar cell modules arrange as a plurality of rows and columns; and
an inclination control member to control inclination angles of the solar cell modules at a time,
wherein the inclination control member comprises:
a support unit to support the solar cell modules;
a control unit disposed on the support unit to control the inclination angles of the solar cell modules; and
a driving unit to operate the control unit,
wherein the solar cell module includes a silicon-based solar cell,
wherein the support unit includes a rail,
one end of the control unit is coupled to the support unit and an opposite end of the control unit is coupled to the solar cell module, and
one end of the solar cell module is coupled to the support unit and an opposite end of the solar cell module is coupled to the control unit,
wherein the control unit includes a first rotational unit coupled to the support unit, and
the solar cell module includes a second rotational unit coupled to the support unit,
the solar power generating device further comprising a third rotational unit to connect the solar cell module to the control unit.

US Pat. No. 10,116,252

METHOD AND APPARATUS FOR EFFICIENT SOLAR POWER COLLECTION

1. A method of seasonally positioning a solar panel, comprising: providing a mounted solar panel moveable between a horizontal position and an angled tracking position, wherein the mounted solar panel is connected to a frame or stand by a moveable joint mechanism, wherein one panel axis is fixed to face in a direction toward the equator,maintaining the solar panel in a fixed and non-tracking horizontal position for a predetermined number of days of a year; and
positioning the solar panel in at least one angled position at an angle to the horizontal position for a remaining number of days of the year, wherein the mounted solar panel is controlled electromechanically or manually, and the mounted solar panel is balanced against wind and snow loading, and the predetermined number of days comprises at least 80 days centered on the summer solstice.

US Pat. No. 10,116,251

MOTOR DRIVE DEVICE AND MOTOR DRIVING METHOD

FANUC CORPORATION, Yaman...

1. A motor drive device that supplies electric power from a power element to a motor and dissipates heat from the power element by way of a heat sink, the motor drive device comprising:a temperature detection unit that detects an actual temperature of the heat sink;
an electric current detection unit that detects electric current from the power element to the motor;
an actual temperature variation calculation unit that calculates an actual temperature variation of the heat sink relative to time, from the actual temperature of the heat sink detected by the temperature detection unit;
an estimated temperature variation calculation unit that calculates an estimated temperature variation of the heat sink relative to time, from an estimated temperature of the heat sink calculated based on the electric current detected by the electric current detection unit; and
a temperature abnormality determination unit that determines existence of a temperature abnormality in the heat sink, according to whether or not the actual temperature variation calculated by the actual temperature variation calculation unit is departing from a permitted range based on the estimated temperature variation calculated by the estimated temperature variation calculation unit.

US Pat. No. 10,116,250

AC-ROTARY-MACHINE CONTROL DEVICE AND ELECTRIC POWER-STEERING SYSTEM PROVIDED WITH AC-ROTARY-MACHINE CONTROL DEVICE

Mitsubishi Electric Corpo...

1. A controller for an AC rotary machine, which is configured to control the AC rotary machine based on an estimated resistance value of the AC rotary machine, the controller comprising:a temperature detector configured to detect an external temperature of the AC rotary machine, and to output the detected external temperature;
a resistance value estimator to estimate, based on the detected external temperature, an actual resistance value of the AC rotary machine, which changes depending on temperature of the AC rotary machine, and to output the estimated resistance value; and
a voltage supply configured to apply a voltage to an AC rotary machine based on the estimated resistance value,
wherein the resistance value estimator calculates a basic estimated resistance value, which is a sum of a first resistance value defined as a fixed value and a second resistance value that is proportional to the detected external temperature, and to calculate the estimated resistance value by adding an estimated resistance correction value to the basic estimated resistance value,
wherein the estimated resistance correction value comprises a negative value having an absolute value that is larger than a difference between a lower limit value of a resistance value error allowable range and a deviation estimate, and is smaller than an absolute value of the deviation estimate,
wherein the deviation estimate is a value set in advance as a lower limit of a range that is taken by a deviation obtained by subtracting the basic estimated resistance value from the actual resistance value, and
wherein the resistance value error allowable range comprises a range of a resistance value error that enables the AC rotary machine to be rotated smoothly.