US Pat. No. 10,924,246

METHOD FOR INSTRUCTING CSI FEEDBACK SIGNALING CONFIGURATION AND BASE STATION

1. A method for instructing CSI feedback signaling configuration, comprising:a base station notifying a terminal, via a first higher layer signaling, one or more CSI-RS resources for measuring CSI, wherein the higher layer is a layer higher than a physical layer in an open system interconnection (OSI) layer model, wherein the CSI-RS resources comprises at least one of:
corresponding time frequency positions of the CSI-RS resources in a respective subframe, a number of ports configuration of the CSI-RS resources, a periodicity and a subframe offset of the CSI-RS resources, a sequence identifier of the CSI-RS resources, and power control information of the CSI-RS resources; and
the base station instructing the terminal to feed back the CSI corresponding to the one or more CSI-RS resources;
wherein the step of the base station instructing the terminal to feed back the CSI corresponding to the one or more CSI-RS resources comprises:
the base station dynamically instructing, through a physical layer signaling, the terminal to select and feedback corresponding CSI based on feedback triggering signaling bits configured for one or more DCI Formats, and based on the DCI Format used in a resource position where DCI carrying the feedback triggering signaling bits in the DCI Format is located;
wherein the feedback triggering signaling bits in the DCI are 1 or more bits, where 0 state represents no CSI of any CSI-RS resource is triggered, and each of the rest of states respectively represents triggering CSI of one of multiple combinations of the CSI-RS resources and/or interference measurement resources (IMR) of the CSI;
wherein at least one of the multiple combinations of the CSI-RS resources and interference measurement resources is combination of multiple CSI-RS resources and interference measurement resources located in a single carrier for aggregated CSI feedback;
wherein before the step of the base station instructing the terminal to feed back the CSI corresponding to the one or more CSI-RS resources and interference measurement resources, the method further comprising: the base station notifying the terminal, via a second higher layer signaling, a candidate configuration set of CSIs for CSI feedback based on the CSI-RS resources and interference measurement resources, wherein the candidate configuration set indicates the one or more CSI-RS resources and interference measurement resources for measuring CSI.

US Pat. No. 10,924,245

DMRS DESIGN FOR SPS ASSIGNED TRAFFIC

QUALCOMM Incorporated, S...

1. A method for wireless communication, comprising:receiving, at a user equipment (UE), a demodulation reference signal (DMRS) during a semi-persistent scheduling (SPS) slot;
selecting a DMRS sequence from a plurality of DMRS sequences in order to detect the DMRS, wherein the selection of the DMRS sequence is based on one of a slot offset value or a type of traffic; and
determining whether a packet transmitted during the SPS slot is intended for the UE based on detecting the DMRS using the selected DMRS sequence,
wherein the selecting the DMRS sequence from the plurality of DMRS sequences based on the slot offset value comprises:
identifying an assigned SPS slot allocated to the UE by a base station, with the UE scheduled to receive a periodic packet from the base station during the assigned SPS slot;
determining the slot offset value for the UE based on identification of a difference between the SPS slot and the assigned SPS slot that is allocated to the UE; and
selecting the DMRS sequence based on the slot offset value.

US Pat. No. 10,924,244

CHANNEL STATE INFORMATION FEEDBACK METHOD AND APPARATUS

Huawei Technologies Co., ...

1. A channel state information (CSI) feedback method, the method comprising:sending, by a network device, a configuration message to a user equipment, wherein the configuration message comprises information about a physical uplink control channel resource configured for feeding back channel station information (CSI) of the user equipment, the physical uplink control channel resource comprising two physical resource block (PRB) pairs, each PRB pair comprising two PRBs distributed in two timeslots, the two PRBs being configured to transmit a physical uplink control channel, and each of the timeslots comprising one of the two PRBs, wherein the information about the physical uplink control channel resource indicates whether the two timeslots are two same consecutive timeslots or two different consecutive timeslots; and
receiving, by the network device, the CSI sent by the user equipment on the physical uplink control channel resource.

US Pat. No. 10,924,243

CHANNEL IDENTIFICATION IN A MIMO TELECOMMUNICATIONS SYSTEM

CommScope Technologies LL...

1. A channel identification system for a MIMO telecommunication system wirelessly communicating with terminal devices, comprising:an interface device configured to receive downlink signals on channels corresponding to a first port and a second port of a base station; and
a processing device, wherein the processing device is configured to:
synchronously capture samples of the downlink signals received from the base station;
determine a first cell-specific reference signal and a second cell-specific reference signal based on the samples; and
determine a channel identification corresponding to at least one channel of the channels by correlating the first cell-specific reference signal and the second cell-specific reference signal.

US Pat. No. 10,924,240

SOUNDING REFERENCE SIGNAL TRANSMISSION TO INDICATE A VIRTUAL ANTENNA PORT

QUALCOMM Incorporated, S...

1. A method of wireless communication performed by a user equipment (UE), comprising:transmitting a sounding reference signal (SRS) on a plurality of antenna ports mapped to a first SRS resource of an SRS resource set for the UE to use to transmit the SRS to a base station; and
transmitting the SRS on one or more virtual antenna ports mapped to a second SRS resource of the SRS resource set,
a quantity of the one or more virtual antenna ports mapped to the second SRS resource being different from a quantity of the plurality of antenna ports mapped to the first SRS resource.

US Pat. No. 10,924,237

DEMODULATION REFERENCE SIGNAL CONFIGURATION IN A MULTI-INPUT MULTI-OUTPUT WIRELESS COMMUNICATION SYSTEM

Qualcomm Incorporated, S...

1. A method of wireless communication at a base station, comprising:allocating a first set of uplink resources for multi-input multi-output (MIMO) communication and a second set of uplink resources for MIMO communication to a first user equipment (UE), the first set of uplink resources being in a first slot corresponding to a first transmission time interval (TTI), the second set of uplink resources being in a second slot, the first slot and the second slot being different slots within a single subframe;
allocating a third set of uplink resources for MIMO communication to a second UE to maintain demodulation reference signal (DM-RS) orthogonality between the first UE and the second UE within the single subframe, the third set of uplink resources being in the first slot and the second slot within the single subframe corresponding to a second TTI, the first TTI and the second TTI being different; and
transmitting to the first UE, information indicating whether to transmit a DM-RS in the second slot that is a same DM-RS as to be transmitted in the first slot or to transmit in the DM-RS in the second slot as a negative of the DM-RS to be transmitted in the first slot, wherein the information further indicates a slot format of a slot designated for DM-RS transmission and an application of an orthogonal cover code (OCC) to effectively maintain the DM-RS orthogonality between the first UE and the second UE within the single subframe.

US Pat. No. 10,924,236

RESOURCE MAPPING METHOD, TRANSMIT END, AND RECEIVE END

Huawei Technologies Co., ...

1. A resource mapping method, comprising:obtaining, by a transmit end, a first operating;
determining, by the transmit end and based on at least the first operating frequency, a first interval of first reference signals;
determining, by the transmit end based on the first interval of the first reference signals, first time-frequency resource locations for transmitting the first reference signals;
mapping, by the transmit end, the first reference signals at the first time-frequency resource locations;
obtaining, by the transmit end, a second operating frequency that is different from the first operating frequency;
determining, by the transmit end and based on at least the second operating frequency, a second interval of second reference signals, wherein the second interval of the second reference signals is different from the first interval of the first reference signals;
determining, by the transmit end and based on the second interval of the second reference signals, second time-frequency resource locations for transmitting the second reference signals; and
mapping, by the transmit end, the second reference signals at the second time-frequency resource locations.

US Pat. No. 10,924,235

METHOD OF RECEIVING PHASE TRACKING REFERENCE SIGNAL BY USER EQUIPMENT IN WIRELESS COMMUNICATION SYSTEM AND DEVICE FOR SUPPORTING SAME

LG Electronics Inc., Seo...

9. A wireless communication device comprising:a transmitter; and
at least one processor operably coupled with the transmitter,
wherein the at least one processor is configured to:
map a phase tracking reference signal (PT-RS) to one or more resource blocks (RBs); and
transmit, to another wireless communication device through the transmitter, a downlink signal including the PT-RS mapped to the one or more RBs, in a state in which a size of a scheduled bandwidth for the another wireless communication device is not less than a specific bandwidth,
wherein the at least one processor is configured to transmit the PT-RS to the another wireless communication device, only in the state in which the size of the scheduled bandwidth for the another wireless communication device is not less than the specific bandwidth, and
wherein in mapping the PT-RS to the one or more RBs, the at least one processor is configured to determine frequency density for the PT-RS based on the size of the scheduled bandwidth for the another wireless communication, and determine the one or more RBs in consideration of the determined frequency density for the PT-RS.

US Pat. No. 10,924,234

COMMUNICATION APPARATUS AND TRANSMISSION METHOD FOR TRANSMITTING A DEMODULATION REFERENCE SIGNAL

Panasonic Intellectual Pr...

1. A communication apparatus, comprising:a receiver, which, in operation, receives resource allocation information relating to a resource allocated for a physical uplink shared channel (PUSCH) transmission, Demodulation Reference Signal (DMRS) information indicating a number of symbols on which a DMRS is to be mapped, and sounding reference signal (SRS) information indicating SRS symbol candidates to which a SRS is to be mapped, the resource including multiple consecutive subframes and multiple subcarriers; and
a transmitter, which, in operation, transmits a signal including the DMRS which is mapped to sets of symbols distributed in non-consecutive subframes of the multiple consecutive subframes,
wherein each of the sets of symbols include multiple consecutive symbols depending on the received DMRS information,
a number of the multiple consecutive symbols is less than 14 symbols regardless of a number of the multiple consecutive subframes included in the resource, and
the sets of symbols are symbols other than the SRS symbol candidates.

US Pat. No. 10,924,231

RADIO BASE STATION APPARATUS, MOBILE STATION APPARATUS AND RADIO COMMUNICATION METHOD

NTT DOCOMO, INC., Tokyo ...

4. A radio communication system comprising:a radio base station apparatus comprising:
a first processor configured to orthogonalize Demodulation Reference Signals (DM-RSs) associated with layers of a Multiple-Input Multiple-Output (MIMO) transmission each allocated to a plurality of radio resources of layers by using two-dimensional orthogonal codes, whereby DM-RSs of a first layer are allocated to same radio resources as in a second layer and are allocated at a same density as in the second layer; and
a transmitter configured to transmit a signal wherein DM-RSs and transmission data are multiplexed, from a plurality of transmission antennas in multiple layers; and
a mobile station apparatus comprising:
a receiver configured to receive the signal; and
a second processor configured to demodulate the transmission data by using the DM-RSs of the signal,
wherein an index of information of the DM-RSs including the two-dimensional orthogonal codes is signaled from the radio base station apparatus to the mobile station apparatus, and the index corresponds to one or more antennas of the plurality of transmission antennas.

US Pat. No. 10,924,230

AVOIDING OR CORRECTING INTER-CELL INTERFERENCE BASED ON AN AZIMUTHAL MODIFICATION

Sprint Communications Com...

1. One or more non-transitory computer-readable media having computer-executable instructions embodied thereon that, when executed, perform a method for dynamically adjusting beamforming weights based on a azimuthal change request, the method comprising:receiving, from a first base station, an indication that a first antenna is configured in a first orientation having a first azimuth and is transmitting a first set of signals to a first coverage area;
receiving, from a second base station, an indication that one or more antennas of the second base station are transmitting a second set of signals to a second coverage area;
receiving, from a the first base station, a proposed configuration for the first antenna, the proposed configuration comprising the first antenna in a second orientation and having a second azimuth, wherein transmitting the first set of signals would correspond to a third coverage area;
prior to the first base station transmitting the first set of signals to the third coverage area, predicting a potential inter-cell interference based on the second coverage area and the third coverage area; and
based on the determined potential inter-cell interference exceeding a predetermined threshold, communicating a response to the first base station.

US Pat. No. 10,924,228

COMMUNICATIONS WITH CARRIER SELECTION, SWITCHING AND MEASUREMENTS

Futurewei Technologies, I...

1. A method for a user equipment, comprising:the user equipment receiving a first configuration signaling from a base station to configure a plurality of component carriers, the plurality of component carriers corresponding to one or more component carrier groups;
the user equipment performing a time and frequency synchronization with a first component carrier in the plurality of component carriers within a first component carrier group of the one or more component carrier groups; and
the user equipment determining a time and frequency synchronization with a second component carrier within the first component carrier group based on the time and frequency synchronization performed with the first component carrier.

US Pat. No. 10,924,225

GROUP-BASED HYBRID AUTOMATIC REPEAT REQUEST (HARQ) ACKNOWLEDGEMENT FEEDBACK

MEDIATEK INC., Hsinchu (...

1. A method, comprising:receiving, by a user equipment (UE) in a wireless communication system, one or more first downlink control informations (DCIs) that are associated with first downlink transmissions belonging to a first hybrid automatic repeat request acknowledgement (HARQ-ACK) feedback group in a wireless communication system;
receiving, by the UE from a base station, a first request that indicates a first group index (GI) of the first HARQ-ACK feedback group and a first HARQ-ACK transmission opportunity (TxOP); and
transmitting, by the UE to the base station, first acknowledge bits for acknowledging receptions of downlink transmissions belonging to the first HARQ-ACK feedback group over the first HARQ-ACK TxOP indicated by the first request.

US Pat. No. 10,924,223

METHOD OF MANAGING HARQ BUFFER FOR NR

Google LLC, Mountain Vie...

1. A method performed by a user device, the method comprising:receiving, from a base station, a configuration of configured scheduling including a configured uplink grant for new transmission of data in a time interval and a radio network temporary identifier (RNTI);
determining a hybrid automatic repeat request (HARQ) process for the time interval;
removing data stored in a buffer of the HARQ process based on the user device not using the configured uplink grant to transmit data in the time interval;
receiving, from the base station, downlink control information (DCI) addressed to the RNTI, the DCI including a request for retransmission from the HARQ process and a second uplink grant for the retransmission; and
after removing the data stored in the buffer of the HARQ process, ignoring, the request for retransmission from the HARQ process.

US Pat. No. 10,924,222

METHOD FOR SENDING INDICATION INFORMATION, METHOD FOR SENDING HARQ-ACK, AND DEVICE

Huawei Technologies Co., ...

1. A method for sending indication information, the method comprising:determining, by a network device, hybrid automatic repeat request-acknowledgment (HARQ-ACK) feedback indication information for instructing at least one terminal device to feed back, wherein the HARQ-ACK feedback indication information comprises information indicating a transmission time interval for the at least one terminal device to feed back a HARQ-ACK and proprietary information specific to the at least one terminal device, wherein the proprietary information comprises at least one of following:
a bit quantity of the HARQ-ACK that the at least one terminal device is to feed back, or
a channel resource used by the at least one terminal device to feed back the HARQ-ACK; and
sending, by the network device, the HARQ-ACK feedback indication information to the at least one terminal device,
wherein sending, by the network device, the HARQ-ACK feedback indication information to the at least one terminal device comprises:
sending, by the network device, first downlink control information to the at least one terminal device, wherein the first downlink control information comprises the HARQ-ACK feedback indication information,
wherein:
the network device comprises a plurality of preset radio network temporary identifiers (RNTIs) used to scramble the first downlink control information; and
before sending, by the network device, the first downlink control information to the at least one terminal device, the method further comprises:
searching, by the network device based on a terminal group to which the at least one terminal device belongs, the plurality of preset RNTIs for an RNTI subset corresponding to the terminal group, and selecting an RNTI from the RNTI subset to scramble the first downlink control information, and
separately sending, by the network device, an identifier number of the selected RNTI to the at least one terminal device for uniquely identify the selected RNTI,
wherein separately sending, by the network device, an identifier number of the selected RNTI to the at least one terminal device comprises:
separately sending, by the network device, second downlink control information to the at least one terminal device, wherein the second downlink control information comprises the identifier number of the selected RNTI.

US Pat. No. 10,924,220

HYBRID AUTOMATIC REPEAT REQUEST METHOD AND TERMINAL DEVICE

Huawei Technologies Co., ...

1. A hybrid automatic repeat request (HARQ) method, comprising:obtaining, by a terminal device, a first uplink grant from a base station, wherein the first uplink grant is carried in a media access control (MAC) message;
transmitting, by the terminal device, uplink data based on the first uplink grant during a plurality of transmission time periods;
starting, by the terminal device, a first timer in a subframe corresponding to a last transmission time period of the plurality of transmission time periods, wherein the terminal device does not listen to a physical downlink control channel (PDCCH) during and based on running of the first timer;
after the first timer is stopped or expires, starting, by the terminal device, a second timer; and
listening, by the terminal device, to the PDCCH during and based on running of the second timer;
detecting, by the terminal device, based on listening to the PDCCH, a second uplink grant from the base station; and
performing, by the terminal device, a HARQ retransmission or an initial transmission based on the second uplink grant;
wherein the method further comprises:
starting a third timer in the subframe corresponding to the last transmission time period of the plurality of transmission time periods, wherein the third timer corresponds to waiting for the base station to send a contention resolution message;
before the third timer expires or is stopped, receiving a contention resolution message from the base station, wherein the contention resolution message indicates that random access contention of the terminal device succeeds; and
stopping the second timer based on the contention resolution message.

US Pat. No. 10,924,218

APPARATUS, SYSTEM AND METHOD OF COMMUNICATING A SINGLE CARRIER (SC) TRANSMISSION

INTEL IP CORPORATION, Sa...

1. An apparatus comprising:memory circuitry; and
a processor comprising logic and circuitry configured to cause an Enhanced Directional Multi-Gigabit (EDMG) wireless communication station (STA) to:
generate a first space-time stream and a second space-time stream according to a Single Carrier (SC) symbol blocking structure and a Space Time Block Code (STBC), wherein the first space-time stream comprises a first Guard Interval (GI) between first and second data symbol blocks of the first space-time stream, and the second space-time stream comprises a second GI between first and second data symbol blocks of the second space-time stream, the first GI comprises a first Golay sequence and the second GI comprises a second Golay sequence different from the first Golay sequence, wherein the first data symbol block of the first space-time stream comprises a first data sequence, the second data symbol block of the first space-time stream comprises a second data sequence, the first data symbol block of the second space-time stream comprises a sign inverted complex conjugate of the second data sequence with reverse order, and the second data symbol block of the second space-time stream comprises a complex conjugate of the first data sequence with reverse order; and
transmit a SC transmission based on the first and second space-time streams in a frequency band above 45 Gigahertz (GHz).

US Pat. No. 10,924,217

APPARATUS, SYSTEM AND METHOD OF COMMUNICATING A PHYSICAL LAYER PROTOCOL DATA UNIT (PPDU)

INTEL IP CORPORATION, Sa...

1. An apparatus comprising:a processor comprising logic and circuitry configured to cause an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station (STA) to:
generate a plurality of spatial streams of an EDMG Physical Layer (PHY) Protocol Data Unit (PPDU);
map the plurality of spatial streams to a respective plurality of pairs of space-time streams according to a Space Time Block Coding (STBC) scheme by mapping sequences of data constellation points of a spatial stream of the plurality of spatial streams to a pair of space-time streams of the plurality of pairs of space-time streams, wherein a first modulated data sequence in an odd numbered space-time stream of the pair of space-time streams comprises a first sequence of data constellation points of the spatial stream, a second modulated data sequence in the odd numbered space-time stream comprises a second sequence of data constellation points of the spatial stream, a first modulated data sequence in an even numbered space-time stream of the pair of space-time streams comprises a sign-inverted complex conjugate of the second sequence of data constellation points, and a second modulated data sequence in the even numbered space-time stream comprises a complex conjugate of the first sequence of data constellation points; and
transmit an Orthogonal Frequency Division Multiplexing (OFDM) transmission of the EDMG PPDU over a channel bandwidth in a frequency band above 45 Gigahertz (GHz), the OFDM transmission based on the plurality of pairs of space-time streams; and
a memory to store information processed by the processor.

US Pat. No. 10,924,213

DEVICE AND METHOD FOR RECEIVING BROADCAST SIGNAL

LG ELECTRONICS INC., Seo...

1. A method of receiving a broadcast signal, the method comprising:receiving the broadcast signal;
orthogonal frequency division multiplexing (OFDM) demodulating the broadcast signal;
parsing a signal frame of the broadcast signal;
time deinterleaving one or more Time Interleaving (TI) blocks of the signal frame by writing the one or more TI blocks into a single linear memory based on memory addresses for actual data cells for the one or more TI blocks, wherein position information of virtual cells skipped in a time interleaving reading operation is recovered; and
forward error correction (FEC) decoding the broadcast signal.

US Pat. No. 10,924,210

METHOD, APPARATUS, AND DEVICE FOR DETERMINING POLAR CODE ENCODING AND DECODING

HUAWEI TECHNOLOGIES CO., ...

1. A polar code encoding and decoding method in a communications system, comprising:obtaining a basic quantized sequence, wherein the basic quantized sequence comprises a quantized value representing a reliability corresponding to a polarized subchannel;
obtaining a target quantized sequence based on the basic quantized sequence, wherein a relative magnitude relationship between elements in the target quantized sequence is nested with a relative magnitude relationship between elements in the basic quantized sequence;
determining K largest quantized values in the target quantized sequence based on a non-fixed bit sequence length K, and using polarized subchannels corresponding to the K largest quantized values, as a non-fixed bit position set; and
performing polar code encoding or decoding based on the non-fixed bit position set.

US Pat. No. 10,924,209

CHANNEL CODING METHOD OF VARIABLE LENGTH INFORMATION USING BLOCK CODE

LG ELECTRONICS INC., Seo...


US Pat. No. 10,924,208

DEVICE FOR GENERATING BROADCAST SIGNAL FRAME INCLUDING PREAMBLE INDICATING STARTING POSITION OF FIRST COMPLETE FEC BLOCK, AND METHOD FOR GENERATING BROADCAST SIGNAL FRAME

Electronics and Telecommu...

1. An apparatus for generating broadcast signal frame, comprising:a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal;
a power normalizer configured to reduce power of the multiplexed signal to a power level corresponding to the core layer signal;
a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both a core layer corresponding to the core layer signal and an enhanced layer corresponding to the enhanced layer signal; and
a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver,
wherein the preamble includes a field indicating a start position of a first complete forward error correction (FEC) block corresponding to each of physical layer pipes,
wherein the start position of the first complete FEC block is specified relative to the first cell of each of the physical layer pipes.

US Pat. No. 10,924,207

TECHNIQUE FOR RADIO TRANSMISSION UNDER VARYING CHANNEL CONDITIONS

Telefonaktiebolaget LM Er...

1. A method of radio receiving data, the method comprising:receiving a modulation symbol that is a combination of at least two partial modulation symbols at different power levels;
demodulating, based on the received modulation symbol, a partial modulation symbol and subtracting the demodulated partial modulation symbol from the received modulation symbol resulting in a residual modulation symbol;
repeating the demodulation based on the residual modulation symbol for demodulating-the at least two partial modulation symbols representing the data,
wherein the demodulation is repeated in the order of decreasing power levels until the demodulation or a decoding of the demodulated partial modulation symbol fails.

US Pat. No. 10,924,205

METHOD FOR TRANSMITTING OR RECEIVING SIGNAL IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR

LG Electronics Inc., Seo...

1. A method of receiving a downlink signal by a user equipment (UE) in a wireless communication system, the method comprising:receiving a configuration for a channel state information-reference signal (CSI-RS) resource; and
receiving slot format-related information (SFI) through a group common-physical downlink control channel (GC-PDCCH),
wherein the UE receives a CSI-RS in a CSI-RS resource or deactivates the reception of the CSI-RS in the CSI-RS resource, according to the SFI received through the GC-PDCCH,
wherein the SFI of the GC-PDCCH indicates whether each of a plurality of resources included in a slot is a downlink (D) resource, an uplink (U) resource, or a third resource for which D or U is not determined, and the third resource is indicated by the SFI of the GC-PDCCH from among third resource candidates which are indicated to the UE through a semi-static configuration, and
wherein if the SFI of the GC-PDCCH configures any one of the U resource or the third resource to the CSI-RS resource, the UE deactivates the reception of the CSI-RS scheduled in the CSI-RS resource.

US Pat. No. 10,924,204

SIGNAL TRANSMISSION DEVICE AND METHOD, AND SIGNAL RECEPTION DEVICE

Industry-University Coope...

1. A signal transmission device, comprising:a bit signal generating unit for generating an N-bit transmission signal based on a K-bit original signal according to a lookup table in which a plurality of K-bit original signals are associated with a plurality of N-bit transmission signals by 1:1 correspondence; and
a transmitting unit for transmitting the N-bit transmission signal via N signal lines such that each line carries one bit,
wherein K is a natural number, and N is an even number greater than K and less than 2K, and
wherein N/2 bits of the plurality of N-bit transmission signals are set to have a logic high and remaining N/2 bits of the plurality of N-bit transmission signals are set to have a logic low.

US Pat. No. 10,924,200

RECONFIGURABLE OPTICAL ADD/DROP MULTIPLEXER

HUAWEI TECHNOLOGIES CO., ...

1. A reconfigurable optical add/drop multiplexer, comprising:N input ports;
N output ports;
M add ports; and
M drop ports,whereinN?1 and M?1
each of the N input ports and each of the M add ports is respectively connected to a corresponding first polarizer, the corresponding first polarizer being one of one or more first polarizers,
each of the N output ports and each of the M drop ports is respectively connected to a corresponding second polarizer, the corresponding second polarizer being one of two or more second polarizers,
a first end of each first polarizer of the one or more first polarizers is connected to a second end of the same first polarizer, forming a loop comprising one of the one or more first polarizers,
a first end of each second polarizer of the two or more second polarizers is connected to a second end of the same second polarizer, forming a loop comprising one of the two or more second polarizers,
an annular waveguide array is between a loop LIi and a loop LOj, the annular waveguide array comprising L first annular waveguide groups, where L?1,
the loop LIi includes one of the one or more first polarizers, and the first polarizer included in the loop LIi is connected to an ith input port Ii of the N input ports, where N?i?1,
the loop LOj includes a first-second polarizer of the two or more second polarizers, and the first-second polarizer included in the loop LOj is connected to a jth output port Oj of the N output ports, where N?j?1,
a second annular waveguide group is between the loop LIi and a loop LDk,
the loop LDk includes a second-second polarizer of the two or more second polarizers, and the second-second polarizer included in the loop LDk is connected to a kth drop port Dk of the M drop ports, where M?k?1,
the input port Ii is configured to receive a first optical signal set,
the corresponding first polarizer of the one or more first polarizers connected to the input port Ii is configured to:
perform a polarization beam splitting on optical signals included in the first optical signal set to obtain a second optical signal set and a third optical signal set; and
output the second optical signal set and the third optical signal set, the second annular waveguide group is configured to:
receive a first optical signal in the second optical signal set and a second optical signal in the third optical signal set; and
transmit the first optical signal and the second optical signal to the drop port Dk,
both a wavelength of the first optical signal and a wavelength of the second optical signal are the same as a resonant wavelength of the second annular waveguide group,
the second-second polarizer connected to the drop port Dk is configured to:
perform a polarization beam combination on the first optical signal and the second optical signal; and
output an optical signal obtained after the polarization beam combination,
the annular waveguide array is configured to:
receive a first optical signal subset in the second optical signal set and a second optical signal subset in the third optical signal set; and
transmit the first optical signal subset and the second optical signal subset to the output port Oj,
wavelengths of optical signals included in the first optical signal subset are in a one-to-one correspondence with wavelengths of optical signals included in the second optical signal subset, and
the first-second polarizer connected to the output port Oj is configured to:
perform a polarization beam combination on the first optical signal subset and the second optical signal subset, and
output an optical signal obtained after the polarization beam combination.

US Pat. No. 10,924,199

COMMUNICATION METHOD AND COMMUNICATION DEVICE

Kyoto University, Kyoto ...

1. A communication method using an almost periodic function code, the communication method comprising:using, for modulation, almost periodic function codes a number of which is in accordance with a number of users or a number of channels, among K almost periodic function codes, wherein
a parameter that determines each of the K almost periodic function codes is represented by ?+(k?1)/K,
where k is an integer from 1 to K and is an identifier for identifying each of the K almost periodic function codes,
K is N or 2N, where N is a code length of each almost periodic function code, and
? is a real number greater than 0 and less than 1/N, and
? is in a range of ¼N???¾N.

US Pat. No. 10,924,198

HIGH SPEED EMBEDDED PROTOCOL FOR DISTRIBUTED CONTROL SYSTEM

1. A method of communication among two or more modules over a common control network, the method comprising:transmitting a message packet over a control network according to a protocol, the message packet having a first portion having a first data rate and a second portion having a second data rate higher than the first data rate;
sending an edge in a portion of the message packet as part of a transition from the first data rate to the second data rate,
wherein the protocol is defined in part by a receiving device adjusting a position of a sample point for second portion bits in response to sensing the edge.

US Pat. No. 10,924,197

ADVERTISING MEASUREMENT AND CONVERSION MEASUREMENT FOR RADIO SYSTEMS

DTS, Inc., Calabasas, CA...

1. A radio receiver comprising:radio frequency (RF) receiver circuitry configured to receive a radio broadcast signal that includes a digital audio file;
an Internet network interface;
a user interface; and
a receiver controller configured to:
initiate play of the digital audio file; and
send radio reception information associated with the digital audio file to a destination via the Internet network interface, wherein the radio reception information includes time of play of the audio file and geolocation information of the radio receiver.

US Pat. No. 10,924,195

BOUNCED RAY TUBES WITH PREPROCESSING OF VISIBILITY

Polaris Wireless, Inc., ...

1. A method for ray launching, comprising:receiving, by a data-processing system, a dataset that is representative of a first structure and a second structure within an environment, wherein the first structure and the second structure are defined in the dataset as having a first surface and a second surface, respectively;
determining, by the data-processing system, whether a reference point within each corresponding tile in a second plurality of tiles into which the second surface is partitioned, is visible or not from a reference point of a first spawning tile in a first plurality of tiles into which the first surface is partitioned, wherein an indication of the visibility of each corresponding tile from the first spawning tile is stored into a computer memory;
projecting, by the data-processing system, a first set of incident ray tubes from the reference point of the first spawning tile to the tiles in the second plurality of tiles, wherein each ray tube in the first set of incident ray tubes is projected toward and defined by a corresponding tile in the second plurality of tiles, including a first incident ray tube projected toward and defined by a first incident tile having a first point, and wherein each ray tube in the first set of incident ray tubes is projected based on i) each of the corresponding tiles in the second plurality of tiles lying within a region defined by bounced ray tube edges of a first precursor ray tube that is incident on the first spawning tile and ii) the stored indication of the visibility of each of the corresponding tiles in the second plurality of tiles from the first spawning tile;
bouncing, by the data-processing system, the first incident ray tube from the first incident tile, wherein the bouncing of the first incident ray tube results in a first bounced ray tube;
evaluating, by the data-processing system, an incidence of bounced ray tubes at a predetermined receive point within the environment, wherein at least one of the bounced ray tubes is based on the first bounced ray tube; and
presenting, by the data-processing system, a propagation result that is based on the evaluating of the incidence of bounced ray tubes.

US Pat. No. 10,924,194

RADIO-FREQUENCY TRANSCEIVER DEVICE, CORRESPONDING SYSTEM AND METHOD

STMicroelectronics S.r.l....

1. A radio-frequency transceiver device, comprising:at least a first transmission pad, wherein said first transmission pad is configured to be connected to a first transmission antenna;
a first transmission circuit, wherein said first transmission circuit is configured to generate a first transmission signal for said first transmission pad by modulating a radio frequency signal as a function of a first transmission control signal;
at least a first reception pad and a second reception pad, said first and second reception pads configured to be connected to a first reception antenna and a second reception antenna, respectively;
at least a first reception circuit and a second reception circuit, wherein said first and second reception circuits are configured to generate a first demodulated reception signal and a second demodulated reception signal, respectively, by demodulating a first signal and a second signal received by said first and second reception pads, respectively, using the radio frequency signal, and wherein each of said first reception circuit and said second reception circuit comprises a band pass filter configured to pass signals having frequencies between a first frequency and a second frequency;
wherein the radio-frequency transceiver device comprises a control circuit configured to operate during a reception test phase to:
generate said first transmission control signal, wherein said first transmission control signal has a frequency lying between said first frequency and said second frequency during said reception test phase;
test, as a function of said first and said second demodulated reception signal, whether said first signal received by said first reception pad corresponds to said second signal received by said second reception pad; and
generate a reception error signal indicating a reception error when said test indicates that said first signal and said second signal do not correspond.

US Pat. No. 10,924,193

TRANSMIT AND RECEIVE RADIO FREQUENCY (RF) SIGNALS WITHOUT THE USE OF BASEBAND GENERATORS AND LOCAL OSCILLATORS FOR UP CONVERSION AND DOWN CONVERSION

International Business Ma...

25. A system for transmitting and receiving radio frequency (RF) signals, the system comprising:a transmit path comprising:
a Field Programmable Gate Array (FPGA) that feeds digital signals to a digital analog converter (DAC), wherein the DAC generates a frequency signal;
one or more filters to produce a first filtered signal and a second filtered signal;
an interface to transmit the second filtered signal to a device under test;
one or more secondary filters to filter the second filtered signal into a sub-signal having one or more components; and
a mixer configured to mix the first filtered signal with the sub-signal to produce a first mixed signal;
a receive path comprising:
one or more filters to filter an output signal received from the device under test;
a second mixer configured to mix the first mixed signal with an output signal of the one or more filters to filter the output signal received from the device under test to produce a second mixed signal; and
an analog-to-digital converter (ADC) to convert the second mixed signal for analysis.

US Pat. No. 10,924,192

VEHICULAR COMMUNICATION DEVICE

DENSO CORPORATION, Kariy...

1. A vehicular communication device used for a vehicle, comprising:a reception section that receives, from a periphery vehicle equipped with a narrow area communicator for performing vehicle interior communication, a communication performance index representing performance of the narrow area communicator;
a reference value setup section that successively sets a reference value as a criterion for the communication performance index, based on the communication performance indexes received by the reception section from a plurality of the periphery vehicles;
an acquisition section that acquires the communication performance index for a targeted narrow area communicator, the targeted narrow area communicator being the narrow area communicator that is targeted at anomaly determination; and
an anomaly determination section that determines anomaly of the targeted narrow area communicator, based on comparison between the reference value set by the reference value setup section and the communication performance index acquired by the acquisition section for the targeted narrow area communicator.

US Pat. No. 10,924,190

OPTICAL RECEIVER AND OPTICAL RECEPTION METHOD

NEC Corporation, Tokyo (...

1. An optical receiver comprising:an optical reception circuit configured to receive wavelength multiplexed light including signal light, convert the signal light into an electrical signal by coherent detection of the signal light performed by using local oscillation light, and output power of the local oscillation light, a bit error rate of the electrical signal, and the electrical signal; and
a controller configured to monitor the power of the local oscillation light and the bit error rate, calculate a signal-to-noise ratio of the signal light, based on the power of the local oscillation light and the bit error rate, and acquire a number of wavelengths of the wavelength multiplexed light and power per wavelength of the signal light, based on the signal-to-noise ratio and the power of the local oscillation light.

US Pat. No. 10,924,189

CONSTANT ENVELOPE PATH-DEPENDENT PHASE MODULATION

RAYTHEON COMPANY, Waltha...

14. A communications method, comprising:generating a carrier waveform;
modulating, using a modulator, the carrier waveform according to a path-dependent phase modulation scheme to produce a modulated signal; and
mapping, using a mapping module, a received data payload to the path-dependent phase modulation scheme, each symbol S in the path-dependent phase modulation scheme including a concatenation of at least one location bit L and at least one path bit P.

US Pat. No. 10,924,188

OPTICAL TRANSMITTER, OPTICAL COMMUNICATION SYSTEM, AND OPTICAL COMMUNICATION METHOD

NEC Corporation, Tokyo (...

1. An optical transceiver, comprising:an encoder configured to encode input digital signals by one of the plurality of encoding methods and output the encoded digital signals;
a controller configured to identify an encoding method corresponding to optical transmission attributes of an optical carrier wave and set drive signals to modulate the optical carrier wave;a mapper configured to map the encoded digital signals to symbol signals and output the mapped signals; andan optical modulator configured to modulate the optical carrier wave based on the mapped signals.

US Pat. No. 10,924,187

OPTICAL TRANSCEIVER WITH A PLURALITY OF BUILT-IN OPTICAL SUBASSEMBLIES

Sumitomo Electric Industr...

1. An optical transceiver comprising:a plurality of optical subassemblies each configured to perform photoelectric conversion between a single optical signal and a single electric signal;
a circuit board including a circuit mounted thereon, the circuit being electrically connected to each of the optical subassemblies;
an optical multiplexer/demultiplexer including a plurality of internal fibers, the optical multiplexer/demultiplexer being optically connected to each of the optical subassemblies through each of the internal fibers and configured to multiplex the single optical signal to generate an optical transmission signal or demultiplex an optical reception signal to generate the single optical signal;
a receptacle optically connected to the optical multiplexer/demultiplexer and configured to transmit the optical transmission signal to an outside and receive the optical reception signal; and
a holding member configured to hold the optical subassemblies and engaged with the circuit board, wherein
the holding member includes a first guide configured to guide at least any one of the internal fibers and a second guide configured to detour at least any one of the internal fibers different from the at least one internal fiber guided by the first guide with respect to the first guide,
the optical subassemblies include a first optical subassembly and a second optical subassembly disposed on an inner side in a lateral direction of the optical transceiver relative to a position of the first optical subassembly,
the internal fibers include a first internal fiber and a second internal fiber,
the optical multiplexer/demultiplexer is optically connected to the first optical subassembly through the first internal fiber and optically connected to the second optical subassembly through the second internal fiber,
the first guide guides the first internal fiber,
the second guide guides the second internal fiber, and
a length of the first internal fiber is set equal to a length of the second internal fiber.

US Pat. No. 10,924,185

SYSTEMS AND METHODS OF DUAL-SIDE ARRAY BI-DIRECTIONAL CWDM MICRO-OPTICS

Hewlett Packard Enterpris...

1. A dual-side bi-directional optical multiplexing system, comprising:a light receiving array to receive light in an egress propagation direction from an optical fiber, and arranged on a first side of and displaced from a central axis of the optical fiber, wherein receiving light comprises receiving light at a plurality of receive wavelengths;
a light transmitting array to emit light in an ingress propagation direction into the optical fiber, and arranged on an opposing side of the central axis of the optical fiber from the light receiving array and displaced from the central axis of the optical fiber, wherein emitting light comprises emitting light at a plurality of transmit wavelengths and wherein the first position of the light receiving array and a second position of the light transmitting array are arranged so as to form dual-sides of the system with respect to the central axis of the optical fiber such that the light receiving array and light transmitting array are equidistant from the central axis of the optical fiber; and
bi-directional micro-optics to interface with the optical fiber to direct light propagating in the egress propagation direction from the optical fiber towards the first position of the light receiving elements array with respect to the dual-sides of the system, the bi-directional micro-optics further interfacing with the light transmitting array to direct light propagating in the ingress direction emitted from the second position of the light transmitting array towards the optical fiber, and wherein the plurality of receive wavelengths propagate in the egress propagation direction through the optical fiber and wherein the plurality of transmit wavelengths are combined for propagation in the ingress direction through the optical fiber, wherein the bi-directional micro-optics comprise:
a zigzag multiplexer/demultiplexer aligned with the optical fiber at the central axis of the optical fiber; and a
a bi-directional multiplexer/de-multiplexer aligned with the optical fiber at the central axis of the optical fiber, wherein the bi-directional multiplexer/demultiplexer selectively deflects the light propagating in the egress propagation direction from the optical fiber towards a zigzag propagation path on the zigzag multiplexer/demultiplexer based on the plurality of receive wavelengths, and selectively deflects light propagating from the zigzag propagation path on the zigzag multiplexer/demultiplexer in the ingress direction towards the optical fiber based on the plurality of transmit wavelengths.

US Pat. No. 10,924,184

TRANSMISSION APPARATUS, TRANSMISSION METHOD, RECEPTION APPARATUS, AND RECEPTION METHOD

SONY CORPORATION, Tokyo ...

1. A transmission apparatus comprising:circuitry configured to:
perform a high dynamic range opto-electronic conversion on high dynamic range video data to obtain transmission video data;
perform encoding processing on the transmission video data to obtain a video stream;
transmit a container including the video stream, program information, and event information, and transmit a layer of the video stream; and
insert first metadata information indicating a standard dynamic range opto-electronic transfer characteristic into the layer of the video stream, the layer corresponding to a first region of video usability information (VUI) of a sequence parameter set (SPS) network abstract layer (NAL) unit, and insert second metadata information indicating a high dynamic range opto-electronic transfer characteristic into a layer of the container.

US Pat. No. 10,924,182

INTEGRATED OPTICAL SWITCHING AND SPLITTING FOR TROUBLESHOOTING IN OPTICAL NETWORKS

CommScope Connectivity Be...

1. An optical data transmission system, comprising:a laser transmitter/receiver unit capable of generating a data transmission signal at a first wavelength;
an OTDR unit capable of generating an OTDR probe signal at a second wavelength different from the first wavelength;
a first coupler unit coupled to receive the data transmission signal and the OTDR probe signal and to output a combined transmission signal comprising the data transmission signal and the OTDR probe signal;
a trunk fiber coupled to receive the combined transmission signal in a first end of the trunk fiber;
an optical circuit comprising
i) an input waveguide coupled to receive the combined transmission signal from a second end of the trunk fiber,
ii) a plurality of outputs, and
iii) an optical network comprising a waveguide splitter module connecting between the input waveguide and the plurality of outputs, the optical network having a plurality of output waveguides coupling to respective outputs of the plurality of outputs, the optical network further comprising at least two wavelength-dependent optical switches disposed on paths taken by the data transmission signal;
wherein the optical circuit is configurable so as to provide the OTDR probe signal to only one of the outputs while providing the data transmission signal to others of the outputs and to the one of the outputs.

US Pat. No. 10,924,180

LOW LATENCY SATELLITE COMMUNICATION RELAY NETWORK

Via Space Networks Inc., ...

1. A communication system, comprising:one or more satellites disposed in one or more orbital planes,
wherein the satellites are disposed at a fixed distance interval and a fixed altitude interval;
at least two terminals positioned at end sections of a plurality of satellites,
wherein the terminals are located at or above a predetermined minimum latitude,
wherein the earth's circumference is inversely proportional to latitude,
wherein the plurality of satellites are configured to provide bi-directional communication between the two terminals,
wherein data transmission between the terminals is based solely on geographic data of the terminals;
an optimal pathway comprising at least one of a straight line and a theoretical pathway; and
a machine-generated boundary box comprising maximum and minimum latitudes and maximum and minimum longitudes of a satellite within which data transmission between the terminals is permitted.

US Pat. No. 10,924,179

MULTI-CONSTELLATION SATELLITE TERMINAL

GOGO BUSINESS AVIATION LL...

1. A mobile communicator, mounted on a mobile platform, for communicating with multiple constellations of satellites, the mobile communicator comprising:a phased array antenna that is configured to propagate electromagnetic signals from the mobile communicator towards satellites via a plurality of antenna resources;
one or more transceivers configured to communicate data that is to be delivered between the mobile platform and a plurality of satellites included in the multiple constellations of satellites; and
a controller executing computer-executable instructions stored on one or more tangible-non-transitory memories to:
command the one or more transceivers to utilize a first portion of the plurality of antenna resources of the antenna array to establish a first communicative connection with a first target satellite of the plurality of satellites via a respective spatial channel of the first target satellite, the first communicative connection for delivering a data stream between the mobile platform and the plurality of satellites; and
while the first communicative connection with the first target satellite is maintained:
command the one or more transceivers to utilize a second portion of the plurality of antenna resources of the antenna array to establish a second communicative connection with a second target satellite via a respective spatial channel of the second target satellite; and
command the one or more transceivers to perform a soft or semi-soft handoff of the data stream from being delivered via the first communicative connection with the first target satellite to being delivered via the second communicative connection with the second target satellite, the soft or semi-soft handoff including a simultaneous delivery, over an interval of time, of a data payload of the data stream to the first target satellite via the first communication channel and of a duplicate of the data payload of the data stream to the second target satellite via the second communication channel.

US Pat. No. 10,924,178

GEOSTATIONARY HIGH ALTITUDE PLATFORM

1. An apparatus comprising:a load;
a controller;
a rectenna;
electrically-powered thrusters, wherein the electrically-powered thrusters are electrohydrodynamic thrusters; and
a super pressure balloon operatively coupled to and adapted to suspend the load, the controller, the rectenna and the electrically-powered thrusters at a predetermined altitude;
the electrically-powered thrusters being adapted to provide a force suitable to counter winds associated with the predetermined altitude;
the rectenna being adapted to produce electricity to power the thrusters, the controller, and the load; and
the controller being adapted to control the thrusters to maintain the apparatus in a geosynchronous position above the earth.

US Pat. No. 10,924,176

NEXT GENERATION IN-BUILDING RELAY SYSTEM AND METHOD

KT CORPORATION, Gyeonggi...

1. A next generation in-building relay system comprising:a fifth generation (5G) signal providing unit configured to down-convert a millimeter wave radio frequency signal to an intermediate frequency signal;
a 5G master hub unit configured to convert the intermediate frequency signal into a radio over fiber (RoF) signal, which is an analog optical signal, and transmit the RoF signal;
an optical coupling unit configured to couple a digital optical signal output from a master hub unit and the analog optical signal output from the 5G master hub unit and transmit the coupled signal to an optical cable; and
an optical distribution unit configured to separate the digital optical signal and the analog optical signal from the coupled signal transmitted from the optical coupling unit, transmit the digital optical signal to a remote optical relay unit, and transmit the analog optical signal to distributed remote units, wherein:
the 5G signal providing unit converts an uplink intermediate frequency signal received from the 5G master hub unit into a millimeter wave radio frequency signal, transmits the millimeter wave radio frequency signal to a 5G base station, and provides the 5G master hub unit with a reference clock and transmission timings of an uplink and a downlink, which are received from the 5G base station;
the 5G master hub unit transmits an uplink intermediate frequency signal received from the distributed remote unit to the 5G signal providing unit; and
the distributed remote units convert uplink millimeter wave radio frequency signals received from a 5G terminal into RoF signals and transmit the RoF signals to the 5G master hub unit.

US Pat. No. 10,924,174

PRECODING MATRIX INDICATION METHOD, APPARATUS, AND SYSTEM

Huawei Technologies Co., ...

7. User equipment comprising a receiver and a transmitter, both of which are coupled to a processor, wherein:the receiver is configured to cooperate with the processor to receive indication information sent by a network device, wherein the indication information comprises information about codebooks used to report precoding matrix indicators (PMI), the information about the codebooks indicates that the used codebooks are at least two of a first codebook to an Nth codebook, the PMIs comprise at least two of a first PMI to an Nth PMI, the first PMI to the Nth PMI respectively indicate a precoding matrix in the first codebook to a precoding matrix in the Nth codebook, and N is an integer greater than or equal to 2; and
the transmitter is configured to cooperate with the processor to send the PMIs based on the indication information,
wherein the first codebook to the Nth codebook comprise at least one codebook used for inter-beam amplitude compensation.

US Pat. No. 10,924,173

BEAM MANAGEMENT IN DIRECTIONAL BEAM NETWORKS

QUALCOMM Incorporated, S...

1. A method of operating a second node, comprising:determining that there has been a failure in a communication link between a first node and the second node;
sweeping over M possible transmit beams in a beam sweep operation by transmitting a burst on at least one of the M possible transmit beams;
receiving a single feedback bit from the first node when the second node has transmitted on a suitable beam wherein the single feedback bit from the first node is received after a transmit-receive switching time after a transmit burst;
terminating the beam sweep operation over M possible transmit beams immediately when the single feedback bit from the first node is received; and
reestablishing the communication link between the first node and the second node using the suitable beam.

US Pat. No. 10,924,171

DISTRIBUTED MOBILITY FOR RADIO DEVICES

Convida Wireless, LLC, W...

1. A first apparatus comprising a processor, a memory, and communication circuitry, the first apparatus being connected to a communications network via its communication circuitry, the first apparatus further comprising computer-executable instructions stored in the memory of the first apparatus which, when executed by the processor of the first apparatus, cause the first apparatus to:establish a connection with a second apparatus, the second apparatus comprising an entity managing operations of a first radio access network;
obtain a first mobility set via communications with the second apparatus, the first mobility set comprising a first list of beams and a first condition within the first radio access network; and
derive, based on a measurement of communications conditions with beams and the first condition within the first mobility set, a second mobility set comprising a second list of beams, wherein the second list of beams are a subset of the first list of beams.

US Pat. No. 10,924,169

SMALL CELL ANTENNAS SUITABLE FOR MIMO OPERATION

CommScope Technologies LL...

1. A base station antenna, comprising:a first set of radiating elements that are configured to generate a first antenna beam that covers a first sector in an azimuth plane and a third sector in the azimuth plane;
a second set of radiating elements that are configured to generate a second antenna beam that covers a second sector in the azimuth plane and a fourth sector in the azimuth plane;
a third set of radiating elements that are configured to generate a third antenna beam that covers a fifth sector in the azimuth plane and a seventh sector in the azimuth plane; and
a fourth set of radiating elements that are configured to generate a fourth antenna beam that covers a sixth sector in the azimuth plane and an eighth sector in the azimuth plane,
wherein the second sector is between the first sector and the third sector,
wherein the fourth sector is between the first sector and the third sector and opposite the second sector,
wherein the sixth sector is between the fifth sector and the seventh sector, and
wherein the eight sector is between the fifth sector and the seventh sector and opposite the sixth sector.

US Pat. No. 10,924,167

FORWARD COMPATIBLE DESIGN FOR NON-ORTHOGONAL UE SIGNATURE SEQUENCES

QUALCOMM Incorporated, S...

1. A method for wireless communication, comprising:identifying, at a user equipment (UE), a codebook matrix having a number of rows equal to a first number and a number of columns equal to a second number, the first number being equal to a number of user equipments (UEs) supported for communication with a base station and the second number being equal to a sequence length of a set of UE specific signature sequences, wherein rows of the codebook matrix comprise a Welch bound equality achieving vector set;
identifying a UE specific signature sequence based at least in part on a mapping between an identifier associated with the UE to one or more rows of the codebook matrix; and
communicating with the base station based at least in part on the UE specific signature sequence.

US Pat. No. 10,924,166

COMPLEXITY REDUCTION FOR TRANSMITTER PRECODING

NXP USA, INC., Austin, T...

1. A method comprising:generating, at a transmitter device, a first set of rotational matrices for a set of channels of the transmitter device;
precoding first data for transmission based on the first set of rotational matrices to generate first precoded data;
transmitting the first precoded data via a first channel of the set of channels at the transmitter device;
generating, at the transmitter device, a second set of rotational matrices for the set of channels based on the first set of rotational matrices;
precoding second data for transmission based on the second set of rotational matrices to generate second precoded data; and
transmitting the second precoded data via a second channel of the set of channels at the transmitter device.

US Pat. No. 10,924,164

BEAMFORMING COMMUNICATION SYSTEMS WITH POWER CONTROL BASED ON ANTENNA PATTERN CONFIGURATION

1. A beamforming communication system comprising:an antenna array including a plurality of antenna elements;
a plurality of signal conditioning circuits, each signal conditioning circuit operatively associated with a corresponding one of the plurality of antenna elements;
an antenna array management circuit configured to generate a plurality of control signals each operable to individually control a corresponding one of the plurality of signal conditioning circuits to operate the antenna array in a selected antenna pattern configuration, the selected antenna pattern configuration chosen from a plurality of antenna pattern configurations providing different levels of power control; and
a power amplifier output tuning control circuit configured to tune an output impedance of each power amplifier to compensate for variation in output impedance associated with a selected antenna pattern configuration.

US Pat. No. 10,924,163

CODEBOOK SUBSET RESTRICTION FOR CSI

Apple Inc., Cupertino, C...

1. An apparatus configured to be employed in a user equipment (UE) comprising:one or more processors configured to:
receive a higher layer parameter for a codebook type;
receive a parameter of a bitmap for a codebook subset restriction of the codebook type;
generate a new radio (NR) codebook based on the parameter of the bitmap; and
restrict Precoder Matrix Indicator (PMI) reporting and Rank Indicator (RI) reporting that corresponds to any precoder that is associated with all layers of rank indicators, based on a configuration of a bit of the parameter of the bitmap or in response to a bit value of a bit of the parameter of the bitmap being zero; and
a radio frequency (RF) interface configured to process, with RF circuitry, data of a transmission based on the NR codebook.

US Pat. No. 10,924,160

FRONT-END MODULES WITH FIXED IMPEDANCE MATCHING CIRCUITS

SKYWORKS SOLUTIONS, INC.,...

1. A receiving system comprising:a first amplifier disposed along a first path, corresponding to a first frequency band, between an input of the receiving system and an output of the receiving system;
a second amplifier disposed along a second path, corresponding to a second frequency band, between the input of the receiving system and the output of the receiving system;
a third amplifier disposed along a third path, corresponding to a third frequency band, between the input of the receiving system and the output of the receiving system;
a first impedance matching circuit with a fixed impedance coupled to the first amplifier and disposed along the first path, the first impedance matching circuit configured to reduce a noise figure for the second frequency band and the third frequency band and to reduce an in-band metric for the first frequency band, the in-band metric comprising an in-band noise figure minus an in-band gain;
a second impedance matching circuit with a fixed impedance coupled to the second amplifier and disposed along the second path, the second impedance matching circuit configured to reduce a noise figure for the first frequency band and the third frequency band; and
a third impedance matching circuit with a fixed impedance coupled to the third amplifier and disposed along the third path, the third impedance matching circuit configured to reduce a noise figure for the first frequency band and the second frequency band.

US Pat. No. 10,924,159

HOUSEHOLD ELECTRICAL SYSTEM COMPRISING TWO-WAY DATA TRANSMISSION BETWEEN A BASE AND AN APPLIANCE

1. A household electrical system comprising an appliance having an electric circuit, a base for the appliance, and a cord connecting the appliance with the base, the cord comprising:a first electrical line formed by a first set of conductive wires for high voltage transmission of an operating power of the appliance;
a second electrical line formed by a second set of conductive wires for low voltage supply of power to the electric circuit;
a third electrical line for providing two-way data transmission between the base and the appliance, the third electrical line being formed by the second set of conductive wires,
wherein the system further includes,
a modulator configured to modulate a voltage and/or a current through the second set of conductive wires to activate the second electrical line and the third electrical line, or to activate the third electrical line; and
an independent electricity source configured to supply power to the electric circuit when the second electrical line is deactivated.

US Pat. No. 10,924,158

MACHINE ASSISTED DEVELOPMENT OF DEPLOYMENT SITE INVENTORY

1. A method, comprising:obtaining, by a processing system including a processor, an image of a target location from an image repository;
applying, by the processing system, image processing to the image to identify a plurality of image features that correspond to a plurality of physical features of the target location; and
identifying, by the processing system, a particular physical feature of the plurality of physical features of the target location as a candidate deployment site of the target location to accommodate equipment of a distributed communication network that facilitates transmission of electromagnetic waves along a surface of a transmission medium.

US Pat. No. 10,924,157

METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR DISTRIBUTION OF TIME SYNCHRONIZATION INFORMATION TO ULTRA-WIDE-BAND DEVICES

CLAIRVOYANT NETWORKS, LLC...

1. A system for distribution of time synchronization information to ultra-wide-band (UWB) devices, the system comprising:a plurality of anchors, wherein each anchor comprises at least one anchor processor, an anchor UWB radio, and an anchor timing system, and wherein each of the anchors performs UWB ranging on a subset of a plurality of tags, each securable to an object for tracking, wherein each tag comprises at least one tag processor, a tag UWB radio, and a tag timing system, wherein the tag timing systems and the anchor timing systems are time synchronized; and
a site master configured for transmitting a first time-synchronization message to at least a first anchor, wherein the first anchor is configured for distributing time synchronization information to at least a second anchor by transmitting a first UWB message during an assigned time slot for the first anchor, wherein the first UWB message includes timing information based on the first time-synchronization message,
wherein each tag is configured for receiving a UWB tag time-synchronization message from one of the first anchor and the second anchor, and wherein each tag is configured for adjusting the tag timing system of the tag based on the UWB tag time-synchronization message and determining an activation time to perform UWB ranging using the tag timing system.

US Pat. No. 10,924,154

ELECTRONIC DEVICE FOR TRANSMITTING OR RECEIVING SIGNAL AND METHOD THEREFOR

Samsung Electronics Co., ...

1. An electronic apparatus comprising:a communication circuit including a plurality of ports; and
a processor, wherein the processor is configured to:
obtain context information of the electronic apparatus;
determine at least one port to be used for each of at least one frequency band among the plurality of ports based on the obtained context information; and
transmit or receive a signal based on the determined at least one port,
wherein the context information includes at least one of sensor information of the electronic apparatus, peripheral device connection information, carrier aggregation (CA) mode information, or primary component carrier (PCC) or secondary component carrier (SCC) information, and
wherein the processor is further configured to determine another port when the sensor information is a second state, which is different from the at least one port to be used in the at least one frequency band when the sensor information is a first state.

US Pat. No. 10,924,151

TRANSMITTER DEVICE AND TRANSCEIVER DEVICE FOR TRANSMITTING DIFFERENT WIRELESS STANDARD SIGNAL

SAMSUNG ELECTRONICS CO., ...

1. A transmitter device configured to receive a first signal from a first base band modem at a first input port and to receive a second signal from a second baseband modem at a second input port comprising:an output port connected to an antenna;
a first impedance circuit configured to transfer the first signal to the output port in a first mode, and configured to transfer the second signal to the output port in a second mode;
a second impedance circuit connected to the first impedance circuit;
a first switch configured to selectively connect the second input port to the first impedance circuit; and
a second switch configured to selectively connect the second impedance circuit to a ground,
wherein, in the first mode, the second input port is disconnected from the first impedance circuit, and the second impedance circuit is connected to the ground; and
wherein, in the second mode, the second input port is connected to the first impedance circuit, and the second impedance circuit is disconnected from the ground.

US Pat. No. 10,924,150

UNIVERSAL MOBILE DEVICE CASES AND METHODS OF MAKING SAME

ADVANCED WIRELESS INNOVAT...

1. An expandable case for a mobile device comprising:a rectangular shaped back with a long axis and a short axis;
a plurality of non-expandable components configured to form the rectangular shaped back wherein a subset of the plurality of non-expandable components curve around to form sides of the expandable case;
a plurality of expandable components that couple the non-expandable components together to form the rectangular shaped back wherein at least one expandable component is configured to allow expansion of the rectangular shaped back along the long axis and at least one expandable component is configured to allow expansion of the rectangular shaped back along a short axis; and,
a window located at a top of the back wherein the window extends a full width of the rectangular shaped back and at least a quarter of the way down from a top of the rectangular shaped back.

US Pat. No. 10,924,148

BUMPERBAND AND CLAMSHELL ASSEMBLY FOR PROTECTING A CELL PHONE SUBHOUSING

Greenmo, Inc., Takoma Pa...

1. A two-piece assembly for protecting a smartphone subhousing formed in a generally flat rectangular structure including a display screen having a surface and a bezel on a frontal surface thereof, a generally flat battery on a portion of a rear side of the subhousing, a stepped ridge extending around peripheral edges of the subhousing and a number of I/O switches and connections disposed at various locations about said peripheral edges, said two-piece assembly comprising:a band of material to encircle peripheral edges of said subhousing thereby forming a bumperband that protects the subhousing from impact forces, said bumperband including an inwardly facing groove structure that enables the bumperband to clamp against both the bezel and the stepped ridge of said subhousing, a raised screen bumper protruding above and to protect the surface of said display screen, and a downwardly protruding perimeter flange that forms a perimeter gap having opposing parallel sidewalls between said bumper band and the subhousing, and
a clamshell backing to cover the rear of said subhousing, said clamshell backing including an upwardly protruding lip having parallel sidewalls substantially complementary to the parallel sidewalls of said perimeter gap and adapted to be frictionally coupled substantially inside said perimeter gap between the subhousing and bumperband when press-fitted with the subhousing and bumperband whereby the perimeter gap and upwardly protruding lip establish a three-part frictionally coupled interconnected sealing relationship between and among said subhousing, bumperband and clamshell backing.

US Pat. No. 10,924,147

WEARABLE DEVICE FOR TRANSMITTING A MESSAGE COMPRISING STRINGS ASSOCIATED WITH A STATE OF A USER

Samsung Electronics Co., ...

1. A wearable device worn on a user, the wearable device comprising:a sensor configured to detect data related to a state of the user; and
at least one processor configured to:
determine a movement of the user,
for a respective determined movement, present, at the wearable device, at least one word from a plurality of words based on the detected data related to the state of the user for the respective determined movement, and
transmit, from the wearable device to a receiver device, a message having contents associated with the determined movement, after the at least one word is presented at the wearable device.

US Pat. No. 10,924,146

TECHNIQUES FOR CONTROLLING SPECIFIC ABSORPTION RATE OF RADIO ENERGY TRANSMISSION

Apple Inc., Cupertino, C...

1. A radio device, comprising:a plurality of radio entities configured to transmit radio energy; and
a controller configured to control the radio energy transmission of the plurality of radio entities to comply with a predefined Specific Absorption Rate (SAR) requirement, to assign time quotas to the plurality of radio entities over multiple time windows,
wherein the controller is configured to enable at least two radio entities of the plurality of radio entities operating concurrently based on a shared SAR transmission power restriction which allows the at least two radio entities transmitting concurrently up to a 100% duty cycle without violating the SAR requirement.

US Pat. No. 10,924,144

WIRELESS CODED COMMUNICATION (WCC) DEVICES WITH POWER HARVESTING POWER SOURCES

1. A device, comprising,a persistent memory,
a flat antenna,
a microcontroller; and
a power source configured to generate power in response to energy harvesting that is facilitated using the flat antenna, the power being transferred to a power storage of the device such that when the power storage has an amount of power the microcontroller performs processing of a part of a task resulting in state data related to the task stored to the persistent memory in response to a first cycle of energy harvesting, wherein in response to one or more additional cycles of energy harvesting, the device continues performance of the task by retrieving the state data for the part of the task from the persistent memory and resulting in assembly of a payload that is sent to an end node via a wireless transmission.

US Pat. No. 10,924,142

RF LEVEL DETECTION FOR DESIRED CHANNEL AMONG MULTIPLE BROADCAST CHANNELS

NXP B.V., Eindhoven (NL)...

1. An method comprising:demodulating a broadcast signal associated with a radio-frequency (RF) transmission, using a bandwidth setting for a desired channel that is among a plurality of broadcast channels and, in response, provide a first frequency-selective demodulated and provide a magnitude indication of a second demodulated signal that is less frequency selective than the first frequency-selective demodulated signal;
using a level estimation circuit to assess a running representation of the magnitude indication over time; and
controlling a speed or rate at which the level estimator assesses the running representation based on a degree of deviation or offset as indicated by the first frequency-selective demodulated signal relative to a carrier frequency used for the broadcast signal.

US Pat. No. 10,924,141

SYSTEMS AND METHODS FOR CANCELLATION OF PASSIVE INTERMODULATION (PIM) FOR A WIRELESS NETWORK RECEIVER

Ubiqam Ltd., Petach-Tikv...

1. A passive intermodulation (PIM) mitigation module for mitigating PIM within a receiver of a wireless network, the PIM mitigation module comprising:at least one processor executing a code for:
receiving transmit signals transmitted by at least one transmission source;
receiving received signals received by at least one reception source;
computing a plurality of synthetic PIM signals from the transmit signals, wherein each of the plurality of synthetic PIM signals is a respective combination of a plurality of frequency components of the transmit signals;
computing a plurality of mitigation weights for mitigating the plurality of synthetic PIM signals; and
performing a PIM mitigation process on the received signals with the plurality of mitigation weights to generate clean signals to provide to the receiver; wherein the plurality of synthetic PIM signals are computed by combinations of frequency bands selected from a plurality of the at least one transmission source denoting a predicted reflection of the transmit signals off at least one non-linear PIM reflection element that is received by the at least one reception source.

US Pat. No. 10,924,136

TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD

SONY CORPORATION, Tokyo ...

1. A transmission device, comprising:an encoding unit configured to
perform LDPC coding for information bits with an information length K=N×r to generate an extended LDPC code having parity bits with a parity length M=N+L?K on a basis of an extended parity check matrix having rows and columns each extended by a puncture length L with respect to a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 9/16, and
puncture a head of the information bits of the extended LDPC code by the puncture length L to generate a punctured LDPC code with the code length N of 69120 bits and the coding rate r of 9/16, wherein
the puncture length L is 1080,
the LDPC code includes the information bits and the parity bits,
the extended parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,
the information matrix portion is represented by a parity check matrix initial value table, and
the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is
723 781 1388 3060 4271 7280 7468 9021 9753 10185 12643 12901 13575 13809 14285 14478 15069 16467 18290 18505 19022 19472 20759 22172 27104 28752 29835 30831 31309
1620 1897 3433 6033 6981 7135 9050 9376 10666 13610 14319 15116 17381 17760 20227 21874 23357 24234 24522 25925 26353 26967 28227 28506 29251 29441 30060 30986 31091
1697 2272 3024 5561 6589 7986 8685 9396 10573 12011 14098 16126 16759 16804 18059 18547 20087 20914 21286 21538 22540 24458 26648 27340 28792 28826 29864 30528 31295
89 454 483 695 2280 2835 3144 4970 6829 9853 12615 15904 16729 20640 23848 27573 29312
4591 6748 11640 13018 14778 15843 17885 18377 20224 21833 22954 23726 25488 27761 28222 29259 29778
242 710 1570 2623 3133 3257 4453 7853 16055 16408 17180 20157 20277 21448 22859 25006 31218
2004 5038 5159 8471 10803 11018 15651 17765 20995 24165 24257 24306 26164 27463 28488 28826 29380
755 3621 4468 6694 6756 14092 14129 14400 15017 20052 22490 23042 24698 28425 28541 30045 30486
7 621 1211 4098 11752 12080 13227 15004 17359 18687 23170 23479 24501 27042 27466 28238 29909
553 6987 8440 9596 11059 11853 12271 14413 14912 16736 16982 17615 20918 22586 25528 29158 29838
6199 6384 7031 7628 19831 20096 22240 22968 23198 23811 24453 24846 24971 26366 27747 29215 30861
396 2135 2913 5364 8082 9967 13434 17293 19440 19687 23273 27397 28840 29333 29392 29683 30223
586 5373 11840 14118 14170 15300 18550 20804 22553 27032 27283 28385
217 2802 5004 12123 13048 15986 19677 21659 22175 22394 23718 24128
648 1958 3508 5127 9238 11939 13886 18348 19773 23638 26227 30729
3893 8133 8600 10046 12651 18576 18665 19209 20689 25078 28352 28524
3026 5164 13169 14079 15656 16754 17794 20083 20246 23872 26005 30450
4851 4882 5925 8452 10057 11070 11725 21083 23252 29070 30608 31252
6688 8303 8582 8764 15723 16277 17054 18883 22842 22940 23539 28970
9607 11750 15772 16971 17190 20592 23323 26419 26898 27490 29091 29399
1012 2607 7224 8102 8817 9674 9770 17979 18893 24996 29668 31315
3584 17014 31265
12000 17144 24886
6902 18241 20350
1199 2754 24431
13260 17335 22894
8888 19827 24948
9274 13805 28264
433 14041 14952
5363 10179 31256
9154 12640 25511
14335 22293 30957
8842 19987 27063
16410 16593 23534
4822 5664 17535
1475 16019 26422
7252 21940 29278
8782 11586 15476
1052 9697 24777
10191 15809 18930
2986 3032 17552
5657 11833 16001
4179 5130 31086
1758 22168 29270
3084 6131 25691
9333 11079 24520
1967 12799 16145
11440 15981 19796
468 6793 14919
9093 13955 30797
17173 25766 27476
4582 4809 10147
5963 17543 21876
14180 15874 28620
17016 24149 30556
14738 17104 17948
15634 17778 22335
728 14554 23232
5991 10705 11245
8045 23380 30580
5686 24591 26518
5591 11501 11609
4343 12894 18875
22562 24339 29973
8746 9630 26437
5229 10200 14780
24267 25130 30609
15 1383 3794
13327 24877 28195
8574 24293 26737
9336 9730 19754
2068 6710 23636
11845 12387 13435
4795 18096 25579
590 12684 13811
1349 8518 29460
963 18419 22976
3057 19095 26881
4734 6527 20320
17454 21268 24658
6077 19792 26610
4466 14709 27325
6137 15076 24579
6449 19034 19754
4950 17466 25784
1057 9565 21979
11834 14753 16610
10460 13992 25301
5035 25738 26623
2092 20670 21405
11911 21918 24068
3653 3719 21050
2096 13350 28971
15322 20225 26055
16987 23172 23946
13424 15893 25683
9347 16252 23298
2203 8155 11928
568 2107 10649
13204 17014 17260
12178 12279 21289
17601 21051 28415
2662 16039 19981
21552 25872 30771
14456 19097 28700
12805 17154 26223
1670 13112 13857
6983 15456 16578.

US Pat. No. 10,924,134

APPARATUS AND METHOD FOR CHANNEL CODING IN COMMUNICATION SYSTEM

HUAWEI TECHNOLOGIES CO., ...

1. A device in a wireless communication network, comprising:a processor, a memory and a transceiver;wherein the processor, by executing program instructions stored in the memory, is configured to:obtain an input sequence, wherein the input sequence comprises K bits of information, and K is a positive integer;
determine a lifting factor Z according to K;
encode the input sequence using an encoding matrix H, to obtain an encoded sequence; and
output the encoded sequence for transmission by the transceiver;wherein the encoding matrix H is obtained from a low density parity check (LDPC) base graph by replacing each element of the LDPC base graph with a matrix of Z rows and Z columns;wherein the LDPC base graph comprises m rows and n columns, 5?m?46, and 27?n?68, and each element in the LDPC base graph has a value of 0 or 1;wherein an element in the LDPC base graph has a value of 1 when:i=0, j=0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, or 23;
i=1, j=0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, or 24;
i=2, j=0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, or 25;
i=3, j=0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, or 25;
i=4, j=0, 1, or 26;wherein i is a row index of the LDPC base graph, 0?i?m, j is a column index of the LDPC base graph, 0?j

US Pat. No. 10,924,133

REDUCING CONTROL CHANNEL OVERHEAD USING POLAR CODES

1. A system, comprising:a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
determining locations of frozen bits in a first control channel information block, wherein the locations of the frozen bits are determined based on a type of polar code;
coding non-frozen bits of the first control channel information block with a first portion of scheduling data that facilitates decoding a second control channel information block; and
coding the frozen bits of the first control channel information block with a second portion of the scheduling data that facilitates decoding the second control channel information block.

US Pat. No. 10,924,131

ELECTRONIC DEVICE AND METHOD FOR COMPRESSING SAMPLED DATA

1. A system for compressing data sampled from an analog waveform signal, the system comprising:a track and hold unit configured to receive one or more analog waveform input signals, sample the one or more analog waveform input signals, and output a stream of DC voltage levels from the one or more analog waveform input signals;
an analog to digital converter configured to receive the stream of DC voltage levels and convert the DC voltage levels into a stream of sampled data points, each data point being a numeric value that varies according to the DC voltage level; and
a data compression unit configured to:
receive the stream of data points,
calculate a slope for each data point in succession, the slope being a value of a change between the data point and its successive data point, and
output the data point when the slope changes in value from a previous data point.

US Pat. No. 10,924,129

TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER DEVICE AND ASSOCIATED CONTROL METHOD

MEDIATEK INC., Hsin-Chu ...

1. A time-interleaved analog-to-digital converter device, comprising:a random number generator, configured to generate a random number sequence;
a plurality of analog-to-digital converters (ADCs), coupled to the random number generator, configured to receive an analog input signal to generate a plurality of digital signals, respectively, wherein each ADC is further configured to generate a selection signal according to the random number sequence; and
an output circuit, coupled to the plurality of ADCs, configured to select one of the digital signals according to the selection signals generated by the ADCs, to generate a digital output signal;
wherein only one of the selection signals respectively generated by the ADCs has an enablement state at a same time, and the output circuit selects the digital signal generated by the ADC whose selection signal has the enablement state.

US Pat. No. 10,924,128

VCO-BASED CONTINUOUS-TIME PIPELINED ADC

ANALOG DEVICES INTERNATIO...

1. A pipelined analog-to-digital converter (ADC), comprising:a continuous-time residue generation front end to quantize an analog input signal, and to generate a first digital signal and an amplified residue signal;
a voltage-controlled-oscillator (VCO) ADC back end to quantize the amplified residue signal, and to generate a second digital signal; and
a digital signal reconstruction filter to filter the first digital signal and the second digital signal, and to generate a final digital signal.

US Pat. No. 10,924,127

GENERATING A CONTROL SEQUENCE FOR QUANTUM CONTROL

Quantum Valley Investment...

1. A system comprising:a quantum system comprising qubits;
a control system configured to:
receive an input signal;
generate a control signal in response to the input signal, and
apply the control signal to the quantum system; and
a computing system comprising one or more processors configured to perform operations comprising:
accessing a quantum system model that represents the quantum system, the quantum system model comprising a control parameter representing the control signal;
accessing a distortion model representing a non-linear relationship between the control signal and the input signal;
defining a target operation to be applied to one or more of the qubits by operation of the control system; and
generating a control sequence comprising a sequence of values for the input signal, the control sequence generated based on the target operation, the quantum system model and the distortion model.

US Pat. No. 10,924,123

PHASE-LOCKED LOOP (PLL) WITH DIRECT FEEDFORWARD CIRCUIT

TEXAS INSTRUMENTS INCORPO...

1. A device comprising:a phase offset detector having a first input, a second input, and an error signal output, the first input is adapted to be coupled to a feedback clock signal generator and the second input is adapted to be coupled to a reference clock signal generator;
a charge pump having an input and an output, the input of the charge pump is coupled to the error signal output of the phase offset detector;
a feedforward circuit having an input and an output, the input of the feedforward circuit is coupled to the error signal output of the phase offset detector;
an integrator having a first input, a second input and an output, the first input of the integrator is coupled to the output of the charge pump and the second input of the integrator is coupled to the output of the feedforward circuit; and
a voltage-controlled oscillator (VCO) having an input coupled to the output of the integrator.

US Pat. No. 10,924,122

METHOD AND SYSTEM FOR PHASE ALIGNMENT OF MULTIPLE PHASED LOCKED LOOPS

Telefonaktiebolaget LM Er...

1. A system for phase alignment of three or more phase adjustable Phased Locked Loops (PLLs), the system comprising:a plurality N of PLLs, wherein N?3 and each PLL comprises:
an oscillator configured to generate a respective output signal;
a frequency divider configured to generate a respective feedback signal by dividing the respective output signal;
a phase comparator arrangement configured to output a respective control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal;
a plurality N of phase detectors, wherein successive ones of the plurality N of PLLs are connected, to each of the plurality N of phase detectors, in a loop such that:
an i-th phase detector is configured to receive an i-th feedback signal generated from the i-th PLL and an (i+1)-th feedback signal generated from the (i+1)-th PLL, wherein i=1, 2, 3, . . . N?1; and
the N-th phase detector is configured to receive the first feedback signal generated from the first PLL and the N-th feedback signal generated from the N-th PLL;
wherein the i-th phase detector is configured to generate an i-th adjustment signal indicating an i-th phase difference between the i-th and (i+1)-th feedback signals for adjusting a phase of the i-th or (i+1)-th PLL;
wherein the N-th phase detector is configured to generate a N-th adjustment signal indicating a N-th phase difference between the first and N-th feedback signal; and
wherein no phase detector receives feedback signals from the same two PLLs.

US Pat. No. 10,924,121

NO FALSE LOCK DLL

Shenzhen Goodix Technolog...

1. A DLL circuit, comprising:a multiplexer;
a delay line,
wherein the multiplexer is configured to cause the delay line to receive a first input clock input to the DLL circuit, and to generate a plurality of output clocks each having a phase based on the first input clock and on a delay of the delay line, wherein the delay of the delay line is controlled at least partly by a sensed phase difference between the first input clock and a particular one of the output clocks,
wherein the multiplexer is further configured to cause the delay line to receive a second input clock, wherein the second input clock is generated based on one of the output clocks, wherein the delay line is configured to generate the output clocks such that the phase of each of the output clocks is based on the received second input clock and on the delay of the delay line, and wherein the delay of the delay line is controlled at least partly by a sensed frequency difference between the first input clock and the second input clock; and
an edge combiner, configured to generate a DLL output clock based on the output clocks generated by the delay line.

US Pat. No. 10,924,120

FINE GRANULARITY IN CLOCK GENERATION

Advanced Micro Devices, I...

1. An oscillator circuit comprising:a phase-locked loop (PLL) having a PLL frequency and a plurality of voltage controlled oscillator (VCO) phase outputs;
a clock divider circuit receiving the VCO phase outputs from the PLL and producing a first stage clock signal at an adjustable frequency related to the PLL frequency and based on selecting a combination of multiple selected VCO phase outputs, the first stage clock signal having a balanced duty cycle at frequencies that are related to the PLL frequency by even fractional divisions of a VCO phase output period based on a number of the quantity VCO phase outputs, and an unbalanced duty cycle at frequencies that related by odd fractional divisions of the VCO clock period;
an enable pattern generator producing a control signal fed to the clock divider circuit and an enable signal indicating an odd fractional division of the PLL frequency is desired; and
a duty cycle adjustment (DCA) circuit receiving the first stage clock signal and the enable signal, and in response to a first value of the enable signal, operates in a first mode which reproduces the first stage clock signal at a second stage clock signal output, and in response to a second value of the enable signal, operates in a second mode which adjusts a falling edge of the first stage clock signal to provide an even duty cycle and feeds a resulting signal to the second stage clock signal output.

US Pat. No. 10,924,119

CLOCK DATA RECOVERY CIRCUIT AND APPARATUS INCLUDING THE SAME

Samsung Electronics Co., ...

1. A clock data recovery circuit configured to receive an input data signal including an embedded clock signal, the clock data recovery circuit comprising:a clock recovery circuit including a phase detector configured to detect a phase of the embedded clock signal and to generate a recovery clock signal from the input data signal based on the detected phase; and
a data recovery circuit configured to generate a recovery data signal from the input data signal by using the recovery clock signal,
wherein the phase detector circuit comprises:
a sampling latch circuit configured to output a first sample signal from the input data signal at a first edge of a first reference clock signal in a period from the first edge of the first reference clock signal to a second edge of the first reference clock signal and output a second sample signal from the input data signal at a first edge of a second reference clock signal having a predetermined phase difference from the first reference clock signal in a period from the first edge of the second reference clock signal to a second edge of the second reference clock signal; and
an edge detection circuit configured to generate a phase control signal based on the first sample signal and the second sample signal and output the phase control signal in a period in which the second sample signal is output from the sampling latch circuit.

US Pat. No. 10,924,118

POSITIVE FEEDBACK XOR/XNOR GATE AND LOW-DELAY HYBRID LOGIC ADDER

Ningbo University, Zheji...

1. A positive feedback XOR/XNOR gate, comprising:a first PMOS (P-type metal-oxide-silicon) transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS (N-type metal-oxide-silicon) transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor,
wherein a gate of the first PMOS transistor, a drain of the second PMOS transistor and a gate of the first NMOS transistor are connected at a first input terminal of the positive feedback XOR/XNOR gate, and a first input signal of the positive feedback XOR/XNOR gate is provided to the first input terminal of the positive feedback XOR/XNOR gate;
a source of the first PMOS transistor, a source of the second PMOS transistor, a drain of the first NMOS transistor, a gate of the third PMOS transistor, a gate of the third NMOS transistor and a drain of the fourth NMOS transistor are connected at an XOR logic output terminal of the positive feedback XOR/XNOR gate, and the XOR logic output terminal of the positive feedback XOR/XNOR gate outputs an XOR logic value;
a gate of the second PMOS transistor, a drain of the first PMOS transistor and a gate of the second NMOS transistor are connected at a second input terminal of the positive feedback XOR/XNOR gate, and a second input signal of the positive feedback XOR/XNOR gate is provided to the second input terminal of the positive feedback XOR/XNOR gate;
an operation voltage is provided to a source of the third PMOS transistor;
a drain of the third PMOS transistor, a drain of the third NMOS transistor and a gate of the fourth NMOS transistor are connected at an XNOR logic output terminal of the positive feedback XOR/XNOR gate, and the XNOR logic output terminal of the positive feedback XOR/XNOR gate outputs an XNOR logic value;
a source of the first NMOS transistor and a drain of the second NMOS transistor are connected; and
a source of the second NMOS transistor, a source of the third NMOS transistor and a source of the fourth NMOS transistor are grounded.

US Pat. No. 10,924,116

ANALOG SWITCH MULTIPLEXER SYSTEMS AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. A motor controller system comprising:a plurality of field effect transistors (FETs) configured to be operatively coupled with one or more phases of a motor, each of the plurality of FETs comprising a gate;
an analog switch multiplexer coupled with each of the gates of the plurality of FETs and with an analog output; and
a digital control block coupled with the analog switch multiplexer and configured to send a multiplexer select control signal to the analog switch multiplexer in response to receiving a serial peripheral interface signal.

US Pat. No. 10,924,113

DYNAMIC CALIBRATION OF FREQUENCY AND POWER STORAGE INTERFACE

WESTERN DIGITAL TECHNOLOG...

1. A data storage device, comprising:one or more memory devices;
a comparator;
a plurality of latches coupled to the comparator; and
a controller coupled to the one or more memory devices, the controller comprising:
a host interface for coupling the data storage device to a host device;
a memory interface for coupling the one or more memory devices to the controller;
a voltage regulator;
an interface timing adjustment engine, wherein the interface timing adjustment engine is configured to adjust a frequency of a timing signal; and
one or more of:
an internal inputs monitor;
a host inputs module;
a device lifetime monitor;
a temperature sensor; and
a voltage sensor,
wherein the controller is configured to:
adjust one or more of the frequency of the timing signal or a voltage of the memory interface within a constraint and based upon information received from one or more of the internal inputs monitor, host inputs module, device lifetime monitor, temperature sensor, and voltage sensor;
determine values for maximum read and write frequencies;
determine values for minimum read and write frequencies;
determine maximum power for read and write voltages;
decrease frequency and increase voltage;
calibrate maximum frequency for read and write;
check for errors on one or more transmitted patterns over the memory interface;
determine a first data pattern at a first frequency;
determine a second data pattern at a second frequency;
determine, using the plurality of latches working in conjunction with the controller, whether the first data pattern equals the second data pattern;
increase the first frequency if the first data pattern equals the second data pattern; and
decrease the first frequency if the first data pattern does not equal the second data pattern.

US Pat. No. 10,924,112

BANDGAP REFERENCE CIRCUIT

EMEMORY TECHNOLOGY INC., ...

1. A bandgap reference circuit, comprising:a mirroring circuit generating a first current, a second current and a third current, wherein the first current flows to a first node, the second current flows to a second node, and the third current flows to an output terminal of the bandgap reference circuit;
an input circuit connected with the first node to receive the first current and connected with the second node to receive the second current; and
an operation amplifier, wherein a positive input terminal of the operation amplifier is connected with the first node, a negative input terminal of the operation amplifier is connected with the second node, and an output terminal of the operation amplifier is connected with the mirroring circuit, wherein the operation amplifier comprises:
a first PMOS transistor, wherein a source terminal of the first PMOS transistor receives a power supply voltage, and a gate terminal of the first PMOS transistor receives a first bias voltage;
a second PMOS transistor, wherein a source terminal of the second PMOS transistor is connected with a drain terminal of the first PMOS transistor, and a gate terminal of the second PMOS transistor receives a second bias voltage;
a first NMOS transistor, wherein a drain terminal of the first NMOS transistor is connected with a drain terminal of the second PMOS transistor, and a gate terminal of the first NMOS transistor receives a third bias voltage;
a second NMOS transistor, wherein a drain terminal of the second NMOS transistor is connected with a source terminal of the first NMOS transistor, a gate terminal of the second NMOS transistor is connected with the drain terminal of the second PMOS transistor, and a source terminal of the second NMOS transistor is connected with a ground terminal;
a third PMOS transistor, wherein a source terminal of the third PMOS transistor receives the power supply voltage, and a gate terminal of the third PMOS transistor receives the first bias voltage;
a fourth PMOS transistor, wherein a source terminal of the fourth PMOS transistor is connected with a drain terminal of the third PMOS transistor, a gate terminal of the fourth PMOS transistor receives the second bias voltage, and a drain terminal of the fourth PMOS transistor is the output terminal of the operation amplifier;
a third NMOS transistor, wherein a drain terminal of the third NMOS transistor is connected with a drain terminal of the fourth PMOS transistor, and a gate terminal of the third NMOS transistor receives the third bias voltage;
a fourth NMOS transistor, wherein a drain terminal of the fourth NMOS transistor is connected with a source terminal of the third NMOS transistor, a gate terminal of the fourth NMOS transistor is connected with the gate terminal of the second NMOS transistor, and a source terminal of the fourth NMOS transistor is connected with the ground terminal;
a fifth NMOS transistor, wherein a drain terminal of the fifth NMOS transistor is connected with the drain terminal of the first PMOS transistor, and a gate terminal of the fifth NMOS transistor is the positive input terminal of the operation amplifier;
a sixth NMOS transistor, wherein a drain terminal of the sixth NMOS transistor is connected with a drain terminal of the third PMOS transistor, and a gate terminal of the sixth NMOS transistor is the negative input terminal of the operation amplifier; and
a reference current source, wherein a first terminal of the reference current source is connected with a source terminal of the fifth NMOS transistor and a source terminal of the sixth NMOS transistor, and a second terminal of the reference current source is connected with the ground terminal.

US Pat. No. 10,924,111

INPUT DEVICE WITH FUNCTION TRIGGERING OR CONTROL WHICH TAKES PLACE BASED ON CAPACITIVELY MEASURED ACTUATION FORCE AND ADAPTATION BY MEANS OF CAPACITIVE CONTACT DETECTION

PREH GMBH

1. An input device, comprising:a capacitive force sensor;
a capacitive touch sensor assigned to the capacitive force sensor; and
an evaluation circuit,
wherein the capacitive force sensor includes an operating surface and a first electrode made out of a conductive material, which yields elastically under an action of an operating force acting upon the operating surface during an operation, and a second electrode made out of a conductive material, which is disposed adjacent to and spaced apart from the first electrode,
wherein the evaluation circuit is configured to detect, in a touch-detection step, an associated characteristic value of a touch on the operating surface during the operation, the associated characteristic value including at least one of a location or a surface of action of the touch, from the capacitive touch sensor, and
wherein the evaluation circuit is further configured to detect, in an operation-detection step shifted in time in relation to the touch-detection step, a measured quantity changing with the operating force by generating a first measuring capacitance between the first and second electrodes and to assign a switching or controlling function to the operation, both in accordance with the characteristic value detected by the capacitive touch sensor in the touch-detection step and in accordance with the measured quantity detected in the operation-detection step,
wherein the evaluation circuit is configured to adapt, in accordance with the characteristic value, a threshold for triggering the switching or controlling function in accordance with the measured quantity, and
wherein the characteristic value is related to at least one of the location or a contact surface of the touch.

US Pat. No. 10,924,108

CIRCUIT ARRANGEMENT WITH GALVANIC ISOLATION BETWEEN ELECTRONIC CIRCUITS

Infineon Technologies Aus...

1. A circuit arrangement, comprising:a first electronic circuit;
a second electronic circuit; and
a coupling circuit connected between the first electronic circuit and the second electronic circuit,
wherein the first electronic circuit is at least partially integrated in a first region of a semiconductor layer,
wherein the second electronic circuit is at least partially integrated in a second region of the semiconductor layer,
wherein the second region adjoins a first insulating layer formed on a first surface of the semiconductor layer and is electrically insulated from the first region by a second insulating layer, and
wherein the coupling circuit is arranged in a third insulating layer formed on a second surface of the semiconductor layer and comprises at least two capacitors connected in series.

US Pat. No. 10,924,107

LOW STATIC CURRENT SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising: a power transistor and a driving circuit coupled to the power transistor; wherein:the driving circuit comprises a first stage, a second stage, a third stage, and a fourth stage;
the first stage comprises an enhancement-mode high-electron-mobility transistor (HEMT) and a depletion-mode HEMT;
the second stage is coupled between the first stage and the power transistor;
the third stage is coupled between the first and second stages;
the fourth stage is coupled between the first and third stages.

US Pat. No. 10,924,106

MILLER TRANSITION CONTROL GATE DRIVE CIRCUIT

GENERAL ELECTRIC COMPANY,...

1. A circuit, comprising:a first switching device coupled to a load;
a first voltage source configured to generate an electrical signal at a voltage level at least equal to a threshold voltage of the first switching device;
a second switching device between the first switching device and the first voltage source, wherein the second switching device is configured to provide a shaped current to the first switching device in response to a control signal, wherein the shaped current is generated based at least in part on the electrical signal generated by the first voltage source, and wherein the shaped current actuates the first switching device; and
a resistor-capacitor (RC) circuit configured to shape the shaped current by changing a duration of the electrical signal, an amplitude of the electrical signal, a shape of the electrical signal, or any combination thereof.

US Pat. No. 10,924,103

DRIVER CIRCUITRY

Kabushiki Kaisha Toshiba,...

1. A driver circuitry comprising:a voltage application circuitry which is connected to a drive terminal of a transistor, and controls a voltage of an input signal and applies to the drive terminal;
a current detection circuitry which is connected to an output terminal of the transistor, and detects that a current output from the transistor becomes a size of a predetermined current or more;
a control circuitry which is connected to the current detection circuitry, and controls the voltage application circuitry based on the voltage of the input signal to output a voltage between the drive terminal and the output terminal at a timing when the current detection circuitry detects the current of the predetermined current or more;
a current source which outputs a current;
a first switch which is connected to the drive terminal and the current source, and switches a connection state between the current source and the drive terminal;
a second switch which is connected to the drive terminal, and switches a connection state with the drive terminal while being synchronized with the first switch; and
a differential amplifier circuitry whose input side is connected to the output terminal through the second switch, and to the current source through the first switch and the second switch, and whose output side is connected to the control circuitry, and which outputs a potential difference between an electric potential at the current source and an electric potential at the output terminal to the control circuitry, wherein:
the control circuitry acquires the voltage between the drive terminal and the output terminal based on the potential difference output by the differential amplifier circuitry.

US Pat. No. 10,924,101

DETERMINISTIC SHUTDOWN OF POWER MODULE

1. A method of operating a semiconductor device, the method comprising:measuring a temperature within a source region of the semiconductor device;
measuring at the semiconductor device an amount of current associated with a short circuit external to the semiconductor device;
determining a particular distribution of the amount of current between the two regions of the semiconductor device; and
shutting off the semiconductor device to cause the particular distribution of current between the two regions of the semiconductor device.

US Pat. No. 10,924,100

METHOD OF OPERATING H-BRIDGE CIRCUITS AND CORRESPONDING DRIVER DEVICE

STMicroelectronics S.r.l....

1. A method for driving an H-bridge circuit, wherein the H-bridge circuit comprises:a supply node configured to be coupled to a supply voltage as well as a first pair of transistors and a second pair of transistors, each pair of transistors including a first transistor and a second transistor,
wherein: the first transistors in the two pairs of transistors have the current paths therethrough included in respective current flow lines between the supply node and a first output node and between the supply node and a second output node, respectively, and the second transistors in the two pairs of transistors have the current paths therethrough coupled to a third output node and a fourth output node, respectively, the first output node and the third output node mutually isolated from each other and the second output node and the fourth output node mutually isolated from each other,
the method comprising:
selecting operation of said H-bridge circuit in one of a plurality of modes, the plurality of modes comprising a first mode, a second mode and a third mode, wherein:
i) operating in the first mode comprises:
shorting the first output node to the third output node to provide a first output terminal and shorting the second output node to the fourth output node to provide a second output terminal,
arranging the second transistors in the two pairs of transistors with the current paths therethrough coupled between the first output terminal and the second output terminal, respectively, and ground, and
wherein an inter-output-terminal electrical load coupled between the first output terminal and the second output terminal is traversed by currents flowing therethrough in opposite directions as a result of the first transistor in the first pair of transistors and the second transistor in the second pair of transistors and the first transistor in the second pair of transistors and the second transistor in the first pair of transistors being made conductive, respectively;
ii) operating in the second mode comprising:
arranging the second transistors in the two pairs of transistors with the current paths therethrough coupled between the third output node and ground and between the fourth output node and ground, respectively,
wherein a first inter-output-node electrical load and a second inter-output-node electrical load are coupled between the first output node and the third output node and between the second output node and the fourth output node, respectively, with the first inter-output-node electrical load and the second inter-output-node electrical load configured to be electrically supplied as a result of the first transistor and the second transistor in the first pair of transistors being made conductive and the first transistor and the second transistor in the second pair of transistors being made conductive, respectively;
iii) operating in the third mode comprising:
coupling the third output node and the fourth output node to a respective supply voltage,
arranging the second transistors in the two pairs of transistors with the current paths therethrough coupled to respective ground-referred loads referred to ground opposite said third output node and said fourth output node, with said respective ground-referred loads configured to be electrically supplied as a result of the second transistor in the first pair of transistors and the second transistor in the second pair of transistors being made conductive,
coupling a first output-node load to said first output node, with said first output load configured to be electrically supplied as a result of the first transistor in the first pair of transistors being made conductive; and
coupling a second output-node load to said second output node, with said second output-node load configured to be electrically supplied as a result of the first transistor in the second pair of transistors being made conductive.

US Pat. No. 10,924,097

SHIFTER CIRCUITS HAVING REGISTERS ARRANGED IN A FOLDED TOPOLOGY

Micron Technology, Inc., ...

1. An apparatus comprising:a shifter configured to receive a command signal at an input node and provide the command signal at an output node a delay time after receiving the command signal, wherein the shifter comprises:
an input register coupled to the input node and configured to receive the command signal from the input node;
an output register coupled to output node and configured to provide the command signal to the output node; and
a plurality of registers arranged in series between the input register and the output register, wherein the apparatus is configured to propagate the command signal through a variable number of the plurality of registers between the input register and the output register, and wherein the variable number is based on a control signal received by the shifter.

US Pat. No. 10,924,095

MULTI-RESONANT COUPLING ARCHITECTURES FOR ZZ INTERACTION REDUCTION

INTERNATIONAL BUSINESS MA...

1. A device, comprising:a first qubit;
a second qubit; and
a multi-resonant architecture comprising a first resonator that capacitively couples the first qubit to the second qubit and a second resonator that capacitively couples the first qubit to the second qubit.

US Pat. No. 10,924,094

PULSE WIDTH MODULATION CONTROL CIRCUIT AND CONTROL METHOD OF PULSE WIDTH MODULATION SIGNAL

Power Forest Technology C...

1. A pulse width modulation control circuit, comprising:a phase-locked loop clock generating circuit, generating a phase-locked loop clock according to a display synchronization signal;
a counter circuit, coupled to the phase-locked loop clock generating circuit and generating a count value according to the phase-locked loop clock, wherein the counter circuit is not coupled to an edge detector, and the counter circuit automatically resets the count value by presetting a reset period of the counter circuit equal to a signal cycle of the display synchronization signal, wherein the reset period of the counter circuit meets a form of 2 N, and N=3; and
a comparison circuit, coupled to the counter circuit and generating a pulse width modulation signal to control a display period of a display frame by comparing a difference between the count value associated with the display synchronization signal and a duty ratio set value associated with the display period of the display frame,
wherein the comparison circuit determines whether the count value associated with the display synchronization signal is less than the duty ratio set value associated with the display period of the display frame,
wherein the comparison circuit sets the pulse width modulation signal to a high level while the count value associated with the display synchronization signal is less than the duty ratio set value associated with the display period of the display frame.

US Pat. No. 10,924,093

INTEGRATED CIRCUIT WITH FINFETS HAVING DUMMY STRUCTURES

NXP USA, Inc., Austin, T...

1. A circuit comprising:a plurality of voltage supply terminals including a lowest voltage supply terminal;
an N-type finFET transistor including at least one semiconductor fin, a gate structure made of a gate material located over the at least one fin, and an end structure of the gate material located over an end of the at least one fin, the at least one fin located over a well region, the finFET including a source electrode and a drain electrode, the end structure electrically tied to the well region;
a current path electrically coupled to the lowest voltage supply terminal, where the N-type finFET transistor is located in the current path, wherein the well region is not electrically tied to the lowest voltage supply terminal.

US Pat. No. 10,924,092

COMBINING VOLTAGE RAMPS TO CREATE LINEAR VOLTAGE RAMP

Silanna Asia Pte Ltd, Si...

1. A ramp generator comprising:an output node at which an output voltage ramp signal is produced, the output voltage ramp signal having first continuous ramp periods and second continuous ramp periods that alternate with each other, the first continuous ramp periods being produced from first preliminary ramp periods of a first preliminary voltage ramp signal during first time periods, the second continuous ramp periods being produced from second preliminary ramp periods of a second preliminary voltage ramp signal during second time periods, and the first and second time periods alternating with each other;
a first preliminary ramp node at which the first preliminary voltage ramp signal is generated, and which is periodically electrically connected to the output node during the first time periods, each of the first preliminary ramp periods having a first preliminary voltage ramp that continuously ramps during and beyond the first time periods; and
a second preliminary ramp node at which the second preliminary voltage ramp signal is generated, and which is periodically electrically connected to the output node during the second time periods, each of the second preliminary ramp periods having a second preliminary voltage ramp that continuously ramps during and beyond the second time periods.

US Pat. No. 10,924,091

IMMEDIATE FAIL DETECT CLOCK DOMAIN CROSSING SYNCHRONIZER

STMICROELECTRONICS INTERN...

1. A synchronizer circuit comprising:a first synchronizer having a first input for receiving a signal associated with a first clock signal, a second input for receiving a second clock signal, and an output for providing a synchronizer circuit output signal;
a second synchronizer having a first input for receiving the signal associated with the first clock signal, a second input for receiving the second clock signal, and an output;
a detection stage having a first input coupled to the output of the first synchronizer and to the output of the second synchronizer, a second input for receiving the second clock signal, and an output; and
a fault output stage having a first input coupled to the detection stage, a second input for receiving the second clock signal, and an output for providing a fault output signal.

US Pat. No. 10,924,089

COMPARING CIRCUIT AND COMPARING MODULE WITH HYSTERESIS

FARADAY TECHNOLOGY CORPOR...

1. A comparing circuit with hysteresis, comprising:an input circuit, comprising:
a first input transistor, configured for receiving a reference voltage; and
a second input transistor, configured for receiving a comparison voltage;
an external circuit, comprising:
a first external transistor, electrically connected to the first input transistor through a first terminal; and
a second external transistor, electrically connected to the second input transistor through a second terminal; and
a coupling module, comprising:
a first current amplification circuit, comprising:
a first coupling transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the first coupling transistor is electrically connected to the first terminal, and the control terminal of the first coupling transistor is selectively electrically connected to either one of the first terminal and the second terminal; and
a second coupling transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the second coupling transistor is electrically connected to the second terminal, and the control terminal of the second coupling transistor is selectively electrically connected to either one of the first terminal and the second terminal; and
a second current amplification circuit, comprising:
a third coupling transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the third coupling transistor is selectively electrically connected to either one of the first terminal and the second terminal, and the control terminal of the third coupling transistor is electrically connected to the second terminal; and
a fourth coupling transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the fourth coupling transistor is selectively electrically connected to either one of the first terminal and the second terminal, and the control terminal of the fourth coupling transistor is electrically connected to the first terminal.

US Pat. No. 10,924,088

OPTICAL PULSE TO VOLTAGE SIGNAL CONVERTER

Rockwell Collins, Inc., ...

1. An optical pulse to voltage signal converter, comprising:a photodetector configured to generate a stream of current pulses by converting a stream of optical pulses received from a pulsed optical source;
a front-end circuit, comprising:
a tunable loading network configured to convert a stream of current pulses into a stream of input voltage signals;
at least one tunable voltage source configured to generate at least one stream of signals with at least one select voltage; and
at least one amplifier coupled to the at least one tunable voltage source, the at least one amplifier configured to compare the stream of input voltage signals and the at least one stream of signals with the at least one select voltage to generate at least one stream of output voltage signals with a select duty-cycle phase and a select duty-cycle resolution,
the select duty-cycle phase being dependent on a set of operational parameters of the tunable loading network and the at least one tunable voltage source,
the select duty-cycle resolution being dependent on a number of steps within at least one conversion stage defined by the at least one tunable voltage source; and
a signal processor, the at least one amplifier further configured to output the at least one stream of output voltage signals to the signal processor.

US Pat. No. 10,924,086

SURFACE ACOUSTIC WAVE (SAW) DEVICE WITH ANTIREFLECTIVE STRUCTURE

Qorvo US, Inc., Greensbo...

1. A device comprising:a piezoelectric substrate comprising:
a front-side surface; and
a back-side surface;
an interdigital transducer (IDT) on the front-side surface of the piezoelectric substrate;
an antireflective structure on at least a portion of the back-side surface of the piezoelectric substrate; and
a dielectric compound on the antireflective structure.

US Pat. No. 10,924,085

GUIDED ACOUSTIC WAVE DEVICE

Qorvo US, Inc., Greensbo...

1. A guided acoustic wave device comprising:a substrate comprising one of quartz and silicon;
a lithium tantalate layer on the substrate, the lithium tantalate layer having a crystalline orientation defined by (YXl)?°, where ? is between 10° and 37°; and
a transducer on the lithium tantalate layer.

US Pat. No. 10,924,082

ACOUSTIC WAVE DEVICE AND MANUFACTURING METHOD FOR SAME

MURATA MANUFACTURING CO.,...

1. An acoustic wave device comprising:a piezoelectric substrate including an electrode formation surface; and
an IDT electrode provided on the electrode formation surface of the piezoelectric substrate; wherein
the IDT electrode includes a close contact layer located on the electrode formation surface of the piezoelectric substrate, and a main electrode layer located on the close contact layer;
the close contact layer includes a first layer in close contact with the piezoelectric substrate, and a second layer in close contact with the main electrode layer;
the first layer includes a first lateral surface, and the second layer includes a second lateral surface;
at least portions of each of the first and second lateral surfaces are inclined relative to a normal direction of the electrode formation surface, and an area of a surface of the second layer that is in close contact with the main electrode layer is smaller than an area of a surface of the first layer that is in close contact with the piezoelectric substrate; and
angles defined by the inclined portions of each of the first and second lateral surfaces with respect to the normal direction of the electrode formation surface are inclination angles of each of the first and second lateral surfaces, and the inclination angle of the second lateral surface is smaller than the inclination angle of the first lateral surface.

US Pat. No. 10,924,081

SUBSTRATE FOR A TEMPERATURE-COMPENSATED SURFACE ACOUSTIC WAVE DEVICE OR VOLUME ACOUSTIC WAVE DEVICE

Soitec, Bernin (FR)

1. A surface acoustic wave device, comprising:a piezoelectric layer;
a stiffening substrate, wherein a ratio of a thickness of the piezoelectric layer to a thickness of the stiffening substrate is less than or equal to 0.125;
a semiconductor layer disposed between the piezoelectric layer and the stiffening substrate; at least two interdigitated metallic comb electrodes on a surface of the piezoelectric layer for generating or receiving surface acoustic waves at the surface of the piezoelectric layer;
a first dielectric layer between the piezoelectric layer and the semiconductor layer; and
a charge-trapping layer at an interface between the first dielectric layer and the semiconductor layer and/or an interface between the first dielectric layer and the piezoelectric layer.

US Pat. No. 10,924,080

ACOUSTIC WAVE DEVICE, HIGH FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION DEVICE

MURATA MANUFACTURING CO.,...

1. An acoustic wave device comprising:a supporting substrate;
an acoustic reflection film provided on the supporting substrate;
a piezoelectric body provided on the acoustic reflection film; and
an interdigital transducer electrode provided on the piezoelectric body; wherein
the acoustic reflection film is a multilayer body including a plurality of acoustic impedance layers including a low acoustic impedance layer whose acoustic impedance is relatively low and a high acoustic impedance layer whose acoustic impedance is relatively high; and
the acoustic reflection film includes a first acoustic impedance layer and a second acoustic impedance layer, the first acoustic impedance layer being one of the plurality of acoustic impedance layers, the second acoustic impedance layer being one of the plurality of acoustic impedance layers and having an arithmetic average roughness different from an arithmetic average roughness of the first acoustic impedance layer.

US Pat. No. 10,924,077

LOW COMPLEXITY LOUDNESS EQUALIZATION

OmniVision Technologies, ...

10. A method of audio adjustment, comprising:capturing a sound input signal and generating sound data with a microphone, wherein the sound input signal has an amplitude that changes with respect to time, and the sound input signal includes one or more frequencies, and wherein the sound data indexes the amplitude with respect to the time;
receiving the sound data from the microphone with a controller coupled to the microphone;
adjusting using the controller, the amplitude of the sound input signal included in the sound data, across the one or more frequencies using a filter disposed in logic of the controller while the amplitude is indexed with respect to the time, wherein the filter has dynamic coefficients Cn(V) of an order n that are functions of the amplitude of the sound input signal, wherein Cn(V) is given by:
Cn(V)=Cn,0+Cn,1V+Cn,2V2+ . . . +Cn,p?1Vp?1,
wherein V is the sound input signal, p is an integer, and Cn,j, j=0, 1, . . . , p?1 are polynomial coefficients; and
outputting filtered sound data.

US Pat. No. 10,924,073

TRANSMISSION DEVICE AND TRANSMISSION/RECEPTION SYSTEM

THINE ELECTRONICS, INC., ...

1. A transmission device comprising:a signal transmitter configured to transmit differential signals from a pair of output terminals that are respectively connected to differential signal lines; and
a request receiver configured to be a receiver into which to input a request signal that makes a request to send out the differential signals for adjusting an offset when differential signal sampling is performed in a reception device that is connected through the differential signal lines,
wherein the signal transmitter includes a current mode driver, and a common voltage of the pair of output terminals is constant over a state where no electric power is supplied to the transmission device and a powered-down state; and
wherein the signal transmitter sends out differential signals of a differential 0 V to the reception device based on the request signal that is input into the request receiver.

US Pat. No. 10,924,072

POWER AMPLIFICATION CIRCUIT

MURATA MANUFACTURING CO.,...

1. A power amplification circuit, comprising:a first amplification transistor that has a first terminal, a second terminal, and a first control terminal, that is configured to perform power amplification on a high-frequency signal input from the first control terminal, and that is configured to output the high-frequency signal on which the power amplification has been performed from the first terminal;
a variable voltage power supply configured to supply a variable voltage to the first terminal;
a bias circuit configured to output a direct current (DC) bias current; and
a current limiting circuit configured to limit the DC bias current,
wherein the bias circuit comprises a constant current amplification transistor that has a third terminal, a fourth terminal, and a second control terminal and that is configured to output the DC bias current from the fourth terminal to the first control terminal, and
wherein the current limiting circuit comprises:
a current limiting transistor that has a fifth terminal, a sixth terminal, and a third control terminal, the sixth terminal being connected to the fourth terminal;
a first resistance element having a first end connected to the fifth terminal and having a second end connected to the variable voltage power supply; and
a second resistance element having a first end connected to the third control terminal and having a second end connected to the second control terminal.

US Pat. No. 10,924,071

SEMICONDUCTOR DEVICE

Murata Manufacturing Co.,...

1. A semiconductor device comprising:a semiconductor substrate including a principal surface that is parallel to a plane defined by a first direction and a second direction substantially orthogonal to the first direction, the principal surface including a first side that is parallel to the first direction;
first unit transistors, each of which is configured to amplify a first signal in a first frequency band to output a second signal; and
second unit transistors, each of which is configured to amplify the second signal to output a third signal,
wherein, on the semiconductor substrate,
the second unit transistors are aligned in the second direction between the first side and a substrate center line in the first direction of the semiconductor substrate in plan view of the principal surface, and
the first unit transistors are aligned such that a first center line in the first direction of a region in which the first unit transistors are aligned is farther from the first side than a second center line in the first direction of a region in which the second unit transistors are aligned.

US Pat. No. 10,924,070

HIGH-FREQUENCY MODULE AND COMMUNICATION DEVICE

MURATA MANUFACTURING CO.,...

1. A high-frequency module comprising:a filter unit including a plurality of filters;
a switch unit connected to the filter unit and including a switch configured to switch a high-frequency signal to pass though one of the plurality of filters;
an amplifying unit configured to amplify the high-frequency signal passing through the filter unit;
a matching unit connected between the filter unit and the amplifying unit and configured to perform impedance matching of the amplifying unit; and
a multilayer substrate provided with the filter unit, the switch unit, the amplifying unit, and the matching unit,
wherein the switch unit and the amplifying unit are provided with one semiconductor chip component including a first region and a second region separated by a ground,
the amplifying unit is provided in the first region,
the switch unit is provided in the second region,
the matching unit is provided on one main surface of the multilayer substrate, and
the one semiconductor chip component is provided on another main surface or in or on an inner layer of the multilayer substrate.

US Pat. No. 10,924,069

SYSTEM AND METHOD FOR LOW DISTORTION CAPACITIVE SIGNAL SOURCE AMPLIFIER

INFINEON TECHNOLOGIES AG,...

1. An integrated circuit for amplifying a signal provided by a capacitive signal source, the integrated circuit comprising:a signal amplifier comprising an input node configured to be coupled to the capacitive signal source;
a controllable attenuation circuit coupled to the input node of the signal amplifier;
a single-ended to differential conversion circuit having an input coupled to an output of the signal amplifier, wherein the single-ended to differential conversion circuit is configured to convert a single-ended signal at the output of the signal amplifier to a differential signal at a first output node and a second output node of the single-ended to differential conversion circuit;
a peak detector coupled to the first output node and the second output node of the single-ended to differential conversion circuit, wherein the peak detector comprises a positive peak detector and a negative peak detector;
a comparator coupled to an output of the positive peak detector and an output of the negative peak detector, wherein the comparator is configured to compare an output of the peak detector with a threshold, and the comparator comprises a differential comparator configured to compare the output of the positive peak detector with a positive threshold, and the output of the negative peak detector with a negative threshold; and
a control circuit coupled between an output of the comparator and a control input of the controllable attenuation circuit.

US Pat. No. 10,924,068

DIGITAL PREDISTORTION CALIBRATION

TEXAS INSTRUMENTS INCORPO...

11. A wireless communication device comprising:transmission circuitry;
receiver circuitry coupled to the transmission circuitry by a feedback loop, the receiver circuitry to receive pulses transmitted by the transmission circuitry;
an accumulator component coupled the receiver circuitry to receive samples output by the receiver circuitry;
a processor coupled to the transmission circuitry and to the accumulator component; and
a non-transitory computer readable storage medium storing a program for digital predistortion (DPD) calibration for execution by the processor, the program including instructions to:
transmit, by the transmission circuitry, a plurality of pulses, wherein each particular pulse of the plurality of pulses to an amplitude step in an interlaced pattern of alternating higher and lower amplitude steps separated by silence gaps, wherein each of the alternating higher amplitude steps is higher than a previous higher amplitude step and each of the alternating lower amplitude steps is lower than a previous lower amplitude step, and wherein at least one silence gap of the silence gaps separates each of the alternating higher and lower amplitude steps;
receive each particular pulse in the receiver circuitry via the feedback loop;
generate, by the accumulator component, an accumulated sample for each particular pulse based on a plurality of samples output by the receiver circuitry for the particular pulse; and
compute amplitude dependent gain (AM/AM) and amplitude dependent phase shift (AM/PM) values for each accumulated sample.

US Pat. No. 10,924,067

POWER AMPLIFIER CIRCUIT

MURATA MANUFACTURING CO.,...

1. A power amplifier circuit comprising:an amplifier transistor having a base or a gate to which an input signal is supplied, and having a collector or a drain from which an amplified signal is output, the amplified signal being obtained by amplifying the input signal;
a bias circuit configured to supply a bias current or a bias voltage to the base or the gate of the amplifier transistor; and
a resistance element connected in series between the base of the amplifier transistor and the bias circuit, or between the gate of the amplifier transistor and the bias circuit, wherein:
the bias circuit comprises:
a voltage generation circuit configured to generate a first direct-current voltage in accordance with a control signal;
a first transistor having a base or a gate to which the first direct-current voltage is supplied, and having an emitter or a source from which the bias current or the bias voltage is supplied to the base or the gate of the amplifier transistor via the resistance element;
a second transistor having a base or a gate to which a second direct-current voltage is supplied, and having an emitter or a source connected to the emitter or the source of the first transistor;
a signal supply circuit disposed between the base or the gate of the second transistor and a supply path of the input signal to the amplifier transistor, the signal supply circuit being configured to supply the input signal to the base or the gate of the second transistor; and
an impedance circuit disposed between the base or the gate of the first transistor and the base or the gate of the second transistor,
when the power amplifier circuit operates in a first mode, the voltage generation circuit is configured to be kept in an on state by the control signal, and
when the power amplifier circuit operates in a second mode, the voltage generation circuit is configured to be kept in an off state by the control signal, the second mode being a mode in which a power level of the amplified signal is less than a power level of the amplified signal in the first mode.

US Pat. No. 10,924,066

OFFSET VOLTAGE TRIMMING FOR OPERATIONAL AMPLIFIERS

SEMICONDUCTOR COMPONENTS ...

1. An operational amplifier comprising:a first differential pair of pMOS transistors, the first differential pair biased by a first bias current that has a first portion that is constant with temperature and a second portion that is proportional to absolute temperature, a ratio of the first and second portions generating a first transconductance of the first differential pair that is substantially constant for temperatures over a range;
a second differential pair of nMOS transistors, the second differential pair biased by a second bias current that has a first portion that is constant with temperature and a second portion that is proportional to absolute temperature, a ratio of the first and second portions generating a second transconductance of the second differential pair that is substantially constant for temperatures over the range; and
a comparator that activates either the first differential pair or the second differential pair based on an input voltage at an input.

US Pat. No. 10,924,065

METHOD FOR CONFIGURING POWER IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREOF

Samsung Electronics Co., ...

1. An electronic device, comprising:an antenna array comprising a first antenna element and a second antenna element;
a communication circuit comprising a first power amplifier connected to the first antenna element and a second power amplifier connected to the second antenna element;
a processor operatively connected to the communication circuit; and
a memory operatively connected to the processor and stores instructions, when executed, cause the processor to:
output a first signal through the first antenna element with a first gain of the first power amplifier,
output a second signal through the second antenna element with a second gain of the second power amplifier, and
change the second gain of the second power amplifier based on a difference between a first transmit power corresponding to the first signal and a second transmit power corresponding to the second signal.

US Pat. No. 10,924,064

BIAS CIRCUIT

SUMITOMO ELECTRIC INDUSTR...

1. A bias circuit configured to supply a gate bias voltage for performing on-off control of an amplifier, to the amplifier, the bias circuit comprising:a first power source connected in series to a gate terminal of the amplifier and configured to output a voltage required for a first gate bias voltage for turning the amplifier to an ON state;
a second power source connected in series to the gate terminal of the amplifier and configured to output a voltage required for a second gate bias voltage for turning the amplifier to an OFF state;
a changeover switch connected between the first power source and the amplifier and configured to supply either the first gate bias voltage or the second gate bias voltage to the amplifier by switching a state between the first power source and the amplifier to either an open state or a short-circuit state on the basis of a control signal related to on-off control of the amplifier; and
a resistance value varying unit connected between the second power source and the amplifier and configured such that a resistance value thereof is variable.

US Pat. No. 10,924,063

COUPLING A BIAS CIRCUIT TO AN AMPLIFIER USING AN ADAPTIVE COUPLING ARRANGEMENT

Analog Devices Internatio...

1. A radio frequency device, comprising:a bias network for an amplifier, the bias network including:
a bias circuit, configured to generate a bias signal for the amplifier, and
a coupling circuit, configured to couple the bias circuit to the amplifier to enable provision of the bias signal to the amplifier,
wherein:
the coupling circuit includes a transistor and a resistor,
the resistor is coupled between a source terminal and a drain terminal of the transistor,
a first source or drain (S/D) terminal of a pair of the source terminal and the drain terminal of the transistor is to couple to an input of the amplifier and a second S/D terminal of the pair is to couple to an output of the bias circuit, and
the coupling circuit is configured so that, during operation, a current between the first S/D terminal and the second S/D terminal of the transistor is dependent on a power level of an input signal to be amplified by the amplifier.

US Pat. No. 10,924,062

POWER AMPLIFYING APPARATUS HAVING BIAS BOOSTING STRUCTURE WITH IMPROVED LINEARITY

Samsung Electro-Mechanics...

1. A power amplifying apparatus comprising:a first bias circuit configured to generate a first bias current by adding a boost current to a base bias current generated from a reference current;
a first amplification circuit configured to receive the first bias current and amplify a signal input through an input terminal of the first amplification unit to output a first amplified signal; and
a bias boosting circuit configured to generate the boost current based on a magnitude of a harmonic component in the amplified signal output from the first amplification circuit.

US Pat. No. 10,924,061

LOW-NOISE LOW-EMISSION CRYSTAL OSCILLATOR AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A crystal oscillator comprising:an inverter configured to receive a first voltage at a first node and output a second voltage at a second node; a feedback network inserted between the first node and the second node, the feedback network comprising a parallel connection of a first branch and a second branch, the first branch comprising a first diode and a second diode stacked up in a forward direction, the second branch comprising a third diode and a fourth diode stacked up in a reverse direction;
a crystal inserted between a fourth node and a fifth node, wherein the fourth node is coupled to the second node, and the fifth node is coupled to the first node;
a first shunt capacitor inserted between the fourth node and a ground node; and
a second shunt capacitor inserted between the fifth node to and the ground node.

US Pat. No. 10,924,060

ULTRA-LOW-POWER OSCILLATOR WITH DC-ONLY SUSTAINING AMPLIFIER

THE REGENTS OF THE UNIVER...

1. An oscillator apparatus, comprising:a resonator configured for oscillating and generating resonator current at an oscillation frequency;
at least one down-converter coupled to a first side of said resonator, said at least one down-converter configured for converting resonator current into direct current (DC);
at least one direct current (DC) amplifier circuit, having at least one feedback resistance between its input and output, wherein said direct current (DC) amplifier circuit is configured for amplifying the DC current into an amplified DC signal;
wherein said feedback resistor of the direct current (DC) amplifier circuit has a resistance that exceeds the resistive loss of said resonator; and
at least one up-converter coupled to a second side of said resonator;
wherein said at least one up-converter is configured for up-converting the amplified signal back into an oscillation frequency to output an oscillation signal.

US Pat. No. 10,924,059

MULTI-ELEMENT RESONATOR

Futurewei Technologies, I...

1. An oscillator circuit, comprising:a resonant tank including a first capacitor formed on a semiconductor substrate, a first inductor formed on the semiconductor substrate, the first inductor is a tapped inductor having at least a first tapped input terminal at an intermediate location between inductor ends, a first inverter connected to the first tapped input terminal, a second capacitor formed on the semiconductor substrate, and a second inductor formed on the semiconductor substrate, the second inductor is a tapped inductor having at least a second tapped input terminal at an intermediate location between inductor ends, a second inverter connected to the second tapped input terminal, the first capacitor, the first inductor, the second capacitor, and the second inductor connected in an alternating ring configuration with each capacitor connected between and in series with a pair of the inductors and each inductor connected between and in series with a pair of the capacitors; and
an amplifier circuit coupled to the resonant tank and configured to amplify a signal in the resonant tank.

US Pat. No. 10,924,058

LOCAL OSCILLATOR DISTRIBUTION FOR A MILLIMETER WAVE SEMICONDUCTOR DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:providing, to a transmitter splitter, a first signal having a wavelength ?;
providing, to a receiver splitter, a second signal having the wavelength ?;
providing, by the transmitter splitter, a plurality of transmitter signals, wherein each of the transmitter signals has the wavelength ?; and
providing, by the receiver splitter, a plurality of receiver signals, wherein each of the receiver signals has the wavelength ?;
wherein the first signal is provided over a first line having a length of ?/X, wherein X is an integer from 4 to 32, inclusive; the second signal is provided over a second line having a length of ?/Y, wherein Y is an integer from 4 to 32, inclusive; or both.

US Pat. No. 10,924,057

SNOW SHEDDING APPARATUS AND METHOD OF USING SAME

NORWICH TECHNOLOGIES, INC...

1. A device, comprising:at least one photovoltaic (PV) module comprising a plurality of PV cells which are electrically interconnected and encapsulated in a frame having a transparent front surface configured to admit light, said frame representing an impediment to the sliding of snow on said transparent front face; and
a structure configured to be attached to said at least one PV module,
said structure comprising an element that covers said frame of said at least one PV module and extends from said frame of said at least one PV module onto said transparent front surface of said at least one PV module, said element having a first surface that sits flush against said transparent front surface, and a second surface being disposed at an acute angle relative to said transparent front surface without either of said first surface and said second surface covering any of the PV cells in said PV module
said structure configured to allow snow on said transparent front surface to slide off said at least one PV module.

US Pat. No. 10,924,056

METHOD AND APPARATUS FOR CLEANING SURFACES

AIRTOUCH SOLAR LTD., Tel...

1. A surface cleaning device for cleaning a surface of a solar panel, wherein the surface cleaning device comprises:a first dust carrying member;
a second dust carrying member;
a motor; and
a motion delay assembly;
wherein the first dust carrying member and the second dust carrying member are coupled to the motor;
wherein the motor is configured to cyclically move the first dust carrying member and the second dust carrying member along a path;
wherein the motion delay assembly is configured to cyclically introduce a momentarily delay in a progress of the first dust carrying member along the path, while the second dust carrying member contacts the surface thereby reducing a gap between the first dust carrying member and the second dust carrying member and induce air to exit the gap and progress along the surface and remove dust that precedes the second dust carrying member
wherein surface cleaning device is configured to position the motion delay assembly at a first position when the surface cleaning device propagates towards one end of the surface and is configured to position the motion delay assembly at a second position when the surface cleaning device propagates towards another end of the surface;
wherein when positioned in the first position the motion delay assembly is within a reach of the first dust carrying member; and
wherein when positioned at the second position the motion delay assembly is outside the reach of the first dust carrying member.

US Pat. No. 10,924,055

MOTOR DRIVE APPARATUS HAVING INPUT POWER SUPPLY VOLTAGE ADJUSTMENT FUNCTION

FANUC CORPORATION, Yaman...

1. A motor drive apparatus, comprising:an AC stabilized power supply configured to convert AC voltage of a commercial AC power source into input power supply voltage and output the input power supply voltage;
a converter configured to convert the input power supply voltage into DC voltage and output the DC voltage to a DC link;
an inverter configured to convert the DC voltage at the DC link into AC voltage for driving a motor and output the AC voltage; and
an input power supply voltage control unit configured to control the input power supply voltage that is output by the AC stabilized power supply according to heat generated by at least one of the converter, the inverter or the motor.

US Pat. No. 10,924,054

FAILURE DIAGNOSIS METHOD FOR INVERTER CIRCUIT

NIDEC ELESYS CORPORATION,...

1. A failure diagnosis method for an inverter circuit, the failure diagnosis method comprising:a first monitoring step of monitoring an inter-terminal voltage between a high-potential-side terminal and a low-potential-side terminal of each of a plurality of driving devices included in the inverter circuit;
a second monitoring step of monitoring a power supply voltage of the inverter circuit; and
a determination step of determining whether there is a failure in each of the plurality of driving devices based on a value of the inter-terminal voltage and a value of the power supply voltage.

US Pat. No. 10,924,053

METHOD FOR REMOTE SUPPORT OF ELECTRIC DRIVE APPARATUS

ABB Schweiz AG, Baden (C...

1. A method comprising:starting in a first apparatus a remote support tool application, said first apparatus having a connection with an at least one electric drive apparatus in a local site;
forwarding by said first apparatus an indication of a configuration parameter data user interface of said first apparatus to a third apparatus in a remote site; and
receiving by said first apparatus from said third apparatus at least one tagged version of a screen of the configuration parameter data user interface of said first apparatus, the at least one tagged version of the screen including a page tag and parameter values.

US Pat. No. 10,924,052

MOTOR CONTROL SYSTEM WITH PHASE CURRENT POLARITY DETECTION

Allegro MicroSystems, LLC...

1. A system for driving a motor, comprising:a motor driver having a plurality of switches coupled to the motor to drive a current through each of a plurality of phase coils of the motor;
a circuit configured to detect a polarity of the current in one or more of the phase coils of the motor and to generate a polarity value representative of the detected current polarity, wherein the circuit comprises at least one comparator having a first input coupled to a node between two of the plurality of switches, a second input coupled to receive a threshold value and an output at which the polarity value is provided; and
a controller configured to provide a plurality of pulse width modulated (PWM) output control signals coupled to the plurality of switches to control the switches to drive the current through the plurality of phase coils of the motor, wherein the controller is configured to alter a duty cycle of the plurality of PWM output control signals to modify a voltage applied to the plurality of phase coils of the motor in response to the polarity value.

US Pat. No. 10,924,051

METHOD FOR ADJUSTING A POWER ELECTRONICS UNIT

AUDI AG, Ingolstadt (DE)...

1. A method for adjusting a modulation of at least one electrical operating parameter of at least one component of a power electronics unit comprising:operating an electric machine of a vehicle supplied by the power electronics unit, and
adjusting the modulation,
wherein a modulation method is selectable by a user from a plurality of modulation methods for carrying out the modulation,
wherein a degree of modulation is adjusted by the user for carrying out the modulation,
wherein the degree of modulation relates to an efficiency and acoustic output of the at least one component of the power electronics unit, so that an increase of the degree of modulation by the user corresponds to an increase of the efficiency and acoustic output of the at least one component of the power electronics unit and a decrease of the degree of modulation by the user corresponds to a decrease of the efficiency and acoustic output of the at least one component of the power electronics unit,
wherein the plurality of modulation methods from which the user selects comprises at least one of a discontinuous modulation method, a space-vector modulation method, and a sinusoidal triangular modulation method.

US Pat. No. 10,924,050

MOTOR CONTROL CIRCUIT AND MOTOR CONTROLLER

MITSUMI ELECTRIC CO., LTD...

1. A motor control circuit comprising:a control circuit configured to output a pulse width modulation signal for controlling a switching operation of an inverter circuit, the inverter circuit being configured to supply an alternating current power to a motor; and
a speed-change detecting circuit configured to:
detect a change in a speed command signal, the change in the speed command signal being a difference between a pre-change speed command signal used before the speed command signal changes and a post-change speed command signal used immediately after the pre-change speed command signal, and
in response to the difference meeting or exceeding a predetermined limit, output a signal indicating that the speed command signal has changed to the control circuit to cause the control circuit to change a duty cycle of the pulse width modulation signal, the speed command signal specifying a target value of a rotational speed of the motor.

US Pat. No. 10,924,049

CONTROL METHOD FOR OSCILLATING MOTORS AND AN OSCILLATING MOTOR

Jiankun Hu, Shenzhen (CN...

1. A control method for oscillating motor, the oscillating motor comprises a U-shaped magnetic yoke, a control unit, an oscillating arm oscillating around a fulcrum, a second magnetic yoke and four permanent magnets; the U-shaped magnetic yoke has a first support leg and a second support leg, and the first support leg and the second support leg are respectively wound with coils; the control unit is electrically connected with coils and produces alternating pulses to generate alternating magnetic poles on the end faces of the two supporting legs of the U-shaped magnetic yoke; the oscillating arm extends outward from the end face direction of the U-shaped magnetic yoke and is bounded by the fulcrum, the end of the oscillating arm close to the U-shaped magnetic yoke is an inner arm, the end of the oscillating arm away from the U-shaped magnetic yoke is an outer arm; the second magnetic yoke is installed at the end of the inner arm close to the U-shaped magnetic yoke; the permanent magnets are fixedly installed on the second magnetic yoke; the four permanent magnets are arranged side by side in sequence, they are: a first permanent magnet, a second permanent magnet, a third permanent magnet and a fourth permanent magnet, according to the arrangement order; the outer end faces of the first permanent magnet and the fourth permanent magnet are of the same polarity, and the outer end faces of the second permanent magnet and the third permanent magnet are of the same polarity; and the outer end faces of the first permanent magnet and the second permanent magnet are of the opposite polarity and arranged corresponding to the end face of the first support leg; the outer end faces of the third permanent magnet and the fourth permanent magnet are of the opposite polarity and arranged corresponding to the end face of the second support leg; there is an air gap between the end faces of the permanent magnets and their corresponding support legs, and alternating magnetic poles generated by the two supporting legs of the U-shaped magnetic yoke cause the permanent magnets, the second magnetic yoke and the oscillating arm to reciprocate;characterized in that:
setting pulse parameters;
the control unit outputs alternating pulses with corresponding pulse widths and frequencies according to the set pulse parameters, so that the oscillating arm oscillates in an oscillation mode corresponding to the pulse parameters; wherein the oscillation mode comprises at least one of a full-amplitude oscillation mode, a sub-amplitude oscillation mode, an in-situ shaking mode and a composite oscillation mode, wherein the composite oscillation mode is generated by superposition of the full-amplitude oscillation mode and the in-situ shaking mode, or is generated by superposition of the sub-amplitude oscillation mode and the in-situ shaking mode.

US Pat. No. 10,924,048

INVERTER CONTROL DEVICE, MOTOR DRIVE DEVICE, AND ELECTRIC POWER STEERING APPARATUS

HITACHI AUTOMOTIVE SYSTEM...

1. An inverter control device comprising:at least first and second inverters;
a current detector that detects a current flowing through a main circuit of the first inverter;
a current controller that generates a voltage command value of the first inverter on the basis of a detected current and a current command; and
a voltage command predictor that generates a voltage command value of the second inverter on the basis of a variation of the voltage command value of the first inverter.

US Pat. No. 10,924,047

CONTROL DEVICE FOR THREE-PHASE ROTARY MACHINE

DENSO CORPORATION, Kariy...

1. A control device for a three-phase rotary machine,the three-phase rotary machine including two sets of three-phase windings and being configured to generate torque being a sum of magnet torque and reluctance torque when alternating currents with different phases are supplied to the two sets of three-phase windings,
the control device comprising:
two power converters that are provided corresponding to the two sets of three-phase windings and that output alternating currents with a same amplitude and a phase difference of (30±60×n) degrees to the two sets of three-phase windings, where n is an integer; and
a control unit that controls energization of the three-phase rotary machine by calculating a d-axis current and a q-axis current of a 6(2k+1)th component to be superimposed on a fundamental wave component on dq coordinates so as to reduce a peak value of phase current that is supplied to the two sets of three-phase windings, where k is an integer of 0 or larger,
wherein
when a ratio of an amplitude of the d-axis current of a 6(2k+1)th component to an amplitude of a q-axis current of the 6(2k+1)th component is defined as a high-order dq amplitude ratio,
the control unit calculates the d-axis current and the q-axis current of the 6(2k+1)th component so that the high-order dq amplitude ratio is 0 when a fundamental wave current amplitude is equal to or smaller than a first threshold, and the high-order dq amplitude ratio is 1 when the fundamental wave current amplitude is larger than a second threshold that is equal to or larger than the first threshold.

US Pat. No. 10,924,046

MOTOR DRIVEN POWER STEERING APPARATUS AND CONTROL METHOD THEREFOR

Hyundai Mobis Co., Ltd., ...

10. A control method for a motor driven power steering apparatus, comprising the steps of:receiving, by a motor control unit, a current command generated to operate a drive motor according to a driving condition of a vehicle from a steering logic unit;
receiving, by the motor control unit, a motor speed for sensing and outputting a rotation state of the drive motor; and
calculating, by the motor control unit, an output voltage from a voltage table according to current-speed based on the current command and the motor speed to output as a voltage command to operate the drive motor.

US Pat. No. 10,924,045

POWER GENERATION CONTROL SYSTEM, POWER GENERATION CONTROL DEVICE, AND EXTERNAL CONTROL DEVICE

Mitsubishi Electric Corpo...

1. A power generation control system, which is configured to simultaneously drive, by an internal combustion engine, a plurality of power generators mounted to the internal combustion engine, the power generation control system comprising:a power generation control device to control each of the plurality of power generators; and
an external control device connected to the power generation control device,
wherein the power generation control device includes:
a field driver to control supplying of a field current to a field coil provided to each of the plurality of power generators;
a voltage controller to determine a conduction rate of the field coil based on an output voltage of each of the plurality of power generators, to control the field driver, to thereby adjust the generated voltage of each of the plurality of power generators at a target voltage value;
a conduction rate detector to detect the conduction rate of the field coil of each of the plurality of power generators;
a first signal transmitter to transmit the conduction rate detected by the conduction rate detector to the external control device;
a first signal receiver to receive a command value for limiting the conduction rate of the voltage controller from the external control device; and
a conduction rate limiter to impose a limit on the conduction rate so as to set the conduction rate determined by the voltage controller to become equal to or smaller than the command value based on the command value received by the first signal receiver,
wherein the external control device includes:
a second signal receiver to receive the conduction rates of the field coils of each of the plurality of power generators, wherein each of the conduction rates has been detected by the conduction rate detector, from the power generation control device;
a conduction rate calculator to obtain an average value of the conduction rates of the field coils of each of the plurality of power generators, wherein the conduction rates have been received by the second signal receiver, to set the command value based on the average value; and
a second signal transmitter to transmit the command value set by the conduction rate calculator to the power generation control device, and
wherein the conduction rate calculator of the external control device is configured to set a power generator having a minimum conduction rate among the plurality of power generators as a power generator excluded from a limiting target based on the conduction rates of the field coils of each of the plurality of power generators, wherein the conduction rates have been received by the second signal receiver, set a power generator other than the power generator excluded from the limiting target among the plurality of power generators as a power generator of the limiting target, and transmit the command value to the power generation control device connected to the power generator of the limiting target via the second signal transmitter.

US Pat. No. 10,924,044

FEED-FORWARD CONTROL SYSTEM AND METHOD FOR GENSET QUICK COLD START

Cummins Power Generation ...

1. A method of reducing cold startup time of a genset for providing a requested power to a utility grid or load, the genset comprising an engine and a generator, the method comprising:determining if the genset is electrically coupled to a utility grid or load;
in response to determining the genset is electrically coupled to the utility grid or load, controlling a speed bias value based on a difference between a target power output and a current power output of the genset in response to the power being produced by the genset; and
controlling the power of the engine using the speed bias value.

US Pat. No. 10,924,043

GENERATOR SET EXERCISING SYSTEM

Cummins Power Generation ...

1. An apparatus, comprising:a control unit structured to
communicate with a first generator set, a second generator set, and a third generator set,
operate the first generator set as an output generator in an exercise mode, and
operate the second generator set and the third generator set as load generators in the exercise mode to use electrical power produced by the first generator set, the second generator set using a second genset portion of the electrical power and the third generator set using a third genset portion of the electrical power.

US Pat. No. 10,924,042

PNEUMATIC ENERGY HARVESTING AND MONITORING

The Boeing Company, Chic...

1. An apparatus comprising:an energy harvesting unit configured to generate electrical energy from a compressed gas in a pneumatic system;
a battery connected to the energy harvesting unit;
a sensor configured to detect a first parameter regarding operation of the energy harvesting unit; and
a controller connected to the sensor and the energy harvesting, unit, wherein:
the sensor and the controller are powered by the energy harvesting unit;
the controller is configured to control the energy harvesting unit and to process measurements for the first parameter detected by the sensor;
the controller is programmed with a learning system configured to:
diagnose an operational condition of the energy harvesting unit based on the measurements for the first parameter;
issue a command to the controller based on the operational condition; and
predict a charging capacity of the battery; and
at least one of:
predict a stiction of a valve body in the pneumatic system;
predict an amperage range overload for a solenoid in the pneumatic system; or
predict a flow capacity of a channel in the pneumatic system,
wherein:
the operational condition comprises a need for more power to be stored in the battery prior to ordinary recharging times and further includes use patterns of the pneumatic system; and
the command is to cause the energy harvesting unit to store energy in the battery,
wherein the controller is further configured to operate the pneumatic system to divert threshold amounts of power at multiple time intervals determined by the learning system.

US Pat. No. 10,924,041

MOTOR DRIVE SYSTEM INCLUDING POWER STORAGE DEVICE

Fanuc Corporation, Yaman...

1. A motor drive system comprising:a converter configured to convert power between AC power in a power source and DC power in a DC link;
an inverter for drive configured to convert power between the DC power in the DC link and AC power serving as one of drive power and regenerative power for a servomotor for drive;
a motor control unit for drive configured to control the servomotor for drive connected to the inverter for drive to operate the servomotor for drive in accordance with a predetermined operation pattern including a plurality of cycles where the servomotor is driven by the motor control unit such that the servomotor is active;
a power storage device configured to store the DC power from the DC link or supplies the DC power to the DC link; and
a determination unit configured to determine whether a holding energy of the power storage device is lower than a threshold for energy shortage determination defined in advance,
wherein when the determination unit determines that the holding energy is lower than the threshold for energy shortage determination, the motor control unit for drive controls the servomotor for drive by setting an additional standby period in between two sequential cycles of the plurality of cycles, during the additional standby period the motor control unit controls the servomotor to stop such that the servomotor is inactive, and
wherein the determination unit determines whether the holding energy of the power storage device is higher than a first threshold for restoration determination defined in advance, and an end point for the additional standby period set upon determination by the determination unit that the holding energy is lower than the threshold for energy shortage determination is set after the determination unit further determines that the holding energy is higher than the first threshold for restoration determination after determining that the holding energy is lower than the threshold for energy shortage determination.

US Pat. No. 10,924,040

OPERATIONAL MODE CONTROL OF A MOTOR

TEXAS INSTRUMENTS INCORPO...

1. A circuit device comprising:measurement logic operable to:
couple to a motor to measure a property associated with motion of the motor; and
provide a measurement signal based on the property;
pattern detection logic coupled to the measurement logic and operable to:
receive the measurement signal;
receive a pattern associated with the motion of the motor, wherein the motor operates in a plurality of commutation states during the motion and the pattern specifies a behavior of the measurement signal over a set of the plurality of commutation states and wherein the pattern specifies the behavior of the measurement signal over a set of contiguous states of the plurality of commutation states;
compare the measurement signal to the pattern; and
provide a mode control signal that specifies a mode of operation from a plurality of modes for control of the motion of the motor based on the comparison; and
control logic coupled to the pattern detection logic and the motor and operable to control the motion of the motor in the mode specified by the mode control signal.

US Pat. No. 10,924,039

MOTOR CONTROL DEVICE AND CONTROL METHOD FOR MOTOR CONTROL DEVICE

FANUC CORPORATION, Yaman...

1. A motor control device for controlling a servomotor so as to axially move a movement target object, comprising:a speed detector configured to detect a movement speed of the movement target object;
an abnormality detector configured to detect an abnormality of the speed detector;
a motor controller configured to perform deceleration control on the servomotor to decelerate the movement target object, upon detection of the abnormality;
a reference speed generator configured to generate a reference speed that decreases with passage of time, based on the movement speed when the movement target object decelerates and a predetermined deceleration;
a speed monitor configured to monitor the movement speed and determine whether or not the movement speed is equal to or greater than the reference speed, wherein the speed monitor is configured to make a determination by using an absolute value of the movement speed; and
a brake controller configured to actuate a brake for braking axial movement of the movement target object, when the movement speed is determined to be equal to or greater than the reference speed, wherein:
the speed monitor is further configured to determine whether or not an absolute value of a value obtained by subtracting the movement speed from the reference speed is equal to or greater than a threshold; and
the brake controller is configured to actuate the brake in a case where the absolute value of the value obtained by subtracting the movement speed from the reference speed is equal to or greater than the threshold even if it is determined that the movement speed is lower than the reference speed, wherein the motor controller is configured to stop the deceleration control of the servomotor when the movement speed is determined to be equal to or greater than the reference speed.

US Pat. No. 10,924,038

CAPACITIVE ACTUATOR MOTOR, CAPACITIVE ACTUATOR, AND CAPACITIVE ACTUATOR UNIT

SUMITOMO HEAVY INDUSTRIES...

1. An actuator, comprising:a capacitive actuator that comprises a plurality of actuator units; and
a motor output cam,
wherein each of the actuator units comprises:
an expandable element having capacitive properties;
a displacement expansion mechanism configured to convert displacement of the expandable element into an expanding displacement in a predetermined direction by generating a buckling phenomenon; and
an output transmission portion configured to transmit an output of the displacement expansion mechanism to the motor output cam;
wherein the motor output cam comprises a periodic shape portion with which the output transmission portion is in contact;
wherein the actuator further comprises an urger configured to always generate an urging force that causes the periodic shape portion and the output transmission portion to come into contact with each other; and
wherein the urging force is always a positive value such that the output transmission portion is pressed against the periodic shape portion regardless of a magnitude of the expanding displacement of the expandable element and the presence or absence of a voltage applied to the expandable element.

US Pat. No. 10,924,037

VIBRATION MOTOR THAT PREVENTS RESONANCE OF CONTACT MEMBER, AND ELECTRONIC APPARATUS

CANON KABUSHIKI KAISHA, ...

1. A vibration motor comprising:a vibrator having a piezoelectric element;
a contact member which is brought into friction contact with the vibrator; and
a fixing member to which the contact member is fixed, the vibration motor being configured to cause the vibrator and the contact member to move relative to each other in a first predetermined direction, by a high-frequency vibration of the piezoelectric element,
wherein the contact member comprises:
a sliding portion which is an area brought into friction contact with the vibrator when the vibrator and the contact member are caused to move relative to each other in the first predetermined direction; and
a fixed portion via which the contact member is fixed to the fixing member, and
wherein the fixed portion is formed at a location alongside the sliding portion in a second predetermined direction orthogonal to the first predetermined direction and orthogonal to an extending direction of the area of the contact member brought into friction contact with the vibrator, and also inward of an end of the contact member in the first predetermined direction.

US Pat. No. 10,924,036

POWER GENERATION DEVICE AND A POWER GENERATION METHOD

Koninklijke Philips N.V.,...

1. A power generation device, comprising:an electrical power generator, the electrical power generator comprising a first generating arrangement and a second generating arrangement,
wherein each generating arrangement generates an output voltage and an output current,
wherein each generating arrangement uses a first generating element and a second generating element, at least one of the first generating element and the second generating element maintains a non-zero state of charge when the first generating element and the second generating element are separated from each other,
wherein the first generating arrangement is moveable with respect to the second generating arrangement,
wherein a movement of the first generating arrangement relative to the second generating arrangement generates an output voltage and an output current,
wherein the output voltage and/or the output current is dependent upon a separation distance between the first generating element and the second generating element of each generating arrangement and the non-zero state of charge,
wherein the generating arrangements are arranged such that an increase in the separation distance between generating elements of the first arrangement results in a related decrease in the separation distance between generating elements of the second arrangement, and vice versa, and
wherein the electrical power generator further comprises a combiner unit that combines the output voltages and output currents of the first generating arrangement and the second generating arrangement.

US Pat. No. 10,924,035

POWER CONVERSION DEVICE

MITSUBISHI ELECTRIC CORPO...

1. A power conversion device comprising:a power converter connected to an electrical storage device that stores direct current (DC) power, and having a function to convert the DC power stored in the electrical storage device into alternating current (AC) power, and also having a function to output the AC power to one or both of a customer load and a power system;
a detector to detect voltage and current at a first point on a power line that connects the power converter with the power system; and
a controller to generate a drive command for controlling the power converter based on the voltage and on the current detected by the detector, wherein
the customer load is connected to a second point, on the power line, between the power converter and the first point,
the power converter operates on a basis of the drive command generated by the controller, and
the controller includes
a calculator to calculate an active power value and a reactive power value of a tidal power based on the voltage and on the current detected by the detector,
an active power command generator to generate a command value for an output of active power based on an active power command value supplied from an external controller disposed outside the power conversion device, and on the active power value calculated by the calculator,
a reactive power command generator to generate a command value for an output of reactive power based on a reactive power command value supplied from the external controller and on the reactive power value calculated by the calculator, and
a drive command generator to generate the drive command based on one or both of the command value for an output of active power generated by the active power command generator and the command value for an output of reactive power generated by the reactive power command generator,
the calculator calculates
the active power value of the tidal power by accumulating an active power value at a frequency of AC power of the power system and one or more active power values at respective multiplied frequencies based on the frequency, or
the reactive power value of the tidal power by accumulating a reactive power value at the frequency of the AC power of the power system and one or more reactive power values at respective multiplied frequencies based on the frequency.

US Pat. No. 10,924,034

METHOD FOR CONTROLLING A CONVERTER, CONTROL DEVICE FOR A CONVERTER AND CONVERTER

Robert Bosch GmbH, Stutt...

1. A method for controlling a converter (1) having a plurality of electrical phases, comprising the following steps:determining (S1) duty ratios for switched-on durations of pulses for pulse-width-modulated control of the electrical phases of the converter (1) in a time frame, wherein the time frame is formed by units of a PWM clock cycle (I, II) of the pulse-width-modulated control; and
adapting (S2) the switching-on points in time and switching-off points in time for the pulse-width-modulated control of the electrical phases, wherein for a first phase in a first PWM clock cycle (I) a switched-on duration is set completely at the end of the first PWM clock cycle (I) and, in a second PWM clock cycle (II) following the first PWM clock cycle (I), the switched-on duration of the first phase is set at the beginning of the second PWM clock cycle (II), wherein the first electrical phase of the converter (1) comprises an electrical phase having the largest duty ratio of the electrical phases of the converter (1), and wherein a conventional control switching takes place for one or more of the other electrical phases during the first PWM clock cycle and the second PWM clock cycle, and wherein the duty ratios of the electrical phases correspond to the duty ratios determined.

US Pat. No. 10,924,033

METHOD OF OPERATING AN INVERTER FOR EMITTER SHUNT CURRENT MEASUREMENT AND INVERTER

Schmidhauser AG, Romansh...

1. A method for operating an inverter, wherein the inverter comprises:a number of bridge arms having respective bridge connections,
wherein a respective bridge arm is electrically connected to a first intermediate circuit pole of the inverter on a first side and wherein a respective bridge arm is electrically connected to a second intermediate circuit pole of the inverter on a second side,
wherein the respective bridge arm has at least two switching means, wherein a respective bridge connection electrically connects depending on a switching state of the switching means of the bridge arm, either to the first intermediate circuit pole or to the second intermediate circuit pole, and
wherein a shunt resistor is arranged in the respective bridge arm, and the shunt resistor performs or does not perform a measurement function depending on a switching state of the switching means,
wherein the method comprises the steps of:
driving the respective switching means of the respective bridge arms using pulse width modulation with a temporally changeable duty cycle such that voltages between the bridge connections have a temporally predefined profile,
wherein the respective switching means of the respective bridge arms are driven with flat-top modulation for particular angular ranges of a respective fundamental oscillation,
wherein a respective duty cycle for the respective switching means of the respective bridge arms is selected such that, during a respective period of the pulse width modulation, at least two shunt resistors always perform their measurement function for a minimum time, and
wherein before two duty cycles for the respective switching means of the respective bridge arms undershoot a given threshold at a same time, switching is performed to a blocking operation of a lower switching means of one of the respective bridge arms.

US Pat. No. 10,924,032

INVERTER AND METHOD FOR OPERATING AN INVERTER WITH ANGLE-INDEPENDENT VARIATION OF PULSE DUTY FACTOR OF SWITCHING ELEMENTS

Schmidhauser AG, Romansh...

1. A method for operating an inverter, wherein the inverter comprises:a plurality of bridge arms, each of which has a bridge terminal,
wherein each of the bridge arms is electrically connected on a first side to a first intermediate circuit pole of the inverter and electrically connected on a second side to a second intermediate circuit pole of the inverter,
wherein each of the bridge arms comprises at least two switching elements, wherein the bridge terminal, depending upon a circuit state of the switching elements, is electrically connected either to the first intermediate circuit pole or to the second intermediate circuit pole, and
wherein a shunt resistor is arranged in each of the bridge arms,
wherein the inverter is configured to generate a rotating field frequency having multiple values including at least two non-zero frequencies;
the method comprising the steps of:
actuating the switching elements of the bridge arms via pulse width modulation with a temporally variable pulse duty factor, such that voltages between the bridge terminals show a temporally defined characteristic,
wherein the switching elements of the bridge arms are actuated with flat-top modulation for specific angular ranges of a fundamental wave,
wherein the temporally variable pulse duty factor for the switching elements of the bridge arms, immediately ahead of or immediately after the angular ranges, varies within a predefined time interval in an angularly-independent manner.

US Pat. No. 10,924,031

INTERNAL PARALLELED ACTIVE NEUTRAL POINT CLAMPED CONVERTER WITH LOGIC-BASED FLYING CAPACITOR VOLTAGE BALANCING

THE GOVERNORS OF THE UNIV...

1. An internal parallelization based single stage active neutral point clamped (IP-ANPC) converter for single-phase or multiple phases AC-DC or DC-AC power conversion, wherein a phase consists of:a low switching frequency (LSF) part; and
a plurality of high switching frequency (HSF) modules, wherein the plurality of HSF modules are modular, connected in parallel to a single output terminal, connected in parallel to the LSF part without a DC link capacitor between the LSF part and the HSF modules, and are modulated independently from each other and independently from the LSF part.

US Pat. No. 10,924,028

MULTIPLE STAGE GATE DRIVE FOR CASCODE CURRENT SENSING

Power Integrations, Inc.,...

1. A power converter, comprising:an energy transfer element coupled between an input of the power converter and an output of the power converter;
a cascode circuit coupled to the energy transfer element, the cascode circuit further configured to generate a first sense signal and a second sense signal; and
a controller coupled to control switching of the cascode circuit to transfer energy from the input of the power converter to the output of the power converter, the controller comprising:
a current sense circuit configured to generate a current limit signal and an overcurrent signal in response to the first sense signal and the second sense signal;
a control circuit configured to generate a control signal in response to the current limit signal and the overcurrent signal; and
a drive circuit comprising a multiple stage gate drive circuit configured to generate a drive signal in response to the control signal, wherein a first stage of the multiple stage gate drive circuit is configured to provide the drive signal to reduce EMI, and a second stage of the multiple stage gate drive circuit is configured to provide the drive signal to enable accurate current sensing of the cascode circuit.

US Pat. No. 10,924,027

SWITCHING POWER SUPPLY DEVICE

PANASONIC INTELLECTUAL PR...

1. A switched-mode power supply device provided with a plurality of power supply circuits that correspond to phases of a polyphase alternator, the switched-mode power supply device comprising:a switching circuit that allows switching of a phase connected to one of the plurality of power supply circuits not corresponding to a certain phase of the polyphase alternator, the switching being done between the certain phase and a phase to which the power supply circuit corresponds;
an inrush current prevention circuit that is disposed on a power supply line on a negative electrode side of the polyphase alternator and is disposed at a position closer to the polyphase alternator than a connection point at which the plurality of power supply circuits are connected to the polyphase alternator, the inrush current prevention circuit configured to prevent an inrush current;
a filter circuit disposed at a position closer to the polyphase alternator than the switching circuit and the inrush current prevention circuit are positioned relative to the polyphase alternator, the filter circuit being a circuit in which all lines for the phases are magnetically coupled to one another; and
a control circuit that controls the switching circuit and the inrush current prevention circuit, wherein
the control circuit allows initial charging of capacitors to be carried out while controlling the switching circuit such that the phase connected to the power supply circuit not corresponding to the certain phase is switched to the certain phase, and while causing the inrush current prevention circuit to function, the capacitors being capacitors that the plurality of power supply circuits respectively include, and
when the initial charging is completed, controls the switching circuit such that the phase connected to the power supply circuit not corresponding to the certain phase is switched to the phase to which the power supply circuit corresponds, and stops the inrush current prevention circuit from functioning.

US Pat. No. 10,924,026

REGENERATIVE CASCADED H BRIDGE POWER SUPPLY

Rockwell Automation Techn...

1. A power supply for use with a multi-phase AC load, the power supply comprising:a phase shifting transformer comprising a primary winding and a plurality of secondary windings magnetically coupled with the primary winding; and
a plurality of power cells, each power cell receiving an input from a respective secondary winding of the plurality of secondary windings and each outputting power to one phase of the multi-phase AC load, wherein power cells outputting power to the same phase of the multi-phase AC load are connected in series;
wherein each power cell comprising:
a rectifier comprising two switches connected in series;
two capacitors connected in series as DC link for smoothing a DC output of the rectifier; and
an inverter comprising two legs of switches, each leg comprising two switches connected in series across the DC link;
wherein a midpoint between the two capacitors is configured to receive a single-phase input from a first terminal of a respective secondary winding, a midpoint between the two switches of the rectifier is configured to receive the single-phase input from a second terminal of the respective secondary winding, and midpoints between the two switches of each leg of the inverter are configured to output power to one phase of the multi-phase AC load.

US Pat. No. 10,924,025

REGENERATIVE CASCADED H BRIDGE POWER SUPPLY

Rockwell Automation Techn...

1. A power supply comprising:a transformer that receives a three-phase primary voltage and steps the three-phase primary voltage up or down to a secondary voltage with a plurality of secondary winding sets to a plurality of first phase voltages, a plurality of second phase voltages, and a plurality of third phase voltages; and
a plurality of power cell sets that each comprise a plurality of power cells cascaded connected, wherein each power cell comprises a rectifier and an inverter, the rectifier comprising two first active switches that are serially connected and receive a phase voltage from a first secondary winding of a given secondary winding set at a first switch midpoint, two second active switches that are serially connected and receive another phase voltage from a second secondary winding of the given winding set at a second switch midpoint, and two capacitors in parallel with the rectifier and the inverter that are serially connected and receive another phase voltage from a third secondary winding of the given secondary winding set at a capacitor midpoint between the capacitors, wherein the two first active switches, the two second active switches, and the two capacitors of each power cell are connected in parallel.

US Pat. No. 10,924,023

CONTROL CIRCUIT HAVING POWER LIMIT FOR AN AC-DC CONVERTER AND INTEGRATED CIRCUITS THEREOF

Chengdu Monolithic Power ...

1. A control circuit having power limit for controlling an AC-DC voltage converter comprising an inductive element and a controllable switch, wherein the controllable switch is coupled between the inductive element and a logic ground, the control circuit comprising:a first sensing circuit, comprising an auxiliary winding coupled to the inductive element, the first sensing circuit is configured to sense a voltage on the inductive element to generate a first sensing signal, wherein when the controllable switch is turned on, the first sensing signal is indicative of an input voltage signal of the AC-DC voltage converter, and wherein when the controllable switch is turned off, the first sensing signal is indicative of a current signal flowing through the inductive element;
a second sensing circuit, connected between the controllable switch and the logic ground, wherein when the controllable switch is turned on, the second sensing circuit is configured to sense a current flowing through the inductive element to provide a second sensing signal; and
a power limit circuit, configured to receive the first sensing signal and the second sensing signal, and further configured to generate a power indication signal based on the first sensing signal and the second sensing signal, wherein the power indication signal is indicative of an input power of the AC-DC voltage converter, and wherein when the power indication signal is larger than a power threshold, the controllable switch is turned off.

US Pat. No. 10,924,022

QUASIRESONANT FLYBACK CONVERTER

HITACHI AUTOMOTIVE SYSTEM...

1. A flyback converter, comprising:an input terminal configured to receive a DC input voltage;
a transformer comprising a primary coil connected to the input terminal and a secondary coil;
a semiconductor switch configured to switch current flow through the primary coil;
a first measurement unit configured to measure the DC input voltage;
a second measurement unit configured to measure a voltage across the semiconductor switch;
a control unit having a synchronization terminal and configured to output a switching signal to the semiconductor switch with a constant frequency in accordance with a synchronization signal input to the synchronization terminal; and
a frequency adjustment unit configured to transmit a synchronization signal to the synchronization terminal based on the DC input voltage measured by the first measurement unit and the voltage measured by the second measurement unit such that the constant frequency of the switching signal output from the control unit becomes variable, wherein the frequency adjustment unit comprises a delay unit configured to delay the DC input voltage measured by the first measurement unit and the voltage measured by the second measurement unit by a predetermined time delay.

US Pat. No. 10,924,021

CONTROL APPARATUS FOR CONTROLLING SWITCHING POWER SUPPLY

FUJI ELECTRIC CO., LTD., ...

1. A control apparatus for controlling a switching power supply during burst control that includes a switching period and a no switching period, the switching power supply includinga half bridge circuit having a first switching element on a high side and a second switching element on a low side, and
a resonance circuit connected to the half bridge circuit, the resonance circuit generating a resonance current and a ringing voltage,the control apparatus comprising:a load detecting circuit that outputs a load signal by shunting and averaging the resonance current of the resonance circuit;
an off signal generating circuit that generates a plurality of off signals for turning off the first switching element and the second switching element during the switching period;
an on signal generating circuit that obtains a number of resonance cycles of the ringing voltage in the no switching period, and generates a first pulse on signal for turning on the second switching element to restart the switching period; and
a control circuit that receives the plurality of off signals generated by the off signal generating circuit and the first pulse on signal generated by the on signal generating circuit, and generates a first control signal and a second control signal for alternating on-off control of the first switching element and the second switching element, wherein
the resonance circuit includes a resonant reactor that has a transformer with an auxiliary winding, a winding voltage being generated by the auxiliary winding;
the plurality of off signals include a first pulse off signal, a second pulse off signal and a third pulse off signal; and
the off signal generating circuit includes:
a threshold voltage generating circuit that receives a feedback voltage corresponding to a difference between an output voltage of the switching power supply and a target voltage for the output voltage, and generates a first threshold voltage and a second threshold voltage for detecting a change in the winding voltage, the second threshold voltage being higher than the first threshold voltage;
a first comparator that outputs the first pulse off signal upon detecting that the winding voltage becomes higher than the first threshold voltage;
a second comparator that outputs the second pulse off signal upon detecting that the winding voltage becomes lower than the second threshold voltage; and
a third comparator that outputs the third pulse off signal upon detecting that a voltage signal corresponding to a current produced by shunting the resonance current becomes lower than a third threshold voltage.

US Pat. No. 10,924,020

PRESTART CONTROL CIRCUIT FOR A SWITCHING POWER CONVERTER

Raytheon Company, Waltha...

1. A switching power converter comprising:an energy storage section with a primary side and a secondary side that are isolated from each other, said energy storage section responsive to a selective application of an input voltage to the primary side of the switching power converter to produce an energy that provides an output voltage on the secondary side of the switching power converter;
a switching control circuit configured to produce a waveform that has a period and a duty cycle, said duty cycle set based on a value of the output voltage, the input voltage or the energy produced by the energy storage section;
a primary switch and a synchronous rectifier switch that during normal operation switch in opposition to each other responsive to the waveform such that when the primary switch is CLOSED and the synchronous rectifier switch is OPEN the energy storage section is charging and when the primary switch is OPEN and the synchronous rectifier switch is CLOSED the energy storage section is discharging;
wherein during PRESTART operation the primary switch and the synchronous rectifier switch are responsive to the waveform such that the primary switch is held OPEN and the synchronous rectifier switch is pulsed between OPEN and CLOSED; and
a prestart control circuit that during PRESTART operation when the synchronous rectifier switch is CLOSED measures a reflected voltage on the primary side of the switching power converter that is proportionate to the output voltage on the secondary side of the switching power converter, and establishes an initial duty cycle value of the switching control circuit for normal operation using the reflected voltage.

US Pat. No. 10,924,019

ASYNCHRONOUS CLOCK PULSE GENERATION IN DC-TO-DC CONVERTERS

TEXAS INSTRUMENTS INCORPO...

1. A circuit comprising:an input terminal;
an output terminal;
a fixed frequency clock circuit configured to generate a clock signal having fixed frequency clock pulses;
a driver circuit configured to operate a switch, coupled to a switch node between the input and output terminal, in response to pulse width modulation (PWM) pulses; and
a pulse generation circuit coupled to receive a feedback voltage associated with the output terminal, the pulse generation circuit including:
a transient sensing circuit having:
an amplifier configured to amplify a difference between a reference voltage and the feedback voltage;
a high pass filter having a filter input coupled to receive the amplified difference, and a filter output; and
a sense output configured to deliver a sense signal corresponding to the filter output; and
a clock augmentation circuit coupled to the transient sensing circuit, and configured to generate an augmented clock signal for triggering the PWM pulses, wherein the augmented clock signal including the clock signal and an additional clock pulse in response to the sense signal.

US Pat. No. 10,924,018

TRACKING ENERGY CONSUMPTION USING A BOOST-BUCK TECHNIQUE

TEXAS INSTRUMENTS INCORPO...

1. An electronic device comprising:a first energy transfer circuit;
a second energy transfer circuit;
a control circuit coupled to the first energy transfer circuit and the second energy transfer circuit, the control circuit comprises an ON-time and OFF-time generator, a control logic block, and an accumulator,
wherein the control logic block is configured to receive a signal from the ON-time and OFF-time generator and to generate switching signals for the first energy transfer circuit and the second energy transfer circuit, and
wherein the accumulator is configured to determine a consumed energy based on generated switching signals;
an inductor having a terminal;
a first switching element having a first terminal and a second terminal, the first terminal of the first switching element is coupled to the terminal of the inductor and the second terminal of the first switching element is coupled to the control circuit;
a first diode having an anode terminal and a cathode terminal, wherein the anode terminal is coupled to the terminal of the inductor;
a second switching element having a first terminal and a second terminal, the first terminal of the second switching element is coupled to the terminal of the inductor and the second terminal of the second switching element to the control circuit; and
a capacitor having a first terminal, the first terminal of the capacitor is coupled to the cathode terminal of the first diode.

US Pat. No. 10,924,017

TECHNIQUES FOR CONTROLLING A SINGLE-INDUCTOR MULTIPLE-OUTPUT SWITCHED-MODE POWER SUPPLY

QUALCOMM Incorporated, S...

1. A method for controlling a switched-mode power supply (SMPS), comprising:selecting a first output of a plurality of outputs of the SMPS based on:
a power demand associated with each of the plurality of outputs if a voltage at one of the plurality of outputs is less than a reference voltage associated with the one of the plurality of outputs, by selecting as the first output the one of the plurality of outputs having the highest power demand; and
an amount of overcharge associated with each of the plurality of outputs if the voltage at the one of the plurality of outputs is greater than the reference voltage, by selecting as the first output the one of the plurality of outputs having the lowest amount of overcharge; and
directing current across an inductive element of the SMPS to the first output based on the selection.

US Pat. No. 10,924,016

METHOD FOR CONVERTING ELECTRIC ENERGY BETWEEN C-TYPE USB DEVICES AND CORRESPONDING DEVICE

STMICROELECTRONICS (GRAND...

1. A USB Type-C device supporting a bidirectional power supply, the device comprising:a first device terminal configured to be coupled to a second USB Type-C device;
a second device terminal configured to be coupled to a rechargeable DC voltage power source; and
a reversible switched-mode power supply coupled to the first device terminal and the second device terminal, wherein the reversible switched-mode power supply comprises a capacitor, wherein a first terminal of the capacitor is linked to the first device terminal, and wherein a second terminal of the capacitor is linked to a switch that is configured to couple the second terminal of the capacitor to a common ground of the reversible switched-mode power supply.

US Pat. No. 10,924,015

METHODS, APPARATUS, AND SYSTEMS FOR CURRENT SENSING IN VALLEY CURRENT-CONTROLLED BOOST CONVERTERS

TEXAS INSTRUMENTS INCORPO...

1. A system comprising:a boost converter configured to operate in a first mode and a second mode, the boost converter including an inductor, a high-side switch and a low-side switch;
a controller configured to control the high-side switch and the low-side switch based on a trigger signal; and
a current sensing system configured to provide the trigger signal responsive to a current from the inductor reaching a threshold level, the current sensing system including:
an input terminal;
a current terminal, the high-side switch coupled between the input terminal and the current terminal;
a comparator having a comparator output and first and second comparator inputs;
a first transistor coupled between the input terminal and the first comparator input;
a second transistor coupled between the current terminal and the first comparator input, the second transistor configured to linearize a first voltage at the first comparator input toward a second voltage at the second comparator input when the current from the inductor is within a threshold range from zero, the second voltage corresponding to an output voltage of the boost converter; and
a third transistor coupled between the current terminal and the second comparator input;
in which the comparator is configured to provide the trigger signal based on a comparison between the first voltage and the second voltage.

US Pat. No. 10,924,014

SWITCHING REGULATOR CONTROLLER DYNAMIC OUTPUT VOLTAGE ADJUSTMENT

Alpha and Omega Semicondu...

1. A controller for a switching regulator, the switching regulator configured to receive an input voltage and to generate a regulated output voltage on an output terminal for driving a load, the controller comprising:an error amplifier configured to receive a feedback voltage indicative of the regulated output voltage and a reference voltage, and to generate an error signal indicative of the difference between the feedback voltage and the reference voltage;
a loop calculator configured to generate an output signal in response to the error signal, the output signal being used by the switching regulator to generate the regulated output voltage having a voltage value related to the reference voltage; and
an output voltage adjust circuit configured to receive a sense current signal sensing a load current flowing through the load and to generate a voltage adjust signal in response to the sense current signal, the output voltage adjust circuit comprises a memory storing a current-voltage lookup table, the current-voltage lookup table containing a set of voltage values indexed to corresponding sense current signal values, the voltage values and the sense current signal values being associated with a predetermined load profile of the load and the current-voltage lookup table providing an output voltage value responsive to load current demand,
wherein the current-voltage lookup table is indexed by a value of the sense current signal to provide the output voltage value being the voltage adjust signal, the voltage adjust signal being applied to generate the reference voltage relative to a predetermined set voltage to increase or decrease the reference voltage, the reference voltage being applied to the error amplifier to generate the error signal; and
wherein the voltage adjust signal is summed with the predetermined set voltage to generate the reference voltage.

US Pat. No. 10,924,013

VOLTAGE-CONTROLLED OSCILLATOR FOR CURRENT MODE HYSTERETIC MODULATOR

Alpha and Omega Semicondu...

1. A voltage-controlled oscillator generating an output clock signal in response to an input feedback signal, the voltage-controlled oscillator comprising:an input tuning circuit coupled to a first node, the first node being coupled to receive a signal indicative of a difference between the input feedback voltage signal and a target voltage, the input tuning circuit applying tuning to modify at least a frequency response of the signal indicative of the difference to generate a first voltage signal on the first node;
a comparator having a first input terminal receiving the first voltage signal, a second input terminal receiving a voltage ramp signal having an increasing voltage value from a first voltage value being a ground voltage to a second voltage value, and an output terminal, the comparator generating an output signal on the output terminal having a first state in response to the voltage ramp signal being less than the first voltage signal and having a second state in response to the voltage ramp signal being equal to or more than the first voltage signal; and
a first logic circuit having an input terminal coupled to the output terminal of the comparator to receive the output signal of the comparator, the first logic circuit generating an output signal having a first state in response to the output signal of the comparator having the second state, the output signal of the first logic circuit being provided as the output clock signal and being applied to reset the voltage ramp signal to the first voltage value.

US Pat. No. 10,924,012

POWER CONVERTER WITH HIGH DUTY CYCLE COMPENSATION

Apple Inc., Cupertino, C...

1. An apparatus, comprising:a voltage regulator circuit including a switch node coupled to a regulated power supply node via an inductor, wherein the voltage regulator circuit is configured to:
source a charge current to the switch node in response to a primary control signal; and
source a bypass current to the regulated power supply node in response to a secondary control signal; and
a primary control loop configured to generate the primary control signal based on a comparison of a first reference voltage level and a sensed inductor current; and
a secondary control loop configured, independently of the primary control loop, to:
generate a second reference voltage level using the first reference voltage level and a bias current; and
generate the secondary control signal based on a comparison of a voltage level of the regulated power supply node and the second reference voltage level whose value is based on the first reference voltage level; and
wherein a difference between the first reference voltage level and the second reference voltage level is based on a difference between a voltage level of an input power supply node and the voltage level of the regulated power supply node.

US Pat. No. 10,924,011

CHIP EMBEDDED POWER CONVERTERS

Faraday Semi, Inc., Irvi...

1. A power converter comprising:a printed circuit board (PCB) comprising:
a bottom side; and
a top side;
embedded circuitry that is chip-embedded into the PCB between the top side of the PCB and the bottom side of the PCB, the embedded circuitry comprising:
a driver configured to generate one or more driver signals; and
one or more switches configured to be driven by the one or more driver signals;
one or more vias extending through the top side of the PCB;
a first inductor positioned over the top side of the PCB, wherein the one or more vias are electrically coupled to the first inductor and to the embedded circuitry, and a footprint of the first inductor at least partially overlaps a footprint of the embedded circuitry;
a second inductor; and
a third inductor;
wherein the first inductor, the second inductor, and the third inductor are arranged in parallel and are driven out of phase from each other.

US Pat. No. 10,924,010

CONTROL CIRCUIT AND CONTROL METHOD FOR SWITCHING REGULATOR AND SWITCHING REGULATOR WITH THE SAME

Silergy Semiconductor Tec...

1. A control circuit for a switching regulator having a first switch, the control circuit comprising:a) a first trigger circuit configured to control a starting moment of a first type time interval in a switching period;
b) a second trigger circuit configured to control a length of said first type time interval;
c) a time regulator configured to generate an adjustment signal to regulate said length of said first type time interval by comparing a second type time interval in said switching period against a reference time; and
d) wherein said length of said first type time interval is controlled to be constant when in a first state, and said length of said first type time interval is regulated correspondingly to improve a regulation range of an output signal of said switching regulator when in a second state.

US Pat. No. 10,924,009

SYSTEM AND METHOD FOR CONTROLLING SWITCHING POWER SUPPLY

SEMICONDUCTOR COMPONENTS ...

21. A control circuit for controlling a switching power supply, comprising:an amplifier circuit generating a comparison signal in response to an output signal of the switching power supply;
a first threshold signal generator generating a first threshold signal based on the comparison signal;
a second threshold signal generator generating a second threshold signal based on the comparison signal;
a timer circuit generating a timeout signal in response to a modulation signal; and
a first comparator determining whether the comparison signal is equal to or greater than a sense signal to assert the modulation signal to have a first logic value when the comparison signal is equal to or greater than the sense signal and the timeout signal has the first logic value,
wherein the first threshold signal generator generates the first threshold signal having a value equal to a sum of a value of the comparison signal and a first threshold value, the first threshold value being proportional to a value of the output signal with a first proportionality constant, the sense signal having a slew rate that is proportional to a second proportionality constant, the first proportionality constant being equal to or less than the second proportionality constant.

US Pat. No. 10,924,008

DEVICES, SYSTEMS, AND METHODS FOR CHARGING ELECTRIC VEHICLES

NIO USA, Inc., San Jose,...

1. A converter, comprising:a plurality of switching elements connected in series and coupled between power signal lines that receive a first voltage from an external power source;
at least one capacitance coupled between the power signal lines and coupled to the plurality of switching elements;
at least one connector including:
a first port that couples to a first battery and a first power signal line of the power signal lines;
a second port that couples to a second battery and a second power signal line of the power signal lines;
a third port coupled to an output line, the output line coupling to the first battery and the second battery; and
a resonant circuit coupled to the plurality of switching elements, a switching frequency of the plurality of switching elements being matched to a resonant frequency of the resonant circuit such that, during a charging mode that charges the first battery and the second battery, the plurality of switching elements, the resonant circuit and the at least one capacitance operate to convert the first voltage into a second voltage that is lower than the first voltage and that balances voltages of the first battery and the second battery through the first, second, and third ports.

US Pat. No. 10,924,007

POWER SUPPLY DEVICE AND METHOD FOR CONTROLLING THE MULTI-PHASE INTERLEAVING OPERATION OF THE POWER SUPPLY DEVICE

KYOSAN ELECTRIC MFG. CO.,...

1. A power supply device of multi-phase interleaving control for performing multi-phase control using a plurality of phase current values, comprising:an LC chopper circuit constituting a step-down chopper circuit that operates according to the multi-phase control of multi-phase interleaving; and
a controller configured to perform a step response control according to the multi-phase control of the LC chopper circuit,
wherein the LC chopper circuit and the controller form a control system that uses a combined current of respective phase current values in the LC chopper circuit, and performs the multi-phase control of a step response of the LC chopper circuit using a control current,
wherein the control system is provided with a factor related to the control current, as an adjustment parameter for response characteristics to a command voltage, and makes an output voltage of the LC chopper circuit follow the command voltage based on switching control of respective phases of the LC chopper circuit by a constant current control, and
wherein, the control current is expressed by:
AV{VREF?vO(t)}+?iC(t)+iR(t)
where Av is a factor by which a difference value between the output voltage vo(t) at time t and the command voltage VREF of the control system is multiplied, ? is a factor by which a capacitance current ic(t) in the LC chopper circuit at time t is multiplied, and iR(t) is a load current of a load R at time t, and
the factor Av of the three-phase interleaving control in the multi-phase interleaving control is expressed by Av=3T/L, where T is sampling cycle and L is inductance of the LC chopper circuit.

US Pat. No. 10,924,006

SUPPRESSION OF REBALANCING CURRENTS IN A SWITCHED-CAPACITOR NETWORK

pSemi Corporation, San D...

1. An apparatus comprising a power converter, said power converter comprising a switching network and a controller that controls said switching network, wherein said controller is configured to cause said switching network to form a switched-capacitor circuit that, during the course of operation, comprises a first path and a second path, wherein said first path extends through a first capacitor network that comprises a plurality of pump capacitors, wherein said second path extends through a second capacitor network that comprises said plurality of pump capacitors, wherein said first path connects to an anode and a cathode of a first pump capacitor from said plurality of pump capacitors, wherein said second path connects to said anode and said cathode of said first pump capacitor and to an anode and a cathode of a second pump capacitor from said plurality of pump capacitors, wherein said anode of said first pump capacitor connects to said anode of said second pump capacitor, wherein said controller is configured such that, when said anode of said first pump capacitor connects to said anode of said second pump capacitor upon formation of said second capacitor network, a voltage difference between said anodes is zero, and wherein said first path comprises a balancing capacitor and said first pump capacitor.

US Pat. No. 10,924,005

SWITCHING-MODE POWER SUPPLIES AND POWER CONTROLLERS CAPABLE OF JITTERING SWITCHING FREQUENCY

LEADTREND TECHNOLOGY CORP...

1. A power converter for converting an input voltage into an output voltage to supply power to a load, the power converter comprising:an inductive device and a power switch, connected in series between the input voltage and an input ground; and
a power controller providing a PWM signal to the power switch in response to a compensation signal to control the power switch, the compensation signal generated in response to the output voltage;
wherein the power controller is configured to provide a maximum switching frequency limiting a switching frequency of the PWM signal;
the power controller jitters the maximum switching frequency, making the maximum switching frequency have a first average switching frequency and a first variation ratio when the compensation signal is a first compensation value, and have a second average switching frequency and a second variation ratio when the compensation signal is a second compensation value;
the first and second compensation values correspond to first and second loads respectively while the first load is heavier than the second load;
the first average switching frequency is higher than the second average switching frequency;
the second variation ratio is larger than the first variation ratio; and
the PWM controller comprises:
an ON-time controller controlling an ON time of the power switch in response to a current-sense signal and the compensation signal; and
an OFF-time controller controlling an OFF time of the power switch in response to the compensation signal, comprising:
a blanking-time generator generating a blanking signal in response to the compensation signal to define a blanking time, the OFF time controlled to end not earlier than an end of the blanking time; and
a jitter generator providing a jitter signal to the blanking-time generator to jitter the blanking time;
wherein the maximum switching frequency is in association with the blanking time.

US Pat. No. 10,924,004

AC-DC CONVERTER CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING A RESPECTIVE AC-DC CONVERTER CIRCUIT ARRANGEMENT

1. An AC-DC converter circuit arrangement for supplying a load, the AC-DC converter circuit arrangement comprising:a switched-mode input converter sub-stage comprising a step-up converter configured to convert a rectified input voltage on an input side into an intermediate voltage higher than the rectified input voltage;
a switched-mode output converter sub-stage configured to convert the intermediate voltage into a direct output voltage at an output side;
a switch configured to switch both the switched-mode input converter sub-stage and the switched-mode output converter sub-stage; and
a control circuit configured to control the switched-mode output converter sub-stage to a power demand at the output side independent of the switched-mode input converter sub-stage by operating the switch with a controlled duty cycle,
wherein the control circuit is connected to the switched-mode output converter sub-stage and the output side and configured to apply a first control parameter based on a sensed output voltage and/or a sensed output current and to apply a second control parameter based on a sensed current and/or a sensed voltage of the switched-mode output converter sub-stage, and
wherein the AC-DC converter circuit arrangement is configured to automatically operate the switched-mode input converter sub-stage in a discontinuous conduction mode by operating the switch during control of the switched-mode output converter sub-stage through the control circuit.

US Pat. No. 10,924,003

SWITCHING POWER SUPPLY

Rohm Co., Ltd., Kyoto (J...

1. A controller IC, comprising:a current detection terminal for detecting a coil current passing in a switching power supply; and
an on-timing setter configured to check for a ground short circuit at the current detection terminal when an output transistor turns off to generate an on-timing setting signal so as to turn on the output transistor,
during normal operation, at a time point that the coil current has decreased to a zero value or a value close thereto and,
during the ground short circuit, after lapse of a predetermined minimum off-period, wherein
the on-timing setter includes:
a zero-current detector configured to generate a zero-current detection signal by comparing a terminal voltage at the current detection terminal or a voltage commensurate therewith with a predetermined threshold voltage;
a timer configured to count the minimum off-period after the output transistor is turned off to generate a timer output signal; and
a selector configured to output one of the zero-current detection signal or a delayed signal thereof and the timer output signal as the on-timing setting signal according to a result of the check for the ground short circuit.

US Pat. No. 10,924,002

TRANSIENT RESPONSE ENHANCEMENT CIRCUIT FOR BUCK-TYPE VOLTAGE CONVERTERS

UNIVERSITY OF ELECTRONIC ...

1. A transient response enhancement circuit for a buck-type voltage converter, comprising a transient load changing detecting module, a compensation voltage predicting operation module and an internal active compensation module; wherein,the transient load changing detecting module detects an output voltage of the buck-type voltage converter, and generates a first control signal when an increase of the output voltage of the buck-type voltage converter is detected;
when the first control signal is generated, if the buck-type voltage converter changes from a heavy load to a light load, a lower power tube in the buck-type voltage converter is controlled to be turned on; if the buck-type voltage converter changes from the light load to the heavy load, an upper power tube in the buck-type voltage converter is controlled to be turned on;
the compensation voltage predicting operation module comprises a transconductance amplifier, a first buffer, a second buffer, a first capacitor, a first switch, a second switch and a third switch;
a transconductance of the transconductance amplifier is adjustable, and a differential input voltage of the transconductance amplifier is a voltage divided value of a voltage difference between a voltage of a switching node at the buck-type voltage converter and the output voltage of the buck-type voltage converter, and an output end of the transconductance amplifier is connected to a first end of the first switch;
a first end of the second switch is connected to a second end of the first switch and an input end of the first buffer and is grounded through the first capacitor, and a second end of the second switch is connected to an output end of the second buffer;
a first end of the third switch is connected to an output end of the first buffer, and a second end of the third switch is connected to an input end of the second buffer and serves as an output end of the compensation voltage predicting operation module;
when the first control signal is generated, the first switch and the third switch are turned on and the second switch is turned off; when the first control signal is not generated, the first switch and the third switch are turned off and the second switch is turned on; and
an input end of the internal active compensation module is connected to the output end of the compensation voltage predicting operation module, and an output end of the internal active compensation module is connected to an output end of an error amplifier in the buck-type voltage converter.

US Pat. No. 10,924,001

GATE DRIVER CONTROLLER AND ASSOCIATED DISCHARGE METHOD

TEXAS INSTRUMENTS INCORPO...

8. A method of controlling an electric motor having first, second and third motor-winding inductors coupled to an inverter circuit, the method comprising: providing energy stored in a capacitor, during motor drive operations, to the first, second and third motor-winding inductors through the inverter circuit; comparing, using at least one processor, the energy stored in the capacitor to an energy threshold; triggering, using the at least one processor, a discharge of the stored energy from the capacitor, in response to the stored energy exceeding the energy threshold, by: activating a first power transistor and a second power transistor in the inverter circuit, in a first operating mode, to dissipate a portion of the stored energy through the first and second motor-winding inductors; and activating the second power transistor and deactivating other power transistors included in the inverter circuit, in a second operating mode, to dissipate the stored energy using the second power transistor and a body diode of another power transistor in the inverter circuit; and monitoring a remainder of the stored energy to determine whether the remainder of the charge energy exceeds the energy threshold.

US Pat. No. 10,924,000

DC-DC CONVERTER WITH REDUCED RIPPLE

NOVUM engineering GmbH, ...

1. A DC/DC converter comprising:an input and an output,
a longitudinal arm arranged between the input and the output and having at least a first inductor and a first capacitor,
a first shunt arm connected across the output,
a second shunt arm having a first active semiconductor switch and a second active semiconductor switch and forming a serial circuit having two end connection points which are connected directly to respective terminals of the output, and a center connection point, wherein a terminal of the first active semiconductor switch facing away from the second active semiconductor switch is connected directly to a terminal of the first capacitor of the longitudinal arm and is connected directly to the output, and
a second inductor having a first terminal connected to a point between the first inductor and the first capacitor and a second terminal connected to the center connection point, and
a controller providing control signals to the first and second active semiconductor switches such that the first and second active semiconductor switches are activated alternately, closing the first active semiconductor switch is when the second active semiconductor switch is opened and vice versa, wherein the input and the output are interchangeable, thereby allowing bi-directional operation of the DC-to-DC converter.

US Pat. No. 10,923,999

ACTIVE POWER FILTER-BASED MODULAR MULTILEVEL CONVERTER

Zhejiang University, Han...

1. An active power filter-based modular multilevel converter, comprising six bridge-arms of three phases, each phase including an upper bridge-arm and a lower bridge-arm, each bridge-arm including a bridge-arm inductor and at least one submodule of a same structure which are connected in series, each submodule being composed of two switch power devices and a capacitor, wherein,an active power filter circuit is provided between the upper and lower bridge-arms of each phase, said circuit including two switch power devices, two submodules, a capacitor, and an inductor, wherein the upper and lower bridge-arms are connected in series by means of two submodules, which are called intermediate submodules; the two switch power devices of the active power filter circuit are connected in series and then connected in parallel to ends of the intermediate submodules which are connected in series; and the capacitor and the inductor are connected in series and then connected in parallel to two ends of the switch power device connected to the lower bridge-arm.

US Pat. No. 10,923,998

SYSTEMS AND METHODS TO HARVEST ENERGY AND DETERMINE WATER HOLDUP USING THE MAGNETOHYDRODYNAMIC PRINCIPLE

Saudi Arabian Oil Company...

1. A magnetohydrodynamic power generation system configured in a pipeline, the magnetohydrodynamic power generation system comprising:one or more permanent magnets;
three or more flow tubes configured inside the pipeline and arranged concentrically around one or more permanent magnets;
a set of electrode pairs lining each of the flow tubes and in contact with a flowing media through the pipeline, the one or more permanent magnets configured such that a magnetic field of the one or more permanent magnets extends through the electrode pairs lining each of the flow tubes causing the electrode pairs lining the flow tubes to generate power in response to the flowing media through the pipeline;
a plurality of downhole valves powered by the magnetohydrodynamic power generation system; and
a processor connected to the set of electrode pairs and the one or more permanent magnets, the processor executing a set of instructions on a non-transitory computer readable media to calculate a water holdup measurement based upon an amount of power generated by the magnetohydrodynamic power generation system.