US Pat. No. 10,115,633

METHOD FOR PRODUCING SELF-ALIGNED LINE END VIAS AND RELATED DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A device comprising:trench lines formed in a dielectric layer;
each trench line including a pair of self aligned line end vias; and
a high-density plasma (HDP) oxide, silicon carbide (SiC) or silicon carbon nitride (SiCNH) formed between each pair of self aligned line end vias,
wherein the trench lines and self aligned line end vias are filled with a metal liner and metal.

US Pat. No. 10,115,632

THREE-DIMENSIONAL MEMORY DEVICE HAVING CONDUCTIVE SUPPORT STRUCTURES AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:a lower-interconnect-level dielectric material layer located over a substrate and embedding lower-interconnect-level metal interconnect structures;
a horizontal layer overlying the lower-interconnect-level dielectric material layer;
an alternating stack of insulating layers and electrically conductive layers located over the horizontal layer;
an array of memory stack structures extending through the alternating stack;
laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer, wherein each of the laterally-insulated conductive via structures comprises a respective first conductive core that is electrically shorted to a respective one of the lower-interconnect-level metal interconnect structures, and a respective first cylindrical dielectric spacer that laterally surrounds the respective first conductive core;
laterally-insulated support structures that vertically extend through a subset of layers in the alternating stack, wherein each of the laterally-insulated support structures comprises a respective second conductive core having a same composition as the first conductive core, and a respective second cylindrical dielectric spacer that laterally surrounds the respective second conductive core, and wherein an entirety of a top planar surface of each second conductive core contacts a respective bottom surface of an overlying upper-interconnect-level dielectric material layer;
wherein:
the alternating stack includes a staircase region in which each electrically conductive layer except a topmost electrically conductive layer laterally extends farther than any overlying electrically conductive layer to provide multiple sets of stepped surfaces, wherein each set of stepped surfaces continuously extend from a bottommost layer of the alternating stack to a topmost layer of the alternating stack;
a retro-stepped dielectric material portion overlies the multiple sets of stepped surfaces; and
the laterally-insulated support structures vertically extend through a respective portion of the multiple sets of stepped surfaces and the retro-stepped dielectric material portion.

US Pat. No. 10,115,631

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a circuit comprising a first transistor;
a first pixel and a second pixel; and
a first wire, a second wire, and a third wire, wherein the first wire, the second wire and the third wire are electrically connected to the circuit,
wherein the second wire is electrically connected to the first pixel,
wherein the third wire is electrically connected to the second pixel,
wherein the circuit is configured to distribute a signal from the first wire to the second wire and the third wire,
wherein the first transistor comprises a first oxide semiconductor film and a second oxide semiconductor film on the first oxide semiconductor film, and
wherein an atomic ratio of indium in the first oxide semiconductor film is different from an atomic ratio of indium in the second oxide semiconductor film.

US Pat. No. 10,115,629

AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICES

International Business Ma...

1. A semiconductor device, comprising:a first metallic structure and a second metallic structure disposed adjacent to each other on a substrate with a space disposed between the first and second metallic structures, wherein the first metallic structure comprises a gate structure of a transistor and wherein the second metallic structure comprises a source/drain contact; and
a dielectric capping layer formed over the first and second metallic structures to form an air gap in the space between the first and second metallic structures;
wherein an upper portion of the air gap is disposed above an upper surface the first metallic structure and below an upper surface of the second metallic structure; and
wherein a bottom portion of the air gap is disposed below a bottom surface of the second metallic structure.

US Pat. No. 10,115,628

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor apparatus, comprising:providing a semiconductor substrate;
forming a dielectric layer on the semiconductor substrate;
forming a functional layer on the dielectric layer, wherein the functional layer is capable of reacting with oxygen;
forming a hard mask layer on the functional layer;
patterning the semiconductor substrate to form an opening on the semiconductor substrate, wherein the opening goes through the hard mask layer and the functional layer and extends into the dielectric layer;
performing an oxidization process on side surfaces of the functional layer inside the opening to form oxide layers; and
performing a first process on the semiconductor substrate, wherein the first process comprises:
removing a portion of the dielectric layer that is underneath the opening to expose the semiconductor substrate; and
removing the oxide layers on the side surfaces of the functional layer to form a contact hole, wherein a first portion of the contact hole is in the functional layer, a second portion of the contact hole is in the dielectric layer, the width of the first portion of the contact hole is larger than the width of the second portion of the contact hole.

US Pat. No. 10,115,626

METHODS FOR FORMING ISOLATION BLOCKS OF SEMICONDUCTOR DEVICES, SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME

VANGUARD INTERNATIONAL SE...

1. A method for forming an isolation block of a semiconductor device, comprising:providing a semiconductor substrate;
performing an etching process to form a plurality of trenches which are parallel to each other in the semiconductor substrate, wherein a plurality of strip structures are between the trenches, the strip structures and the trenches occupy a first region in the semiconductor substrate, and the strip structures are arranged staggered with the trenches;
forming a shielding layer on the semiconductor substrate after the formation of the plurality of trenches, wherein the first region is exposed by an opening of the shielding layer; and
performing a thermal oxidation process, such that the strip structures are oxidized to form a plurality of oxidized portions, wherein the oxidized portions extend into the trenches and are connected to each other to form an isolation block in the semiconductor substrate.

US Pat. No. 10,115,625

METHODS FOR REMOVAL OF HARD MASK

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device comprising:providing a substrate prepared with isolation regions, the substrate having a non-planar substrate surface topology created by the isolation regions, wherein the substrate comprises at least first and second regions, the first region comprises a memory region and the second region comprises a logic region;
forming a hard mask layer covering the substrate and the isolation regions with a non-planar surface topology, wherein the hard mask layer comprises a pad layer and a first hard mask layer on the pad layer, the hard mask layer includes a non-planar hard mask surface topology which tracks the underlying non-planar substrate surface topology; and
selectively removing a select portion of the hard mask layer over a select region, which is one of the first and second regions, while leaving a non-select portion of the hard mask layer over a non-select region, which is other of the first and second regions, for processing of the select region of the substrate.

US Pat. No. 10,115,623

SUBSTRATE PROCESSING APPARATUS

SCREEN Holdings Co., Ltd....

1. A substrate processing apparatus for processing a substrate, comprising:a substrate holding part for holding a substrate;
a substrate rotation mechanism for rotating said substrate holding part about a central axis perpendicular to said substrate; and
a magnetic-material movement mechanism for moving a first chucking magnetic material into close proximity to said substrate holding part and moving said first chucking magnetic material away from said substrate holding part,
wherein said substrate holding part includes:
a chuck support part; and
at least three chuck members supported on said chuck support part,
said at least three chuck members includes at least one movable chuck member whose position can be changed between a chuck position and an unchuck position,
each movable chuck member included in said at least one movable chuck member includes a second chucking magnetic material that applies a force that holds an outer edge portion of said substrate on said each movable chuck member by magnetic action between said first chucking magnetic material and said second chucking magnetic material when said first chucking magnetic material is moved into close proximity to said substrate holding part, and
said substrate rotation mechanism includes:
a rotor that has an annular shape centered about said central axis and includes a permanent magnet; and
a stator that has an annular shape centered about said central axis and rotates said rotor that is in a floating state.

US Pat. No. 10,115,622

WAFER PROCESSING LAMINATE AND METHOD FOR PROCESSING WAFER

SHIN-ETSU CHEMICAL CO., L...

1. A wafer processing laminate comprising a support, a temporary adhesive material layer laminated on the support, and a wafer stacked on the temporary adhesive material layer, the wafer having a front surface on which a circuit is formed and a back surface to be processed, the temporary adhesive material layer comprising a first temporary adhesive layer composed of a thermoplastic resin layer (A) laminated on the front surface of the wafer, a second temporary adhesive layer composed of a thermosetting resin layer (B) laminated on the first temporary adhesive layer, and a third temporary adhesive layer composed of a separation layer (C) laminated between the support and the thermosetting resin layer (B), the thermoplastic resin layer (A) being soluble in a cleaning liquid (D) after processing the wafer, the thermosetting resin layer (B) being insoluble in the cleaning liquid (D) after heat curing and capable of absorbing the cleaning liquid (D) such that the cleaning liquid (D) permeates into the layer (B), the layer (C) having a peeling force of 0.5 gf or more and 50 gf or less which is required for peeling the thermosetting resin layer (B) along an interface between the thermosetting polymer layer (B) and the separation layer (C), or which is required for peeling the thermosetting polymer layer (B) with cohesion failure of the separation layer (C), when the polymer layer (B) laminated on the separation layer (C) on the support is thermally cured, as measured by 180° peeling using a test piece having a width of 25 mm.

US Pat. No. 10,115,620

APPARATUS AND METHOD FOR ADJUSTMENT OF A HANDLING DEVICE FOR HANDLING ELECTRONIC COMPONENTS

ASM TECHNOLOGY SINGAPORE ...

1. An apparatus for handling electronic components, the apparatus comprising:a rotary device;
an imaging device located on the rotary device which is positionable by the rotary device;
a plurality of pick heads arranged circumferentially around the rotary device, each pick head being operable to hold an electronic component;
a fiducial mark located at a fixed position relative to the rotary device such that the rotary device is rotatable relative to the fiducial mark, the fixed position of the fiducial mark being indicative of an arrangement of an electronic component which is held by a respective pick head; and
at least one handling device for handling the electronic components, the position of the at least one handling device being adjustable for aligning the at least one handling device with the arrangement of the electronic component held by the pick head;
wherein the imaging device is operative to capture at least one image comprising the fiducial mark and the at least one handling device for deriving an offset between the at least one handling device and the arrangement of the electronic component as indicated by the fixed position of the fiducial mark.

US Pat. No. 10,115,619

COUPLING TRANSFER SYSTEM

NATIONAL INSTITUTE OF ADV...

1. A transfer box having a sealing structure hermetically sealable by means of tight coupling of a transfer box body and a transfer box door, said transfer box structured in such a way that magnets of the transfer box body face magnetic bodies of the transfer box door when the transfer box door is closed on the transfer box body, wherein these magnets and the magnetic bodies which are connected together form a loop constituting a first magnetic closed circuit in which magnetism is transmitted through the magnets and the magnetic bodies, said magnetic bodies of the transfer box door being configured to form a loop constituting a second magnetic closed circuit with magnetized electromagnets connected together with the magnetic bodies when the electromagnets face the magnetic bodies on a side opposite to the transfer box body side in which magnetism is transmitted through the magnetic bodies and the magnetized electromagnets.

US Pat. No. 10,115,618

RETICLE TRANSFER SYSTEM AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:moving reticles in a local fabrication system, the local fabrication system comprising:
a plurality of lithography apparatuses;
a first service area configured to serve a first group of lithography apparatuses;
a second service area configured to serve a second group of lithography apparatuses; and
an internal buffer located at a boundary between the first service area and the second service area, wherein the internal buffer is a movable buffer;
transporting a first reticle from the first service area to a lithography apparatus in the second service area;
transporting a second reticle from the second service area to the lithography apparatus in the second service area; and
loading the first reticle into the internal buffer when the second reticle is processed in the lithography apparatus.

US Pat. No. 10,115,617

SYSTEM ARCHITECTURE FOR VACUUM PROCESSING

INTEVAC, INC., Santa Cla...

1. A system for processing wafers in a vacuum processing chamber, comprising:a plurality of carriers, each carrier comprising a frame having a plurality of openings, each opening configured to accommodate a single wafer;
a transport mechanism configured to transport the plurality of carriers through a loading station, to the vacuum processing chamber, and to an unloading station;
a return mechanism configured to return empty carriers from the unloading station to the loading station in an atmospheric environment, the return mechanism comprising a first carrier elevator positioned in the unloading station, a second carrier elevator positioned in the loading station, and a conveyor between the first and second carrier elevators;
a plurality of susceptors, each susceptor configured for supporting a single wafer;
an attachment mechanism for attaching a plurality of susceptors to each of the carriers, wherein each of the susceptors is attached to a corresponding position at an underside of a corresponding carrier, such that a wafer positioned on one of the susceptors is situated within one of the plurality of opening in the carrier;
a plurality of masks, each mask attached over front side of one of the plurality of opening in the carrier;
an alignment mechanism, configured to align the wafers to the masks;
a lifter configured for separating the susceptors from the carrier and masks;wherein said plurality of masks comprise:a plurality of inner masks, each configured for placing on top of one of the plurality of opening in the carrier, the inner mask having an opening-pattern to mask parts of the wafer and expose remaining parts of the wafer; and,
a plurality of outer masks, each configured for placing on top of a corresponding inner mask, the outer mask having an opening configured to partially cover the inner mask.

US Pat. No. 10,115,615

SUBSTRATE PROCESSING APPARATUS AND CONTROL METHOD OF SUBSTRATE PROCESSING APPARATUS

TOSHIBA MEMORY CORPORATIO...

1. A substrate processing apparatus comprising:a processing unit to process a substrate; and
a manipulator for maintenance, the manipulator being placed near the processing unit,
wherein the manipulator includes:
a first arm; and
a second arm combined with the first arm,
the manipulator causes the first arm and the second arm to move independently of each other according to control of a controller;
the substrate processing apparatus further comprises a load lock chamber for maintenance that can accommodate the first arm and the second arm;
wherein the manipulator, according to control of the controller, causes at least a tip portion of the second arm to move into the processing unit for the tip portion to suck a part in the processing unit and causes the first arm and the second arm to hand the part from the second arm onto the first arm and to transfer the part with the first arm into the load lock chamber.

US Pat. No. 10,115,613

METHOD OF FABRICATING A FAN-OUT PANEL LEVEL PACKAGE AND A CARRIER TAPE FILM THEREFOR

SAMSUNG ELECTRONICS CO., ...

1. A method of fabricating a semiconductor package, comprising:forming a cavity in a package substrate;
providing the package substrate and a die on a carrier tape film, the carrier tape film including a tape substrate, an adhesive layer on the tape substrate, and an insulating layer on the adhesive layer, and the die being provided in the cavity of the package substrate, wherein the adhesive layer and the insulating layer have a first light initiator and a second light initiator respectively, and wherein the package substrate includes substrate pads on a top and bottom surface of the package substrate;
forming an encapsulation layer to cover the insulating layer and the die in the cavity and cover the package substrate on the insulating layer;
irradiating a first light that selectively reacts with the first light initiator onto the adhesive layer to reduce an adhesive strength of the adhesive layer;
removing the tape substrate from the insulating layer; and
irradiating a second light that reacts with the second light initiator onto a portion of the insulating layer to form first contact holes on a portion of the package substrate and on a portion of the die.

US Pat. No. 10,115,612

MANUFACTURING METHOD FOR VERTICAL CAVITY SURFACE EMITTING LASER

Murata Manufacturing Co.,...

1. A manufacturing method for a vertical cavity surface emitting laser, the method comprising steps of:forming, on a substrate, a multilayer body including first and second Distributed Bragg Reflector layers, an active layer, and a to-be-oxidized layer becoming a current constriction structure;
processing the multilayer body such that a lateral surface of at least the to-be-oxidized layer is exposed; and
forming the current constriction structure by oxidizing the to-be-oxidized layer from the lateral surface thereof after the multilayer body has been processed,
wherein the step of forming the current constriction structure includes steps of:
placing a uniformly-heated plate on a heat conduction member, the uniformly-heated plate having a planar upper surface;
positioning the substrate along the uniformly-heated plate so that the entire substrate is spaced from the planar upper surface of the uniformly-heated plate thereby forming a gap between the planar upper surface of the uniformly-heated plate and the substrate; and
heating the substrate by radiant heat from the uniformly-heated plate by heating the heat conduction member,
wherein the uniformly-heated plate is made of an anisotropic material having a larger thermal conductivity in a planar direction than in a vertical direction, and
wherein the step of positioning the substrate includes a step of supporting a peripheral edge portion of the substrate by a spacer that is attached to the heat conduction member, and a thermal conductivity of the spacer is smaller than the thermal conductivity of the uniformly-heated plate in the vertical direction.

US Pat. No. 10,115,610

SUBSTRATE PROCESSING APPARATUS

SCREEN Holdings Co., Ltd....

1. A substrate processing apparatus comprising:a spin chuck including a disk-shaped spin base including a circular upper surface disposed under a substrate and an outer peripheral surface whose outer diameter is greater than that of the substrate, a plurality of chuck pins that hold a substrate horizontally such that a lower surface of the substrate and the upper surface of the spin base are opposed in an up-down direction across an interval, and a spin motor that rotates the spin base and the plurality of chuck pins about a vertical rotation axis passing through a central portion of the substrate held by the plurality of chuck pins;
a shielding member including a disk portion, which includes an opposed surface disposed over the substrate held by the spin chuck, and a cylinder portion, which includes an inner peripheral surface surrounding the substrate held by the spin chuck about the rotation axis and an outer peripheral surface provided with an annular outer vertical portion extending vertically, wherein a lowest end of the inner peripheral surface is disposed around the spin base, and a distance in a radial direction from the lowest end of the inner peripheral surface to the outer peripheral surface of the spin base is not less than a distance in a vertical direction from the upper surface of the substrate held by the spin chuck to the opposed surface;
an upper inert gas supply unit that causes a downward discharge port provided at the opposed surface of the shielding member to discharge downward an inert gas;
a cup that is open upward and includes a cup tubular portion that surrounds the spin base about the rotation axis, an annular cup upper end portion that is disposed at a more inward position than the cup tubular portion and an annular cup inclined portion that extends obliquely upward from the cup tubular portion to the cup upper end portion; and
an exhaust unit that discharges a gas in the cup to outside of the cup; wherein
the cup upper end portion includes an annular cup inner peripheral end, which defines a circular opening having a diameter greater than the outer diameter of the outer peripheral surface of the spin base, and a cup lower end extending downward from an inner end of the cup inclined portion,
the cup inner peripheral end is a portion that is positioned most inward in the cup upper end portion,
the cylinder portion of the shielding member is disposed between the cup upper end portion and the spin base,
the lowest end of the inner peripheral surface of the shielding member and the outer peripheral surface of the spin base define an annular discharge port which discharges an atmosphere between the substrate and the shielding member, and
the outer vertical portion of the cylinder portion of the shielding member and the cup lower end define an annular clearance between the outer vertical portion and the cup lower end.

US Pat. No. 10,115,609

SEPARATION AND REGENERATION APPARATUS AND SUBSTRATE PROCESSING APPARATUS

Tokyo Electron Limited, ...

1. A separation and regeneration apparatus comprising:a controller including a processor coupled with a memory;
a mixed gas generating unit configured to receive a wafer covered with a first fluorine-containing organic solvent having a first boiling point;
a supercritical fluid supply line connecting to the mixed gas generating unit, the supercritical fluid supply line being provided with a first valve;
a discharge line connected to the mixed gas generating unit and including a second valve; and
a distillation tank configured to store hot water, the distillation tank including:
a water supply line that allows for periodic supply of water into the distillation tank,
a water level gauge configured to measure a level of the hot water within the distillation tank,
a distillation tank heater, and
an introduction line connected to the discharge line and running between the mixed gas generating unit and the distillation tank, the introduction line terminating in the distillation tank,
wherein the controller is programmed to:
control a mixed gas generating unit heater that heats the mixed gas generating unit to a predetermined temperature;
control the distillation tank heater to maintain the water within the distillation tank at a temperature between the first boiling point and the second boiling point,
open the first valve of the supercritical fluid supply line so as to introduce a second fluorine-containing organic solvent having a second boiling point lower than the first boiling point from the supercritical fluid supply line into the mixed gas generating unit, such that a mixed gas is generated from the first fluorine-containing organic solvent covering the wafer and the second fluorine-containing organic solvent introduced from the supercritical fluid supply line; and
close the first valve of the supercritical fluid supply line and open the second valve of the discharge line so as to discharge the mixed gas from the mixed gas generating unit to the distillation tank through the discharge line such that the mixed gas is conveyed into the hot water within the distillation tank through the introduction line to be separated into a liquid state of the first fluorine-containing organic solvent, a gaseous state of the second fluorine-containing organic solvent, and F ions that will be incorporated into the hot water.

US Pat. No. 10,115,607

METHOD AND APPARATUS FOR WAFER OUTGASSING CONTROL

APPLIED MATERIALS, INC., ...

1. A semiconductor processing system, comprising:a purge station, comprising:
an enclosure;
a gas supply coupled to the enclosure;
an exhaust pump coupled to the enclosure;
a first purge gas port formed in the enclosure;
a first channel operatively connected to the gas supply at a first end and to the first purge gas port at a second end, wherein the first channel comprises:
a particle filter;
a heater; and
a flow controller;
a second purge gas port formed in the enclosure; and
a second channel operatively connected to the second purge gas port at a third end and to the exhaust pump at a fourth end, wherein the second channel comprises a dry scrubber.

US Pat. No. 10,115,606

METHODS OF PROMOTING ADHESION BETWEEN UNDERFILL AND CONDUCTIVE BUMPS AND STRUCTURES FORMED THEREBY

Intel Corporation, Santa...

1. A method of forming a package structure comprising:modifying a filler to have a surface comprising a thiol based adhesion promoter; and
subsequent to modifying the filler, adding the modified filler to an underfill material; and
forming the underfill material having the modified filler on conductive bumps of the package structure, wherein the thiol based adhesion promoter comprises a molecular weight above about 150 g/mol.

US Pat. No. 10,115,604

SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE

MediaTek Inc., Hsin-Chu ...

1. A method for fabricating a base for a semiconductor package, comprising:providing a carrier with conductive seed layers on the top surface and the bottom surface of the carrier;
forming radio-frequency (RF) devices respectively on the conductive seed layers;
laminating a first base material layer and a second base material layer respectively on the conductive seed layers, covering the RF devices; and
separating the first base material layer the second base material layer, which contain the RF devices thereon, from the carrier to form a first base and a second base.

US Pat. No. 10,115,602

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A method of manufacturing a semiconductor device, comprising:alternately stacking mold insulating layers and sacrificial layers on a substrate;
forming a plurality of channel holes penetrating through the mold insulating layers and the sacrificial layers and allowing a plurality of recessed regions to be formed in the substrate;
cleaning a surface of the plurality of recessed regions, wherein processes of forming a first protective layer in an upper region of the channel holes and performing an anisotropic dry etching process on the plurality of recessed regions in a lower portion of the channel holes are alternately repeated one or more times, in-situ;
forming epitaxial layers on the plurality of recessed regions of the substrate using the substrate in the plurality of recessed regions as seed;
forming a gate dielectric layer and a first semiconductor layer, covering a side wall of each of the channel holes and a top surface of the epitaxial layers;
forming a spacer on the gate dielectric layer, wherein processes of forming a second protective layer in the upper region of the channel holes and performing the anisotropic dry etching process on the first semiconductor layer are alternately repeated one or more times, in-situ;
removing a portion of the gate dielectric layer on the top surface of the epitaxial layers, wherein processes of forming a third protective layer in the upper region of the channel holes and performing the anisotropic dry etching process on the gate dielectric layer using the spacer as an etching mask are alternately repeated one or more times, in-situ; and
forming second semiconductor layers connected to the epitaxial layer in the channel holes.

US Pat. No. 10,115,601

SELECTIVE FILM FORMATION FOR RAISED AND RECESSED FEATURES USING DEPOSITION AND ETCHING PROCESSES

Tokyo Electron Limited, ...

1. A substrate processing method, comprising:providing a substrate having a recessed feature with a sidewall and a bottom portion;
depositing a film in the recessed feature and on a field area around the opening of the recessed feature, wherein the film is non-conformally deposited with a greater film thickness on the bottom portion than on the sidewall and the field area;
etching the film in an atomic layer etching (ALE) process in the absence of a plasma, wherein the etching thins the film on the bottom portion and removes the film from the sidewall and the field area; and
repeating the depositing and the etching at least once to increase the film thickness on the bottom portion.

US Pat. No. 10,115,598

SUBSTRATE HOLDER, A METHOD FOR HOLDING A SUBSTRATE WITH A SUBSTRATE HOLDER, AND A PLATING APPARATUS

EBARA CORPORATION, Tokyo...

1. An apparatus for plating a substrate, comprising:a plating bath configured to house the substrate and an anode; and
an intermediate mask arranged between the substrate and the anode, wherein
the intermediate mask has a plate-shaped member having an opening through which an electric field from the anode to the substrate is made to pass and a plurality of edge parts that form the opening, and wherein
the apparatus further includes a drive mechanism configured to move each of the edge parts in a direction toward the substrate in a state where the plate-shaped member is fixed to the plating bath.

US Pat. No. 10,115,597

SELF-ALIGNED DUAL-METAL SILICIDE AND GERMANIDE FORMATION

Taiwan Semiconductor Manu...

1. A method comprising:growing a first epitaxy semiconductor region on a wafer, wherein the first epitaxy semiconductor region comprises an upward facing facet facing upwardly and a downward facing facet facing downwardly;
forming a second epitaxy semiconductor region on the upward facing facet and the downward facing facet;
forming a first metal layer over the second epitaxy semiconductor region on the upward facing facet; and
performing a first anneal, wherein the first metal layer reacts with the second epitaxy semiconductor region to form a first metal silicide/germanide layer, the downward facing facet being free of the first metal silicide/germanide layer.

US Pat. No. 10,115,595

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

SUMITOMO HEAVY INDUSTRIES...

1. A method of manufacturing a semiconductor device comprising:ion-injecting a dopant into a semiconductor layer formed of a group III-V compound semiconductor containing nitrogen as a Group V element;
performing a first activation annealing on the semiconductor layer having the ion-injected dopant using a heat-treating furnace under temperature conditions of 700° C. to 900° C.; and
performing a second activation annealing by allowing a pulsed laser beam to be incident on the semiconductor layer after the first activation annealing is performed,
wherein annealing is performed in a nitrogen atmosphere during the performing of the second activation annealing.

US Pat. No. 10,115,593

CHEMICAL MODIFICATION OF HARDMASK FILMS FOR ENHANCED ETCHING AND SELECTIVE REMOVAL

Applied Materials, Inc., ...

1. A carbon-based hardmask layer, comprising:a substrate; and
an amorphous carbon layer above the substrate, the amorphous carbon layer comprising carbon and hydrogen, and the amorphous carbon layer comprising a metallic filler bonded to the carbon, wherein a total atomic percentage of the hydrogen in the amorphous carbon layer is between 5% and 50%, and the total atomic percentage of the metallic filler in the amorphous carbon layer is between 5% and 90%.

US Pat. No. 10,115,591

SELECTIVE SIARC REMOVAL

Tokyo Electron Limited, ...

1. A method for an integration process of selectively removing a silicon-containing antireflective coating (SiARC) in a substrate, the method comprising:providing a substrate in a process chamber, the substrate comprising:
a resist layer, a SiARC layer, a pattern transfer layer, and an underlying layer;
performing a pattern transfer process configured to remove the resist layer and create a structure on the substrate, the structure comprising portions of the SiARC layer and the pattern transfer layer;
performing a nitridation modification process on the SiARC layer of the structure, the nitridation modification process using a plasma of nitrogen ions and bombarding the SiARC layer to implant the nitrogen ions therein to an implantation depth, converting the SiARC layer into a nitrided SiARC layer having an increased nitrogen content; and
performing a removal process of the nitrided SiARC layer of the structure, wherein the increased nitrogen content increases percent removal of the SiARC layer and increases etch selectivity of the SiARC layer relative to the pattern transfer layer and/or the underlying layer.

US Pat. No. 10,115,590

MANUFACTURING OF SILICON STRAINED IN TENSION ON INSULATOR BY AMORPHISATION THEN RECRYSTALLISATION

1. A method for making a structure comprising a strained silicon layer, the method comprising:providing a substrate that has at least one region coated with a stack comprising a silicon semiconducting layer, the silicon semiconducting layer itself being coated with a second semiconducting area comprising silicon germanium, the second semiconducting area itself being coated with a third semiconducting area comprising an interface delimitation layer that is in contact with the second semiconducting area, the interface delimitation layer being made of silicon or silicon germanium with a germanium concentration lower than a germanium concentration of the second semiconducting area;
making at least one ion implantation such that the silicon semiconducting layer and the second semiconducting area are selectively amorphised, while keeping a continuous crystalline portion in the third semiconducting area; and then
recrystallising the second semiconducting area and the silicon semiconducting layer using the continuous crystalline portion of the third semiconducting area as a starting area for a recrystallisation front, the second semiconducting area imposing its parameter on the silicon semiconducting layer so as to strain the silicon semiconducting layer.

US Pat. No. 10,115,588

SUBSTRATE TREATING APPARATUS AND SUBSTRATE TREATING METHOD

SCREEN Holdings Co., Ltd....

1. A substrate treating apparatus, comprising:a mount unit on which a carrier for accommodating a plurality of substrates is placed;
a substrate level detecting mechanism that detects presence/absence of a substrate and a level of the substrate;
a substrate condition acquiring unit that acquires an inclination of the substrate in a forward/backward direction relative to a horizontal direction in accordance with the detected presence/absence of the substrate and the detected level of the substrate;
a poor inclination determining unit that determines whether or not the inclination of the substrate is larger than a pre-set threshold; and
an unloading order changing unit that reverses an order, in regard to unloading of the plurality of substrates in the carrier from the top, between the poor inclined substrate and a substrate at least immediately above the poor inclined substrate when the poor inclination determining unit determines presence of the poor inclined substrate.

US Pat. No. 10,115,587

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device comprising:providing a silicon wafer manufactured by a floating method from a polycrystalline silicon ingot, the silicon wafer having a first main surface and a second main surface that are opposite to each other;
forming an oxide layer on the first main surface of the silicon wafer, the oxide layer having an opening through which the silicon wafer is exposed and in which a diffusion source is filled; and
performing heat treatment to the silicon wafer with the oxide layer formed thereon, to thereby diffuse impurity from the diffusion source at the first main surface to the second main surface of the silicon wafer, so as to create a diffusion layer that forms a pn junction with the silicon wafer, wherein
the heat treatment is performed for a time that is at least as long as a time for forming the diffusion layer with a predetermined diffusion depth of 100 ?m, and
the entire heat treatment has a single heat treatment step that is performed in a diffusion furnace, in a nitrogen-free inert gas atmosphere and at a temperature that is more than 1300° C. and no more than 1350° C.

US Pat. No. 10,115,586

METHOD FOR DEPOSITING A PLANARIZATION LAYER USING POLYMERIZATION CHEMICAL VAPOR DEPOSITION

Tokyo Electron Limited, ...

1. A method for processing a substrate, the method comprising:providing a substrate containing a plurality of features with gaps between the plurality of features;
delivering precursor molecules by gas phase exposure to the substrate;
adsorbing the precursor molecules on the substrate to at least substantially fill the gaps with a layer of the adsorbed precursor molecules; and
reacting the precursor molecules to form a polymer layer that at least substantially fills the gaps.

US Pat. No. 10,115,584

COMPOSITION AND METHOD FOR FORMING A DIELECTRIC LAYER

Ramot at Tel-Aviv Univers...

1. A method of forming a porous layer, comprising:disassembling peptide supramolecular structures into discrete peptide nanospheres;
coating a substrate with a composition comprising a sol-gel precursor and a mixture of said discrete nanospheres in a medium that at least partially prevents assembly of said nanosphreres into supramolecular or colloidal structures, wherein a variance in a size of said nanosphreres is less than 2 nm2;
drying said composition; and
treating said dried composition so as to decompose said nanospheres, thereby forming voids in said dried composition.

US Pat. No. 10,115,583

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

HITACHI KOKUSAI ELECTRIC ...

1. A method of manufacturing a semiconductor device, comprising:supplying a process gas to a process chamber in a state in which a substrate with an insulating film formed thereon is mounted on a substrate support part inside the process chamber;
forming a first silicon nitride layer on the insulating film by supplying a first electric power from a plasma generation part to the process chamber and generating plasma of the process gas; and
forming a second silicon nitride layer, whose stress is lower than a stress of the first silicon nitride layer, on the first silicon nitride layer by supplying a second electric power from an ion control part to the process chamber in addition to supplying the first electric power and generating the plasma of the process gas.

US Pat. No. 10,115,582

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate comprising a MEMS region and a connection region thereon;
a dielectric layer disposed on said substrate in said connection region;
a poly-silicon layer disposed on said dielectric layer, wherein said poly-silicon layer serves as an etch-stop layer;
a connection pad disposed on said poly-silicon layer;
a passivation layer covering said dielectric layer and directly contacting with said poly-silicon layer, wherein said passivation layer comprises an opening that exposes entire said connection pad and a transition region between said connection pad and said passivation layer; and
a conductive layer conformally covering said connection pad and said poly-silicon layer in said opening of said passivation layer.

US Pat. No. 10,115,581

REMOVAL OF PARTICLES ON BACK SIDE OF WAFER

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a semiconductor device, comprising:loading a semiconductor wafer into a wafer handling system, the semiconductor wafer having a front side and a back side and having an outer rim, an inner region, and an outer region, wherein one or more alignment marks are positioned in an outer region of the wafer's front side, wherein the outer region is shaped an as annular ring having a predetermined width, wherein an outer boundary of the annular ring is spaced apart from the outer rim of the wafer by a distance in a range of about 2 mm to about 3 mm;
removing, with a brush, contaminant particles in the outer region of the wafer's back side without brushing the outer rim and without brushing the inner region, such that the brush is passed over the outer region on the back side of the wafer;
holding the brush against the back side of the wafer with tension provided by a spring; and
collecting the removed contaminant particles and discarding the collected contaminant particles out of the wafer handling system.

US Pat. No. 10,115,579

METHOD FOR MANUFACTURING WAFER-LEVEL SEMICONDUCTOR PACKAGES

ASM TECHNOLOGY SINGAPORE ...

1. Method for manufacturing a semiconductor package, comprising the steps of:providing a semiconductor wafer including a plurality of bond pads on a first side of the wafer;
covering the first side of the wafer with a dielectric material to form a dielectric layer over the bond pads;
removing portions of the dielectric layer corresponding to positions of the bond pads to form a plurality of wells, wherein each well is configured to form a through-hole between top and bottom surfaces of the dielectric layer for exposing each bond pad;
depositing a conductive material into the wells to form a conductive layer between the bond pads and a top surface of the dielectric layer; and thereafter
singulating the semiconductor wafer to form a plurality of semiconductor packages.

US Pat. No. 10,115,578

WAFER AND METHOD OF PROCESSING WAFER

Disco Corporation, Tokyo...

1. A method of processing a wafer having on a face side thereof a device area with a plurality of devices formed therein and an outer circumferential excess area surrounding the device area, comprising:a grinding step for grinding a reverse side of the wafer corresponding to the device area with a grinding wheel that is smaller in diameter than the wafer, thereby forming a first portion corresponding to the device area and an annular second portion surrounding said first portion, said annular second portion being thicker and more protrusive toward a reverse side thereof than said first portion,
wherein in the grinding step, said grinding wheel and said wafer are moved relatively to each other so that an angle formed between the reverse side of said first portion and an inner side surface of said annular second portion is larger than 45° and smaller than 75°.

US Pat. No. 10,115,577

ISOTOPE RATIO MASS SPECTROMETRY

California Institute of T...

1. A method of isotope ratio mass spectrometry, comprising:injecting a sample for analysis into a gas chromatography column;
directing an effluent from the gas chromatography column to a switching arrangement; and
selecting a configuration of the switching arrangement, such that: in a first mode, the effluent from the gas chromatography column is provided as an input to a peak broadener; and in a second mode, an effluent from the peak broadener is provided to a mass spectrometer for isotope ratio mass spectrometry without the effluent from the gas chromatography column being provided as an input to the peak broadener.

US Pat. No. 10,115,575

PROBABILITY-BASED LIBRARY SEARCH ALGORITHM (PROLS)

DH Technologies Developme...

1. A system for determining corresponding mass peaks in experimental and library product ion spectra using a mass-to-charge ratio (m/z) tolerance probability function with values between 1 and 0, comprising:an ion source that ionizes one or more known compounds of a sample, producing an ion beam of precursor ions;
a tandem mass spectrometer that receives the ion beam from the ion source and that selects at least one precursor ion from the ion beam corresponding to at least one compound of the one or more known compounds and fragments the at least one precursor ion, producing a product ion mass spectrum for the at least one precursor ion; and
a processor in communication with the tandem mass spectrometer that
receives the product ion mass spectrum from the tandem mass spectrometer,
receives an m/z tolerance probability function that varies from 1 to 0 with increasing values of an m/z difference between two mass peaks and that includes one or more values between 1 and 0,
retrieves from a memory a library product ion mass spectrum for the at least one compound,
calculates an m/z difference between at least one experimental product ion mass peak in the product ion mass spectrum and at least one library product ion mass peak in the library product ion mass spectrum,
calculates an m/z tolerance probability, (pm/z)1, from the m/z difference using the m/z tolerance probability function, and
determines if the at least one experimental product ion mass peak and the at least one library product ion mass peak are corresponding peaks based on the m/z tolerance probability, (pm/z)1.

US Pat. No. 10,115,574

HERMETICALLY SEALED MAGNETIC KEEPER CATHODE

Kurt J. Lesker Company, ...

1. A sputtering cathode comprising:a magnet array including an outer, ring magnet surrounding an inner, disk magnet;
a sputtering target on one side of the magnet array covering a side of the ring magnet and a side of the disk magnet;
a magnetic keeper disk between the sputtering target and the disk magnet, the magnetic keeper disk in contact with the sputtering target and spaced from the disk magnet by a gap;
a cooling well between the ring magnet and the disk magnet, wherein the cooling well is in direct contact with the sputtering target;
one or more cooling tubes coupled to the cooling well;
an outer body flange surrounding the one or more cooling tubes and contacting a side of the ring magnet opposite the sputtering target;
an inner body flange contacting a side of the disk magnet opposite the sputtering target; and
one or more insulators positioned between the ring magnet and the disk magnet, the one or more insulators coupling the inner body flange, the outer body flange, and the one or more cooling tubes together in an operative relation, and electrically isolating the inner body flange, the outer body flange, and the one or more cooling tubes from each other without the use of one or more elastomer seals.

US Pat. No. 10,115,572

METHODS FOR IN-SITU CHAMBER CLEAN IN PLASMA ETCHING PROCESSING CHAMBER

Applied Materials, Inc., ...

1. A method for in-situ chamber cleaning after an etching process, comprising:supplying a cleaning gas mixture including at least an oxygen containing gas and a hydrogen containing gas into a processing chamber in which the etching process was performed on a substrate comprising Cr containing material;
controlling a processing pressure at less than 2 millitorr;
applying a RF source power to the processing chamber to form a plasma from the cleaning gas mixture; and
cleaning the processing chamber in the presence of the plasma.

US Pat. No. 10,115,571

REAGENT DELIVERY SYSTEM FREEZE PREVENTION HEAT EXCHANGER

APPLIED MATERIALS, INC., ...

1. A reagent delivery system, comprising:a water tank having an inner volume that holds a reagent liquid when disposed therein; and
a heat exchanger having a central opening disposed in the inner volume and configured to keep a top surface of the reagent liquid from freezing when reagent liquid is disposed within the water tank,
wherein the heat exchanger is formed from a plurality of concentric cylinders that permits a flow of a reagent liquid between the concentric cylinders, and wherein each of the plurality of concentric cylinders is perforated to allow the reagent liquid to flow through the concentric cylinders.

US Pat. No. 10,115,566

METHOD AND APPARATUS FOR CONTROLLING A MAGNETIC FIELD IN A PLASMA CHAMBER

APPLIED MATERIALS, INC., ...

1. An electromagnetic cosine-theta (cos ?) coil ring assembly for use in a process, comprising:a cylindrical body;
an inner electromagnetic cosine-theta (cos ?) coil ring including a first plurality of inner coils disposed about an inner surface of the cylindrical body and configured to generate a magnetic field in a first direction; and
an outer electromagnetic cosine-theta (cos ?) coil ring including a second plurality of outer coils disposed about an outer surface of the cylindrical body and configured to generate a magnetic field in a second direction different from the first direction, wherein the outer electromagnetic cos ? coil ring is disposed concentrically about the inner electromagnetic cos ? coil ring.

US Pat. No. 10,115,565

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

PANASONIC INTELLECTUAL PR...

1. A plasma processing apparatus comprising;an induction coupling-type plasma torch unit that includes
a dielectric member that defines a ring-shape chamber constituting ring-shape space which communicates with an opening portion having an opening width of 1 mm or more,
a gas supply pipe that introduces gas into an inside of the ring-shape chamber, and
a coil that is provided in a vicinity of the dielectric member defining the ring-shape chamber;
a high-frequency power supply that is connected to the coil; and
a base material mounting table that is configured to be mounted with a base material near the opening portion, wherein a distance between an end surface of the opening portion and a base material is 1 mm or less, wherein
the dielectric member has an outside dielectric block that defines an outside boundary of the ring-shape space; and an inside dielectric block that is inserted into the outside dielectric block and defines an inside boundary of the ring-shape space,
the shape of the ring-shaped space is a continuous loop having straight portions constituted by two long sides and two short sides connected to both ends of the straight portions, the two short sides being semicircular, semielliptical, or linear, and
the opening portion is a linear rectangular opening portion provided along only one of the two long sides constituting the straight portions, the opening portion opening towards a direction perpendicular to the longitudinal direction of the one of the two long sides.

US Pat. No. 10,115,564

UNIFORMITY CONTROL CIRCUIT FOR USE WITHIN AN IMPEDANCE MATCHING CIRCUIT

Lam Research Corporation,...

1. A system comprising:a kilohertz (kHz) radio frequency (RF) generator for generating and supplying a kHz RF signal;
a megahertz (MHz) RF generator for generating and supplying a MHz RF signal;
a first RF cable connected to an output of the kHz RF generator for receiving the kHz RF signal;
a second RF cable connected to an output of the MHz RF generator for receiving the MHz RF signal;
an impedance matching circuit coupled to the kHz RF generator via the first RF cable and coupled to the MHz RF generator via the second RF cable, wherein the impedance matching circuit has an output and includes:
a first circuit including a first plurality of tuning elements located along a path for transferring the kHz RF signal;
a second circuit including a second plurality of tuning elements for transferring the MHz RF signal, wherein the first and second circuits are coupled to the output; and
a uniformity control circuit defined from at least one of the first plurality of tuning elements;
an RF transmission line coupled to the impedance matching circuit; and
a plasma chamber including an electrode, wherein the electrode is connected to the RF transmission line;
wherein the uniformity control circuit is located serially along the path of the first circuit to define a capacitance to adjust a radial uniformity profile of an etch rate produced using the plasma chamber, to provide a pre-determined level of isolation from the MHz RF signal, and to achieve a pre-determined level of power delivered by the kHz RF generator to the electrode of the plasma chamber.

US Pat. No. 10,115,562

SYSTEMS INCLUDING A BEAM PROJECTION DEVICE PROVIDING VARIABLE EXPOSURE DURATION RESOLUTION

Samsung Electronics Co., ...

1. A beam projection device, comprising: a charged particle beam source configured to radiate a first beam; an aperture plate having a first array of apertures therein, respective ones of the apertures configured to generate respective second beams from the first beam; a blanking aperture plate having an array of blanking apertures therein corresponding to respective apertures of the first array of apertures and configured to selectively deflect second beams passing therethrough responsive to voltages applied to respective potential electrodes of the blanking apertures; a limiting aperture plate comprising a limiting aperture configured to pass ones of the second beams not deflected by the blanking apertures; and a plurality of electrode control circuits, respective ones of which are configured to apply voltages to respective ones of the potential electrodes, wherein, during a first time interval, the plurality of electrode control circuits applies voltages to the potential electrodes for durations based on clock signal with a first frequency, wherein, during a second time interval, the plurality of electrode control circuits applies voltages to the potential electrodes for durations based on a clock signal with a second frequency different from the first frequency, and wherein, during the first time interval and second time interval, beams passing through the limiting aperture are projected on the same target object to provide overlapping exposures of the target object.

US Pat. No. 10,115,560

APPARATUS FOR MODIFYING SURFACES OF TITANIUM IMPLANTS MADE OF TITANIUM ALLOY

Sodick Co., Ltd., Kanaga...

1. A metal surface modification apparatus for modifying surfaces of titanium implants made of a titanium alloy, the metal surface modification apparatus comprising:a vacuum chamber configured to accommodate the implants in a vacuum environment;
a transfer unit disposed within the vacuum chamber, and configured to move the implants at least in a first horizontal uniaxial direction and in a second horizontal uniaxial direction perpendicular to the first horizontal uniaxial direction;
a table disposed on the transfer unit, and configured such that the implants are placed thereon;
an electron gun including a cathode electrode, an annular anode electrode configured to generate plasma, and a solenoid configured to generate a magnetic field; and
a tilting unit configured to tilt the implants to a predetermined angle as the transfer unit moves the implants;
wherein the tilting unit further comprises:
a plurality of holding jigs configured to have a plurality of respective lower parts having curved surfaces, respectively, and to hold the implants, respectively;
a movable holding base fastened onto the table, and configured to have a plurality of receiving depressions formed through an upper surface thereof to have curved surfaces corresponding to the curved surfaces of the lower parts of the holding jigs; and
a stationary pushing plate disposed on the movable holding base to cover the movable holding base, and configured to be moved relative to the movable holding base and to have a plurality of through holes positioned to face the receiving depressions.

US Pat. No. 10,115,559

APPARATUS OF PLURAL CHARGED-PARTICLE BEAMS

HERMES MICROVISION, INC.,...

1. A method for converting a single charged particle source into a plurality of virtual sub-sources, comprising steps of:deflecting, by a plurality of micro-deflectors of a micro-deflector array, a charged-particle beam of the single charged-particle source into a plurality of parallel beamlets forming a plurality of virtual images respectively, wherein each of the plurality of virtual images is one of the plurality of sub-sources;
adding, by a plurality of micro-compensators of a micro-compensator array, aberrations to each of the plurality of virtual images, wherein each micro-compensator of the plurality of micro-compensators is aligned with a corresponding one of the micro-deflectors; and
cutting a current of each of the plurality of beamlets.

US Pat. No. 10,115,558

METHODS AND DEVICES FOR CHARGE COMPENSATION

Carl Zeiss Microscopy Gmb...

1. A method, comprising:a) scanning a primary particle beam over a surface of a sample for a duration of a time I1;
b) introducing a gas pulse for a duration of time I2, which overlaps with I1, so that a region of the sample surface is discharged;
c) detecting interaction products of the primary particle beam and the sample during a) and b);
d) generating a first image of the sample on the basis of the detected interaction products; and
e) selecting a partial image from the first generated image so that image regions having image interference are not contained in the partial image,
wherein I2 is less than 100 milliseconds.

US Pat. No. 10,115,557

X-RAY GENERATION DEVICE HAVING MULTIPLE METAL TARGET MEMBERS

HAMAMATSU PHOTONICS K.K.,...

1. An X-ray generation device comprising:an electron gun for emitting an electron beam;
a target unit having a target buried in a substrate having principal faces opposed to each other;
a housing at one end side of which the target unit is arranged and at the other end side opposed to the one end side of which the electron gun is arranged, the housing having an electron passage for the electron beam to pass;
a deflector for deflecting the electron beam passing in the electron passage to enable scanning on the target unit;
a signal acquisition unit for acquiring an incident signal generated from scanning the target unit with the electron beam; and
a control unit for controlling the deflector, based on the incident signal acquired by the signal acquisition unit,
wherein the target unit comprises:
the substrate comprising an electrical insulating material having X-ray permeability
a plurality of first metal members buried in the substrate and serving as the target; and
one or more second metal members, the one or more second metal members being surrounded by the plurality of first metal members or surrounding at least one of the plurality of first metal members, and the one or more second metal members generating location information by serving as a reference when identifying a location of the at least one of the plurality of first metal members based on the incident signal generated from the scanning with the electron beam,
wherein the one or more second metal members, when viewed from a normal direction to the principal faces, have a surface area larger than the a surface area of the plurality of first metal members, and have a length in the normal direction shorter than a length of the target, and
the control unit controls the deflector to scan the electron beam over the target, detects the plurality of first metal members based on the location information of the one or more second metal members acquired from the incident signal, and controls the deflector to irradiate the first metal member with the electron beam and generate X-rays.

US Pat. No. 10,115,556

TRIODE HOLLOW CATHODE ELECTRON GUN FOR LINEAR PARTICLE ACCELERATORS

Altair Technologies, Inc....

1. A triode hollow-cathode electron gun configured to provide electrons and substantially mitigates the impact of back-streaming electrons, the triode hollow-cathode electron gun comprising;a hollow cathode with a concave surface configured to emit a beam of electrons, wherein the cathode is impregnated with Barium to enhances emission of the beam of electrons by lowering work function of the cathode, and wherein the hollow cathode includes an axially-oriented cylindrical channel configured to accommodate back streaming of the beam of electrons;
a heating filament configured to provide heat to the hollow cathode enabling a thermionic emission process;
an anode configured to attract and focus the beam of electrons emitted from the hollow cathode by maintaining a positive voltage potential relative to the cathode;
a control grid configured to control or modulate and focus the beam of electrons emitted from the hollow cathode, wherein the control grid has a concave profile; and
a protruding sleeve that is substantially centered on the axis of the triode hollow-cathode electron gun and configured to maintain a convergent shape and a trajectory of the emitted beam of electron, wherein the protruding sleeve increasing the laminarity of the beam of electrons by reducing undesirable transverse momentum of the beam of electrons, and wherein the sleeve is further configured to inhibit release of Barium from the cathode thereby increasing cathode life.

US Pat. No. 10,115,555

ELECTRICAL SWITCH FOR A LOAD IN A VEHICLE

Amazon Technologies, Inc....

1. An unmanned aerial vehicle (UAV), comprising:a frame;
a power load;
a power source; and
an electrical switch comprising a moving member and a plurality of electrically conductive members, the plurality of electrically conductive members configured to move between mechanical positions in a predefined order to electrically couple the power load and the power source, wherein:
a first electrically conductive member is configured to move to a first mechanical position and form a first electrically conductive path between the power load and the power source based at least in part on the first mechanical position, the first electrically conductive path having first electrical resistivity;
a second electrically conductive member is configured to move to a second mechanical position and form a second electrically conductive path between the power load and the power source based at least in part on the second mechanical position, the second electrically conductive path having second electrical resistivity different from the first electrical resistivity; and
the moving member is configured to move the second electrically conductive member based at least in part on movement of the first electrically conductive member to the first mechanical position such that movement of the second electrically conductive member to the second mechanical position occurs based at least in part on the movement of the first electrically conductive member according to the predefined order.

US Pat. No. 10,115,554

FUSE CASE AND CASE COVER OF VACUUM CONTACTOR

LSIS CO., LTD., Anyang-S...

1. A fuse case and a case cover, which are detachable and applied to a vacuum contactor including a truck, a main circuit unit, and a front cover covering a front side of the main circuit unit, the fuse case and the case cover comprising:a fuse connected to an upper terminal of the main circuit unit and blowing, when a fault current is generated in a circuit, to break the circuit;
the fuse case opened in an upper side, accommodating the fuse, and having an insertion coupling part formed on a side surface thereof; and
the case cover coupled to the upper side of the fuse case, coupled to the insertion coupling part in an insertion-coupling manner, and covering a rear end portion of the fuse,
wherein the case cover includes an upper surface portion and side surface portions, and the side surface portions include a first side surface portion formed on a front side and a second side surface portion formed on a rear side,
wherein the first and second side surface portions are formed as dual walls and have a first rail recess and a second rail recess, respectively, and
wherein the side surface of the fuse case is inserted into the first rail recess and the second rail recess.

US Pat. No. 10,115,553

GROUND FAULT CIRCUIT INTERRUPTER AND RESET MECHANISM THEREOF

ZHANGJIAGANG CITY BAREP E...

1. A reset mechanism of a ground fault circuit interrupter (GFCI), comprising: a reset button and a reset lever disposed at a bottom of the reset button, wherein the reset mechanism further comprises: an electromagnet, a slide rocker, a rotary lifting block, and a reset mounting bracket, wherein rotating shafts are separately disposed at two sides of the rotary lifting block; the rotary lifting block is disposed on the reset mounting bracket in a movable manner by using the pair of rotating shafts; lifting parts protruding outwards are separately disposed at two sides of one end of the rotary lifting block; a clamping hook facing inwards is disposed on a bottom surface of another end of the rotary lifting block; a lifting block spring used for resetting the rotary lifting block is disposed on one side of the lifting part of the rotary lifting block; a bottom of the lifting block spring abuts against the rotary lifting block; a position-limiting block matched with one side of the lifting part of the rotary lifting block is disposed on the reset mounting bracket; the reset mounting bracket is provided with a rocker insertion hole matched with the slide rocker below the rotary lifting block; the slide rocker penetrates the rocker insertion hole in a movable manner; the slide rocker is provided with a rocker bending part on an end part of one side of the lifting part of the rotary lifting block; an end part of the rocker bending part is provided with a rocker bayonet; the electromagnet is disposed at one side of the rocker bending part of the slide rocker; an iron core of the electromagnet is provided with an iron core card slot matched with the rocker bayonet; the rocker bayonet is clamped to the iron core card slot of the iron core; the reset lever is disposed above one side of the clamping hook of the rotary lifting block in a movable manner; and a reset lever spring used for resetting the reset button is sleeved on the reset lever.

US Pat. No. 10,115,552

RETROFIT CAFI/GFI REMOTE CONTROL MODULE

Schneider Electric USA, I...

1. A retrofit remote control module providing a simple thermal-magnetic circuit breaker with arc fault or ground fault, or both, sensing and interruption capabilities for a branch circuit, comprising:a case housing a current path with neutral and line conductors,
line sensors for sensing current flow within the current path,
electronics connected to the line sensors to determine anomalies in the sensed current flow, and
a bistable relay in the current path between the simple thermal-magnetic circuit breaker and the load, the relay being operated by said electronics to open the branch circuit; and
connectors for attaching the neutral and line conductors to a branch circuit on a downstream side of the module, and attaching the neutral and line conductors to the load side of the simple thermal-magnetic circuit breaker on an upstream side of the module.

US Pat. No. 10,115,550

ELECTRICAL SWITCHING DEVICE WITH A LOW SWITCHING NOISE

TE Connectivity Germany G...

1. An arrangement for an electrical switching device, comprising:a contact spring; and
a component attached to the contact spring at a fastening location and having an edge extending in an inclined manner with respect to a longitudinal direction of the contact spring, the component having at least two switching state positions and a transition phase between the switching state positions, the component movable with respect to the contact spring between the two switching state positions and abutting the contact spring along the edge in the transition phase, the edge abutting the contact spring at an abutting location positioned at an intersection of the edge with a line extending through the fastening location orthogonal to the longitudinal direction.

US Pat. No. 10,115,549

ELECTRICAL STORAGE SYSTEM

TOYOTA JIDOSHA KABUSHIKI ...

1. An electrical storage system comprising:an electrical storage device;
a load;
a positive electrode line that connects the electrical storage device to the load;
a negative electrode line that connects the electrical storage device to the load;
a first relay provided in the positive electrode line;
a second relay provided in the negative electrode line;
a third relay connected in series with a first resistive element, the third relay and the first resistive element being connected in parallel with the first relay, the first resistive element being provided in the positive electrode line;
a drive circuit including a coil, a first power line, a second power line, and a sensor,
the coil being configured to generate electromagnetic force for switching the second relay and the third relay from a non-energized state to an energized state by energization at a first current value, the coil being configured to generate electromagnetic force for switching the first relay, the second relay and the third relay from a non-energized state to an energized state by energization at a second current value larger than the first current value, the energized state being on state, the non-energized state being off state,
the first power line including a first switch element and a second switch element connected in series with each other, the first power line being configured to supply current having the second current value from a power supply to the coil,
the second power line including a second resistive element and a third switch element connected in series with each other, the second power line being configured to supply current having the first current value from the power supply to the coil, and
the sensor being configured to change an output signal on the basis of whether each switch element is in the energized state or the non-energized state,
the drive circuit being configured to cause both the second and third relays and the first relay to operate at different timings; and
a controller configured to:
(a) control operation of the drive circuit,
(b) output a control signal for setting each switch element to the non-energized state, and
(c) determine whether any one of the switch elements has a failure in the energized state on the basis of the output signal of the sensor.

US Pat. No. 10,115,547

MEDIUM OR HIGH VOLTAGE SWITCH BUSHING

Hubbell Incorporated, Sh...

1. A medium or high voltage switch, comprising:a bottle assembly comprising:
a bottle formed of a first material and defining a chamber; and
a plurality of contacts for selectively opening and closing an electrical circuit, the plurality of contacts disposed within the chamber;
a bushing formed of a second material and defining a cavity configured to receive the bottle assembly;
a sleeve formed of a third material and overmolded onto the bottle; and
a dielectric grease disposed between the bottle assembly and the bushing,
wherein the bottle assembly and the bushing have an interference fit.

US Pat. No. 10,115,546

ELECTRICAL TRIPOUT DEVICE INTEGRATING A CIRCUIT BREAKER AND AN ISOLATOR

GENERAL ELECTRIC TECHNOLO...

1. A current-interrupter device (1) comprising a circuit breaker (2) including a first stationary conductive support (4) carrying both a stationary arcing contact (14) and a movable arcing contact (16) that is movable between a closed position and an open position, and also carrying a movable permanent contact (17) that is movable between a closed position and an open position, the movable arcing contact (16) and the movable permanent contact (17) being dynamically linked together by forming a single movable unit and being electrically connected to the first stationary conductive support (4), and a disconnector (3) including a second stationary conductive support (6) carrying a disconnector contact (18) that is movable between a closed position and an open position, and wherein:the movable disconnector contact (18) is electrically connected with the stationary arcing contact (14) when the movable disconnector contact (18) is in its closed position;
the movable disconnector contact (18) is spaced apart from the stationary arcing contact (14) when the movable disconnector contact (18) is in its open position;
the movable disconnector contact (18) and the movable permanent contact (17) are electrically connected to each other when they are both in their respective closed positions;
the movable disconnector contact (18) and the movable permanent contact (17) are spaced apart from one another when the movable disconnector contact (18) is in its open position; and
the movable disconnector contact (18) and the movable permanent contact (17) are spaced apart from one another when the movable permanent contact (17) is in its open position.

US Pat. No. 10,115,545

ACTUATING METHOD AND DEVICE FOR A HELICOIDAL SWITCH

GORLAN TEAM, S.L.U., (ES...

1. An actuating device for mechanically converting rotational movement into helicoidal movement, the actuating device comprising:a fixed body having a through cavity extending along an axis, said fixed body being provided with two guiding surfaces parallel to one another and arranged in an inclined manner,
a moving rod housed such that it has the capacity for movement in said through cavity, the moving rod being provided with a lug emerging radially with respect to an axial axis of the rod,
wherein said lug is arranged tightly between said guiding surfaces, such that it can slide over them, making contact with both surfaces; and
wherein the guiding surfaces comprise an annular shape arranged around the through cavity, and where the guiding surfaces are accessible from outside the fixed body.

US Pat. No. 10,115,544

SINGULATED KEYBOARD ASSEMBLIES AND METHODS FOR ASSEMBLING A KEYBOARD

APPLE INC., Cupertino, C...

1. A row of interconnected key assemblies comprising:an array of key assemblies, each key assembly comprising:
a chassis having a first retaining feature and a second retaining feature;
a switch housing formed on the chassis;
a key mechanism surrounding the switch housing and engaged with the first retaining feature; and
a buckling dome positioned within an opening defined through the switch housing and engaged with the second retaining feature.

US Pat. No. 10,115,541

SWITCH COMPONENT, PUSH SWITCH, ELECTRONIC DEVICE INCLUDING PUSH SWITCH

CITIZEN ELECTRONICS CO., ...

1. A switch component comprising:a metallic spring plate comprising an outer peripheral edge and at least one pair of protrusions protruding from the outer peripheral edge; and
a cover of rubber covering at least one part of an upper surface of the metallic spring plate and comprising at least one pair of supporting portions that support the metallic spring plate,
the at least one pair of supporting portions supporting the at least one pair of protrusions of the metallic spring plate from below.

US Pat. No. 10,115,539

LUMINATED KEY STRUCTURE AND ELECTRONIC DEVICE WITH THE SAME

Chiun Mai Communication S...

1. A key structure comprising:a substrate having at least one light emitting element disposed on a substrate surface thereof;
a light guiding element being made of optical transmission material and disposed opposite to the substrate; wherein the light guiding element comprises a main body and a light guiding portion, and the main body comprises a first surface and a second surface opposite to the first surface, wherein the light guiding portion projects from the first surface, and the light guiding portion and the first surface cooperatively form a receiving space;
a key body being mad of opaque material and received in the receiving space;
a first reflective film being disposed on the second surface;
a second reflective film being disposed on the substrate surface of the substrate;
wherein when light is emitted from the at least one light emitting element, the light is reflected between the first reflective film and the second reflective film, transmitted to the light guiding portion, and transmitted out of the key structure through the light guiding portion.

US Pat. No. 10,115,537

APPARATUS FOR DETECTING A SWITCH POSITION

Robert Bosch GmbH, Stutt...

1. An apparatus for detecting a configuration of a switch comprising:a first circuit node and a second circuit node configured to connect the apparatus to an AC electric voltage;
a switch connected between the first circuit node and a third circuit node;
a resistor connected between the first circuit node and the third circuit node in parallel with the switch;
a calculation device connected between the second circuit node and a microcomputer device, the calculation device further comprising at least one transistor or filter stage configured to generate digitized values of the AC electric voltage for detection by the microcomputer device; and
the microcomputer device operatively connected to the calculation device and configured to identify the configuration of the switch, the microcomputer device being operatively configured to:
measure a first amplitude of a positive half-cycle of the AC electric voltage during at least one full cycle of the AC electric voltage based on the digitized values generated by the calculation device;
measure a second amplitude of a negative half-cycle of the AC electric voltage during the at least one full cycle of the AC electric voltage based on the digitized values generated by the calculation device;
detect that the switch is open in response to an asymmetry between the first amplitude and the second amplitude of the AC electric voltage; and
detect that the switch is closed in response to a symmetry between the first amplitude and the second amplitude of the AC electric voltage.

US Pat. No. 10,115,536

ELECTROMAGNETIC ACTUATOR AND ELECTRICAL CONTACTOR COMPRISING SUCH AN ACTUATOR

SCHNEIDER ELECTRIC INDUST...

1. An electromagnetic actuator for operation of an electrical contactor, the actuator comprising:a fixed part including:
at least one coil that generates a magnetic field and that is centered on a longitudinal axis,
at least one core that concentrates the magnetic flux, the core being installed within the coil, and including a spreading plate for the magnetic field which defines an active surface which is perpendicular to the longitudinal axis and at least one magnetic flux return element;
an armature that is moveable in translation along the longitudinal axis with respect to the fixed part, between a first position which is remote from the active surface and a second position which is closer to the surface, in response to a load induced by the magnetic field;
at least one elastic return member that restores the armature to a predetermined position, from among the first position and the second position;
wherein the spreading plate includes at least one rib closing magnetic field lines between the spreading plate and the armature, the rib protrudes with respect to the active surface on the armature side, the rib is arranged at a level of one edge of the spreading plate, and the rib includes braces extending in a direction perpendicular to a longest dimension of the rib.

US Pat. No. 10,115,535

ELECTRIC STORAGE DEVICE

TAIYO YUDEN CO., LTD., T...

1. An electric storage device comprising:an electric storage element having a positive electrode and a negative electrode;
a non-aqueous electrolytic solution that contains a non-aqueous solvent primarily constituted by a non-carbonate cyclic ester and a cyclic carbonate ester, an electrolyte containing lithium salt, and a sulfonate ester derivative whose reduction potential is higher than that of the non-carbonate cyclic ester and that of the cyclic carbonate ester; and
an outer container that stores the electric storage element and non-aqueous electrolytic solution,
wherein a volume ratio of the non-carbonate cyclic ester to the cyclic carbonate ester in the non-aqueous solvent is 1/9 or more but 7/3 or less.

US Pat. No. 10,115,534

ALL-SOLID-STATE CAPACITOR WITH SOLID ELECTROLYTE HAVING A POLYCRYSTALLINE STRUCTURE

KYOCERA CORPORATION, Kyo...

1. An all-solid-state capacitor, comprising:an inorganic solid electrolyte having a polycrystalline structure, the polycrystalline structure being composed of crystal particles and a crystal grain boundary formed between the crystal particles; and
a pair of current collectors disposed so as to hold the inorganic solid electrolyte in between,
the inorganic solid electrolyte having a main crystal phase of perovskite crystal structure that is expressed by a general formula, ABO3,
A-site elements of the main crystal phase comprising Li and M which is at least one of elements in Group 2 of the Periodic Table of Elements, and
B-site elements of the main crystal phase comprising Ti and M? which is at least one of elements in Group 5 of the Periodic Table of Elements,
wherein an electrical resistivity at the crystal grain boundary in the inorganic solid electrolyte is greater than or equal to 5×102 ?m,
wherein a grain boundary phase is present at the crystal grain boundary of the crystal particles composed of the main crystal phase, and the grain boundary phase is composed of an amorphous phase or a crystal phase which differs from the main crystal phase.

US Pat. No. 10,115,533

RECHARGEABLE POWER SOURCE COMPRISING FLEXIBLE SUPERCAPACITOR

UNIVERSITI PUTRA MALAYSIA...

1. A rechargeable power source for an electronic device, characterized in that, the rechargeable power source comprising:a flexible supercapacitor comprising an electrolyte sandwiched between nickel foams electrodeposited with a nanocomposite, wherein the said nanocomposite comprises a conducting polymer, graphene oxide and a metal oxide; and
a charge connection unit comprising a microcontroller having an electrical connection line connecting an energy collecting unit with the flexible supercapacitor.

US Pat. No. 10,115,531

ENERGY STORAGE DEVICE HAVING IMPROVED HEAT-DISSIPATION CHARACTERISTIC

LS MITRON LTD., Anyang-s...

1. An energy storage device, comprising:a cell assembly formed by connecting at least two cylindrical energy storage cells in series;
a case having an accommodation portion shaped corresponding to an outer surface of the energy storage cells to accommodate the cell assembly; and
a heat-dissipating pad installed between the outer surface of the energy storage cells of the cell assembly and an inner surface of the accommodation portion,
wherein the case includes at least two case blocks,
wherein the accommodation portion is formed by coupling the case blocks,
wherein the heat-dissipating pad has elasticity, and
wherein an interval between the accommodation portion and the energy storage cells is smaller than a thickness of the heat-dissipating pad before being compressed and greater than a diameter tolerance of the energy storage cells.

US Pat. No. 10,115,530

SOLAR CELL AND METHODS OF FABRICATION AND USE THEREOF

SEQUENCE DESIGN LTD., No...

1. A dye-sensitized solar cell comprising:a) a first electrically conductive layer;
b) a mesoporous oxide layer contiguous with the first electrically conductive layer and comprised of volcanic ash particles and photoactive dye molecules adsorbed on the ash particles;
c) an electrolyte layer contiguous with the mesoporous oxide layer and comprised of a redox mediator;
d) a catalyst layer comprised of an electrically conductive catalyst material; and
e) a second electrically conductive layer contiguous with the catalyst layer.

US Pat. No. 10,115,529

ELECTROLYTIC CAPACITOR HAVING A SOLID ELECTROLYTE LAYER AND MANUFACTURING METHOD THEREOF

NIPPON CHEMI-CON CORPORAT...

1. A solid electrolytic capacitor, comprising:a capacitor element with an anode electrode foil and a cathode electrode foil wound with an interposed separator,
a solid electrolyte layer formed in the capacitor element by using a conductive polymer dispersion in which particles of a conductive polymer are dispersed in a solvent; and
voids inside the capacitor element in which the solid electrolyte layer has been formed filled with an electrolytic solution containing less than 9 wt % of an ammonium salt of a composite compound of inorganic acid and organic acid as a solute and containing 20 wt % or more ethylene glycol with respect to a solvent in the electrolytic solution.

US Pat. No. 10,115,526

CAPACITOR, CAPACITOR MOUNTING STRUCTURE, AND TAPED ELECTRONIC COMPONENT SERIES

Murata Manufacturing Co.,...

1. A capacitor comprising:a capacitor main body including a first main surface and a second main surface which extend along a longitudinal direction and a width direction, a first side surface and a second side surface which extend along the longitudinal direction and a thickness direction, and a first end surface and a second end surface which extend along the width direction and the thickness direction; and
a first inner electrode and a second inner electrode provided in the capacitor main body and opposing each other via a ceramic section; wherein
in the capacitor main body, a dimension along the thickness direction of a first region where the first and second inner electrodes are provided is t1;
in the capacitor main body, a dimension along the thickness direction of a second region that is positioned on a side of the first main surface relative to the first region is t2;
in the capacitor main body, a dimension along the thickness direction of a third region that is positioned on a side of the second main surface relative to the first region is t3;
a condition of t3/t1>about 0.07 is satisfied;
the ceramic section includes BaTiO3 and Mn;
a content of Mn in the ceramic section is less than about 0.2 mol part with respect to BaTiO3 of 100 mol part;
a distance along the width direction from a portion where both of the first and second inner electrodes are provided to the first side surface is w2 and a distance along the width direction from a portion where both of the first and second inner electrodes are provided to the second side surface is w3;
at least one of w2 and w3 is no more than about 70 ?m; and
at least one of w2 and w3 is no less than about 55 ?m.

US Pat. No. 10,115,525

ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a body including a capacitance portion having dielectric layers formed of a dielectric material;
internal electrodes and a cover portion covering at least one surface of the capacitance portion, the cover portion including cover layers formed of a dielectric material, the cover portion including a plurality of first and second cover layers that are stacked alternately; and
an external electrode disposed on the body, the external electrode connected to the internal electrodes,
wherein average diameters of dielectric grains included in the first and second cover layers are different from each other.

US Pat. No. 10,115,523

CERAMIC ELECTRONIC COMPONENT AND MOUNTING STRUCTURE OF THE SAME

Murata Manufacturing Co.,...

1. A ceramic electronic component comprising:a multilayer body with a rectangular parallelepiped or rectangular parallelepiped shape and including a plurality of ceramic layers, a plurality of first inner electrode layers, and a plurality of second inner electrode layers, the multilayer body including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction orthogonal or substantially orthogonal to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction orthogonal or substantially orthogonal to the lamination direction and the width direction;
a first outer electrode electrically connected to the plurality of first inner electrode layers and located on at least the first end surface of the multilayer body, and a second outer electrode electrically connected to the plurality of second inner electrode layers and located on at least the second end surface of the multilayer body;
a first substrate connection terminal bonded to at least one of the first outer electrode and the multilayer body by a bonding material that electrically insulates the first substrate connection terminal from the first outer electrode, and a second substrate connection terminal bonded to at least one of the second outer electrode and the multilayer body by a bonding material that electrically insulates the second substrate connection terminal from the second outer electrode; and
a first metal terminal electrically connecting the first outer electrode and the first substrate connection terminal, and a second metal terminal electrically connecting the second outer electrode and the second substrate connection terminal; wherein
while the first metal terminal maintains an elastically deformed state, a first end portion of the first metal terminal is bonded to the first outer electrode by an electrically conductive bonding material and a second end portion of the first metal terminal is bonded to the first substrate connection terminal by a bonding section with a different melting point from a melting point of the electrically conductive bonding material; and
while the second metal terminal maintains an elastically deformed state, a first end portion of the second metal terminal is bonded to the second outer electrode by an electrically conductive bonding material and a second end portion of the second metal terminal is bonded to the second substrate connection terminal by a bonding section with a different melting point from a melting point of the electrically conductive bonding material.

US Pat. No. 10,115,519

ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. An electronic component comprising:a multilayer body constituted by insulator layers that are laminated in a laminating direction;
a primary coil including n primary coil conductor layers and a parallel primary coil conductor layer each disposed on one of the insulator layer, n being a natural number;
a secondary coil including n secondary coil conductor layers each disposed on one of the insulator layers; and
a tertiary coil including n tertiary coil conductor layers each disposed on one of the insulator layers,
wherein current paths of the primary coil, the secondary coil, and the tertiary coil are substantially equal to one another in length,
the primary coil, the secondary coil, and the tertiary coil constitute a common mode filter,
respective ones of the primary coil conductor layers, the secondary coil conductor layers, and the tertiary coil conductor layers, are arrayed in a mentioned order from one side toward other side in the laminating direction and constitute a coil conductor layer group,
n coil conductor layer groups are arrayed from the one side toward the other side in the laminating direction, and
the parallel primary coil conductor layer is electrically connected to a predetermined primary coil conductor layer in parallel, has a substantially same shape as the predetermined primary coil conductor layer in a plan view which is a one viewed from the laminating direction, and is disposed on the other side in the laminating direction relative to a predetermined tertiary coil conductor layer which is the tertiary coil conductor layer disposed at a farthest position on the other side in the laminating direction.

US Pat. No. 10,115,518

COIL ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A coil electronic component comprising:a substrate;
a coil pattern disposed on at least one of first and second main surfaces of the substrate;
an insulating part disposed on a surface of the coil pattern to prevent short circuits between adjacent patterns in the coil pattern;
a body region filling at least a core region of the coil pattern and having a magnetic material; and
a magnetic flux controlling part coated on a surface of the insulating part and having a material having a saturation magnetic flux density higher than that of a magnetic material contained in the body region,
wherein a content of Fe contained in the magnetic flux controlling part is greater than a content of Fe contained in the body region.

US Pat. No. 10,115,517

COIL ARRANGEMENT FOR GENERATING A ROTATING ELECTROMAGNETIC FIELD AND POSITIONING SYSTEM FOR DETERMINING A POSITION OF AN IDENTIFICATION TRANSMITTER

Volkswagen Aktiengesellsc...

1. A coil arrangement for generating a rotating electromagnetic field, the coil arrangement comprising:at least three coils, each coil having at least one associated coil winding;
a ferromagnetic coil yoke that establishes a magnetic coupling between the at least three coils, and
at least three capacitors, a first capacitor of the at least three capacitors being connected in series to a first coil of the at least three coils, a second capacitor of the at least three capacitors being connected in series to a second coil of the at least three coils and a third capacitor of the at least three capacitors being connected in series to a third coil of the at least three coils,
wherein two or more coil windings, each having a number of windings that may be actuated jointly or separately, are arranged per coil of the at least three coils, and
wherein the coil arrangement further comprises at least three additional capacitors, a first additional capacitor of the at least three additional capacitors being connected in parallel to one of the two or more coil windings of the first coil of the at least three coils, a second additional capacitor of the at least three additional capacitors being connected in parallel to one of the two or more coil windings of the second coil of the at least three coils and a third additional capacitor of the at least three additional capacitors being connected in parallel to one of the two or more coil windings of the third coil of the at least three coils.

US Pat. No. 10,115,516

PLANAR INDUCTOR

THYSSENKRUPP ROTHE ERDE G...

1. A planar inductor for progressive surface layer hardening, the planar inductor comprising:a carrier;
an induction coil that is disposed at least partially in a first side of the carrier, wherein the induction coil is exposed and is configured as a conductor loop; and
at least two spacing elements that are arranged at a distance from each other, wherein the at least two spacing elements are coupled to the carrier and protrude beyond the carrier and beyond the conductor loop.

US Pat. No. 10,115,514

THREE-PHASE HIGH FREQUENCY TRANSFORMER

Seiden Mfg. Co., Ltd., (...

1. A three-phase high frequency transformer comprising:a three-legged ferrite core including three solid-cylindrical cores that are formed of ferrite and that are disposed at uniform intervals on a circumference, a ceiling plate formed of ferrite and located at one end of the solid-cylindrical cores, and a bottom plate formed of ferrite and located at the other end of the solid-cylindrical cores; and
three sets of coils having primary coils of a predetermined inner diameter formed by flat wires wound edgewise, and secondary coils that have an inner diameter that is the same as the inner diameter of the primary coils and are formed of flat wires wound edgewise, the flat wires forming the secondary coils having at least one of a width or a thickness different than those of the flat wires forming the primary coils, each of the flat wires of the primary coils and the secondary coils having a larger measurement in a width direction than in a thickness direction,
wherein the primary coils and the secondary coils are configured such that high frequency current flows therein,
wherein both the primary coils and the secondary coils are helical coils,
wherein the flat wires structuring one of the primary coils and secondary coils are inserted within the intervals of the flat wires structuring the other of the primary coils and the secondary coils, and the three sets of coils are structured such that inner peripheries of the primary coils and inner peripheries of the secondary coils coincide, and are disposed such that the respective solid-cylindrical cores are inserted in respective inner portions of the three sets of coils,
wherein both the primary coils and the secondary coils are Y-connected,
wherein each of the three primary coils of the three sets of coils is Y-connected by connecting one end of each of the three primary coils to a first connecting piece,
wherein each of the three secondary coils of the three sets of coils is Y-connected by connecting one end of each of the three secondary coils to a second connecting piece,
wherein the first connecting piece is a plate-like or planar conductor disposed at a side of one of the ceiling plate or the bottom plate along the upper or lower surface of one of the ceiling plate or the bottom plate, or a conductor disposed along the periphery surface of one of the ceiling plate or the bottom plate, and
wherein the second connecting piece is a plate-like or planar conductor disposed at a side of the other of the ceiling plate or the bottom plate along one of the upper or lower surface of the other of the ceiling plate and the bottom plate, or a conductor disposed along the periphery surface of the other of the ceiling plate and the bottom plate, or a plate-like conductor disposed on the same side as the first connecting piece.

US Pat. No. 10,115,512

SWITCHING ARRANGEMENT

TE Connectivity Germany G...

1. A switch assembly comprising:two contacts;
a switch including a contact bridge, a motor connected to the contact bridge, and an armature connected to the contact bridge, the switch having an open position in which the contacts are electrically separated from one another and a closed position in which the contacts are in electrical contact with each other through the contact bridge, the armature having a distal end positioned opposite the contact bridge that is displaced by the motor when the switch transitions from the open to the closed position;
a switch status detector positioned remotely and electrically isolated from the switch, the motor positioned between the contact bridge and the switch status detector; and
a switching device having a switch housing into which the switch and two contacts are positioned, a wall of the switch housing having a signal-permeable wall region, the distal end of the armature is positioned in the switch housing proximate to the signal-permeable wall region and the switch status detector is positioned outside the switch housing proximate to the signal-permeable wall region.

US Pat. No. 10,115,510

COIL FOR A SWITCHING DEVICE WITH A HIGH-FREQUENCY POWER

1. A coil apparatus including a coil former for use in forming an electrical coil comprising several windings, the coil former having a generally conical shape, the coil apparatus comprising:a first, relatively larger end;
a second, relatively smaller end;
a spiral track along the exterior of the coil former, the spiral track configured to accept an electrically conductive wire to thereby form said electrical coil comprising said several windings,
wherein the spiral track across the coil former proximate to the first end has a first diameter and wherein adjacent loops of the spiral track proximate to the first end have a first spacing between said adjacent loops;
wherein the spiral track across the coil former proximate to the second end has a second diameter and wherein adjacent loops of the spiral track proximate to the second end have a second spacing between said adjacent loops of the spiral track proximate to the second end;
wherein the first diameter is larger than the second diameter; and
wherein the first spacing is smaller than the second spacing;
wherein the coil former is adapted to remain within the electrical coil during operation of the electrical coil;
wherein the coil former partly fills an interior cavity of the electrical coil; and
wherein the coil former includes a first cylindrical part, a second cylindrical part, and a conical part disposed between the first cylindrical part and the second cylindrical part.

US Pat. No. 10,115,509

ULTRAFINE-CRYSTALLINE ALLOY RIBBON, FINE-CRYSTALLINE, SOFT-MAGNETIC ALLOY RIBBON, AND MAGNETIC DEVICE COMPRISING IT

HITACHI METALS, LTD., To...

1. An ultrafine-crystalline alloy ribbon having a structure, in which more than 0% and less than 30% by volume of ultrafine crystal grains having an average particle size of 30 nm or less are dispersed in an amorphous matrix; an ultrafine crystal grains-depleted region having a smaller number density of ultrafine crystal grains than in a center portion of said ribbon being formed in a region of 0.2 mm in width from each edge of the ribbon along a longitudinal direction; and the number density of ultrafine crystal grains having particle sizes of 3 nm or more being 300/?m2 or less in said ultrafine crystal grains-depleted region, and 500/?m2 or more in the center portion of said ribbon,wherein a distance between said edge and a position at which a number density of ultrafine crystal grains is 1/2 of a number density of ultrafine crystal grains in said center portion is 0.5 to 0.6 mm, the distance being 1 to 2.4% of the entire width of said ultrafine-crystalline alloy ribbon,
wherein the total width of both ultrafine crystal grains-depleted regions is 5% or less of the entire width of said ultrafine-crystalline alloy ribbon, and
wherein said ultrafine-crystalline alloy ribbon is made of a magnetic alloy having a composition represented by the general formula of Fe100-x-y-zAxByXz, wherein A is Cu and/or Au, X is at least one element selected from the group consisting of Si, S, C, P, Al, Ge, Ga and Be, part of Fe may be substituted by at least one element D selected from the group consisting of Ni, Mn, Co, V, Cr, Ti, Zr, Nb, Mo, Hf, Ta, and W, part of Fe may be substituted by at least one element selected from the group consisting of Re, Y, Zn, As, Ag, In, Sn, Sb, platinum-group elements, Bi, N, O, and rare earth elements, and x, y and z are numbers meeting the conditions of 0

US Pat. No. 10,115,508

MAGNETIC-DIELECTRIC COMPOSITE FOR HIGH-FREQUENCY ANTENNA SUBSTRATE AND MANUFACTURING METHOD THEREFOR

LG ELECTRONICS INC., Seo...

1. A magnetic-dielectric composite for a high-frequency antenna substrate, the magnetic-dielectric composite comprising:a porous insulating dielectric substrate comprising an upper surface, a lower surface, and a side surface and provided with a plurality of pores penetrating the upper surface and the lower surface; and
soft magnetic material nanowires provided in the pores,wherein the soft magnetic material nanowires are surrounded by the porous insulating dielectric substrate to be apart from each other.

US Pat. No. 10,115,507

LOW-B BARE EARTH MAGNET

Xiamen Tungsten Co., Ltd....

1. A low-B rare earth magnet containing a main phase of R2T14B and comprising the following raw material components:13.5 at %˜14.5 at % of R,
5.2 at %˜5.8 at % of B,
0.3 at %˜0.8 at % of Cu,
0.3 at %˜3 at % of Co, and
a balance being T and inevitable impurities, wherein:
the R is at least one rare earth element comprising Nd, and
the T is an element mainly comprising Fe the T further comprises X,
the X is at least three elements selected from Al, Si, Ga, Sn, Ge, Ag, Au, Bi, Mn, Cr, P or S, and
a total composition of the X is 0 at %-1.0 at %.

US Pat. No. 10,115,506

ND—FE—B SINTERED MAGNET AND METHODS FOR MANUFACTURING THE SAME

Beijing Zhong Ke San Huan...

1. A sintered Nd-Fe-B magnet consisting essentially of: rare earth element R, additive element T, iron Fe, and boron B, wherein said magnet comprises a rare-earth rich phase and a main phase of Nd2Fe14B crystalline structure, and wherein the numeric sum of maximum energy product (BH)max in MGOe and intrinsic coercivity Hcj in kOe is no less than 76, i.e., (BH)max(MGOe)+Hcj(kOe)?76,wherein said magnet comprises 28 to 32 wt % rare earth element R, 0-4wt % additive element T, 0.93-1.0 wt % boron B, with the balance of iron Fe, and impurities, wherein R is one or more elements selected from Y, Sc, and fifteen elements of lanthanide series,
wherein T is one or more elements selected from Ti, V, Cr, Mn, Co, Ni, Cu, Zn, Ga, Ge, Al, Zr, Nb, Mo, and Sn,
wherein the average crystalline grain size of said main phase is in a range from 5.0 ?m to 9.1 ?m, and
wherein oxygen content of said magnet is in a range from 1000 to 1625 ppm.

US Pat. No. 10,115,505

CHIP RESISTOR

E I DU PONT DE NEMOURS AN...

1. A method of manufacturing a chip resistor comprising the steps of:(a) applying a conductive paste on an insulating substrate, wherein the conductive paste comprises,
(i) 40 to 80 weight percent (wt. %) of a conductive powder;
(ii) 1 to 14 wt. % of a glass frit,
(iii) 0.01 to 3 wt. % of magnesium oxide (MgO),
(iv) 10 to 55 wt. % of an organic vehicle, and
(v) anorthite (CaAl2Si2O8),
wherein the wt. % is based on weight of the conductive paste;
(b) firing the applied conductive paste to form the front electrodes.

US Pat. No. 10,115,502

INSULATOR AND CONDUCTOR COVER FOR ELECTRICAL DISTRIBUTION SYSTEMS

Eco Electrical Systems, ...

1. A dielectric cover for an insulator and conductor supported by the insulator, the conductor being for carrying a voltage, the insulator being supported by a support structure in an electrical distribution system, the cover comprising:an insulator cover portion configured to cover at least a top portion of the insulator, the insulator cover portion comprising a knob and a ridge extending down from an inside ceiling of the insulator cover portion; and
an arm configured to cover a portion of the conductor extending from the insulator, the arm having a keyhole formed in a ceiling of the arm, the keyhole having a wide portion that fits over the knob in a first position, wherein the keyhole has a narrow portion that restricts vertical movement of the arm in a locked position,
the arm also having a resilient tab that snaps over the ridge in the locked position.

US Pat. No. 10,115,501

SUBSTRATE FOR SUPERCONDUCTING WIRE, METHOD FOR MANUFACTURING THE SAME, AND SUPERCONDUCTING WIRE

Toyo Kohan Co., Ltd., To...

1. A substrate for a superconducting wire, comprising a non-magnetic metal plate, a layer of copper or a copper alloy superposed on the non-magnetic metal plate, and an outermost protective layer consisting of a plated film of nickel or a nickel alloy formed on the layer of copper or the copper alloy, wherein the crystal orientation of the outermost protective layer exhibitsa c-axis orientation rate of 99% or higher,
a ?? of 6 degrees or less, and
a percentage of an area in which the crystal orientation is deviated by 6 degrees or more from the (001) [100] per unit area of 6% or less, wherein the crystal orientation deviation is observed via the electron back scatter diffraction (EBSD) method.

US Pat. No. 10,115,498

HYBRID CABLE, METHOD FOR ITS MANUFACTURE AND USE OF SUCH A HYBRID CABLE

LEONI Kabel Holding GmbH,...

1. An electric lead, comprising:at least three conductors, each having a line being surrounded by a conductor sheath;
two of said conductors are signal conductors;
a common partial lead sheath surrounding said signal conductors, said common partial lead sheath and said signal conductors forming a first partial lead;
another of said conductors is a power conductor forming a second partial lead;
a separating sleeve directly surrounding said first partial lead and said second partial lead, said separating sleeve being formed from a synthetic non-woven fabric or a plastic film; and
a common sheath surrounding said separating sleeve.

US Pat. No. 10,115,495

TRANSPARENT CONDUCTOR AND OPTICAL DISPLAY INCLUDING THE SAME

SAMSUNG SDI CO., LTD., Y...

1. A transparent conductor comprising:a base layer; and
a conductive layer on the base layer, the conductive layer comprising metal nanowires and a matrix, the matrix comprising a mixture of a first dye having a maximum absorption wavelength of about 450 nm to about 550 nm and a second dye having a maximum absorption wavelength of about 350 nm to 449 nm,
wherein the transparent conductor has a reflective a* value of about ?0.3 to about +0.3.

US Pat. No. 10,115,491

PRODUCTION OF MOLYBDENUM-99 USING ELECTRON BEAMS

Canadian Light Source Inc...

1. An apparatus for producing molybdenum-99 (99Mo) from a plurality of molybdenum-100 (100Mo) targets through a photo-nuclear reaction on the 100Mo targets, the apparatus comprising:a linear accelerator component capable of producing an electron beam;
a converter component capable of receiving the electron beam and producing therefrom a shower of bremsstrahlung photons;
a target irradiation component for receiving the shower of bremsstrahlung photons, the target irradiation component having a chamber for receiving, demountingly engaging, and positioning therein a target holder housing a plurality of 100Mo target discs;
a target holder transfer and recovery component for receiving, manipulating and conveying the target holder therein by remote control, said target holder transfer and recovery component engaged with and communicable with the target irradiation component; and
a cooling system sealingly engaged with the converter component for circulation of a coolant fluid therethrough.

US Pat. No. 10,115,489

EMERGENCY METHOD AND SYSTEM FOR IN-SITU DISPOSAL AND CONTAINMENT OF NUCLEAR MATERIAL AT NUCLEAR POWER FACILITY

Grand Abyss, LLC, Tulsa,...

1. A method for emergency in-situ subsurface isolation of nuclear material at a nuclear power or nuclear storage facility, the method comprising:conveying a mobile radioactive material during an emergency from a source of the radioactive material into a borehole in proximity to, and in flow communication with, the source of the mobile radioactive material and into a prepared first vertical-oriented gravity fracture, the borehole being at a depth suitable for safely isolating the mobile radioactive material, the prepared first vertical-oriented gravity fracture being in a surrounding rock formation located below and in communication with a bottom end of the borehole and available to receive the mobile radioactive material exiting the bottom end of the borehole during the emergency;
wherein the mobile radioactive material passes from the borehole into the prepared first vertical-oriented gravity fracture; and
wherein the mobile radioactive material is not in a containment vessel when entering the borehole;
prior to the conveying, creating the prepared first vertical-oriented gravity fracture by using a slurry containing a weighting material;
wherein the slurry is denser than the surrounding rock formation; and
wherein no mobile radioactive material is in or mixed with the slurry.

US Pat. No. 10,115,488

PASSIVE SAFETY EQUIPMENT FOR A NUCLEAR POWER PLANT

KOREA ATOMIC ENERGY RESEA...

20. A passive safety facility for a nuclear power plant, comprising:a cooling section formed to cool fluid discharged from a nuclear reactor coolant system along with fluid contained within an area between the nuclear reactor coolant system and a containment; and
a circulation inducing jet device configured to receive the fluid discharged from the nuclear reactor coolant system, and formed to jet the received fluid to the cooling section, at least part of which is open toward an inside of the containment to entrain the fluid contained within the area between the nuclear reactor coolant system and the containment by a pressure drop caused while jetting the received fluid so as to jet the entrained fluid along with the received fluid, wherein
the containment is formed to surround the steam generator which is configured to generate steam or the nuclear reactor coolant system which is configured to accommodate the steam generator,
the circulation inducing jet device comprises:
a fluid jetting section connected to the nuclear reactor coolant system to receive the fluid discharged from the nuclear reactor coolant system, and formed to jet the received fluid;
a fluid entraining section formed in an annular shape around the fluid jetting section to entrain the fluid contained within the area between the nuclear reactor coolant system and the containment;
a circulating fluid jetting section configured to surround the fluid jetting section with a portion having an inner diameter larger than that of the fluid jetting section to form the fluid entraining section, and supply the received fluid and the entrained fluid to the cooling section;
a turbine blade rotatably installed at an outlet of the jetting section to induce the jetting of the received fluid; and
a pump impeller connected to the turbine blade to rotate along with the turbine blade, and induce the entrainment of the fluid contained with the area between the nuclear reactor coolant system and the containment through the fluid entraining section.

US Pat. No. 10,115,487

SHUTDOWN SYSTEM FOR A NUCLEAR STEAM SUPPLY SYSTEM

SMR INVENTEC, LLC

1. A nuclear steam supply system with shutdown cooling system, the nuclear steam supply system comprising:a reactor vessel having an internal cavity;
a reactor core comprising nuclear fuel disposed within the internal cavity and operable to heat a primary coolant;
a steam generating vessel fluidly coupled to the reactor vessel;
a riser pipe positioned within the steam generating vessel and fluidly coupled to the reactor vessel;
a primary coolant loop formed within the reactor vessel and the steam generating vessel, the primary coolant loop being configured for circulating primary coolant through the reactor vessel and steam generating vessel; and
a primary coolant cooling system comprising:
an intake conduit having an inlet fluidly coupled to the primary coolant loop;
a pump fluidly coupled to the intake conduit, the pump configured and operable to extract and pressurize primary coolant from the primary coolant loop and discharge the pressurized primary coolant through an injection conduit;
a Venturi injection nozzle having an inlet fluidly coupled to the injection conduit and an outlet positioned within the riser pipe to inject pressurized primary coolant into the riser pipe from the pump; and
a heat exchanger configured and operable to cool the extracted primary coolant.

US Pat. No. 10,115,485

METHOD OF PLANNING AN EXAMINATION, METHOD OF POSITIONING AN EXAMINATION INSTRUMENT, TOMOSYNTHESIS SYSTEM AND COMPUTER PROGRAM PRODUCT

Siemens Healthcare GmbH, ...

1. A method for planning an examination of an examination object by a tomosynthesis machine, the method comprising the following steps:a) capturing raw data of the examination object, the raw data having been acquired from a plurality of defined acquisition angles;
b) reconstructing an auxiliary data set from the raw data;
c) calculating depth data from the auxiliary data set and calculating a number of projections from a perspective of a respectively defined projection center on a basis of the auxiliary data set or on a basis of the raw data, wherein each of the projections contains a number of image points and each of the image points is linked to the depth data associated therewith, and wherein perspectives of the projections are tilted relative to one another at least on a section of a circular path;
d) displaying the projections;
e) enabling at least one projection to be chosen;
f) marking a position of an examination region of the examination object in the at least one projection thus chosen; and
g) calculating a real three-dimensional position of the examination region using the marked position and the depth data thereof.

US Pat. No. 10,115,484

TRACKING MEDICATION INVENTORY USING ONE OR MORE LINKED PRESSURE SENSORS

1. A system for tracking an inventory of medication, the system comprising:one or more medication detecting devices, each of the medication detecting devices including:
a medication container for receiving a first amount of a medication;
a pressure sensor including a pressure sensing portion in sensory contact with the medication portion for measuring a pressure applied by the first amount of medication on the medication portion;
an embedded processor in electronic communication with the pressure sensing component and a sensor communication module;
one or more personal communication devices, the one or more personal communication devices including:
a display,
at least one computer readable storage medium,
a device communication component; and
a processor in communication with the display, the at least one computer readable storage medium, and the device communication module;
a remote database in communication with the one or more medication detecting devices and the one or more personal communication device via the sensor communication module of the one or more medication detecting devices and the device communication module of the personal communication device, the remote database including a processor and one or more computer readable storage mediums;
an interactive user interface displayed on the display of the personal communication device for receiving one or more medication parameters from a user corresponding to a change in pressure detected by the pressure sensing component of each of the one or more medication detecting devices and for displaying information related to the one or more medication detecting devices;
wherein when one of the one or more medication detecting devices detects a pressure change on the pressure sensor, the detected change of pressure is transmitted to the remote database, wherein the remote database processor analyzes the change in pressure from the one or more medication detecting devices and transmits an alert when the detected pressure change corresponds to the medication input parameters inputted by the user.

US Pat. No. 10,115,478

SEMICONDUCTOR MEMORY DEVICE

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device, comprising:a plurality of memory cell arrays each memory cell array including a first region, a second region, and a third region in the second region;
a repair controller suitable for storing a first repair address information, generating a first mode enable signal for accessing the third region by comparing the first repair address information with a row address during a first mode for a repair operation, and disabling the first mode enable signal in response to a refresh command regardless of a result of the comparing the first repair address information with the row address; and
a refresh operation controller suitable for generating a refresh address for performing a refresh operation in response to the refresh command, wherein a first refresh address corresponding to the first region and the second region is generated in response to the refresh command, and a second refresh address corresponding to the third region is generated in response to the first refresh address.

US Pat. No. 10,115,476

ADVANCED PROGRAMMING VERIFICATION SCHEMES FOR MEMORY CELLS

Apple Inc., Cupertino, C...

1. An apparatus, comprising:a plurality of blocks, wherein each block of the plurality of blocks includes a plurality of data storage cells;
circuitry configured to:
measure respective durations of one or more write commands associated with storing data in one or more data storage cells of the plurality of data storage cells in a particular block of the plurality of blocks;
compare the respective durations of the one or more write commands to a predefined duration range; and
identify the particular block as bad in response to a determination that the respective durations of the one or more write commands deviate from the predefined duration range.

US Pat. No. 10,115,475

COMPENSATION CIRCUIT FOR COMPENSATING FOR AN INPUT CHARGE IN A SAMPLE AND HOLD CIRCUIT

NXP USA, Inc., Austin, T...

1. A compensation circuit for compensating for an input charge at a first input of a sample and hold circuit, the input charge for charging a first input capacitor of the sample and hold circuit during sampling an analogue input voltage signal, the compensation circuit comprising:a first buffer having a first buffer input for electrically coupling to the first input of the sample and hold circuit, and a first buffer output;
a first compensation capacitor comprising
a first compensation terminal switchable between the first buffer input and the first buffer output, and
a second compensation terminal switchable between the first buffer output and a reference terminal; and
a control circuit configured to
switch the first compensation terminal to the first buffer output and the second compensation terminal to the reference terminal when the sample and hold circuit is configured for sampling the analogue input voltage signal, for storing a compensation charge into the first compensation capacitor, wherein the compensation charge is substantially equal to the input charge, and
switch the first compensation terminal to the first buffer input and the second compensation terminal to the first buffer output when the sample and hold circuit is configured for holding the analogue input voltage signal, for discharging the first compensation capacitor of the stored compensation charge into the first input of the sample and hold circuit.

US Pat. No. 10,115,474

ELECTRONIC DEVICE WITH A FUSE READ MECHANISM

Micron Technology, Inc., ...

1. A method of operating an electronic device, comprising:precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information,
wherein precharging the fuse read node includes precharging the fuse read node with an intermediate precharging device configured to provide the intermediate voltage instead of a transistor configured to connect the fuse read node to a source providing the input voltage;
connecting the fuse cell to the fuse read node for reading the information; and
determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.

US Pat. No. 10,115,473

METHOD, SYSTEM AND DEVICE FOR CORRELATED ELECTRON SWITCH (CES) DEVICE OPERATION

ARM Ltd., Cambridge (GB)...

1. A method comprising:applying a first programming signal generated by a write circuit to terminals of a correlated electron switch (CES) element to provide a first current in the CES element sufficient to place the CES element in a high impedance or insulative state; and
applying a second programming signal from the write circuit to the terminals of the CES element to provide a voltage across terminals of the CES element sufficient to place the CES element in a low impedance or conductive state, the second programming signal further providing a second current in the CES element having a magnitude greater than a magnitude of the first current,
wherein the magnitude of the second current is sufficiently high to prevent a subsequent transition of the CES element to the high impedance or insulative state responsive to a subsequently applied programming signal generated by the write circuit.

US Pat. No. 10,115,472

REDUCING READ DISTURB EFFECT ON PARTIALLY PROGRAMMED BLOCKS OF NON-VOLATILE MEMORY

International Business Ma...

1. A method in a data storage system including a non-volatile memory array controlled by a controller, the method comprising:in response to receipt of write data to be written to the non-volatile memory array, the controller determining whether a read count of an unfinalized candidate block of storage within the non-volatile memory array satisfies a read count threshold applicable to the unfinalized candidate block; and
in response to determining that the read count of the unfinalized candidate block satisfies the read count threshold, the controller finalizing programming of the unfinalized candidate block and programming an alternative block with the write data, wherein programming the alternative block includes programming a physical page in the alternative block with a data page forming part of a page stripe spanning multiple blocks.

US Pat. No. 10,115,471

STORAGE SYSTEM AND METHOD FOR HANDLING OVERHEATING OF THE STORAGE SYSTEM

Western Digital Technolog...

1. A method for handling overheating of a storage system, the method comprising:performing the following in a storage system comprising a memory, a temperature sensor, a power supply, and a controller, wherein the controller comprises transistors:
executing first computer-readable program code by the controller to:
determine whether a temperature sensed by the temperature sensor is above a first threshold temperature by comparing the temperature sensed by the temperature sensor to the first threshold temperature; and
in response to determining that the temperature sensed by the temperature sensor is above the first threshold temperature, perform a thermal throttling operation to reduce a number of memory operations performed in the memory; and
executing second computer-readable program code by the controller to:
determine whether the thermal throttling operation was successful in lowering the temperature below the first threshold temperature by comparing a temperature sensed by the temperature sensor after performing the thermal throttling operation to the first threshold temperature; and
in response to determining that the thermal throttling operation was unsuccessful in lowering the temperature below the first threshold temperature, lower a voltage supplied by the power supply to the controller, wherein lowering the voltage supplied to the controller reduces temperature by reducing leakage current of the transistors in the controller.

US Pat. No. 10,115,469

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A nonvolatile memory, comprising:a bit line coupled to a first diffusion layer and a switch MOS transistor;
a source line coupled to a second diffusion layer;
a memory gate line coupled to a memory gate electrode;
a control gate line coupled to a control gate electrode;
a first driver which drives the control gate line;
a second driver which drives the memory gate line;
a third driver which drives the switch MOS transistor; and
a fourth driver which drives the source line;
wherein the second and the fourth drivers include MOS transistors whose gate withstand voltages are higher than those of MOS transistors included in the first and the third drivers.

US Pat. No. 10,115,467

ONE TIME ACCESSIBLE (OTA) NON-VOLATILE MEMORY

Jonker LLC, Zephyr Cove,...

1. A method of operating a floating gate based non-volatile memory cell device that operates to store a logic state based on a value of a charge physically present on the floating gate in a memory cell, such that a first amount of charge represents a first logical value, and a second amount of charge represents a second logical value, the improvement comprising:a hybrid read operation that when effectuated:
i. reads the stored memory cell logic state during a first phase;
and
ii. erases the stored memory cell logic state during an immediately subsequent second phase;
iii. senses said stored memory cell logical state by at least one of: 1) integrating a total charge flowing through the device during at least a portion of time of said hybrid read operation; and/or 2) detecting a change in current as a function of at least a portion of time of said hybrid read operation for said memory device;
wherein a threshold voltage of the floating gate based memory cell device is caused to increase during an entirety of said hybrid read operation;
further wherein a stored logic state of the non-volatile memory cell device can be read at most once before it is erased.

US Pat. No. 10,115,465

FUNCTIONAL DATA PROGRAMMING IN A NON-VOLATILE MEMORY

Micron Technology, Inc., ...

1. A method of operating a memory, comprising:receiving a plurality of digits of data;
determining a value of the plurality of digits of data;
selecting a function to represent the value of the plurality of digits of data, wherein the selected function is a non-binary mathematical function of a cell number of each memory cell within a grouping of memory cells;
determining a desired threshold voltage of each memory cell of the grouping of memory cells in response to the selected function, wherein the desired threshold voltage of a particular memory cell of the grouping of memory cells corresponds to the value of the selected function for the cell number of the particular memory cell; and
programming the particular memory cell to its desired threshold voltage.

US Pat. No. 10,115,464

ELECTRIC FIELD TO REDUCE SELECT GATE THRESHOLD VOLTAGE SHIFT

SanDisk Technologies LLC,...

1. An apparatus, comprising:a NAND string comprising non-volatile memory cells;
a string select line;
a plurality of word lines connected to control gates of the non-volatile memory cells; and
a control circuit in communication with the NAND string, the string select line, and the plurality of word lines, the control circuit configured to:
apply a read pass voltage to a word line adjacent to the string select line;
decrease the read pass voltage on the adjacent word line to a steady state voltage after a selected memory cell on the NAND string is sensed;
increase a voltage on the string select line after the voltage on the adjacent word line is decreased to the steady state voltage; and
float the string select line and the adjacent word line after the voltage on the string select line is increased.

US Pat. No. 10,115,463

VERIFICATION OF A RAM-BASED TCAM

XILINX, INC., San Jose, ...

1. An integrated circuit (IC), comprising:a memory including at least one random access memory (RAM); and
a verification circuit, coupled to the memory, including a W-bit address bus and an N-bit data bus coupled to each of the at least one RAM, a counter coupled to the address bus and operable to generate a W-bit address signal, a register coupled to the address bus and operable to store a W-bit address value, a multiplexer coupled to the data bus and operable to output a selected bit of the data bus, and circuitry configured to decode or check bits stored in the memory based on output of the register and output of the multiplexer.

US Pat. No. 10,115,462

ADDRESS DECODER FOR A NON-VOLATILE MEMORY ARRAY USING MOS SELECTION TRANSISTORS

STMICROELECTRONICS S.R.L....

1. An address decoder for a non-volatile memory device comprising:a row-decoder circuit configured to select and bias word lines of a plurality of word lines of a memory array with row-driving signals (VWL), the-memory array comprising memory cells arranged using the plurality of word lines and a plurality of bit lines, wherein
each memory cell comprises a memory element and an access element, wherein each access element includes a MOS transistor to enable access to the memory element,
respective source terminals of the MOS transistors of a same word line of the plurality of word lines are connected to respective source lines of a plurality of source lines of the memory array, and
a total number of the plurality of source lines of the memory array is greater than or equal to a total number of the plurality of word lines of the memory array;
a column-decoder circuit configured to select and bias the bit lines of the plurality of bit lines of the memory array with column-driving signals (VBL); and
a source-decoder circuit configured to generate source-driving signals (VSL) for biasing the plurality of source lines of the memory array based on a logic combination of row-driving signals (VWL) of associated subsets of the plurality of word lines.

US Pat. No. 10,115,460

PHASE-CHANGE MEMORY DEVICE WITH DRIVE CIRCUIT

STMICROELECTRONICS S.R.L....

1. A memory device comprising:an array of memory cells, each memory cell including a phase-change material;
a word line coupled to memory cells of the array;
a control circuit configured to be controlled so as to operate in a read mode or in a write mode;
a first pull-up MOSFET and a second pull-up MOSFET having channels of a first type, the first and second pull-up MOSFETs being connected in series between a first power-supply node configured to be set at a first supply voltage and the word line, the second pull-up MOSFET being arranged between the first pull-up MOSFET and the word line;
a first pull-down MOSFET and a second pull-down MOSFET having channels of a second type, the first and second pull-down MOSFETs being connected in series between the word line and a second power-supply node configured to be set at a reference potential, the second pull-down MOSFET being arranged between the first pull-down MOSFET and the word line; and
a biasing MOSFET coupled between the word line and a third power-supply node configured to be set at a second supply voltage that is higher than the first supply voltage, wherein the first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than a breakdown voltage of the biasing MOSFET, wherein the control circuit is coupled to the first and the second pull-up MOSFETs, the first pull-down MOSFET, and the biasing MOSFET.

US Pat. No. 10,115,459

MULTIPLE LINER INTERCONNECTS FOR THREE DIMENSIONAL MEMORY DEVICES AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A structure comprising an electrically conductive structure embedded within at least one dielectric material layer, wherein the electrically conductive structure comprises:a metal portion consisting essentially of an elemental metal or an intermetallic alloy of at least two elemental metals;
a first metallic liner comprising a first metallic material and contacting a bottom surface of the metal portion and at least lower portions of sidewalls of the metal portion; and
a second metallic liner comprising a second metallic material and contacting a top surface of the metal portion,wherein:the first metallic material and the second metallic material differ in composition; and
the first metallic liner and the second metallic liner contact an entirety of all surfaces of the metal portion; andwherein the structure comprises at least one feature selected from:a first feature that the metal portion comprises copper and the second metallic liner consists essentially of aluminum;
a second feature that the metal portion comprises copper and the second metallic liner comprises a material selected from cobalt, cobalt-tungsten and cobalt-tungsten-phosphorus;
a third feature that the first metallic liner comprises a material selected from a conductive metallic nitride and an elemental transition metal;
a fourth feature that the metal portion comprises copper, the first metallic liner comprises titanium and the second metallic liner comprises aluminum; or
the fifth feature that the at least one dielectric material layer comprises an air-gap dielectric layer including at least one cavity filled with vacuum or a gas phase material.

US Pat. No. 10,115,457

THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION BY SENSING COMMON SOURCE LINE CURRENTS

Micron Technology, Inc., ...

1. A method for threshold voltage distribution determination, comprising:applying a first sensing voltage to a selected access line to which a group of memory cells is coupled;
determining a first current on a source line to which the group of memory cells is commonly coupled, the first current corresponding to a first quantity of memory cells of the group that conduct in response to the applied first sensing voltage;
applying a second sensing voltage to the selected access line;
determining a second current on the source line, the second current corresponding to a second quantity of cells of the group that conduct in response to the applied second sensing voltage; and
determining at least a portion of a threshold voltage distribution corresponding to the group of memory cells based, at least in part, on a difference between the first current and the second current.

US Pat. No. 10,115,455

SEMICONDUCTOR DEVICES, CIRCUITS AND METHODS FOR READ AND/OR WRITE ASSIST OF AN SRAM CIRCUIT PORTION BASED ON VOLTAGE DETECTION AND/OR TEMPERATURE DETECTION CIRCUITS

1. A method of operating a semiconductor device that is powered by a first power supply potential, comprising:determining in which of a plurality of voltage windows the first power supply potential is located;
changing at least one voltage window signal when the first power supply potential moves from one voltage window into another of the voltage windows;
detecting a change in the at least one voltage window signal; and
generating at least one read assist signal having a predetermined logic level in response to the at least one voltage window signal; and
altering a read operation to a static random access memory (SRAM) cell in response to the at least one read assist signal having the predetermined logic level.

US Pat. No. 10,115,454

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a memory array which includes a plurality of memory cells arranged in a matrix;
word lines which are provided and correspond respectively to rows of the memory array;
word line drivers which are coupled to ends of the word lines, and activate the word lines by coupling the one ends of the word lines to a first power source, when a corresponding row is selected; and
assist drivers which are coupled to other ends of the word lines, and couple the other ends of the word lines to the first power source in accordance with a voltage of the other ends of the word lines,
wherein each of the assist drivers receives a control signal pulse, and
wherein the control signal pulse is transmitted to the assist drivers through a signal wiring.

US Pat. No. 10,115,453

INTEGRATED CIRCUITS WITH SRAM DEVICES HAVING READ ASSIST CIRCUITS AND METHODS FOR OPERATING SUCH CIRCUITS

Globalfoundries Singapore...

1. A read assist circuit for use in a semiconductor memory device, the read assist circuit comprising:a first drive device for driving a wordline of the semiconductor memory device to a wordline driving voltage, wherein the first drive device operates at a first current; and
a second drive device for maintaining the wordline of the semiconductor memory device at the wordline driving voltage, wherein the second drive device operates at a second current, and wherein the second current is lower than the first current, wherein the read assist circuit is configured to activate the first drive device for a pulse width, and wherein the read assist circuit is configured to maintain the second drive device when the first drive device is not activated.

US Pat. No. 10,115,452

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a substrate;
a circuit having a transistor formed on the substrate;
an oscillation circuit generating a frequency signal;
a substrate voltage generation circuit generating a substrate voltage in accordance with the frequency signal from the oscillation circuit; and
a control circuit varying a frequency of the frequency signal from the oscillation circuit during a stand-by period of the circuit,
wherein the stand-by period of the circuit includes a stand-by transition period in which transition from an active state to a stand-by state of the circuit is made and a stand-by stable period in which the stand-by state is maintained,
wherein the control circuit sets a frequency of the frequency signal from the oscillation circuit differently between the stand-by transition period and the stand-by stable period, and
wherein the control circuit sets a frequency of the frequency signal from the oscillation circuit during the stand-by transition period to be higher than a frequency of the frequency signal from the oscillation circuit during the stand-by stable period.

US Pat. No. 10,115,451

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. A method of operating an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising:a plurality of said semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising:
a floating body region configured to be charged to a level indicative of a state of the memory cell;
a first region in electrical contact with said floating body region, located at a surface of said floating body region;
a second region in electrical contact with said floating body region, located at a surface of said floating body region, spaced apart from said first region;
a gate positioned between said first region and said second region; and
a third region in electrical contact with said floating body region, located below said floating body region;
said method comprising:
selecting said third region of at least one of said semiconductor memory cells in at least one of said at least two memory sub-arrays; and
operating said at least one of said memory sub-arrays independently of operation of a remainder of said at least two memory sub-arrays not selected.

US Pat. No. 10,115,450

CASCODE COMPLIMENTARY DUAL LEVEL SHIFTER

International Business Ma...

1. A level shifter comprising:a first circuit section,
a second circuit section in parallel with the first circuit section, and
an inverter between the first circuit section and the second circuit section, wherein the first circuit section comprises:
a first p-channel field effect transistor (FET), a second p-channel FET, a first n-channel FET, and a second n-channel FET connected to each other in series;
a third n-channel FET, a drain of the third n-channel FET being connected to a first connection point at which a drain of the first p-channel FET and a source of the second p-channel FET are connected to each other, a source of the third n-channel FET being connected to a gate of the second p-channel FET;
a third p-channel FET, a gate of the third p-channel FET being connected to a second connection point at which the source of the third n-channel FET and the gate of the second p-channel FET are connected to each other, a drain of the third p-channel FET being connected to a third connection point at which a drain of the second p-channel FET and a drain of the first n-channel FET are connected to each other;
a fourth p-channel FET, a source of the fourth p-channel FET being connected to a gate of the first n-channel FET, a drain of the fourth p-channel FET being connected to a fourth connection point at which a source of the first n-channel FET and a drain of the second n-channel FET are connected to each other; and
a first condenser, ends of the first condenser being respectively connected to a fifth connection point at which the drain of the first p-channel FET and the source of the second p-channel FET are connected to each other, and a sixth connection point at which the source of the first n-channel FET and the drain of the second n-channel FET are connected to each other;
wherein the second circuit section comprises:
a fifth p-channel FET, a sixth p-channel FET, a fourth n-channel FET, and a fifth n-channel FET connected in series, a gate of the fifth p-channel FET being connected to the drain of the first p-channel FET, a drain of the fifth p-channel FET being connected to a gate of the first p-channel FET, a gate of the sixth p-channel FET being connected to the gate of the second p-channel FET, a gate of the fourth n-channel FET being connected to the gate of the first n-channel FET;
a sixth n-channel FET, a drain of the sixth n-channel FET being connected to a seventh connection point at which the drain of the fifth p-channel FET and a source of the sixth p-channel FET are connected to each other, a source of the sixth n-channel FET being connected to the gate of the sixth p-channel FET;
a seventh p-channel FET, a gate of the seventh p-channel FET being connected to an eighth connection point at which the source of the sixth n-channel FET and the gate of the sixth p-channel FET are connected to each other, a drain of the seventh p-channel FET being connected to a ninth connection point at which a drain of the sixth p-channel FET and a drain of the fourth n-channel FET are connected to each other;
an eighth p-channel FET, a source of the eighth p-channel FET being connected to the gate of the fourth n-channel FET, a drain of the eighth p-channel FET being connected to a tenth connection point at which a source of the fourth n-channel FET and a drain of the fifth n-channel FET are connected to each other; and
a second condenser, ends of the second condenser being respectively connected to an eleventh connection point at which the drain of the fifth p-channel FET and the source of the sixth p-channel FET are connected to each other, and a twelfth connection point at which the source of the fourth n-channel FET and the drain of the fifth n-channel FET are connected to each other;
an inverter input terminal of the inverter is connected to a gate of the fourth p-channel FET and a gate of the second n-channel FET;
an inverter output terminal of the inverter is connected to a gate of the eighth p-channel FET and a gate of the fifth n-channel FET;
the seventh connection point constitutes a first output terminal;
the tenth connection point constitutes a second output terminal;
a first voltage is applied to a source of the first p-channel FET and a source of the fifth p-channel FET; and
a second voltage being lower than the first voltage is applied to a source of the second n-channel FET and a source of the fifth n-channel FET, the first voltage or a third voltage being lower than the first voltage and higher than the second voltage is outputted from the first output terminal, the second voltage or a fourth voltage being lower than the first voltage and higher than the third voltage is outputted from the second output terminal.

US Pat. No. 10,115,447

LOGIC GATE MODULE FOR PERFORMING LOGIC FUNCTIONS COMPRISING A MRAM CELL AND METHOD FOR OPERATING THE SAME

CROCUS TECHNOLOGY SA, Gr...

1. A logic gate module for performing logic functions comprising a MRAM cell including a magnetic tunnel junction comprising a sense layer having a sense magnetization, a storage layer having a storage magnetization, and a spacer layer between the sense and the storage layers, the MRAM cell having a junction resistance determined by the degree of alignment between the sense magnetization and the storage magnetization;wherein, during a programming operation, the storage magnetization is switchable between m directions to store data corresponding to one of m logic states, with m?4; and
wherein, during a user input operation, the sense magnetization is switchable between said m directions in accordance with a user input, such that the MRAM cell is usable as a n-bit cell with n?2;
the logic gate module further comprising a comparator for comparing the junction resistance with a reference value and outputting a digital signal indicating a difference between the junction resistance and the reference value, wherein by providing said digital signal based on a selected reference value and a programmed direction of the storage magnetization and in response to the user input orientation, the logic gate module is able to perform a logic function of said user input, said logic function being one of said logic functions and being associated to the selected reference value and the programmed direction;
the reference value being selectable to have: a value substantially equal to a maximum value corresponding to the sense and storage magnetizations being antiparallel, such that the logic gate module is configured to perform the logic functions “OR”, NAND”, “A+notB” or “notA+B”; a value substantially equal to a minimum value corresponding to the sense and storage magnetizations being parallel, such that the logic gate module can perform the logic functions “NOR” or “AND”, “A.notB” or “notA.B”; and a value substantially equal to an intermediate value corresponding to a value between the maximum value and the minimum value, such that the logic gate module is configured to perform the logic function “XOR”.

US Pat. No. 10,115,445

MAGNETIC MEMORY DEVICE THAT IS PROTECTED AGAINST READING USING AN EXTERNAL MAGNETIC FIELD AND METHOD FOR OPERATING SUCH MAGNETIC MEMORY DEVICE

CROCUS TECHNOLOGY SA, Gr...

1. A magnetic memory device configured to be used with a self-referenced read operation, the memory comprising a plurality of magnetic units, each unit including:a first magnetic tunnel junction comprising a first storage layer having a first storage magnetization and a first sense magnetic layer having a first sense magnetization;
a second magnetic tunnel junction comprising a second storage layer having a second storage magnetization and a second sense magnetic layer having a second sense magnetization;
a current line and a strap electrically connecting the first and second magnetic tunnel junctions in series;
a field line comprising:
a first line portion for passing, during the read operation, a first current portion of a field current, the first current portion generating a first magnetic field adapted for varying the first sense magnetization and a first resistance of the first magnetic tunnel junction; and
a second line portion for passing a second current portion of the field current, the second current portion generating a second magnetic field adapted for varying the second sense magnetization direction and a second resistance of the second magnetic tunnel junction, the second current portion having a polarity opposed to the one of the first current portion;
each magnetic unit being provided with a data state such that the first storage magnetization is aligned in a direction opposed to the one of the second storage magnetization;
wherein the first magnetic field is adapted for varying the first sense magnetization in a first direction and the second magnetic field is adapted for varying the second sense magnetization in a second direction opposed to the first direction, such that, in each magnetic unit either, the first storage magnetization is parallel to the first sense magnetization and the second sense magnetization, or the first storage magnetization is antiparallel to the first sense magnetization and to the second sense magnetization;
the current line being configured for providing an output signal that varies in response to the sum of the resistances of the first and second magnetic tunnel junctions of each of said plurality of magnetic units, such that said data state can be determined only when the input signal is provided to the field line.

US Pat. No. 10,115,444

DATA BIT INVERSION TRACKING IN CACHE MEMORY TO REDUCE DATA BITS WRITTEN FOR WRITE OPERATIONS

QUALCOMM Incorporated, S...

1. A cache memory, comprising:a cache array comprising one or more cache entries, each comprising a cache data field and a bit change track field; and
a cache controller configured to write data in the one or more cache entries of the cache array;
the cache controller configured to:
receive a write request comprising a memory address and a write data word;
generate a bit change track word in the bit change track field in a cache entry among the one or more cache entries in the cache array corresponding to the memory address of the write request, the bit change track word indicating a bit inversion state based on bit inversions determined by a comparison between the write data word and a current cache data word stored in the cache data field in the cache entry;
determine if the write data word is to be stored in an inverted form based on the bit inversion state; and
responsive to determining that the write data word is to be stored in the inverted form, cause the write data word to be stored in association with the memory address of the write request in the inverted form.

US Pat. No. 10,115,443

TECHNIQUES TO IMPROVE SWITCHING PROBABILITY AND SWITCHING SPEED IN SOT DEVICES

National University of Si...

1. A method for switching a magnetization direction of a ferromagnet (FM) layer of a spin orbit torque (SOT) device, comprising:applying an in-plane assist field; and
applying one or more in-plane input current pulses each having a tuned pulse width or a pulse width selected to be within a range of tuned pulse widths, and an intensity, to switch the magnetization direction of the FM layer,
wherein the tuned pulse width or range of tuned pulse widths are selected to avoid a specific pulse width that causes switch-back of the magnetization direction of the FM layer of the SOT device.

US Pat. No. 10,115,442

DEMAND-BASED PROVISIONING OF VOLATILE MEMORY FOR USE AS NON-VOLATILE MEMORY

Microsoft Technology Lice...

1. A computing device comprising:one or more volatile memories logically partitioned into a plurality of pages;
a firmware of the computing device;
one or more processors that cause the computing device to at least:
provide, by the firmware, information indicative of a first subset of the plurality of pages of volatile memory, the first subset comprising one or more pages of volatile memory identified by the firmware as non-volatile storage;
receive, by the firmware, an indication of demand for additional non-volatile storage on the computing device;
update, by the firmware and based at least in part on the received indication, data indicative of pages of memory identified as non-volatile storage to include a second subset of the plurality of pages in addition to the first subset of the plurality of pages; and
provide, by the firmware, information indicative of updates to the data indicative of pages of memory identified as non-volatile storage.

US Pat. No. 10,115,440

WORD LINE CONTACT REGIONS FOR THREE-DIMENSIONAL NON-VOLATILE MEMORY

SANDISK TECHNOLOGIES LLC,...

1. An apparatus comprising:a stack of word line layers comprising word lines for a three-dimensional non-volatile memory array, the stack of word line layers comprising a plurality of tiers;
a plurality of word line switch transistors for transferring word line bias voltages to the word lines;
a plurality of word line contact regions for coupling the word line switch transistors to the word lines, a word line contact region comprising a stepped structure for a tier of the word line layers, wherein a level region separates a word line contact region for a first tier from a word line contact region for a second tier; and
a plurality of connectors coupling the word line switch transistors to the word lines, the connectors comprising vertical conductors, wherein connectors for a single word line contact region comprise vertical conductors disposed within the single word line contact region, at a first side of the single word line contact region, and at a second side of the single word line contact region.

US Pat. No. 10,115,439

ON-DIE TERMINATION OF ADDRESS AND COMMAND SIGNALS

RAMBUS INC., Sunnyvale, ...

1. A memory controller to control the operation of a memory device, the memory controller comprising:a command/address (CA) circuit to drive CA signals onto a CA bus; and
a driver to drive a chip select signal onto the CA bus;
the memory controller to store register values, in the memory device, that represent one or more impedance values of on-die termination (ODT) impedances to apply to respective inputs of the memory device that receive the CA signals, and wherein the register values include one or more register values to selectively enable application of a chip select ODT impedance to an input of the memory device that receives the chip select signal.

US Pat. No. 10,115,438

SENSE AMPLIFIER CONSTRUCTIONS

Micron Technology, Inc., ...

1. A sense amplifier construction comprising:a first n-type transistor and a second n-type transistor extending elevationally outward relative to be vertically offset from the first n-type transistor, the first transistor comprising a first semiconductor material pillar extending along a first gate and comprising a first channel region elevationally between first transistor top and bottom n-type source/drain regions, the second transistor comprising a second semiconductor material pillar extending along a second gate and comprising a second channel region elevationally between second transistor top and bottom n-type source/drain regions;
a third p-type transistor and a fourth p-type transistor extending elevationally outward relative to the third p-type transistor, the third transistor comprising a third semiconductor material pillar extending along a third gate and comprising a third channel region elevationally between third transistor top and bottom p-type source/drain regions, the fourth transistor comprising a fourth semiconductor material pillar extending along a fourth gate and comprising a fourth channel region elevationally between fourth transistor top and bottom p-type source/drain regions;
a lower voltage activation line electrically coupled to each of the top source/drain region of the first transistor and the bottom source/drain region of the second transistor; and
a higher voltage activation line electrically coupled to each of the top source/drain region of the third transistor and the bottom source/drain region of the fourth transistor.

US Pat. No. 10,115,437

STORAGE SYSTEM AND METHOD FOR DIE-BASED DATA RETENTION RECYCLING

Western Digital Technolog...

1. A storage system comprising:a controller; and
a plurality of memory dies in communication with the controller, wherein each of the memory dies comprises its own temperature sensor, wherein at least one of the memory dies is characterized by a relatively lower endurance than at least one other of the memory dies, and wherein the at least one of the memory dies with the relatively lower endurance is positioned farther away from the controller than the at least one other of the memory dies.

US Pat. No. 10,115,436

FILTER MEDIA AND FILTER PRODUCTS FOR ELECTRONIC ENCLOSURES

Seagate Technology LLC, ...

1. An electronic device enclosure comprising:a base and a cover,
at least one data storage disk within the enclosure,
one or more heads for reading or writing data onto the disk, and
a filter in fluid communication with an interior of the enclosure, the filter comprising filter media that includes activated carbon and graphene, wherein the graphene is in the form of graphene particles having a dimension in the range of 2 to 20 microns.

US Pat. No. 10,115,435

METHODS AND SYSTEMS FOR PRIORITIZING PLAYBACK OF MEDIA CONTENT IN A PLAYBACK QUEUE

SPOTIFY AB, Stockholm (S...

1. A method, comprising:at a client device having one or more processors and memory storing instructions for execution by the one or more processors:
playing a first media item from a playback queue, the playback queue comprising a first portion having a plurality of media items with respective positions that define an order in which the media items are to be played;
while playing the first media item:
detecting a first user input indicating selection of a second media item;
in response to the first user input, assigning the second media item to a second portion of the playback queue, comprising adding the second media item to the second portion from a list of search query results, wherein the second portion has playback priority over the first portion; and
detecting a second user input indicating selection of a third media item to be played from the first portion of the playback queue, wherein the third media item is a media item from the plurality of media items of the first portion and the first portion includes one or more additional media items that precede the third media item with respect to the order in which the media items of the first portion are to be played;
in response to the second user input:
ceasing playback of the first media item;
playing the third media item;
removing the third media item from the first portion of the playback queue; and
removing the one or more additional media items that precede the third media item from the first portion of the playback queue while retaining other media items in the first portion that are after the third media item with respect to the order in which the media items of the first portion are to be played; and
after playing the third media item, playing the second media item before playing the other media items in the first portion that are after the third media item with respect to the order in which the media items of the first portion are to be played.

US Pat. No. 10,115,434

METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR EDITING MEDIA CONTENT

NOKIA TECHNOLOGIES OY, E...

1. A method comprising:facilitating receipt of a first media content comprising a first audio track and a first video track, and a second media content comprising a second audio track;
determining a first plurality of audio sections associated with the first audio track and a second plurality of audio sections associated with the second audio track;
performing section mapping between the first plurality of audio sections and the second plurality of audio sections to determine a plurality of mapping audio sections in the second audio track corresponding to the first plurality of audio sections;
determining, in a first audio section of the first plurality of audio sections, a relative position of at least one first video transition with respect to the first audio section;
creating a corresponding at least one second video transition associated with the at least one first video transition with respect to a mapping audio section of the plurality of mapping audio sections, the mapping audio section corresponding to the determined first audio section of the first plurality of audio sections, the corresponding at least one second video transition being created at a same relative position with respect to the mapping audio section as the relative position of the at least one first video transition with respect to the first audio section; and
modifying the first video track based on the relative position of the corresponding at least one second video transition in the mapping audio section to generate a second video track corresponding to the second audio track.

US Pat. No. 10,115,433

SECTION IDENTIFICATION IN VIDEO CONTENT

A9.COM, INC., Palo Alto,...

14. A system, comprising:at least one processor; and
memory storing instructions that, when executed by the at least one processor, cause the system to:
obtain video content from a content source;
obtain content interaction information associated with the video content and corresponding to data reflecting user actions with the video content, the content interaction information comprising historical activity of a plurality of users;
use the content interaction information to identify a portion of the video content;
analyze the portion of the video content to generate an indexed sequence of the portion of the video content; and
modify the video content based at least in part on the indexed sequence to generate modified video content.

US Pat. No. 10,115,432

METHOD AND APPARATUS FOR CONSTRUCTING SENSORY EFFECT MEDIA DATA FILE, METHOD AND APPARATUS FOR PLAYING SENSORY EFFECT MEDIA DATA FILE, AND STRUCTURE OF THE SENSORY EFFECT MEDIA DATA FILE

Myongji University Indust...

1. A method for constructing a sensory effect media data file, the method comprising:receiving a media object including media data;
scanning the media object to extract information representing a property of the media data;
constructing first composition information representing the extracted information representing a property of the media data;
inserting the first composition information into a composition information container field;
receiving a sensory effect object including sensory effect data;
scanning the sensory effect object to extract information representing a property of the sensory effect data;
constructing second composition information representing the extracted information representing a property of the sensory effect data;
inserting second composition information into the composition information container field;
extracting a sample of the media data from the media object;
inserting the extracted sample of the media data into a media data field, the extracted sample representing data associated with a timestamp; and
extracting a sample of the sensory effect data from the sensory effect object;
inserting the extracted sample of the sensory effect data into the media data field;
wherein the extracted sample of the sensory effect data inserted into the media data field comprises timed data from among the sensory effect data, the timed data being data affected by time, and untimed data from among the sensory effect data is included into the composition information container field.

US Pat. No. 10,115,431

IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD

SONY CORPORATION, Tokyo ...

1. An image processing device, comprising:circuitry configured to:
receive a moving image,
wherein the moving image includes a plurality of frame images, and
wherein each of the plurality of frame images includes at least one object;
extract a first plurality of object images from each of the plurality of frame images;
select, based on a threshold value, a second plurality of object images corresponding to a sequence of movement of the at least one object in the moving image;
control, based on the second plurality of object images, a display device to display a first output image;
receive, at an interface, an edit operation from a user, wherein the edit operation corresponds to selection of a third plurality of object images from the first output image;
generate a second output image based on the edit operation, wherein the second output image comprises the third plurality of object images; and
control the display device to display the second output image.

US Pat. No. 10,115,423

NEAR-FIELD TRANSDUCER UTILIZING ANGLED REFLECTORS

Seagate Technology LLC, ...

1. An apparatus, comprising:a near-field transducer comprising an enlarged portion with a peg extending from the enlarged portion towards a media-facing surface, wherein an end of the peg faces the media-facing surface and an end of the enlarged portion opposed to the pea terminates a first distance away from the media surface;
two reflectors located co-planar with near-field transducer and located on either side of the near-field transducer in a crosstrack direction, the two reflectors being separated by a gap proximate the peg of the near-field transducer, the two reflectors each comprising:
a first edge at the media facing surface; and
a second flat edge at an acute angle to the media-facing surface, the second flat edge facing the near-field transducer, wherein a portion of the reflector near an intersection of the first and second edges is located between the end of the peg and the media-facing surface, the second flat edge terminating away from the intersection at a second distance from the media-facing surface that is less that the first distance of the near-field transducer; and
a waveguide coupling light to the near-field transducer to form a hot spot on a recording medium, the two reflectors concentrating the light on the peg of the near-field transducer.

US Pat. No. 10,115,422

HARD DISK DRIVE, MANUFACTURING METHOD OF THE SAME, AND SERVO DATA WRITING METHOD

Kabushiki Kaisha Toshiba,...

1. A method for writing servo data, including address data and a pair of two-phase burst data, on a disk using a write element of a head, comprising:writing the servo data as the head moves outwardly towards a radial position on the disk one step at a time, so as to overwrite part of servo data that have been written in a previous step, wherein the same address data are written as the head moves outwardly in two consecutive steps;
writing the servo data as the head moves inwardly towards the radial position one step at a time, so as to overwrite part of servo data that have been written in a previous step, wherein the same address data are written as the head moves inwardly in two consecutive steps; and
writing either one of two-phase burst data, or address data and the other of said two-phase burst data, at the radial position, so as to overwrite (i) at least part of servo data written in a last step of the writing as the head moved outwardly or (ii) at least part of servo data written in a last step of the writing as the head moved inwardly.

US Pat. No. 10,115,421

MOTOR BASE ASSEMBLY FOR STORAGE DEVICE

Western Digital Technolog...

17. A motor base assembly comprising:a basewall having an interior surface and an exterior surface;
a stiffener support portion on the interior surface of the basewall, wherein the stiffener support portion comprises:
a stiffener guide slot;
a secondary plate slot in communication with the stiffener guide slot, wherein the secondary plate slot is angled relative to the stiffener guide slot; and
a hole in between and connecting the stiffener guide slot with the secondary plate slot;
a land region on the exterior surface of the basewall,
wherein the stiffener guide slot and the secondary plate slot are configured to receive a second stiffener region of a flexible printed circuit and hold the second stiffener region in a substantially perpendicular position relative to the basewall; and
wherein the hole is configured to guide a first stiffener region of the flexible printed circuit and hold the first stiffener region over the land region in a substantially parallel position relative to the land region.

US Pat. No. 10,115,420

HEAD GIMBAL ASSEMBLY (HGA) SUPPORT CARTRIDGE FOR MAGNETIC HEAD AND DISK TESTERS

Guzik Technical Enterpris...

1. A cartridge for magnetic head and disk testers, comprising:a cartridge base,
a mounting platform, including a head mounting unit support surface adapted to receive a head mounting unit,
a counterweight element,
wherein the head-mounting unit support surface and the counterweight element are moveable relative to the cartridge base in opposite directions along a displacement axis,
an actuator assembly for controlling movement of the head-mounting unit support surface and the counterweight element relative to the cartridge base, and
a displacement sensing assembly positioned beneath the head mounting unit support surface and configured to sense movement of the head-mounting unit support surface relative to the cartridge base along the displacement axis.

US Pat. No. 10,115,419

METHOD FOR AFC SHIELDS FOR MULTIPLE SENSOR MAGNETIC TRANSDUCERS AND MAGNETIC TRANSDUCERS HAVING MULTIPLE SENSORS AND AFC SHIELDS

WESTERN DIGITAL (FREMONT)...

1. A magnetic recording device comprising:a magnetic read transducer comprising:
a first read sensor, a second read sensor, and a third read sensor, wherein the first read sensor, the second read sensor, and the third read sensor are positioned in a down track direction with the second read sensor between the first read sensor and the third read sensor, and wherein the first read sensor, the second read sensor, and the third read sensor are offset from one another in a cross track direction, the down track direction being in a plane that is parallel to an air bearing surface of the magnetic read transducer and the cross track direction being in a plane that is perpendicular to the air bearing surface;
a first middle shield between the first read sensor and the second read sensor, wherein the first middle shield comprises a first top middle shield and a first bottom middle shield separated by a first insulator; and
a second middle shield between the second read sensor and the third read sensor, wherein the second middle shield comprises a second top middle shield and a second bottom middle shield separated by a second insulator,
wherein the first top middle shield comprises a first antiferromagnetic layer and the first bottom middle shield comprises a second antiferromagnetic layer; and
wherein the first antiferromagnetic layer is separated from the second antiferromagnetic layer by the first insulator; and
wherein the first top middle shield further comprises a first plurality of layers between the first antiferromagnetic layer and the first read sensor and the first bottom middle shield further comprises a second plurality of layers between the second antiferromagnetic layer and the second read sensor.

US Pat. No. 10,115,417

ELECTRICALLY CONDUCTIVE MAGNETIC SHIELD LAMINATE STRUCTURE FOR CONTACT RECORDING SENSOR

International Business Ma...

1. An apparatus, comprising:an array of magnetic sensor structures on a common media facing surface;
a magnetic shield adjacent each of the magnetic sensor structures, each of the magnetic shields having at least one laminate pair comprising a magnetic layer and an electrically conductive nonmagnetic layer; and
a nonmagnetic spacer layer between each sensor structure and the associated magnetic shield,
wherein a longitudinal axis of the array of magnetic sensor structures is oriented nonparallel to a direction of media travel thereover; and
wherein each magnetic shield further includes a non-laminated magnetic portion sandwiching the laminate pairs between the non-laminated magnetic portion and the sensor structure.

US Pat. No. 10,115,416

MAGNETIC RECORDING WRITE APPARATUS HAVING A POLE HAVING AN ASPECT RATIO GREATER THAN ONE AND AN AUXILIARY POLE

Western Digital (Fremont)...

1. A magnetic write apparatus comprising:a main pole comprising:
a pole tip occupying a portion of a media facing surface;
a yoke recessed from the media facing surface and extending from the pole tip in a yoke direction that is perpendicular to the media facing surface; and
a yoke extension region extending in the yoke direction from the yoke,
wherein the main pole has a total length in the yoke direction, the total length extending from the media facing surface to a back surface of the yoke extension region, the back surface being the surface of the yoke extension region that is farthest away from the media facing surface in the yoke direction;
wherein the main pole is substantially rectangular in shape with rounded corners in the cross track direction, wherein the rounded corners have a radius of curvature that is at least 2 microns and not more than 4 microns;
wherein the main pole has a main pole width in a cross track direction that is perpendicular to the yoke direction and to the media facing surface; and
wherein the main pole has an aspect ratio obtained by dividing the total length by the main pole width, and wherein the aspect ratio is greater than 1.

US Pat. No. 10,115,415

MAGNETIC PULSE RECORDING SCHEME IN PERPENDICULAR MAGNETIC RECORDING

Headway Technologies, Inc...

1. A magnetic recording apparatus, comprising:(a) a high density disk (HDD) controller configured to input a data sequence to a preamplifier (preamp);
(b) wherein the preamp is configured to convert the data sequence to a recording current and to send the recording current to a write head in a perpendicular magnetic recording (PMR) write head on a head gimbal assembly (HGA); and
(c) wherein the PMR write head comprises a main pole that terminates at an air bearing surface proximate to a magnetic recording medium, configured so that the recording current causes the write head to generate a magnetic field that is applied from the main pole to write a plurality of bits in the magnetic recording medium such that the magnetic field is turned off for a certain period (tOFF) of time in a bit duration when a total recording time (tREC) for each bit is less than the bit duration and the bit duration equals the sum (tREC+tOFF), and when the main pole has a down-track length greater than a bit length for each of the plurality of bits.

US Pat. No. 10,115,414

DJ CONTROL DISC CONFIGURATION OPTIMIZED FOR DJ PERFORMANCE

inMusic Brands, Inc., Cu...

1. A DJ control disc, comprising:an axis of rotation, a top surface, an outer peripheral edge about a circumference of the disc;
the peripheral edge defining a groove that extends about the entirety of the circumference of the disc; and
the peripheral edge further includes an upper portion extending axially downward from the top surface and the groove extending axially downward from the upper portion;
wherein the upper portion linearly slopes downward and radially outward from the top surface defining a bevel,
wherein the groove includes a cross section that extends through a plane which is perpendicular to the top surface and parallel to the axis of rotation, the cross section having a concave curved arc shape, and
whereby the groove being configured and arranged for removable receipt a finger of an operator, when the disc is rotated about its axis of rotation, so that the operator can manually control rotation of the disc about the axis of rotation.

US Pat. No. 10,115,413

LINEAR PREDICTIVE ANALYSIS APPARATUS, METHOD, PROGRAM AND RECORDING MEDIUM

NIPPON TELEGRAPH AND TELE...

1. A linear predictive analysis method for obtaining a coefficient which can be converted into a linear predictive coefficient corresponding to an input time series signal for each frame which is a predetermined time interval, the linear predictive analysis method comprising:an autocorrelation calculating step of calculating autocorrelation Ro(i) between an input time series signal Xo(n) of a current frame and an input time series signal Xo(n?i) i sample before the input time series signal Xo(n) or an input time series signal Xo(n+i) i sample after the input time series signal Xo(n) for each of at least i=0, 1, . . . , Pmax; and
a predictive coefficient calculating step of obtaining a coefficient which can be converted into linear predictive coefficients from the first-order to the Pmax-order using modified autocorrelation R?o(i) obtained by multiplying the autocorrelation Ro(i) by a coefficient for each corresponding i,
wherein the linear predictive analysis method further comprises a coefficient determining step of acquiring the coefficient from one coefficient table among coefficient tables t0, t1 and t2 using a period, an estimate value of the period, a quantization value of the period or a value having negative correlation with a fundamental frequency based on an input time series signal in the current frame or a past frame and a value having positive correlation with intensity of periodicity or a pitch gain assuming that a coefficient wt0(i) is stored in the coefficient table t0, a coefficient wt1(i) is stored in the coefficient table t1, and a coefficient wt2(i) is stored in the coefficient table t2,
for at least part of i other than i=0, wt0(i) in the coefficient determining step, a coefficient table is selected and a coefficient stored in the selected coefficient table is acquired so as to comprise a case where, in at least two ranges among three ranges constituting a possible range of the period, the estimate value of the period, the quantization value of the period or the value having negative correlation with the fundamental frequency, a coefficient determined when the value having positive correlation with the intensity of periodicity or the pitch gain is small is greater than a coefficient determined when the value having positive correlation with the intensity of periodicity or the pitch gain is great, and a case where, in at least two ranges among three ranges constituting a possible range of the value having positive correlation with the intensity of periodicity or the pitch gain, a coefficient determined when the period, the estimate value of the period, the quantization value of the period or the value having negative correlation with the fundamental frequency is great is greater than a coefficient determined when the period, the estimate value of the period, the quantization value of the period or the value having negative correlation with the fundamental frequency is small.

US Pat. No. 10,115,412

SIGNAL PROCESSOR WITH SIDE-TONE NOISE REDUCTION FOR A HEADSET

1. A signal processor for a headset configured with a microphone terminal for receiving a microphone signal, a loudspeaker terminal for outputting a loudspeaker signal, and a far-end terminal for communicating an inbound signal and an outbound signal with a far-end; comprising:an outbound path from the microphone terminal to the far-end terminal;
a side-tone path configured to generate a side-tone signal from the microphone signal via a side-tone filter,
an inbound path from the far-end terminal to the loudspeaker terminal and comprising a combiner configured to combine the side-tone signal and the inbound signal to generate the loudspeaker signal; and
a side-tone filter controller that receives the microphone signal and computes a first noise estimate with a signal-to-noise level of the microphone signal at respective frequency bands and based thereon controls the side-tone filter to improve a signal-to-noise ratio of the side-tone signal;wherein the side-tone filter in the side-tone path comprises multiple filter stages that are individually controlled based on the first noise estimate; andwherein the multiple filter stages are configured from a group consisting of: multiple peak filters and a high-shelf filter;and wherein the side-tone filter controller executes an iterative process of:determining parameters for a filter stage based on the first noise estimate;
computing a frequency domain gain estimate of the frequency domain gain transfer function for a filter stage;
computing a second noise estimate by subtracting the frequency domain gain estimate from the first noise estimate;
updating the first noise estimate to be in accordance with the second noise estimate;wherein the filter stages are controlled via coefficients computed from the parameters for a respective filter stage computed over iterations of the iterative process; andwherein determining parameters for a filter stage comprises fitting a filter that has a largest possible gain-bandwidth product while optimizing the signal-to-noise ratio in an audio band of interest.

US Pat. No. 10,115,411

METHODS FOR SUPPRESSING RESIDUAL ECHO

Amazon Technologies, Inc....

1. A computer-implemented method for removing double-talk effects, the method comprising:receiving, by a device having a microphone and a loudspeaker, first audio data during a communication connection;
outputting, by the loudspeaker, audible sound corresponding to the first audio data;
receiving second audio data from the microphone, the second audio data being in a time domain and including a first representation of the audible sound and a first representation of speech detected by the microphone;
determining third audio data corresponding to an estimate of the audible sound detected by the microphone, the third audio data being in the time domain and including a second representation of the audible sound;
performing acoustic echo cancellation to remove the third audio data from the second audio data to generate fourth audio data in the time domain, the fourth audio data corresponding to output from an acoustic echo canceller;
determining fifth audio data by taking a discrete Fourier transform of the second audio data, the fifth audio data being in the frequency domain and corresponding to the output from the microphone;
determining sixth audio data by taking a discrete Fourier transform of the third audio data, the sixth audio data being in the frequency domain and corresponding to the estimate of the audible sound detected by the microphone;
determining seventh audio data by taking a discrete Fourier transform of the fourth audio data, the seventh audio data being in the frequency domain and corresponding to the output from the acoustic echo canceller;
selecting a first frequency band within a human hearing range;
determining a first correlation value corresponding to the first frequency band, wherein the first correlation value is determined using a normalized cross power spectral density function between the fifth audio data and the sixth audio data, the first correlation value indicating a correlation between the fifth audio data and the sixth audio data;
determining, based on the first correlation value, a first gain value associated with the first frequency band;
determining a second correlation value corresponding to a second frequency band using the normalized cross power spectral density function, the second frequency band within the human hearing range;
determining, based on the second correlation value, a second gain value associated with the second frequency band; and
determining eighth audio data using the seventh audio data, the first gain value, and the second gain value, the eighth audio data including a second representation of the speech.

US Pat. No. 10,115,409

ADAPTIVE PROCESSING OF SOUND DATA

Samsung Electronics Co., ...

1. An electronic device comprising:a speaker;
a communication module configured to communicate with an external electronic device; and
a processor connected to the communication module,
wherein the processor is configured to:
receive data and additional data from the external electronic device using the communication module, the additional data indicating attributes of the data;
when the attributes of the data are determined to be speech according to the additional data, decode the data using a first decoding scheme and change the quality of the decoded data using a first signal processing scheme, which is at least one of a plurality of first signal post-processing schemes;
when the attributes of the data are determined to be music according to the additional data, decode the data using a second decoding scheme, which is different than the first decoding scheme, and change the quality of the decoded data by using a second signal processing scheme, which is at least one of a plurality of second signal post-processing schemes, wherein the second signal processing scheme is different than the first signal processing scheme; and
output, through the speaker, an audio signal corresponding to the data changed using the first signal processing scheme or the second signal processing scheme,
wherein the plurality of first signal post-processing schemes includes a scheme for reducing or removing noise from the decoded data, a scheme for removing a low-band portion of the frequency domain of the decoded data, and a scheme for adjusting dynamics of the decoded data.

US Pat. No. 10,115,408

DEVICE AND METHOD FOR QUANTIZING THE GAINS OF THE ADAPTIVE AND FIXED CONTRIBUTIONS OF THE EXCITATION IN A CELP CODEC

VOICEAGE CORPORATION, To...

1. A device for decoding a sound signal encoded in a bitstream including a gain codebook index, comprising:at least one processor; and
a memory coupled to the processor and comprising non-transitory code instructions that when executed cause the processor to implement:
a decoder of an adaptive codebook contribution of an excitation from the bitstream;
a decoder of a fixed codebook contribution of the excitation from the bitstream;
a device for retrieving quantized adaptive and fixed codebook gains in a sub-frame of
a frame of the encoded sound signal, comprising:
an estimator of the fixed codebook gain in the sub-frame, wherein:
(i) the estimator is supplied with a parameter representative of a classification of the frame,
(ii) the estimator, for a first sub-frame of the frame, uses the parameter representative of the classification of the frame and an energy of the fixed codebook contribution to estimate the fixed codebook gain, and
(iii) the estimator comprises, for each sub-frame of the frame following the first sub-frame, (1) a logarithm calculator, (2) a calculator of a linear estimation of the fixed codebook gain in logarithmic domain using the parameter representative of the classification of the frame, quantized adaptive codebook gains of at least one previous sub-frame of the frame supplied to the calculator of linear estimation directly, and quantized fixed codebook gains of the at least one previous sub-frame supplied to the calculator of linear estimation in logarithmic domain through the logarithm calculator, and (3) a converter of the linear estimation in logarithmic domain in linear domain to produce the estimated fixed codebook gain;
a gain codebook for supplying the quantized adaptive codebook gain and a correction factor for the sub-frame in response to the gain codebook index; and
a multiplier of the estimated fixed codebook gain by the correction factor to provide the quantized fixed codebook gain in the sub-frame;
a multiplier of the adaptive codebook contribution by the quantized adaptive codebook gain;
a multiplier of the fixed codebook contribution by the quantized fixed codebook gain;
an adder of the adaptive codebook contribution multiplied by the quantized adaptive codebook gain and the fixed codebook contribution multiplied by the quantized fixed codebook gain to form a total excitation; and
a synthesis filter for synthesizing the sound signal by filtering the total excitation.

US Pat. No. 10,115,406

APPARATUS AND METHOD FOR AUDIO SIGNAL ENVELOPE ENCODING, PROCESSING, AND DECODING BY SPLITTING THE AUDIO SIGNAL ENVELOPE EMPLOYING DISTRIBUTION QUANTIZATION AND CODING

Fraunhofer-Gesellschaft z...

1. An apparatus for decoding to acquire a reconstructed audio signal envelope, comprising:a signal envelope reconstructor for generating the reconstructed audio signal envelope depending on at least one splitting point, and
an output interface for outputting the reconstructed audio signal envelope,
wherein the signal envelope reconstructor is configured to generate the reconstructed audio signal envelope such that the at least one splitting point divides the reconstructed audio signal envelope into at least two audio signal envelope portions, wherein a predefined assignment rule defines a signal envelope portion value for each signal envelope portion of the at least two signal envelope portions depending on said signal envelope portion, and
wherein the signal envelope reconstructor is configured to generate the reconstructed audio signal envelope such that, for each of the at least two signal envelope portions, an absolute value of its signal envelope portion value is greater than half of an absolute value of the signal envelope portion value of each of the other signal envelope portions.

US Pat. No. 10,115,405

METHOD FOR REDUCTION OF ALIASING INTRODUCED BY SPECTRAL ENVELOPE ADJUSTMENT IN REAL-VALUED FILTERBANKS

Dolby International AB, ...

1. An audio decoder for producing a full bandwidth audio signal having a lowband portion and a highband portion, the apparatus comprising:a cosine modulated, real-valued analysis filterbank that receives a time domain decoded audio signal and produces a plurality of real-valued subband signals;
a high frequency reconstructor that regenerates at least some of the highband portion by copying one or more of the plurality of real-valued subband signals up to the highband portion;
an aliasing detector that identifies subband signals where aliasing created by spectral envelope adjustment of an audio signal may occur based at least in part on a linear predictor applied to at least some of the plurality of real-valued subband signals;
an energy estimator that estimates an energy of at least some of the plurality of copied real-valued subband signals;
an aliasing reducer that modifies a gain to be applied to at least some of the identified subbands signals based at least in part on the estimated energy; and
a real-valued synthesis filterbank that combines the plurality of real-valued subband signals with the highband portion to produce the full bandwidth audio signal, the full bandwidth audio including real-valued time domain samples,
wherein the audio decoder is implemented at least in part with one of more hardware elements,
wherein the linear predictor uses a covariance method of linear predictive coding (LPC),
wherein the linear predictor is a second order linear predictor, and
wherein the aliasing detector further comprises a subband examiner that examines subbands having channel numbers k and k?1.

US Pat. No. 10,115,403

ENCODING OF MULTIPLE AUDIO SIGNALS

QUALCOMM Incorporated, S...

1. A device comprising:a processor configured to receive a first combined frame and a second combined frame corresponding to a multi-channel audio signal;
a memory configured to store first lookahead portion data of the first combined frame, the first lookahead portion data received from the processor; and
a combiner configured to generate a frame at a multi-channel encoder, the frame including a subset of samples of the first lookahead portion data, one or more samples of updated sample data corresponding to the first combined frame, and a group of samples of second combined frame data corresponding to the second combined frame.

US Pat. No. 10,115,402

AUDIO ENCODING DEVICE, METHOD AND PROGRAM, AND AUDIO DECODING DEVICE, METHOD AND PROGRAM

NTT DOCOMO, INC., Tokyo ...

1. An audio encoding device for encoding an audio signal consisting of a plurality of frames, the encoding device comprising:a processor;
an audio encoding unit executed by the processor to encode the audio signal;
an auxiliary information encoding unit executed by the processor to estimate and encode auxiliary information about a temporal change of power of the audio signal, the auxiliary information used in packet loss concealment in decoding of the audio signal,
wherein the auxiliary information encoding unit estimates and encodes quantized transient power and a flag of sudden change of power, as the auxiliary information about the temporal change of power of the audio signal; and
wherein the auxiliary information encoding unit is configured to operate in a first mode to encode the quantized transient power and the flag of sudden change of power in response to the flag being indicative of the presence of a transient in the audio signal, and the auxiliary information encoding unit is further configured to operate in a second mode to encode only the flag in response to the flag being indicative of the absence of a transient in the audio signal.

US Pat. No. 10,115,401

CODING OF SPECTRAL COEFFICIENTS OF A SPECTRUM OF AN AUDIO SIGNAL

1. Decoder for decoding spectral coefficients of a spectrogram of an audio signal from a data stream, composed of a sequence of a spectra, the decoder being configured todecode the spectral coefficients along a spectrotemporal path which scans the spectral coefficients spectrally from low to high frequency within one spectrum and then proceeds with spectral coefficients of a temporally succeeding spectrum,
decode, by entropy decoding, a currently to be decoded spectral coefficient of a current spectrum depending, in a context-adaptive manner, on a template of previously decoded spectral coefficients including a spectral coefficient belonging to the current spectrum, the template being positioned at a location of the currently to be decoded spectral coefficient, by adjusting at least one of a relative spectral distance between the spectral coefficient belonging to the current spectrum and the currently to be decoded spectral coefficient or a relative spectral distance between the spectral coefficient belonging to the current spectrum and a further spectral coefficient of the template which belongs to the current spectrum depending on an information concerning a shape of the spectrum.

US Pat. No. 10,115,399

AUDIO CLASSIFIER THAT INCLUDES ANALOG SIGNAL VOICE ACTIVITY DETECTION AND DIGITAL SIGNAL VOICE ACTIVITY DETECTION

NXP B.V., Eindhoven (NL)...

1. An audio classifier comprising:a first processor having hard-wired logic configured to receive an audio signal and detect audio activity from the audio signal, wherein the first processor is an analogue processor; and
a second processor having reconfigurable logic configured to classify the audio signal as a type of audio signal in response to the first processor detecting audio activity, wherein the second processor is a digital processor;
in which the second processor is a voice activity detector, in which the second processor is configured to classify the audio signal as either speech or not speech;
in which the second processor is configured to determine at least three features of the audio signal and classify the audio signal as either speech or not speech in accordance with the at least three features, in which the at least three features comprises:
short term energy;
tonal power ratio; and
spectral crest factor;
wherein the second processor is configured to compute the tonal power ratio and the crest factor using common computed quantities and is configured to classify the audio signal as speech only if each of the short term energy, the tonal power ratio, and the spectral crest factor exceeds a corresponding feature-specific predetermined threshold.

US Pat. No. 10,115,398

SIMPLE AFFIRMATIVE RESPONSE OPERATING SYSTEM

Intelligently Interactive...

1. A system, comprising:a processor;
a sensor coupled to the processor;
an electronic sensory presentation device; and
non-transitory memory storing:
an identification of a single, unique, system-wide, and context-independent affirmative action for use in modifying system parameters, selecting options, and selecting items of content;
system parameters, wherein each system parameter is associated with an identifier from a sequence of system parameter identifiers;
options, wherein each option is part of a list of possible commands or navigation options, and wherein each option is associated with an identifier from a sequence of option identifiers; and
instructions that, when executed by the processor, cause the processor to:
store the items of content, wherein each item of content comprises a webpage, a book, an article, a text-based communication, an event stored in a calendar system, an audio file, or a video file, and is not one of the options or the system parameters;
store a sequence of identifiers of content, wherein each identifier of the sequence of identifiers of content is associated with an item of content;
enter a first list-pause cycle comprising:
a first list-pause that comprises:
 outputting, via the sensory presentation device, an identifier from the sequence of identifiers of content; and
 pausing a predetermined length of time;
repeating the first list-pause, each repetition of the first list-pause outputting a different next identifier from the sequence of identifiers of content, until determining, via input from the sensor, that the affirmative action has been performed during the pause of a most recent first list-pause; and
responsive to determining that the affirmative action has been performed during the pause of the most recent list-pause, outputting, via the sensory presentation device, an item of content associated with the identifier output during that most recent first list-pause;
enter a second list-pause cycle comprising:
a second list-pause comprising:
 outputting, via the sensory presentation device, an identifier from the sequence of option identifiers; and
 pausing a predetermined length of time;
 repeating the second list-pause, each repetition of the second list-pause outputting a different next identifier from the sequence of option identifiers, until determining, via input from the sensor, that the single unique affirmative action has been performed during the pause of a most recent second list-pause; and
 responsive to determining that the affirmative action has been performed during the pause of the most recent second list-pause, either navigating to an application mode or performing a command based on the option associated with the identifier output during that most recent second list-pause; and
enter a third list-pause cycle comprising:
a third list-pause comprising:
 outputting, via the sensory presentation device, an identifier from the sequence of system parameter identifiers; and
 pausing a predetermined length of time;
repeating the third list-pause, each repetition of the third list-pause outputting a different next identifier from the sequence of system parameter identifiers, until determining, via input from the sensor, that the single unique affirmative action has been performed during the pause of a most recent third list-pause; and
responsive to determining that the affirmative action has been performed during the pause of the most recent third list-pause, modifying the system parameter associated with the identifier output during that most recent third list-pause.

US Pat. No. 10,115,397

LOW POWER DETECTION OF A VOICE CONTROL ACTIVATION PHRASE

Imagination Technologies ...

1. A microphone system comprising a microphone and hardware logic configured to compare an audio stream received via the microphone with a pre-defined phrase and in response to detecting the pre-defined phrase in the audio stream, to send a trigger signal to activate a module external to the microphone system, and, in response to partially detecting the pre-defined phrase in the audio stream, to adapt the operation of the microphone system based on a number of partial matches which are detected.

US Pat. No. 10,115,395

VIDEO DISPLAY DEVICE AND OPERATION METHOD THEREFOR

LG ELECTRONICS INC., Seo...

1. A method for operating a video display device, the method comprising:transmitting a voice acquisition command signal to at least one peripheral device connected to the video display device;
receiving at least one first voice signal acquired by the at least one peripheral device in response to the voice acquisition command signal, wherein the at least one first voice signal is acquired through a microphone of the at least one peripheral device;
receiving at least one second voice signal acquired through a microphone of the video display device;
comparing a voice level of the first voice signal with a voice level of the second voice signal or a noise level of the first voice signal with a noise level of the second voice signal;
based on the comparison result, selecting a voice signal from the first voice signal or the second voice signal for performing voice recognition;
recognizing a voice of a user based on the selected voice signal; and
controlling the video display device to perform an operation corresponding to the recognized voice,
wherein the voice acquisition command signal is transmitted from the video display device to the at least one peripheral device based on a trigger voice.

US Pat. No. 10,115,394

APPARATUS AND METHOD FOR DECODING TO RECOGNIZE SPEECH USING A THIRD SPEECH RECOGNIZER BASED ON FIRST AND SECOND RECOGNIZER RESULTS

MITSUBISHI ELECTRIC CORPO...

1. A voice recognition apparatus which performs recognition of voice to be outputted from an output unit, the voice recognition apparatus comprising:a processor configured to control:
first, second and third voice recognizers which each recognize an input voice and obtain a recognition result including a candidate character string corresponding to the input voice, each of said first, second and third voice recognizers include a memory that stores a dictionary; and
a controller which, when it is decided based on said recognition result obtained by each of said first and second voice recognizers to cause said third voice recognizer to recognize said input voice, causes said third voice recognizer to recognize said input voice by using the dictionary included in said third voice recognizer including said candidate character string obtained by at least one of said first and second voice recognizers, and causes said output unit to output said recognition result obtained by said third voice recognizer, wherein
the recognition results obtained by each of said first and second voice recognizers further include score values indicating accuracy of said candidate character strings, and
whether or not to cause the third voice recognizer to recognize said input voice is decided based on an index including at least one of said score values which are obtained by said first and second voice recognizers and are a maximum, a similarity indicating a degree that said candidate character strings obtained by said first and second voice recognizers match each other, and an order distance indicating a degree of difference in an order of said candidate character strings aligned in order of said score values obtained by said first and second voice recognizers.

US Pat. No. 10,115,393

REDUCED SIZE COMPUTERIZED SPEECH MODEL SPEAKER ADAPTATION

Microsoft Technology Lice...

13. A computer-implemented method of adapting a speech engine acoustic model, comprising:inserting an adaptive matrix into an adaptive layer of a computer-readable speech engine acoustic model;
adapting the adaptive matrix to a speaker, using training data to modify a set of weights in the adaptive matrix to generate a speaker-adapted speech engine acoustic model, with the adapting of the adaptive matrix comprising performing speaker-specific adaptation of the adaptive matrix to produce adapted layer weights of the adaptive layer, with the adapting of the adaptive matrix comprising a data size reduction technique that is either:
threshold value adaptation, with the threshold value adaptation comprising comparing a set of adapted layer weights in the adaptive layer to a predetermined threshold value and either constraining weights in the set of layer weights that are less than the threshold value to be a single target value, or constraining weights in the set of layer weights that are greater than the threshold value to be the single target value, wherein the threshold value adaptation comprises a weight constraining operation that is either: constraining weights in the set of layer weights that are less than the threshold value to be the single target value, wherein the threshold value is greater than or equal to zero, and wherein the target value is zero; or constraining weights in the set of layer weights that are greater than the threshold value to be the single target value, wherein the threshold value is less than or equal to zero, and wherein the target value is zero;
diagonal-based quantization, wherein the diagonal-based quantization comprises constraining to a first range and quantizing a set of diagonal weights of the adaptive layer, and constraining to a second range and quantizing a set of non-diagonal weights of the adaptive layer, with the first range being different from the second range; or
a combination of the threshold value adaptation and the diagonal-based quantization;
accessing the speaker-adapted speech engine acoustic model; and
using the speaker-adapted speech engine acoustic model in performing speech recognition on computer-readable audio speech input via a computerized speech recognition engine.

US Pat. No. 10,115,392

METHOD FOR ADJUSTING A VOICE RECOGNITION SYSTEM COMPRISING A SPEAKER AND A MICROPHONE, AND VOICE RECOGNITION SYSTEM

VISTEON GLOBAL TECHNOLOGI...

1. A method for adjusting a voice recognition system to different surrounding acoustic noise levels and voice characteristics, wherein the voice recognition system comprises a speaker and a microphone, the method comprising the steps of:a) memorizing an audio frequency signal by the voice recognition system;
wherein the audio frequency signal comprises any prompt output by the speaker or any audible signal output by the speaker and/or a prompt signal prompting for a user input signal and/or a welcome signal;
wherein the audio frequency signal is recognized by the voice recognition system;
b) playing back the audio frequency signal by means of the speaker, wherein after the playing back of the audio frequency signal, a user is prompted to provide the user input signal;
c) detecting an acoustic effect of the playing back of the audio frequency signal by the microphone;
d) generating a detection signal by the microphone based on the detected acoustic effect of the playing back of the audio frequency signal;
e) automatically adjusting parameters of the voice recognition system upon detecting the generated detection signal and prior to the user operatively using the voice recognition system; and
f) receiving the user input signal by the voice recognition system; wherein the user input signal comprises a first voice command;
wherein the steps a) through f) are performed in sequential order;
wherein the adjusting of parameters of the voice recognition system includes an adjustment of a gain of an amplifier associated to the microphone, speaker or both;
wherein the voice recognition system is in a vehicle; and
wherein the step of playing back the audio frequency signal is conducted during an initial use of the voice recognition system once the user enters the vehicle.

US Pat. No. 10,115,391

METHOD AND APPARATUS FOR PROVIDING VOICE FEEDBACK INFORMATION TO USER IN CALL

SHANGHAI ROBOT TECHNOLOGY...

1. A method for providing a voice feedback information to a user in a call, where the method is applied to a computer equipment, comprising:acquiring a text information obtained by conducting a voice recognition on a voice information of the user;
identifying a menu item to be jumped to according to the text information in conjunction with a plurality of menu items of other party in the call, wherein the menu item to be jumped to is away from a present menu item by at least two levels; and
jumping to the identified menu item, and sending the voice feedback information that corresponds to the menu item and is to be provided to the user,
wherein identifying a menu item to be jumped to according to the text information in conjunction with a plurality of menu items of the other party in the call further comprises:
supplementing the text information according to a context information of the call, when it is determined that a menu item to be jumped to is not identified according to the text information; and
identifying the menu item to be jumped to according to the supplemented text information in conjunction with the plurality of menu items of the other party.

US Pat. No. 10,115,390

SYSTEM AND METHOD TO FACILITATE CONVERSION BETWEEN VOICE CALLS AND TEXT COMMUNICATIONS

Amazon Technologies, Inc....

1. A method comprising:receiving an indication of environmental conditions associated with a first user device;
determining, by one or more processing devices, that the environmental conditions indicate that communications with the first user device are to be made in a voice call mode;
receiving, from a second user device, a first text data packet corresponding to text communications with the first user device;
converting the first text data packet into a first voice data packet; and
sending, via a wireless network, the first voice data packet to the first user device.

US Pat. No. 10,115,386

DELAY TECHNIQUES IN ACTIVE NOISE CANCELLATION CIRCUITS OR OTHER CIRCUITS THAT PERFORM FILTERING OF DECIMATED COEFFICIENTS

QUALCOMM Incorporated, S...

1. An apparatus comprising:a down sample unit; and
an up sample unit,
wherein the down sample unit and the up sample unit combined together produce a combined delay,
wherein the down sample unit and the up sample unit are each tunable such that the combined delay associated with processing a sample via the down sample unit and the up sample unit corresponds to a delay associated with one or more tap delays of a filter configured to filter samples in a down-sampled domain, and
wherein the combined delay associated with processing the sample via the down sample unit and the up sample unit is tunable based on a sampling ratio of the down sample unit and the up sample unit.

US Pat. No. 10,115,385

ULTRASONIC TRANSMISSION/RECEPTION UNIT, MANUFACTURING METHOD OF ULTRASONIC TRANSMISSION/RECEPTION UNIT, AND ULTRASONIC FLOW METER DEVICE

PANASONIC INTELLECTUAL PR...

1. An ultrasonic transmission/reception unit comprising:a metal plate;
an acoustic matching member fastened to a first main surface of the metal plate;
a piezoelectric substrate fastened to a second main surface of the metal plate such that the piezoelectric substrate corresponds to a portion of the metal plate to which the acoustic matching member is fastened;
a first lead wire connected to an end portion of the piezoelectric substrate which is more distant from the metal plate, to supply a voltage applied to the piezoelectric substrate;
a second lead wire connected to the metal plate, to supply the voltage applied to the piezoelectric substrate; and
a vibration suppression member containing a thermoplastic resin as a major component, the vibration suppression member being configured to cover, in a unitary manner, the second main surface of the metal plate, except for a portion of the second main surface to which the piezoelectric substrate is fastened, a surface of the piezoelectric substrate, an end surface of the metal plate, an outer peripheral portion of the first main surface of the metal plate, the first lead wire, and the second lead wire
wherein the vibration suppression member contacts no portion of the acoustic matching member directly;
wherein the metal plate has a flat plate shape and houses no piezoelectric substrate.

US Pat. No. 10,115,384

PICKUP APPARATUS FOR MUSICAL INSTRUMENT

Abeseishi Ltd., Fukushim...

1. A pickup apparatus, for a musical instrument, to be fixed to the musical instrument, comprising:a disc-shaped piezoelectric element;
a couple of circular members receiving interposition of the piezoelectric element therebetween; and
leg portions being arranged on a surface of any one of the couple of circular members,
each circular member including protrusions formed protrusively toward the other circular member in two positions along a peripheral edge of an opposite surface in a face-to-face relationship with the other circular member, and
the piezoelectric element being supported within an air gap formed by the protrusions between the couple of circular members in a state of the piezoelectric element being interposed between the protrusions possessed by respective circular wood members.

US Pat. No. 10,115,383

HUMBUCKING PICKUP AND METHOD OF PROVIDING PERMANENT MAGNET EXTENDING THROUGH OPPOSING COILS PARALLEL TO STRING ORIENTATION

Fender Musical Instrument...

1. A humbucking pickup for a musical instrument, comprising:a bobbin assembly including a first bobbin and a second bobbin;
a first coil wound around the first bobbin;
a second coil wound around the second bobbin;
a permanent magnet extending through an opening in the first bobbin and second bobbin with the first coil and second coil disposed around the permanent magnet; and
a housing disposed over the bobbin assembly, wherein a north pole and south pole of the permanent magnet are oriented in parallel to a top surface of the housing.

US Pat. No. 10,115,381

DEVICE AND METHOD FOR SIMULATING A SOUND TIMBRE, PARTICULARLY FOR STRINGED ELECTRICAL MUSICAL INSTRUMENTS

1. A device for simulating a sound timbre, particularly for stringed electrical musical instruments, which comprises an input for acquiring an electrical signal generated by a musical instrument, and a filter which operate on said electrical signal generated by a source musical instrument, wherein said filter applies to said electrical signal generated by said source musical instrument a transfer function obtained by correlating the sound profile of a target musical instrument to the sound profile of said source musical instrument, said sound profiles comprising respectively the average frequency spectrum of a range of notes played on said target musical instrument and the average frequency spectrum of a corresponding range of notes played on said source musical instrument, wherein said musical instrument comprises strings and said sound profiles are defined on the basis of said electrical signals generated by said musical instruments, corresponding to the playing of at least one note per string, covering at least one tenth of the range of extension of said musical instruments.

US Pat. No. 10,115,380

PROVIDING FEEDBACK ON MUSICAL PERFORMANCE

International Business Ma...

1. A computer-implemented method for providing feedback on a musical performance performed with a musical instrument, the computer-implemented method comprising:identifying an instrument profile associated with the musical instrument used to perform the musical performance, the instrument profile comprising information relating to one or more tuning characteristics of the instrument and including a description of commonly out of tune notes for the instrument;
analyzing a pitch of notes of the musical performance based on the instrument profile to determine a measure of tuning of the musical performance comprising:
identifying notes of the musical performance that are described as commonly out of tune notes by the instrument profile;
excluding the identified notes of the musical performance;
determining an average pitch of the non-excluded notes; and
determining a first measure of tuning of the musical performance based on the determined average pitch; and
generating a feedback signal based on the determined measure of tuning.

US Pat. No. 10,115,379

ACOUSTIC GUITAR USER INTERFACE

Gibson Brands, Inc., Nas...

1. An acoustic guitar comprising:a neck;
a body; and
a user interface module comprising:
an audio effect module configured to implement one or more audio effects;
one or more effect controllers, wherein each effect controller is configured to set a level of a corresponding audio effect implemented by the audio effect module;
a first two blend potentiometer configured to allow the user to adjust a blend between a piezo pickup and a magnetic pickup;
a second two blend potentiometer configured to allow the user to adjust a blend between a microphone and an output set by the first two blend potentiometer; and
a voice controller configured to allow a user to select a patch from a plurality of available patches, wherein each patch of the plurality of available patches comprises a configuration of one or more audio effects set at various levels to arrive at a desired effect template.

US Pat. No. 10,115,378

LASER ETCHED STRINGED INSTRUMENT AND METHOD OF MANUFACTURE

11. A method of adorning at least one of a body, a neck, and a headstock of a stringed instrument, the method comprising steps of:obtaining a stringed instrument having at least one coating layer applied over at least one of said body, said neck and said headstock;
defining a digital representation of an artwork image for application upon a target section of said stringed instrument, wherein said target section of said stringed instrument is at least one of said body, said neck and said headstock;
programming said digital representation of said artwork image into a computer controlling a laser etching system;
programming a laser etching power into said computer;
locating a laser and said target section of said stringed instrument in registration with one another whereby said laser will replicate said artwork image onto said target section of said stringed instrument at a desired location; and
etching said artwork image onto said target section of said stringed instrument at a desired location by using a laser to remove a portion of an at least an outer layer of said at least one coating layer from said target section of said stringed instrument in accordance with said digital representation said artwork image, wherein said removed portion of said at least an outer layer exposes a material beneath said removed portion of said at least an outer layer, creating a contrast, wherein said contrast creates a visible image replicating said artwork image.

US Pat. No. 10,115,373

POSITION DETECTING SYSTEM AND POSITION DETECTING PROGRAM

NINTENDO CO., LTD., Kyot...

1. A position detecting system comprising:an information transmission device, comprising a plurality of transmitters, for transmitting predetermined information;
a mobile terminal for receiving the predetermined information; and
a control device capable of communicating with the mobile terminal, the mobile terminal including:
a display for displaying a first image and a second image, wherein the second image is part of the first image;
first receiver circuitry for receiving the predetermined information transmitted from the information transmission device;
an image processing unit for changing the first image in accordance with the predetermined information received by the first receiver circuitry;
a pointing device for accepting an input by a user, wherein
the input by the user comprises a selection of a predefined course comprising course data, wherein the course data includes predetermined coordinates of a series of predetermined destination positions of the mobile terminal associated with the selected course; and
transmitter circuitry for transmitting, to the control device, current positional information corresponding to the predetermined information received by the first receiver circuitry and operation information indicating the input entered by the user through the pointing device,
the control device arranged separately from the mobile terminal and the information transmission device and including:
second receiver circuitry for receiving the current positional information and the operation information transmitted from the mobile terminal;
provider circuitry for providing feedback information to a user of the mobile terminal, wherein
the image processing unit changes the second image in accordance with the current positional information, and
the provider circuitry provides the feedback information based on the operation information and the received current positional information transmitted by the mobile terminal, wherein
the image processing unit changes a display form of the second image between a first display form indicating the second image is selectable by the user and a second display form indicating the second image is not selectable by the user when the current positional information indicates a predetermined destination position of the series of predetermined destination positions associated with the selected course, and wherein
the display form indicates that the second image is selectable when the current positional information indicates the predetermined destination position.

US Pat. No. 10,115,372

DISPLAY APPARATUS AND CONTROLLING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A display apparatus comprising:a sensor configured to sense ambient light;
a display configured to provide a screen including a first area which displays a content and a second area outside the first area; and
a processor configured to change a size of the second area based on the sensed ambient light,
wherein the processor is further configured to divide the second area into a plurality of edge areas based on the sensed ambient light and change respective sizes of the plurality of edge areas.

US Pat. No. 10,115,370

USER TERMINAL DEVICE AND CONTROL METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A mobile device comprising:a first input user interface;
a second input user interface;
a third input user interface;
a sensing device configured to sense an operating condition of the mobile device; and
a controller configured to enable the first input user interface and disable the second input user interface if the operating condition corresponds to a first condition, enable the second input user interface and disable the first input user interface if the operating condition corresponds to a second condition different from the first condition, and enable the first input user interface and the second input user interface and disable the third input user interface if the operating condition corresponds to a third condition different from each of the first condition and the second condition,
wherein the operating condition is at least one of an external environment of the mobile device and a motion of the mobile device, and
wherein when the first input user interface and the second input user interface are inputted simultaneously, one of the first input user interface and the second input user interface is selected based on a preset priority level set by a user via a user interface for setting a priority level.

US Pat. No. 10,115,368

LIQUID CRYSTAL DISPLAY DRIVING METHOD AND DRIVE DEVICE

Shenzhen China Star Optoe...

1. A liquid crystal display driving method, comprising the following steps:acquiring a gray level value of a current frame image of a pixel electrode of a liquid crystal display when the liquid crystal display is activated;
determining a gray level of the current gray level value, the gray level including a high gray level and a low gray level;
if the current gray level value is the high gray level, then determining whether to perform an overvoltage driving on the pixel electrode according to a first gray level difference threshold value which is predetermined;
if the current gray level value is the low gray level, then determining whether to perform the overvoltage driving on the pixel electrode according to a second gray level difference threshold value which is predetermined, and the first gray level difference threshold value being less than the second gray level difference threshold value;
wherein determining whether to perform the overvoltage driving on the pixel electrode according to the first gray level difference threshold value which is predetermined comprises:
acquiring a first gray level difference value of the current frame image and a previous frame image;
determining whether the first gray level difference value is larger than the first gray level difference threshold value;
if the first gray level difference value is larger than the first gray level difference threshold value, then activating the overvoltage driving;
wherein determining whether to perform the overvoltage driving on the pixel electrode according to the second gray level difference threshold value which is predetermined comprises:
acquiring a second gray level difference value of the current frame image and the previous frame image;
determining whether the second gray level difference value is larger than the second gray level difference threshold value;
if the second gray level difference value is larger than the second gray level difference threshold value, then activating the overvoltage driving.

US Pat. No. 10,115,367

DRIVING CIRCUIT AND LIQUID CRYSTAL DISPLAY DEVICE

Shenzhen China Star Optoe...

1. A driving circuit, characterized in that, the driving circuit comprises: a first diode, a second diode, a third diode, a fourth diode, a first capacitor, a second capacitor and an adjustable voltage source, wherein; an anode of the first diode is used to input an input voltage, a cathode of the first diode is connected to an anode of the second diode, a cathode of the second diode is connected to an anode of the third diode, a cathode of the third diode is connected to an anode of the fourth diode, a cathode of the fourth diode is used to output an output voltage, a first end of the first capacitor is connected to a common end of the first diode and the second diode, a first end of the second capacitor is connected to a common end of the third diode and the fourth diode, a second end of the first capacitor and a second end of the second capacitor are connected to an output terminal of the adjustable voltage source; and the adjustable voltage source comprises three field effect transistors (FET) including a first FET, a second FET and a third FET, wherein a gate of the first FET is used to input a first voltage, a drain of the first FET is connected to the output terminal, and a source of the first FET is used to input a first selective voltage, a gate of the second FET is used to input a second voltage, a drain of the second FET is connected to the output terminal, and a source of the second FET is used to input a second selective voltage; and a gate of the third FET is used to input a third voltage, a drain of the third FET is connected to the output terminal, and a source of the third FET is used to input a third selective voltage wherein the first selective voltage, the second selective voltage and the third selective voltage are pulse width modulation voltages with different duty ratios; when the input voltage is not changed, one of the first to third selective voltages is selected to output the output terminal and the output voltage is different, wherein, the first capacitor and the second capacitor are non-adjustable capacitors.