US Pat. No. 10,992,306

OSCILLATION CIRCUIT AND A SELF-START-UP CONTROL CIRCUIT ADAPTABLE THERETO

Himax Technologies Limite...

1. A self-start-up control circuit adaptable to an oscillation circuit, comprising:a state circuit that generates a reset signal according to a level of a control voltage for a voltage-controlled oscillator (VCO) of the oscillation circuit; and
a start-up circuit that starts up the VCO by generating an enable signal according to the reset signal;
wherein the start-up circuit comprises:
a counter that stores a number of times specific state transition of the reset signal has occurred; and
a pulse generator that generates the enable signal with a predetermined width when the stored number of the counter is lower than or equal to a predetermined count.

US Pat. No. 10,992,305

INITIALIZATION METHOD FOR PRECISION PHASE ADDER

Blue Danube Systems, Inc....

1. A method for initializing a phase adder circuit for use with a signal distribution network having a first line carrying a first signal of a frequency fo and a second line carrying a second signal of the frequency fo, said phase adder including a multiplier circuit with a first input electrically connected to the first line of the distribution network and a second input electrically connected to the second line of the distribution network, a mixer circuit electrically connected to the multiplier circuit, an amplifier circuit, a low pass loop filter, and a voltage controlled oscillator (VCO) with an input and an output, said method comprising:during a first phase of operation, determining a reference voltage which when applied to the input of the VCO causes the VCO to produce at its output a signal having a frequency of nf0, where n is a positive integer;
during a second phase of operation, supplying a signal of frequency nfo to a first input of the mixer;
supplying a signal of frequency (nfo+?f) to a second input of the mixer, wherein n is an integer greater than zero, and ?f is a frequency that is smaller than fo; and
determining an adjustment signal which when applied to the amplifier circuit causes the amplifier circuit to output a signal having a DC component equal to the reference voltage; and
during a third phase of operation, forming a primary phase locked loop (PLL) circuit including the mixer, the amplifier circuit, the low pass loop filter and the VCO; and
applying the adjustment signal to the amplifier circuit.

US Pat. No. 10,992,303

LOW-POWER, LOW-NOISE MILLIMETER WAVELENGTH FREQUENCY SYNTHESIZER

The Regents of the Univer...

1. A system that implements a frequency synthesizer, comprising:an intermediate-frequency (IF) synthesizer that generates an IF signal based on a reference signal;
a sub-sampling phase-locked loop (SSPLL) that generates a high-frequency output signal based on an input signal;
a switch that selects either the reference signal or the IF signal to be the input signal to the SSPLL, wherein when the reference signal is the input signal to the SSPLL, the frequency synthesizer operates in a low-noise normal-operating mode in which the frequency synthesizer can become unlocked from a desired target frequency, and when the IF signal is the input signal to the SSPLL, the frequency synthesizer operates in a higher-noise, frequency-acquisition mode in which the frequency synthesizer automatically locks to the target frequency; and
a sub-sampling lock detector (SSLD), which is configured to:
determine whether the frequency synthesizer becomes unlocked from the target frequency during the normal-operating mode, and if so, to activate the switch to move the frequency synthesizer into the frequency-acquisition mode, and
determine whether the frequency synthesizer becomes relocked to the target frequency during the frequency-acquisition mode, and if so, to activate the switch to move the frequency synthesizer into the normal-operating mode.

US Pat. No. 10,992,300

OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE

SEIKO EPSON CORPORATION, ...

1. An oscillator comprising:a resonator;
a temperature control element that controls a temperature of the resonator;
a first temperature sensing element that outputs a first temperature detection signal;
a second temperature sensing element that is provided at a position farther from the resonator than the first temperature sensing element and outputs a second temperature detection signal;
an analog/digital conversion circuit that converts the first temperature detection signal into a first temperature code which is a digital signal, and converts the second temperature detection signal into a second temperature code which is a digital signal; and
a digital signal processing circuit that generates a temperature control code for controlling the temperature control element based on the first temperature code and the second temperature code, wherein
the digital signal processing circuit generates a first correction code based on the second temperature code and generates the temperature control code based on a code obtained by adding the first correction code to the first temperature code.

US Pat. No. 10,992,299

METHOD AND SYSTEM FOR PROVIDING WORD ADDRESSABLE NONVOLATILE MEMORY IN A PROGRAMMABLE LOGIC DEVICE

GOWIN Semiconductor Corpo...

1. A programmable integrated circuit device able to be selectively programmed to perform one or more logic functions, the device comprising:a plurality of configurable logic blocks (“LBs”) able to be selectively programmed to perform one or more logic functions;
a routing fabric coupled the plurality of configurable LBs and configured to selectively route information between the plurality of configurable LBs and input/output ports based on a routing configuration signals; and
a nonvolatile memory (“NVM”) coupled to the plurality of configurable LBs and configured to be flexibly organized to include a configuration NVM storage and a user NVM storage, wherein the user NVM storage is a word addressable memory organized in an array of word-wide memory storage, wherein each of the array of word-wide memory storage is accessible by a memory address operable as random memory access.

US Pat. No. 10,992,292

ELECTRONIC PERSISTENT SWITCH

ARRIS ENTERPRISES LLC, S...

7. An electrical switch that:generates a voltage pulse;
toggles a switch position at a latch in response to the voltage pulse being received at the latch, wherein the switch position is toggled from an output of a first voltage to an output of a second voltage;
outputs a current reference voltage from a programmable voltage reference element, wherein the current reference voltage comprises the second voltage; and
adjusts the current reference voltage at the programmable voltage reference element, wherein the current reference voltage is adjusted from the first voltage to the second voltage.

US Pat. No. 10,992,289

DYNAMIC FLIP FLOP AND ELECTRONIC DEVICE

DIGWISE TECHNOLOGY CORPOR...

1. A dynamic flip-flop, having an input end and an output end, and comprising:a transmission gate coupled to the input end and used to receive a first data signal, and output the first data signal to a first node according to a first clock signal and an inverted second clock signal thereof;
a first inverter coupled to the transmission gate via the first node, and used to invert the first data signal and output the inverted first data signal to a second node;
a second inverter coupled between the second node and the output end, and used to invert the inverted first data signal in order to generate a second data signal, and output the second data signal to the output end;
a pull-up transistor coupled between the second node and a power supply voltage, and used to pull up a voltage of the second node to the power supply voltage; and
a pull-down transistor coupled between the second node and a ground voltage, and used to pull down the voltage of the second node to the ground voltage;
wherein the transmission gate comprises a first N-type metal-oxide-semiconductor field-effect transistor and a first P-type metal-oxide-semiconductor field-effect transistor connected in parallel with each other, the drain of the first N-type MOS field-effect transistor and the drain of the first P-type MOS field-effect transistor are commonly coupled to the input end of the dynamic flip-flop via a third node, the source of the first N-type MOS field-effect transistor and the source of the first P-type MOS field-effect transistor are commonly coupled to the first node via a fourth node, the gate of the first N-type MOS field-effect transistor is used to receive the first clock signal, and the gate of the first P-type MOS field-effect transistor is used to receive the second clock signal;
wherein the first inverter is a tri-state inverter, and comprises a second P-type MOS field-effect transistor, a third P-type MOS field-effect transistor, a second N-type MOS field-effect transistor and a third N-type MOS field-effect transistor connected in series with each other, the source of the second P-type MOS field-effect transistor is coupled to the power supply voltage, the source of the third N-type MOS field-effect transistor is coupled to the ground voltage, the gate of the second P-type MOS field-effect transistor and the gate of the third N-type MOS field-effect transistor are respectively coupled to the first node for receiving the first data signal, the source of the third P-type MOS field-effect transistor is coupled to the drain of the second P-type MOS field-effect transistor, the source of the second N-type MOS field-effect transistor is coupled to the drain of the third N-type MOS field-effect transistor, the drain of the third P-type MOS field-effect transistor and the drain of the second N-type MOS field-effect transistor are commonly coupled to the second node via a fifth node, the gate of the third P-type MOS field-effect transistor is used to receive the first clock signal, and the gate of the second N-type MOS field-effect transistor is used to receive the second clock signal;
wherein the second inverter comprises a fourth P-type MOS field-effect transistor and a fourth N-type MOS field-effect transistor connected in series with each other, the source of the fourth P-type MOS field-effect transistor is coupled to the power supply voltage, the source of the fourth N-type MOS field-effect transistor is coupled to the ground voltage, the drain of the fourth P-type MOS field-effect transistor and the drain of the fourth N-type MOS field-effect transistor are commonly coupled to the output end of the dynamic flip-flop via a sixth node, and the gate of the fourth P-type MOS field-effect transistor and the gate of the fourth N-type MOS field-effect transistor are commonly coupled to the second node via a seventh node for receiving the inverted first data signal;
wherein the pull-up transistor is a fifth P-type MOS field-effect transistor, the pull-down transistor is a fifth N-type MOS field-effect transistor, the source of the fifth P-type MOS field-effect transistor is coupled to the power supply voltage, the source of the fifth N-type MOS field-effect transistor is coupled to the ground voltage, the drain of the fifth P-type MOS field-effect transistor and the drain of the fifth N-type MOS field-effect transistor are respectively coupled to the second node, and the gate of the fifth P-type MOS field-effect transistor and the gate of the fifth N-type MOS field-effect transistor are respectively coupled to the output end of the dynamic flip-flop for receiving the second data signal;
wherein the pull-up transistor and the pull-down transistor constitute a feedback inverter, and the feedback inverter is configured as a weak keeper circuit compared to the first inverter.

US Pat. No. 10,992,288

OSCILLATOR DEVICE

TDK Corporation, Tokyo (...

1. An oscillator device comprising:a ring oscillator circuit with at least one delay stage with an output of a last delay stage fed back to an input of a first delay stage, wherein each of the delay stages is configured to receive a charging current and to provide a delay that is dependent on the charging current and at least one of the delay stages comprises a metal-oxide-semiconductor field-effect transistor; and
a bias circuit comprising an output terminal coupled to an input terminal of the ring oscillator circuit,
wherein the bias circuit is configured to receive a temperature-independent reference voltage and comprises a current source with a main NMOS-transistor, the current source configured to provide a control current to the ring oscillator circuit which is proportional to a difference of the temperature-independent reference voltage and a gate-source voltage of the main NMOS-transistor,
wherein the gate-source voltage of the main NMOS-transistor comprises a negative temperature coefficient, and
wherein a transistor aspect ratio width/length of the main NMOS-transistor is adjusted such that the control current of the bias circuit comprises a desired positive temperature coefficient for compensating temperature-dependent delay drifts of the delay stages.

US Pat. No. 10,992,284

FILTER USING TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATORS WITH MULTIPLE FREQUENCY SETTING LAYERS

Resonant Inc., Austin, T...

1. A filter device, comprising:a substrate;
a single-crystal piezoelectric plate having front and back surfaces, the back surface attached to a surface of the substrate, portions of the single-crystal piezoelectric plate forming one or more diaphragms spanning respective cavities in the substrate;
a conductor pattern formed on the front surface, the conductor pattern including a plurality of interdigital transducers (IDTs) of a plurality of resonators, interleaved fingers of each of the plurality of IDTs disposed on a respective diaphragm of the one or more diaphragms;
a first frequency setting dielectric layer having a first thickness disposed over the fingers of the IDTs of a first subset of the plurality of resonators; and
a second frequency setting dielectric layer having a second thickness greater than the first thickness disposed over the fingers of the IDTs of a second subset of the plurality of resonators, wherein the first subset and the second subset are not identical.

US Pat. No. 10,992,283

HIGH POWER TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATORS ON ROTATED Z-CUT LITHIUM NIOBATE

Resonant Inc., Austin, T...

1. An acoustic resonator device comprising:a substrate having a surface;
a rotated Z-cut lithium niobate piezoelectric plate having front and back surfaces, the back surface attached to the surface of the substrate except for a portion of the piezoelectric plate forming a diaphragm that spans a cavity in the substrate; and
an interdigital transducer (IDT) formed on the front surface of the piezoelectric plate such that interleaved fingers of the IDT are disposed on the diaphragm, the piezoelectric plate and the IDT configured such that a radio frequency signal applied to the IDT excites a shear primary acoustic mode in the diaphragm, wherein
a thickness of the interleaved fingers of the IDT is greater than or equal to 0.85 times a thickness of the piezoelectric plate and less than or equal to 2.5 times the thickness of the piezoelectric plate.

US Pat. No. 10,992,253

COMPACTABLE POWER GENERATION ARRAYS

California Institute of T...

1. A compactable power generation array comprising:at least one structural substrate body;
an array of at least two solar concentrators resiliently connected to the at least one structural substrate body, each of the at least two solar concentrators having a plurality of structural support layers, wherein the plurality of structural support layers are layered such that they form a curved body having a front reflector surface and a back surface, and a first edge resiliently connected to the resilient connector and a second edge disposed opposite said first edge;
at least one photovoltaic cell disposed on at least a portion of the back surface of each of the solar concentrators;
at least one power transmitter electromechanically connected to the at least one photovoltaic cell and wherein the at least one power transmitter converts an electrical current generated by the at least one photovoltaic cell into a wireless signal and transmits said wireless signal;
wherein the compactable power generation array is deployable between a deployed position and a compacted positon wherein the at least one power transmitter is separated from the array of at least two solar concentrators by a gap in the deployed position and rests in a separate and parallel plane from that of the array of at least two solar concentrators;
wherein the at least two solar concentrators are deployable between a compacted configuration and a deployed configuration,
wherein in the compacted configuration the first and second edges and the curved body of each of the at least two solar concentrators are positioned parallel to the plane of the at least one structural substrate body,
and wherein in the deployed configuration the second edge and curved body of each of the at least two solar concentrators are positioned out of plane from the plane of the at least one structural substrate body;
wherein the at least two solar concentrators are placed under stress through the application of a holding force when the solar concentrator is disposed in the compacted configuration such that the at least two solar concentrators self-articulate to the deployed configuration upon removal of the holding force; and
wherein when disposed in the deployed configuration, each of the solar concentrators is configured to receive and re-direct solar radiation onto the at least one photovoltaic cell disposed on an adjacent solar concentrator.

US Pat. No. 10,992,249

POWER CONVERSION DEVICE FOR ELECTRIC VEHICLE

MITSUBISHI ELECTRIC CORPO...

1. A power conversion device for an electric vehicle comprising:an inverter to drive a motor mounted in an electric vehicle; and
a controller to control the inverter based on an operation command,
wherein the controller
includes a sensorless control unit, and
corrects an initial resistance value set in the controller, based on temperature information of a temperature sensor provided in the power conversion device or temperature information transmitted from outside of the power conversion device, sets a resistance value of the motor to the corrected initial resistance value, and causes the sensorless control unit to operate based on the set resistance value of the motor, and
the controller further includes:
a resistance estimation unit to calculate a resistance estimated value that is an estimated value of the resistance value of the motor using a current flowing to the motor; and
a resistance-value setting unit to retain the corrected initial resistance value, output the initial resistance value to the sensorless control unit until receiving the resistance estimated value from the resistance estimation unit, and output the resistance estimated value to the sensorless control unit after receiving the resistance estimated value from the resistance estimation unit, wherein
the controller includes a resistance-estimation-performing determination unit to generate a resistance-estimation performing flag when receiving the operation command as an input, and to input the flag into the resistance estimation unit and the resistance-value setting unit,
the resistance estimation unit calculates, when receiving the resistance-estimation performing flag as an input, the resistance estimated value using an electric current flowing in the motor, and
the resistance-value setting unit outputs, when receiving the resistance-estimation performing flag as an input, the initial resistance value to the sensorless control unit.

US Pat. No. 10,992,239

SINGLE-STAGE THREE-PHASE HIGH-GAIN BOOST TYPE THREE-PORT INTEGRATED INVERTER

QINGDAO UNIVERSITY, Qing...

1. A single-stage three-phase high-gain boost-type three-port integrated inverter, comprising a center-tapped energy storage inductor, an energy storage switch, a three-phase inverter bridge, and a three-phase filter; wherein the center-tapped energy storage inductor, the three-phase inverter bridge, and the three-phase filter are successively connected in cascade, a drain terminal and a source terminal of the storage switch are respectively connected to the center tap of the energy storage inductor and a negative electrode of an input DC power source; a battery charging/discharging switch unit is connected between a positive electrode of the input DC power source, a positive electrode of a battery and two ends of the center-tapped energy storage inductor; the battery charging/discharging switch unit comprises a charging subcircuit switch, a discharging subcircuit switch, and a blocking diode; an anode and a cathode of a charging subcircuit diode are respectively connected to a right end of the center-tapped energy storage inductor and a drain terminal of the charging subcircuit switch; a source terminal of the charging subcircuit switch is connected to a drain terminal of the discharging subcircuit switch and a positive electrode of the battery; a source terminal of the discharging subcircuit switch is connected to a cathode of the blocking diode and a left end of the center-tapped energy storage inductor; an anode of the blocking diode is connected to the positive electrode of the input DC power source; a negative electrode of the battery is connected to the negative electrode of the input DC power source; the blocking diode is configured to avoid a short circuit between the battery and the input DC power source circuit when the discharging subcircuit switch is turned on, and a terminal voltage Ub of the battery is greater than a voltage Ui of the input DC power source; the voltage Ui of the input DC power source or the terminal voltage Ub of the battery, a left part inductor L1 of the center-tapped energy storage inductor L, and the energy storage switch form a magnetizing loop; the voltage Ui of the input DC power source or the terminal voltage Ub of the battery, the center-tapped energy storage inductor L, one of the line-to-line voltage loops of the three-phase inverter bridge having an instantaneous value of a line-to-line voltage not less than (?6/2)Up or the charging subcircuit switch, and the battery form a demagnetizing loop; wherein Up is an RMS line-to-neutral voltage of a three-phase output; the three-phase inverter bridge comprises two-quadrant power switches configured to withstand bidirectional voltage stress and unidirectional current stress; a maximum voltage gain of the inverter is (1+dN2/N1)/(1?d), wherein, d is a duty ratio of the inverter varying according to a sine law, and N1 and N2 respectively are number of turns of a left part and a right part windings of the center-tapped energy storage inductor L; the inverter has an input port, an output port, and an intermediate port for energy storage composed of the charging/discharging switch unit of the battery; the inverter has three power supply modes including a first mode, a second mode and a third mode; in the first mode, the input DC power source supplies power to the output load and the battery; in the second mode, the input DC power source and the battery supply power to the output load; and in the third mode, the battery supplies power to the load; the first mode, the second mode and the three mode are respectively equivalent to a single-input double-output converter, a double-input single-output inverter with parallel connection and time-phased supplying power and a single-input single-output inverter; the inverter employs an energy management and control strategy including a master-slave load sharing for photovoltaic cells and the battery, a double-loop improved separate zone SPWM with an outer RMS output voltage loop of the inverter with a maximum power point tracking of the photovoltaic cells and an inner current loop of the energy storage inductor, and the inverter is configured to be switched smoothly and seamlessly among the three power supply modes.

US Pat. No. 10,992,219

POWER CONVERSION DEVICE

MITSUBISHI ELECTRIC CORPO...

1. A power conversion device comprising a plurality of cascaded converter cells,each of the converter cells including:
a first input/output node;
a second input/output node;
an energy storage device; and
a bridge circuit configured to switch between connection and disconnection between the first and second input/output nodes and the energy storage device, wherein at least one arm of a plurality of arms forming the bridge circuit includes a plurality of semiconductor switching elements connected in parallel,
wherein between the first input/output node and the second input/output node of each of the converter cells, no switch is provided other than the semiconductor switching elements forming the bridge circuit,
each of the converter cells further including:
a power supply circuit configured to generate a drive voltage based on a voltage held by the energy storage device,
a drive controller configured to operate according to the drive voltage;
a battery power supply; and
at least one latch-type switch connected between an output of the battery power supply and gates of all semiconductor switching elements provided in the at least one arm, each of the semiconductor elements provided in the at least one arm being capable of establishing a short circuit between the first input/output node and the second input/output node,
wherein when the at least one latch-type switch is turned on, the gate of each semiconductor switching element provided in the at least one arm receives a voltage for turning on the semiconductor switching element,
wherein the drive controller is configured to:
when none of a plurality of predetermined abnormality modes is detected, control the bridge circuit in accordance with an externally provided command; and
when at least one of the plurality of abnormality modes is detected, turn on the at least one latch-type switch,
wherein the plurality of abnormality modes includes a voltage of the energy storage device being outside a predetermined range.

US Pat. No. 10,992,216

LINEAR MOTOR

AAC Technologies Pte. Ltd...

1. A linear motor, comprising:a housing having a receiving space;
a vibrator received in the receiving space;
a stator received in the receiving space;
an elastic member suspending the vibrator in the housing; and
a circuit board,
wherein the housing comprises a bottom cover and a shell, the shell covers the bottom cover and encloses the receiving space together with the bottom cover,
the stator comprises an iron core fixed in the housing, a yoke sleeved on the iron core, and a first coil and a second coil that are respectively provided on two sides of the yoke, the second coil being provided between the yoke and the bottom cover,
the circuit board is fixed to the bottom cover,
the vibrator comprises a magnet spaced apart from the stator, the iron core is provided with a groove formed by recessing inwardly from a surface thereof, and a coil lead of the first coil passes through the groove to be electrically connected to the circuit board.

US Pat. No. 10,992,184

NON-CONTACT POWER RECEPTION APPARATUS FOR NON-CONTACT CHARGING AND ELECTRONIC SETTLEMENT PERFORMED IN A SINGLE PORTABLE TERMINAL

GE Hybrid Technologies, L...

1. A portable electronic device, comprising:a power reception coil configured to receive a wireless power signal and provide the wireless power signal to a power rectification unit of the portable electronic device; and
a communication antenna capable of transmitting or receiving a wireless data signal and provide the wireless data signal to a data processor of the portable electronic device, wherein the power reception coil and the communication antenna are positioned between a battery cell of the portable electronic device and one side of the portable electronic device.

US Pat. No. 10,992,180

DEVICE FOR INDUCTIVELY TRANSFERRING ELECTRICAL ENERGY AND/OR DATA, AND METHOD FOR PRODUCING SUCH A DEVICE

Balluff GmbH, Neuhausen ...

1. A device for inductively transferring electrical energy and/or data from a primary-sided carrier to at least one positionable secondary-sided recipient comprisingat least one primary-sided coil arrangement; and
at least one secondary-sided coil arrangement;
wherein the at least one primary-sided coil arrangement transfers the electrical energy and/or data to the at least one secondary-sided coil arrangement by electromagnetic induction;
wherein the at least one primary-sided coil arrangement or the at least one secondary-sided coil arrangement comprises an embroidered high frequency strand configured to carry electrical energy and/or data and with a predeterminable winding number embroidered on at least one flexible carrier so as to have meander-shaped windings with crossover regions where a first portion of the embroidered high frequency strand crosses over a second portion of the embroidered high frequency strand; and
wherein the meander-shaped windings are not embroidered in the crossover regions so as to have straight courses without punctures in the at least one flexible carrier in the crossover regions of the embroidered high frequency strand.

US Pat. No. 10,992,177

INDUCTIVELY COUPLED CHARGER

TEXAS INSTRUMENTS INCORPO...

1. A device wirelessly coupled to a charging circuit to receive an input voltage and an input current, the device comprising:a regulation switch having a control terminal, an input wirelessly coupled to the charging circuit and a battery voltage output coupled to a battery;
a charge controller having an output terminal coupled to the control terminal of the regulation switch, the charge controller operable to control the regulation switch to regulate the battery output voltage based on the input current and the battery output voltage; and
a loop controller operable to monitor the input voltage and the input current to generate a feedback signal, the loop controller wirelessly provides the feedback signal to the battery charging circuit to adjust the input voltage.

US Pat. No. 10,992,174

MONITORING CONTROL SYSTEM

Tokyo Electric Power Comp...

1. A monitoring control system that performs monitoring control of power transmission systems and power distribution systems in a plurality of areas, the monitoring control system comprising:a transmission monitoring control server that is provided in each of the areas, the system monitoring control server including a plurality of transmission monitoring control subsystems that each perform monitoring control of the power transmission system in the area;
a distribution monitoring control server that is provided in each of the areas, the distribution monitoring control server including a plurality of distribution monitoring control subsystems that each perform monitoring control of the power distribution system in the area;
a calculation server that acquires, from an external system, information on outage plan of the power distribution system and information on outage plan of the power transmission system at a predetermined cycle, and stores to manage outage plan names related to outages of the power transmission system and outages of the power distribution system generated from the acquired information by predetermined processing in a centralized manner; and
a network that connects the transmission monitoring server, the distribution monitoring server, the calculation server, and a terminal that controls transmission facilities and distribution facilities in the areas, wherein
the transmission monitoring control server, the distribution monitoring control server, and the calculation server are consolidated and provided as a server base, and
the transmission monitoring control subsystems and the distribution monitoring control subsystems each perform monitoring control of the power transmission system and the power distribution system in the areas on the basis of the outage plan name that is managed by the calculation server in a centralized manner.

US Pat. No. 10,992,163

MOBILE TERMINAL

LG ELECTRONICS INC., Seo...

1. A first mobile terminal comprising:a memory;
a display unit;
an interface unit connected to a cable through which at least one of data and power is transmitted; and
a controller configured to:
obtain a first power information including a remaining power of a battery of the first mobile terminal,
receive, through the cable, a second power information including a remaining power of a battery of a second mobile terminal,
compare the remaining power of the battery of the first mobile terminal with the remaining power of the battery of the second mobile terminal, and
transmit, through the cable, a power to the second mobile terminal if the remaining power of the battery of the first mobile terminal is greater than the remaining power of the battery of the second mobile terminal.

US Pat. No. 10,992,160

CHARGING DEVICE, CHARGING METHOD, POWER ADAPTER AND TERMINAL

GUANGDONG OPPO MOBILE TEL...

1. A charging device, comprising:a charging receiving terminal, configured to receive a first alternating current;
a first rectifier, configured to rectify the first alternating current and output a first voltage with a first pulsating waveform;
a switch unit, configured to modulate the first voltage according to a control signal to obtain a modulated first voltage;
a transformer, configured to output a plurality of voltages with pulsating waveforms according to the modulated first voltage; and
a compositing unit, configured to composite the plurality of voltages to output a second alternating current; wherein
an output end of the compositing unit is configured to be coupled to a battery such that the second alternating current is applied to the battery, and for each cycle of the second alternating current, a peak voltage of a positive half is greater than an absolute value of a valley voltage of a negative half, and the compositing unit comprises two controllable switch circuit and a control module, the control module is configured to control the two controllable switch circuit to switch on or off alternately; and
a central control module, configured to output the control signal to the switch unit so as to adjust voltage and/or current of the second alternating current outputted by the compositing unit, in response to a charging requirement of the battery.

US Pat. No. 10,992,159

ADAPTIVE CONTROL OF WIRELESS POWER TRANSFER

Massachusetts Institute o...

1. A method for wireless power transmission comprising:wirelessly transmitting power from a base station including a plurality of transmitting coils to a plurality of receivers including a corresponding plurality of receiver coils, the wireless transmission of power including adapting a plurality of driving signals for driving the transmitting coils according to a plurality of magnetic channel characteristics characterizing a plurality of magnetic channels between the transmitting coils and the receiver coils; and
without interruption of the wireless transmission of power,
inferring changes in the magnetic channels between the transmitting coils and the receiver coils, and
updating the plurality of magnetic channel characteristics according to the inferred changes in the magnetic channels between the transmitting coils and the receiver coils;
wherein the base station wirelessly transmits power simultaneously to the plurality of receivers.

US Pat. No. 10,992,158

SYSTEMS, DEVICES, AND/OR METHODS FOR MANAGING WIRELESS ELECTRICAL GRID LOCATION OR PERSONAL AREA NETWORK (WIGL) ENERGY

1. A multi point power charger comprising:a converter that is configured to convert electrical energy having an alternating current to a direct current;
a base band processor configured to receive direct current electrical energy from the converter and output a plurality of energy streams;
a radio frequency processor, configured to receive the plurality of energy streams from the base band processor and output phase shifted energy streams; and
a multidirectional antenna array configured to receive the phase shifted energy streams from the radio frequency processor, the multidirectional antenna array comprising a plurality of transducers, the plurality of transducers arranged in a regular pattern that are configured to emit a plurality of directional beams; and
a wireless electrical grid router coupled to the multi point power charger, the wireless electrical grid router configured to receive energy from the multi point power charger and packs the energy into packets, wherein energy packets are returned to the multi point power charger and routed to devices in at least one of the plurality of directional beams based on quality of service parameters defined by a user;
wherein, the multi point power charger is coupleable to an electrical energy source, the multi point power charger configured to emit the plurality of directional beams, wherein each of the plurality of directional beams is directable toward a determined direction of an electronic device, the multi point power charger configured to wirelessly charge or wirelessly power the electronic device, wherein the multi point power charger is configured to:
via an inertia measurement unit, determine a location of the electronic device;
direct the at least one of the plurality of directional beams toward the determined location of the electronic device;
automatically update the location of the electronic device;
redirect the at least one of the plurality of directional beams toward the updated location of the electronic device.

US Pat. No. 10,992,156

AUTONOMOUS SCREENING AND OPTIMIZATION OF BATTERY FORMATION AND CYCLING PROCEDURES

The Board of Trustees of ...

1. A method of optimizing charging policies for battery cell formation or cycling, the method comprising:a) defining a parameter space for a plurality of battery cells being optimized for lifetime;
b) specifying hyperparameters, wherein said hyperparameters comprise resource hyperparameters, parameter space hyperparameters, and algorithm hyperparameters;
c) selecting a subset of said charging policies, including repetitions of policies, wherein said charging policies include one or more charging rates;
d) testing said subset of said charging policies on the plurality of battery cells being optimized, using a battery cycling instrument, until a number of cycles required for accurate lifetime prediction is achieved;
e) employing an optimal experimental design (OED) algorithm to obtain recommendations for running at least one next test;
f) iteratively seeking a lifetime-optimized charging policy according to said hyperparameters by running said recommended tests by repeating c)-e) above one or more times using closed-loop lab testing; and
g) providing the lifetime-optimized charging policy as an output.

US Pat. No. 10,992,149

SAFE BATTERY ENERGY MANAGEMENT SYSTEMS, BATTERY MANAGEMENT SYSTEM NODES, AND METHODS

Element Energy, Inc., Sa...

1. A method for safe operation of an energy storage system including a plurality of battery management system nodes that are electrically coupled together, comprising:receiving, at a first battery management system node of the plurality of battery management system nodes, a safety signal indicating that a first battery of the first battery management system node is at risk of an unsafe failure; and
in response to receiving the safety signal at the first battery management system node operating the first battery management system node to cause a controlled discharge of the first battery, such that the first battery is discharged to a lower state of charge than a second battery of a second battery management system node of the plurality of battery management system nodes.

US Pat. No. 10,992,147

DIAGNOSTIC METHOD FOR ELECTRIC PROPULSION SYSTEM WITH RECONFIGURABLE BATTERY SYSTEM

GM Global Technology Oper...

14. A method for use with an electric propulsion system having a rotary electric machine and a reconfigurable battery system connected to a direct current (“DC”) voltage bus, the battery system having multiple battery modules, the method comprising:in response to a transition from a parallel-connected (“P-connected”) configuration of the battery system to a series-connected (“S-connected”) configuration prior of the battery system during a direct current fast charging (“DCFC”) operation of the battery system, determining, via a controller, measured values for each of a positive bus rail voltage of a positive bus rail, a negative bus rail voltage of the negative bus rail, and a mid-bus voltage between the positive bus rail and the negative bus rail;
calculating, via the controller, expected values of each of the first bus rail voltage, the second bus rail voltage, and the mid-bus voltage;
identifying an electrical condition of the electric propulsion system, as a diagnosed condition, from among a plurality of possible electrical conditions by comparing the measured values of the first and second bus rail voltages and the mid-bus voltage to the expected values of the first and second bus rail voltages and the mid-bus voltage, respectively; and
executing a control action in response to the diagnosed electrical condition, including recording a diagnostic code in memory of the controller that is indicative of the diagnosed electrical condition.

US Pat. No. 10,992,146

METHODS AND APPARATUS FOR CONTROLLING CHARGE CURRENT IN A BATTERY PACK CONTAINING CELLS OF DISPARATE TYPES

Motorola Solutions, Inc.,...

1. A battery pack for an electronic device, comprising:one or more battery cells of a first cell type electrically connected between positive and negative terminals of the battery pack, each battery cell of the first cell type having a first impedance and a first charge current limit;
one or more battery cells of a second cell type electrically connected between the positive and negative terminals of the battery pack in parallel with the one or more battery cells of the first cell type, each battery cell of the second cell type having a second impedance greater than the first impedance and a second charge current limit greater than the first charge current limit; and
a respective current control circuit electrically connected in series with each of the one or more battery cells of the first cell type and configured to, during an operation to charge the one or more battery cells of the first cell type and the one or more battery cells of the second cell type at the same time, reduce a charge current through the battery cell of the first cell type below the first charge current limit.

US Pat. No. 10,992,144

BATTERY BALANCING AND CURRENT CONTROL WITH BYPASS CIRCUIT FOR LOAD SWITCH

Galley Power LLC, Hudson...

1. A circuit comprising:a bypass circuit connected to a terminal of a battery and connected in parallel with a load switch, the bypass circuit configured to selectively direct a bypass current around the load switch; and
a controller configured to: 1) in a first mode, control at least one parameter of the bypass current based on at least one reference value corresponding to thermal stress of the battery, the at least one reference value being based on a recorded usage history of charging currents and discharging currents of the battery over a period of time, and 2) in a second mode, control the bypass circuit to disable the bypass current.

US Pat. No. 10,992,140

ELECTRICAL POWER DISTRIBUTION ASSEMBLY FOR AN AIRCRAFT

1. An airplane comprising:an electrical power distribution assembly for an airplane, the electrical power distribution assembly comprising
a primary electric switch device located in a Kaman fairing of the airplane, the Karman fairing including an aerodynamic bulge situated at a junction between a wing of the airplane and a fuselage of the airplane, an interior volume of the Karman fairing being not pressurized, the primary electric switch device receiving power from a jet of the airplane via a first cable, the primary electric switch including contactors and a circuit breaker and providing power to a first load provided in proximity to the wing of the airplane, and
a secondary electric switch device disposed in the fuselage of the airplane and electrically connected to the primary electric switch device via a second cable so as to receive power from the primary electric switch device, the secondary electric switch device including a circuit breaker and providing power to a second load provided in the fuselage of the airplane,
wherein a venturi tube causes air to leak from the cabin into the Karman fairing so that a temperature inside the Karman fairing does not drop below a threshold temperature,
wherein a grid made of electrically conductive material is positioned so as to reduce an electromagnetic field in the Karman fairing, and
wherein the contactors of the primary electric switch device are reinforced and proof against water runoff.

US Pat. No. 10,992,139

ELECTRICAL POWER SYSTEM

1. An electrical power system, comprising:a photovoltaic panel, configured to generate electrical power from a solar source;
an output source, electrically coupled to the photovoltaic panel with a first maximum power point tracking charge controller; wherein the output source is at least one battery
an inverter, electrically coupled to the photovoltaic panel with a second maximum power point tracking charge controller;
a bi-directional buck/boost converter, electrically coupled to the first maximum power point charge controller and the second maximum power point charge controller;
a microcontroller operatively coupled to the bi-directional buck/boost converter wherein the microcontroller is programmed with instructions to:
determine a photovoltaic panel current coming in from the photovoltaic panel;
providing impedance matched coupling for the photovoltaic panel, the output source, and the inverter;
direct an output source current to the output source;
direct an inverter current to the inverter;
engage an output source charging cycle;
adjust an impedance presented to the photovoltaic panel by the output source;
adjust an impedance presented to the photovoltaic panel by the inverter; and
operate as a current sink.

US Pat. No. 10,992,138

MASTERLESS DISTRIBUTED POWER TRANSFER CONTROL

Cummins Power Generation ...

1. An automatic transfer switch structured to be coupled to a first power source and a second power source, comprising:one or more controller circuits configured to:
determine an assignment of priorities for each of a plurality of power sources coupled through a distribution system, wherein the priorities establish a hierarchy of the power sources for supplying power to a load;
obtain information indicating an availability of each of the plurality of power sources and determine a set of available power sources from among the plurality of power sources based on the information;
identify a preferred power source and a standby power source from the plurality of power sources based on the priorities and the information, wherein the preferred power source and the standby power source are among the set of available power sources, and wherein the priority of the preferred power source is higher than the priority of the standby power source;
determine to change the preferred power source from the first power source to the second power source in response to detecting a condition; and
a switching device configured to:
transfer power between the first power source and the second power source in response to determining to change the preferred power source to the second power source.

US Pat. No. 10,992,134

LOAD SHEDDING SYSTEM FOR BOTH ACTIVE AND REACTIVE POWER BASED ON SYSTEM PERTURBATION

Schweitzer Engineering La...

1. A non-transitory computer readable medium comprising instructions that, when executed by a processor, cause operations comprising:receiving electrical measurements of a power system prior to a contingency;
detecting the contingency in the power system;
receiving electrical measurements of the power system following the contingency;
determining perturbation of active power and perturbation of reactive power in the power system using the electrical measurements prior to the contingency and the electrical measurements following the contingency in linearized perturbation-based power flow equations of the power system; and
sending a signal to cause one or more sheddable loads of the power system to be shed due to the contingency based on the perturbation of the active power and the perturbation of reactive power to satisfy user defined system frequency and voltage requirements without requiring measurements from nonsheddable loads.

US Pat. No. 10,992,129

GROUND FAULT PROTECTION METHODS

GE ENERGY POWER CONVERSIO...

1. A ground fault protection method for a power distribution system comprising a plurality of power converter systems electrically connected to a point of common coupling, each power converter system including a power converter with a plurality of semiconductor switching devices controlled using a pulse width modulation strategy with a switching frequency, the method comprising:applying a spectrum analysis process to each power converter system that uses measured or derived zero sequence currents associated with the respective power converter system to determine the location of a ground fault within the power distribution system, and
applying a switching frequency process where the switching frequency of the power converter of at least one of the power converter systems is different from the switching frequency of the power converter of at least another one of the power converter systems during at least part of the time that the spectrum analysis process is applied,
wherein the power converters are operated continuously at different fixed switching frequencies during normal operation and during a ground fault condition.

US Pat. No. 10,992,128

BATTERY REVERSE VOLTAGE PREVENTION SYSTEM AND METHOD

LG CHEM, LTD., Seoul (KR...

1. A battery reverse voltage prevention system, the system comprising:a first metal oxide silicon field effect transistor (MOSFET) connecting a battery and a load and blocking a reverse voltage applied from the battery;
a resistor unit of which one side is connected with a gate terminal of the first MOSFET and the other side is connected with a ground terminal; and
a second MOSFET connected with the resistor unit in parallel,
wherein when constant voltage is applied to the second MOSFET, the second MOSFET is turned on and current of the battery, which flows to the resistor unit, is reduced to decrease an opening/closing delay time of the first MOSFET, and
wherein the first and second MOSFETs are P-type channel MOSFETs.

US Pat. No. 10,992,127

ELECTRONIC CONTROL UNIT

Hitachi Automotive System...

1. An electronic control unit comprising:a load unit configured to operate with a current supplied via a power-supply input terminal from a battery;
a reverse connection protection element arranged on a power supply path connecting the power-supply input terminal with the load unit and configured to prevent a reverse current when the battery is reversely connected to the power-supply input terminal; and
a current-abnormality detecting unit configured to detect an abnormality of a current flowing through the reverse connection protection element based on a voltage difference between a voltage on the power-supply input terminal side of the reverse connection protection element and a voltage on the load unit side, wherein
the reverse connection protection element is constituted by a first diode having an anode side connected to the power-supply input terminal side and a cathode side connected to the load side, and
the current-abnormality detecting until includes a second diode having an anode side connected to the power-supply input terminal side of the reverse connection protection element, and detects an abnormality of a current flowing through the reverse connection protection element based on a voltage difference between a voltage on a cathode side of the second diode through which a predetermined constant current flows and a voltage on the load unit side of the first diode.

US Pat. No. 10,992,126

CIRCUIT INTERRUPTER INSTALLATION AND ASSOCIATED METHOD

EATON INTELLIGENT POWER L...

1. A method comprising:in a circuit interrupter installation having a plurality of poles, a neutral conductor, and an Electronic Trip Unit (ETU), determining:
that a plurality of fundamental frequency phase current vectors are, when summed, substantially equal to a fundamental frequency neutral current vector, and
that a plurality of triplen odd-numbered harmonic phase current vectors are, when summed, substantially equal to a triplen odd-numbered neutral current vector; and
responsive to the determining, performing at least one of:
outputting a notification that is representative of a possibility that one of the neutral conductor and a neutral current sensor is wired backward in the circuit interrupter installation, and
employing with the ETU a reverse vector that is an opposite of the fundamental frequency neutral current vector.

US Pat. No. 10,992,120

SIDEWALL CLOSEOUT AREA ASSEMBLY, SYSTEM, AND METHOD FOR ROUTING CONDUCTIVE ELEMENTS IN AN AIRCRAFT

The Boeing Company, Chic...

1. A sidewall closeout area assembly for an aircraft, the sidewall closeout area assembly comprising:a raceway having a first end, a second end, and a raceway body formed between the first end and the second end, wherein:
the first end of the raceway is configured to attach to a bottom portion of a sidewall assembly configured for installation in a cabin of the aircraft;
the second end of the raceway is configured to attach to one or more aircraft floor structures; and
the raceway body has a first side configured to face an interior frame of the aircraft, and the raceway body comprises one or more first access openings providing access to one or more of, a crown area and an underfloor area, in the aircraft, for a plurality of conductive elements routed along the raceway;
a raceway cover removably coupled to the raceway, the raceway cover having a first cover side facing a second side of the raceway body, and having a second cover side configured to face an interior of the cabin, the raceway cover comprising one or more second access openings providing access to the cabin and access to an overfloor area in the cabin for the plurality of conductive elements routed along the raceway; and
a closeout area formed between the raceway body and the raceway cover, the closeout area configured to house and protect the plurality of conductive elements routed along the raceway,
wherein the sidewall closeout area assembly facilitates accessibility to the plurality of conductive elements, and provides a routing path for the plurality of conductive elements that does not need to be reconfigured for different aircraft cabin layouts.

US Pat. No. 10,992,119

ELECTRIC SPINNING PLIERS

1. Electric spinning pliers, comprising:a housing;
a plier head coupled to a rotatable shaft, the rotatable shaft extending longitudinally through the housing;
an electric motor within the housing configured to rotate the rotatable shaft;
a head-operating handle configured to open the plier head, the head-operating handle remaining stationary when the plier head rotates on the rotatable shaft; and
at least one bearing coupled to the rotatable shaft, the at least one bearing coupling the head-operating handle to the plier head.

US Pat. No. 10,992,116

FLEXIBLE ELECTRICAL ISOLATION DEVICE

Quanta Associates, L.P., ...

1. Method for assembling an isolation link, the method steps comprising:(a) mounting a flexible membrane having opposite first and second ends around an elongate dielectric flexible member having a plurality of strands and first and second ends, wherein the first end of the flexible member protrudes from the first end of the flexible membrane and the second end of the flexible member protrudes from the second end of the flexible membrane,
(b) mounting a first sealing assembly to the first end of the flexible membrane and a second sealing assembly to the second end of the flexible membrane so as to fluidically seal the first and second ends of the flexible membrane, wherein said first and second sealing assemblies' are adapted to couple to a corresponding socket, each said socket having a bore, and wherein each said bore has an interior surface, a narrow opening and an opposite wide opening, wherein the narrow openings of the sockets are adjacent their respective sealing assembly of said first and second sealing assemblies,
(c) coupling the narrow opening of the first socket to the first sealing assembly and the narrow opening of the second socket to the second sealing assembly,
(d) mounting the first socket to the first end of the flexible member so that the flexible member extends into the bore of the first socket, and mounting the second socket to the second end of the flexible member so that the flexible member extends into the bore of the second socket,
(e) brooming the first and second ends of the flexible member so as to form corresponding first and second broomed strands of the flexible member within the bores of the first and second sockets respectively,
(f) inserting a liquid fixing agent into the first and second broomed strands and the bores of the first and second sockets, so as to substantially fill voids between the rope strands of the first and second broomed strands and between the first and second broomed strands and the inner surface of the bore, and so that the liquid fixing agent is uniformly infiltrated into the narrow ends of the first and second sockets,
(g) then curing the liquid fixing agent to secure the first and second broomed strands within the first and second bores respectively,
(h) mounting a first coupler to the wide end of the first socket and a second coupler to the wide end of the second socket, and
(i) filling the flexible membrane with dielectric fluid so as to displace any air within the flexible membrane and flexible member.

US Pat. No. 10,992,114

SYSTEMS AND METHODS FOR USING DYNAMIC MATERIALS IN NO-POWER ACTUATION OF TELECOMMUNICATIONS MAINTENANCE HARDWARE

Verizon Patent and Licens...

1. An apparatus, comprising:a flap;
an actuation apparatus, at least partially coupled to the flap, that is capable of actuating the flap from an open position to a closed position, with respect to a particular surface, wherein the actuation apparatus includes:
a self-actuating material responsive to heat, wherein the self-actuating material is capable of maintaining a first shape state or a different second shape state based on how much heat is applied to the self-actuating material,
wherein the first state shape causes the flap, affixed to the actuation apparatus, to be closed with respect to the particular surface, and
wherein the second state shape causes the flap, affixed to the actuation apparatus, to be open with respect to the particular surface; and
one or more actuator arms that do not include the self-actuating material that is responsive to heat,
wherein the one or more actuator arms include at least a first actuator arm and a second actuator arm separated by, and coupled to, a hinge that includes the self-actuating material.

US Pat. No. 10,992,108

GENERATION OF HIGH-POWER SPATIALLY-RESTRUCTURABLE SPECTRALLY-TUNABLE BEAMS IN A MULTI-ARM-CAVITY VECSEL-BASED LASER SYSTEM

Arizona Board of Regents ...

1. A laser source comprising:a laser cavity network including first and second spatially-distinct cavity arms and a collinear portion, wherein the first and second spatially-distinct cavity arms share the collinear portion,
at least one of the first and second cavity arms containing, intracavity,
a corresponding gain medium that includes one of (i) a VECSEL-based laser gain medium, (ii) a solid-state gain medium, and (iii) a fiber amplifier, and that is configured to provide amplification of light at a corresponding wavelength;
and
at least one of a first optical system, disposed across an axis of the at least one of the first and second cavity arms to either refract or reflect light incident thereon while transforming a transverse distribution of said light that has traversed said at least one of the first and second cavity arms, and
a second optical system, disposed across said axis between the corresponding gain medium and the collinear portion and characterized by optical losses at the corresponding wavelength;
wherein said laser source is configured to maintain, in operation, intracavity generation of light at the corresponding wavelength, said light having:
a) a first transverse mode distribution in a first portion of the laser cavity network between the corresponding gain medium and the second optical system,
b) a second transverse mode distribution in a second portion of the laser cavity network between the second optical system and the collinear portion, and
c) a third transverse mode distribution in a third portion of the laser cavity network, the third portion being a remaining portion of the laser cavity network;
wherein the first and third transverse mode distributions are different from one another.

US Pat. No. 10,992,106

METHOD FOR GENERATING SINGLE PICOSECOND OPTICAL PULSES WITH SUBSTANTIALLY SUPPRESSED TRANSIENT EMISSION TAIL IN SEMICONDUCTOR DIODE LASER

UNM Rainforest Innovation...

1. A method for generating single optical pulses of picosecond-range duration with suppressed transient emission tails in response to applying unipolar or bipolar injection-current pulses of picosecond-range duration to a semiconductor diode laser comprising: generating a sequence of picosecond-range unipolar or bipolar current pulses and applying said sequence of current pulses to a pre-biased semiconductor diode laser so that a first positive injection current pulse enables the semiconductor diode laser to generate a single optical output pulse, whereas the closing positive current pulse suppresses generation of a transient emission tail; wherein said semiconductor diode laser is a ring semiconductor diode laser.

US Pat. No. 10,992,100

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:forming a first reflective structure on a substrate, the first reflective structure comprising first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant;
forming an emitting semiconductor region on the first reflective structure;
forming a second reflective structure on the emitting semiconductor region, the second reflective structure comprising second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant;
depositing a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure;
depositing a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure;
forming a conductive connector on the bonding layer;
reflowing the conductive connector;
after reflowing the conductive connector, forming an isolation material around the conductive connector, the first reflective structure, the emitting semiconductor region, and the second reflective structure;
after forming the isolation material, forming a conductive via through the isolation material; and
connecting the conductive via to the first reflective structure.

US Pat. No. 10,992,097

APPARATUS AND METHOD FOR AN OPTICAL RESONATOR WITH AN INTEGRATED BRAGG GRATING

Honeywell International I...

1. A gyroscope, comprising:a first laser configured to generate a first laser pump signal;
an optical resonator comprising a waveguide, including Brillouin gain material, on a substrate and coupled to the first laser;
wherein the optical resonator has resonant frequencies substantially equal to a frequency of an optical signal configured to be coupled into the optical resonator and to a frequency of at least one Stokes signal, where each of the at least one Stokes signal has an order equal to or less than N-1, and where each of the at least one Stokes signal is configured to be generated by the Brillouin gain material;
a Bragg grating with periodic notches that are on parallel sides, of the waveguide, which are perpendicular to the substrate;
wherein the Bragg grating has a Bragg frequency substantially equal to the center frequency of the Nth order Stokes signal;
an input axis parallel to a center axis of the optical resonator;
wherein the first laser pump signal generates a first order Stokes signal in the optical resonator that propagates in an opposite direction, around the optical resonator, of the first laser pump signal;
a first photodetector coupled to the optical resonator;
a second photodetector coupled to the optical resonator and configured to generate a first signal in response to a first portion of the first pump signal coupled out of the optical resonator;
wherein the first photodetector is configured to generate a first beat signal in response to a first Stokes signal, corresponding to the first pump signal, which is coupled out of the optical resonator and a second portion of the first pump signal;
resonance tracking servo system circuitry coupled to the first laser and the second photodetector;
processing system circuitry coupled to the first photodetector;
wherein the resonance tracking servo system circuitry is configured to alter the frequency of the first laser pump signal based upon the first signal; and
wherein the processing system circuitry is configured to generate data representative of an angular rotation rate around the input axis based upon the first beat signal.

US Pat. No. 10,992,096

FIBER ENCAPSULATION MECHANISM FOR ENERGY DISSIPATION IN A FIBER AMPLIFYING SYSTEM

Waymo LLC, Mountain View...

1. A multi-stage optical fiber amplifier, comprising:a preamplifying stage, comprising:
a first optical fiber comprising a gain medium; and
a first pump source arranged to optically pump the first optical fiber, wherein optically pumping the first optical fiber amplifies optical signals in a wavelength range transmitted through the gain medium of the first optical fiber; and
a booster amplifying stage, comprising:
a second optical fiber comprising a gain medium, wherein the second optical fiber is optically coupled to the first optical fiber and arranged to receive optical signals from the first optical fiber;
a polymer layer that at least partially surrounds the second optical fiber, wherein the polymer layer is optically transparent;
a second pump source arranged to optically pump the second optical fiber, wherein optically pumping the second optical fiber amplifies optical signals in the wavelength range transmitted through the gain medium of the second optical fiber and generates excess heat and excess photons;
a heatsink layer disposed adjacent to the polymer layer, wherein the heatsink layer conducts the excess heat away from the second optical fiber; and
an optically transparent layer disposed adjacent to the polymer layer opposite the heatsink layer, wherein the optically transparent layer transmits the excess photons away from the second optical fiber.

US Pat. No. 10,992,089

SAFETY SOCKET OUTLET

1. A multiple socket comprising a housing, a power supply component and connections for safety plugs, with the respective connections and safety plugs being dimensionally matched to each other, with the socket comprisingat least one flexible cover for the connections with accesses for the contact pins of safety plugs, wherein the accesses are provided in the form of slots which expand when the contact pins of a safety plug are inserted,
a cover plate which is arranged underneath and connected to the cover or covers, with apertures for the contact pins of a safety plug being provided in said cover plate,
an insert arranged in the housing for a current conductor, a neutral conductor and a ground conductor, wherein the contacts of the current conductor, the neutral conductor and the ground conductor each being connected with one another via rails, being arranged in separate retaining elements and being accessible for the contact pins of a safety plug through the flexible cover and the cover plate, and
an on/off switch connected to the power conductor;
wherein the cover plate is designed so as to form the upper retaining element for the insert, with a lower retaining element being arranged at the bottom of the housing.

US Pat. No. 10,992,086

HIGH PERFORMANCE CABLE TERMINATION

Amphenol Corporation, Wa...

1. An electrical termination comprising:a conductive ground shield enclosing, at least in part, an end of a flexible cable; and
a conductive, compressible member disposed between, and in electrical contact with, the end of the cable and the conductive ground shield, the conductive, compressible member being molded to the conductive ground shield, wherein the conductive, compressible member comprises an elastomer and a plurality of conductive particulates embedded in the elastomer.

US Pat. No. 10,992,083

COMMUNICATION HARNESS, COMMUNICATION HARNESS SET, AND RELAY CONNECTOR

PANASONIC INTELLECTUAL PR...

1. A communication harness set for mutual data transmission by differential transmission between at least two electronic devices via a relay connector, the communication harness set comprising:a first communication harness; and
a second communication harness,
wherein each of the first communication harness and the second communication harness includes:
a cable;
a first signal line which is covered with the cable, and through which a first signal for differential transmission is transmitted;
a second signal line which is covered with the cable, and through which a second signal for differential transmission is transmitted; and
a first ground line covered with the cable,
wherein a supply voltage is superposed on the first signal line,
the first signal line of the first communication harness is electrically connected to the first signal line of the second communication harness via the relay connector,
the second signal line of the first communication harness is electrically connected to the second signal line of the second communication harness via the relay connector, and
the first ground line of the first communication harness is electrically isolated from the first ground line of the second communication harness by the relay connector.

US Pat. No. 10,992,078

CONNECTION SYSTEM FOR ESTABLISHING AN ELECTRICAL CONNECTION THROUGH A DRAPE AND METHODS THEREOF

Bard Access Systems, Inc....

1. A connection system for establishing one or more electrical connections through a drape, the connection system comprising:a first connector including:
an alignment protrusion; and
a first piercing element having one or more electrical contacts, the first piercing element configured to pierce the drape; and
a second connector including:
an alignment notch configured to accept the alignment protrusion;
a channel along a length of the second connector configured to allow the alignment protrusion to slide along the channel, wherein:
the alignment notch is positioned above the channel, and
alignment of the alignment protrusion of the first connector with the alignment notch of the second connector enables movement of the alignment protrusion down through the alignment notch and into the channel; and
a first receptacle having one or more electrical contacts configured to form at least a first electrical connection of the one or more electrical connections with the first connector when the first piercing element is inserted in the first receptacle.

US Pat. No. 10,992,073

ELECTRICAL TERMINAL ASSEMBLY WITH INCREASED CONTACT AREA

Lear Corporation, Southf...

1. An electrical terminal assembly comprising:a contact member including a contact base having contact arms that extend from the contact base in an arm direction and are arranged on opposite sides of a terminal plane; and
a spring member supported on the contact member including a spring base, spring arms that extend from the spring base in the arm direction on opposite sides of the terminal plane into engagement with the contact arms at respective spring contacts, and a shroud that is connected to the spring base and extends around the contact arms and beyond the contact arms in the arm direction, the shroud including:
an end shield that is located in the arm direction beyond the contact arms,
side shields located on opposite sides of the contact arms that connect the end shield to the spring base,
shield arms that connect the end shield to the spring base, and
terminal guides that extend from the end shield in the arm direction and toward the terminal plane, wherein the terminal guides are spaced apart from each other to define crenels between adjacent terminal guides.

US Pat. No. 10,992,067

CONNECTION DEVICE FOR CONNECTION OF AN ELECTRICAL LINE

1. A connection device for connection of an electrical conductor, comprising:a housing which has an insertion opening for insertion of an electrical conductor;
a spring element arranged on the housing, which spring element has a spring leg configured to lock the conductor inserted in the insertion opening; and
an adjusting element which is arranged adjustably on the housing,
wherein by adjustment of the adjusting element, the spring leg is movable between a clamping position in which the conductor inserted in the insertion opening is lockable in the insertion opening, and a release position in which the conductor may be inserted into the insertion opening, or the conductor inserted in the insertion opening is releasable from the insertion opening,
wherein the spring element has an actuation section arranged on the spring leg, on which the adjusting element is configured to act during an adjustment for the movement of the spring leg, and on which a support section is formed, which is configured to bear against the spring leg at a support point when the spring leg is moved.

US Pat. No. 10,992,064

MOBILE DEVICE

WISTRON CORP., New Taipe...

1. A mobile device, comprising:a WLAN (Wireless Local Area Network) module, having a first port, a second port, and a first control port;
a WWAN (Wireless Wide Area Network) module, having a third port, a fourth port, a fifth port, and a sixth port;
a first antenna element, coupled to the third port;
a second antenna element;
a first switch element, coupling the second antenna element to the first port or the fourth port according to a first control signal;
a third antenna element;
a second switch element, coupling the third antenna element to the second port or the fifth port according to a second control signal;
a fourth antenna element, coupled to the sixth port;
wherein the first control port is arranged for outputting a WLAN state signal;
wherein the first control signal and the second control signal are determined according to at least the WLAN state signal;
wherein the mobile device further comprises:
an embedded controller, configured to generate the first control signal and the second control signal;
wherein the WWAN module further has a third control port for outputting an antenna control signal, and the embedded controller determines the first control signal and the second control signal according to the WLAN state signal and the antenna control signal;
wherein if the antenna control signal has a low logic level, the WWAN module is operating in a small MIMO (Multi-Input and Multi-Output) mode, and if the antenna control signal has a high logic level, the WWAN module is operating in a large MIMO mode.

US Pat. No. 10,992,061

ELEMENTARY ANTENNA COMPRISING AMPLIFICATION CHAINS FOR DELIVERING SIGNALS TO AND AMPLIFYING SIGNALS ARISING FROM A PLANAR RADIATING DEVICE THEREOF

THALES, Courbevoie (FR) ...

1. An elementary antenna comprising a planar radiating device comprising a substantially plane radiating element and at least one of a transmit circuit and a receive circuit comprising at least one amplification chain of a first type and at least one amplification chain of a second type,each amplification chain of the first type being coupled to at least one excitation point of a first set of at least one excitation point of the substantially plane radiating element and each amplification chain of the second type being coupled to at least one point of a second set of excitation points of the substantially plane radiating element,
the excitation points of the first set and the second set being distinct and the amplification chain of the first type being different from the amplification chain of the second type so that they exhibit different amplification properties,
wherein the excitation points of the first set and of the second set exhibit distinct impedances.

US Pat. No. 10,992,049

ELLIPTICALLY POLARIZED CAVITY BACKED WIDEBAND SLOT ANTENNA

Nokia Shanghai Bell Co., ...

1. An antenna comprising:a cavity backed slot antenna portion having positioned therein a coupling device comprising at least one of a probe antenna, exciter or radiator configured to provide radio frequency excitation for the antenna; and,
a planar log periodic parasitic dipole portion positioned in spaced relation to the cavity backed slot antenna portion, wherein the cavity backed slot antenna portion and the planar log periodic parasitic dipole portion are configured to produce elliptically polarized radiation patterns.

US Pat. No. 10,992,048

DEVICE AND METHOD FOR COMBINED SIGNAL TRANSMISSION OR FOR COMBINED SIGNAL TRANSMISSION AND ENERGY TRANSMISSION

MOLEX CVS DABENDORF GMBH,...

1. A device for combined signal transmission or for combined signal and energy transmission, the device comprising:at least one winding structure for generating a first electromagnetic field for transmitting energy or for transmitting signals to a wireless communication device, said at least one winding structure having a central axis being a symmetrical axis of said winding structure;
at least one antenna structure for transmitting further signals, said antenna structure having a first part structure and a second part structure, said first part structure being disposed opposite said second part structure such that signals can be received and transmitted in a first frequency range by way of said at least one antenna structure, said first part structure and said second part structure being galvanically separate from one another, said first part structure including a tapering part and said second part structure including a tapering part, said tapering part of said first part structure and said tapering part of said second part structure tapering towards one another;
wherein at least one selected part structure selected from the group consisting of said first part structure and said second part structure of said antenna structure comprises a blind conductor structure that extends perpendicular to an axis that connects said first part structure and said second part structure, and wherein said blind conductor structure is formed on a face of said selected part structure that lies opposite a tapering face of said selected part structure;
wherein said first part structure is arranged adjacent said at least one winding structure in a projection plane that is oriented perpendicular to said central axis of said at least one winding structure; and
a damping structure for damping the first electromagnetic field, said damping structure overlapping at least in part said at least one winding structure in the projection plane.

US Pat. No. 10,992,046

LOW PROFILE HIGH GAIN DUAL POLARIZATION UHF/VHF ANTENNA

BAE Systems Information a...

1. A UHF/VHF antenna, comprising: a dual polarization spiral antenna located a distance above a ground plane, the spiral antenna having spiral sections with arms attached to the spiral sections; one or more resistors grounding the spiral sections and arms; a cavity being located under the spiral antenna and below the ground plane; at least one feed attached to the spiral antenna; wherein the distance above the ground plane is about two inches or less than 1/10 wavelength at a high frequency of operation;wherein each of the arms comprise a plurality of rectangular sections;
and wherein the plurality of rectangular sections have resistors coupled in series electrically coupling the rectangular sections.

US Pat. No. 10,992,041

DUAL-FREQUENCY FEED SOURCE ASSEMBLY AND DUAL-FREQUENCY MICROWAVE ANTENNA

ROSENBERGER TECHNOLOGIES ...

1. A dual-frequency feed-source module, comprising:a first waveguide;
a second waveguide coaxially positioned inside of the first waveguide; and
a secondary reflector, wherein the secondary reflector is attached to a terminal opening outside of the first waveguide,
wherein the first waveguide and the second waveguide share the secondary reflector, and the secondary reflector receives and emits microwave energy through a primary reflector.

US Pat. No. 10,992,036

PORTABLE COMMUNICATION DEVICE AND ANTENNA DEVICE WITH REMOVEABLE MATCHING CIRCUIT

MOTOROLA SOLUTIONS, INC.,...

1. An antenna device comprising:a base;
an antenna element;
an electrical connector at the base;
a matching circuit removably positioned between the electrical connector and the antenna element, the electrical connector and the antenna element in electrical communication via the matching circuit; and
a metal shell removably attached to the base, the metal shell surrounding and protecting the matching circuit,
wherein the base comprises threads that extend towards the matching circuit, and the metal shell comprises complementary threads that removably mate with the threads of the base, the metal shell being removably attached to the base via the complementary threads and the threads of the base, and
wherein the metal shell is formed from metal, the metal shell being electrically isolated from the antenna element, the electrical connector and the matching circuit.

US Pat. No. 10,992,023

ELECTRONIC DEVICE INCLUDING ANTENNA

Samsung Electronics Co., ...

1. An electronic device, comprising: a housing comprising:a front plate facing a first direction,
a back plate facing a second direction opposite to the first direction, and
a side surface which surrounds the front plate and the back plate,
wherein the front plate includes a screen area and a bezel area;
a display exposed through the screen area of the front plate;
a first circuit board disposed between the display and the back plate and including a first surface facing to the display and a second surface facing to the back plate;
a first antenna array overlaid on the bezel area in the first surface;
a second antenna array disposed on the second surface;
a wireless communication circuit disposed on the first circuit board and electrically connected with the first antenna array and the second antenna array,
a second circuit board disposed facing to the side surface between the display and the back plate and connected to the first circuit board; and
a third antenna array disposed on the second circuit board and electrically connected with the wireless communication circuit,
wherein the wireless communication circuit is configured to:
form a first beam which has directionality in the first direction using the first antenna array, form a second beam which has directionality in the second direction using the second antenna array, and form a third beam which has directionality in a third direction orthogonal to the first direction and the second direction, using the third antenna array.

US Pat. No. 10,992,022

MICROWAVE ANTENNA APPARATUS, PACKING AND MANUFACTURING METHOD

SONY CORPORATION, Tokyo ...

1. Microwave antenna apparatus comprising:a mold layer of mold material,
a semiconductor element comprising a semiconductor unit and semiconductor feed lines on a first surface of the semiconductor unit, wherein the semiconductor element is within the mold layer such that an outer surface of the semiconductor feed lines is not covered by mold material,
an antenna element comprising an antenna substrate layer and a ground layer, wherein the antenna element is within the mold layer, and
a redistribution layer comprising at least one redistribution substrate layer and a metal layer, wherein the redistribution layer is on a surface of the mold layer such that the metal layer is in contact with the outer surface of one or more semiconductor feed lines, wherein
a radiating element is either on a surface of the antenna substrate layer facing away from the redistribution layer or within or on the redistribution layer, and
the ground layer is on a surface of the antenna substrate layer facing the redistribution layer, on a surface of the antenna substrate layer facing away from the redistribution layer, or within the antenna substrate layer, wherein the antenna element comprises one or more connection lines connecting the metal layer or the ground layer on the surface of the antenna substrate layer facing the redistribution layer with the radiating element on the surface of the antenna substrate layer facing away from the redistribution layer through the antenna substrate layer.

US Pat. No. 10,992,021

CROSS TALK AND INTERFERENCE REDUCTION FOR HIGH FREQUENCY WIRELESS INTERCONNECTS

Intel Corporation, Santa...

1. A packaged device, comprising:a first package substrate mounted to a printed circuit board (PCB);
a plurality of first antennas formed on the first package;
a second package substrate mounted to the PCB;
a second plurality of antennas formed on the second package; and
a guiding structure formed between the first and second packages, wherein the guiding structure comprises a plurality of fins that define a plurality of pathways between the first antennas and the second antennas.

US Pat. No. 10,992,019

POWER DIVIDING CIRCUIT AND POWER DIVIDER

NANNING FUGUI PRECISION I...

1. A power divider comprising:a substrate,
a power dividing circuit, the power dividing circuit positioned on the substrate, the power dividing circuit comprising:
an input port;
a first output port;
a second output port;
an impedance converter;
a first microstrip line, wherein an end of the first microstrip line is connected to the impedance converter, another end of the first microstrip line is connected to the first output port; and
a second microstrip line, wherein an end of the second microstrip line is connected to the impedance converter, another end of the second microstrip line is connected the second output port,
wherein the impedance converter comprises a third microstrip line and a fourth microstrip line, an end of the third microstrip line is connected to the input port, and another end of the third microstrip line is connected to the first microstrip line and the second microstrip line, an end of the fourth microstrip line is connected between the input port and the third microstrip line, and another other end of the fourth microstrip line is in an open state;
wherein each of the first microstrip line and the second microstrip line has an impedance of 50 ohms and an electrical length of 90 degrees; each of the third microstrip line and the fourth microstrip line has an impedance of 50 ohms and an electrical length of 35.26 degrees.

US Pat. No. 10,992,018

COAXIAL-WAVEGUIDE-TO-HOLLOW- WAVEGUIDE TRANSITION CIRCUIT

MITSUBISHI ELECTRIC CORPO...

1. A coaxial-waveguide-to-hollow-waveguide transition circuit, comprising:a hollow waveguide having a pair of long sides facing each other and a pair of short sides facing each other in a cross section perpendicular to a waveguide-axis direction thereof, the hollow waveguide having, as inner walls, a pair of wide walls forming the pair of long sides and a pair of narrow walls forming the pair of short sides;
at least one coaxial waveguide located outside the hollow waveguide and having an end coupled to one wide wall of the pair of wide walls; and
a strip conductor located inside an internal path of the hollow waveguide, wherein
the hollow waveguide has a termination surface in one end of the hollow waveguide in the waveguide-axis direction,
the at least one coaxial waveguide includes at least one conducting core wire extending from the end of the at least one coaxial waveguide into the internal path of the hollow waveguide, and
the strip conductor makes a short-circuit connection between the at least one conducting core wire and at least one of the termination surface and at least one narrow wall of the pair of narrow walls, and includes a first connection end connected to the at least one conducting core wire, and a second connection end connected to either the termination surface or the at least one narrow wall, wherein a length of the strip conductor between the first connection end and the second connection end is equal to an odd multiple of a quarter of a wavelength of a high-frequency signal in the strip conductor.

US Pat. No. 10,992,011

BATTERY MODULE, BATTERY PACK INCLUDING BATTERY MODULE, AND VEHICLE INCLUDING BATTERY PACK

LG CHEM, LTD., Seoul (KR...

1. A battery module, comprising:a plurality of battery cells;
a cell housing configured to accommodate the plurality of battery cells, the cell housing having an upper edge; and
a cover housing configured to cover an upper side of the cell housing,
wherein the cover housing includes:
an upper cover configured to form an upper portion of the cover housing;
a lower cover coupled to the upper cover and disposed at the upper edge of the cell housing; and
a bus bar disposed between the lower cover and the upper cover, electrically connected to electrodes of the plurality of battery cells, and sealing-coupled to at least one of the upper cover and the lower cover,
wherein the lower cover is between the upper edge of the cell housing and a lower surface of the upper cover.

US Pat. No. 10,992,009

NONAQUEOUS ELECTROLYTE BATTERY SEPARATOR AND NONAQUEOUS ELECTROLYTE BATTERY

Toray Industries, Inc.

1. A nonaqueous electrolyte battery separator comprising:a porous film (I) containing a polyolefin resin; and
a porous layer (II) containing an inorganic filler, a water-soluble polymer having a structure represented by general formula (1), a water-insoluble polymer selected from the group consisting of styrene resins, styrene-butadiene rubber, acrylic resins, polyalkylene oxides and fluororesins, and
a basic compound, wherein the basic compound is at least one compound selected from the group consisting of an alkali metal compound, a quaternary ammonium compound having 1 to 20 carbon atoms, and an aliphatic tertiary amine having 1 to 20 carbon atoms:
wherein:R1 and R2 each independently represent a hydroxyl group, a carboxyl group or a sulfonic acid group;
R3 and R4 each independently represent a halogen, a nitro group or a monovalent organic group having 1 to 10 carbon atoms;
a and b each independently represent an integer of 1 or more;
c and d each independently represent an integer of 0 or more, provided that a+c and b+d each independently represent an integer of 1 to 4;
n1 represents an integer of 0 to 3; and
X1 represents a single bond, CH2, SO2, CO, 0, S, C(CH3)2 or C(CF3)2;wherein the basic compound is present in an amount of 0.2 to 4 mole equivalents based on acidic groups in the water-soluble polymer, andwherein the nonaqueous electrolyte battery separator has a thermal shrinkage ratio of 5% or less when heated at 160° C. for 1 hour and 5% or less when heated at 200° C. for 1 hour.

US Pat. No. 10,992,001

ENERGY DISTRIBUTION SYSTEM

1. An energy distribution system, comprising:a housing defining a cavity having a rear terminal with an open end opposite of a front terminal;
an inlet unit disposed in the housing at a rear end thereof wherein the inlet comprises a pair of opposing pistons disposed in a pair of opposing wells;
wherein the inlet unit is in fluid communication with the rear terminal;
a first pair of opposing magnets embedded in the pair of opposing pistons;
a pressurized gas disposed in a pair of airtight chambers formed by the pair of opposing pistons and the pair of opposing wells;
a reservoir disposed in the housing between the inlet and a second pair of opposing magnets;
the reservoir comprising an air ionizer configured to ionize air passing through a tunnel therethrough;
the second pair of opposing magnets disposed in the housing between the reservoir and a capacitor; and
the capacitor disposed in the cavity between the second pair of opposing magnets and the front terminal.

US Pat. No. 10,991,996

BATTERY HEAT EXCHANGE SYSTEM

CONTEMPORARY AMPEREX TECH...

1. A battery heat exchange system, comprising a liquid feeding mechanism, a heat exchange mechanism and a liquid draining mechanism;wherein
the liquid feeding mechanism provides a circulating liquid;
the heat exchange mechanism is connected with the liquid feeding mechanism and comprises a plurality of heat exchange units and a plurality of connecting units; each heat exchange unit is used to heat or cool a corresponding battery module, and the plurality of connecting units are used to connect the heat exchange units together;
the liquid draining mechanism is connected with the heat exchange mechanism, and the circulating liquid provided by the liquid feeding mechanism flows through the heat exchange mechanism and then is drained from the liquid draining mechanism;
each heat exchange unit comprises a plurality of liquid cooling pipes used to heat or cool the battery modules; and two liquid collecting pipes provided at two ends of the plurality of liquid cooling pipes and connected to the plurality of liquid cooling pipes; and
one of the liquid collecting pipes comprises a connecting piece and a liquid collector, the connecting piece has a plurality of through-holes connected to the liquid cooling pipes respectively, and a flow channel is formed between the connecting piece and the liquid collector for flow of liquid.

US Pat. No. 10,991,992

SYSTEM FOR SUPPLYING POWER TO A PORTABLE BATTERY USING AT LEAST ONE SOLAR PANEL

LAT Enterprises, Inc., R...

1. A system for charging a portable battery pack comprising:the portable battery pack including one or more batteries enclosed in a wearable pouch;
wherein the one or more batteries include:
at least one battery element;
a battery cover including one or more channels to accommodate wires of one or more flexible omnidirectional leads and a compartment sized to receive the at least one battery element;
a battery back plate attached to the battery cover; and
the one or more flexible omnidirectional leads including a connector portion and a wiring portion, wherein a flexible spring is provided around the wiring portion, wherein the wiring portion and the flexible spring are held securely in the one or more channels in the battery cover such that a portion of the flexible spring is positioned inside the battery cover and a portion of the flexible spring is positioned outside the battery cover;
wherein the wearable pouch includes one or more openings through which the one or more flexible omnidirectional leads from the one or more batteries can be accessed; and
wherein the one or more flexible omnidirectional leads are operable to charge at least one of the one or more batteries.

US Pat. No. 10,991,990

LOW PROFILE SENSOR AND ELECTROCHEMICAL CELL INCLUDING SAME

Robert Bosch Battery Syst...

1. An electrochemical cell, comprising a single positive electrode that forms a first portion of an outer surface of the cell and provides a positive cell terminal,a single negative electrode that forms a second portion of an outer surface of the cell and provides a negative cell terminal,
a separator that is disposed between the positive electrode and the negative electrode, wherein the positive electrode, the negative electrode and the separator are arranged in a stacked configuration,
a sealing material layer that connects and forms a seal between a peripheral edge of the positive electrode and a peripheral edge of the negative electrode, and
a sensor device including circuit board and an electronic device that is supported on the circuit board, the electronic device including a sensor and a conmunication device,
wherein
the sensor device is in physical contact with, and electrically connected to, one of the positive electrode and the negative electrode,
at least a first portion of the sensor device is disposed outside the cell,
the sensor device includes a second portion that includes an electrically conductive sensor contact pad that is electrically connected to the sensor, and
the second portion of the sensor device is disposed on an outer surface of the cell.

US Pat. No. 10,991,988

BATTERY PACK, AND BATTERY SYSTEM COMPRISING THE SAME

OMRON CORPORATION, Kyoto...

1. A battery system, comprising:a battery pack that is charged by a charger, comprising:
an input component to which current and voltage are applied from the charger;
a current and voltage measurement component configured to measure the current and voltage inputted to the input component;
an improper charge detector configured to determine whether charging occurs via an improper charging method by comparing a measurement result from the current and voltage measurement component with a reference measurement result corresponding to charging applied by a designated charger;
a storage component configured to store the measurement result, comprising a current value or a voltage value measured by the current and voltage measurement component, and the reference measurement result corresponding to the charging applied by the designated charger; and
the designated charger, comprising an improper charge detector configured to:
receive the measurement result from the storage component of the battery pack;
compare the received measurement result and a second reference measurement result corresponding to charging applied with a specific designated charger; and
determine whether charging occurs via an improper charging method, based on the comparison, wherein
the improper charge detector performs waveform analysis or frequency analysis on the basis of the measurement result from the current and voltage measurement component.

US Pat. No. 10,991,983

NONAQUEOUS ELECTROLYTIC SOLUTION AND NONAQUEOUS ELECTROLYTIC SOLUTION SECONDARY BATTERY

Central Glass Company Lim...

1. A nonaqueous electrolytic solution for nonaqueous electrolytic solution secondary batteries, the nonaqueous electrolytic solution comprising:a nonaqueous solvent,
an electrolyte dissolved in the nonaqueous solvent,
(I) a difluoro ionic complex (1) represented by the general formula (1), and
(II) at least one compound selected from the group consisting of a difluorophosphate salt, a monofluorophosphate salt, a salt having an imide anion represented by each of the general formulas (II-1) to (II-8) below, and a silane compound represented by the general formula (II-9) below,
wherein 95 mol % or more of the difluoro ionic complex (1) is a difluoro ionic complex (1-Cis) in a cis configuration represented by the general formula (1-Cis),

wherein in (1-Cis),

wherein in the general formula (1) and the general formula (1-Cis),
A+ is any one selected from the group consisting of a metal ion, a proton, and an onium ion, and M is any one selected from the group consisting of Si, P, As, and Sb;
F is a fluorine atom; 0 is an oxygen atom;
t is 2 when M is Si, and t is 1 when M is P, As, or Sb;
X is an oxygen atom or —N(R1)—; N is a nitrogen atom; and R1 is a hydrocarbon group having 1 to 10 carbon atoms and optionally having a hetero atom and/or a halogen atom (the hydrocarbon group optionally having a branched-chain or ring structure when the number of carbon atoms is 3 or more);
when X is —N(R1)—, and p is 0, X and W are bonded directly and optionally form a structure as shown in at least one selected from the general formulas (1-Cis-1) to (1-Cis-3) below; in the case of the general formula (1-Cis-2) below where the direct bond is a double bond, R1 is not present,
Y is a carbon atom or a sulfur atom; q is 1 when Y is a carbon atom; q is 1 or 2 when Y is a sulfur atom;
W represents a hydrocarbon group having 1 to 10 carbon atoms and optionally having a hetero atom and/or a halogen atom (the hydrocarbon group optionally having a branched-chain or ring structure when the number of carbon atoms is 3 or more), or —N(R2)—; wherein,R2 represents a hydrogen atom, an alkaline metal, or a hydrocarbon group having 1 to 10 carbon atoms and optionally having a hetero atom and/or a halogen atom; when the number of carbon atoms is 3 or more, R2 optionally has a branched-chain or ring structure;p is 0 or 1, q is an integer of 0 to 2, r is an integer of 0 to 2, and further, p+r?1,

wherein
in the general formulas (II-1) to (II-8), R3 and R14 are each independently a fluorine atom or an organic group selected from a straight chain or branched alkoxy group having 1 to 10 carbon atoms, an alkenyloxy group, an alkynyloxy group, a cycloalkoxy group having 3 to 10 carbon atoms, a cycloalkenyloxy group, and an aryloxy group having 6 to 10 carbon atoms, and at least one of a fluorine atom, an oxygen atom, and an unsaturated bond is optionally present in the organic group; Z1 and Z5 are each independently a fluorine atom or an organic group selected from a straight chain or branched alkyl group having 1 to 10 carbon atoms, an alkenyl group, an alkynyl group, a cycloalkyl group having 3 to 10 carbon atoms, a cycloalkenyl group, an aryl group having 6 to 10 carbon atoms, a straight chain or branched alkoxy group having 1 to 10 carbon atoms, an alkenyloxy group, an alkynyloxy group, a cycloalkoxy group having 3 to 10 carbon atoms, a cycloalkenyloxy group, and an aryloxy group having 6 to 10 carbon atoms, and at least one of a fluorine atom, an oxygen atom, and an unsaturated bond is optionally present in the organic group; n1 represents an integer of 1 to 8; and B+, C+, and D+ each independently represent any one selected from the group consisting of a metal ion, a proton, and an onium ion, and C+ and D+ are optionally identical; and
in the general formula (II-9), R15 each independently represent a group having a carbon-carbon unsaturated bond; R16 are each independently selected from a fluorine atom and a straight chain or branched alkyl group having 1 to 10 carbon atoms, and the alkyl group optionally has a fluorine atom and/or an oxygen atom; and a is 2 to 4.

US Pat. No. 10,991,982

ELECTROLYTE-ADDITIVE FOR LITHIUM-ION BATTERY SYSTEMS

1. An electrolyte for an electrochemical energy store comprising an electrolyte salt and a solvent, characterized in that the electrolyte comprises at least one compound of the general formula (1) as indicated below:
where:
X is C, S or S?O;
R1 is selected from the group consisting of CN, C1-C10-alkyl, C1-C10-alkoxy, C3-C7-cycloalkyl, C6-C10-aryl, —CO—O—R2 and combinations thereof, wherein the alkyl, alkoxy, cycloalkyl and aryl groups are each unsubstituted or monosubstituted or polysubstituted by at least one substituent selected from the group consisting of F, C1-4-alkyl, CN and mixtures thereof; and
R2 is selected from the group consisting of C1-C10-alkyl, C3-C7-cycloalkyl, C6-C10-aryl and mixtures thereof.

US Pat. No. 10,991,981

NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

PANASONIC INTELLECTUAL PR...

1. A non-aqueous electrolyte secondary battery comprising:a positive electrode including a positive electrode active material that comprises a Ni-containing lithium composite oxide as a main component;
a negative electrode; and
a non-aqueous electrolyte;
wherein the non-aqueous electrolyte includes:
a non-aqueous solvent including a fluorine-containing cyclic carbonate;
an isocyanuric acid derivative represented by the formula below:

wherein R1 to R3 are each independently —CnH2n—CH?CH2 or hydrogen, provided that at least one of R1 to R3 is —CnH2n—CH?CH2; and n is an integer; and
a cyclic carboxylic anhydride represented by the formula below:

wherein R4 to R7 are each independently hydrogen, an alkyl group, an alkene group, or an aryl group.

US Pat. No. 10,991,979

ELECTROLYTIC SOLUTION, BATTERY, BATTERY PACK, ELECTRONIC DEVICE, ELECTRIC VEHICLE, ELECTRICAL STORAGE DEVICE, AND ELECTRIC POWER SYSTEM

Murata Manufacturing Co.,...

1. A battery comprising:a positive electrode, a negative electrode and an electrolyte,
wherein the electrolyte includes a first compound represented by formula (1) and a second compound represented by formula (2) being contained in the battery:
[formula 1]
X?CR1R2?l?CF2?m?CR3R4?n  (1)
(wherein X represents a hydrogen group, a fluorine group, a vinyl group, an ethynyl group or combinations thereof; Y represents a vinyl group or an ethynyl group; R1, R2, R3 and R4 independently represent a hydrogen group, an alkyl group having 1 to 4 carbon atoms, an alkenyl group having 1 to 4 carbon atoms, an alkynyl group having 1 to 4 carbon atoms or combinations thereof, and wherein each of the alkyl group, the alkenyl group and the alkynyl group includes a first substituent; and wherein 1 represents an integer of 0 to 16; m represents an integer of 1 to 18; and n represents an integer of 0 to 16);

(wherein R5 an R6 independently represent an alkyl group having 1 to 18 carbon atoms, an alkenyl group having 1 to 18 carbon atoms, an alkynyl group having 1 to 18 carbon atoms, an alkylene group having 2 to 18 carbon atoms, an alkenylene group having 2 to 18 carbon atoms, an alkynylene group having 2 to 18 carbon atoms or combinations thereof, wherein each of the alkyl group, the alkenyl group, the alkynyl group, the alkylene group, the alkenylene group and the alkynylene group includes a second substituent, a cyclic structure, a branched structure, or combinations thereof; and wherein Z represents a linking group selected from oxygen (O), sulfur (S), nitrogen (N), phosphorus (P), SO2, and combinations thereof; p represents an integer of 0 to 2; q represents a numerical value obtained by subtracting 1 from a numerical value of a valency of Z; r represents an integer of 0 or more; s represents a numerical value obtained by subtracting 1 from a numerical value of a valency of R6; and t represents a numerical value obtained by subtracting 1 from a numerical value of a valency of R5).

US Pat. No. 10,991,966

DOPED POLYMER ELECTROLYTES AND METHODS OF MAKING AND USING THE SAME

Triad National Security, ...

1. A polymer electrolyte, comprising:a cationic-functionalized polymer comprising a polymer and least one cationic functional group, wherein the polymer is selected from a polyaryl polymer, a polyarylamide, a polyimide, a polystyrene, a polysulfone, a polyether, a polyether sulfone, a polyketone, a polyetherketone, a polyarylether, a polyolefin, or a polynitrile, and wherein the at least one cationic functional group (CFG) is selected from ammonium [—NH3+,
imidazoliumguanidiniumphosphazeniumsulfonium [sulfoniumoxoniumpiperidiniumpyridiniumquinoliniumand phosphoniumwherein R1, R2, and R3 are independently hydrogen, aliphatic, aryl, or heteroaryl; anda polyacid dopant having a structure satisfying a formula R—[PO(OH)2]n or R—[S(O)2OH]n wherein R comprises an aliphatic or aromatic group and n is an integer selected from 2 to 4.

US Pat. No. 10,991,964

FUEL CELL SYSTEM AND METHOD OF CONTROLLING THE SAME

Hyundai Motor Company, S...

1. A method of controlling a fuel cell system, comprising:selecting, by a controller, a first control parameter;
learning, by the controller, system efficiency at each of at least one configurable candidate value of the first selected control parameter based on supplied current by driving the fuel cell system; and
determining, by the controller, a value of the first selected control parameter by comparing the system efficiency at each of the at least one configurable candidate value of the selected control parameter with system efficiency corresponding to an initial performance index, at each of at least one predetermined representative current point,
wherein the determination of the value of the first selected control parameter further includes calculating, by the controller, a base of life (BOL) efficiency difference at each of the at least one predetermined current point.

US Pat. No. 10,991,960

ELECTROLYTE STORAGE TANK, FLOW BATTERY, BOX-TYPE FLOW BATTERY SYSTEM AND CHARGE-DISCHARGE CONTROL METHOD OF FLOW BATTERY

DALIAN RONGKEPOWER CO., L...

1. An electrolyte storage tank provided with an electrolyte return inlet and an electrolyte delivery outlet, whereina circular pipe I and a circular pipe II are provided inside the electrolyte storage tank;
the circular pipe II is in communication with the electrolyte return inlet;
the circular pipe I is in communication with the electrolyte delivery outlet;
the annular perimeter of the circular pipe I is not equal to the annular perimeter of the circular pipe II;
a plurality of liquid holes are formed in walls of both of the circular pipe I and the circular pipe II.

US Pat. No. 10,991,943

NICKEL ACTIVE MATERIAL PRECURSOR FOR LITHIUM SECONDARY BATTERY, METHOD FOR PRODUCING NICKEL ACTIVE MATERIAL PRECURSOR, NICKEL ACTIVE MATERIAL FOR LITHIUM SECONDARY BATTERY PRODUCED BY METHOD, AND LITHIUM SECONDARY BATTERY HAVING CATHODE CONTAINING NICKEL

Samsung SDI Co., Ltd., Y...

1. A nickel-based active material precursor for a lithium secondary battery, comprising a core, an intermediate layer located on the core, and a shell located on the intermediate layer,wherein porosity gradually decreases in the order of the core, the intermediate layer, and the shell, and
each of the intermediate layer and the shell has a radial arrangement structure.

US Pat. No. 10,991,939

NEGATIVE ACTIVE MATERIAL FOR RECHARGEABLE LITHIUM BATTERY AND RECHARGEABLE LITHIUM BATTERY INCLUDING SAME

SAMSUNG SDI CO., LTD., Y...

1. A negative active material for a rechargeable lithium battery, the negative active material comprising:a silicon-carbon composite including crystalline carbon and a silicon particle,
wherein:
the silicon-carbon composite further includes an alkali metal or an alkaline-earth metal, and
the alkali metal or the alkaline-earth metal is present in the silicon-carbon composite in an amount of greater than 1,000 ppm and less than about 5,000 ppm by weight.

US Pat. No. 10,991,935

STRUCTURAL LITHIUM-ION BATTERIES WITH CARBON FIBER ELECTRODES

The MITRE Corporation, M...

1. A structural battery for a device comprising:one or more carbon fiber-reinforced polymer electrodes comprising two or more carbon fiber sheets, one or more metallic tabs, and a polymer, and
a liquid electrolyte,
wherein the structural battery is molded into a shape of a functional component of a device.

US Pat. No. 10,991,931

ENERGY STORAGE APPARATUS

GS YUASA INTERNATIONAL, L...

1. An energy storage apparatus, comprising:an energy storage device which includes an electrode terminal;
an outer case; and
an external connection terminal,
wherein the external connection terminal includes:
an external connection part to be connected to an external conductive member;
a circuit breaking part; and
a bus bar which connects the electrode terminal or the external connection part with the circuit breaking part, and which is formed inside the outer case and has an insert-molded structure such that the bus bar is integrally formed with the outer case,
wherein the bus bar includes an outer exposed portion on which the circuit breaking part is detachably mounted from an outside of the outer case,
wherein the outer case includes:
a body which accommodates the energy storage device; and
a lid body which covers an opening of the body and inside which the bus bar is formed by insert molding,
wherein the outer exposed portion is exposed from the lid body, and
wherein the bus bar is disposed inside the lid body.

US Pat. No. 10,991,927

SEPARATOR AND ENERGY STORAGE DEVICE

Ningde Amperex Technology...

1. A separator, comprising:a first porous substrate; and
a second porous substrate arranged on at least one surface of the first porous substrate;
wherein the elongation at break of the second porous substrate is greater than the elongation at break of the first porous substrate in at least one of machine and transverse directions of the separator,
wherein the second porous substrate has a tensile strength of 150 kgf/cm2 or more in the machine and the transverse directions.

US Pat. No. 10,991,921

BATTERIES COMPRISING A MULTILAYER DIELECTRIC AND SEALING FILM AND METHOD OF MAKING THE BATTERIES

BRIGHTVOLT, INC., Lakela...

1. A battery comprising:a battery cell having a periphery, the battery cell comprising an anode, a cathode and an electrolyte between the anode and cathode;
an anode tab comprising a first portion in electrical contact with the anode and a second portion extending beyond the periphery of the cell and/or a cathode tab comprising a first portion in electrical contact with the cathode and a second portion extending beyond the periphery of the cell;
an upper packaging layer and a lower packaging layer surrounding the battery cell, wherein the upper and lower packaging layers are sealed together to form a seal area in a periphery of the battery cell and wherein the anode and/or cathode tabs extend between the upper and lower packaging materials in the seal area; and
a multi-layer dielectric sealing film between the anode and/or cathode tabs and the upper packaging material in the seal area, wherein the multi-layer dielectric sealing film comprises a layer of dielectric material and a first layer of sealing material.

US Pat. No. 10,991,919

METHOD AND APPARATUS FOR MANUFACTURING FLEXIBLE LIGHT EMITTING DEVICE

SAKAI DISPLAY PRODUCTS CO...

1. A method for producing a flexible light-emitting device, comprising:providing a multilayer stack which has a first surface and a second surface, the multilayer stack including
a glass base which defines the first surface,
a functional layer region including a TFT layer and a light-emitting device layer,
a synthetic resin film provided between the glass base and the functional layer region and bound to the glass base, the synthetic resin film including a flexible substrate region supporting the functional layer region and an intermediate region surrounding the flexible substrate region, and
a protection sheet which covers the functional layer region and which defines the second surface;
dividing the intermediate region and the flexible substrate region of the synthetic resin film from each other;
irradiating an interface between the synthetic resin film and the glass base with lift-off light; and
separating the multilayer stack into a first portion and a second portion by increasing a distance from a stage to the glass base while the second surface of the multilayer stack is kept in contact with the stage,
wherein the first portion of the multilayer stack includes a light-emitting device which is in contact with the stage, the light-emitting device including the functional layer region and the flexible substrate region of the synthetic resin film,
the second portion of the multilayer stack includes the glass base and the intermediate region of the synthetic resin film, and
irradiating the interface between the synthetic resin film and the glass base with the lift-off light includes;
forming the lift-off light from a plurality of arranged light sources and temporally and spatially modulating a power of the plurality of light sources according to a shape of the flexible substrate region of the synthetic resin film;
reducing an irradiation intensity of the lift-off light for at least part of an interface between the intermediate region of the synthetic resin film and the glass base below a threshold level of the irradiation intensity which is necessary for delamination;
irradiating the at least part of the interface between the intermediate region of the synthetic resin film and the glass base with the lift-off light,
irradiating the interface between the flexible substrate region of the synthetic resin film and the glass base with the lift-off light whose irradiation intensity is higher than threshold level,
wherein, after separating the multilayer stack into the first portion and the second portion, performing a process on the light-emitting device which is in contact with the stage, and
the process includes attaching a dielectric and/or electrically-conductive film to the light-emitting device, cleaning or etching the plurality of light-emitting device, and mounting an optical part and/or an electronic part to the light-emitting device.

US Pat. No. 10,991,911

PACKAGE STRUCTURE, PACKAGING METHOD AND ELECTRONIC DEVICE

WUHAN CHINA STAR OPTOELEC...

1. A packaging method, comprising the following steps:providing a substrate, sequentially forming a base layer, an inorganic film layer, an OLED layer and a first barrier layer on the substrate;
forming a buffer layer on the first barrier layer by using an inkjet printing process, wherein the buffer layer is doped with a modified epoxy acrylate;
irradiating the buffer layer and the first barrier layer with UV light so that the modified epoxy acrylate reacts with the first barrier layer to adhere the buffer layer to the first barrier layer;
wherein the buffer layer comprises a first surface in contact with the first barrier layer and a second surface opposite to the first surface, in fabricating the buffer layer, the ink jet printing process is used for a plurality of times so that a basic layer is formed each time, the modified epoxy acrylate doped during ink jet printing is sequentially reduced so that a concentration of the modified epoxy acrylate in the buffer layer gradually decreases in a direction of the first surface toward the second surface.

US Pat. No. 10,991,863

LIGHT-EMITTING DIODE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

KAISTAR LIGHTING(XIAMEN) ...

1. A light-emitting diode package structure, comprising:a first substrate including a light-emitting region and a welding region defined thereon and including a load circuit configured in the light-emitting region;
a second substrate including a control region defined thereon and a driving circuit configured in the control region, wherein the first substrate and the second substrate are spaced apart from each other, and the welding region is located at a side of the light-emitting region that is farther away from the second substrate;
a light-emitting module disposed on the first substrate and electrically connected to the load circuit; and
a driving module disposed on the second substrate and electrically connected to the driving circuit, wherein the driving module is electrically connected to the light-emitting module.

US Pat. No. 10,991,862

LIGHT-EMITTING DIODE PACKAGES

CreeLED, Inc., Newark, C...

1. A light-emitting diode (LED) package comprising:a submount;
a metal pattern on the submount, wherein the metal pattern comprises:
a metal trace;
at least one die attach pad that includes a first portion of the metal trace; and
at least one bond pad formed by a second portion of the metal trace, wherein a third portion of the metal trace is continuous between the first portion of the metal trace and the second portion of the metal trace;
at least one LED chip mounted on the at least one die attach pad;
a bond metal on the second portion of the metal trace, and on a surface of the submount that is adjacent the second portion of the metal trace, wherein the bond metal only partially covers the third portion of the metal trace; and
a light-altering material arranged around a perimeter of the at least one LED chip on the surface of the submount, wherein the light-altering material covers a portion of the bond metal on the surface of the submount, and the at least one bond pad is uncovered by the light-altering material.

US Pat. No. 10,991,859

LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME

NICHIA CORPORATION, Anan...

1. A light-emitting device comprising:at least one light-emitting element having an upper surface and at least one lateral surface;
a first light-transmissive member bonded to the upper surface of the light-emitting element, the first light-transmissive member containing a wavelength conversion member and including:
an upper surface,
at least one lateral surface, and
a lower surface having an area larger than an area of the upper surface of the light-emitting element and having a periphery located outward of the upper surface of the light-emitting element;
a second light-transmissive member bonded to the upper surface of the first light-transmissive member and including:
a lower surface having an area larger than an area of the upper surface of the first light-transmissive member and having a periphery located outward of the upper surface of the first light-transmissive member, and
an upper surface having an area smaller than an area of the upper surface of the light-emitting element;
a first light-guiding member disposed over the at least one lateral surface of the light-emitting element and the periphery of the lower surface of the first light-transmissive member;
a second light-guiding member disposed over the at least one lateral surface of the first light-transmissive member and the periphery of the lower surface of the second light-transmissive member, and
a light-reflective member covering the at least one lateral surface of the first light-guiding member, at least one lateral surface of the second light-guiding member, and at least one lateral surface of the second light-transmissive member.

US Pat. No. 10,991,857

METHOD OF FABRICATING LIGHT EMITTING DEVICE PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A method of fabricating a light emitting device package comprising in sequence:(1) forming a plurality of semiconductor light emitting parts above a growth substrate, each having a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer vertically stacked on the growth substrate;
(2) after forming the plurality of semiconductor light emitting parts, and after the plurality of semiconductor light emitting parts are moved to be disposed below the growth substrate, forming a partition structure having a plurality of light emitting windows in the growth substrate, the partition structure including partitions formed of a portion of the growth substrate, and each partition formed between two adjacent semiconductor light emitting parts of the plurality of semiconductor light emitting parts in a plan view; and
(3) after forming the partition structure and while the plurality of light emitting parts are disposed below the growth substrate:
filling a resin having a wavelength conversion material into each of the plurality of light emitting windows; and
forming a plurality of wavelength conversion parts by planarizing a surface of the resin.

US Pat. No. 10,991,826

SEMICONDUCTOR DEVICE AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A device comprising:a fin protruding from a substrate;
a gate stack extending over and along sidewalls of the fin;
a gate spacer extending along a sidewall of the gate stack;
a recess in the fin adjacent the gate spacer; and
a source/drain region in the recess, comprising:
a first doped silicon layer lining the recess, the first doped silicon layer comprising a germanium dopant and a first n-type dopant; and
second doped silicon layer on the first doped silicon layer, the second doped silicon layer comprising a second n-type dopant that is different from the first n-type dopant, wherein a portion of the second doped silicon layer is free of the first n-type dopant, and wherein the first doped silicon layer extends between the second doped silicon layer and the fin.

US Pat. No. 10,991,823

FABRICATION OF VERTICAL FIN TRANSISTOR WITH MULTIPLE THRESHOLD VOLTAGES

INTERNATIONAL BUSINESS MA...

16. A method of fabricating a pair of vertical fin field effect transistors, comprising:forming a shallow trench isolation region in a single-crystal silicon substrate;
forming a hardmask layer on the single-crystal silicon substrate and the shallow trench isolation region, wherein the shallow trench isolation region is below the hardmask layer;
forming a first trench in the hardmask layer on one side of the shallow trench isolation region, and a second trench in the hardmask layer on the opposite side of the shallow trench isolation region from the first trench;
forming a silicon-germanium fin material in the first trench and the second trench, wherein the silicon-germanium fin material extends above a top surface of the hardmask layer;
forming a capped portion over the first trench;
oxidizing the silicon-germanium fin material to form a silicon oxide layer, a graded fin material over the second trench, and a modified vertical fin having an upper portion with an increased germanium concentration in the second trench;
removing the capped portion and silicon oxide layer; and
removing the silicon-germanium fin material and graded fin material.

US Pat. No. 10,991,808

STEEP-SWITCH FIELD EFFECT TRANSISTOR WITH INTEGRATED BI-STABLE RESISTIVE SYSTEM

INTERNATIONAL BUSINESS MA...

1. An apparatus comprising:a semiconductor structure including a recess formed in a portion of the source/drain contact using a recess patterning process;
a bi-stable resistive system (BRS) material deposited in the recess in contact with the portion of a source/drain contact; and
a metallization layer contact formed upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

US Pat. No. 10,991,798

REPLACEMENT SACRIFICIAL NANOSHEETS HAVING IMPROVED ETCH SELECTIVITY

INTERNATIONAL BUSINESS MA...

1. A method of forming a nanosheet transistor, the method comprising:forming a nanosheet stack comprising alternating layers of channel nanosheets and sacrificial nanosheets;
wherein each of the layers of channel nanosheets comprises a first type of semiconductor material;
wherein each of the layers of sacrificial nanosheets comprises a second type of semiconductor material;
removing the layers of sacrificial nanosheets from the nanosheet stack;
forming layers of replacement sacrificial nanosheets in spaces that were occupied by the sacrificial nanosheets;
wherein each of the layers of replacement sacrificial nanosheets comprises a first type of non-semiconductor material; and
removing the layers of replacement sacrificial nano sheets.

US Pat. No. 10,991,797

SELF-ALIGNED TWO-DIMENSIONAL MATERIAL TRANSISTORS

International Business Ma...

1. A method of forming a semiconductor device, the method comprising:forming a structure comprising at least a handle wafer, a two-dimensional (2D) material layer, a gate structure formed on and in contact with the 2D material layer, an insulating layer in contact with the 2D material layer and the gate structure, and a sacrificial layer in contact with the insulating layer and the gate structure;
etching a portion of the sacrificial layer thereby exposing a first portion of the insulating layer;
forming an inter-layer dielectric on the first portion of the insulating layer and sidewalls of the sacrificial layer;
removing the sacrificial layer and a second portion of the insulating layer thereby exposing a portion of the 2D material layer; and
forming a source contact layer and a drain contact layer each in contact with the portion of the 2D material layer.

US Pat. No. 10,991,794

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Semiconductor Manufacturi...

1. A method for manufacturing a semiconductor device, comprising:providing a semiconductor structure, wherein the semiconductor structure comprises:
a substrate,
a gate structure disposed on the substrate,
initial spacer layers on side surfaces of two sides of the gate structure, and
a first inter-layer dielectric layer covering the gate structure and the initial spacer layers,
wherein the substrate comprises a source and a drain respectively located on the two sides of the gate structure;
etching the first inter-layer dielectric layer to form a source contact hole exposing the source and a drain contact hole exposing the drain, wherein the source contact hole and the drain contact hole further expose a part of the initial spacer layer on at least one side of the gate structure;
removing the exposed part of the initial spacer layer to expose the side surface of the at least one side of the gate structure;
forming a spacer structure layer on the exposed side surface of the at least one side of the gate structure, wherein:
the spacer structure layer comprises a first spacer layer, a sacrificial spacer layer, and a second spacer layer,
the first spacer layer is positioned between the gate structure and the sacrificial spacer layer, the sacrificial spacer layer is positioned between the first spacer layer and the second spacer layer, and a bottom end of the second spacer layer is higher than a bottom end of the first spacer layer, and
the first spacer layer is formed on the exposed side surface of the at least one side of the gate structure, the sacrificial spacer layer is formed on a side surface of the first spacer layer, and the second spacer layer is formed on a side surface of the sacrificial spacer layer;
after the spacer structure layer is formed, forming, in the source contact hole, a source contact member connected to the source, and forming, in the drain contact hole, a drain contact member connected to the drain;
after the source contact member and the drain contact member are formed, selectively removing the sacrificial spacer layer to form an air gap and maintaining the first spacer layer and the second spacer layer, wherein a bottom end of the air gap is positioned above the bottom end of the first spacer layer and below the bottom end of the second spacer layer; and
forming a second inter-layer dielectric layer on the first inter-layer dielectric layer, the source contact member, and the drain contact member, wherein the second inter-layer dielectric layer covers the air gap.

US Pat. No. 10,991,779

ELECTRO-OPTICAL APPARATUS, MANUFACTURING METHOD FOR ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC DEVICE

SEIKO EPSON CORPORATION, ...

1. A light-emitting device comprising:a substrate;
an opposing electrode provided on the substrate;
a light-reflective layer provided between the substrate and the opposing electrode;
a light-emitting layer disposed between the light-reflective layer and the opposing electrode;
a first pixel electrode disposed between the light-reflective layer and the light-emitting layer;
a second pixel electrode disposed between the light-reflective layer and the light-emitting layer, the second pixel electrode being provided adjacent to the first pixel electrode;
a first insulating layer disposed between the light-reflective layer and the first pixel electrode, the first insulating layer being disposed between the light-reflective layer and the second pixel electrode, the first insulating layer contacting the first pixel electrode and the second pixel electrode, the first insulating layer provided across under the first pixel electrode and under the second pixel electrode in common, and
a second insulating layer disposed between the light-reflective layer and the first insulating layer, the second insulating layer overlapping the first pixel electrode in plan view, wherein
at least part of an edge of the second insulating layer is disposed in a first region that is between the first pixel electrode and the second pixel electrode in plan view.

US Pat. No. 10,991,778

ORGANIC EL DISPLAY APPARATUS AND MANUFACTURING METHOD THEREFOR

SAKAI DISPLAY PRODUCTS CO...

1. An organic EL display apparatus comprising:a substrate having a surface on which a drive circuit comprising a thin film transistor is formed;
a planarizing layer to cover the drive circuit to planarize the surface of the substrate; and
an organic light emitting element having a first electrode, the first electrode being formed on a surface of the planarizing layer and connected to the drive circuit, an organic light emitting layer, the organic light emitting layer being formed on the first electrode, and a second electrode, the second electrode being formed on the organic light emitting layer,
wherein the planarizing layer comprises a two-layer structure comprising an inorganic insulating layer and an organic insulating layer, the inorganic insulating layer and the organic insulating layer being deposited on the thin film transistor, and
wherein a connection between the drive circuit and the first electrode is made via a conductor layer being embedded at an interior of a contact hole formed at the planarizing layer, the conductor layer comprising a titanium layer and a copper layer, and the first electrode is formed so as to electrically connect to the conductor layer, and
wherein a surface of the conductor layer and the surface of the planarizing layer are formed on the same plane with 20 nm or more and 50 nm or less in arithmetic average roughness Ra by polishing, and the first electrode and the organic light emitting layer each having an almost same surface roughness as that of the surface of the planarizing layer are formed, thereby a surface of the organic light emitting layer is formed with no inclined surface due to unevenness of a light emitting surface even when viewed microscopically.

US Pat. No. 10,991,765

OPTICAL STACK FOR IMPROVED COLOR UNIFORMITY IN OLED DISPLAY

3M INNOVATIVE PROPERTIES ...

1. An optical stack comprising first and second layers and a nanostructured interface therebetween, the first layer having a first refractive index, the second layer having a different second refractive index being at least 1.4, the nanostructured interface having a substantially azimuthally symmetric power spectral density (PSD), a wavenumber-PSD product having a maximum for a wavenumber larger than 6 radians/micrometer times the second refractive index, wherein for all wavenumbers less than 6 radians/micrometer times the second refractive index, the wavenumber-PSD product is no more than 0.3 times the maximum, andwherein the optical stack is configured to be disposed on an encapsulated emissive layer of an organic light emitting diode (OLED) display with the second layer disposed between the first layer and the encapsulated emissive layer and with the nanostructured interface proximate to, and outside of, an evanescent zone of the encapsulated emissive layer to reduce a variation in color with view angle of light emitted from the OLED display.

US Pat. No. 10,991,752

VERTICALLY INTEGRATED IMAGE SENSOR CHIPS AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

17. A method comprising:bonding an image sensor wafer to a device wafer;
etching-through a semiconductor substrate of the image sensor wafer to form a recess, wherein a dielectric layer of the image sensor wafer is exposed to the recess;
through the recess, forming conductive features to electrically couple the image sensor wafer to the device wafer; and
sawing the image sensor wafer and the device wafer, with a scribe line passing through the recess.

US Pat. No. 10,991,743

SOLID STATE IMAGE PICKUP DEVICE AND PRODUCTION METHOD, SEMICONDUCTOR WAFER, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A solid state image pickup device comprising:a chip region in which a plurality of pixels and elements for driving the pixels are provided; and
a measuring region that is provided in a neighboring relationship with the chip region and in which the elements and wiring lines necessary for driving of the pixels are not provided but measurement pads for measuring a property of the chip region therethrough are provided; and
a dicing line that partitions a plurality of regions including the chip region and the measuring region, wherein the dicing line includes copper and a coverage of copper at a location of the dicing line is lower than a coverage of copper in a region not including the dicing line.

US Pat. No. 10,991,738

METHOD FOR PRODUCING CURVED ELECTRONIC CIRCUITS

1. A method for producing several curved electronic circuits, comprising:placing several adhesive elements between several electronic chips and several curved bearing surfaces, with the several electronic chips disposed between the several curved bearing surfaces and a flexible film, and such that the several electronic chips, the several adhesive elements, and the several curved bearing surfaces are arranged in a single volume configured to be depressurised towards an environment outside the single volume, wherein the single volume includes empty spaces present between the several electronic chips and the several curved bearing surfaces, the empty spaces being in fluid communication with each other within the single volume;
before establishing a pressure difference between an inside and an outside of the single volume, disposing the several curved bearing surfaces between the several electronic chips and a rigid support, the flexible film being attached to the rigid support;
establishing the pressure difference between the inside and the outside of the single volume such that the flexible film applies a pressure on the several electronic chips, and collectively deforms the several electronic chips in accordance with the several curved bearing surfaces; and
stopping the establishing of the pressure difference between the inside and the outside of the single volume, the several electronic chips being collectively maintained against the several curved bearing surfaces by the several adhesive elements such that a shape of each of the several electronic chips conforms to a corresponding shape of each of the several curved bearing surfaces,
wherein the single volume is defined at least by the rigid support and the flexible film.

US Pat. No. 10,991,726

PIXEL ARRAY SUBSTRATE

Au Optronics Corporation,...

1. A pixel array substrate comprising:a substrate having a transparent window, a wire region, and an active region, wherein the wire region is located around the transparent window, and the wire region is located between the active region and the transparent window;
a plurality of pixels disposed at the active region, wherein each of the plurality of pixels comprises a first signal line, a second signal line, an active device, and a pixel electrode, the first signal line and the second signal line are interlaced, the active device is electrically connected to the first signal line and the second signal line, and the pixel electrode and the active device are electrically connected; and
a plurality of connection wires disposed at the wire region, wherein each of the plurality of connection wires is electrically connected to first signal lines of the plurality of pixels located at two opposite sides of the transparent window;
the plurality of connection wires comprising a first wire group, the first wire group comprising a plurality of first connection wires, each of the plurality of first connection wires having a first segment and a second segment, a first insulation layer being disposed between the first segment and the second segment, the first segment and the second segment being electrically connected;
the plurality of connection wires comprising a second wire group, the second wire group comprising a plurality of second connection wires;
the first segment of one of the plurality of first connection wires and one of the plurality of second connection wires being overlapped, the first insulation layer being disposed between the first segment of the one of the plurality of first connection wires and the one of the plurality of second connection wires.

US Pat. No. 10,991,723

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS

SONY SEMICONDUCTOR SOLUTI...

1. A semiconductor device, comprising:an SOI substrate in which a silicon substrate layer, a first insulating layer, and a semiconductor layer are layered in this order;
a first transistor provided on the semiconductor layer;
a second transistor provided on the silicon substrate layer and withstanding a higher voltage than the first transistor; and
an element separation film provided between the first transistor and the second transistor,
the element separation film including a second insulating layer embedded in an opening, the opening penetrating the semiconductor layer and the first insulating layer and reaching an inside of the silicon substrate layer, and
a portion of the second insulating layer constituting a gate insulating film of the second transistor.

US Pat. No. 10,991,720

STACKED TYPE SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a substrate;
a stacked body provided above the substrate and in which an insulating film and an electrode film are alternately stacked in a first direction;
an insulating member which extends through the stacked body in the first direction and a second direction crossing the first direction and separates the stacked body in a third direction crossing the first and second directions; and
a pillar including a semiconductor which extends through the stacked body in the first direction,
the insulating member including a first part and a second part provided on the first part,
each of the first part and the second part including a maximum portion where a first distance from a side surface of the insulating member to a central plane of the insulating member becomes maximum, and
the maximum portion of the first part and the maximum portion of the second part being placed away from ends of the insulating member in the first direction.

US Pat. No. 10,991,713

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a semiconductor substrate;
a first signal line extending in a first direction;
a second signal line disposed apart from the first signal line in a second direction and extending in the first direction, the second direction crossing the first direction and being parallel to the semiconductor substrate;
a first insulating layer provided between the first signal line and the second signal line;
a first interconnect layer provided above the semiconductor substrate and extending in a third direction, the third direction crossing the first and second directions and being parallel to the semiconductor substrate;
a second interconnect layer located apart from the first interconnect layer in the second direction and extending in the third direction;
a first memory cell which stores first information by applying voltage across the first signal line and the first interconnect layer;
a second memory cell which stores second information by applying voltage across the second signal line and the second interconnect layer;
a first conductive layer provided on the first signal line and the second signal line;
a third interconnect layer provided above the first interconnect layer and extending in the third direction;
a fourth interconnect layer located apart from the third interconnect layer in the second direction and extending in the third direction;
a third signal line provided on the first conductive layer and extending in the first direction;
a fourth signal line provided on the first conductive layer, disposed apart from the third signal line in the second direction, and extending in the first direction;
a second insulating layer provided between the third signal line and the fourth signal line;
a third memory cell which stores third information by applying voltage across the third signal line and the third interconnect layer; and
a fourth memory cell which stores fourth information by applying voltage across the fourth signal line and the fourth interconnect layer.

US Pat. No. 10,991,712

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a substrate;
a plurality of conductive layers and a plurality of insulating layers that are stacked above the substrate, where an end of a stacked structure formed by the conductive layers and the insulating layers having a staircase structure in which the conductive layers form treads of respective steps, the staircase structure including a step pair formed by a first step part and a second step part, risers of respective steps of the step pair being opposed to each other, and a plurality of the step pairs being provided at different levels in the form of a staircase in the staircase structure;
a plurality of first contact plugs provided on treads of respective steps of the first step part;
second contact plugs provided in both of an intermediate region between the first step part and the second step part of the step pair and the second step part to extend in the stacked structure in a direction in which the conductive layers and the insulating layers are stacked; and
a CMOS (Complementary Metal Oxide Semiconductor) circuit provided below the stacked structure and electrically connected to the second contact plugs, wherein
the second contact plugs are provided in both of the intermediate region in which the first contact plug is not formed thereon and the second step part in which the first contact plug is not formed thereon.

US Pat. No. 10,991,709

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a memory cell formation region and a peripheral circuit formation region;
a memory cell formed in the memory cell formation region; and
a field-effect transistor formed in the peripheral circuit formation region,
wherein the memory cell comprises:
a first gate insulating film formed on the semiconductor substrate located in the memory cell formation region, and including a charge storage film formed of silicon nitride;
a memory gate electrode formed on the first gate insulating film; and
a first offset spacer contacting each of a sidewall of the memory gate electrode and a side end portion of the charge storage film so as to cover a side surface of the first gate insulating film, and formed of silicon oxide, and
wherein the field-effect transistor comprises:
a second gate insulating film formed on the semiconductor substrate located in the peripheral circuit formation region, and including a high dielectric constant film having a dielectric constant higher than that of a silicon nitride film,
a gate electrode formed on the second gate insulating film, and
a second offset spacer contacting each of a sidewall of the gate electrode and a side end portion of the high dielectric constant film so as to cover a side surface of the second gate insulating film, and formed of silicon nitride.

US Pat. No. 10,991,703

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device, comprising:a semiconductor substrate;
an interlayer insulating film that is formed on the semiconductor substrate;
a nonvolatile memory element that includes a real ferroelectric capacitor formed on the interlayer insulating film, wherein
the real ferroelectric capacitor includes:
a first bottom electrode formed on the interlayer insulating film,
a first ferroelectric film formed on the first bottom electrode, and
a first top electrode formed on the first ferroelectric film, and
the first bottom electrode of the real ferroelectric capacitor is electrically connected to the semiconductor substrate through a first plug penetrating the interlayer insulating film;
a shield ring having a ring-like shape as viewed from above,
wherein the shield ring is formed continuously around the semiconductor device and along a scribe region of the semiconductor device in order to prevent entry of moisture; and
a first dummy ferroelectric capacitor formed intermittently around the semiconductor device and along the shield ring, wherein
the shield ring includes a real capacitor oxidation suppression structure,
the real capacitor oxidation suppression structure includes a second dummy ferroelectric capacitor and a second plug,
the second dummy ferroelectric capacitor includes a second bottom electrode, a second ferroelectric film, and a second top electrode,
the second dummy ferroelectric capacitor is not used as the nonvolatile memory element,
the second bottom electrode is formed on the interlayer insulating film,
the second ferroelectric film is formed on the second bottom electrode,
the second top electrode is formed on the second ferroelectric film, and
the second plug penetrates the interlayer insulating film and electrically connects the second bottom electrode to the semiconductor substrate.

US Pat. No. 10,991,676

SYSTEMS AND METHODS FOR FLASH STACKING

Invensas Corporation, Sa...

1. A method for producing a microelectronic stack comprising:providing a plurality of wafers having a first face and a second face forming a body thereof for production of microelectronic components, the plurality of wafers each having at least one dielectric region thereon wherein the at least one dielectric region extends from the first face to the second face;
disposing a plurality of conductive metallic traces over the dielectric region in a manner selected from a group consisting of printing, direct imaging, and stenciling wherein each of the conductive metallic traces has at least one corresponding trace on each of the plurality of wafers;
bonding each of the plurality of wafers thereby forming a layered stack of wafers,
wherein the first face of one of the plurality of wafers is bonded to the second face of another one of the plurality of wafers;
dicing the layered stack of wafers along predetermined dicing lanes such that the dicing exposes a vertical edge of a stack wherein the exposed vertical edge is formed of the dielectric region and the plurality of conductive metallic traces; and
interconnecting the metallic traces along the vertical edge through electroless plating such that the metallic traces are electronically interconnected through each layer of the stack.

US Pat. No. 10,991,670

SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING SPACER WITH EMBEDDED SEMICONDUCTOR DIE

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device assembly comprising:a semiconductor die having:
a first surface including active circuitry;
a second surface opposite the first surface; and
a plurality of side surfaces each extending between the first surface of the semiconductor die and the second surface of the semiconductor die;
a conductive spacer having a cavity defined therein, the semiconductor die being electrically and thermally coupled with the conductive spacer, the semiconductor die being at least partially embedded in the cavity; and
a direct bonded metal (DBM) substrate, the DBM substrate being electrically coupled with the first surface of the semiconductor die.

US Pat. No. 10,991,666

LOCATION DISPLACEMENT DETECTION METHOD, LOCATION DISPLACEMENT DETECTION DEVICE, AND DISPLAY DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A location displacement detection device that detects a location displacement of an electrical connection portion of a device relative to an electrical connection portion of a semiconductor element electrically connectable to the electrical connection portion of the device, the location displacement detection device comprisinga location displacement detection unit that detects the location displacement of the electrical connection portion of the device relative to the electrical connection portion of the semiconductor element, based on a conduction state between the electrical connection portion of the semiconductor element and the electrical connection portion of the device,
the electrical connection portion of the semiconductor element comprises first and second connection portions arranged in a first direction with a first spacing apart from each other, and third and fourth connection portions arranged in a second direction perpendicular to the first direction with a second spacing apart from each other.

US Pat. No. 10,991,663

SEMICONDUCTOR DEVICE INCLUDING DUMMY CONDUCTIVE CELLS

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:forming a plurality of dummy conductive cells that provides different densities in empty areas in a plurality of metal layers of a semiconductor device according to overlap conditions of the empty areas each arranged between a pair of neighboring metal layers of the plurality of metal layers,
wherein forming the plurality of dummy conductive cells comprises:
forming a group of dummy conductive cells in a single empty area of the empty areas when the single empty area in one pair of the neighboring metal layers is overlapped by a signal line in the same pair of the neighboring metal layers, and
wherein when viewed in plan view, projection areas of the group of dummy conductive cells are vertically overlapped by a projection area of the signal line.

US Pat. No. 10,991,654

INDUCTIVE CONNECTION STRUCTURE FOR USE IN AN INTEGRATED CIRCUIT

STMicroelectronics S.r.l....

1. An apparatus, comprising:an integrated circuit having a plurality of metallization layers;
a connection terminal on an upper metallization layer of said plurality of metallization layers;
a conductive element below the connection terminal, said conductive element configured to electrically couple the connection terminal to one or more circuit elements of the integrated circuit;
an inductive element in at least one metallization layer of said plurality of metallization layers that are located below the upper metallization layer and surrounding at least part of said conductive element;
a containment structure provided extending through said plurality of metallization layers and surrounding at least the inductive element, said containment structure configured to contain a magnetic field generated by the inductive element.

US Pat. No. 10,991,651

INTERCONNECTION STRUCTURE HAVING REDUCED CAPACITANCE AND METHOD OF MANUFACTURING THE SAME

Nanya Technology Corporat...

1. A method of forming a semiconductor component, comprising:forming a plurality of metallic lines on a substrate;
depositing an insulative film to cover the substrate and the metallic lines, wherein the insulative film has a topology following the topology of the substrate and the metallic lines;
depositing a passivation layer to bury the insulative film, wherein the insulative film and the passivation layer have different dielectric constants; and
performing a removal process to remove the insulative film and thus creating an air spacer interposed between the substrate and the passivation layer and between the metallic lines and the passivation layer.

US Pat. No. 10,991,649

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first substrate including a surface;
a pad array on the surface of the first substrate, wherein the pad array comprises a first type pad and a second type pad at a same level;
a conductive bump connecting one of the first type pad of the second type pad to a second substrate;
a first via connected to a conductive feature at a different level to the first type pad, the first via being located within a projection area of the first type pad and directly contacting the first type pad, wherein the second type pad is laterally connected with a conductive trace on the same level, and the conductive trace is connected to a second via that is at a same level with the first via; and
a dielectric in the first substrate, the dielectric contacting the second type pad, wherein the second type pad is floated on the dielectric, and a bottom surface of the first type pad contacts each of the dielectric and a center of a top surface of the first via located within the projection area of the first type pad.

US Pat. No. 10,991,643

POWER MODULE COMPRISING A HOUSING WHICH IS FORMED IN LEVELS

Robert Bosch GmbH, Stutt...

1. A power module (1, 30), comprisingat least one power semiconductor (4, 34, 35),
at least one further electronic component (20, 48, 49, 17, 50), and
a housing, which is formed by a shaped body and which is formed by an encapsulation compound (12, 13),
wherein the housing is formed in at least first and second levels (2, 3, 31, 32), and the at least one power semiconductor component (4, 34, 35) is arranged in the first level (3, 31), and the at least one further electronic component (20, 48, 49, 17, 50) is arranged in the second level (2), at least one electrically conductive layer forming an electrically conductive connection structure (18, 19, 24, 51, 52, 53, 54) on a surface (26) of an inner interface (25), the inner interface (25) extending between the first and second levels (2, 3), of the power module, said layer being applied onto the surface (26), the at least one further electronic component (20, 48, 49, 17, 50) being electrically conductively connected to the connection structure (18, 19, 24, 51, 52, 53, 54), the power semiconductor component (4, 34, 35) in the first level (3, 31) being electrically connected to the further component in the second level (2) by the connection structure (18, 19, 24, 51, 52, 53, 54), wherein the encapsulation compound (29) is a cement compound which is formed with the formation of cement crystals (12) so that each of the first and second levels (2, 3, 31, 32) is formed by a continuous crystal structure, and wherein the connection structure forms a capacitive sensor configured to record moisture on the inner interface (25).

US Pat. No. 10,991,642

INTEGRATED CIRCUIT, AND MOTOR DEVICE INCLUDING THE SAME

JOHNSON ELECTRIC INTERNAT...

1. An integrated circuit comprising a bare die and a multiplexed pin, the multiplexed pin electrically connected to first and second switch circuits, the first and second switch circuits respectively connected to first and second circuit modules disposed on the bare die and controlling a connection between the first and second circuit modules and the multiplexed pin,the first switch circuit being connected to a first die pad by a metal layer trace within the bare die, the second switch circuit being connected to a second die pad by a metal layer trace within the bare die, and the first and second die pads connected to the multiplexed pin through a bond wire respectively.

US Pat. No. 10,991,640

SEMICONDUCTOR PACKAGES INCLUDING BRIDGE DIE

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a first semiconductor die disposed on a package substrate;
a stack of second semiconductor dies disposed on the package substrate to be spaced apart from the first semiconductor die;
a first bridge die including first through vias that electrically connect the first semiconductor die to the package substrate;
a second bridge die including second through vias that electrically connect the stack of the second semiconductor dies to the package substrate;
a third semiconductor die disposed to overlap with the first semiconductor die and the stack of the second semiconductor dies;
first inner connectors electrically connecting the first semiconductor die to the third semiconductor die;
second inner connectors electrically connecting the stack of the second semiconductor dies to the third semiconductor die; and
redistribution lines disposed to electrically connect the third semiconductor die to the second bridge die,
wherein the second bridge die further includes third through vias that are electrically coupled to the redistribution lines to electrically connect the third semiconductor die to the package substrate, and
wherein the redistribution lines extend such that first ends of the redistribution lines are connected to the third semiconductor die and second ends of the redistribution lines are connected to the third through vias.

US Pat. No. 10,991,637

WAFER-LEVEL CHIP-SCALE PACKAGE INCLUDING POWER SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF

MagnaChip Semiconductor, ...

1. A method of manufacturing a wafer-level chip-scale package, the method comprising:forming a power semiconductor device comprising a first semiconductor device and a second semiconductor device electrically connected to the first semiconductor device on a semiconductor substrate;
forming a first source metal bump and a first gate metal bump on the first semiconductor device, and forming a second source metal bump and a second gate metal bump on the second semiconductor device of the power semiconductor;
forming a recessed area and a rim disposed around the recessed area by polishing a bottom of the semiconductor substrate;
depositing a back metal layer comprising nickel-vanadium on the recessed area;
forming a common drain electrode, connected to the first semiconductor device and the second semiconductor device, by depositing a first metal layer comprising copper or silver on the recessed area and a second metal layer comprising nickel on the first metal layer; and
flattening the bottom of the semiconductor substrate by trimming the rim.

US Pat. No. 10,991,636

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:forming a conductive material embedded within a dielectric material; and
forming a dielectric layer over the conductive material and the dielectric material, wherein the forming the dielectric layer forms the dielectric layer with isolated pores, wherein the forming the dielectric layer forms the dielectric layer with a scaling factor less than or equal to about 1.8.

US Pat. No. 10,991,635

MULTIPLE CHIP BRIDGE CONNECTOR

International Business Ma...

1. A bridge connector comprising:one or more semiconductor layers in the bridge connector, the bridge connector having a bridge connector shape, the bridge connector shape having one or more edges;
one or more bridge connector contacts on a surface of the bridge connector shape, all the bridge connector contacts being within a tolerance distance from one or more of the edges;
one or more connections, the connections running through one or more of the semiconductor layers and connecting two or more of the bridge connector contacts; and
an opening passing completely through the bridge connector, the opening having an opening shape, the opening shape being non-rectangular, and the opening being centered within the bridge connector and not in the tolerance distance.

US Pat. No. 10,991,634

METHOD AND SYSTEM FOR MANUFACTURING SOLAR CELLS AND SHINGLED SOLAR CELL MODULES

CHENGDU YEFAN SCIENCE AND...

1. A method of manufacturing a solar cell comprising:pretreating a wafer, by:
texturing one or more surfaces of the wafer;
diffusing a p-type layer on a front side of the wafer to form PN junctions in the wafer;
removing the p-type layer at a back side and edges of the wafer and impurities on surfaces of the wafer formed during the junction diffusion by etching;
forming a silicon dioxide layer on the back side of the wafer;
forming a multicrystalline silicon layer on the silicon dioxide layer;
implanting phosphorus atoms into the multicrystalline silicon layer by ion implanting;
activating the phosphorus atoms implanted by annealing; and
depositing a first layer of film on the front side of the wafer, and a second layer of film on the front and back sides of the wafer;
screen-printing a precious metal paste on a surface of the pretreated wafer;
sintering and curing the screen-printed wafer to form a solar cell;
performing laser scribing at a side of the solar cell away from a surface of the solar cell having the PN junctions and dividing the solar cell into a plurality of solar cell strips; and
performing testing, appearance inspection, and sorting on the plurality of solar cell strips respectively in the cell manufacturing process, wherein the sorting of the plurality of solar cell strips is based upon a result of the testing.

US Pat. No. 10,991,632

ASSEMBLY PROCESS FOR CIRCUIT CARRIER AND CIRCUIT CARRIER

AB MIKROELEKTRONIK GESELL...

1. A process for the production of a circuit carrier having at least one light emitting diode, the circuit carrier for use in a motor vehicle, the process comprising:illuminating a light emitting region of a light emitting diode with light from a light source that is separated from the light emitting diode, the light having a wavelength in a range of 400 nm to 500 nm;
detecting a position of the light emitting region of the light emitting diode while illuminating the light emitting region of the light diode with the light from the light source that is separated from the light emitting diode;
positioning the light emitting diode in relationship to one or more reference points of the circuit carrier based at least in part on the position of the light emitting region.

US Pat. No. 10,991,631

HIGH PERFORMANCE SIGE HETEROJUNCTION BIPOLAR TRANSISTORS BUILT ON THIN-FILM SILICON-ON-INSULATOR SUBSTRATES FOR RADIO FREQUENCY APPLICATIONS

Newport Fab, LLC, Newpor...

1. A method of fabricating a silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) on the same semiconductor substrate, the method comprising:forming a first silicon region and a second silicon region over a dielectric layer formed over the semiconductor substrate;
forming one or more shallow trench isolation regions through the first and second silicon regions, wherein all of the one or more shallow trench isolation regions extend entirely through the first and second silicon regions;
fabricating a SOI CMOS transistor in the first silicon region; and
fabricating a collector region of the SOI HBT in the second silicon region by:
performing a first implant to introduce an impurity of a first conductivity type into a local collector region in the second silicon region; and
performing a second implant to introduce an impurity of the first conductivity type into an extrinsic collector region in the second silicon region, wherein the extrinsic collector region is separated from, and is not continuous with, the local collector region within the second silicon region, and wherein the local collector region is more heavily doped than the extrinsic collector region.

US Pat. No. 10,991,630

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:forming a gate stack on a fin;
etching the fin to form a recess in the fin adjacent the gate stack;
dispensing a plurality of silicon precursors during a first growth process to form a first layer of an epitaxial source/drain region in the recess, the plurality of silicon precursors being dispensed during the first growth process at flow rates having a first set of flow-rate ratios; and
dispensing the plurality of silicon precursors during a second growth process to form a second layer of the epitaxial source/drain region on the first layer of the epitaxial source/drain region, the plurality of silicon precursors being dispensed during the second growth process at flow rates having a second set of flow-rate ratios, the second set of flow-rate ratios being different than the first set of flow-rate ratios,
wherein the silicon precursors of the first growth process have a first ratio of a sum of a quantity of bonded gas-phase silicon atoms and a quantity of bonded gas-phase hydrogen atoms to a quantity of bonded gas-phase chlorine atoms, and
wherein the silicon precursors of the second growth process have a second ratio of a sum of a quantity of bonded gas-phase silicon atoms and a quantity of bonded gas-phase hydrogen atoms to a quantity of bonded gas-phase chlorine atoms, the second ratio being greater than the first ratio.

US Pat. No. 10,991,628

ETCH STOP LAYER BETWEEN SUBSTRATE AND ISOLATION STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A device, comprising:a substrate;
semiconductor fins extending from the substrate;
an isolation structure over the substrate and laterally between the semiconductor fins;
a gate dielectric layer on a top surface of the isolation structure and on sidewalls of the semiconductor fins;
a liner layer between sidewalls of the semiconductor fins and the isolation structure; and
an etch stop layer between the substrate and the isolation structure and laterally between the semiconductor fins, the etch stop layer including a material different than that of the isolation structure and the liner layer.

US Pat. No. 10,991,627

METHODS FOR FORMING FIN FIELD-EFFECT TRANSISTORS

Taiwan Semiconductor Manu...

1. A device comprising:a first fin structure including a plurality of adjacent parallel semiconductor fins extending from a first level of a substrate, each fin of the first fin structure having a first height as measured from the first level of the substrate;
a second fin structure extending from the first level of the substrate, each fin of the second fin structure having a second height as measured from the first level of the substrate, the second height different from the first height, wherein the second fin structure is directly adjacent the first fin structure and extends lengthwise parallel to the first fin structure;
an isolation structure extending from the first fin structure to the second fin structure and extending over a top surface of the second fin structure, wherein a top portion of the first fin structure extends above a top surface of the isolation structure; and
a gate structure disposed over the first fin structure, the gate structure comprising a gate dielectric and a gate electrode over the gate dielectric.

US Pat. No. 10,991,626

METHOD FOR CONTROLLING TRANSISTOR DELAY OF NANOWIRE OR NANOSHEET TRANSISTOR DEVICES

Tokyo Electron Limited, ...

1. A semiconductor device comprising:a substrate having a planar surface;
a first gate-all-around field effect transistor (GAA-FET) provided on the substrate and including a first channel having an untrimmed volume of the first channel material corresponding to a volume of the first channel material within a first stacked fin structure from which the first channel was formed; and
a second GAA-FET provided on the substrate and including a second channel having a trimmed volume of second channel material which is less than the untrimmed volume of the first channel material by a predetermined trim amount corresponding to a delay adjustment of the second GAA-FET relative to the first GAA-FET, wherein the first and second GAA FETs are electrically connected as complementary FETs, wherein
the trimmed volume of the second channel material is trimmed selectively laterally from the edges of the first channel along a direction parallel to a plane of the substrate.

US Pat. No. 10,991,625

AUTOMATED TRANSFER AND DRYING TOOL FOR PROCESS CHAMBER

Taiwan Semiconductor Manu...

1. A method processing a plurality of IC die, comprising:passing a singulated semiconductor die through a housing of an integrated circuit processing tool and into an inner chamber of the integrated circuit processing tool;
subjecting the singulated semiconductor die to a liquid while performing scanning acoustic microscopy on the singulated semiconductor die to evaluate the singulated semiconductor die for defects, wherein the liquid remains present on an upper surface and a lower surface of the singulated semiconductor die after evaluation;
transferring the singulated semiconductor die to a drying station that dries only a frontside of the singulated semiconductor die; and
transferring the singulated semiconductor die from the drying station to a die wipe station that dries only a backside of the singulated semiconductor die.

US Pat. No. 10,991,622

WAFER PROCESSING METHOD

DISCO CORPORTION, Tokyo ...

1. A wafer processing method including a substrate and a device layer stacked over a surface of the substrate, the wafer having devices formed in respective regions divided by a plurality of intersecting streets, the method comprising:a mask forming step of forming, on a back side of the wafer, a mask to be used in forming a plurality of etched grooves in the substrate along the intersecting streets from the back side of the wafer;
a plasma etching step of applying plasma etching from the back side of the wafer through the mask after performing the mask forming step, thereby forming the etched grooves in the substrate along the intersecting streets and defining chip regions surrounded by the etched grooves;
a water immersion step of applying ultrasonic vibrations to the wafer by an ultrasonic vibrator, after performing the plasma etching step, to form cracks in the device layer along outer peripheral edges of the chip regions or rupturing the device layer along the outer peripheral edges of the chip regions; and
a tape bonding step of bonding a tape to a front side of the wafer before performing at least the water immersion step,
wherein the devices are separated from the tape after performing the water immersion step.

US Pat. No. 10,991,621

SEMICONDUCTOR DIE SINGULATION

TEXAS INSTRUMENTS INCORPO...

1. A method for making a semiconductor device, comprising:forming a metal layer on a backside surface of a semiconductor wafer, the semiconductor wafer having semiconductor dies spaced apart by scribe lanes on an active surface of the semiconductor wafer opposite the backside surface;
forming a layer with a modulus greater than about 4000 MegaPascals (MPa) up to about 8000 MPa over the metal layer on the backside surface of the semiconductor wafer;
mounting the backside surface of the semiconductor wafer including the metal layer and the layer with a modulus greater than about 4000 MPa up to about 8000 MPa on a first side of a dicing tape having an adhesive;
sawing between the semiconductor dies along the scribe lanes by using a saw blade to cut through the semiconductor wafer, the metal layer on the backside of the semiconductor wafer, and the layer with a modulus greater than about 4000 MPa up to about 8000 MPa;
separating the semiconductor dies one from another by stretching the dicing tape;
positioning singulated semiconductor dies on die mount portions of a substrate;
coupling leads of the substrate to bond pads on the semiconductor dies;
covering the semiconductor dies and at least a portion of the leads with mold compound; and
cutting the substrate and the mold compound along saw streets between the semiconductor dies on the substrate, forming separate packaged semiconductor devices, each including at least one semiconductor die.

US Pat. No. 10,991,617

METHODS AND APPARATUS FOR CLEAVING OF SEMICONDUCTOR SUBSTRATES

APPLIED MATERIALS, INC., ...

1. A method of cleaving a substrate in a chamber, comprising:adjusting a pressure of the chamber to a process pressure;
adjusting a temperature of the substrate to a nucleation temperature of ions implanted in the substrate using fast sweeping microwaves (FSM);
adjusting the temperature of the substrate below the nucleation temperature of the ions implanted in the substrate using FSM;
maintaining the temperature of the substrate at a soak temperature; and
detecting when cleaving of the substrate has occurred.

US Pat. No. 10,991,616

HIGH SPEED LOW TEMPERATURE METHOD FOR MANUFACTURING AND REPAIRING SEMICONDUCTOR PROCESSING EQUIPMENT AND EQUIPMENT PRODUCED USING SAME

Watlow Electric Manufactu...

1. A plate and shaft device used in semiconductor processing, said plate and shaft device comprising:a plate, said plate comprising a first ceramic, said plate comprising a joining interface surface of said first ceramic;
a shaft, said shaft comprising a second ceramic, said shaft comprising an interior space and an exterior, said shaft comprising a joining interface surface of said second ceramic, said shaft coupled to a bottom surface of said plate;
a first metal joining layer directly disposed between said joining interface surface of said plate and said joining interface surface of said shaft, wherein said first metal joining layer hermetically seals said interior space of said shaft from said exterior of said shaft through said first metal joining layer, said first metal joining layer comprising aluminum,wherein the conductive heat coefficient of said first ceramic is higher than the conductive heat coefficient of said second ceramic.

US Pat. No. 10,991,612

METHOD OF PROCESSING WAFER HAVING PROTRUSIONS ON THE BACK SIDE

DISCO CORPORATION, Tokyo...

1. A method of processing a wafer, having a first side with a device area comprising a plurality of devices, and a second side being opposite to the first side, wherein the second side has a plurality of protrusions protruding along a thickness direction of the wafer and the method comprises:providing a protective film;
providing a base sheet having a cushioning layer applied to a front surface thereof;
attaching a front surface of the protective film to the second side of the wafer, wherein the protective film is directly adhered to at least a peripheral portion of the second side with an adhesive;
attaching a back surface of the protective film opposite to the front surface thereof to the cushioning layer,
embedding the protrusions protruding along the thickness direction of the wafer in the cushioning layer so that a back surface of the base sheet opposite to the front surface thereof is substantially parallel to the first side of the wafer; and
processing the first side of the wafer.

US Pat. No. 10,991,611

WAFER PROCESSING LAMINATE AND METHOD FOR PROCESSING WAFER

SHIN-ETSU CHEMICAL CO., L...

1. A wafer processing laminate comprising a support, a temporary adhesive material layer laminated on the support, and a wafer stacked on the temporary adhesive material layer, the wafer having a front surface on which a circuit is formed and a back surface to be processed, the temporary adhesive material layer comprising a first temporary adhesive layer composed of a thermoplastic resin layer (A) laminated on the front surface of the wafer and a second temporary adhesive layer composed of a thermosetting resin layer (B) laminated on the first temporary adhesive layer, the thermoplastic resin layer (A) being soluble in a cleaning liquid (D) after processing the wafer, the thermosetting resin layer (B) being insoluble in the cleaning liquid (D) after heat curing and capable of absorbing the cleaning liquid (D) such that the cleaning liquid (D) permeates into the layer (B),wherein the temporary adhesive material layer further comprises a third temporary adhesive layer composed of a separation layer (C) laminated between the support and the thermosetting resin layer (B), wherein the separation layer (C) does not remain on the thermosetting resin layer (B) when the support is separated from the wafer processing laminate along the separation layer (C),
one or more of adhesive strength between the support and the separation layer (C), adhesive strength between the thermosetting resin layer (B) and the separation layer (C), and cohesive failure strength of the separation layer (C) are decreased by X-rays, ultraviolet rays, visible rays or infrared rays, and
the separation layer (C) contains one or more of a fluorine material, an aromatic hydrocarbon material and a thermosetting naphthalene derivative.

US Pat. No. 10,991,610

SYSTEMS AND METHODS FOR TREATING SUBSTRATES WITH CRYOGENIC FLUID MIXTURES

TEL MANUFACTURING AND ENG...

1. A substrate cleaning system, comprising:a vacuum process chamber comprising a substrate holder for a microelectronic substrate that rotates and translates the substrate during a treatment, wherein the vacuum process chamber is at a pressure of 10 Torr or less, and wherein the microelectronic substrate has a surface;
a fluid delivery system comprising a pressurized and cooled cleaning gas, wherein the pressurized and cooled cleaning gas comprises at least one of argon and nitrogen, and wherein the pressurized and cooled cleaning gas is in a gas phase comprising less than 1 weight percent of a liquid phase and wherein the pressurized and cooled gas is at a temperature in the range from 70 K to 150 K;
a fluid expansion component, the fluid expansion component comprising:
an inlet orifice through which the pressurized and cooled cleaning is introduced into the fluid expansion component;
an outlet orifice through which the expanded pressurized and cooled cleaning gas is expanded into the process chamber as a flow of gas clusters that flows laterally across the substrate surface, wherein the outlet orifice is positioned to provide a gap distance between the outlet orifice and the microelectronic substrate in the range from 2 mm to 10 mm, and wherein the angle of incidence between the flow of gas clusters and the substrate surface is between 60 degrees and about 90 degrees;
a first gas expansion region disposed between the inlet orifice and the outlet orifice in which the pressurized and cooled gas is expanded in a first expansion stage; and
a second gas expansion region disposed between the first expansion region and the outlet orifice, the second expansion region comprising a cross-sectional geometry that is different from the first expansion region, wherein the pressurized and cooled gas expands further in a second expansion stage to form the gas cluster spray, and wherein the second expansion region helps to constrain the expanding pressurized and cooled gas to form the flow of the gas clusters; and
a transition orifice between the first gas expansion region and the second gas expansion region through which the pressurized and cooled gas expands further into the second expansion region, wherein the transition orifice is smaller than the diameter of the first expansion region.

US Pat. No. 10,991,604

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor structure, comprising:loading a substrate into a first load port;
loading the substrate from the first load port into a first load lock chamber;
loading the substrate from the first load lock chamber into a first processing chamber;
disposing a conductive layer over the substrate in the first processing chamber;
loading the substrate from the first processing chamber into the first load lock chamber;
loading the substrate from the first load lock chamber into an enclosure filled with an inert gas and disposed between the first load lock chamber and a second load lock chamber;
loading the substrate from the enclosure into the second load lock chamber;
loading the substrate from the second load lock chamber into a second processing chamber;
disposing a conductive member over the conductive layer in the second processing chamber;
loading the substrate from the second processing chamber into the second load lock chamber; and
loading the substrate from the second load lock chamber into a second load port.

US Pat. No. 10,991,602

SUBSTRATE WASHING DEVICE

EBARA CORPORATION, Tokyo...

1. A substrate washing device comprising:a substrate holding mechanism that holds a substrate;
a substrate rotating mechanism that rotates the substrate held by the substrate holding mechanism; and
a two-fluid nozzle that ejects a two-fluid jet including droplets toward a surface of the rotating substrate, wherein
the two-fluid nozzle has a nozzle leading end formed of a conductive material and a nozzle base end formed of a non-conductive material, the conductive material being conductive carbon PEEK or conductive carbon PTFE, wherein the nozzle leading end is configured to discharge liquid external to the nozzle,
the two-fluid nozzle is configured to eject the droplets together with carrier gas, the droplets being positively electrified without adding charge from an external source, wherein the carrier gas and the liquid are mixed to form the droplets inside the nozzle and wherein
the substrate washing device further comprises an oscillation arm having the two-fluid nozzle on its leading end, the two-fluid nozzle being moved by the oscillation arm and facing the substrate.

US Pat. No. 10,991,601

APPARATUS AND METHOD FOR TREATING SUBSTRATE

SEMES CO., LTD., Chungch...

1. An apparatus for treating a substrate, the apparatus comprising:a processing vessel having a processing space inside;
a substrate support unit configured to support and rotate the substrate or a jig in the processing space;
a liquid dispensing unit including a treating liquid dispensing member configured to dispense a treating liquid for treating the substrate and a cleaning solution dispensing member configured to dispense a cleaning solution for cleaning the processing vessel; and
a controller configured to control the substrate support unit and the liquid dispensing unit,
wherein the substrate support unit includes:
a support plate having a vacuum line formed therein to clamp the substrate by vacuum pressure; and
a pressure-reducing member configured to produce the vacuum pressure in the vacuum line, and
wherein the controller controls the substrate support unit and the liquid dispensing unit to perform a first clamping step of clamping the substrate to the support plate by producing a first vacuum pressure in the vacuum line when treating the substrate by dispensing the treating liquid onto the substrate supported on the substrate support unit and clamping the jig to the support plate by producing a second vacuum pressure different from the first vacuum pressure, in the vacuum line when cleaning the processing vessel by dispensing the cleaning solution onto the jig supported on the substrate support unit.

US Pat. No. 10,991,599

SELF-ALIGNED VIA AND PLUG PATTERNING FOR BACK END OF LINE (BEOL) INTERCONNECTS

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a plurality of metal lines, wherein an individual one of the plurality of metal lines has a first portion, a second portion and a third portion, the first portion and the second portion separated by and in contact with a first dielectric plug, and the second portion and the third portion separated by and in contact with a second dielectric plug, the first dielectric plug having a different composition than the second dielectric plug; and
a plurality of dielectric material lines laterally alternating with the plurality of metal lines.

US Pat. No. 10,991,598

METHODS OF FABRICATING SEMICONDUCTOR PACKAGES INCLUDING CIRCUIT PATTERNS

SK hynix Inc., Icheon-si...

1. A method of fabricating a semiconductor package, the method comprising:forming a first plating layer on a first surface of a substrate body;
forming first circuit resist patterns and first monitoring resist patterns, each of the first monitoring resist patterns having different widths, on the first plating layer;
etching the first plating layer to form first circuit patterns and a first monitoring pattern by using the first circuit resist patterns and the first monitoring resist patterns as etch masks, wherein the first monitoring pattern includes sub-patterns which are etched from a portion of the first plating layer;
monitoring a first residual rate of the first circuit patterns by inspecting a number of the etched sub-patterns of the first monitoring pattern remaining on the first surface of the substrate body.

US Pat. No. 10,991,595

DRY ETCHING PROCESS FOR MANUFACTURING TRENCH STRUCTURE OF SEMICONDUCTOR APPARATUS

TAIWAN CARBON NANO TECHNO...

1. A dry etching process for manufacturing a trench structure of a semiconductor apparatus, comprising the steps of:step 1, providing a semiconductor substrate, the semiconductor substrate being provided with a photoresist layer which is patterned thereon and placed in a reaction chamber, the semiconductor substrate comprising a reserved area shielded by the photoresist layer and a predetermined etching area which is exposed, and the reaction chamber comprising an upper electrode and a lower electrode;
step 2, introducing a first etching gas into the reaction chamber to perform a first etching process, and removing a part of the predetermined etching area to form a trench, the trench comprising a first depth, and the first etching gas comprising sulfur hexafluoride, oxygen, helium, nitrogen trifluoride and a first organic silicide;
step 3, introducing a second etching gas into the reaction chamber to perform a second etching process, and etching the trench from the first depth to a second depth, the second etching gas comprising sulfur hexafluoride, oxygen, helium and a second organic silicide, wherein a pressure in the reaction chamber in the second etching process is higher than a pressure in the reaction chamber in the first etching process; and
step 4, introducing a third etching gas into the reaction chamber to perform a third etching process, the third etching gas comprising hydrobromic acid, oxygen, and helium;
wherein a temperature in the reaction chamber varies within +/?1% per second, a pressure in the reaction chamber varies within +/?5% per second, and a power of the upper electrode or the lower electrode varies within +/?1% per second.

US Pat. No. 10,991,593

ETCHING METHOD AND ETCHING PROCESSING APPARATUS

Tokyo Electron Limited, ...

1. A method of etching silicon-containing film formed above a substrate, the etching being performed in a processing vessel while supplying gas, a first electric power of a first frequency, and a second electric power of a second frequency less than the first frequency, the processing vessel including a lower electrode on which the substrate is placed during etching of the silicon-containing film, and including an upper electrode facing the lower electrode, the processing vessel being configured to supply the first electric power to the lower electrode or the upper electrode, and to supply the second electric power to the lower electrode, the silicon-containing film being formed on an electrode layer of a floating potential, the method comprising:supplying, during etching of the silicon-containing film, the first electric power as a continuous wave and the second electric power as the continuous wave or as a pulse wave having a duty cycle of 50% or more, while a distance from the electrode layer to a bottom of an etching pattern formed on the silicon-containing film is larger than a predetermined distance; and
supplying, during the etching of the silicon-containing film, the first electric power as the continuous wave and the second electric power as the pulse wave having the duty cycle of 20% or less, when the distance from the electrode layer to the bottom of the etching pattern formed on the silicon-containing film becomes not larger than the predetermined distance; wherein
a magnitude of the second electric power supplied while the distance from the electrode layer to the bottom of the etching pattern is larger than the predetermined distance is a same as a magnitude of the second electric power supplied after the distance from the electrode layer to the bottom of the etching pattern becomes not larger than the predetermined distance.

US Pat. No. 10,991,591

REACTIVE ION ETCHING APPARATUS

ULVAC, INC., Kanagawa (J...

1. A reactive ion etching apparatus comprising:a stage on which a to-be-processed substrate is disposed inside a vacuum chamber;
a gas introduction means for introducing an etching gas into the vacuum chamber in vacuum atmosphere;
a plasma generation means for generating inside the vacuum chamber a plasma which ionizes the introduced etching gas;
a radio-frequency power source connected to the stage through a first output line so as to apply bias potential to the to-be-processed substrate;
the stage being provided with an electrostatic chuck having a pair of electrodes so that, at the time of etching the to-be-processed substrate, DC voltage is applied to the pair of electrodes, whereby the to-be-processed substrate is electrostatically absorbed to the electrostatic chuck;
wherein: the radio-frequency power source is arranged to be connected, through a second output line, to the pair of electrodes so as to apply thereto radio-frequency potential in a manner to be superposed on the DC voltage;
both a first capacitor and a second capacitor are interposed respectively in the first output line and the second output line; and
a capacitance ratio of the first capacitor to the second capacitor is set to a range of 2.5 to 25.

US Pat. No. 10,991,589

CORRELATION BETWEEN CONDUCTIVITY AND PH MEASUREMENTS FOR KOH TEXTURING SOLUTIONS AND ADDITIVES

NAURA Akrion, Inc.

1. A method of etching material from at least one substrate, the method comprising:a) circulating a circulation volume of an etchant solution through a first closed-loop system and in contact with at least one silicon substrate to etch silicon from the at least one silicon substrate, the circulation volume of the etchant solution being at a known temperature;
b) measuring conductivity of the circulation volume of the etchant solution circulating through the first closed-loop system;
c) measuring pH of the circulation volume of the etchant solution circulating through the first closed-loop system; and
d) assigning an etchant concentration value to the measured conductivity of step b) based on the measured pH of step c);
e) measuring conductivity of a second closed-loop system and comparing against the etchant concentration value and perform a feed-and-bleed event to the second closed-loop system based on the etchant concentration value obtained from the first closed-loop system;
wherein the second closed-loop system is configured to etch a material.

US Pat. No. 10,991,585

TRIMMING OPTICAL DEVICE STRUCTURES

University of Southampton...

1. A method of trimming the refractive index of material forming at least part of one or more structures integrated in one or more pre-fabricated devices, the method comprising:implanting one or more first regions of material of one or more pre-fabricated devices, encompassing at least partially one or more device structures, with ions to alter the crystal form of the material within the one or more first regions and change the refractive index of the material within the one or more first regions; and
heat treating one or more second regions of material of the one or more devices, encompassing at least partially the one or more first regions, to alter the crystal form of the material within the one or more first regions encompassed by the one or more second regions and change the refractive index thereof, thereby trimming the refractive index of the material of at least part of the one or more device structures, such that the one or more device structures provide one or more predetermined device outputs.

US Pat. No. 10,991,583

SELF ALIGNED LITHO ETCH PROCESS PATTERNING METHOD

TAIWAN SEMICONDUCTOR MANU...

1. A method of defining a pattern, the method comprising:forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask of a substrate, the multi-layer hard mask comprising the first layer disposed on an underlying second layer, thereby exposing first portions of the second layer;
implanting an etch rate modifying species in the first layer in a portion of each of the plurality of cut shapes to form a plurality of etch stops;
directionally etching the first layer at the plurality of cut shapes such that the plurality of etch stops maintain;
forming a spacer layer on the first layer and the first portions of the second layer;
forming a second plurality of openings within the spacer layer to expose second portions of the second layer;
directionally etching the spacer layer to remove the spacer layer from sidewalls of the plurality of etch stops; and
etching portions of the second layer of the multi-layer hard mask exposed through the first plurality of openings and the second plurality of openings.

US Pat. No. 10,991,582

TEMPLATE FOR IMPRINT LITHOGRAPHY INCLUDING A RECESSION, AN APPARATUS OF USING THE TEMPLATE, AND A METHOD OF FABRICATING AN ARTICLE

CANON KABUSHIKI KAISHA, ...

1. A template comprising:a body for imprint lithography, wherein the body includes a first surface and a second surface, wherein the second surface is opposite the first surface, the body having a recession extending from the first surface lying along a base plane, the recession configured to at least partially fill with a formable material and including a main portion having a tapered sidewall and an aperture, wherein a distal surface is within the recession, wherein the recession includes an intermediate portion having an intermediate sidewall, wherein the main portion is disposed between the first surface and the distal surface of the recession, and wherein the aperture extends from the distal surface to the second surface.

US Pat. No. 10,991,581

METHOD FOR MANUFACTURING SEMICONDUCTOR FILM

THE JAPAN STEEL WORKS, LT...

1. A method for manufacturing a semiconductor film comprising the steps of:(a) irradiating, through a first optical path, an amorphous semiconductor film with a first pulsed laser beam having a first intensity; and then after the step (a),
(b) irradiating, through a second optical path, the semiconductor film with a second pulsed laser beam having a second intensity, the second intensity of the second pulsed laser beam being lower than the first intensity of the first pulsed laser beam,
wherein
the step (b) is performed after a predetermined delay time has elapsed from the step (a),
the delay time is such that the semiconductor film is irradiated with the second pulsed laser beam before the semiconductor film that melted after it has been irradiated with the first pulsed laser beam film is solidified, and
the delay time is set by adjusting lengths of the first and second optical paths.

US Pat. No. 10,991,580

LASER CRYSTALLIZING APPARATUS

SAMSUNG DISPLAY CO., LTD....

1. A laser crystallizing apparatus comprising:a first light source unit configured to emit a first input light having a linearly polarized laser beam shape;
a second light source unit configured to emit a second input light having a linearly polarized laser beam shape;
a polarization optical system configured to rotate the first input light and/or the second input light at a predetermined rotation angle;
an optical system configured to convert at least one of the first input light and the second input light, which pass through the polarization optical system, into an output light;
a stage on which a target substrate is seated and onto which the output light is directed; and
a monitoring unit configured to receive the first input light or the second input light from the polarization optical system and measure a laser beam quality thereof.

US Pat. No. 10,991,579

METHODS OF MAKING AND USING TIN OXIDE FILM WITH SMOOTH SURFACE MORPHOLOGIES FROM SPUTTERING TARGET INCLUDING TIN AND DOPANT

APPLIED MATERIALS, INC., ...

1. A sputtering method, comprising:flowing an oxygen containing gas and an inert gas into a physical vapor deposition processing chamber having a sputtering target including a tin and a dopant, wherein the dopant comprises 0.5% to 5% atomic percent of the sputtering target;
applying an electrical bias to the sputtering target to sputter atoms from the sputtering target; and
depositing a semiconductor layer on a substrate comprising the sputtered atoms, the semiconductor layer comprising the tin, the dopant, and the oxygen,
wherein at least a portion of the semiconductor layer comprises a tin oxide compound and a silicon compound.

US Pat. No. 10,991,578

FORMING A PLANAR SURFACE OF A III-NITRIDE MATERIAL

HEXAGEM AB, Hjarup (SE)

1. A semiconductor device including a nanostructure, comprising a planar layer of a column III-nitride semiconductor crystal that comprises:an array of epitaxially grown nanowire structures; and
semiconductor material disposed only on m-plane side surfaces of the nanowire structures, such that the semiconductor material extends only between upper ends of the nanowire structures and comprises column III atoms redistributed from the nanowire structures,
wherein:
the array of nanowire structures and the semiconductor material form a column III-nitride continuous planar layer having a planar c-plane upper surface comprising planar upper surfaces of the nanowire structures and the semiconductor material;
the semiconductor material is thinner than a height of the nanowire structures, such that the semiconductor material is disposed on only 20 to 70 percent of the length of the nanowire structures; and
the semiconductor material is arranged in level with upper ends of the nanowire structures at the planar c-plane upper surface of the of the continuous planar layer.

US Pat. No. 10,991,575

SEMICONDUCTOR DEVICE WITH PARTIAL REGIONS HAVING IMPUNITY CONCENTRATIONS SELECTED TO OBTAIN A HIGH THRESHOLD VOLTAGE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first electrode;
a second electrode, a direction from the first electrode toward the second electrode being aligned with a first direction;
a third electrode, a position in the first direction of the third electrode being between a position in the first direction of the first electrode and a position in the first direction of the second electrode;
a first layer including at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium, the first layer including first to sixth partial regions, a direction from the first partial region toward the first electrode, a direction from the second partial region toward the second electrode, and a direction from the third partial region toward the third electrode being aligned with a second direction crossing the first direction, the fourth partial region being between the third partial region and the third electrode in the second direction, a position in the first direction of the fifth partial region being between a position in the first direction of the first partial region and a position in the first direction of the fourth partial region, a position in the first direction of the sixth partial region being between the position in the first direction of the fourth partial region and a position in the first direction of the second partial region, a concentration of a first impurity in the fourth partial region being higher than a concentration of the first impurity in the fifth partial region and higher than a concentration of the first impurity in the sixth partial region; and
a second layer including AlxGa1-xN (0

US Pat. No. 10,991,573

UNIFORM DEPOSITION OF SIOC ON DIELECTRIC AND METAL SURFACES

ASM IP HOLDING B.V., Alm...

1. A plasma enhanced atomic layer deposition (PEALD) process for depositing SiOC on two or more different surfaces of a substrate comprising:providing a substrate comprising a first surface and a second surface, wherein the first surface comprises a different material from the second surface, and wherein the first surface is a metal surface and the second surface is a dielectric surface;
conducting two or more deposition cycles comprising alternately and sequentially contacting the first and second surfaces of the substrate with a first precursor comprising silicon and a second plasma reactant.

US Pat. No. 10,991,571

HIGH TEMPERATURE ATOMIC LAYER DEPOSITION OF SILICON OXIDE THIN FILMS

Versum Materials US, LLC,...

1. A process to deposit a silicon oxide film onto a substrate, comprising the steps of:a. providing a substrate in a reactor;
b. introducing into the reactor at least one silicon precursor;
c. purging the reactor with purge gas;
d. introducing an oxygen source into the reactor; and
e. purging the reactor with purge gas; andwherein steps b through e are repeated until a desired thickness of silicon oxide is deposited, wherein the process in conducted at one or more temperatures ranging from over 600 to 800° C. and one or more pressures ranging from 50 milliTorr (mT) to 760 Torr, wherein the at least one silicon precursor having a formula selected from the group consisting of methoxytrimethylsilane, ethoxytrimethylsilane, iso-propoxytrimethylsilane, tert-butoxytrimethylsilane, tert-pentoxytrimethylsilane, phenoxytrimethylsilane, acetoxytrimethylsilane, methoxytriethylsilane, ethoxytriethylsilane, iso-propoxytriethylsilane, tert-butoxytriethylsilane, tert-pentoxytriethylsilane, phenoxytriethylsilane, acetoxytriethylsilane, methoxydimethylsilane, ethoxydimethylsilane, iso-propoxydimethylsilane, tert-butoxydimethylsilane, tert-pentoxydimethylsilane, phenoxydimethylsilane, acetoxydimethylsilane, methoxydimethylphenylsilane, ethoxydimethylphenylsilane, iso-propoxydimethylphenylsilane, tert-butoxydimethylphenylsilane, tert-pentoxydimethylphenylsilane, phenoxydimethylphenylsilane, acetoxydimethylphenylsilane, dimethoxydimethylsilane, diethoxydimethylsilane, di-isopropoxydimethylsilane, di-t-butoxydimethylsilane, diacytoxydimethylsilane, dimethoxydiethylsilane, diethoxydiethylsilane, di-isopropoxydiethylsilane, di-t-butoxydiethylsilane, diacytoxydiethylsilane, dimethoxydi-isopropylsilane, diethoxydi-isopropylsilane, di-isopropoxydi-isopropylsilane, di-t-butoxydi-isopropylsilane, diacytoxydi-isopropylsilane, dimethoxymethylvinylsilane, diethoxymethylvinylsilane, di-isopropoxymethylvinylsilane, di-t-butoxymethylvinylsilane, diacytoxymethylvinylsilane, 1,1,3,4-tetramethyl-1-sila-2,5-dioxacyclopentane, 1,1,3,3,4,4-hexamethyl-1-sila-2,5-dioxacyclopentane, and mixtures thereof.

US Pat. No. 10,991,569

ELECTRODE ARRANGEMENT FOR A DISCHARGE LAMP, GAS DISCHARGE LAMP, PROTECTIVE FILM AND METHOD FOR PROVIDING A PROTECTIVE FILM ON AN ELECTRODE ARRANGEMENT

OSRAM GmbH, Munich (DE)

1. An electrode arrangement for a discharge lamp, the electrode arrangement comprising:an electrically conductive electrode unit comprising an electrode and an electrode plate, on which the electrode is arranged;
an electrically conductive connection unit for coupling to an energy source, wherein the connection unit comprises a connection unit plate;
a cylinder composed of an electrically nonconductive material, said cylinder being arranged between the electrode plate and the connection unit plate; and
at least one electrically conductive conduction film which is arranged on at least one part of an outer side of the cylinder and extends from the connection unit plate as far as the electrode plate and electrically conductively connects the connection unit plate and the electrode plate to one another;
wherein the electrode arrangement comprises a cap-shaped and integrally embodied protective film arranged on the electrode plate or connection unit plate, such that the protective film at least for the most part covers a plate side facing away from the cylinder and an outer lateral surface of the electrode plate or of the connection unit plate.

US Pat. No. 10,991,565

ION ANALYZER

SHIMADZU CORPORATION, Ky...

1. An ion analyzer, comprising:a) an ionization chamber to be maintained at atmospheric pressure;
b) an analysis chamber configured to analyze an ion generated in the ionization chamber;
c) a vacuum pump configured to evacuate an inside of the analysis chamber;
d) a capillary configured to allow the ionization chamber and the analysis chamber to communicate with each other;
e) a conductance changer that is a heater configured to heat the capillary, or is a heating-gas supply mechanism configured to supply a heating gas into the ionization chamber, the conductance changer configured to decrease a conductance of the capillary by adding heat, while keeping a state in which the analysis chamber is communicating with the ionization chamber through the capillary; and
f) a controller configured to operate the conductance changer during a time period of starting up the ion analyzer in such a manner as to decrease the conductance of the capillary by controlling the conductance changer to add the heat when a degree of vacuum in the analysis chamber is lower than a predetermined degree of vacuum.

US Pat. No. 10,991,560

SAMPLE INTRODUCTION SYSTEM FOR SPECTROMETERS

Micromass UK Limited, Wi...

1. A method of mass or ion mobility spectrometry comprising:supplying liquid comprising an analyte towards a heated surface, wherein the heated surface is heated to a temperature that is sufficiently high to cause a portion of the liquid to vaporise and form vapour between the heated surface and the liquid;
wherein the surface comprises a ratchet shaped profile such that the formation of said vapour repels said liquid away from the heated surface and focuses the analyte into an inlet aperture of a mass or ion mobility spectrometer; and
wherein the method comprises urging the liquid along the heated surface and varying a force with which the liquid is urged along the surface so as to control a rate of movement of the liquid along the heated surface and thereby control a rate of evaporation of the liquid.

US Pat. No. 10,991,557

REACTION CHAMBER, DRY ETCHING MACHINE AND ETCHING METHOD

HKC Corporation Limited, ...

1. A reaction chamber, comprising a cavity and an upper electrode disposed in the cavity, wherein the reaction chamber further comprises:a gas diffusion plate disposed directly above the upper electrode, and blocks the cavity; the gas diffusion plate is provided with a plurality of air holes, and is configured to introduce a process gas into the cavity in which the upper electrode is located; and
an adjustment assembly disposed on the gas diffusion plate and configured to adjust a ventilation area of each of the plurality of air holes;
a drive assembly connected to the adjustment assembly, and configured to drive the adjustment assembly for adjustment; and
a control assembly connected to the drive assembly, and configured to control an actuation of the drive assembly;
a first detection assembly, which is disposed above the gas diffusion plate, connected to the control assembly, and configured to detect the ventilation area of each of the plurality of air holes.

US Pat. No. 10,991,556

ADJUSTABLE EXTENDED ELECTRODE FOR EDGE UNIFORMITY CONTROL

APPLIED MATERIALS, INC., ...

1. A process kit for a substrate processing chamber, the process kit comprising:a ring having a first ring component and a second ring component, the first ring component interfaced with the second ring component such that the second ring component is movable relative to the first ring component to form a gap therebetween;
an adjustable tuning ring positioned beneath the second ring component and contacting a bottom surface of the second ring component, the adjustable tuning ring having a top surface and a bottom surface, the top surface of the adjustable tuning ring contacting the second ring component; and
an actuating mechanism interfaced with the bottom surface of the adjustable tuning ring, the actuating mechanism configured to actuate the adjustable tuning ring such that the gap between the first ring component and the second ring component is varied.

US Pat. No. 10,991,553

NANOSECOND PULSER THERMAL MANAGEMENT

Eagle Harbor Technologies...

1. A nanosecond pulser system comprising:a plurality of switches electrically coupled in parallel, each of the plurality of switches having a switch heat sink;
a transformer comprising:
at least one transformer core that includes a first core surface;
a plurality of primary windings electrically coupled with the plurality of switches; and
a plurality of secondary windings;
an output electrically coupled with the plurality of secondary windings, the output providing pulses having a voltage greater than about 1 kV, a pulse width less than about 1 ?s, and a pulse repletion frequency greater than about 20 kHz;
at least one switch cold plate physically coupled with the first switch surface of at least a subset of the plurality of switches, the at least one switch cold plate comprising a metal; and
a core cold plate physically coupled with the first core surface, the core cold plate comprising a metal.

US Pat. No. 10,991,550

MODULAR RECIPE CONTROLLED CALIBRATION (MRCC) APPARATUS USED TO BALANCE PLASMA IN MULTIPLE STATION SYSTEM

Lam Research Corporation,...

1. A circuit tuning radio frequency (RF) power, comprising:a low frequency (LF) to mid frequency (MF) tuning circuit including a variable low frequency to mid frequency (LF/MF) capacitor coupled in series with an LF/MF inductor, the LF/MF tuning circuit coupled between ground and a common node configured to receive an RF input supplying the RF power that is selectable, wherein in the LF/MF tuning circuit the LF/MF inductor is coupled to the common node and to the variable LF/MF capacitor, wherein in the LF/MF tuning circuit the variable LF/MF capacitor is coupled to the LF/MF inductor and to the ground; and
a high frequency (HF) tuning circuit coupled in parallel to the LF/MF tuning circuit between the ground and the common node, the HF tuning circuit including a variable HF capacitor coupled in series with an HF inductor, wherein in the HF tuning circuit the HF inductor is coupled to the common node and to the variable HF capacitor, wherein in the HF tuning circuit the variable HF capacitor is coupled to the HF inductor and to the ground,
wherein cross parallel isolation occurs between the LF/MF inductor of the LF/MF tuning circuit and the HF inductor of the HF tuning circuit when adjusting the variable LF/MF capacitor or the variable HF capacitor,
wherein the common node is coupled to an output node that is configured to provide an RF output.

US Pat. No. 10,991,546

ISOLATED LINAC RESONATOR PICKUP CIRCUIT

Applied Materials, Inc., ...

1. An ion implantation system, comprising:an ion source to generate ions;
a linear accelerator to accelerate the ions toward a workpiece, wherein the linear accelerator comprises one or more cavities;
a controller; and
a monitoring circuit, comprising:
a pickup loop disposed proximate one of the cavities;
a transceiver to transmit and receive information from the controller; wherein the monitoring circuit is electrically isolated from the controller and the linear accelerator.

US Pat. No. 10,991,545

METHOD AND DEVICE FOR SPATIAL CHARGED PARTICLE BUNCHING

NexGen Semi Holding, Inc....

1. A charged particle buncher comprising:a series of spaced apart electrodes arranged to generate a shaped electric field, the series comprising a first electrode, a last electrode and one or more intermediate electrodes; and
a waveform device attached to the electrodes and configured to apply a periodic potential waveform to each electrode independently in a manner so as to form a quasi-electrostatic time varying potential gradient between adjacent electrodes and to cause spatial distribution of charged particles that form a plurality of nodes and antinodes, wherein the nodes have a charged particle density and the antinodes have substantially no charged particle density;
wherein the charged particle buncher is configured to output the nodes and anti nodes in a charged particle beam with an energy greater than 500 keV.

US Pat. No. 10,991,541

DETECTOR FOR DETECTING INCIDENT ELECTRON BEAM

Canon Kabushiki Kaisha, ...

1. A detector, comprising:a semiconductor substrate which detects an incident electron beam;
a supporting substrate which is thicker than the semiconductor substrate and which supports the semiconductor substrate; and
an insulating film layer which is provided between the semiconductor substrate and the supporting substrate, wherein
at least one charge suppression film which is not electrically connected to the semiconductor substrate is formed inside the insulating film layer.

US Pat. No. 10,991,540

LIQUID CRYSTAL POLYMER FOR MOUNTING X-RAY WINDOW

Moxtek, Inc., Orem, UT (...

1. An x-ray window comprising:a thin film configured for transmission of x-rays;
a housing;
a pair of adhesive layers including a proximal adhesive layer and a distal adhesive layer, the thin film is sandwiched between the proximal adhesive layer and the distal adhesive layer, and the proximal adhesive layer is located closer to the housing than the distal adhesive layer;
the proximal adhesive layer is sandwiched between and provides a hermetic seal between the thin film and the housing;
the proximal adhesive layer includes an aromatic polyester liquid crystal polymer;
the distal adhesive layer includes liquid crystal polymer;
a ring located at an opposite side of the distal adhesive layer from the thin film, the ring being metallic; and
the proximal adhesive layer, the thin film, and the distal adhesive layer are sandwiched between the ring and the housing.

US Pat. No. 10,991,538

HIGH BRIGHTNESS X-RAY REFLECTION SOURCE

Sigray, Inc., Concord, C...

1. An x-ray target comprising:a thermally conductive substrate comprising a surface; and
a plurality of structures separate from one another and on or embedded in at least a portion of the surface, each of at least two structures of the plurality of structures comprising:
a thermally conductive first material in thermal communication with the substrate; and
at least one layer over the first material, the at least one layer comprising at least one second material different from the first material, the at least one second material configured to generate x-rays upon irradiation by electrons, the first materials of the at least two structures separate from one another and the at least one layers of the at least two structures separate from one another.

US Pat. No. 10,991,537

VERTICAL VACUUM CHANNEL TRANSISTOR

International Business Ma...

1. A vertical vacuum channel transistor, comprising:a sharp tip structure comprising two tip portions, wherein one tip portion of the two tip portions is an emitter of the vertical vacuum channel transistor and another tip portion of the two tip portions is a collector of the vertical vacuum channel transistor;
a vacuum channel between the two tip portions; anda gate of the vertical vacuum channel transistor, wherein a metal contact for each of the emitter, the collector and the gate of the vertical vacuum channel transistor is formed in a respective trench for each of the emitter, the collector and the gate of the vertical vacuum channel transistor that each extend downward in a vertical direction from a common top surface, wherein the two tip portions are formed from a silicon germanium (SiGe) material, wherein the silicon germanium (SiGe) material is a portion of an inverted T-shaped fin structure, and further comprising:a bottom spacer formed on a horizontal surface of the inverted T-shaped fin structure;
a high-K dielectric layer formed on sidewalls of the inverted T-shaped fin structure; and
a metal gate layer formed on the high-K dielectric layer, wherein the high-K dielectric layer is also formed on a top surface of the bottom spacer.

US Pat. No. 10,991,535

MINIATURE CIRCUITS BREAKER OPERATING MECHANISM AND MINIATURE CIRCUIT BREAKER

1. A miniature circuit breaker operating mechanism, comprising:an operating handle, configured to realize opening and closing of a circuit breaker;
a lock catch, configured to keep a moving contact of the circuit breaker in a closed state, and the operating handle and the lock catch being rotatably connected to a circuit breaker housing, respectively;
a first connecting link, being rotationally connected to the circuit breaker housing, and wherein the first connecting link and the lock catch share and rotate around a same rotating shaft, the moving contact being arranged on the first connecting link; and
a second connecting link, being connected with the operating handle, and being matched with the lock catch and the first connecting link to cooperate with a linkage structure,
wherein when the operating handle is rotating to a closed position, the second connecting link is driving the lock catch and the first connecting link to rotate to realize closing, and
wherein when the lock catch is tripped, a position limit of the moving contact and the first connecting link is released, so that the moving contact and the first connecting link are restored under action of a first elastic member.

US Pat. No. 10,991,534

LEAKAGE PROTECTOR

Dongguan City Tuocheng In...

1. A leakage protector, comprising a housing (7), the housing (7) being provided with an input terminal (11) and an output terminal (12), characterized in that the leakage protector further comprises a rotating member (2), a MCU (Microprogrammed Control Unit) (41), an electromagnet (3) and a leakage protection module (4) in the housing (7), the MCU (41) is configured to connect an external power supply through the input terminal (11) for power supply, the electromagnet (3) is configured to control connection and disconnection between the input terminal (11) and the output terminal (12);the rotating member (2) is rotatably disposed in the housing (7), a magnetic member (27) is provided in the rotating member (2), the electromagnet (3) is configured to attract the magnetic member (27) to drive the rotating member (2) to rotate;
one side of the rotating member (2) is provided with a first pressing member (21), the housing (7) is provided with a first immovable contact member (22) electrically connected to the output terminal (12) and a first elastic member (23) electrically connected to the output terminal (12), when the input terminal (11) is connected to the external power source, the input terminal (11) supplies power to the electromagnet (3), and the electromagnet (3) attracts the magnetic member (27) to drive the rotating member (2) to rotate, so that the first pressing member (21) is pressed against the first elastic member (23) to allow the first elastic member (23) to contact the first immovable contact member (22), thereby connecting the input terminal (11) and the output terminal (12);
when the input terminal (11) and the output terminal (12) are short-circuited or leak, the leakage protection module (4) sends a signal to the MCU (41) so that the MCU (41) controls the electromagnet (3) to disconnect the input terminal (11) from the output terminal (12).

US Pat. No. 10,991,531

ELECTROMAGNETIC RELAY

DENSO CORPORATION, Kariy...

1. An electromagnetic relay comprising:an exciting coil configured to form a magnetic field on energization;
a stationary core placed in a coil center hole formed in an inner diameter portion of the exciting coil and configured to form a magnetic circuit;
a yoke placed to cover an outer periphery of the exciting coil and an end of the exciting coil in an axial direction to form a magnetic circuit, the yoke having an opening portion formed in its one side in the axial direction correspondingly to a position of the stationary core;
a movable core facing the stationary core through the opening portion and configured to be attracted toward the stationary core on energization of the exciting coil; and
a return spring configured to urge the movable core in a direction opposite to a direction of attraction, wherein
a first gap is formed between the stationary core and the movable core on deenergization of the exciting coil,
a second gap is formed between the yoke and the movable core on deenergization of the exciting coil, the second gap allowing the yoke and the movable core to generate an attractive force therebetween in a direction to attract the movable core toward the stationary core on energization of the exciting coil, and
the return spring is made of a magnetic material and is placed to magnetically bridge the first gap or the second gap.

US Pat. No. 10,991,527

CONTACT PIECE FOR A HIGH-VOLTAGE CIRCUIT BREAKER AND METHOD FOR PRODUCING SAME

Siemens Aktiengesellschaf...

1. A method for producing a contact piece for a high-voltage circuit breaker, the method comprising the following steps:producing at least one contact pin including a contact shaft and a contact carrier as a monolithic contact element by placing the contact shaft in a mold for producing the contact carrier, and casting the contact shaft as an insert part into the contact carrier during casting;
forming at least part of the contact shaft of a material identical to a material of the contact carrier;
locally melting the contact shaft as a result of the casting of the contact carrier and resultant heating of the contact shaft; and
configuring the contact carrier to mechanically fasten the at least one contact pin in the high-voltage circuit breaker.

US Pat. No. 10,991,526

FUSE CUTOUT COVER WITH VARIABLE ROOFS FOR DIFFERENT FUSE CUTOUTS

Eco Electrical Systems, ...

1. A fuse cutout dielectric cover for a fuse cutout, the fuse cutout dielectric cover comprising:a first portion configured for at least covering a top of a first insulator in a first type of fuse cutout,
the first type of fuse cutout further comprising a first connector that provides electricity to a top end of a first fuse, a first metal hook assembly electrically contacting the first connector, and a first metal pull ring electrically connected to the first fuse;
a second portion extending from the first portion, the second portion having a roof portion configured for covering at least a portion of the first connector; and
an attachable roof extension for extending the roof portion to cover the top end of the first fuse.

US Pat. No. 10,991,524

INFORMATION HANDLING SYSTEM KEYBOARD DISCRETE ROW ILLUMINATION

Dell Products L.P., Roun...

1. A method for illumination of an information handling system keyboard having plural keys aligned in plural rows, the method comprising:disposing plural lightguides under the keyboard, at least one of the plural lightguides disposed under each of the plural rows of keys;
directing illumination into each of the lightguides from a side edge of the keyboard;
illuminating each key with an opening formed proximate each key in the lightguide disposed under the key;
detecting inactivity at the plural keys for a predetermined time; and
in response to the inactivity, directing illumination into only one of the plural lightguides.

US Pat. No. 10,991,522

MOVABLE CONTACT POINT, SWITCH WITH MOVABLE CONTACT POINT, AND EMBOSSED TAPE FOR CONTAINING MOVABLE CONTACT POINT

PANASONIC INTELLECTUAL PR...

1. A movable contact comprising a conductive member having an outer end having substantially a rectangular shape when viewed from above the conductive member, whereinthe conductive member includes:
a dome portion having an upper surface which is convex upward, a lower surface which is concave upward, and an outer border;
a flange having an outer border and an inner border which is connected to the outer border of the dome portion, the flange extending from the inner border of the flange to the outer border of the flange in a direction away from the dome portion when viewed from above the conductive member;
connection portions provided at four corners of the rectangular shape of the conductive member, respectively, each of the connection portions having a lower border and an upper border which is connected to the lower border of the flange, the each of the connection portions protruding from the upper border of the each of the connection portions downward to the lower border of the each of the connection portions; and
contact portions, respective one of the contact portions having an outer border and an inner border which is connected to the lower border of the each of connection portions, the respective one of the contact portions extending from the inner border of the respective one of the contact portions away from the flange when viewed from above the conductive member, and
the connection portion, a first boundary portion where the each of the connection portions is connected to the flange, and a second boundary portion where the each of the connection portions is connected to the respective one of the contact portions constitute a drawn portion.