US Pat. No. 10,600,954

METHOD FOR PRODUCING HERMETIC PACKAGE

NIPPON ELECTRIC GLASS CO....

1. A method of producing a hermetic package, the method comprising the steps of:preparing a ceramic base and forming a sealing material layer on the ceramic base;
preparing a glass substrate and arranging the ceramic base and the glass substrate so that the glass substrate is brought into contact with the sealing material layer on the ceramic base; and
irradiating the sealing material layer with laser light from a glass substrate side to seal the ceramic base and the glass substrate with each other through intermediation of the sealing material layer, to thereby provide a hermetic package,
wherein the ceramic base comprises a base part and a frame part formed on the base part and the sealing material layer is formed on a top of the frame part, and
wherein the forming a sealing material layer is performed by applying and firing a sealing material paste to form a sealing material layer formed of a sintered body of a sealing material on the ceramic base.

US Pat. No. 10,600,952

SURFACE ACOUSTIC WAVE SENSOR COATING

Pulmostics Limited, Dubl...

1. A surface acoustic wave sensor, comprising:a piezoelectric substrate defined by an outer surface;
a plurality of interdigitated electrodes mounted on the outer surface of the piezoelectric substrate, the electrodes being defined by one or more outer portions and an inner portion abutting the outer surface of the piezoelectric substrate; and
a coating layer on the outer surface of the piezoelectric substrate and the outer portions of the electrodes, the coating layer selected from a group consisting of a perfluoro-silane type compound, a perfluoro-trichloro-silane type compound, a perfluoro-acrylate type compound, polytetrafluoroethylene, and heptadecafluorodecyltrimethoxysilane.

US Pat. No. 10,600,950

STRUCTURALLY EMBEDDED AND INHOSPITABLE ENVIRONMENT SYSTEMS HAVING AUTONOMOUS ELECTRICAL POWER SOURCES

FACE INTERNATIONAL CORPOR...

1. An electrically-energized device, comprising:an electrical power source configured to provide electrical energy to power at least one of an electrically-energized sensor and an electrically-energized communication element, the electrical power source including one or more electrical power source components, at least one of the one or more electrical power source components comprising:
a first conductor formed of a first conductive material and having a first surface and a second surface, the first surface of the first conductor facing away from a build surface and being conditioned to have a first work function value,
a dielectric layer with a thickness in a range of 200 angstroms or less formed over the conditioned first surface of the first conductor; and
a second conductor formed of a second conductive material and having a first surface with a second work function value, and having a second surface, and being arranged over the dielectric layer such that the first surface of the second conductor faces the dielectric layer, the first conductor, the dielectric layer and the second conductor forming a layered structure of the electrical power source component;
a first electrical lead and a second electrical lead electrically connecting the at least one of the electrically-energized sensor and the electrically-energized communication element with the electrical power source;
the first work function value and the second work function value being in a range of 5.0 electron volts (eV) or less; and
the first work function value being at least 1.0 eV less than the second work function value;
wherein said electrical power source is disposed in proximity to, and is in thermal communication with, said at least one of an electrically-energized sensor and an electrically-energized communication element, such that thermal energy is communicated from said at least one of an electrically-energized sensor and an electrically-energized communication element to said electrical power source when said at least one of an electrically-energized sensor and an electrically-energized communication element receives electrical power from said electrical power source.

US Pat. No. 10,600,945

LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE

LG INNOTEK CO., LTD., Se...

1. A light emitting device package comprising:a first frame having a first through hole;
a second frame having a second through hole;
a body disposed between the first and second frames;
a light emitting device including a first bonding pad and a second bonding pad;
a first conductive part in the first through hole; and
a second conductive part in the second through hole,
wherein the first through hole passes through an upper surface and a lower surface of the first frame,
wherein the second through hole passes through an upper surface and a lower surface of the second frame,
wherein the first bonding pad faces the first frame and is overlapped with the first through hole in a vertical direction,
wherein the second bonding pad faces the second frame and is overlapped with the second through hole in the vertical direction, and
wherein the first bonding pad includes a first contact region that is in contact with the first conductive part on the first through hole and a first non-contact region that is not in physical contact with the first conductive part.

US Pat. No. 10,600,943

LIGHT EMITTING DEVICE INCLUDING LIGHT EMITTING UNIT ARRANGED IN A TUBE

EPISTAR CORPORATION, Hsi...

1. A light-emitting device, comprising:a carrier comprising a first portion and a second portion extended from the first portion;
a first electrode pad disposed on the first portion;
a plurality of light-emitting units disposed on the second portion;
a conductive line electrically connecting at least one of the plurality of light-emitting units and the first electrode pad;
a first reflective layer disposed on the conductive line without covering the plurality of light-emitting units; and
an optic structure comprising a wavelength converting material, contacting the plurality of light-emitting units without covering the first portion,
wherein the first portion is wider than the second portion in a top view.

US Pat. No. 10,600,942

LIGHT EMITTING DEVICE AND METHOD FOR PRODUCING THE SAME

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light emitting device, the method comprising:providing a structure comprising:
a substrate that includes a first wiring electrode and a second wiring electrode located at an upper surface of the substrate,
a light emitting element mounted on the upper surface of the substrate,
a wavelength conversion member disposed on or above an upper surface of the light emitting element,
a light-transmissive member disposed on an upper surface of the wavelength conversion member, and
a light reflective member that includes:
a portion disposed on each side surface of the light emitting element, the wavelength conversion member, and the light-transmissive member, and
a portion disposed on an upper surface of the light-transmissive member;
removing a portion of the light-transmissive member and the portion of the light reflective member that is disposed on the upper surface of the light-transmissive member so that the light-transmissive member is exposed from the light reflective member as viewed from an upper side of the structure.

US Pat. No. 10,600,941

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

AU OPTRONICS CORPORATION,...

1. A method for fabricating an electronic device, comprising:providing an optical layer, wherein the optical layer comprises a first surface and a second surface opposite to each other, and the first surface has a plurality of first convex lens structures;
forming an adhesive layer on the first convex lens structures;
picking up a plurality of light-emitting elements by using the first convex lens structures, wherein the light-emitting elements are bonded on the first convex lens structures through the adhesive layer; and
transferring, through the optical layer, the light-emitting elements bonded by the first convex lens structures to a driving-circuit substrate.

US Pat. No. 10,600,939

SOLID-STATE LIGHT EMITTING DEVICES AND SIGNAGE WITH PHOTOLUMINESCENCE WAVELENGTH CONVERSION AND PHOTOLUMINESCENT COMPOSITIONS THEREFOR

Intematix, Corporation, ...

1. A method of manufacturing a photoluminescent wavelength conversion component for a solid-state light emitting device, comprising:mixing a blue light excitable phosphor material and a light reflective material with a U.V. curable light transmissive binder to form a composition, wherein the blue light excitable phosphor material has an average particle size of 10 ?m to 20 ?m, wherein a weight percent loading of the light reflective material to the blue light excitable phosphor material is 0.01% to 10%, wherein the light reflective material has a particle size in a range of 0.1 ?m to 10 ?m, the blue light excitable phosphor material being excitable by light of wavelength 380 nm to 480 nm;
screen printing the composition as a layer over at least a part of a substrate, wherein the substrate and the light transmissive binder in a cured state have refractive indices that are within 0.02 of each other, and wherein the substrate is selected from the group consisting of: an acrylic, a polycarbonate, a silicone and a glass; and
at least partially curing the light transmissive binder.

US Pat. No. 10,600,937

PRECISE BONDLINE CONTROL BETWEEN LED COMPONENTS

LUMILEDS HOLDING B.V., (...

1. A device comprising:a light emitting diode;
a wavelength converting phosphor layer; and
an adhesive layer bonding the light emitting diode to the wavelength converting phosphor layer, the adhesive layer comprising:
a plurality of spacers dispersed in
a silicone matrix, the diameters of the spacers determining a thickness of the adhesive layer;
wherein the plurality of spacers have a size distribution with a mean diameter of between 1 and 5 microns and a coefficient of variation of less than 5%.

US Pat. No. 10,600,935

NITRIDE BASED SEMICONDUCTOR DEVICE WITH IMPROVED LATTICE QUALITY

1. A nitride based semiconductor device, comprising a buffer layer made from aluminum nitride (AlN);a three-dimensional stress tuning layer formed on said buffer layer and having a structure formula of AlxGayIn1-x-yN, where x?0, y>0, x+y?1;
a first-type semiconductor layer directly formed on said three-dimensional stress tuning layer and having a structure formula of Alx1Ga1-x1N, where x1 is between 0.5 and 1;
an active layer formed on said first-type semiconductor layer; and
a second-type semiconductor layer formed on said active layer,
wherein said buffer layer has an irregular top surface disposed in contact with said three-dimensional stress tuning layer, said buffer layer cooperating with said three-dimensional stress tuning layer to define an interface therebetween, said interface having a three-dimensional composition distribution,
wherein a lattice constant of said three-dimensional stress tuning layer ranges between a lattice constant of said buffer layer and a lattice constant of said first-type semiconductor layer.

US Pat. No. 10,600,932

MANUFACTURING METHOD OF OPTOELECTRONIC SEMICONDUCTOR DEVICE

ULTRA DISPLAY TECHNOLOGY ...

1. A manufacturing method of an optoelectronic semiconductor device, comprising:providing a matrix substrate, wherein the matrix substrate comprises a substrate and a matrix circuit disposed on the substrate;
transferring a plurality of micro-sized optoelectronic semiconductor elements from a temporary substrate to the matrix substrate, wherein the micro-sized optoelectronic semiconductor elements are separately disposed on the matrix substrate, and at least one electrode of each of the micro-sized optoelectronic semiconductor elements is electrically connected with the matrix circuit;
forming a protective layer completely covering the micro-sized optoelectronic semiconductor elements, wherein a height of the protective layer is greater than a height of the micro-sized optoelectronic semiconductor elements; and
grinding the protective layer until a residual on a back surface of each of the micro-sized optoelectronic semiconductor elements and the back surface are removed to expose a new surface.

US Pat. No. 10,600,930

PHOTODETECTOR AND LIDAR DEVICE USING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A photodetector comprising:a first semiconductor layer;
a porous semiconductor layer disposed on the first semiconductor layer; and
at least one photo-sensing element including a second semiconductor layer of a first conductivity type disposed in a region of the porous semiconductor layer and a third semiconductor layer of a second conductivity type disposed on the second semiconductor layer.

US Pat. No. 10,600,928

SYSTEMS WITH PHOTOVOLTAIC CELLS

Apple Inc., Cupertino, C...

8. An item, comprising:communications circuitry that communicates wirelessly with an electronic device;
a battery that provides power to the communications circuitry;
a flexible material that forms a curved outer surface of the item; and
a thin-film photovoltaic cell on the flexible material, wherein the thin-film photovoltaic cell conforms to the curved outer surface and wherein the flexible material has a conductive path that conveys electricity between the thin-film photovoltaic cell and the battery to charge the battery.

US Pat. No. 10,600,926

SOLAR CELL AND METHOD OF MANUFACTURING THE SAME

LG ELECTRONICS INC., Seo...

1. A solar cell comprising:a semiconductor substrate;
a first semiconductor region positioned at a front surface or a back surface of the semiconductor substrate and doped with impurities of a first conductive type;
a first electrode on the first semiconductor region;
a second electrode on the back surface of the semiconductor substrate; and
a second semiconductor region positioned between the semiconductor substrate and the second electrode and doped with impurities of a second conductive type opposite the first conductive type, the second semiconductor region having a plurality of concave-convex portions,
wherein the second electrode is formed of a metal foil, and an air gap is formed between the second electrode formed of the metal foil and a back surface of the second semiconductor region,
wherein the second electrode formed of the metal foil includes:
a contact portion on the back surface of the second semiconductor region; and
a non-contact portion that is spaced apart from the back surface of the second semiconductor region to form the air gap between the second electrode and the back surface of the second semiconductor region,
wherein the contact portion of the second electrode has a protrusion that projects toward a concave portion of the plurality of concave-convex portions of the second semiconductor region and is connected to the second semiconductor region, and
wherein the non-contact portion of the second electrode is spaced apart from the second semiconductor region by the air gap.

US Pat. No. 10,600,925

SOLAR BATTERY

Tsinghua University, Bei...

1. A solar battery comprising:a first electrode, a second electrode, a solar cell, an insulating layer and a gate electrode, wherein the solar cell is electrically connected to the first electrode and the second electrode, the gate electrode is insulated from the solar cell, the first electrode and the second electrode through the insulating layer, the solar cell comprises:
a semiconductor structure comprising a P-type semiconductor and an N-type semiconductor overlapped with each other and defining a first surface and a second surface;
a single carbon nanotube located on the first surface of the semiconductor structure and there is no other carbon nanotubes located on the first surface;
a transparent conductive film located on the second surface of the semiconductor structure, wherein the transparent conductive film is formed on the second surface by a depositing method or a coating method, the semiconductor structure is located between the carbon nanotube and the transparent conductive film, and the carbon nanotube, the semiconductor structure and the transparent conductive film are stacked with each other to form a multi-layered stereoscopic structure.

US Pat. No. 10,600,921

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a silicon carbide semiconductor device, comprising:implanting an impurity into a back surface of a semiconductor substrate formed from silicon carbide to thereby form in a surface layer of the back surface of the semiconductor substrate a high-concentration semiconductor region that has an impurity concentration that is higher than that of the semiconductor substrate, the high-concentration semiconductor region formed to a thickness greater than 200 nm;
forming a carbon protection film on a front surface semiconductor device structure;
performing heat treatment of the semiconductor substrate, including the carbon protection film, to activate the impurity in the back surface of the semiconductor substrate;
after performing the heat treatment of the semiconductor substrate to activate the impurity in the back surface of the semiconductor substrate, removing a portion of the back surface of the semiconductor substrate to reduce a thickness of the high-concentration semiconductor region to a thickness of 200 nm or less;
forming a metal electrode on a surface of the high-concentration semiconductor region; and
performing a heat treatment to form an ohmic contact of the metal electrode and the high-concentration semiconductor region, wherein
the impurity concentration of the high-concentration semiconductor region is a range from 1×1019/cm3 to 8×1020/cm3,
the impurity is implanted by acceleration energy of 150 keV or less, and
one of aluminum, phosphorus, arsenic, nitrogen, boron, magnesium, and gallium is implanted as the impurity.

US Pat. No. 10,600,918

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor comprising:
a gate electrode;
an oxide semiconductor layer overlapping with the gate electrode; and
a first gate insulating film and a second gate insulating film between the gate electrode and the oxide semiconductor layer,
wherein the first gate insulating film has a dielectric constant higher than the second gate insulating film, and
wherein the first gate insulating film comprises crystal.

US Pat. No. 10,600,913

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a substrate;
a first fin-type pattern disposed on the substrate;
a second fin-type pattern disposed on the substrate;
a first source/drain disposed on the first fin-type pattern;
a second source/drain disposed on the second fin-type pattern;
a first nanowire disposed on the first fin-type pattern and spaced apart from the first fin-type pattern, the first nanowire being connected with the first source/drain;
a second nanowire disposed on the first nanowire and spaced apart from the first fin-type pattern, the second nanowire being connected with the first source/drain, the second nanowire being spaced apart from the first nanowire;
a third nanowire disposed on the second fin-type pattern and spaced apart from the second fin-type pattern, the third nanowire being connected with the second source/drain;
a fourth nanowire disposed on the third nanowire and spaced apart from the second fin-type pattern, the fourth nanowire being connected with the second source/drain, the fourth nanowire being spaced apart from the third nanowire;
a first gate-all-around structure disposed on the first fin-type pattern, and encircling the first nanowire and the second nanowire; and
a second gate-all-around structure disposed on the second fin-type pattern, and encircling the third nanowire and the fourth nanowire,
wherein the first gate-all-around structure includes a first conductive film and a first gate insulating layer surrounding the first nanowire, and a second conductive film and a second gate insulating layer surrounding the second nanowire,
wherein the second gate-all-around structure includes a third conductive film and a third gate insulating layer surrounding the third nanowire, and a fourth conductive film and a fourth state insulating layer surrounding the fourth nanowire,
wherein each of the first and second gate insulating layers includes a first high-k insulating film and a first interfacial layer disposed on a periphery of the first nanowire and a periphery of the second nanowire, and
wherein each of the third and fourth gate insulating layers includes a second high-k insulating film and a second interfacial layer disposed on a periphery of the third nanowire and a periphery of the fourth nanowire,
wherein the first conductive film includes a first filling film and a first function film, and the second conductive film includes a second film and a second function film,
wherein the third conductive film includes a third film and a third function film, and the fourth conductive film includes a fourth filling film and a fourth function film,
wherein the first gate-all-around structure includes the first function film and the second function film each having a first Si concentration, and
wherein the second gate-all-around structure includes the third function film and the fourth function film each having a second Si concentration different from the first Si concentration.

US Pat. No. 10,600,912

SELF-ALIGNED REPLACEMENT METAL GATE SPACERLESS VERTICAL FIELD EFFECT TRANSISTOR

International Business Ma...

1. A structure comprising:a semiconductor nanowire having a channel segment between a source segment and a drain segment located in distal ends of the nanowire, wherein an entirety of the source segment is vertically above the channel segment and an entirety of the drain segment is vertically beneath the channel region and in direct physically contact with a surface of a substrate;
an epitaxial source region located laterally adjacent to the semiconductor nanowire and directly contacting an entirety of an outermost vertical sidewall of the source segment of the nanowire and a topmost surface of the source segment of the semiconductor nanowire;
an epitaxial drain region located laterally adjacent to the semiconductor nanowire and directly contacting an entirety of an outermost vertical surface of the drain segment of the nanowire; and
a gate stack comprising a gate dielectric layer having a first portion directly contacting an entirety of an outermost vertical sidewall of the channel segment of the nanowire and a conductive electrode formed over the gate dielectric layer, wherein the outermost vertical sidewall of the source segment, the outermost vertical sidewall of the drain segment and the outermost sidewall of the channel segment are vertically aligned to each other and wherein the gate stack has a topmost surface that is coplanar with a topmost surface of the epitaxial source region.

US Pat. No. 10,600,909

SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME

VANGUARD INTERNATIONAL SE...

1. A semiconductor device, comprising:an insulating layer disposed over a semiconductor substrate;
a semiconductor layer disposed over the insulating layer, having a first conductivity type;
an epitaxial layer disposed over the semiconductor layer, wherein the epitaxial layer has the first conductivity type;
a drift region disposed in the epitaxial layer and adjacent to an upper surface of the epitaxial layer, wherein the drift region has the first conductivity type;
a gate structure disposed over the epitaxial layer, wherein the gate structure partially covers the drift region;
a source region disposed in the epitaxial layer outside the drift region;
a drain region disposed in the drift region; and
a plurality of doped region pairs disposed in the drift region and arranged in a direction from the drain region toward the source region, wherein each of the plurality of doped region pairs comprises:
a first doped region having a second conductivity type opposite to the first conductivity type; and
a second doped region disposed over the first doped region, wherein the second doped region has the first conductivity type, wherein the second doped regions of the plurality of doped region pairs are located at a same depth.

US Pat. No. 10,600,907

HIGH VOLTAGE SEMICONDUCTOR DEVICE

MagnaChip Semiconductor, ...

1. A high voltage semiconductor device, comprising:a P-type first body region and a N-type drift region formed in a semiconductor substrate;
a gate electrode formed over the P-type first body region and the N-type drift region;
an insulation layer formed over the N-type drift region and overlapped with the gate electrode;
a first isolation layer formed spaced apart from the insulation layer;
an N-type first well region formed in the N-type drift region, wherein the N-type first well region is in contact with both the insulation layer and the first isolation layer; and
an N-type second well region formed spaced apart from the N-type first well region and being in contact with the first isolation layer,
wherein a depth of the N-type second well region and a depth of the N-type first well region with respect to a top surface of the semiconductor substrate are substantially similar.

US Pat. No. 10,600,904

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface;
a first wiring and a second wiring disposed on the first surface;
a first conductive film electrically connected to the first wiring; and
a gate electrode,
the semiconductor substrate having a source region of a first conductivity type located in the first surface, a drain region of the first conductivity type located in the second surface, a drift region of the first conductivity type located on the drain region, and a body region of a second conductivity type sandwiched between the source region and the drift region, the second conductivity type being a conductivity type opposite to the first conductivity type,
the drift region being disposed so as to surround the body region in a plan view,
the first wiring having a first portion disposed so as to extend across a boundary between the drift region and the body region in a plan view, and electrically connected to the drift region,
the gate electrode being insulated from and facing the body region sandwiched between the source region and the drift region,
the second wiring being electrically connected to the source region,
the first conductive film being insulated from and facing the second wiring,
wherein the first conductive film has one end portion which is terminated on the gate electrode, and the first wiring is connected with the one end portion of the first conductive film.

US Pat. No. 10,600,895

POWER DEVICE

RICHTEK TECHNOLOGY CORPOR...

1. A power device, comprising:an operation layer, including a top surface, a body region of a first conductive type and a drift region of a second conductive type, the body region and the drift region are connected in a lateral direction, to form a PN junction along a channel width direction between the body region and the drift region;
a gate, formed on the top surface, and the PN junction is located under the gate in a thickness direction;
a source of the second conductive type, the source being formed in a portion of the operation layer between the body region and the top surface;
a drain of the second conductive type, the drain being formed in a portion of the operation layer between the drift region and the top surface;
a first conduction portion, formed on the top surface for electrically connecting the source;
a conduction layer, formed on the first conduction portion and being electrically connected to the source via the first conduction portion; and
a plurality of second conduction portions, formed on the top surface and between the conduction layer and the drift region in a thickness direction, and arranged separately along the channel width direction, to electrically connect the drift region and the conduction layer, wherein at least one Schottky diode is formed by the second conduction portions and the drift region;
wherein the gate is located between the first conduction portion and the second conduction portions in the lateral direction; and
wherein when the power device is in a normal operation including a conduction state and a non-conduction state, a depletion region is continuously formed without break in the drift region, to encompass a junction between the drift region and the second conduction portions under the top surface.

US Pat. No. 10,600,892

INTEGRATED FERROELECTRIC CAPACITOR/ FIELD EFFECT TRANSISTOR STRUCTURE

Samsung Electronics Co., ...

1. A method of forming a semiconductor structure, the method comprising:providing a functional gate structure located on a surface of a semiconductor material portion and laterally surrounded by a middle-of-the-line (MOL) dielectric material;
recessing the functional gate structure to provide a capacitor cavity located above a remaining portion of the functional gate structure; and
forming a ferroelectric capacitor in the capacitor cavity, the ferroelectric capacitor comprising a bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure, wherein the bottom electrode structure is located entirely beneath the U-shaped ferroelectric material liner.

US Pat. No. 10,600,891

SMOOTHING SURFACE ROUGHNESS OF III-V SEMICONDUCTOR FINS FORMED FROM SILICON MANDRELS BY REGROWTH

INTERNATIONAL BUSINESS MA...

1. A III-V semiconductor vertical fin device, comprising:a spacer layer on a substrate, wherein the material of the spacer layer is a flowable oxide;
a vertical fin on the spacer layer, wherein the vertical fin is a binary or ternary III-V semiconductor material;
a gate structure over a middle section of the vertical fin.

US Pat. No. 10,600,890

CONTACT TO METAL GATE ISOLATION STRUCTURE

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising:a substrate;
a semiconductor fin on the substrate;
an isolation region on sidewalls of the semiconductor fin and having an upper surface lower than an upper surface of the semiconductor fin;
a gate structure on a portion of the semiconductor fin and on a first portion of the isolation region, wherein the portion of the semiconductor fin covered by the gate structure is referred to as a first region, and wherein a second portion of the isolation region disposed on at least one of two opposite sides of the gate structure is referred to as a second region, the first region having an upper surface higher than an upper surface of the second region; and
a first spacer layer on a sidewall of the gate structure; and
a second spacer layer on the second region and on a sidewall of the of the first region,
wherein the first spacer layer comprises a portion on the second spacer layer, and the first and second spacer layers have different materials.

US Pat. No. 10,600,885

VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE AND DRAIN JUNCTIONS

INTERNATIONAL BUSINESS MA...

1. A method of forming a fin field effect transistor device, comprising:forming a plurality of vertical fins on a substrate;
forming a bottom source/drain layer adjacent to the plurality of vertical fins;
growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins;
forming a dummy gate liner on the doped layer and the bottom source/drain layer;
forming a dummy gate fill on the dummy gate liner;
forming a protective cap layer on the dummy gate fill; and
removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins.

US Pat. No. 10,600,883

VERTICAL TRANSPORT FETS HAVING A GRADIENT THRESHOLD VOLTAGE

International Business Ma...

1. A semiconductor structure comprising:a vertical transport nFET and a laterally adjacent vertical transport pFET, wherein
the vertical transport nFET comprises:
at least one semiconductor fin present in an nFET device region and extending upwards from a surface of a base semiconductor substrate;
a bottom n-doped source/drain structure located on the base semiconductor substrate and contacting sidewall surfaces of a lower portion of the at least one semiconductor fin, wherein the bottom n-doped source/drain structure serves as a drain region;
a gate dielectric layer located above the bottom n-doped source/drain structure and contacting another portion of the sidewall surfaces of the at least one semiconductor fin;
an nFET gate structure located laterally adjacent a sidewall of the gate dielectric layer, the nFET gate structure comprising a TiN liner having a first threshold voltage and a TiN portion having a second threshold voltage that is greater than the first threshold voltage; and
a top n-doped source/drain structure located on an upper portion of the at least one semiconductor fin and serving a source region; and
the vertical transport pFET comprises:
at least one semiconductor fin present in a pFET device region and extending upwards from the surface of the base semiconductor substrate;
a bottom p-doped source/drain structure located on the base semiconductor substrate and contacting sidewall surfaces of a lower portion of the at least one semiconductor fin, wherein the bottom p-doped source/drain structure serves as a drain region;
a gate dielectric layer located above the bottom p-doped source/drain structure and contacting another portion of the sidewall surfaces of the at least one semiconductor fin;
a pFET gate structure located laterally adjacent a sidewall of the gate dielectric layer, the pFET gate structure comprising a TiN liner having the second threshold voltage and a TiN portion having a third threshold voltage that is greater than the second threshold voltage; and
a top p-doped source/drain structure located on an upper portion of the at least one semiconductor fin and serving as a source region.

US Pat. No. 10,600,881

TUNNELING FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF

Huawei Technologies Co., ...

1. A fabrication method of a tunneling field-effect transistor, wherein the method comprises:providing a semiconductor substrate;
forming semiconductor fins on the semiconductor substrate;
etching the semiconductor fins to obtain a semiconductor nanosheet, wherein the semiconductor nanosheet is vertically disposed;
performing first-type doping on a first substrate of the semiconductor substrate to form a drain region, wherein the drain region is located above a second substrate of the semiconductor substrate, the first substrate is a part of the semiconductor substrate, is located under the semiconductor nanosheet, and is in contact with the semiconductor nanosheet, and the second substrate is a part, of the semiconductor substrate, remaining after the first substrate is excluded from the semiconductor substrate;
depositing a first dielectric material on the drain region and the second substrate, wherein the first dielectric material covers the drain region;
depositing at least one layer of dielectric materials to form a dielectric layer on a surface of the semiconductor nanosheet, wherein the at least one layer of dielectric materials comprises a second dielectric material, the dielectric layer comprises at least a gate dielectric layer formed by using the second dielectric material, and the dielectric layer surrounds a channel;
depositing a conductive material to form a gate metal layer on a surface of the gate dielectric layer, wherein the gate metal layer surrounds the gate dielectric layer;
etching the dielectric layer and the gate metal layer; and
performing second-type doping on an exposed part of the nanosheet to form a source region.

US Pat. No. 10,600,880

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Panasonic Intellectual Pr...

1. A semiconductor device comprising:a substrate having a main surface inclined in an off-direction from a {0001} surface; and
a semiconductor layer disposed on the main surface of the substrate,
wherein:
the semiconductor layer has a level difference for alignment mark,
an epitaxial layer is provided in the level difference for alignment mark and on a main surface of the semiconductor layer in a region adjacent to the level difference for alignment mark, and
where an upstream side is an off-angle upstream side and a downstream side is an off-angle downstream side in a direction with the off-direction projected on the main surface of the substrate, the epitaxial layer is disposed on a first portion of the main surface of the semiconductor layer, the first portion being situated on the off-angle upstream side of the level difference for alignment mark and on a second portion of the main surface of the semiconductor layer, the second portion being situated on the off-angle downstream side of the level difference for alignment mark, in the region adjacent to the level difference for alignment mark, and a value of |WL?WR| is 1 ?m or less, in which WL represents a distance from a center of the level difference for alignment mark to a boundary between an off-angle upstream side corner portion of the level difference for alignment mark and a main surface or a {0001} facet plane generated on the main surface, and WR represents a distance from the center of the level difference for alignment mark to a boundary between an off-angle downstream side corner portion of the level difference for alignment mark and the main surface or the {0001} facet plane generated on the main surface.

US Pat. No. 10,600,876

METHODS FOR CHAMFERING WORK FUNCTION MATERIAL LAYERS IN GATE CAVITIES HAVING VARYING WIDTHS

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a first cavity having a first width and a second cavity having a second width greater than said first width in a dielectric material;
forming a first conformal layer in said first and second cavities;
forming spacers in said first and second cavities, said spacers covering a first portion of said first conformal layer positioned on sidewalls of said first and second cavities, exposing a second portion of said first conformal layer positioned on said sidewalls of said first and second cavities, and exposing bottom portions of said first conformal layer positioned on lowermost surfaces of said first and second cavities;
forming a material layer in said first and second cavities to cover said bottom portions of said first conformal layer;
performing a first etch process to remove said second portion of said first conformal layer positioned on said sidewalls of said first and second cavities;
removing said spacers and said material layer to expose said bottom portions of said first conformal layer; and
forming a fill material in said first and second cavities.

US Pat. No. 10,600,874

SCHOTTKY BARRIER DIODE

TAMURA CORPORATION, Toky...

1. A Schottky barrier diode, comprising:a Ga2O3-based substrate of n+-type conductivity; and
a Ga2O3-based epitaxial layer of n?-type conductivity on a principal surface of the Ga2O3-based substrate,
wherein the Ga2O3-based epitaxial layer is configured to have a thickness of 0.402 ?m to 33.3 ?m when a reverse withstand voltage VRM is set at 100V to 10000V.

US Pat. No. 10,600,873

SEMICONDUCTOR DEVICE HAVING A JUNCTION PORTION CONTACTING A SCHOTTKY METAL

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device, comprising:a first conductive-type SiC semiconductor layer having a front surface and a rear surface;
an anode electrode having a multi-layered structure being in contact with the front surface of the SiC semiconductor layer; and
a cathode electrode formed on the rear surface of the SiC semiconductor layer,
wherein a Schottky junction is formed between the anode electrode and the front surface of the SiC semiconductor layer,
fine recesses are formed only in a Schottky junction portion of the SiC semiconductor layer,
a part of the anode electrode is embedded in the fine recesses, and
the multi-layered structure includes a first layer, a second layer on the first layer, and a third layer on the second layer.

US Pat. No. 10,600,872

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide semiconductor device, comprising:a silicon carbide semiconductor substrate of a first conductivity type, having a front surface;
a first silicon carbide layer of the first conductivity type provided on the front surface of the substrate, the first silicon carbide layer having a first surface, and a second surface opposite to the first surface and facing the front surface of the substrate;
a second silicon carbide layer of the first conductivity type selectively provided in the first surface of the first silicon carbide layer, the second silicon carbide layer having a first surface, and a second surface opposite to the first surface and facing the first surface of the first silicon carbide layer;
a third silicon carbide layer of a second conductivity selectively provided on the first surface of the second silicon carbide layer, the third silicon carbide layer having a first surface, and a second surface opposite to the first surface and facing the first surface of the second silicon carbide layer;
a trench at least penetrating the third silicon carbide layer and reaching the second silicon carbide layer; and
a gate insulating film provided on a surface of the trench, the gate insulating film having a first surface, and a second surface opposite to the first surface and facing the trench, a part of the first surface facing the second silicon carbide layer, wherein
fluorine and chlorine are both undetectable
in the gate insulating film,
at a boundary between the first surface of the gate insulating film and the second silicon carbide layer, or
at a boundary between the trench and the second surface of the gate insulating film.

US Pat. No. 10,600,869

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SHINDENGEN ELECTRIC MANUF...

1. A silicon carbide semiconductor device comprising:an epitaxial layer of a first conductive type;
a first semiconductor region of a first conductive type formed on a surface of the epitaxial layer of the first conductive type, and having higher impurity concentration than that of the epitaxial layer of the first conductive type;
a body region of a second conductive type formed at a position deeper than that of the first semiconductor region of the first conductive type;
a channel region of a second conductive type formed such that
the channel region of the second conductive type
penetrates the first semiconductor region of the first conductive type from a surface of the epitaxial layer of the first conductive type,
reaches the body region of the second conductive type, and
defines
a first part of the first semiconductor region of the first conductive type formed entirely on the body region of the second conductive type and
a second part of the first semiconductor region of the first conductive type formed partially on the body region of the second conductive type, wherein
the first part of the first semiconductor region of the first conductive type and the channel region of the second conductive type define a first boundary surface, and
the second part of the first semiconductor region of the first conductive type and the channel region of the second conductive type define a second boundary surface,
the channel region of the second conductive type having lower impurity
concentration than that of the body region of the second conductive type;
a second semiconductor region of a first conductive type formed toward the body region of the second conductive type from the surface of the epitaxial layer of the first conductive type, the second semiconductor region of the first conductive type having higher impurity concentration than that of the first semiconductor region of the first conductive type,
a body contact region of a second conductive type formed such that the body contact region of the second conductive type penetrates the first semiconductor region of the first conductive type from the surface of the epitaxial layer of the first conductive type and reaches the body region of the second conductive type, the body contact region of the second conductive type having higher impurity concentration than that of the body region of the second conductive type; and
a gate electrode formed on at least the channel region of the second conductive type with a gate insulating film interposed therebetween, wherein
the channel region of the second conductive type and the second semiconductor region of the first conductive type are formed at a planar position where the first part of the first semiconductor region of the first conductive type remains between the channel region of the second conductive type and the second semiconductor region of the first conductive type and separates the channel region of the second conductive type from the second semiconductor region of the first conductive type, and
the second boundary surface is positioned on the body region of the second conductive type as viewed in a plan view.

US Pat. No. 10,600,866

STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF

QUALCOMM Incorporated, S...

1. A chip, comprising:a first gate;
a second gate;
a first source;
a first source contact disposed on the first source;
a metal interconnect above the first source contact and the first gate;
a first gate contact electrically coupling the first gate to the metal interconnect;
a first via electrically coupling the first source contact to the metal interconnect;
a power rail; and
a second via electrically coupling the first source contact to the power rail;
wherein the second gate is between the first source and the first gate, and the metal interconnect passes over the second gate.

US Pat. No. 10,600,865

MATERIALS AND METHODS FOR THE PREPARATION OF NANOCOMPOSITES

THE UNIVERSITY OF CHICAGO...

1. A colloidal material comprising nanoparticles and inorganic capping agents, wherein each inorganic capping agent is bound to an outer surface of a nanoparticle, and the inorganic capping agents comprise HnMOy, where n=0, 1, or 2, y=2, 3, or 4, M is a metal, metalloid or phosphorus and HnMOy is negatively charged.

US Pat. No. 10,600,858

ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting display device comprising:a panel comprising a display unit on which an image is formed and a pad unit comprising a plurality of terminals connected to the display unit and arranged in a plurality of rows on a substrate; and
a flexible circuit board comprising metal wirings arranged in a plurality of layers so as to be respectively connected in correspondence to the plurality of rows of terminals in the pad unit and being coupled to the pad unit,
wherein the pad unit comprises a one-row terminal zone in which only terminals in a single row from among the plurality of rows of terminals electrically connect the metal wirings to the display unit.

US Pat. No. 10,600,857

ORGANIC LIGHT EMITTING DISPLAY PANEL WITH AN INCREASED WIDTH OF WIRING

BOE TECHNOLOGY GROUP CO.,...

1. An organic light emitting display panel comprising a display region and a non-display region, the display region provided with a gate wiring, a data wiring, an anode wiring and a cathode, wherein the cathode is disposed in a central region of the display region, the gate wiring, the data wiring, and the anode wiring are disposed along an edge region of the display region; the gate wiring has a first gate wiring parallel to a first direction, the data wiring has a first data wiring parallel to the first direction, the anode wiring has a first anode wiring parallel to the first direction, the first direction is a direction from the display region to the non-display region, a width of at least one of the first gate wiring, the first data wiring, and the first anode wiring, is gradually increased in the first direction,wherein a shape of at least one of the first gate wiring, the first data wiring, and the first anode wiring is trapezoid, a longer bottom edge of the trapezoid is disposed adjacent to the non-display region, and
wherein the data wiring is located over the gate wiring, the anode wiring is located over the data wiring, and the cathode is above the anode wiring.

US Pat. No. 10,600,856

DISPLAY DEVICE WITH A FLEXIBLE SUBSTRATE

LG Display Co., Ltd., Se...

1. A display device, comprising:a first flexible substrate;
a low reflection layer on the first flexible substrate;
a second flexible substrate on the low reflection layer;
a thin film transistor and an organic light emitting diode on the second flexible substrate;
an upper protective member configured to encapsulate the thin film transistor and the organic light emitting diode; and
an electrically conductive interconnection configured to electrically connect the low reflection layer with a surface of the upper protective member,
wherein the low reflection layer is provided between the first flexible substrate and the second flexible substrate, and the low reflection layer is formed of a conductive material, and
wherein the low reflection layer is exposed through at least one exposure hole disposed in an inorganic insulating layer.

US Pat. No. 10,600,852

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A method of manufacturing an organic light-emitting display apparatus, the method comprising:providing a substrate on which a display area is defined, wherein the display area is configured to display an image;
forming a thin film transistor on the display area of the substrate;
forming a via-insulating layer covering the thin film transistor;
forming a conductive material on the via-insulating layer;
forming a second insulating material on the conductive material;
exposing the conductive material by irradiating light onto the second insulating material and removing a portion of the second insulating material;
forming a pixel electrode and a wire that is spaced apart from the pixel electrode by etching an exposed portion of the conductive material;
forming a pixel-defining layer covering an edge area of the pixel electrode, and a spacer covering the wire, by reflowing the second insulating material;
forming an organic emission layer on the pixel electrode; and
forming a counter electrode on the organic emission layer;
wherein a height between the via-insulating layer and a top of the spacer is greater than a height between the via-insulating layer and a top of the pixel defining layer.

US Pat. No. 10,600,851

ORGANIC LIGHT-EMITTING DISPLAY PANEL AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE

SHANGHAI TIANMA AM-OLED C...

1. An organic light-emitting display panel, comprising:an array substrate including a plurality of driving elements;
a plurality of organic light-emitting components corresponding to the plurality of driving elements; and
a plurality of fingerprint identification units,
wherein:
each organic light-emitting component includes an anode and a cathode, and light emitted by the organic light-emitting component emits away from the array substrate,
a pixel defining layer is disposed between adjacent organic lighting emitting components,
a fingerprint identification unit is disposed at a non-display area between organic light-emitting components and on a side of the pixel defining layer away from the array substrate, and
a periphery of the fingerprint identification unit is provided with a light-shielding layer having a height equaling to or greater than a height of the fingerprint identification unit in a direction perpendicular to a surface of the array substrate, and the light-shielding layer blocks the fingerprint identification unit from illumination by the light emitted by the organic light-emitting component.

US Pat. No. 10,600,850

METHOD OF FABRICATING FILM, METHOD OF FABRICATING ARRAY SUBSTRATE, AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A method of fabricating a film, comprising:filling ink droplets containing a solvent and material constituting the film into pixel units of an array substrate;
freezing the ink droplets on the array substrate; and
sublimating the solvent of the ink droplets on the array substrate,
wherein the pixel units of the array substrate are separated by a pixel define layer and arranged in a matrix, and
sublimating the solvent of the ink droplets on the array substrate comprises:
placing the array substrate into a vacuum chamber;
adjusting a pressure of the vacuum chamber to a value not exceeding a triple point pressure of the solvent of the ink droplets;
adjusting a temperature of the vacuum chamber to a value greater than a triple point temperature of the solvent of the ink droplets; and
sublimating the solvent of the ink droplets on the array substrate in vacuum.

US Pat. No. 10,600,849

DISPLAY DEVICE HAVING A REFLECTING AREA

LG DISPLAY CO., LTD., Se...

1. A display device comprising:a lower substrate including emitting areas and reflecting areas;
an upper substrate opposite the lower substrate;
light-emitting structures on the emitting areas of the lower substrate; and
changeable reflective structures on the upper substrate, the changeable reflective structures overlapping with the reflecting areas of the lower substrate,
wherein each of at least two among the changeable reflective structures includes a first changeable electrode, a changeable transmitting layer, a second changeable electrode and a reflective pattern, which are sequentially stacked on the upper substrate,
wherein each of at least two among the reflective patterns is disposed between neighboring emitting areas of the lower substrate, so that the reflective patterns do not overlap with the emitting areas of the lower substrate in a cross-section view, and
wherein a transmissivity of the changeable transmitting layer is changed by a voltage difference between the first changeable electrode and the second changeable electrode.

US Pat. No. 10,600,848

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device comprising:a plurality of pixels including a first pixel and a second pixel that is adjacent to the first pixel, each of the plurality of pixels including a plurality of subpixels,
wherein the first pixel shares at least one of the plurality of subpixels with a first adjacent pixel so that portions of the at least one subpixel that is shared are respectively allocated to the first pixel and the first adjacent pixel, and the second pixel shares at least one of the plurality subpixels with a second adjacent pixel so that portions of the at least one subpixel that is shared are respectively allocated to the second pixel and the second adjacent pixel, and the first pixel and the second pixel are vertically symmetrical.

US Pat. No. 10,600,847

ORGANIC LIGHT EMITTING DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting display device, comprising:a substrate;
a first protection layer disposed on the substrate;
a plurality of conductive lines disposed on the first protection layer and extending substantially in a first direction;
a second protection layer disposed on the conductive lines;
a first electrode disposed on the second protection layer and overlapping at least a part of the conductive lines;
a pixel defining layer disposed on the second protection layer and including an opening exposing at least a part of the first electrode;
an organic light emission layer disposed on the first electrode; and
a second electrode disposed on the organic light emission layer,
wherein the plurality of conductive lines comprises a first conductive line, a second conductive line, and a third conductive line,
wherein the opening is divided into a first polygon and a second polygon with respect to an imaginary straight line that passes through the opening at a maximum length in the first direction,
wherein a planar area of the first polygon is different from a planar area of the second polygon,
wherein the imaginary straight line extend along and overlaps with the first conductive line,
wherein an overlap area between the first polygon and the first conductive line and the second conductive line and an overlap area between the second polygon and the first conductive line and the third conductive line have a ratio equal to about 1:1, and
wherein the opening is asymmetric with respect to the imaginary straight line.

US Pat. No. 10,600,845

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device, comprising:a plurality of global bit lines extending along a first direction;
a pair of word lines separated from each other, extending along a second direction;
a bit line between the pair of word lines, extending along a third direction different from the first direction and the second direction;
variable resistivity layers between the bit line and each word line of the pair of word lines, the variable resistivity layers functioning as a memory element;
a selector between the bit line and one of the plurality of global bit lines,
wherein the selector includes:
a semiconductor layer coupled with the bit line and the one of the plurality of global bit lines, and
a pair of gates on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating layers therebetween; and
a control circuit configured to perform respective operations of reading, writing, and erasing on the memory element.

US Pat. No. 10,600,844

MEMORY STRUCTURES HAVING REDUCED VIA RESISTANCE

Intel Corporation, Santa...

1. A memory structure, comprising:a memory cell;
a via;
a dielectric material separating the memory cell from the via;
a metal ceramic composite material layer on the memory cell and the dielectric material; and
a conductive layer on the metal ceramic composite material layer and the via, wherein the conductive layer is in direct contact with an upper surface of the via;
wherein either:
the via extends beyond an upper surface of the metal ceramic composite material layer into the conductive layer to a distance not greater than 100 nm; or
the memory structure further comprises a barrier layer disposed between the metal ceramic composite material layer and the conductive layer, said barrier layer having an upper surface that is planar with an upper surface of the via.

US Pat. No. 10,600,842

MEMORY CELLS, MAGNETIC MEMORY CELLS, AND SEMICONDUCTOR DEVICES

Micron Technology, Inc., ...

1. A magnetic memory cell, comprising:a magnetic cell core, comprising:
a first magnetic region adjacent a tunnel barrier material;
a second magnetic region adjacent the tunnel barrier material;
a seed material adjacent the first magnetic region and an intermediary material adjacent the second magnetic region,
wherein sidewalls of the first magnetic region, the second magnetic region, the tunnel barrier material, and the seed material are aligned; and
an oxide material over sidewalls of only a portion of the magnetic cell core, the oxide material over sidewalls of the tunnel barrier material, sidewalls of the seed material free of the oxide material, wherein the magnetic cell core exhibits a homogeneous crystal structure with an increasing purity in a direction toward a laterally central portion of the magnetic cell core;
wherein the oxide material comprises an oxide of a material with which the oxide material is in contact.

US Pat. No. 10,600,841

MEMORY DEVICE HAVING SOURCE CONTACTS LOCATED AT INTERSECTIONS OF LINEAR PORTIONS OF A COMMON SOURCE, ELECTRONIC SYSTEMS, AND ASSOCIATED METHODS

Micron Trechnology, Inc.,...

15. A method of forming an array of memory cells, comprising:forming an access device having an access line extending in a first direction;
forming a cell contact operably coupled to the access device;
forming a magnetic tunnel junction region over the cell contact;
forming a data line operably coupled to the magnetic tunnel junction region, the data line extending in a second direction transverse to the first direction; and
forming a common source comprising first linear portions and second linear portions extending transverse to one another and extending at an acute angle to each of the first direction and the second direction, the common source operably coupled to source contacts of the memory cells of the array, wherein each source contact is located at an intersection of a first linear portion and a second linear portion of the common source.

US Pat. No. 10,600,839

SEMICONDUCTOR DEVICE INCLUDING OXIDE SEMICONDUCTOR

Semiconductor Energy Labo...

1. A semiconductor device comprising:memory elements arranged in a matrix of n rows and m columns, where each of n and m is a natural number of 2 or more,
wherein each of the memory elements comprise a transistor whose channel formation region comprises an oxide semiconductor, and
wherein the semiconductor device performs vector matrix multiplication while canceling an effect due to dark current of the memory elements.

US Pat. No. 10,600,835

ELECTRONIC MODULE AND METHOD OF MANUFACTURING THE SAME

Samsung Electro-Mechanics...

1. An electronic module comprising:a first component comprising a first surface;
a second component disposed to be spaced apart from the first surface by a distance of about 40 ?m to about 200 ?m;
an inner spacer spacing the first component and the second component apart from each other;
an outer spacer spacing the first component and the second component apart from each other, the outer spacer surrounding the inner spacer and being spaced apart from the inner spacer; and
an adhesive portion disposed on the first surface of the first component between the first surface of the first component and bonding surfaces of the inner spacer and the outer spacer, and disposed on the first surface of the first component along a space between the inner spacer and the outer spacer,
wherein a spacing distance between the inner spacer and the outer spacer is 50% or less of an overall width of the inner spacer and the outer spacer, and
wherein an overall width of the adhesive portion is 100% to 150% of the overall width of the inner spacer and the outer spacer.

US Pat. No. 10,600,828

SOLID-STATE IMAGING ELEMENT, SENSOR APPARATUS, AND ELECTRONIC DEVICE

SONY CORPORATION, Tokyo ...

1. A solid-state imaging element including a pixel having a transistor comprising:a gate electrode having at least one fin portion formed so as to be buried from a planar portion planarly formed on a surface of a semiconductor substrate toward an inside of the semiconductor substrate;
a channel portion provided across a source and a drain so as to be in contact with a side surface of the tin portion via an insulating film,
wherein the transistor is formed to have a width of the channel portion narrower than a depth of the fin portion; and
a shallow trench isolation provided to surround the transistor and isolating the transistor from an outside, and
wherein a low concentration region having impurity concentration lower than in the channel portion is provided in the semiconductor substrate between the shallow trench isolation and the outer side surface of the fin portion.

US Pat. No. 10,600,817

THIN FILM TRANSISTOR AND FLAT DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a thin film transistor (TFT), the TFT including:
a scan line,
an active layer including an oxide semiconductor, the active layer having a first region, a second region, and a third region that are linearly and sequentially aligned along a first direction, the second region being a channel region between the first region and the third region,
an insulating layer between the active layer and the scan line, wherein the scan line, the insulating layer, and the active layer are sequentially stacked on a substrate along a third direction, the insulating layer covering the scan line, the third direction being substantially perpendicular to the first direction,
a first electrode having a first contact portion contacted with the first region of the active layer, and
a second electrode having a second contact portion contacted with the third region of the active layer;
a first capacitor electrode on a substrate;
a second capacitor electrode connected to the second electrode of the TFT, the second capacitor electrode being insulated from the first capacitor electrode; and
a pixel electrode connected to the second electrode of the TFT and to the second capacitor electrode,
wherein the scan line includes a straight portion extending along the first direction,
wherein the first contact portion and the second contact portion overlap with edge portions of the scan line in a second direction, the second direction being substantially perpendicular to the first direction and the third direction,
wherein the straight portion of the scan line includes a first portion that overlaps the first and second contact portions, and second portions that do not overlap the first and second electrodes and disposed at both sides of the first portion in the first direction, and
wherein a width of the first electrode and a width of the second electrode in the second direction are larger than widths of the second portions of the straight portion in the second direction,
the first contact portion overlaps an end portion of the first region of the active layer at one side of the active layer in the first direction, and
the second contact portion overlaps an end portion of the third region of the active layer at an opposite side of the active layer in the first direction.

US Pat. No. 10,600,816

ARRAY SUBSTRATE COMPRISING GRAPHENE CONDUCTIVE LAYER AND MANUFACTURING METHOD OF THE SAME

SHENZHEN CHINA STAR OPTOE...

1. A manufacturing method of an array substrate, comprising:providing a substrate;
depositing a bottom gate on the substrate, and depositing a gate insulating layer covering the bottom gate;
disposing a carbon nanotube active layer on the gate insulating layer;
forming a graphene conductive layer in contact with the active layer on two opposite sides of the carbon nanotube active layer, wherein the graphene conductive layer forms a gap on the carbon nanotube active layer to expose a partial surface of the carbon nanotube active layer; and
forming a source and a drain respectively on the conductive layer on the two opposite sides of the carbon nanotube active layer;
wherein the carbon nanotube active layer is prepared by soaking and rinsing the substrate covered with the gate insulating layer with acetone, methanol and isopropanol, and then blowing with nitrogen, the substrate covered with the gate insulating layer is immersed in a carbon nanotube solution to deposit a carbon nanotube film, after the deposition is complete, the substrate is taken out and baked at 150° C. for 30 min to obtain a carbon nanotube network-like thin film, and the excess carbon nanotubes are removed by oxygen plasma; and
wherein a photoresist is used to protect the gap on the carbon nanotube active layer, the substrate is immersed into the graphene conductive layer solution to deposit the graphene conductive layer, after the deposition was completed, the substrate was baked at 150° C. for 30 minutes to remove excess graphene conductive layer solution for drying the substrate.

US Pat. No. 10,600,814

ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising a display area and a non-display area, the non-display area comprising:at least one first wiring configured to be connected with a signal line within the display area and with a driver integrated circuit disposed within the non-display area; and
at least one second wiring configured to cause photoresist to be uniformly distributed during a spin coating process of the photoresist,
wherein the first wiring comprises a first V-shaped corner, a salient of the first V-shaped corner being directed towards the display area, and the second wiring is arranged to prevent the photoresist from accumulating towards the first V-shaped corner or to guide the photoresist flowing out from the first V-shaped corner to be dispersed.

US Pat. No. 10,600,812

MANUFACTURING METHOD OF ARRAY SUBSTRATE

Au Optronics Corporation,...

1. A manufacturing method of an array substrate, comprising:forming a plurality of scan lines on a substrate, the substrate having a pixel region and a fan-out region;
forming a plurality of data lines;
forming a plurality of transistors, wherein each of the transistors is electrically connected to the corresponding scan line and the corresponding data line;
forming a plurality of common electrodes;
forming a plurality of pixel electrodes, wherein each of the pixel electrodes is electrically connected to the corresponding transistor;
forming a plurality of first fan-out lines in the fan-out region;
forming a plurality of second fan-out lines in the fan-out region; and
forming a plurality of third fan-out lines in the fan-out region, wherein each of the third fan-out lines comprises:
a transparent conductive layer; and
an auxiliary conductive layer, disposed on the transparent conductive layer and in contact with the transparent conductive layer;
wherein the third fan-out lines and the common electrodes are formed by a same photomask.

US Pat. No. 10,600,810

BACKSIDE FIN RECESS CONTROL WITH MULTI-HSI OPTION

Intel Corporation, Santa...

1. A semiconductor device, comprising:a first fin comprising:
a first active channel region on a top portion of the first fin;
a first sub-channel region underneath the first active channel region; and
a first active channel height from a top surface of the first active channel region to a top surface of the first sub-channel region; and
a second fin comprising:
a second active channel region on a top portion of the second fin;
a second sub-channel region underneath the second active channel region of the second fin, wherein the first and second sub-channel regions comprise an insulator material;
a second active channel height from a top surface of the second active channel region to a top surface of the second sub-channel region,
wherein the first and second fins have a same height and the first active channel height is substantially different from the second active channel height; and
etch stop layers between the active channel regions and the sub-channel regions, wherein first surfaces of the etch stop layers are in contact with the active channel region and second surfaces of the etch stop layers are in contact with the insulator material of the first and second sub-channel regions.

US Pat. No. 10,600,805

VERTICAL MEMORY DEVICES WITH COMMON SOURCE INCLUDING ALTERNATELY REPEATED PORTIONS HAVING DIFFERENT WIDTHS

Samsung Electronics Co., ...

1. A vertical memory device, comprising:gate lines spaced apart from each other on a substrate in a first direction vertical to a top surface of the substrate;
channels extending through ones of the gate lines in the first direction; and
opening structures extending through the gate lines on the substrate, each of the opening structures including first and second openings alternately and repeatedly arranged in a second direction parallel to the top surface of the substrate, the first and second openings having first and second widths, respectively, in a third direction that is parallel to the top surface of the substrate and crossing the second direction, the second width being greater than the first width, and the opening structures being spaced apart from each other in the third direction,
wherein at least one of the channels is disposed between the second openings of neighboring ones of the opening structures in the third direction, the second openings facing each other in the third direction.

US Pat. No. 10,600,801

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a substrate having a first doped region with a first conductive dopant;
a plurality of stack-structures of nonvolatile memory cells spaced apart on the substrate, each of the plurality of stack-structures comprising:
a plurality of gate patterns vertically spaced apart from one another on the substrate;
a vertical active pattern extending through each of the plurality of stack-structures across from the plurality of gate patterns; and
a gate dielectric layer extending between the plurality of gate patterns and the vertical active pattern, extending in a horizontal direction parallel with a top surface of the substrate, and covering a lower surface and an upper surface of each of the plurality of gate patterns,
wherein the first doped region contacts a sidewall of the vertical active pattern without the gate dielectric layer between the vertical active pattern and the first doped region.

US Pat. No. 10,600,798

MANUFACTURING METHOD OF NON-VOLATILE MEMORY STRUCTURE

Powerchip Semiconductor M...

1. A manufacturing method of a non-volatile memory structure, comprising:forming memory cells on a substrate;
forming at least one isolation layer between the memory cells;
forming at least one shield electrode on the at least one isolation layer, wherein the at least one shield electrode is electrically connected to a source line; and wherein the non-volatile memory structure is a vertical non-volatile memory structure, and a manufacturing method of the vertical non-volatile memory structure comprises: forming a stacked layer on the substrate, wherein the stacked layer comprises first sacrificial layers and second sacrificial layers that are alternately stacked; forming a first opening in the stacked layer, wherein the first opening exposes the substrate; forming a charge storage structure layer on a sidewall of the first opening; forming a channel layer on the charge storage structure layer; forming a patterned hard mask layer on the stacked layer, wherein the patterned hard mask layer covers the charge storage structure layer and the channel layer; forming a second opening in the stacked layer by using the patterned hard mask layer as a mask, wherein the second opening exposes the substrate; removing the second sacrificial layers exposed by the second opening to form third openings; forming gate structures in the third openings; removing the first sacrificial layers exposed by the second opening to form fourth openings; conformally forming the at least one isolation layer on a surface of the fourth openings and on the gate structures; and forming the at least one shield electrode on the at least one isolation layer in the fourth openings and forming the source line connected to the at least one shield electrode and the substrate in the second opening.

US Pat. No. 10,600,797

NOR MEMORY CELL WITH VERTICAL FLOATING GATE

GREENLIANT IP LLC, Santa...

1. An electrically erasable programmable nonvolatile memory cell comprising:a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, the trench region comprising a bottom portion and a sidewall portion adjacent a trench in the semiconductor substrate;
a channel region between the first substrate region and the bottom portion of the trench region, the channel region having:
a first channel portion adjacent to the first substrate region;
a second channel portion adjacent to the first channel portion and the trench region; and
a third channel portion adjacent to the second channel portion and comprising the sidewall portion of the trench region;
an electrically conductive control gate insulated from and disposed over the first channel portion;
an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, the floating gate having:
a first floating gate portion disposed inside the trench; and
a second floating gate portion longer than the first floating gate portion, disposed above the trench and extending away from the trench, the second floating gate portion being electrically connected to the first floating gate portion on a first end and having a tip on a second end, wherein a first portion of the tip has a smaller cross section than a second portion of the tip;
an insulation region disposed over the second channel portion between the control gate and the second floating gate portion;
an electrically conductive source line electrically connected to the trench region, the source line extending away from the substrate and forming a first capacitive coupling with the floating gate;
a dielectric layer between the floating gate and the source line; and
an electrically conductive erase gate insulated from and disposed over the tip of the second floating gate portion.

US Pat. No. 10,600,792

PROGRAMMABLE LOGIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a programmable logic element comprising a look-up table; and
a memory element comprising:
a switch; and
a node comprising:
an electrode electrically connected to the programmable logic element;
an insulating film over the electrode;
a first wiring over the electrode and the insulating film; and
a second wiring over the electrode and the insulating film,
wherein the memory element is configured to hold configuration data written through the switch to the node, and
wherein the look-up table is configured such that logic operation executed by the look-up table varies depending on the configuration data.

US Pat. No. 10,600,790

MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

UNITED MICROELECTRONICS C...

1. A manufacturing method of a semiconductor memory device, comprising:providing a semiconductor substrate, wherein a memory cell region and a peripheral region are defined on the semiconductor substrate;
forming a dielectric layer on the semiconductor substrate;
forming a first trench on the memory cell region, wherein the first trench penetrates the dielectric layer;
forming a second trench on the peripheral region, wherein the second trench penetrates the dielectric layer;
forming a metal conductive layer, wherein the first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench; and
forming a gate dielectric layer on the semiconductor substrate, wherein the gate dielectric layer is at least partially formed on the peripheral region, and at least a part of the gate dielectric layer is located between the first metal gate structure and the semiconductor substrate.

US Pat. No. 10,600,788

INTEGRATED ASSEMBLIES COMPRISING STUD-TYPE CAPACITORS

Micron Technology, Inc., ...

1. An integrated assembly, comprising:conductive pillars supported by a base and included within first electrodes of capacitors; the conductive pillars having first upper surfaces;
dielectric liners along outer surfaces of the conductive pillars; the dielectric liners having second upper surfaces;
conductive liners along the dielectric liners and included within second electrodes of the capacitors; the conductive liners having third upper surfaces;
the first upper surfaces being beneath the third upper surfaces;
insulative pads being over the first upper surfaces and having fourth upper surfaces;
the second upper surfaces, third upper surfaces and fourth upper surfaces being substantially coplanar with one another; and
a conductive plate extending across the insulative pads and laterally outwardly from the conductive liners; the conductive plate electrically coupling the conductive liners to one another.

US Pat. No. 10,600,786

METHOD FOR FABRICATING A DEVICE WITH A TENSILE-STRAINED NMOS TRANSISTOR AND A UNIAXIAL COMPRESSION STRAINED PMOS TRANSISTOR

STMICROELECTRONICS Inc, ...

1. A method for making a transistor device with at least a P type transistor provided with a transistor channel structure with uniaxial compressive strain, the method comprising:forming a mask on a first region of a silicon surface layer of a strained silicon-on-insulator (sSOI) type of substrate comprising a support layer, an insulating layer separating the support layer from the surface layer, the surface layer being based on a strained semiconducting silicon material, strained with a biaxial tensile strain, the mask being formed from plural elongated mask blocks located on first zones of the surface layer, the first zones and the mask blocks having a length L1 measured parallel to a first direction and a width W1 measured parallel to a second direction perpendicular to the first direction, the width W1 being such that W1 making at least one ion implantation of the surface layer through the elongated openings in the mask, so as to make the second zones amorphous and to induce a relaxation of the first zones in the second direction while keeping the first zones strained in the first direction;
recrystallising the second zones of the surface layer after making the at least one ion implantation of the surface layer; then
making a second mask formed of elements located on each side of and adjacent to the mask blocks; then
removing the mask blocks between the elements of the second mask so as to form cavities exposing the first zones; then
germanium-enriching the first zones, so as to induce a compressive strain of the first zones in the second direction and to have the first zones relaxed in the first direction; and then
forming replacement gate blocks in the cavities on the first zones of the surface layer, the pate blocks extending parallel to the second direction.

US Pat. No. 10,600,784

SEMICONDUCTOR INTEGRATED CIRCUIT AND LOGIC CIRCUIT

Socionext Inc., Kanagawa...

1. A semiconductor integrated circuit comprising a standard cell having a NAND function, the standard cell comprising:first and second n-channel transistors connected together in series between an output node and a ground node, and
first and second p-channel transistors connected together in parallel between the output node and a power supply node,
wherein the first n-channel transistor is comprised of n fin transistor(s) where n is an integer equal to or greater than one, the first n-channel transistor having its gate connected to a first input node, the n fin transistor(s) forming the first n-channel transistor comprising a first fin extending in a first direction and a first gate extending in a second direction perpendicular to the first direction,
the second n-channel transistor is comprised of m fin transistors where m is an integer greater than n, the second n-channel transistor having its gate connected to a second input node, the m fin transistors forming the second n-channel transistor comprising a second fin extending in the first direction and a second gate extending in the second direction,
the first p-channel transistor having its gate connected to the first input node, and
the second p-channel transistor having its gate connected to the second input node.

US Pat. No. 10,600,783

SELF-CUT SIDEWALL IMAGE TRANSFER PROCESS

International Business Ma...

1. A semiconductor structure comprising:a set of first structures formed on a first region of a silicon substrate, wherein each of the first structures comprises a mandrel having a first hardmask disposed on a top surface thereof, wherein the mandrel has a first width and a first height;
a set of second structures formed on a second region of the silicon substrate, wherein each of the second structures comprises a mandrel having a second hardmask disposed on a top surface thereof and an oxide layer disposed on the hardmask, wherein the mandrel has a second width and a second height;
a set of third structures formed on a third region of the silicon substrate, wherein each of the third structures comprises a mandrel having a third hardmask disposed on a top surface thereof, wherein the mandrel has a third width and a third height;
wherein the set of first structures and the set of third structures are separated by the set of second structures and further wherein the second width is greater than the first width and the third width.

US Pat. No. 10,600,780

3D CHIP SHARING DATA BUS CIRCUIT

Xcelsis Corporation, San...

1. A three-dimensional (3D) circuit comprising:a first integrated circuit (IC) die comprising a first semiconductor substrate and a first set of interconnect layers defined on the first semiconductor substrate;
a second IC die vertically stacked with the first IC die and comprising a second semiconductor substrate and a second set of interconnect layers defined on the second semiconductor substrate; and
a data input/output (I/O) circuit defined on the second semiconductor substrate to receive data from and to supply data to at least a first external circuit outside of the 3D circuit,
wherein data signals from the data I/O circuit are supplied from the second IC die to a first set of circuits defined on the first IC die.

US Pat. No. 10,600,779

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND POWER CONVERSION APPARATUS

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a first main surface and a second main surface, and including a transistor region forming a transistor extending from said first main surface to said second main surface and a diode region forming a diode extending from said first main surface to said second main surface; and
a first electrode disposed on said first main surface of said semiconductor substrate over said transistor region and said diode region, wherein
said semiconductor substrate includes a MOS gate structure on a first main surface side in said transistor region,
said semiconductor device includes:
an interlayer dielectric covering a gate electrode of said MOS gate structure, and having a contact hole exposing a semiconductor layer of said MOS gate structure; and
a barrier metal disposed in said contact hole,
said first electrode enters said contact hole, is in contact with the semiconductor layer of said MOS gate structure through said barrier metal in said contact hole, and is in direct contact with a semiconductor layer in said diode region of said semiconductor substrate,
said barrier metal includes titanium nitride, titanium carbide, or titanium silicide, and
no barrier metal is disposed on said first main surface of said semiconductor substrate in said diode region.

US Pat. No. 10,600,778

METHOD AND APPARATUS OF FORMING HIGH VOLTAGE VARACTOR AND VERTICAL TRANSISTOR ON A SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a semiconductor device comprising:receiving a substrate structure including a substrate, the substrate structure further including a first bottom source/drain and a first fin formed on a vertical transistor portion of the substrate and a second bottom source/drain and a second fin formed on a varactor portion of the substrate, the substrate structure further including a bottom spacer formed on the first bottom source/drain of the vertical transistor portion and the second bottom source/drain of the varactor portion;
applying a mask to the portion of the bottom spacer formed on the first bottom source/drain of the vertical transistor portion;
removing the portion of the bottom spacer formed on the second bottom source/drain of the varactor portion;
removing the mask from the portion of the bottom spacer formed on the first bottom source/drain of the vertical transistor portion; and
depositing a gate oxide on the vertical transistor portion and the varactor portion.

US Pat. No. 10,600,777

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor device, comprising:a semiconductor body including a first semiconductor layer of a first conductivity type;
a first electrode provided on the semiconductor body;
a second electrode provided on the semiconductor body with a first insulating film interposed, the second electrode being provided at a position surrounded with the first electrode when viewed from above, and being separated from the first electrode;
a third electrode provided on the semiconductor body at a position surrounded with the second electrode when viewed from above, and being separated from the second electrode; and
a control electrode provided between the semiconductor body and the first electrode, the control electrode being electrically connected to the second electrode, the control electrode being electrically insulated from the semiconductor body with a second insulating film interposed, and being electrically insulated from the first electrode with a third insulating film interposed,
the semiconductor body further including a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, and a sixth semiconductor layer of the first conductivity type,
the second semiconductor layer being selectively provided between the first semiconductor layer and the first electrode,
the third semiconductor layer being selectively provided between the second semiconductor layer and the first electrode and electrically connected to the first electrode,
the fourth semiconductor layer including a major portion and an outer edge portion, the major portion being provided between the first semiconductor layer and the second electrode and between the first semiconductor layer and the third electrode, the outer edge portion being provided between the first semiconductor layer and the first electrode,
the fifth semiconductor layer being selectively provided in the fourth semiconductor layer, the fifth semiconductor layer being positioned between the outer edge portion of the fourth semiconductor layer and the first electrode, and including a portion electrically connected to the first electrode,
the sixth semiconductor layer being provided at a position away from the fifth semiconductor layer in the fourth semiconductor layer, the sixth semiconductor layer being positioned between the major portion of the fourth semiconductor layer and the third electrode, and including a portion electrically connected to the third electrode,
the control electrode being disposed at a position capable of facing the first semiconductor layer, the second semiconductor layer and the third semiconductor layer with the second insulating film interposed.

US Pat. No. 10,600,776

DEVICE AND METHOD FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION

NXP B.V., Eindhoven (NL)...

1. An electrostatic discharge (ESD) protection device, the ESD protection device comprising:a first bipolar device connected to a first node;
a second bipolar device connected to the first bipolar device and to a second node; and
a metal-oxide-semiconductor (MOS) device connected to the first and second nodes and to the first and second bipolar devices and configured to shunt current in response to an ESD pulse received between the first and second nodes, wherein the first bipolar device, the second bipolar device, and the MOS device are formed on a deep well structure, wherein the deep well structure comprises a deep N-well layer that is formed on top of a substrate layer and below an N-well, and wherein the N-well is in contact with the deep N-well layer and in contact with the substrate layer.

US Pat. No. 10,600,774

SYSTEMS AND METHODS FOR FABRICATION OF GATED DIODES WITH SELECTIVE EPITAXIAL GROWTH

QUALCOMM Incorporated, S...

1. An integrated circuit (IC) comprising:a logic region comprising at least one Field-Effect Transistor (FET), the at least one FET comprising a plurality of FET fins, each of the plurality of FET fins comprising a respective FET fin epitaxial bump; and
an input/output (I/O) region comprising at least one I/O gated diode, the at least one I/O gated diode comprising a plurality of diode fins, wherein at least one of the plurality of diode fins comprises a source and a drain, and wherein at least one of the source and the drain does not comprise an epitaxial bump.

US Pat. No. 10,600,773

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device manufacturing method comprising:forming a chip stacked body by stacking a second semiconductor chip on a first surface of a first semiconductor chip, a first bump electrode being between and contacting the first surface and the second semiconductor chip, and stacking a third semiconductor chip on the second semiconductor chip, a second bump electrode being between and contacting the second semiconductor chip and the third semiconductor chip;
stacking a fourth semiconductor chip on the chip stacked body;
connecting the first bump electrode to a first through silicon via of the second semiconductor chip by reflowing the first bump electrode;
connecting the second bump electrode to the first through silicon via of the second semiconductor chip and a second through silicon via of the third semiconductor chip by reflowing the second bump electrode;
connecting the chip stacked body to a first substrate by using a first adhesive such that the first surface of the first semiconductor chip faces a second surface of the first substrate;
connecting the chip stacked body to a second substrate by using a second adhesive and a third bump electrode, the second adhesive being provided between the chip stacked body and the second substrate, in a direction perpendicular to the second substrate, and between the third bump electrode and the fourth semiconductor chip in a direction parallel to the second substrate, such that a gap is left between the chip stacked body and the second substrate and between the fourth semiconductor chip and the second substrate; and
after connecting the chip stacked body to the second substrate by using the second adhesive and the third bump electrode, sealing the second surface, the first, second, third, and fourth semiconductor chips with a resin that also enters the gap left between the chip stacked body and the second substrate and between the fourth semiconductor chip and the second substrate.

US Pat. No. 10,600,772

SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL CHIPS CONNECTED BY HYBRID BONDING METHOD

Micron Technology, Inc., ...

1. An apparatus comprising:a first semiconductor chip comprising:
a first plurality of memory cell arrays, each disposed on an associated one of intersections of first and second signal lines;
a first plurality of bonding electrodes electrically connected respectively to corresponding first signal lines; and
a first plurality of switches configured to respectively couple one of the second signal lines to a corresponding one of the first plurality of bonding electrodes; and
a second semiconductor chip comprising:
a second plurality of memory cell arrays, each disposed on an associated one of intersections of third and fourth signal lines;
a second plurality of bonding electrodes respectively coupled to the first plurality of bonding electrodes of the first semiconductor chip and electrically connected respectively to corresponding third signal lines;
a third plurality of bonding electrodes electrically connected respectively to corresponding third signal lines and coupled to a logic chip; and
a second plurality of switches configured to respectively couple one of the fourth signal lines to a corresponding one of the second and third plurality of bonding electrodes;
wherein the first and second plurality of switches are configured to turn on/off so that one memory cell array of the first semiconductor chip and the second semiconductor chip is accessed through a corresponding one of the third plurality of bonding electrodes to the logic chip.

US Pat. No. 10,600,771

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a first interconnection including a first extending portion that extends in a first direction, and a first curved portion that is curved with respect to the first extending portion;
a second interconnection including a second extending portion that extends in the first direction and is adjacent to the first extending portion in a second direction perpendicular to the first direction, and a second curved portion that is curved with respect to the second extending portion;
a first plug provided on the first curved portion, or provided on a first non-opposite portion that is included in the first extending portion and is not opposite to the second extending portion in the second direction; and
a second plug provided on the second curved portion, or provided on a second non-opposite portion that is included in the second extending portion and is not opposite to the first extending portion in the second direction.

US Pat. No. 10,600,770

SEMICONDUCTOR DICE ASSEMBLIES, PACKAGES AND SYSTEMS, AND METHODS OF OPERATION

Micron Technology, Inc., ...

1. An assembly, comprising:an interposer comprising a glass material;
a semiconductor die comprising a logic die having a proximity coupling on a side of the interposer; and
at least one other semiconductor die comprising a proximity coupling configured for
communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer, the at least one other die comprising a number of stacked memory dice, each of the logic die and the memory dice comprising a proximity coupling for mutual signal communication;
wherein:
the logic die is in electrically conductive communication with conductive traces of the interposer for communicating power and ground/bias;
the number of stacked memory dice comprises memory dice stacked in stair-step fashion with exposed bond pads on treads of stairs; and
further comprising wire bonds respectively extending from the exposed bond pads to conductive traces of the interposer for communicating power and ground/bias; and
the interposer comprises an optical waveguide for signal communication with an optical I/O of the logic die and extends to a socket for optical signal communication with higher level packaging.

US Pat. No. 10,600,769

ELECTRONIC COMPONENT

AIROHA TECHNOLOGY GROUP, ...

1. An electronic component, comprising:a substrate comprising a metal layer and at least one via connecting with the metal layer;
an III-V die disposed on the metal layer; and
a silicon die stacked to the III-V die, the silicon die comprises a plurality of conductive contacts on an active surface of the silicon die, and the silicon die is coupled to the III-V die in a face-down orientation and electrically connected to the III-V die via the conductive contacts,
wherein the active surface of the silicon die faces toward the substrate.

US Pat. No. 10,600,767

MAKING SEMICONDUCTOR DEVICES BY STACKING STRATA OF MICRO LEDS

Hong Kong Beida Jade Bird...

1. A method for fabricating a micro-LED display chip, comprising:providing a substrate supporting an array of pixel drivers; and
fabricating two or more strata stacked on top of the substrate and pixel drivers, with a planar interface between adjacent strata, by:
for a bottom stratum: bonding, using metal layers, an unpatterned epitaxial structure on top of the substrate and pixel drivers; and for any other stratum: bonding, using metal layers, an unpatterned epitaxial structure on top of a previous stratum;
patterning the epitaxial structure to form micro LEDs and patterning the bonding metal layers to form metal pads, some of the metal pads functioning as lower contact metal pads electrically connected to bottoms of the micro LEDs;
for all strata except a top stratum, filling and planarizing the stratum to create a planar top interface, the top interface including electrical connections to tops of the micro LEDs;
filling and planarizing the top stratum to create a planar top interface, the planar top interface including electrical connections to tops of the micro LEDs; and
fabricating a common electrode on top of the planar top interface of the top stratum, the tops of the micro LEDs electrically connected to the common electrode, wherein the common electrode is further electrically connected to one or more of the metal pads of the bottom stratum.

US Pat. No. 10,600,766

DUAL-CHANNEL HEAT-CONDUCTING ENCAPSULATION STRUCTURE AND ENCAPSULATION METHOD OF A SOLID-STATE PHOSPHOR INTEGRATED LIGHT SOURCE

FUJIAN CAS-CERAMIC OPTOEL...

1. A solid-state phosphor integrated light source, comprising a solid-state phosphor, a transparent organic silica gel, a plurality of LED chips, a plurality of heat-conducting columns, and a substrate,wherein each of the plurality of heat-conducting columns has a first end in contact with the solid-state phosphor and a second end in contact with the substrate so as to form a pap between the solid-state phosphor and the substrate, wherein the plurality of LED chips are disposed on the substrate inside the gap, the transparent organic silica gel fills a space in the gap, and
wherein each of the plurality of heat-conducting columns is located in an interspace between two or more of the plurality of LED chips.

US Pat. No. 10,600,763

MULTI-DECK THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

Yangtze Memory Technologi...

1. A method for forming a three-dimensional (3D) memory device, comprising:forming a first dielectric deck comprising a first plurality of interleaved sacrificial layers and dielectric layers above a first substrate;
forming a first channel structure extending vertically through the first dielectric deck;
forming a heterogeneous interface in a second substrate;
bonding the second substrate and the first substrate in a face-to-face manner;
splitting a single-crystal silicon layer from the second substrate along the heterogeneous interface in the second substrate to leave the single-crystal silicon layer bonded on the first dielectric deck;
patterning a first inter-deck plug comprising single-crystal silicon in the single-crystal silicon layer, such that the first inter-deck plug is above and in contact with the first channel structure;
forming a second dielectric deck comprising a second plurality of interleaved sacrificial layers and dielectric layers above the first inter-deck plug;
forming a second channel structure extending vertically through the second dielectric deck, such that the second channel structure is above and in contact with the first inter-deck plug; and
forming a first memory deck and a second memory deck each comprising interleaved conductor layers and the dielectric layers by replacing the sacrificial layers in the first dielectric deck and the second dielectric deck with the conductor layers.

US Pat. No. 10,600,761

NANOSCALE INTERCONNECT ARRAY FOR STACKED DIES

Invensas Corporation, Sa...

1. A method of fabricating a microelectronic assembly, comprising:forming an insulating layer comprising a diblock copolymer on a substrate, the insulating layer including a self-assembled nanoscale matrix array of a first polymer and a second polymer;
removing the second polymer from the nanoscale matrix array to reveal a plurality of nanoscale holes in the nanoscale matrix array;
filling the plurality of nanoscale holes with one or more conductive materials to form a plurality of nanoscale conductors within the insulating layer, the nanoscale conductors extending from a first surface of the insulating layer to a second surface of the insulating layer opposite the first surface;
joining the array of nanoscale conductors within the insulating layer to a plurality of first element contacts at a first face of a first microelectronic element, the plurality of first element contacts facing the first surface of the insulating layer;
removing the substrate from the second surface of the insulating layer;
joining the array of nanoscale conductors within the insulating layer to a plurality of second element contacts at a second face of a second microelectronic element, the plurality of second element contacts facing the second surface of the insulating layer; and
forming electrical interconnections between the first element contacts of the first microelectronic element and the second element contacts of the second microelectronic element with the plurality of nanoscale conductors, wherein the plurality of nanoscale conductors are arranged without regard to a specific alignment of the plurality of nanoscale conductors to either the plurality of first element contacts or the plurality of second element contacts.

US Pat. No. 10,600,758

SEMICONDUCTOR SENSOR PACKAGE

STMICROELECTRONICS PTE LT...

1. A method, comprising: forming a plurality of through holes in a substrate, the substrate including a first surface and a second surface;forming a plurality of first trenches in the first surface of the substrate, each first trench of the plurality of first trenches being substantially parallel to each other, each first trench of the plurality of first trenches is overlapping and aligned with a number of through holes of the plurality of through holes;
forming a plurality of second trenches in the first surface of the substrate, each second trench of the plurality of second trenches being transverse to the plurality of first trenches and overlapping at least one of the through holes of the plurality of through holes; and
forming a non-conductive material in the plurality of through holes, the plurality of first trenches, and the plurality of second trenches.

US Pat. No. 10,600,757

SEMICONDUCTOR PACKAGE

Chengwei Wu, New Taipei ...

1. A semiconductor package, comprising:a first die, the first die having an active surface and a back surface, the first die comprising a first connection end and a second connection end on the active surface, the first connection end being closer to a side edge of the first die than the second connection end;
a second die, the second die having an active side and a back side, the second die comprising a third connection end and a fourth connection end on the active surface, the fourth connection end being closer to a side edge of the second die than the third connection end;
a first set of metal pillars;
a second set of metal pillars;
a first redistribution structure, the first redistribution structure comprising at least two insulating layers, a first trace, and a second trace, the first die being connected to the first redistribution structure through the first set of metal pillars, the second die being connected to the first redistribution structure through the second set of metal pillars, the first trace being connected between the first connection end and the third connection end, the second trace being connected between the second connection end and the fourth connection end; and
a first molding material, wherein the first molding material is beside the first die and the second die.

US Pat. No. 10,600,755

METHOD OF MANUFACTURING AN ELECTRONIC DEVICE AND ELECTRONIC DEVICE MANUFACTURED THEREBY

Amkor Technology, Inc., ...

11. A method of manufacturing an electronic device, the method comprising:providing a substrate comprising a substrate conductive interconnection structure;
providing a semiconductor die comprising a die conductive interconnection structure protruding from a first side of the die; and
pressing a first surface of the die conductive interconnection structure and a first surface of the substrate conductive interconnection structure together with an interface layer comprising at least one layer of ink at an interface between the first surface of the die conductive interconnection structure and the first surface of the substrate conductive interconnection structure,
wherein after said pressing, the interface layer has a substantially consistent thickness,
wherein said pressing comprises performing said pressing utilizing a thermocompression bonding process.

US Pat. No. 10,600,753

FLIP CHIP BACKSIDE MECHANICAL DIE GROUNDING TECHNIQUES

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit (IC) package comprising:a semiconductor die including a first side and a second side opposite the first side, the first side including active circuitry;
a sheet attached to the second side, the sheet including a tip that electrically connects with the second side; and
a lid attached to a substrate, and contacting the sheet;
wherein the tip includes two parallel surfaces, and wherein each of the two parallel surfaces forms an acute angle with respect to a plane along a surface of the sheet, and wherein the tip extends from an edge of a hole in the sheet.

US Pat. No. 10,600,751

CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT

International Business Ma...

1. A pillar-type connection comprising:a first conductive layer that includes a hollow core;
a second conductive layer coupled to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core; and
a conductive via that terminates at a top surface of the first conductive layer.

US Pat. No. 10,600,748

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A fan-out semiconductor package comprising:a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip;
a second interconnection member disposed on a portion of the encapsulant and on the active surface of the semiconductor chip;
a first passivation layer disposed on the second interconnection member,
wherein the second interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip,
the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and
the first passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member,
wherein the first passivation layer is an outermost insulating layer of the fan-out semiconductor package.

US Pat. No. 10,600,746

RADIO FREQUENCY TRANSISTOR AMPLIFIERS AND OTHER MULTI-CELL TRANSISTORS HAVING GAPS AND/OR ISOLATION STRUCTURES BETWEEN GROUPS OF UNIT CELL TRANSISTORS

Cree, Inc., Durham, NC (...

1. A multi-cell transistor, comprising:a semiconductor structure; and
a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure,
wherein the unit cell transistors are spaced apart from each other along a second direction and arranged in a plurality of groups, wherein a first distance in the second direction between two adjacent unit cell transistors in a first of the groups is less than a second distance in the second direction between a first unit cell transistor that is at one end of the first of the groups and a second unit cell transistor that is in a second of the groups, where the second unit cell transistor is adjacent the first unit cell transistor,
wherein the multi-cell transistor further comprises a metal isolation structure that extends above the semiconductor structure in the first direction between the first of the groups and the second of the groups, and
wherein the metal isolation structure is electrically connected to source regions of the unit cell transistors.

US Pat. No. 10,600,745

COMPENSATING FOR MEMORY INPUT CAPACITANCE

Micron Technology, Inc., ...

1. An apparatus, comprising:a substrate;
an access line comprising a first portion in contact with the substrate and a second portion;
a memory die coupled with the substrate via the second portion of the access line;
a memory controller coupled with the access line and configured to transmit, through the access line to the memory die, a signal having an amplitude level and modulated with a modulation scheme having at least two levels; and
an inductive region coupled with the access line and configured to change a first noise level associated with the amplitude level of the signal to a second noise level based at least in part on altering a capacitance of the access line.

US Pat. No. 10,600,740

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH EPITAXIAL LAYERS AND AN ALIGNMENT MARK

Infineon Technologies Aus...

1. A semiconductor substrate, comprising:an alignment mark contained within in a kerf region of a semiconductor wafer or in an inactive region of a semiconductor die, the alignment mark comprising a groove with a minimum width of at least 100 ?m and a vertical extension in a range 100 nm to 1 ?m in a process surface of a semiconductor layer, and at least one fin within the groove at a distance of at least 60 ?m to a closest inner corner of the groove.

US Pat. No. 10,600,739

INTERPOSER WITH INTERCONNECTS AND METHODS OF MANUFACTURING THE SAME

HRL Laboratories, LLC, M...

1. An interposer, comprising:an interposer substrate comprising a plurality of vias, the interposer substrate having a first surface and a second surface opposite the first surface; and
a plurality of metallic interconnects in the plurality of vias,
wherein the interposer substrate comprises a dielectric material,
wherein a first pitch of the plurality of vias at a first end of the plurality of vias is different than a second pitch of the plurality of vias at a second end of the plurality of vias,
wherein the plurality of metallic interconnects are slanted at angles relative to the first surface of the interposer substrate,
wherein the angles at which the plurality of metallic interconnects are slanted relative to the first surface of the interposer substrate varies between the plurality of metallic interconnects, and
wherein the angle of at least one metallic interconnect of the plurality of metallic interconnects varies non-uniformly.

US Pat. No. 10,600,737

PREVENTION OF PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS IN AN INTEGRATED CIRCUIT

STMicroelectronics (Rouss...

1. A process, comprising:forming an opening in a porous material dielectric region, said opening having a side wall and a bottom wall;
depositing a non-porous dielectric barrier on said side wall and said bottom wall;
performing an anisotropic etch to completely remove a portion of the non-porous dielectric barrier along the bottom wall, wherein performing the anisotropic etch comprises performing a plasma etch; and
filling the opening with metal material to form an electrically conductive element that is laterally separated from an upper portion of the porous material dielectric region by the non-porous dielectric barrier along the side wall but is in contact with a lower portion of the porous material dielectric region along the bottom wall.

US Pat. No. 10,600,733

FABRICATING UNIQUE CHIPS USING A CHARGED PARTICLE MULTI-BEAMLET LITHOGRAPHY SYSTEM

ASMl Netherlands B.V., V...

1. A method of manufacturing electronic devices using a maskless lithographic exposure system using a maskless pattern writer that is arranged to write patterns onto a wafer directly using a charged particle beam, the method comprising:generating control data for controlling the maskless pattern writer to expose the wafer for creation of the electronic devices, wherein the control data is generated based on a feature data set defining features selectable for individualizing the electronic devices; and
exposing by the maskless pattern writer of the wafer according to the control data resulting in writing patterns corresponding to features selected from the feature data set.

US Pat. No. 10,600,732

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

United Microelectronics C...

1. A structure of semiconductor device, comprising:a substrate, wherein an interconnection layer is formed on the substrate, the interconnection layer comprises:
a first inter-layer dielectric layer, disposed over the substrate;
a lower wiring structure, formed in the first inter-layer dielectric layer;
a hard mask layer, disposed on the first inter-layer dielectric layer, wherein the hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure;
a second inter-layer dielectric layer disposed on the hard mask layer, wherein the second inter-layer dielectric layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening, wherein the second inter-layer dielectric layer has a protruding portion to fill the second opening of the mask layer; and
a metal line layer, filling the via opening and the trench pattern in the second inter-layer dielectric layer and the first opening of the hard mask layer.

US Pat. No. 10,600,728

THROUGH-HOLE ELECTRODE SUBSTRATE

Dai Nippon Printing Co., ...

1. A through-hole electrode substrate comprising:a substrate including a first through-hole and a second through-hole, the first through-hole and the second through-hole being adjacent to each other;
a first through-hole electrode arranged within the first through-hole;
a second through-hole electrode arranged within the second through-hole;
a first insulation layer arranged on the surface of the substrate, the first insulation layer having a first opening on the first through-hole electrode and a second opening on the second through-hole electrode, and the first insulation layer covering at least one part of a first boundary section between the first through-hole and the first through-hole electrode and at least one part of a second boundary section between the second through-hole and the second through-hole electrode;
a first conductive layer arranged above each of the first through-hole electrode and the second through-hole; and
a second insulation layer arranged on another surface of the substrate, the second insulation layer having a third opening on the first through-hole electrode and a fourth opening on the second through-hole electrode, and the second insulation layer covering at least one part of the first boundary section and at least one part of the second boundary section,
wherein the first insulation layer is arranged between the first conductive layer and the first through-hole electrode at the first boundary section and between the first conductive layer and the second through-hole electrode at the second boundary section;
the second insulation layer is arranged between the first conductive layer and the first through-hole electrode at the first boundary section and between the first conductive layer and the second through-hole electrode at the second boundary section;
a distance between the first opening and the second opening differs from a distance between the third opening and the fourth opening;
the first insulation layer is a resin layer; and
a thickness of the resin layer is 1 ?m to 20 ?m.

US Pat. No. 10,600,724

LEADFRAME WITH VERTICALLY SPACED DIE ATTACH PADS

TEXAS INSTRUMENTS INCORPO...

1. A method of making a packaged integrated circuit device, comprising:providing a lead frame with a first die attach pad and a second die attach pad, each die attach pad having a top surface, a bottom surface and an edge surface extending between the top surface and the bottom surface, the top surfaces of the first die attach pad and the second die attach pad being positioned at the same elevation, the edge surfaces of the first die attach pad and the second die attach pad being parallel and separated by a gap having a gap distance, at least one of the parallel edge surfaces being nonplanar between the top and bottom surfaces;
attaching a first component to the first die attach pad;
attaching a second component to the second die attach pad; and
encapsulating the lead frame, first component and second component with a layer of mold compound.

US Pat. No. 10,600,723

THERMALLY ENHANCED SEMICONDUCTOR PACKAGE AND PROCESS FOR MAKING THE SAME

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a precursor package including a module substrate, a thinned flip chip die, and a mold compound component, wherein:
the thinned flip chip die comprises a device layer with electronic components, a dielectric layer over an upper surface of the device layer, and a plurality of interconnects extending from a lower surface of the device layer and coupled to an upper surface of the module substrate;
the mold compound component resides over the upper surface of the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity above the upper surface of the thinned flip chip die; and
the mold compound component is not over the thinned flip chip die;
depositing a thermally conductive film over at least the upper surface of the thinned flip chip die at a bottom of the cavity; and
applying a thermally enhanced mold compound component over at least a portion of the thermally conductive film to fill the cavity.

US Pat. No. 10,600,722

HEAT SINK FOR ALTERNATOR

DENSO International Ameri...

1. A heat sink assembly for an alternator comprising:a clip for clipping the heat sink assembly onto a diode rectifier heat sink of the alternator;
thermally and electrically conductive material on an inner surface of the clip; and
a heat sink on an outer surface of the clip opposite to the thermally conductive material, the heat sink including fins, thermal energy from a hot spot of the alternator to which the heat sink assembly is clipped is conducted to the heat sink by way of the thermally conductive material and the clip and is radiated from the fins to cool the hot spot.

US Pat. No. 10,600,721

HEAT EXCHANGER FOR DUAL-SIDED COOLING OF ELECTRONIC MODULES

Dana Canada Corporation, ...

1. A heat exchanger assembly comprising:a first heat sink element and a second heat sink element separated by a space, wherein the first heat sink element defines a first fluid flow passage and the second heat sink element defines a second fluid flow passage, and wherein the first and second heat sink elements are parallel to one another;
at least one heat-generating electronic component located in said space and sandwiched between the first and second heat sink elements, wherein each said heat-generating electronic component has a first side surface in thermal contact with an inner surface of the first heat sink element and an opposite side surface in thermal contact with the inner surface of the second heat sink element; and
a clamping assembly, comprising:
(a) a first spring element arranged in contact with an outer surface of the first heat sink element; and
(b) a second spring element arranged in contact with an outer surface of the second heat sink element;
wherein the first and second heat sink elements are sandwiched between the first and second spring elements, and wherein the first and second spring elements are joined together so as to apply compressive forces to the first and second heat sink elements and thereby cause the at least one heat-generating electronic component to be clamped between the first and second heat sink elements;
wherein each said spring element comprises one or more discrete force application regions for applying force to one of the heat sink elements, and a plurality of fastening regions for maintaining the position of the spring element relative to the outer surface of the heat sink element with which it is in contact;
wherein the force application regions are located such that at least some of the force application regions are positioned approximately centrally above or below a side surface of one of the heat-generating electronic components; and
wherein the force application regions are spaced apart along the longitudinal axis by a center-to-center distance between adjacent heat-generating electronic components.

US Pat. No. 10,600,720

SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor module comprising a semiconductor element, a resin package sealing the semiconductor element, and a heat sink located at a main surface of the resin package, the resin package comprising a pair of side surfaces each adjacent to the main surface and opposite to each other;
an insulating sheet covering the heat sink;
a cooling plate which is constituted of resin containing heat transfer fillers, the cooling plate having a first surface and a second surface opposite from the first surface, wherein the first surface covers the insulating sheet and is in direct contact with the main surface of the resin package around the insulating sheet, and the second surface is provided with fins; and
a cooler constituted of resin and at least partly defining a coolant passage configured to flow coolant along the fins, wherein the cooler surrounds the cooling plate in a view along a normal direction of the cooling plate, and is in direct contact with each of the pair of side surfaces of the resin package,
wherein
a peripheral edge of the cooling plate is separated from the cooler by a gap;
the gap extends from the coolant passage to the main surface of the resin package such that the coolant passage is partly defined by the main surface of the resin package;
the cooler directly contacts the main surface of the resin package around the peripheral edge of the cooling plate; and
the cooler comprises an outer cylinder at least partly defining the coolant passage and at least two beams provided in the outer cylinder and being in direct contact with the pair of side surfaces and the main surface of the resin package.

US Pat. No. 10,600,719

BONDED BODY, POWER MODULE SUBSTRATE WITH HEAT SINK, HEAT SINK, METHOD OF MANUFACTURING BONDED BODY, METHOD OF MANUFACTURING POWER MODULE SUBSTRATE WITH HEAT SINK, AND METHOD OF MANUFACTURING HEAT SINK

MITSUBISHI MATERIALS CORP...

1. A bonded body, comprising:an aluminum member which is constituted by an aluminum alloy; and
a metal member which is constituted by copper,
wherein the aluminum member and the metal member are bonded to each other,
wherein the aluminum member is constituted by the aluminum alloy in which a solidus temperature is set to be less than a eutectic temperature of a metal element that constitutes the metal member and aluminum,
a Ti layer is formed at a bonding portion between the aluminum member and the metal member, and the aluminum member and the Ti layer, and the Ti layer and the metal member are respectively subjected to solid-phase diffusion bonding,
a Cu—Ti layer is formed at a bonding interface between the metal member and the Ti layer, and a thickness of the Cu—Ti layer is 1 ?m to 8 ?m,
the aluminum member includes 9.6 mass % to 12.0 mass % of Si, and an Al—Ti—Si layer in which Si is solid-soluted in Al3Ti is formed at a bonding interface between the aluminum member and the Ti layer,
the Al—Ti—Si sub-layer includes a second Al—Ti—Si sub-layer that is in direct contact with the aluminum member, and a first Al—Ti—Si sub-layer that is in between the second Al—Ti—Si sub-layer and the Ti layer, and
a Si concentration of the second Al—Ti—Si sub-layer is lower than a Si concentration of the first Al—Ti—Si sub-layer.

US Pat. No. 10,600,718

HEAT SINK PACKAGE

II-VI Delaware, Inc., Wi...

1. A semiconductor device package comprising:a silicon substrate for supporting an integrated circuit mounted in a flip-chip fashion;
a high electron mobility transistor (HEMT) formed in a layer of Gallium Nitride (GaN) having a first major active device surface mounted in the flip-chip fashion on the silicon substrate;
an interconnect making thermal contact with the layer of GaN on its first major active device surface, said interconnect comprising a high areal density ohmic contact layer covering a high percentage of the first major active device surface;
a first high areal density heat sink/heat spreader disposed across a majority of the interconnect, and in electrical and thermal contact with said interconnect; and
a second high areal density heat sink/heat spreader embedded within the silicon substrate and in electrical and thermal contact with the first heat sink/heat spreader.

US Pat. No. 10,600,717

SEMICONDUCTOR DEVICE

Toyota Jidosha Kabushiki ...

1. A semiconductor device comprising:a first semiconductor element;
a first heat dissipation plate connected to the first semiconductor element;
a sealing body that integrally holds the first semiconductor element and the first heat dissipation plate; and
a first terminal that is electrically connected to the first semiconductor element and protrudes from the sealing body, wherein:
the first heat dissipation plate has
a first insulating substrate,
a first inner conductor layer that is located on a first side of the first insulating substrate and is electrically connected to the first semiconductor element, and
a first outer conductor layer that is located on a second side of the first insulating substrate;
the first outer conductor layer is exposed on a first main surface of the sealing body;
the first terminal protrudes from a first side surface adjacent to the first main surface of the sealing body;
on the first main surface of the sealing body, at least one first groove extending in a direction along the first side surface is provided in a range located between the first outer conductor layer and the first side surface;
wherein the at least one first groove includes a plurality of first grooves; and
a groove located closer to the first side surface among the first grooves has a larger depth.

US Pat. No. 10,600,716

POWER CONVERTER

TOYOTA JIDOSHA KABUSHIKI ...

1. A power converter comprising:two switching elements connected in series;
a positive electrode conductive plate connected to a high-potential terminal of a series connection of the two switching elements;
a negative electrode conductive plate connected to a low-potential terminal of the series connection of the two switching elements;
a mid-point conductive plate connected to a middle point of the series connection of the two switching elements;
a first heat sink having electric conductivity, the first heat sink facing the positive electrode conductive plate with a first isolating layer interposed between the first heat sink and the positive electrode conductive plate, the first heat sink facing the negative electrode conductive plate with the first isolating layer interposed between the first heat sink and the negative electrode conductive plate, and the first heat sink being connected to a ground terminal maintained at a ground potential; and
a second heat sink having electric conductivity, the second heat sink facing the mid-point conductive plate with a second isolating layer interposed between the second heat sink and the mid-point conductive plate, the second heat sink being isolated from the ground terminal.

US Pat. No. 10,600,715

INTEGRATED CIRCUIT CHIP PACKAGING

INTERNATIONAL BUSINESS MA...

1. A method of mounting an integrated circuit chip to a circuit board, the method comprising:placing said integrated circuit chip into a cavity extending from a surface of said circuit board to an embedded conductor;
electrically connecting said integrated circuit chip to said embedded conductor;
disposing a thermal slug on a top surface of said integrated circuit chip; and
disposing an underfill material from a top surface of said circuit board to a side surface of the thermal slug, such that the top surface of said circuit board and a portion of the side surface of the thermal slug are exposed from the underfill material.

US Pat. No. 10,600,713

SEMICONDUCTOR PACKAGES INCLUDING A HEAT INSULATION WALL

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a first package substrate;
a built-in package disposed on the first package substrate and configured to include a first semiconductor chip and a heat insulation wall for thermally isolating the first semiconductor chip; and
a second semiconductor chip disposed on the first package substrate to be spaced apart from the built-in package,
wherein the built-in package further includes a first molding layer filling a gap between the first semiconductor chip and the heat insulation wall,
wherein the built-in package further includes a heat conductor that penetrates the first molding layer to be in contact with the first semiconductor chip,
wherein the heat conductor includes a material having a thermal conductivity which is higher than a thermal conductivity of the first molding layer, and
wherein the heat conductor includes a silicon dummy chip.

US Pat. No. 10,600,712

ELECTRONIC DEVICE

SHINDENGEN ELECTRIC MANUF...

1. An electronic device comprising:a substrate;
a conductor layer having a first conductor layer and a second conductor layer provided on the substrate;
a first electric element provided on the first conductor layer;
a second electric element provided on the first electric element; and
a connector consisting of a base end part having a supporting surface, which is provided on the second conductor layer, and a head part integrally formed with the base end part, connected to a front surface electrode of the second electric element via a conductive adhesive, and extending parallel to the supporting surface,
wherein an area of the base end part placed on the second conductor layer is larger than an area of the head part placed on the second electric element,
wherein the base end part has a bent part being bent and extending toward an upper side,
wherein the base end part is located at a side of the substrate compared with the head part, and a gravity center position of the connector is at a side of the base end part of the connector and is located lower than the head part,
wherein the head part has a second projection protruding toward a side of the second electric element and a first projection protruding toward the side of the second electric element from the second projection,
wherein a planar shape of the second projection is an oval shape, and
wherein a major axis of the oval shape is provided along a width direction of the head part.

US Pat. No. 10,600,711

WAFER-LEVEL PACKAGE WITH ENHANCED PERFORMANCE

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a first thinned die comprising a first device layer and a first dielectric layer over the first device layer, wherein the first device layer comprises a plurality of first die contacts at a bottom surface of the first device layer;
a multilayer redistribution structure comprising a first dielectric pattern, redistribution interconnects, a second dielectric pattern, and a plurality of package contacts, wherein:
the first dielectric pattern is formed underneath the first thinned die and the plurality of first die contacts is exposed through the first dielectric pattern;
the redistribution interconnects are electrically connected to the plurality of first die contacts through the first dielectric pattern and extend underneath the first dielectric pattern, wherein connections between the redistribution interconnects and the plurality of first die contacts are solder-free;
the second dielectric pattern is formed underneath the first dielectric pattern to partially encapsulate each redistribution interconnect; and
each of the plurality of package contacts is separate and on a bottom surface of the multilayer redistribution structure, wherein the redistribution interconnects connect the plurality of first die contacts to certain ones of the plurality of package contacts;
a support dielectric layer, which extends over a continuous air gap surrounding each of the plurality of package contacts, wherein at least a portion of each side of each of the plurality of package contacts is covered by the support dielectric layer, and a bottom surface of each of the plurality of package contacts is not covered by the support dielectric layer;
a first mold compound residing over the multilayer redistribution structure and around the first thinned die, and extending beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die, wherein the top surface of the first thinned die is exposed at a bottom of the opening; and
a second mold compound filling the opening and in contact with the top surface of the first thinned die.

US Pat. No. 10,600,707

FIBER-CONTAINING RESIN SUBSTRATE, ENCAPSULATED SEMICONDUCTOR DEVICES MOUNTING SUBSTRATE, ENCAPSULATED SEMICONDUCTOR DEVICES FORMING WAFER, ENCAPSULATED SEMICONDUCTOR DEVICES MOUNTING SHEET, SEMICONDUCTOR EQUIPMENT, AND METHOD FOR MANUFACTURING SEMICONDUCT

SHIN-ETSU CHEMICAL CO., L...

1. A fiber-containing resin substrate for collectively encapsulating a semiconductor devices mounting surface of a substrate or a sheet on which two or more semiconductor devices are mounted or a semiconductor devices forming surface of a wafer on which semiconductor devices are formed, comprising:a thermosetting epoxy resin-impregnated fiber base material composed of a fiber base material impregnated with a thermosetting epoxy resin that is semi-cured or cured, and
an uncured resin layer formed on one side of the thermosetting epoxy resin-impregnated fiber base material for coating the semiconductor devices mounting surface or the semiconductor devices forming surface,
wherein the uncured resin layer is a layer formed from a composition containing:
(A) a crystalline bisphenol A type epoxy resin and/or a crystalline bisphenol F type epoxy resin,
(B) an epoxy resin that is non-fluid at 25° C. other than the component (A),
(C) a phenol compound having two or more phenolic hydroxy groups in a molecule thereof,
(D) an inorganic filler, and
(E) an urea-based curing accelerator.

US Pat. No. 10,600,703

PROCESS FOR PACKAGING CIRCUIT COMPONENT HAVING COPPER CIRCUITS WITH SOLID ELECTRICAL AND THERMAL CONDUCTIVITIES AND CIRCUIT COMPONENT THEREOF

1. A method for packaging a circuit component, comprising:forming a first protruding pad on a first copper substrate;
forming a second protruding pad on a second copper substrate and placing a circuit dice of the circuit component on the second protruding pad having a conductive paste coated thereon wherein a first electrode of the dice facing the second protruding pad;
placing a copper block on the second copper substrate at a position beside where the dice is placed and having a conductive paste coated thereon;
stacking the first copper substrate onto the second copper substrate with the first protruding pad having a conductive paste coated thereon aligned and pressing onto the circuit dice and the copper block wherein a second electrode of the dice facing the first protruding pad;
heat-treating the stacked structure for the circuit dice and the copper block to form secured electrical connection with the first and second copper substrates respectively and further forming a hermetic seal in the space between the first and second copper substrates; and
using the hermetic seal as a rigid processing structure, etching the exposed surface of the first and second copper substrates to remove the entire thickness of copper other than in the area of the first and second protruding pads and in the area other than where the copper block connects to the second copper substrate, thereby forming the device terminals of the circuit component package.

US Pat. No. 10,600,701

WAFER AND METHOD FOR PROCESSING A WAFER

INFINEON TECHNOLOGIES AG,...

1. A method for processing a wafer, comprising:providing a wafer, the wafer comprising at least one metallization structure, a first separation line region, a second separation line region and third a third separation line region, wherein the wafer is configured to be diced along the first, second, and third separation line regions;
forming at least one opening in the at least one metallization structure, wherein the at least one metallization structure is located within the first separation line region so that first separation line region intersects the at least one opening,
wherein the second and third separation line regions are neighboring parallel separation line regions that are substantially perpendicular to the first separation line region, and wherein the at least one metallization structure is located exclusively between the second and third separation line regions.

US Pat. No. 10,600,700

TEST STRUCTURE AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A test structure manufacturing method, comprising:providing a top wafer structure, wherein the top wafer structure comprises a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer;
providing a bottom wafer;
forming a pad material layer on the bottom wafer;
patterning the pad material layer, to form multiple initial second pads in a pad region;
forming an insulation layer on a side surface of each initial second pad;
etching the multiple initial second pads to form trenches, to form multiple second pads that are spaced from each other at a top of the bottom wafer; and
bonding, in an eutectic manner, the multiple first pads with the multiple second pads, wherein each first pad is bonded with a second pad, to form multiple pads.

US Pat. No. 10,600,688

METHODS OF PRODUCING SELF-ALIGNED VIAS

Micromaterials LLC, Wilm...

1. A method to provide a self-aligned via, the method comprising:forming a seed gapfill layer on recessed first insulating layers positioned between first conductive lines, the first conductive lines extending along a first direction;
forming pillars from the seed gapfill layer, the pillars extending above the first conductive lines;
depositing a second insulating layer in gaps between the pillars on the first conductive lines;
removing the pillars to form gaps in the second insulating layer;
depositing a third insulating layer in the gaps in the second insulating layer, onto the recessed first insulating layers and on the second insulating layer to form an overburden of third insulating layer on the second insulating layer; and
selectively etching a portion of the overburden of the third insulating layer and some of the second insulating layer to expose the first conductive lines and form vias and a trench extending in a second direction different from the first direction.

US Pat. No. 10,600,661

RAPID HEAT TREATMENT APPARATUS

ULTECH CO., LTD., Daegu ...

1. A rapid heat treatment apparatus, comprising:a chamber for rapid heat treatment;
a support stage which is disposed on an lower inner side of the chamber and supports and rotates a substrate for rapid heat treatment;
a heat source device which is disposed on an upper inner side of the chamber and radiates light to rapidly heat the substrate for rapid heat treatment;
a substrate for temperature measurement which is placed apart at a distance above a part of the substrate for rapid heat treatment, and is made of a same material as the substrate for rapid heat treatment;
a thermocouple for temperature measurement which is installed at the substrate for temperature measurement to measure a temperature of the substrate for temperature measurement;
a support part of a light transmitting material which supports the substrate for temperature measurement; and
a light transmitting plate which is disposed between the support part and the heat source device to isolate the two internal space parts of the chamber,
wherein the temperature of the substrate for temperature measurement measured by the thermocouple is regarded as temperature of the substrate for rapid heat treatment.

US Pat. No. 10,600,586

INTERLOCKING DEVICE FOR CIRCUIT BREAKER

ZHEJIANG CHINT ELECTRICS ...

1. An interlocking device for a circuit breaker, comprising a control assembly and an interlocking assembly which are connected with each other in a driving manner; the control assembly can be connected with a connecting rod assembly and a cam assembly of an energy storage operation mechanism of the circuit breaker in a latching manner, thereby controlling the energy storage operation mechanism to finish a switching-on/switching-off operation; the control assembly comprises a switching-off half-shaft, a switching-off latch, a switching-on half-shaft and a switching-on latch; the interlocking assembly comprises a switching-on guide rod, a switching-off guide rod and a driving guide rod;the control assembly further comprises a switching-on button; the switching-on latch can be connected with the cam assembly in a latching manner, the driving guide rod is connected with the switching-on button in a driving manner; in the switching-on operation, one end part of the switching-on guide rod can be arranged between the driving guide rod and the switching-on half-shaft, and after the switching-on button is pushed, the switching-on guide rod drives the switching-on latch to be tripped from the cam assembly;
the control assembly further comprises a switching-off button; one end of the switching-off latch is connected with the switching-off half-shaft in a latching manner, and the other end of the switching-off latch is connected with the connecting rod assembly in a latching and limiting manner; in the switching-off operation, after the switching-off button is pushed, the switching-off guide rod drives the switching-off half-shaft to rotate and to trip the switching-off half-shaft from the switching-off latch, and to trip the switching-off latch from the connecting rod assembly;
one end of the switching-on half-shaft is connected with the switching-on latch in a driving manner, and the other end of the switching-on half-shaft and the driving guide rod face each other;
the interlocking assembly further comprises an interlocking guide rod and an energy storage indicator; the energy storage operation mechanism of the circuit breaker comprises a rotating shaft assembly for driving the switching-on/switching-off operation; a middle part of the interlocking guide rod is rotatably mounted on the energy storage operation mechanism; one end of the interlocking guide rod is a limiting portion which corresponds to the rotating shaft assembly and the energy storage indicator, and another end of the interlocking guide rod is a driving portion which is in contact and connection with the switching-on guide rod; the rotating shaft assembly and the energy storage indicator can be in contact and matched with the limiting portion of the interlocking guide rod, such that the interlocking guide rod acts on the switching-on guide rod; when the energy storage operation mechanism is in a switching-off energy storage state, the driving portion of the interlocking guide rod does not limit a switching-on interlocking portion of the switching-on guide rod the energy storage operation mechanism further comprises a driving shaft for mounting the connecting rod assembly and the cam assembly, wherein the rotating shaft assembly and the interlocking assembly are mounted at two sides of the driving shaft respectively.

US Pat. No. 10,600,584

TRIGGER ACTIVATED TOOLS HAVING ACTIVATION LOCKOUTS

Hubbel Incorporated, She...

1. A trigger activated tool, comprising:an activatable device;
an activation trigger depending from a handle portion for movement about a first axis between a first position and a second position, the activation trigger being configured to activate the activateable device in the second position;
a lockout depending from the activation trigger for movement about a second axis between a locked state and an unlocked state, the locked state preventing activation of the activatable device by the activation trigger; and
a drain trigger depending from the handle portion for movement about the first axis, the drain trigger being configured to relieve potential energy within the activatable device when the lockout is in both the locked and unlocked states, the drain trigger being configured to relieve potential energy within the activatable device when the activation trigger is in the first position, but not the second position, wherein the first and second axes are offset from one another.

US Pat. No. 10,600,579

ELECTROLYTIC CAPACITOR INCLUDING HYDROXY COMPOUND AND MANUFACTURING METHOD THEREFOR

Panasonic Intellectual Pr...

1. An electrolytic capacitor comprising:an anode body including a dielectric layer; and
a solid electrolyte layer covering at least a part of the dielectric layer, wherein:
the solid electrolyte layer includes:
a first conductive polymer layer covering at least a part of the dielectric layer and including a first conductive polymer; and
a second conductive polymer layer covering at least a part of the first conductive polymer layer and including a second conductive polymer,
the second conductive polymer layer is a layer in which the second conductive polymer, a polymer dopant, and a hydroxy compound are mixed,
the hydroxy compound has two or more alcoholic hydroxy groups or two or more phenolic hydroxy groups, the hydroxy compound having a melting point ranging from 40° C. to 150° C., inclusive,
the first conductive polymer layer further includes the hydroxy compound, and
a concentration of the hydroxy compound included in the second conductive polymer layer is higher than a concentration of the hydroxy compound included in the first conductive polymer layer.

US Pat. No. 10,600,578

ELECTRIC VEHICLE INVERTER MODULE CAPACITORS

SF MOTORS, INC., Santa C...

1. A capacitor module of an inverter module to provide electrical power to an electric vehicle, comprising:a capacitor housing;
a plurality of positive terminals coupled with a first surface of the capacitor housing and extending from the first surface at a first angle;
a plurality of negative terminals coupled with the first surface of the capacitor housing;
a divider coupled with the first surface of the capacitor housing, the divider disposed between the plurality of positive terminals and the plurality of negative terminals, and the divider electrically isolates the plurality of positive terminals from the plurality of negative terminals;
a plurality of mounting holes formed on an outer surface of the capacitor housing;
a first plurality of separating elements formed on a first side surface of the divider, each separating element of the first plurality of separating elements disposed between a pair of positive terminals of the plurality of positive terminals; and
a second plurality of separating elements formed on a second side surface of the divider, each separating element of the second plurality of separating elements disposed between a pair of negative terminals of the plurality of negative terminals.

US Pat. No. 10,600,577

ELECTRIC VEHICLE INVERTER MODULE CAPACITORS

SF MOTORS, INC., Santa C...

1. A capacitor module of an inverter module to provide electrical power to an electric vehicle, comprising:a capacitor housing;
a plurality of positive terminals coupled with a first surface of the capacitor housing and extending from the first surface at a first angle;
a plurality of negative terminals coupled with the first surface of the capacitor housing; a divider coupled with the first surface of the capacitor housing, the divider disposed between the plurality of positive terminals and the plurality of negative terminals, and the divider electrically isolates the plurality of positive terminals from the plurality of negative terminals;
a plurality of mounting holes formed on an outer surface of the capacitor housing;
an extension portion of the divider, the extension portion disposed between the plurality of positive terminals and the plurality of negative terminals to electrically insulate the plurality of positive terminals from the plurality of negative terminals, and wherein the plurality of positive terminals are adjacent to a first side surface of the extension portion and the plurality of negative terminals are adjacent to a second side surface of the extension portion;
a first divider support member to hold the plurality of positive terminals and the plurality of negative terminals; and
a second divider support member to hold the plurality of positive terminals and the plurality of negative terminals.

US Pat. No. 10,600,576

VOLUMETRIC EFFICIENCY WET ELECTROLYTE CAPACITOR HAVING A FILL PORT AND TERMINATIONS FOR SURFACE MOUNTING

VISHAY SPRAGUE, INC., Be...

1. A wet electrolytic capacitor, comprising:a body defining an interior area and comprising a fill port formed through a wall of the body, the body having a first portion and a second portion;
a compressible fill port plug positioned adjacent the fill port;
a fill port cover welded to the body and covering the fill port plug and configured to compress the fill port plug against the fill port to seal the fill port.

US Pat. No. 10,600,573

CAPACITOR COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A capacitor component comprising:a body in which a dielectric layer and an internal electrode are alternately stacked; and
an external electrode disposed on the body and connected to the internal electrode,
wherein the dielectric layer includes a composite layer including a first dielectric material and a metallic particle and first and second protective layers spaced apart by the composite layer and including a second dielectric material; and
wherein a thickness of each of the first and second protective layers is equal to or greater than ? of a thickness of the dielectric layer.

US Pat. No. 10,600,571

MULTILAYER CERAMIC ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic electronic component comprising:a ceramic body including dielectric layers and first and second internal electrodes alternately laminated with the dielectric layers disposed therebetween in a stacking direction, the first and second internal electrodes being exposed to first and second external surfaces of the ceramic body, respectively, in a length direction; and
first and second external electrodes disposed on the first and second external surfaces of the ceramic body to be electrically connected to the first and second internal electrodes, respectively, the first and second external electrodes extending along a surface of the ceramic body in the length direction,
wherein Lb/La is greater than zero and less than or equal to 0.6, where a longest distance from the first external electrode to the second external electrode in the length direction is denoted by “La”, and a shortest distance from the first external electrode to the second external electrode in the length direction is denoted by “Lb”,
wherein BWd is greater than BWc, where an average length of an extending portion of each of the first and second external electrodes in the length direction, corresponding to an edge of the ceramic body, is denoted by “BWc”, and an average length of an extending portion of each of the first and second external electrodes in the length direction, corresponding to a center of the surface of the ceramic body is denoted by “BWd”,
wherein the ceramic body has a hexahedral shape having at least one rounded corner, and
wherein 0

US Pat. No. 10,600,570

ELECTRONIC COMPONENT

TDK CORPORATION, Tokyo (...

1. An electronic component, comprising:an element body of a rectangular parallelepiped shape including a first principal surface arranged to constitute a mounting surface, a second principal surface opposing the first principal surface in a first direction, a pair of side surfaces opposing each other in a second direction, and a pair of end surfaces opposing each other in a third direction; and
a plurality of external electrodes disposed at both end portions of the element body in the third direction, wherein
the plurality of external electrodes includes a plating layer including a first portion covering the first principal surface and a pair of second portions covering the pair of side surfaces, and
a thickness of the first portion is smaller than each thickness of the pair of second portions.

US Pat. No. 10,600,568

CAPACITOR AND METHOD OF FABRICATING THE SAME

United Microelectronics C...

1. A capacitor, comprising:a first electrode located on a top surface of a dielectric layer;
a dielectric covering a sidewall and a top surface of the first electrode; and
a second electrode covering the dielectric and the dielectric layer, wherein an orthographic projection area of the second electrode on the dielectric layer is greater than an orthographic projection area of the first electrode on the dielectric layer, and a bottommost surface of the second electrode is in direct physical contact with the dielectric layer, wherein the bottommost surface of the second electrode is coplanar with a bottommost surface of the first electrode and a bottommost surface of the dielectric.

US Pat. No. 10,600,566

METHOD FOR FORMING A PLANAR, CLOSED LOOP MAGNETIC STRUCTURE

INTERNATIONAL BUSINESS MA...

1. A method for forming a planar, closed loop magnetic structure, comprising:forming a first antiferromagnetic layer at a first blocking temperature for a closed magnetic loop to define a first pin direction for first magnetic moments;
forming a second antiferromagnetic layer at a second blocking temperature lower than the first blocking temperature for the closed magnetic loop to define a second pin direction different from the first pin direction for second magnetic moments; and
forming a coil around at least one core segment of the closed magnetic loop such that when the coil is energized the first and second magnetic moments rotate to follow a contour of the closed magnetic loop.

US Pat. No. 10,600,564

INDUCTIVE POWER TRANSFER SYSTEM PRIMARY TRACK TOPOLOGIES

AUCKLAND UNISERVICES LIMI...

1. A multiphase Inductive Power Transfer (IPT) primary track conductor arrangement comprising phase conductors including a first phase conductor and a second phase conductor, the phase conductors being arranged substantially in a plane and being operable to provide a magnetic field for inductive power transfer on one side of the plane, the phase conductors also being arranged to overlap each other such that there is minimal mutual coupling between the phase conductors, and the arrangement being associated with a magnetically permeable member, the magnetically permeable member being provided on an opposite side of the plane,wherein a forward current path of the first phase conductor and a return current path of the first phase conductor are arranged to produce a first series of alternating pole areas, and a forward current path of the second phase conductor and a return current path of the second phase conductor are arranged to produce a second series of alternating pole areas, and wherein the magnetically permeable member is configured to channel flux between adjacent pole areas.

US Pat. No. 10,600,560

ELECTRONIC COMPONENT INCLUDING OUTER ELECTRODES AND A SHIELD ELECTRODE

MURATA MANUFACTURING CO.,...

1. An electronic component comprising:a main body having a rectangular or substantially rectangular parallelepiped shape;
an inner conductor that is provided inside the main body;
one or more outer electrodes that are provided on a bottom surface of the main body and are not provided on four side surfaces of the main body; and
a shield electrode that covers the four side surfaces of the main body and has a rectangular or substantially rectangular cylindrical shape; wherein
the shield electrode is not physically connected to the one or more outer electrodes at a surface of the main body and is physically connected to the inner conductor at a surface of the main body; and
the main body includes a stack of a plurality of insulator layers on top of one another in a stacking direction that connects the top surface and the bottom surface of the main body;
the plurality of insulator layers include a first insulator layer; and
the electronic component further comprises;
one or more passive elements that are provided in the main body; and
a first ground conductor that is provided on the first insulator layer, which is positioned closer to the top surface of the main body than the one or more passive elements.

US Pat. No. 10,600,558

ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. An electronic component comprising:a body containing glass;
external conductors including a first external electrode and a second external electrode each disposed on an external surface of the body;
a spiral conductor disposed within the body; and
extended conductors including a first extended conductor and a second extended conductor each disposed within the body,
wherein one end portion of the spiral conductor is electrically connected to the first external electrode with the first extended conductor therebetween and another end portion of the spiral conductor is electrically connected to the second external electrode with the second extended conductor therebetween, and
wherein the spiral conductor contains Ag and at least one oxide selected from the group consisting of Al2O3, SiO2, ZnO, TiO2, and ZrO2, and the extended conductors contain Ag, but none of Al2O3, SiO2, ZnO, TiO2, and ZrO2.

US Pat. No. 10,600,557

REACTOR HAVING AIR DISCHARGE PATHS

AUTONETWORKS TECHNOLOGIES...

1. A reactor comprising:a coil having winding portions;
a magnetic core having inner core portions arranged inside the winding portions, and outer core portions arranged outside the winding portions;
inner resin portions filling gaps between inner peripheral faces of the winding portions and the inner core portions, and being continuous along an axial direction of the winding portions; and
inner interposed members that are interposed between the inner peripheral faces of the winding portions and the inner core portions, and forming resin flow paths configured to provide flow paths of resin for forming the inner resin portions, wherein:
the inner interposed members have spacers arranged between the winding portions and the inner core portions, and
at least one of the spacers include at least one air discharge path extending from a surface of one inner core portion to the at least one end face side of the winding portions, the at least one air discharge path being: (i) disposed between the surface of one inner core portion and the at least one end face side of the winding portion, and (ii) in communication with one of the resin flow paths.

US Pat. No. 10,600,556

INDUCTOR STRUCTURE

VANGUARD INTERNATIONAL SE...

1. An inductor structure formed on a substrate and disposed in a first region, a second region, a third region and a fourth region, wherein the first region comprises a first boundary, a second boundary, a third boundary and a fourth boundary, the second region comprises a fifth boundary, a sixth boundary, a seventh boundary and an eighth boundary, the third region comprises a ninth boundary, a tenth boundary, an eleventh boundary and a twelfth boundary, and the fourth region comprises a thirteenth boundary, a fourteenth boundary, a fifteenth boundary and a sixteenth boundary, comprising:a first conducting line;
a second conducting line; and
a third conducting line connected between the first conducting line and the second conducting line and comprising:
a first portion sequentially extended along the first, the third, the thirteenth, the sixteenth, the sixth, the eighth, the tenth and the eleventh boundaries; and
a second portion sequentially extended along the ninth, the twelfth, the fifth, the seventh, the fourteenth, the fifteenth, the second and the fourth boundaries,
wherein the first boundary is parallel to the second boundary, the third boundary is parallel to the fourth boundary, and the first and second boundaries are vertical to the third and the fourth boundaries,
wherein the fifth boundary is parallel to the sixth boundary, the seventh boundary is parallel to the eighth boundary, and the fifth and sixth boundaries are vertical to the seventh and the eighth boundaries,
wherein the ninth boundary is parallel to the tenth boundary, the eleventh boundary is parallel to the twelfth boundary, and the ninth and tenth boundaries are vertical to the eleventh and the twelfth boundaries, and
wherein the thirteenth boundary is parallel to the fourteenth boundary, the fifteenth boundary is parallel to the sixteenth boundary, and the thirteenth and fourteenth boundaries are vertical to the fifteenth and the sixteenth boundaries,
wherein the first portion of the third conducting line comprises a first segment directly connected to the first conducting line and extended along the first boundary, and the second portion of the third conducting line comprises a ninth segment directly connected to the first conducting line and extended along the ninth boundary.

US Pat. No. 10,600,555

COMMON MODE FILTER

TDK CORPORATION, Tokyo (...

1. A device, comprising:a core having a first end and a second end; and
first and second wires wound around the core, each of the first and second wires having 1st to Nth turns counting from the first end to the second end, the 1st to Nth turns including an i?1th turn, an ith turn, a jth turn, and a j+1th turn, where j is greater than i,
wherein the ith turn of the first wire is closer to the first end than the ith turn of the second wire, the i?1th turn of the second wire is closer to the first end than the ith turn of the first wire, and the i?1th turn of the first wire is closer to the first end than the i?1th turn of the second wire,
wherein the jth turn of the first wire is closer to the second end than the jth turn of the second wire, the j+1th turn of the second wire is closer to the second end than the jth turn of the first wire, and the j+1th turn of the first wire is closer to the second end than the j+1th turn of the second wire,
wherein the first and second wires form a first winding layer on the core and a second winding layer on the first layer,
wherein each of the i?1th turn, the ith turn, the jth turn, and the j+1th turn of the first wire is positioned at the first winding layer,
wherein each of the ith turn and the jth turn of the second wire is positioned at the first winding layer, and
wherein each of the i?1th turn and the j+1th turn of the second wire is positioned at the second winding layer.

US Pat. No. 10,600,554

COIL COMPONENT

Murata Manufacturing Co.,...

1. A coil component comprising:a drum-shaped core including a winding core portion and first and second flange portions disposed at respective opposing first and second end portions of the winding core portion; and
first and second wires that are wound around the winding core portion and are not electrically connected to each other, wherein
the first and second wires form a wire assembly by being wound around the winding core portion together,
the wire assembly includes a twisted wire portion at which the first and second wires are twisted together, an inner layer portion that is in contact with and wound around a circumferential surface of the winding core portion, an outer layer portion wound around an outer circumference of the inner layer portion, a plurality of outward transition portions each extending from the inner layer portion to the outer layer portion, and an inward transition portion extending from the outer layer portion to the inner layer portion,
the outer layer portion includes
a plurality of first outer layer portions that are each connected to a respective one of the outward transition portions extending from a position of the inner layer portion that is between end portions of the inner layer portion in a winding axial direction and connected to the inward transition portion, and
a second outer layer portion that is connected to an outward transition portion extending from an end position of the inner layer portion near the second end portion in the winding axial direction,
the inward transition portion extends to another position of the inner layer portion that is between the end portions of the inner layer portion in the winding axial direction, and
a number of windings included in the second outer layer portion is less than a number of windings in at least one of the first outer layer portions.

US Pat. No. 10,600,552

SURFACE-MOUNTED REACTOR AND MANUFACTURING METHOD THEREFOR

HITACHI METALS, LTD., To...

1. A surface mountable reactor, comprising:a coil;
a first magnetic core comprising an axial portion around which the coil is disposed and flange portions at both ends of the axial portion;
a second magnetic core that is disposed outside the coil to connect the flange portions of the first magnetic core; and
a resin mount disposed outside the coil, wherein the second magnetic core comprises a plurality of components separable toward outside the coil,
a circumference of the coil is surrounded by the second magnetic core and the resin mount,
the coil is housed in a space surrounded by (i) the flange portions of the first magnetic core, (ii) the second magnetic core, and (iii) the resin mount, and
the coil has end portions disposed outside the resin mount to form mount terminals.

US Pat. No. 10,600,548

LIQUID COOLED MAGNETIC ELEMENT

Prippell Technologies, LL...

1. A magnetic element, comprising:a first electrically conductive coil, having a first annular surface and a second annular surface;
a second electrically conductive coil, having a first annular surface and a second annular surface; and
a spacer between the first electrically conductive coil and the second electrically conductive coil, and
the spacer having a first flat face, the first flat face being separated from the first annular surface of the first coil by a first gap,
the magnetic element comprising:
a plurality of pairs of coils including the first coil and the second coil, each coil having an inner end and an outer end, the inner ends of each pair being connected together,
a plurality of first spacers including the spacer; and
a plurality of second spacers,
one of the first spacers having two flat faces and being between the two coils of a respective pair of coils, and
one of the second spacers being between a coil of one pair of coils and a coil of another pair of coils.

US Pat. No. 10,600,544

STACKED BODY AND METHOD OF PRODUCING STACKED BODY

MURATA MANUFACTURING CO.,...

1. A stacked body comprising:a base including a plurality of insulating base material layers made of thermoplastic resin;
a conductive pattern located on the plurality of insulating base material layers; and
a dummy pattern electrically isolated from the conductive pattern and extending along at least a portion of the conductive pattern outside of the conductive pattern on the plurality of insulating base material layers on which the conductive pattern is located in a plan view; wherein
the plurality of insulating base material layers are stacked on each other;
the conductive pattern includes a plurality of linear portions at an outermost side of the conductive pattern in a plan view;
the dummy pattern is located along the conductive pattern; and
a bent portion or a wide portion, which has a larger width than the other linear portions in a direction perpendicular or substantially perpendicular to a direction in which a linear portion extends, in a plan view, is located on at least one of the linear portion of the conductive pattern and the dummy pattern extending along the linear portion, excluding an end portion of the linear portion and an end portion of the dummy pattern.

US Pat. No. 10,600,540

LAMINATED COIL COMPONENT

TDK CORPORATION, Tokyo (...

1. A laminated coil component comprising:an element assembly formed by laminating a plurality of insulation layers; and
a coil unit formed inside the element assembly by a plurality of coil conductors, wherein:
the element assembly includes (1) a coil unit arrangement layer which has the coil unit arranged therein and is made from glass ceramic and (2) a crystalline shape retention layer which is made from glass-ceramic;
the coil unit arrangement layer contains no SrO and has a softening point of below 1050° C.;
no conductor is arranged in the shape retention layer; and
when baked, the coil unit arrangement layer becomes amorphous but retains its shape because of the crystalline shape retention layer which is not softened during baking.

US Pat. No. 10,600,538

PERMANENT MAGNET COMPRISING A STACK OF N PATTERNS

1. A magnet comprising a stack of N patterns stacked immediately one above the other in a stacking direction, where N is an integer number greater than or equal to two, each pattern comprising:i) an antiferromagnetic layer made of antiferromagnetic material,
ii) a ferromagnetic layer made of ferromagnetic material,
wherein
the direction of magnetization of the ferromagnetic layer is fixed by an exchange coupling with the antiferromagnetic layer of this pattern, and
the direction of magnetization of the ferromagnetic layer of N-1 patterns is fixed by an exchange coupling with the antiferromagnetic layer of an immediately adjacent pattern in the stack,
wherein the directions of magnetization of the ferromagnetic layers of all the patterns in said stack are identical to one another,
wherein at least one ferromagnetic layer in said stack comprises:
a first sub-layer made of CoFeB whose thickness is greater than 0.05 nm, and
a second sub-layer made of a ferromagnetic material different from CoFeB and whose thickness is greater than the thickness of the first sub-layer,
wherein the magnet is a permanent magnet and wherein the permanent magnet has a total magnetic moment per unit area greater than 50×10?3 A.

US Pat. No. 10,600,537

ELECTRICAL CABLE

TE CONNECTIVITY CORPORATI...

1. An electrical cable comprising:a conductor assembly having a first conductor, a second conductor, and an insulator structure surrounding the first conductor and the second conductor, the first and second conductors carrying differential signals, the insulator structure having an outer surface; and
a cable shield wrapped around the conductor assembly and engaging the outer surface of the insulator structure, the cable shield having an inner edge and a flap covering the inner edge, the cable shield forming a void at the inner edge, the void being located closer to the first conductor than the second conductor, the void compromising the first conductor by reducing an effective dielectric constant surrounding the first conductor;
wherein the first conductor is shifted closer to the cable shield a shift distance compared to the second conductor to increase capacitance of the first conductor compared to the second conductor, the shift distance being selected based on the size of the void and the volume of air introduced in to the void along the first conductor compared to the second conductor along the length of the electrical cable.

US Pat. No. 10,600,532

SERVICE LOOP FOR TOP DRIVE EQUIPMENT HAVING AN EMBEDDED LAY LINE

NEXANS, Courbevoie (FR)

1. A top drive service loop cable assembly comprising:a plurality of cabled internal cable components;
a jacket covering said internal cable components;
a flange connected to said jacket and supporting said internal cable components,
wherein said jacket has a recessed embedded lay line embossed into said cable and aligned with internal cable components,
wherein said recessed embedded lay line is impressed into uncured rubber of said jacket with a nylon tape coated with a release agent which is impressed into said uncured rubber via a mold extruder, during extrusion, and
wherein said jacket is vulcanized and then said nylon tape is removed, leaving said embossed and recessed embedded lay line in said jacket.

US Pat. No. 10,600,531

HIGHLY BENDABLE INSULATED ELECTRIC WIRE

YAZAKI CORPORATION, Mina...

1. A highly bendable insulated electric wire comprising:a conducting wire formed by stranding a plurality of metal strands; and
an insulator covering the conducting wire,
wherein a twist pitch ratio of the conducting wire (a twist pitch/an outer diameter of the conducting wire) is 10.8 or less,
the insulator is made of a resin composition containing a vinyl chloride resin and having an elongation rate of 130% or higher at ?40° C., and
an adhesion strength between the conducting wire and the insulator is 20 N or less.

US Pat. No. 10,600,528

PROCESS FOR PRODUCING GALLIUM-68 THROUGH THE IRRADIATION OF A SOLUTION TARGET

Ion Beam Applications S.A...

1. A process for producing and purifying 68Gallium radioisotope, the process comprising:irradiating a target containing a target solution comprising zinc using an accelerated particle beam;
diluting the irradiated target solution with water;
feeding the diluted target solution into a strong cation exchanger;
washing the strong cation exchanger;
eluting zinc isotopes from the strong cation exchanger with a zinc elution solution including acetone;
washing the strong cation exchanger;
eluting 68Gallium isotope from the strong cation exchanger with hydrochloric acid solution to obtain an eluted solution;
feeding the eluted solution into a strong anion exchanger,
washing the strong anion exchanger; and
eluting 68Gallium isotope from the strong anion exchanger with hydrochloric acid solution to obtain a final solution
wherein the irradiated target solution is diluted between 5 and 15 volume times with water.

US Pat. No. 10,600,526

CASK TRANSPORT ASSEMBLY

1. A system for transporting a cask comprising:a cask transport device including:
a support assembly including a plurality of support assembly wheels and a support frame coupled to and supported by the support assembly wheels;
a tower disposed above the support assembly;
an upper beam assembly coupled to the tower frame;
a bottom block assembly coupled to the upper beam assembly, the bottom block assembly movable from a first vertical position relative to the upper beam assembly to a second vertical position relative to the upper beam assembly; and
a controller; and
a low profile transport device having
a frame having a top surface and a recess disposed along the top surface to hold and transport an object;
a plurality of wheels disposed below the frame that support the frame;
a plurality of pivotable wheel struts coupled to the wheels, wherein the wheel struts are each individually adjustable relative to the frame from a first position relative to the frame to a second position relative to the frame to allow the low profile transport device to climb an obstacle without tilting the frame; and
a motor that generates movement of the wheels;
wherein movement of the low profile transport device is controllable via the controller on the cask transport device.

US Pat. No. 10,600,525

GAS PERMEABLE HYDROPHOBIC MATERIAL

Triad National Security, ...

1. A porous material configured for use as a filter material in a nuclear material storage container, the porous material comprising an aluminosilicate substrate and a coating having a thickness of greater than zero to 5 microns, the coating comprising a copper oxide coating, a copper oxide nanowire coating, a fluorine coating, a fluoride coating, or combinations thereof.

US Pat. No. 10,600,518

CONTROL ROD/CONTROL ROD DRIVE MECHANISM COUPLINGS

BWXT mPower, Inc., Charl...

1. An apparatus comprising:a connecting rod of a control rod assembly of a nuclear reactor, the connecting rod including:
a hollow or partially hollow connecting rod tube defining an interior volume and comprising a first material having a first density at room temperature, and
a filler disposed in the interior volume of the hollow or partially hollow connecting rod tube, the filler comprising a second material having a second density at room temperature that is greater than the first density,
wherein the connecting rod further comprises a welded plug sealing off the interior volume of the hollow or partially hollow connecting rod tube.

US Pat. No. 10,600,517

NETWORK SYSTEM OF INDIVIDUAL USER DEVICES TO GENERATE GROUP IMPLEMENTED TREATMENT PLAN

Medsphere Systems Corpora...

1. A method executed on a computing device to reduce redundant interventions during the generation and implementation of a collaborative medical treatment plan on a patient, the method comprising:receiving a plurality of selected diagnostic categories and a list of selected team members from a computing device in communication with a treatment plan server;
generating an initial treatment plan stored on the treatment plan server based on the selected diagnostic categories;
permitting client devices associated to the selected team members collaborating virtually to access the initial treatment plan on the treatment plan server, wherein the client devices are heterogeneous and networked;
updating the treatment plan periodically on the treatment plan server for access by the selected team members, wherein updating the treatment plan comprises:
(i) receiving a plurality of treatment objectives and a plurality of interventions based on the initial treatment plan from the client devices, each treatment objective being associated to one or more interventions; and
(ii) generating a completed treatment plan by:
(1) associating each individual team member to one or more interventions,
(2) generating a matrix of the individual team members and their associated one or more interventions, and
(3) assigning the interventions to the team members based on the matrix such that one or more individual interventions assigned to a single team member is shared between multiple treatment objectives; and
directing the plurality of client devices to present the updated treatment plan to the selected team members through the native user interfaces of the client devices, wherein said graphical user interfaces for the updated treatment plan are individualized for each selected team member.

US Pat. No. 10,600,515

OPERATIVELY TUNING IMPLANTS FOR INCREASED PERFORMANCE

1. A process for preoperatively selecting an implant optimized to a particular patient's biomechanical characterization, comprising:obtaining, from at least one of a CT device, an MRI device, a radiological device, an ultrasound device and an X-ray device, image data of a patient;
deriving, using a computing device, from the image data, a plurality of dimensions including at least one dimension that includes at least one of anatomic landmark data and soft tissue attachment data;
accessing a database containing a correlation of anatomic data and biomechanical function related to a plurality of implant designs;
executing, using the computer device, a plurality of iterative simulations of a model of the patient created from the plurality of dimensions and data from the database concerning at least one of the implant designs, wherein at least one parameter concerning a configuration of the at least one implant relative to the model of the patient is changed between iterations; and
calculating, from the plurality of iterative simulations, and outputting by the computing device a recommendation of at least one of implant size, implant position, and ligamentous releases.

US Pat. No. 10,600,514

INTUITIVE AUTOMATION IN PATIENT MODELING

Varian Medical Systems, I...

1. A method of automatic structure delineation, the method comprising:causing display, by a computer system, of an image from medical image data;
causing display, by the computer system, of a graphical user interface, the graphical user interface comprising a list of structures corresponding to an area of interest displayed in the image and one or more operations available to be performed;
receiving user supplied input through the graphical user interface, the user supplied input corresponding to a selection of structures from the list of structures;
determining and performing a Boolean operation based on the user supplied input, wherein the Boolean operation comprises a union of or an intersection of each structure of the selection of structures indicated by the user supplied input for inclusion in the Boolean operation;
generating a graphical delineation of the structures resulting from the Boolean operation;
storing the graphical delineation as one or more corresponding output structures; and
updating the display to include the graphical delineation of the one or more output structures.

US Pat. No. 10,600,511

ACCELERATING HUMAN UNDERSTANDING OF MEDICAL IMAGES BY DYNAMIC IMAGE ALTERATION

International Business Ma...

1. A method for dynamically altering at least one image, comprising:receiving a plurality of data, wherein the received plurality of data includes at least one existing medical image;
determining that one or more user instructions for the received existing image were received;
implementing the one or more user instructions on the received existing medical image; and
altering the received existing medical image based on the one or more implemented user instructions and a medical knowledge base,
wherein in response to determining at least one medical condition in connection with the received plurality of data, determining a plurality of progressions and a plurality of regressions based on the determined medical condition,
wherein the existing medical image is determined based on the determined plurality of progressions and determined plurality of regressions to the determined medical condition,
wherein the user dynamically switches the generated plurality of progressions and the generated plurality of regressions of the received existing medical image.

US Pat. No. 10,600,509

WEARABLE DEVICE FOR AUTOMATED CONSTRUCTION OF TRAINING PLANS AND METHOD OF USING THE SAME

INTERNATIONAL BUSINESS MA...

1. A system for automatically generating an athletic training schedule, comprising:a wearable device, including one or more sensors for determining a quantity of athletic training performed by a user wearing the wearable device and an athletic performance of the user; and
a processor configured to:
receive the quantity of athletic training performed and the athletic performance data from the wearable device, and to estimate a relationship between the quantity of athletic training performed and an increase in the athletic performance by fitting a known curve relating athletic training performed and an increase in athletic performance to the received quantity of athletic training performed and the athletic performance data from the wearable device, wherein the athletic performance data is an indication of athletic speed or a time required to complete an athletic event;
receive a selection of a competitive target;
estimating a performance level of the selected competitive target;
determine a minimum level of training needed to meet or exceed the estimated performance level, based on the estimated relationship between the quantity of athletic training performed and the athletic performance; and
automatically generate the athletic training schedule based on the determined minimum level of training.

US Pat. No. 10,600,507

COGNITIVE NOTIFICATION FOR MENTAL SUPPORT

INTERNATIONAL BUSINESS MA...

1. A computer implemented method, comprising:A computer implemented method, comprising:
monitoring, by a computer device, biometric data of a user;
monitoring, by the computer device, social media content of the user; and
determining, by the computer device and based on the biometric data and the social media content, that the user has experienced a changed mental state;
wherein the determining that the user has a changed mental state is based on the monitoring of the biometric data by monitoring the user's heart rate using a heart rate sensor, and by monitoring the social media content by performing a contextual analysis of the social media content to determine a topic of the social media content and a sentiment of the user while engaging in communicating on social media regarding the topic of the social media content,
wherein the sentiment of the user is determined by using at least one selected from a group consisting of: facial analysis using a camera; and tonal analysis using a microphone, and
wherein the determining that the user has experienced a changed mental state comprises:
correlating the social media content and the biometric data; and
determining that the biometric data deviates from a normal range of the heart rate concurrently with the determined topic of the social media content matching a predefined topic and the determined sentiment matching a predefined sentiment,
further comprising:
selecting a caregiver from among a plurality of caregivers based on a biometric feedback loop analysis using the biometric data for the determined topic and an evaluation of past effectiveness of each of the caregivers in providing a positive impact on the user's sentiments in the past with regard to the determined topic, wherein the positive impact is determined by improvements in the user's biometric data and in determined sentiments of the user for the determined topic of the social media content; and
notifying, by the computer device, the selected caregiver of the changed mental state.

US Pat. No. 10,600,503

SYSTEMS MEDICINE PLATFORM FOR PERSONALIZED ONCOLOGY

GEORGETOWN UNIVERSITY, W...

1. A method for providing data relating to cancer, the method comprising:(a) receiving, into a processing device, raw data of a plurality of data types selected from the group consisting of mRNA expression data, miRNA expression data, metabolomics data, DNA copy number data, and next-generation sequencing;
(b) in the processing device, normalizing the raw data into normalized data of a single data type, wherein said normalization comprises background correction, normalization between arrays, and offset, wherein the offset is calculated to shrink log ratios to zero at lower intensities to reduce variability of the log ratios for low intensity spots;
(c) storing the normalized data in a database, wherein said database is comprised of a correlation of the plurality of data types to clinical outcomes, wherein the normalized data are pre-processed and mapped to existing data structures prior to storage in said database;
(d) receiving a query for the data from a device used by a user into the database;
(e) performing the query through the normalized data in the database to locate the data; and
(f) outputting the data from the database to the device used by the user, wherein said output is comprised of a personalized clinical outcome comprising a cytobands display and a heatmap view.

US Pat. No. 10,600,502

SYSTEMS AND METHODS FOR DISPENSING A STATIN MEDICATION OVER THE COUNTER

AstraZeneca UK Ltd., Lon...

1. A method of managing cholesterol in a human subject with who was previously qualified for delivery of an over the counter statin pharmaceutical composition, the method comprising:a) receiving a re-order request from the subject for the statin pharmaceutical composition, at a computer system having a processor programmed to receive the re-order request;
b) providing a survey for obtaining a plurality of survey results from the subject, via a computer system having a processor programmed to perform the survey, wherein the plurality of survey results comprises:
whether the subject has experienced a muscle irregularity since taking the statin pharmaceutical composition,
whether the subject is pregnant,
whether the subject is taking a medication that interacts with the statin pharmaceutical composition, and
whether the subject had an atherosclerotic cardiovascular event or a heart procedure since last ordering the statin pharmaceutical composition;
c) receiving the plurality of survey results, at a computer system having a processor programmed to receive the survey results;
d) applying an algorithm to the plurality of survey results, via a computer system having a processor programmed to perform the algorithm, wherein the algorithm:
i) runs all or a portion of the plurality of survey results against a plurality of filters, wherein, when a respective filter in the plurality of filters is fired, the re-fulfillment process is terminated or the subject is provided with a warning corresponding to the respective filter, and wherein the plurality of filters comprises:
a pregnancy filter,
a muscle irregularity filter,
a drug interaction filter, and
an atherosclerotic cardiovascular event filter;
ii) obtains, when the re-fulfillment process is not terminated, acknowledgment from the subject for each warning issued to the subject by any filter in the plurality of filters, and
iii) proceeds with the re-fulfillment process when (1) the re-fulfillment process is not already terminated by the firing of a filter in the plurality of filters and (2) the subject has acknowledged each warning associated with each filter in the plurality of filters that was fired and that is associated with a warning, wherein the re-fulfillment process further comprises:
storing an indication in a subject profile of a re-order for the statin pharmaceutical composition,
communicating an over the counter drug facts label for the statin pharmaceutical composition to the subject, and
authorizing, upon confirmation from the subject that the over the counter drug facts label has been received and read, a re-order provision of the statin pharmaceutical composition to the subject, wherein the re-order provision includes a destination of the subject; and
e) administering, upon authorization of the re-order provision, the statin pharmaceutical composition to manage cholesterol in the human subject.

US Pat. No. 10,600,500

BAMBAM: PARALLEL COMPARATIVE ANALYSIS OF HIGH-THROUGHPUT SEQUENCING DATA

The Regents of the Univer...

1. A sequence analysis computer system comprising:a file system storing a first digital sequence file and a different, second digital sequence file wherein each file includes sequence short reads that are aligned with respect to sequence locations; and
at least one computer operating as a sequence analysis engine that is configured to:
identify in the first and second digital sequence files a first common sequence location from the sequence locations;
read from the first digital sequence file a first set of sequence short reads that overlap with the first common sequence location, thereby forming a first pileup stored in a memory;
read from the second digital sequence file a second set of sequence short reads that overlap with the first common sequence location, thereby forming a second pileup stored in the memory;
identify at least one variant as a difference among inferred bases at the first common sequence location as a function of the sequence short reads in the first pileup and the sequence short reads in the second pileup that overlap the first common sequence location by optimizing likelihoods of the inferred bases based on observed bases of the first pileup and the second pileup at the first common sequence location; and
output the at least one variant in a file as a sequence difference between the first digital sequence file and the second digital sequence file.

US Pat. No. 10,600,497

TIMING-DRIFT CALIBRATION

Rambus Inc., Sunnyvale, ...

1. A dynamic random access memory (DRAM) chip having a memory core, the memory core including a plurality of storage cells, the DRAM chip comprising:a signaling interface to receive an instruction from a memory controller that is separate from the DRAM chip;
an oscillator circuit to generate an oscillating signal; and
a counter circuit coupled to the oscillator circuit, wherein, in response to the instruction, the counter circuit is to begin a count of a number of edges of the oscillating signal, and wherein the counter circuit is to count the number of edges of the oscillating signal during a measurement duration period.

US Pat. No. 10,600,495

PARALLEL MEMORY SELF-TESTING

TEXAS INSTRUMENTS INCORPO...

1. Circuitry to perform parallel testing of a plurality of memories, comprising:a plurality of local adapters; and
a controller to generate a sequence of commands to be applied to one or more of the plurality of local adapters, each given command of the sequence of commands including expected data, and a command address;
each local adapter being coupled with the controller and with an associated memory of the plurality of memories to:
translate the given command to a memory type of the associated memory;
map the command address to a local address of the associated memory;
transfer the expected data to the local address of the associated memory; and
provide test results to the controller according to read data from the local address of the associated memory and the expected data of the given command.

US Pat. No. 10,600,494

METHODS AND APPARATUSES FOR SELF-TRIMMING OF A SEMICONDUCTOR DEVICE

Micron Technology, Inc., ...

1. An apparatus comprising:a semiconductor device comprising a self-trimming circuit configured to receive a reference voltage and a test command signal, the self-trimming circuit configured to convert the reference voltage to a target voltage based on the test command signal and further configured to adjust a voltage trim code until an internal voltage matches the target voltage to determine a trim level associated with the internal voltage.

US Pat. No. 10,600,492

HIGH STABILITY SHIFT REGISTER WITH ADJUSTABLE PULSE WIDTH

INT TECH CO., LTD., Hsin...

1. A high stability shift register with adjustable pulse width, comprising:a first signal processor, configured to receive a first voltage and generate a first signal and a second signal in response to a first sub-control signal and a second sub-control signal;
a second signal processor, configured to receive the first voltage, and generate a third signal and a fourth signal in response to a third sub-control signal, the first signal and the second signal; and
a third signal processor, configured to receive the first voltage and a second voltage having a voltage level different from that of the first voltage and generate an output signal in response to the third signal and the fourth signal;
wherein the first signal processor comprises:
a first transistor, having a first source terminal that is applied with the first voltage and a first gate terminal that is applied with the first sub-control signal;
a sixth transistor, having a sixth source terminal that is applied with the first sub-control signal and a sixth gate terminal that is applied with the second sub-control signal; and
a capacitor, having a first electrode that is applied with the second sub-control signal and a second electrode that is connected with a first node electrically connected with a first drain terminal of the first transistor,
wherein the first signal is outputted from the first node, and the second signal is outputted from a sixth drain terminal of the sixth transistor.

US Pat. No. 10,600,490

PROGRAMMING OF MEMORY CELLS IN THREE-DIMENSIONAL MEMORY DEVICES

YANGTZE MEMORY TECHNOLOGI...

1. A three-dimensional (3D) memory device, comprising:a NAND memory string extending vertically above a substrate and comprising a plurality of memory cells arranged vertically in series; and
a peripheral circuit configured to program the memory cells based on incremental step pulse programming (ISPP), wherein different verification voltages of the ISPP are applied to at least two of the memory cells,
wherein a first verification voltage applied to a first one of the memory cells is smaller than a second verification voltage applied to a second one of the memory cells that is above the first one of the memory cells in the NAND memory string, and
verification voltages applied to each of the memory cells increase from bottom to top of the NAND memory string.

US Pat. No. 10,600,487

METHODS OF ERASING DATA IN NONVOLATILE MEMORY DEVICES AND NONVOLATILE MEMORY DEVICES PERFORMING THE SAME

Samsung Electronics Co., ...

1. A method of erasing data in a nonvolatile memory device, comprising:applying an erase voltage to an erase source terminal of a memory block having a plurality of memory cells therein, which are stacked in a vertical direction relative to an underlying substrate;
applying a first voltage to a first selection line among a plurality of selection lines in the memory block, the first voltage being higher than the erase voltage, the first selection line being disposed closest to the erase source terminal among the plurality of selection lines and being used for selecting the memory block as an erase target block; and
applying a second voltage to a second selection line among the plurality of selection lines, the second voltage being lower than the erase voltage, the second selection line being disposed farther from the erase source terminal than the first selection line and being used for selecting the memory block as the erase target block.

US Pat. No. 10,600,486

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

SK hynix Inc, Gyeonggi-d...

1. A semiconductor memory device comprising:a memory block including a plurality of memory cell strings;
a peripheral circuit configured to perform an erase operation on the memory block; and
a control logic configured to control the peripheral circuit to apply operation voltages including first and second source line control voltages, a pre-erase voltage, and an erase voltage to a source line of the memory block sequentially to form a trap,
wherein the pre-erase voltage is configured to be applied to the source line to generate a gate induced drain leakage current,
wherein the erase voltage is configured to be applied to the source line to control memory cells of the memory block from a floating state to a ground voltage state, and
wherein the first source line control voltage has a greater level than the second source line control voltage.

US Pat. No. 10,600,484

SYSTEM AND METHOD FOR MINIMIZING FLOATING GATE TO FLOATING GATE COUPLING EFFECTS DURING PROGRAMMING IN FLASH MEMORY

Silicon Storage Technolog...

1. A memory device, comprising:an array of non-volatile memory cells, wherein each of the non-volatile memory cells includes a floating gate, and
a controller configured to:
identify programming values associated with incoming data, wherein each of the programming values is associated with a relative amount of electrons to be placed onto one of the floating gates;
perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

US Pat. No. 10,600,482

QUANTUM MEMORY DEVICE

OXFORD UNIVERSITY INNOVAT...

1. A quantum memory device for storing one or more modes of electromagnetic radiation, the quantum memory device comprising:an atomic ensemble comprising atomic valence electrons having a first state, a second state and a third state, wherein the second state has a higher energy than, and is linked to, the first state by an atomic transition, and the third state has a higher energy than, and is linked to, the second state by one or more atomic transitions;
a signal source of electromagnetic radiation arranged to generate one or more modes of electromagnetic radiation to be stored having a frequency corresponding to an off-resonant atomic transition between the first state and the second state of atomic valence electrons in the atomic ensemble, wherein the one or more modes of electromagnetic radiation from the signal source are arranged to be incident upon the atomic ensemble to stimulate off-resonant transitions of the atomic valence electrons in the atomic ensemble between the first state and the second state, and wherein the signal source electromagnetic radiation has a bandwidth of greater than 1 GHz;
one or more control sources of electromagnetic radiation each arranged to generate electromagnetic radiation having a frequency corresponding to an off-resonant atomic transition from the one or more atomic transitions linking the second state and the third state of atomic valence electrons in the atomic ensemble, wherein the electromagnetic radiation from the one or more control sources is arranged to be incident upon the atomic ensemble to stimulate off-resonant transitions of the atomic valence electrons in the atomic ensemble between the second state and the third state, and wherein the electromagnetic radiation from each of the one or more control sources has a bandwidth of greater than 1 GHz; and
wherein the quantum memory device is arranged such that on incidence of one or more modes of electromagnetic radiation from the signal source and electromagnetic radiation from each of the one or more control sources to the atomic ensemble, a coherent excitation of the transition between the first state and the third state is created that stores the one or more modes of electromagnetic radiation from the signal source in the atomic ensemble, and subsequent incidence of electromagnetic radiation from each of the one or more control sources upon the atomic ensemble stimulates emission of the one or more stored modes of electromagnetic radiation from the atomic ensemble.

US Pat. No. 10,600,478

MULTI-BIT CELL READ-OUT TECHNIQUES FOR MRAM CELLS WITH MIXED PINNED MAGNETIZATION ORIENTATIONS

Spin Memory, Inc., Fremo...

1. A memory device comprising:an array of Multi-Bit Cells (MBCs), the MBCs each including a plurality of cell elements having different sets of state parameter values, wherein a pinned magnetization polarization of a first cell of the plurality of cell elements is opposite a pinned magnetization polarization of a second cell of the plurality of cell elements;
one or more memory circuits configured to;
sequentially apply different successive sets of state programming conditions to a selected plurality of the MBCs, wherein a respective set of state programming conditions programs a corresponding one of the plurality of cell elements to a respective state parameter value;
determine, after applying each of the set of programming conditions, a state change result for the selected plurality of the MBCs; and
determine a read state of the selected plurality of MBCs based on the determined state change results.

US Pat. No. 10,600,476

ROW BASED MEMORY WRITE ASSIST AND ACTIVE SLEEP BIAS

Intel Corporation, Santa...

1. An apparatus comprising:an interconnect comprising a poly extending in a first direction;
a plurality of power supply rails extending in a second direction, wherein the second direction is parallel to the first direction, wherein the plurality of power supply rails include ground power supply rails; and
a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, and wherein the memory array comprises bit-cells that are organized such that there are no gap bit-cells in the array.

US Pat. No. 10,600,474

WRITE ASSIST

GLOBALFOUNDRIES INC., Gr...

1. A device, comprising:a core comprising a memory array, the memory array comprising memory cells having bitlines, the memory array being arranged in columns, wherein the core includes a metallization layer comprising connections to the memory array, and wherein the metallization layer is devoid of memory cells;
digit lines connected to the bitlines of a column of the memory array;
a write driver connected to the digit lines;
a write assist circuit connected to the write driver; and
a wire bridge located in the metallization layer of the core connecting the write assist circuit to the write driver,
the write assist circuit comprising:
a first precharge transistor connected to a first digit line, the first precharge transistor maintaining a first voltage on the first digit line prior to write operations,
a second precharge transistor connected to a second digit line, the second precharge transistor maintaining a second voltage on the second digit line prior to write operations,
a first boost signal connected to the first digit line, the first boost signal providing a first boost voltage to the first digit line during write operations, and
a second boost signal connected to the second digit line, the second boost signal providing a second boost voltage to the second digit line during write operations.

US Pat. No. 10,600,473

APPARATUSES AND METHODS TO PERFORM LOGICAL OPERATIONS USING SENSING CIRCUITRY

Micron Technology, Inc., ...

1. An apparatus, comprising:sensing circuitry including a sense amplifier and a compute component;
selection logic circuitry coupled to the sense amplifier via a pair of complementary sense lines and coupled to a first compute component storage location via a first pair of complementary signal lines and a second compute component storage location via a second pair of complementary signal lines; and
a controller coupled to the sensing circuitry and selection logic circuitry and configured to cause performance of a logical operation between an operand in the first compute component storage location or the second compute component storage location and an operand sensed by the sense amplifier.

US Pat. No. 10,600,472

SYSTEMS AND METHODS FOR MEMORY CELL ARRAY INITIALIZATION

Micron Technology, Inc., ...

1. An apparatus comprising:at least one mode register configured to enable an array reset mode;
a memory cell array including one or more sense amplifiers, each of the one or more sense amplifier including at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line;
control logic coupled to the memory cell array, and in communication with the at least one mode register, the control logic configured to:
drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage, wherein the bit-line precharge voltage corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines, wherein the at least one mode register is further configured to enable a self-refresh mode, wherein the control logic is further configured to generate, in response to the self-refresh mode being enabled, an internal self-refresh pulse, wherein the internal self-refresh pulse causes a current row address of the memory cell array to be activated; and
a refresh counter comparator, wherein the at least one mode register further comprises a valid data register, and wherein the refresh counter comparator is configured to set, at a first row address of the refresh counter, the valid data register to a first state indicating that all memory cells of the memory cell array have not been reset, and wherein when the refresh counter outputs the first row address a second time, resetting the valid data register to a second state indicating that all memory cells of the memory cell array have been reset and resetting the mode register.

US Pat. No. 10,600,471

SEMICONDUCTOR DEVICE PERFORMING ROW HAMMER REFRESH OPERATION

Micron Technology, Inc., ...

1. An apparatus comprising:a memory cell array including a plurality of word lines each coupled to a plurality of memory cells; and
a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command,
wherein a first number of the plurality of word lines are selected in response to the first internal signal, and
wherein a second number of the plurality of word lines are selected in response to the second internal signal, the second number is smaller than the first number.

US Pat. No. 10,600,468

METHODS FOR OPERATING FERROELECTRIC MEMORY CELLS EACH HAVING MULTIPLE CAPACITORS

WUXI PETABYTE TECHNOLOGIE...

1. A method for writing a ferroelectric memory cell comprising a transistor and N capacitors, where N is a positive integer greater than 1, wherein the transistor is electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a respective one of N plate lines in parallel, the method comprising:applying a plate line signal pulsed between 0 V and a supply voltage (Vdd) of the ferroelectric memory cell to each of the N plate lines according to a plate line time sequence; and
applying a bit line signal pulsed between 0 V and the Vdd to the bit line according to a bit line time sequence to write a valid state of data into the N capacitors, wherein
the data consists of N+1 valid states that can be written into the N capacitors;
the valid states of the data are determined based on the plate line time sequence; and
the bit line time sequence is determined based on the valid state of the data written into the N capacitors.

US Pat. No. 10,600,466

RESISTIVE MEMORY DEVICE HAVING REDUCED CHIP SIZE AND OPERATION METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A memory device comprising:a voltage generator generating a write word line voltage according to activation of a write enable signal;
a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output word line voltage;
a word line power path connected to the switch circuit to receive the output word line voltage; and
a word line driver driving a word line of the memory device according to a voltage applied to the word line power path, wherein the memory device starts to receive a write command after a certain delay following the activation of the write enable signal, and a write operation is performed on the memory device within an activation period of the write enable signal in response to the received write command,
wherein at least one read command is further received during the activation period of the write enable signal, and
wherein only a read command is received during a deactivation period of the write enable signal.

US Pat. No. 10,600,464

SEMICONDUCTOR STORAGE DEVICE, DRIVING METHOD, AND ELECTRONIC DEVICE

SONY CORPORATION, Tokyo ...

1. A semiconductor storage device, comprising:at least one or more selection transistors;
a resistance change element, wherein one end of the resistance change element is connected to a bit line and the other end of the resistance change element is connected to a drain terminal of a selection transistor, wherein a resistance value of the resistance change element changes in response to flowing a current of a predetermined value or larger through the resistance change element; and
a write control unit connected to a connection point between the selection transistor and the resistance change element, wherein the write control unit controls the current flowing through the resistance change element when data is written in the resistance change element, wherein the write control unit is a write control transistor, wherein a gate terminal of the write control transistor is short-circuited to one of a source terminal and a drain terminal of the write control transistor, wherein the one of a source terminal and a drain terminal of the write control transistor is connected to the connection point between the selection transistor and the resistance change element and the other of a source terminal and a drain terminal of the write control transistor is connected to a write control wiring, and wherein the selection transistor and the write control transistor have polarities that are different from each other.

US Pat. No. 10,600,463

MAGNETIC STORAGE DEVICE HAVING A MEMORY CELL INCLUDING A MAGNETORESISTIVE EFFECT ELEMENT AND A SELECTOR WHICH INCLUDES TITANIUM (TI), GERMANIUM (GE) AND TELLURIUM (TE)

TOSHIBA MEMORY CORPORATIO...

1. A magnetic storage device comprising:a first memory cell including a magnetoresistive effect element and a selector, the selector including titanium (Ti), germanium (Ge) and tellurium (Te).

US Pat. No. 10,600,460

PERPENDICULAR MAGNETIC MEMORY USING SPIN-ORBIT TORQUE

Everspin Technologies, In...

1. A memory, comprising:a first magnetic tunnel junction that includes:
a free magnetic layer;
a reference magnetic layer; and
a dielectric layer between the free magnetic layer and the reference magnetic layer; and
a first spin-orbit-torque control strip line on a first side surface of the free magnetic layer, wherein current in the first spin-orbit-torque control strip line causes spin current in the free magnetic layer, wherein the spin current is perpendicular to the first side surface of the free magnetic layer, and where the first side surface of the free magnetic layer is perpendicular to an interface of the free magnetic layer and the dielectric layer.