US Pat. No. 10,218,505

SERVER BASED SETTINGS FOR CLIENT SOFTWARE WITH ASYMMETRIC SIGNING

GOOGLE LLC, Mountain Vie...

1. A method, comprising:receiving, by a server, at least one value of settings for an application on a device separate from the server, the application configured to accept only signed settings values from the server and having a settings menu with preferences for how the application operates, the value associated with an authenticated user of the application;
signing the received value by the server;
storing, by the server, the received value in a database, wherein the received value is associated with the application and with the authenticated user in the database;
after storing the received value in the database, receiving, by the server, a request for the received value from the application on the device, the request generated by the authenticated user; and
in response to receiving the request for the received value, retrieving, by the server, the received value from the database, and providing a signed settings value corresponding to the received value to the application on the device.

US Pat. No. 10,218,504

PUBLIC KEY VALIDATION IN SUPERSINGULAR ISOGENY-BASED CRYPTOGRAPHIC PROTOCOLS

ISARA Corporation, Water...

1. A supersingular isogeny-based cryptography method, comprising:obtaining a secret integer of a first entity;
obtaining a public key of a second entity, the public key comprising a first image curve and a first pair of elliptic curve points;
computing, by operation of one or more processors, a second image curve based on the secret integer and the first pair of elliptic curve points;
computing, by operation of one or more processors, a shared secret value based on the second image curve, wherein the shared secret value is shared by the first entity and the second entity;
obtaining an encrypted generator point generated by the second entity, wherein the encrypted generator point comprises an encrypted version of a generator point obtained by the second entity based on a secret integer of the second entity and a second pair of elliptic curve points;
obtaining a decrypted generator point by decrypting the encrypted generator point based on the shared secret value; and
using the decrypted generator point to validate the public key.

US Pat. No. 10,218,503

ENCRYPTION KEY STORAGE AND MODIFICATION IN A DATA STORAGE DEVICE

SEAGATE TECHNOLOGY LLC, ...

15. A storage device, comprising:a first storage medium comprising a first portion of a hidden root key of an encryption key, the encryption key including the hidden root key combined with a zeroizable root key;
a one-time writable storage medium comprising at least one bit of the hidden root key, the one-time writable storage location including one or more electronic fuses; and
a processor configured to:
generate the hidden root key;
generate the zeroizable root key unique to a particular die of the storage device among a plurality of dies on the storage device, wherein the hidden root key is encrypted using the zeroizable root key;
combine the hidden root key with the zeroizable root key to generate the encryption key;
blow at least one of the one or more electronic fuses of the storage device to render the encryption key unusable;
store at least one bit of the hidden root key in a one-time writable storage location, the one-time writable storage location including the one or more electronic fuses;
determining that stored encrypted data is to be deleted; and
modify the at least one bit of the encryption key stored in the one-time writable storage location.

US Pat. No. 10,218,502

CONFIDENTIAL COMMUNICATION MANAGEMENT

VISA INTERNATIONAL SERVIC...

1. A client computer comprising:a memory that stores computer-executable instructions; and
one or more hardware processors configured to access the memory and execute the computer-executable instructions to implement a method comprising:
determining a client key pair comprising a client private key and a client public key;
determining a protected server key identifier associated with a server computer, the protected server key identifier encrypted by a server identifier encryption key maintained by the server computer, the protected server key identifier usable by the server computer to validate a server key identifier associated with a server private key;
identifying the server public key associated with the protected server key identifier;
generating a shared secret using the server public key and the client private key;
encrypting message data using the shared secret to obtain encrypted message data; and
sending, to the server computer, a message including the encrypted message data, the protected server key identifier, and the client public key.

US Pat. No. 10,218,501

METHOD, DEVICE, AND SYSTEM FOR ESTABLISHING SECURE CONNECTION

Huawei Device (Dongguan) ...

1. A method for establishing a secure connection, comprising:securely obtaining, by a first device, a first public key estimated value of a second device in an out-of-band manner, wherein the first public key estimated value is a value obtained after an operation is performed based on a first key-exchange public key of the second device by using a preset algorithm;
encrypting, by the first device, an asymmetric encryption public key of the first device by using the obtained first public key estimated value;
sending, by the first device, the encrypted asymmetric encryption public key and second key-exchange public key information of the first device to the second device, wherein the second key-exchange public key information comprises a second key-exchange public key of the first device, and the second key-exchange public key is used by the second device to generate a shared key by using the second key-exchange public key and a key-exchange private key of the second device and establish a secure connection to the first device by using the generated shared key;
receiving, by the first device, the encrypted first key-exchange public key of the second device that is sent by the second device, wherein the encrypted first key-exchange public key is obtained by the second device after the second device decrypts the received encrypted asymmetric encryption public key of the first device by using the first public key estimated value of the second device and encrypts the first key-exchange public key by using the decrypted asymmetric encryption public key of the first device;
decrypting, by the first device, the encrypted first key-exchange public key by using an asymmetric encryption private key corresponding to the asymmetric encryption public key;
performing, by the first device by using the preset algorithm, an operation based on the decrypted first key-exchange public key, to obtain a second public key estimated value; and
when the first public key estimated value is consistent with the second public key estimated value, determining, by the first device, that the decrypted first key-exchange public key is correct, generating a shared key by using a key-exchange private key of the first device and the decrypted first key-exchange public key, and establishing a secure connection to the second device by using the shared key.

US Pat. No. 10,218,499

SYSTEM AND METHOD FOR SECURE COMMUNICATIONS BETWEEN CONTROLLERS IN A VEHICLE NETWORK

Lear Corporation, Southf...

1. A system for secure communications between controllers in a vehicle network, the system comprising:a plurality of controllers associated in a group and configured to communicate with each other, each controller in the group having an initial controller identification (ID) number and configured to communicate with a gateway controller;
wherein each controller in the group is configured to calculate an updated controller ID number and to transmit in a secure fashion the updated controller ID number to the gateway controller, and the gateway controller is configured to authenticate the updated controller ID number of each controller in the group and to transmit in a secure fashion the updated controller ID number of each controller in the group to all of the controllers in the group; and
wherein each controller in the group is further configured to include its updated controller ID number in network messages transmitted to other controllers in the group, and to authenticate other controllers in the group based on the updated controller ID numbers in network messages received from the other controllers.

US Pat. No. 10,218,497

HYBRID AES-SMS4 HARDWARE ACCELERATOR

Intel Corporation, Santa...

1. A System on Chip (SoC) comprising:a processor core; and
a single hardware accelerator coupled to the processor core, the single hardware accelerator to encrypt or decrypt data, the single hardware accelerator comprising:
a first block cipher to encrypt or decrypt the data according to a first encryption algorithm;
a second block cipher to encrypt or decrypt the data according to a second encryption algorithm; and
a combined substitution box (Sbox) coupled to receive input from the first block cipher and the second block cipher for common computations, the combined Sbox comprising logic to perform Galois Field (GF) multiplications and inverse computations, wherein the inverse computations are in a common ground-field and extension-field polynomial for the first encryption algorithm of the first block cipher and for the second encryption algorithm of the second block cipher to provide a hybrid Sbox design.

US Pat. No. 10,218,496

OUTPUTTING A KEY BASED ON AN AUTHORIZED SEQUENCE OF OPERATIONS

Cryptography Research, In...

1. A method comprising:receiving a plurality of values associated with generating a key;
receiving a sequence of operations associated with generating the key;
determining, by a processing device, whether an ordering of operations and a number and type of the operations from the received sequence of operations matches an ordering of operations and a number and type of operations from an authorized sequence of operations; and
outputting the key when the ordering of the operations and the number and type of the operations from the received sequence of operations matches the ordering and the number and type of the operations from the authorized sequence of operations and not outputting the key when the ordering of the operations and the number and type of the operations from the received sequence of operations does not match the ordering of the operations and the number and type of the operations from the authorized sequence of operations.

US Pat. No. 10,218,495

SECURE COMPUTATION METHOD, SECURE COMPUTATION SYSTEM, SECURE COMPUTATION SERVER, REGISTRANT TERMINAL, USER TERMINAL AND PROGRAM

NIPPON TELEGRAPH AND TELE...

1. A secure computation method,wherein n>k is satisfied, where n and k are integers not less than 2; and
storages of n secure computation servers store n registered password shared values obtained by splitting a registered password of an informant and n utilization password shared values obtained by splitting a utilization password of an information analyst;
the secure computation method comprising:
a registration authentication request step in which an authentication request section of a registrant terminal allocates, to the n secure computation servers, n registration input password shared values obtained by splitting a registration input password input by the informant;
a registration authentication execution step in which authentication execution sections of at least k of the n secure computation servers verify whether the registration input password agrees with the registered password, by using the registration input password shared values and the registered password shared values;
a registration authentication result examination step in which the authentication request section of the registrant terminal receives authentication results that are results of verifying whether or not the registration input password agrees with the registered password from the at least k of the n secure computation servers, and judges to be authentication success only when all of the authentication results indicate authentication success;
a secret sharing step in which a secret sharing section of the registrant terminal splits target data input by the informant to generate n data shared values;
a registration request step in which a registration request section of the registrant terminal allocates the data shared values to the n secure computation servers;
a registration execution step in which registration execution sections of the n secure computation servers store the data shared values in the storages;
a utilization authentication request step in which an authentication request section of a user terminal allocates, to the n secure computation servers, n utilization input password shared values obtained by splitting a utilization input password input by the information analyst;
a utilization authentication execution step in which authentication execution sections of at least k of the n secure computation servers verify whether the utilization input password agrees with the utilization password, by using the utilization input password shared values and the utilization password shared values;
a computation request step in which a computation request section of the user terminal sends a data processing request for the target data to the n secure computation servers;
a secure computation step in which secure computation sections of at least k of the n secure computation servers execute secure computation of the data shared values in accordance with the data processing request to generate n processing result shared values, which are obtained by splitting a processing result obtained by executing requested data processing on the target data; and
a result recovering step in which a result recovering section of the user terminal recovers the processing result from, out of the processing result shared values, at least k processing result shared values received from the at least k of the n secure computation servers.

US Pat. No. 10,218,494

PERFORMING BLOCK FORM REDUCTIONS MODULO NON-MERSENNE PRIMES IN CRYPTOGRAPHIC PROTOCOLS

ISARA Corporation, Water...

1. A method of performing a cryptography protocol, the method comprising:producing an integer during execution of a cryptography protocol defined by a cryptosystem;
identifying a prime modulus, a first constant and a second, distinct constant defined by the cryptosystem, wherein the prime modulus is defined by the cryptosystem in terms of a plurality of constants comprising the first constant and the second constant;
computing, by operation of one or more processors, a plurality of block coefficients to represent the integer in a block form, the plurality of block coefficients comprising:
a first block coefficient obtained by a first modular reduction modulo the first constant; and
a second block coefficient obtained by a second modular reduction modulo the second constant;
computing, by operation of one or more processors, a reduced representation of the integer based on the plurality of block coefficients, wherein the reduced representation is less than the prime modulus; and
using the reduced representation of the integer in the execution of the cryptography protocol in a communication system, wherein the execution of the cryptography protocol further comprises exchange of cryptographic correspondence over a communication network between a first computing device and a second computing device in the communication system.

US Pat. No. 10,218,493

RADIO WITH DYNAMICALLY CONTROLLED CORRELATION THRESHOLD

Itron, Inc., Liberty Lak...

1. A method, comprising:receiving and processing, at an analog frontend, a radio frequency (RF) signal;
receiving, at a digital backend, digital signals based on the processed RF signal;
defining, by operation of a channelizer of the digital backend, a plurality of channels;
calculating, by operation of a logic device, a plurality of rates of false packet detections associated with the plurality of channels, respectively;
adjusting, by operation of a correlation threshold calculator, based at least in part on a first rate of false packet detections from among the plurality of rates of false packet detections, a first correlation threshold associated for use with a first channel from among the plurality of channels and for use with a first modulation scheme;
correlating, using a packet processor, a signal from the channelizer with a preamble of a packet, wherein the correlating is based at least in part on the first correlation threshold, the first channel and the first modulation scheme, wherein the packet processor comprises a plurality of correlation loops, each correlation loop associated with a respective correlation threshold from among a plurality of correlation thresholds adjusted by the correlation threshold calculator, and wherein at least some of the plurality of correlation thresholds are used to evaluate correlation of signals in a particular channel plan and at least some are used to evaluate correlation of signals using a particular modulation scheme;
decoding, by operation of one of a plurality of decoders, the packet within the first channel using the first modulation scheme.

US Pat. No. 10,218,492

CLOCK AND DATA RECOVERY FOR PULSE BASED MULTI-WIRE LINK

QUALCOMM Incorporated, S...

1. A method, comprising:transcoding a data word into a multi-digit number, wherein transcoding the data word into the multi-digit number includes embedding clock information in the multi-digit number; and
transmitting a combination of pulses over a plurality of connectors of a multi-wire communication link in each transmission interval in a sequence of transmission intervals, wherein each digit of the multi-digit number defines the combination of pulses for a corresponding transmission interval in the sequence of transmission intervals,
wherein a pulse is transmitted on at least one of the plurality of connectors during each transmission interval in the sequence of transmission intervals, and
wherein the plurality of connectors comprises N connectors and the multi-digit number is expressed as a base (2N?1) number.

US Pat. No. 10,218,491

RECEIVING CIRCUIT, INTEGRATED CIRCUIT, AND RECEIVING METHOD

SOCIONEXT INC., Yokohama...

1. A receiving circuit comprising:a deserializer circuit configured to convert serial data to parallel data in accordance with an operating clock;
a phase difference detection circuit configured to detect a phase difference between the operating clock and the serial data on the basis of the parallel data;
a control circuit configured to determine a phase adjustment amount for shifting a phase of the operating clock by 1 bit of the serial data in accordance with a result of integration of the phase difference when a separation of the parallel data output from the deserializer circuit is not logically correct; and
a phase interpolator circuit configured to cause the phase of the operating clock to shift by the 1 bit of the serial data by using the phase adjustment amount,
wherein the control circuit includes
a phase adjustment circuit configured to calculate the result of the integration of the phase difference by integrating the phase difference, and
a sequencer circuit configured to determine a phase correction amount for causing the phase of the operating clock to shift by the 1 bit on the basis of the result of the integration of the phase difference when the separation of the parallel data output from the deserializer circuit is not logically correct,
wherein the phase adjustment circuit is configured to determine the phase adjustment amount based on the result of the integration of the phase difference and the phase correction amount.

US Pat. No. 10,218,490

WIDEBAND SIMULTANEOUS TRANSMIT AND RECEIVE (STAR) SUBSYSTEM

Northrop Grumman Systems ...

1. A simultaneous transmit and receive (STAR) system, said system comprising:a single antenna aperture;
a transmitter circuit for transmitting signals over a frequency band through the antenna aperture;
a receiver circuit for receiving signals from the antenna aperture, where the receiver circuit uses the same frequency band as the transmitter circuit at the same time;
a circulator for directing transmit signals from the transmitter circuit to the antenna aperture and received signals from the antenna aperture to the receiver circuit; and
a canceller circuit including a plurality of tuners that operate on the transmit signals and digitally synthesize a cancellation signal which is injected into the receiver circuit, where the cancellation signal cancels out components of the transmit signals and correlated noise which are present in the received signals due to antenna reflection and circulator leakage, and where the plurality of tuners include true time delay tuners which apply a true time delay to a leakage component and a reflection component of each of one or more digital transmit signals, and amplitude tuners which apply an amplitude scale factor to the leakage component and the reflection component of each of the digital transmit signals.

US Pat. No. 10,218,489

WIRELESS BACKHAUL CONFIGURATION

Telefonaktiebolaget LM Er...

1. A method, performed in a network node, of coordinating transmission on a backhaul link with transmission on an end-user access link in a wireless network, wherein transmission is performed in time division duplex, TDD, radio frames transmitted on respective frequency bands on the backhaul link and the end-user access link, the method comprising:determining a backhaul TDD configuration of the backhaul link and an end-user access TDD configuration of the end-user access link;
selecting a backhaul sub-frame and an end-user access sub-frame;
determining an offset between the backhaul sub-frame and the end-user access sub-frame based on the backhaul TDD configuration and the end-user access TDD configuration and an amount of time to get data received via one of the links ready for transmission on the other link; and
adjusting transmission on the backhaul link or on the end-user access link by a time-shift based on the determined offset.

US Pat. No. 10,218,487

RADIO CONFIGURATION OPTIMIZATION FOR FULL-DUPLEX COMMUNICATIONS

Intel Corporation, Santa...

1. An apparatus of an Access Point (AP), the AP comprising transceiver circuitry that includes an AP Medium Access Control (MAC) layer, and processor circuitry that stores a full duplex radio configuration, the AP being configured to:receive from a station (STA), that includes a STA MAC layer, a Full Duplex Request To Send (FD-RTS) message that indicates that the STA has a STA message that has message length A to transmit to the AP, the FD-RTS being received during a transmission opportunity (TXOP) obtained by the STA;
responsive to reception of the FD-RTS, transmit to the STA a Full Duplex Clear To Send (FD-CTS) message; and
collaborate with the STA in dynamic adjustment of the full duplex radio configuration to reduce a difference between an expected transmission time of the STA message and an expected transmission time of an AP message,
wherein
the AP MAC layer is configured to implement a collaborative dynamic adjustment via a MAC layer protocol between the AP MAC layer and the STA MAC layer,
the AP is configured to compare message length A and message length B,
responsive to a comparison that indicates that message length B is less than message length A, the AP performs a calculation that minimizes the difference between an expected transmission time of the STA message and an expected transmission time of the AP message, and
the AP receives the entire STA message from the STA and transmits the entire AP message to the STA, in full duplex communication with the STA during the TXOP.

US Pat. No. 10,218,486

METHOD FOR TRANSMITTING AND RECEIVING SIGNAL FOR LOW LATENCY IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR

LG ELECTRONICS INC., Seo...

1. A method for transmitting a signal for low transmission latency in a wireless communication system, the method comprising:mapping a signal to at least one advanced subframe included in a radio frame; and
transmitting, by a transmitting side, the at least one advanced subframe to a receiving side,
wherein the radio frame comprises the at least one advanced subframe and at least one special symbol separated from the at least one advanced subframe,
wherein the at least one advanced subframe comprises N number of symbols, wherein N is smaller than or equal to 3, and
wherein the at least one special symbol is transmitted in a different time duration from a transmission time duration of the at least one advanced subframe.

US Pat. No. 10,218,485

METHOD AND APPARATUS FOR ALLOCATING CHANNEL STATE INFORMATION-REFERENCE SIGNAL IN WIRELESS COMMUNICATION SYSTEM

1. A method for receiving a signal, comprising:receiving a signal comprising Channel State Information Reference Signals (CSI-RSs) for antenna ports in an antenna port set; and
acquiring channel state information of a first antenna port in the antenna port set and channel state information of a second antenna port in the antenna port set based on the CSI-RSs,
wherein the CSI-RSs for the antenna ports in the antenna port set are mapped to 2 consecutive Resource Elements (REs) in a time-frequency resource area, the time-frequency resource area being defined by one sub-frame and 12 sub-carriers, and the 2 consecutive REs corresponding to 1 sub-carrier in a frequency axis and two symbols in a time axis,
wherein the CSI-RSs for the first antenna port and the second antenna port in the antenna port set are discriminated from each other by orthogonal codes including a first orthogonal code for the first antenna port and a second orthogonal code for the second antenna port, and
wherein the first orthogonal code is [1, 1], and the second orthogonal code is [1,?1].

US Pat. No. 10,218,482

NETWORK NODE AND METHOD FOR MANAGING TRANSMISSION OF CELL REFERENCE SYMBOLS

TELEFONAKTIEBOLAGET LM ER...

1. A method performed by a network node for managing transmission of Cell Reference Symbols (CRS), the method comprising:applying a first CRS mode with respect to a first subframe, wherein applying the first CRS mode with respect to the first subframe comprises transmitting in a first cell N PRBs (N>1) during the first subframe, wherein each of the N PRBs of the first subframe comprises at least one CRS, thereby, by applying the first CRS mode with respect to the first subframe the network node is transmitting CRS in all of the N PRBs of the first subframe;
determining that the first cell is not actively serving any user equipments (UEs);
after determining that the first cell is not actively serving any UEs, applying a second CRS mode with respect to second subframe, wherein applying the second CRS mode with respect to the second subframe comprises transmitting in the first cell N PRBs during the second subframe, wherein not more than M of the N PRBs of the second subframe comprises at least one CRS, wherein M is less than N, thereby, by applying the second CRS mode with respect to the second subframe, the network node is not transmitting CRS in all of the N PRBs of the second subframe.

US Pat. No. 10,218,481

APPARATUS AND METHOD FOR TRANSMITTING A REFERENCE SIGNAL IN A WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method of transmitting reference signals by a base station via a downlink channel including a physical downlink control channel (PDCCH) and a physical downlink shared channel (PDSCH) in a wireless communication system, the method comprising:determining first radio resources for first type channel state information reference signals (CSI-RSs) to be transmitted via a first sub-band and second radio resources for second type CSI-RSs, to be transmitted via a second sub-band, wherein each sub-band includes consecutive resource blocks (RBs), wherein the first type and second type CSI-RSs are used for channel measurement, wherein the first radio resources are determined by a first duty cycle and a first offset and the second radio resources are determined by a second duty cycle and a second offset;
transmitting control signal associated with the first and second radio resources, wherein the control signal includes first information on whether the first type CSI-RSs are periodic or aperiodic, wherein the control signal includes second information on whether the second type CSI-RSs are periodic or aperiodic, wherein the control signal includes third information on a time point to transmit the first type CSI-RSs when the first type CSI-RSs are aperiodic, wherein the control signal includes fourth information on a time point to transmit the second type CSI-RSs when the second type CSI-RSs are aperiodic; and
transmitting at least one of the first type CSI-RSs based on the first radio resources or the second type CSI-RSs based on the second radio resources.

US Pat. No. 10,218,480

UPLINK SOUNDING SIGNAL TRIGGERING METHOD AND SYSTEM, AND APPARATUS

HUAWEI TECHNOLOGIES CO., ...

13. A user equipment (UE), comprising:a memory storage comprising instructions;
a communication interface receiving a downlink control information (DCI) from a base station, with the DCI comprising a sounding reference signal (SRS) control information intended for each UE of Y number of UEs, and with Y comprising a positive integer greater than 1, with a bit quantity of the SRS control information intended for an ith UE in the Y number of UEs is ki, with i comprising an integer according to 1?i?Y, and with ki comprising a positive integer; and
a processor in communication with the memory and the communication interface, wherein the processor executes the instructions to trigger, after detecting that the DCI comprises SRS control information intended for the UE, an SRS transmission according to the SRS control information intended for the UE.

US Pat. No. 10,218,479

METHOD AND APPARATUS FOR TRANSMITTING CHANNEL STATE INFORMATION-REFERENCE SIGNALS IN WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method of estimating channel state information (CSI) at a user equipment (UE) in a wireless communication system, the method comprising:receiving, by the UE, resource information on N patterns among channel state information—reference signal (CSI-RS) transmission patterns for an 8-port CSI-RS transmission,
wherein N is an integer larger than 1;
receiving, by the UE, CSI-RSs for 8*N antenna ports via resource elements (REs) related to the N patterns, and
estimating the CSI based on the received CSI-RSs.

US Pat. No. 10,218,478

METHOD FOR DETERMINING WEIGHT FOR BEAMFORMING IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR

LG ELECTRONICS INC., Seo...

1. A method for determining a weight for hybrid beamforming by a base station in a wireless communication system, the method comprising:signaling to a user equipment a configuration for repeated transmission of a first omnidirectional beam equally formed in all directions;
receiving the first omnidirectional beam from the user equipment by forming a second omnidirectional beam;
repeatedly receiving the first omnidirectional beam from the user equipment by sequentially forming a plurality of directional beams corresponding to a plurality of directions; and
determining a weight for hybrid beamforming,
wherein the determining of the weight for hybrid beamforming comprises:
obtaining a gain difference between the first omnidirectional beam received through the second omnidirectional beam and the first omnidirectional beam received through a first directional beam among the plurality of directional beams;
selecting a precoding matrix indicator (PMI) from a codebook based on a combination of an index of the first directional beam and the gain difference; and
acquiring, based on the selected PMI, a coefficient of a phase shifter and a coefficient of a power amplifier for analog beamforming of the hybrid beamforming.

US Pat. No. 10,218,477

METHOD FOR DETERMINING CHANNEL QUALITY AND APPARATUS THEREOF

Beijing Zhigu Rui Tuo Tec...

1. A method for determining channel quality, the method comprising:at the same time when a data symbol is sent to a receiver by using a channel, receiving at least one reference signal by using the channel; and
determining, at least according to the at least one reference signal, quality of the channel at a corresponding moment when the data symbol is sent to the receiver.

US Pat. No. 10,218,476

TRANSMISSION OF REFERENCE SIGNALS

Nokia Solutions and Netwo...

1. A method comprising:determining resources for reference signalling by a mobile station on at least one component carrier of a plurality of aggregated component carriers;
sending, to the mobile station, information indicating the at least one component carrier of the plurality of aggregated component carriers and the associated resources to be used by the mobile station for configuration for reference signalling;
sending a trigger for reference signalling to the mobile station; and
receiving, in response to the trigger, at least one reference signal from the mobile station on the at least one component carrier indicated, wherein an uplink component carrier, on which the at least one reference signal is received, is derived by the mobile station from said information indicating the associated resources by analysing predefined bits of the information according to a pre-established protocol to identify the at least one component carrier and to determine time instances for transmission of reference signalling,
wherein indication of the at least one component carrier and the trigger are communicated in the same message,
and further comprising:
determining that the message is only for assigning resources for signalling of aperiodic channel state information;
checking the state of the trigger for reference signalling;
determining, based on the message, that only reference signalling is to be transmitted; and
determining at least one component carrier for reference signalling based on analysis of a predefined field of the message.

US Pat. No. 10,218,474

DEVICE AND METHOD OF HANDLING SCHEDULING REQUEST TRANSMISSION

HTC Corporation, Taoyuan...

1. A communication device for handling scheduling request (SR) transmissions, comprising:a storage unit, for storing instructions of:
being configured to communicate with a first cell and a second cell;
being configured a first SR period for a first SR transmission on the first cell and a second SR period for a second SR transmission on the second cell, wherein the second SR period is smaller than the first SR period;
starting a SR prohibit timer according to the second SR period;
releasing a SR configuration or a physical uplink control channel (PUCCH) configuration for the second SR transmission;
keeping the SR prohibit timer running in response to the release of the SR configuration or the release of the PUCCH configuration;
performing the first SR transmission on the first cell, after the SR prohibit timer expires; and
starting the SR prohibit timer according to the first SR period in response to the first SR transmission; and
a processing circuit, coupled to the storage unit, configured to execute the instructions stored in the storage unit.

US Pat. No. 10,218,473

CONTROL CHANNEL DETECTION METHOD, USER EQUIPMENT, AND BASE STATION

Huawei Technologies Co., ...

1. A control channel detection method, comprising:receiving, from a base station, parameter configuration information corresponding to different control channel resource sets, including performing rate de-matching according to zero power channel state information-reference signal (ZP CSI-RS) configuration information, wherein the parameter configuration information comprises information about a mapping relationship between an enhanced control channel element and an enhanced resource element group and comprises the ZP CSI-RS configuration information; and
detecting a control channel in the corresponding different control channel resource sets according to the parameter configuration information.

US Pat. No. 10,218,472

COMMUNICATION TERMINAL

Sun Patent Trust, New Yo...

1. A communication terminal, comprising:communication circuitry which, in operation, communicates with a first base station through a plurality of carriers, including at least a primary carrier and a secondary carrier, by carrier aggregation; and
control circuitry which, in operation:
measures reception quality of radio signals transmitted through the plurality of carriers from the first base station to obtain measured values;
compares the measured value of the primary carrier to a first threshold value; and
compares the measured value of the secondary carrier to a second threshold value, wherein the control circuitry:
when discontinuous reception is performed by the communication terminal, wherein periods during which the discontinuous reception is performed by the communication terminal include no data transmission and reception intervals of determined length:
when the measured value of the primary carrier is lower than the first threshold value, performs a cell search for a first corresponding carrier having a same frequency as the primary carrier, of a first neighboring cell, and for a second corresponding carrier, having a same frequency as the secondary carrier, of a second neighboring cell; and
when the measured value of the primary carrier is equal to or higher than the first threshold value, does not perform the cell search; and
when discontinuous reception is not performed by the communication terminal, determines whether to perform the cell search based on the measured value of the primary carrier and the measured value of the secondary carrier.

US Pat. No. 10,218,471

SELECTION OF POSITIONING REFERENCE SIGNAL OCCASIONS

QUALCOMM Incorporated, S...

1. A method for wireless communications at a user equipment (UE), comprising:identifying a first pair of positioning reference signal (PRS) occasions for monitoring a PRS at a first frequency and a second pair of PRS occasions for monitoring a PRS at a second frequency and occurring after the first pair of PRS occasions;
measuring a first PRS of the first pair of PRS occasions at the first frequency;
measuring a first PRS of the second pair of PRS occasions at the second frequency;
measuring a second PRS of the first pair of PRS occasions at the first frequency after measuring the first PRS of the second pair of PRS occasions at the second frequency;
generating a PRS measurement report;
establishing a radio resource control (RRC) connection with a base station or a location server, or both; and
transmitting the PRS measurement report to the base station or the location server, or both using the RRC connection.

US Pat. No. 10,218,470

SECONDARY SYNCHRONIZATION SIGNAL MAPPING

Intel Corporation, Santa...

1. An apparatus of a user equipment (UE), the apparatus comprising:processing circuitry, the processing circuitry configured to:
decode a primary synchronization signal (PSS) to obtain physical layer identity, the PSS received from an evolved Node-B (eNB);
decode a secondary synchronization signal (SSS) to obtain a physical-layer cell-identity group from two sequences, wherein the physical-layer cell-identity group is an integer, each of the two sequences taken from a set of N sequences indexed by an index pair;
determine a physical-layer cell identity (PCI) based on the physical layer identity and the physical-layer cell-identity group; and
perform time and frequency synchronization with a cell of the eNB based on the PSS and the SSS; and
memory, the memory coupled to the processing circuitry and configured to store the PCI.

US Pat. No. 10,218,469

UNIFIED FORWARD ERROR CORRECTION AND RETRANSMISSION IN A RELIABLE NETWORK PROTOCOL

VMWARE, INC., Palo Alto,...

1. A method of transmitting packets at a first node of a network to a second node of the network, comprising:transmitting packets from the first node to the second node;
determining a total number of packets that are in flight between the first node and the second node;
determining whether or not the total number of packets that are in flight is less than a threshold number of packets;
upon determining that the total number of packets that are in flight is less than the threshold number of packets, computing a target number of forward-error-correction (FEC) packets based in part on the total number of packets that are in flight;
transmitting a new FEC packet if a number of FEC packets that are in flight is less than the target number of FEC packets; and
transmitting a data packet if the number of FEC packets that are in flight is equal to or greater than the target number of FEC packets.

US Pat. No. 10,218,468

USB DEVICE, DATA TRANSFER SYSTEM AND DATA TRANSFER METHOD

Renesas Electonics Corpor...

1. A USB device comprising:a first processing unit configured to, when a predetermined error is included in a first header of a first packet received from a host apparatus, discard the first header and transmit a first payload of the first packet to a subsequent stage; and
a second processing unit configured to discard the first payload received from the first processing unit and transmit a first packet resending request to the host apparatus.

US Pat. No. 10,218,467

METHODS AND SYSTEMS FOR MANAGING ERROR CORRECTION MODE

PISMO LABS TECHNOLOGY LIM...

1. A method carried out at a first communications router for managing an error correction mode, comprising the steps of:(a) transmitting a first data packet to a second communications router;
(b) storing the first data packet in a local non-transitory storage medium;
(c) activating the error correction mode when a delay inquiry message is received from the second communications router; wherein the delay inquiry message indicates that the first data packet has not been received by the second communications router successfully;
(d) retransmitting the first data packet to the second communications router;
(e) transmitting an error correction packet corresponding to the first data packet; wherein the delay inquiry message comprises a global sequence number of the first data packet;
(f) deactivating the error correction mode when a back-to-normal message is received from the second communications router; wherein the back-to-normal message indicates that the first communications router no longer needs to be in error correction mode.

US Pat. No. 10,218,466

ENHANCED PHYSICAL CHANNEL TRANSMISSION METHOD, COMMUNICATIONS DEVICE, USER EQUIPMENT, AND BASE STATION

Huawei Technologies Co., ...

1. An enhanced physical channel transmission method at a base station or a user equipment served by the base station, comprising:determining each first information corresponding to each of one or more enhanced physical channel transmission levels, wherein each enhanced physical channel transmission level is respectively configured by the first information, and each first information comprises repetition configuration information and enhanced transmission configuration information that are of enhanced transmission of a physical channel, wherein the repetition configuration information is a repetition quantity of the enhanced transmission, and the enhanced transmission configuration information at least comprises a radio frame configuration information of an enhanced physical channel transmission opportunity and/or configuration information of the enhanced physical channel transmission opportunity;
determining, according to each first information, a start radio frame of an enhanced physical channel transmission opportunity corresponding to each enhanced physical channel transmission level and a start position, in the start radio frame, of the enhanced physical channel transmission opportunity, wherein the start position is a start subframe; and
performing the enhanced transmission of the physical channel by using the start position in the start radio frame as a start point;
wherein
the first subframe in the (X+1)th physical channel transmission opportunity in the start radio frame corresponding to each enhanced physical channel transmission level is used as the start subframe, and
X=mod (m×Rep_num, ON),
wherein Rep_num is the repetition quantity, ON is a quantity of physical channel transmission opportunities comprised in a radio frame that has a physical channel transmission opportunity, m is an integer greater than or equal to 0, mod is a modulo function.

US Pat. No. 10,218,465

METHOD AND SYSTEM FOR MAXIMIZING CHANNEL BANDWIDTH WHILE EMPLOYING ERROR CONTROL CODING

Nextivity, Inc., San Die...

1. In a data communication system that communicates data on a wireless channel, a method for maximizing channel bandwidth while employing error control coding, the method comprising:applying, by a communication device of the data communication system associated with the wireless channel, a cyclical redundancy check (CRC) code to information being transmitted on the channel;
extending the CRC code to include a single CRC code bit appended to the CRC code, the single CRC code bit having a value of 0;
adding, by the communication device and using the extended CRC code, an error correcting code to the information, the adding of the error correcting code including adding an additional information bit with a value of 0 to a plurality of error correcting code parity bits provided by the error correcting code to the information, the plurality of error correcting code parity bits also having a value of 0; and
transmitting, by the communication device, the information including the CRC code on the wireless channel without the single CRC code bit, the additional information bit, and the error correcting code parity bits;
receiving, by a receiving device of the data communication system, the transmitted information;
setting, by the receiving device, each of the single CRC code bit that is not transmitted, additional information bit, and error correcting code parity bits to 0; and
decoding, by the receiving device, the transmitted information, the decoding including decoding the information with the single CRC code bit, the additional information bit, and the error correcting code parity bits that have been set to 0.

US Pat. No. 10,218,464

METHOD AND AN APPARATUS FOR GENERATING A SECOND DATA PACKET FROM A FIRST DATA PACKET

Alcatel Lucent, Boulogne...

1. A method for generating a second data packet for a second network layer from a first data packet including a first header portion with information related to a first network layer higher than the second network layer, comprising:generating, based on the first header portion, a second header portion including information related to the second network layer;
encoding the second header portion using a first Forward Error Correction (FEC) code to provide a FEC encoded second header portion;
generating a payload portion including the first data packet;
encoding the payload portion using a second FEC code, different from the first FEC code, to provide a FEC encoded payload portion; and
generating the second data packet for the second network layer by linking the FEC encoded second header portion and the FEC encoded payload portion;
wherein the second header portion comprises information on a destination of the second data packet in the second network layer and an origin of the second data packet in the second network layer.

US Pat. No. 10,218,463

METHOD AND SYSTEM FOR WIRELESS LOCAL AREA NETWORK (WLAN) LONG SYMBOL DURATION MIGRATION

InterDigital Patent Holdi...

1. A method for supporting early detection of a frame by a station (STA), the method comprising:receiving, in a high efficiency signal A (HE-SIG-A) field of the frame, an indication of transmission opportunity (TXOP) duration and an indication of a modulation and coding scheme (MCS) of a high efficiency signal B (HE-SIG-B) field of the frame;
decoding the HE-SIG-B field based on the indicated MCS, wherein the HE-SIG-B field comprises a common field and a field indicative of a STA identifier; and
on a condition the field indicative of the STA identifier of the HE-SIG-B field matches an identifier of the STA, decoding a payload of the frame.

US Pat. No. 10,218,462

APPARATUS AND METHOD FOR SUPPORTING COOPERATIVE TRANSMISSION

ELECTRONICS AND TELECOMMU...

1. An apparatus for supporting cooperative transmission, the apparatus comprising:a controller configured to determine detection bits received from a plurality of relay terminals based on channel states between a source terminal and the plurality of relay terminals, the relay terminals configured to detect sub-data corresponding to the detection bits from data comprising a sequence of bits when the data is transmitted from a source terminal;
an interface configured to receive the sub-data from the relay terminals, respectively; and
a restorer configured to restore the data by combining the received sub-data,
wherein the plurality of relay terminals includes a first relay terminal and a second relay terminal, and
the controller is configured to determine an additional bit having a relatively low transmission error rate as a detection bit with respect to the first relay terminal, and determine a basic bit having a relatively high transmission error rate as a detection bit with respect to the second relay terminal.

US Pat. No. 10,218,461

WIRELESS COMMUNICATION METHOD, ENODEB, AND USER EQUIPMENT

Panasonic Intellectual Pr...

1. A wireless communication method performed by an eNode B (eNB), comprising steps of:transmitting a first downlink control information (DCI) to a user equipment (UE) in a first physical downlink control channel (PDCCH) candidate or enhanced PDCCH (EPDCCH) candidate; and
transmitting a second DCI to the UE in a second PDCCH candidate or EPDCCH candidate,
wherein an assignment of the second PDCCH candidate or EPDCCH candidate is determined based on an assignment of the first PDCCH candidate or EPDCCH candidate according to a defined algorithm, wherein the defined algorithm is based on an assignment dependency between the first PDCCH candidate or EPDCCH candidate and the second PDCCH candidate or EPDCCH candidate, and is configured through radio resource control (RRC) signaling or fixed by specification,
wherein an aggregation level (AL) for a group of PDCCH candidate(s) or EPDCCH candidate(s) suitable for transmitting the second DCI is based on an approximation function to approximate one of the possible ALs for the second DCI based on a determined relationship between a desired receiving power per bit of the first DCI and the second DCI according to the defined algorithm.

US Pat. No. 10,218,460

SYSTEM AND METHOD FOR IMPROVED PUSH-TO-TALK COMMUNICATION PERFORMANCE

KODIAK NETWORKS, INC., P...

1. A push-to-talk (PTT) application server comprising:one or more processors; and
a non-transitory, computer-readable medium storing programming executable by the one or more processors, the programming comprising instructions to:
receive a request from a user equipment (UE) device to access the PTT application server;
detect radio access network (RAN) congestion, and in response to detecting RAN congestion:
modify one or more PTT call parameters; and
transmit according to the modified one or more PTT call parameters to the UE device, wherein the modified one or more PTT call parameters comprises reducing a number of signals transmitted to the UE device.

US Pat. No. 10,218,459

APPARATUS AND METHODS FOR SYMBOL TIMING ERROR DETECTION, TRACKING AND CORRECTION

Maxlinear, Inc., Carlsba...

1. A method for communication, the method comprising:in a demodulator of a receiver, said demodulator comprising a fast Fourier transform (FFT) module, timing control circuitry, and a combiner:
sampling, by said FFT module, an input signal to generate a digital output signal of the demodulator;
generating, by said timing control circuitry, a first error signal based on a first characteristic of an output of said FFT module;
generating, by said timing control circuitry, a second error signal based on a second characteristic of said output of said FFT module, said output of said FFT being processed by an inverse fast Fourier transform module for said generating;
selectively combining, by said combiner, said first error signal and said second error signal to generate a third error signal; and
controlling, by a variable rate interpolator, a sampling timing of said FFT module using said third error signal.

US Pat. No. 10,218,458

SYSTEM AND METHOD FOR MULTI-USER FULL DUPLEX LINK ADAPTATION

FUTUREWEI TECHNOLOGIES, I...

1. A method comprising:providing, by a first serving point, a multi-user full duplex mode enabling a first link direction from a first wireless device to the first serving point, and a second link direction from the first serving point to a second wireless device;
requesting, by the first serving point from the second wireless device, a first channel quality indicator indicating channel quality between the first serving point and the second wireless device in a full duplex time period and a second channel quality indicator indicating channel quality between the first serving point and the second wireless device in a non-full duplex time period;
evaluating, by the first serving point, the full duplex mode using the first and second channel quality indicators; and
adjusting, by the first serving point, at least one parameter of the full duplex mode based on the evaluating.

US Pat. No. 10,218,457

TECHNIQUES FOR IMPROVING FEEDBACK PROCESSES BASED ON A LATENCY BETWEEN A TRANSMISSION TIME INTERVAL (TTI) AND A FEEDBACK OPPORTUNITY

QUALCOMM Incorporated, S...

1. A method for wireless communication, comprising:identifying a latency between a start of a transmission time interval (TTI) of a transmission burst and a scheduled feedback opportunity for the TTI;
determining a duration of the TTI of a transmission in the transmission burst, the duration including a number of symbol periods and being based at least in part on a time for feedback associated with the latency; and
performing the transmission before the scheduled feedback opportunity for the TTI based at least in part on the determined duration of the TTI.

US Pat. No. 10,218,456

MODULATION PROCESSING METHOD AND DEVICE

1. A coding and modulation processing method, wherein, the method comprises:a base station transmitting a high-layer configuration signaling to a user equipment (UE), wherein the high-layer configuration signaling is used to indicate whether to support a high-order Quadrature Amplitude Modulation (QAM) modulation scheme, and the high-order QAM modulation scheme is a modulation scheme of M QAM, wherein M is a number greater than 64;
after the base station transmits the high-layer configuration signaling, the method further comprises:
the base station transmitting a downlink control signaling to the UE, wherein the downlink control signaling at least comprises a modulation and coding scheme field (IMCS), when the high-layer configuration signaling indicates not supportimg the high-order QAM modulation scheme, then the modulation and coding scheme field (IMCS) being determined based on a first Modulation and Coding Schemes (MCS) table which does not support the high-order QAM modulation scheme; when the high-layer configuration signaling indicates supporting the high-order QAM modulation scheme, in combination with predefined information, determining whether the modulation and coding scheme field (IMCS) is determined based on a second MCS table which supports the high-order QAM.

US Pat. No. 10,218,455

METHOD AND APPARATUS FOR INCREASING AND DECREASING VARIABLE OPTICAL CHANNEL BANDWIDTH

Huawei Technologies Co., ...

1. A method for increasing variable optical channel bandwidth, the method comprising:adding, by a first network node, a timeslot increase indication to a higher order optical channel data unit (HO ODU) frame and sending the HO ODU frame to which the timeslot increase indication is added to a second network node, wherein the timeslot increase indication is used to instruct a timeslot, occupied by a flexible optical transport data unit (ODUflex) bit stream, of the HO ODU frame, starting from a next HO ODU frame of the HO ODU frame, to increase from X timeslots to Y timeslots, X is greater than zero and less than Y, and the second network node is a downstream network node of the first network node in a link through which a service stream flows;
starting from the next HO ODU frame of the HO ODU frame to which the timeslot increase indication is added, mapping, by the first network node, a bit stream at a third rate formed by an ODUflex bit stream at a first rate and an idle data bit stream at a second rate to the Y timeslots of the HO ODU frame and sending the HO ODU frame to the second network node, wherein a rate corresponding to the Y timeslots of the HO ODU frame is greater than or equal to the third rate, both the first rate and the second rate are less than the third rate, and the second rate is a difference value between the third rate and the first rate;
after each network node in the link receives the HO ODU frame to which the timeslot increase indication is added, mapping, by the first network node, an ODUflex frame to which a rate increase indication is added to the HO ODU frame and sending the HO ODU frame to the second network node, wherein the ODUflex frame to which the rate increase indication is added is an ODUflex frame bearing the ODUflex bit stream, and the rate increase indication is used to instruct a rate of the ODUflex bit stream, starting from a next ODUflex frame of the ODUflex frame to which the rate increase indication is added, to increase from the first rate to the third rate; and
starting from the next ODUflex frame of the ODUflex frame to which the rate increase indication is added, mapping, by the first network node, the ODUflex bit stream at the third rate to the Y timeslots of the HO ODU frame and sending the HO ODU frame to the second network node.

US Pat. No. 10,218,454

OPEN, MODULAR, AND SCALABLE OPTICAL LINE SYSTEM

Google LLC, Mountain Vie...

1. A reconfigurable optical add/drop multiplexer (ROADM) comprising:a plurality of interconnected ROADM blocks, each ROADM block including an egress switchable-gain amplifier, an output power detector coupled to an output of the egress switchable-gain amplifier, and a wavelength-selective switch coupled to an input of the egress switchable-gain amplifier;
a plurality of noise loading amplifiers, each noise loading amplifier coupled to a port of the wavelength-selective switch;
a plurality of add/drop blocks coupled to the wavelength-selective switches of the plurality of ROADM blocks; and
a controller configured to:
activate each noise loading amplifier that is coupled to an unused port of the wavelength-selective switch;
receive an indication of an output signal power from the output power detector; and
adjust gain and equalization parameters of the egress switchable-gain amplifier based on the received indication of the output signal power.

US Pat. No. 10,218,453

METHODS AND APPARATUS FOR LOGICAL ASSOCIATIONS BETWEEN ROUTERS AND OPTICAL NODES WITHIN A WAVELENGTH DIVISION MULTIPLEXING (WDM) SYSTEM

Juniper Networks, Inc., ...

1. An apparatus, comprising:a memory; and
a processor operatively coupled to the memory, the processor configured to be operatively coupled to an optical multiplexer, the optical multiplexer including a plurality of input ports,
the processor configured to partition the plurality of input ports into a plurality of input port groups including a first input port group and a second input port group, the first input port group including a first set of input ports from the plurality of input ports, the second input port group including a second set of input ports from the plurality of input ports mutually exclusive from the first set of input ports,
the processor configured to assign a first router identifier to the first input port group, the first router identifier associated with a first router,
the processor configured to assign a second router identifier to the second input port group, the second router identifier associated with a second router,
the processor configured to associate, based on the first router identifier, the first input port group with the first router and associate, based on the second router identifier, the second input port group with the second router causing (1) the first router to be operatively coupled to the optical multiplexer via the first set of input ports and not the second set of input ports, and (2) the second router to be operatively coupled to the optical multiplexer via the second set of input ports and not the first set of input ports, when the optical multiplexer is operatively coupled to the first router and the second router.

US Pat. No. 10,218,452

HIGH SPEED EMBEDDED PROTOCOL FOR DISTRIBUTED CONTROL SYSTEM

Concio Holdings LLC, Win...

1. An apparatus for use in communicating with other devices over a control network, the apparatus comprising:a processing device configured to operatively connect through a communication port to control receiving and sending communications over a control network;
the processing device configured to communicate using a protocol within a CAN message frame;
wherein the protocol includes:
transmission of a synchronization pulse at a first edge of the CAN message frame, and
synchronizing bit timing between a CAN message bit timing and the protocol's bit timing, which is faster than the CAN message bit timing, at one or more falling edges of the CAN message frame or during or just after the synchronization pulse.

US Pat. No. 10,218,451

COMMUNICATION DEVICE FOR PERFORMING CARRIER SEARCH IN TD-SCDMA SYSTEM AND METHOD OF CONTROLLING SAME

Samsung Electronics Co., ...

1. A communication device operating in a wireless communication system, the communication device comprising:a memory configured to store frequency history information; and
a processor electrically connected to the memory,
wherein the processor is configured to:
measure reception power of at least one of a plurality of first signals included in a first band,
determine a first candidate frequency set according to a strength of the reception power,
determine a second candidate frequency set from the first candidate frequency set based on the frequency history information, and
determine whether a cell corresponding to a second frequency included in the second candidate frequency set exists,
wherein if a first frequency in the first candidate frequency set is included in the frequency history information, a primary frequency included in the frequency history information is added to the first candidate frequency set so as to determine the second candidate frequency set.

US Pat. No. 10,218,450

INTERFERENCE MITIGATION IN SHORT-RANGE WIRELESS COMMUNICATION

AMAZON TECHNOLOGIES, INC....

1. A method of short-range wireless communication, comprising:determining with a power detector circuit of a first device that a first energy level of a first received wireless signal is greater than or equal to ?25 dBm/MHz, wherein a first component of the first received wireless signal is generated by a first radio of a second device, the first radio configured to generate signals in a first frequency range from 2402 MHz to 2480 MHz, and wherein a second component of the first received wireless signal is generated by a second radio of the second device, the second radio configured to generate signals in a second frequency range from 2300 MHz to 2400 MHz and in a third frequency range from 2496 MHz to 2690 MHz, and wherein the second device is located in close proximity of the first device;
sending the first received wireless signal to a first attenuator circuit;
attenuating, with the first attenuator circuit, the first energy level of the first received wireless signal by between 30 dB and 60 dB to generate a first attenuated signal;
determining that a second energy level of a second received wireless signal is between ?25 dBm/MHz and ?50 dBm/MHz, wherein the second received wireless signal is received from the second device;
sending the second received wireless signal to a second attenuator circuit;
attenuating, with the second attenuator circuit, the second energy level of the second received wireless signal by a second amount of less than or equal to 30 dB to generate a second attenuated signal;
filtering, with an intermediate frequency (IF) filter, the first attenuated signal to generate a first output signal, wherein the filtering the first attenuated signal comprises attenuating first frequencies of the first attenuated signal outside of a first passband of the IF filter;
filtering, with the IF filter, the second attenuated signal to generate a second output signal, wherein the filtering comprises attenuating second frequencies of the second attenuated signal outside of a second passband of the IF filter, wherein the first passband is narrower than the second passband;
demodulating the first output signal to generate a first data effective to cause the first device to perform a first action; and
demodulating the second output signal to generate second data effective to cause the first device to perform a second action.

US Pat. No. 10,218,449

FREQUENCY/PHASE SYNTHESIZER NOISE CANCELLATION

QUALCOMM Incorporated, S...

1. An open-loop feed-forward cross-correlator noise cancellation device, comprising:a synthesizer to generate a synthesized output clock signal based at least in part on a reference clock signal;
a cross-correlator device coupled to the synthesizer to receive the reference clock signal and the synthesized output clock signal and to cross-correlate the reference clock signal and the synthesized output clock signal to generate a cross-correlated output signal; and
a delay line coupled to the cross-correlator device, a delay of the delay line based at least in part on the cross-correlated output signal.

US Pat. No. 10,218,448

SYSTEM AND METHOD FOR DETERMINING VEHICLE POSITION BASED UPON LIGHT-BASED COMMUNICATION AND TIME-OF-FLIGHT MEASUREMENTS

OSRAM SYLVANIA Inc., Wil...

1. A first light based communication (LBC) system on a first vehicle for determining vehicle position, the system comprising:a transmitter array of light emitting diodes (LEDs);
a receiver array of photodiodes, wherein the receiver array has a solid angle of view and each photodiode is associated with a non-overlapping subset of the solid angle of view; and
a controller coupled to the transmitter array of LEDs and the receiver array of photodiodes, the controller including a processor configured to determine a relative distance between the first vehicle and a second vehicle based on a digital message and a time-of-flight pulse, wherein:
an angle of the second vehicle with respect to the first vehicle is determined to be within the subset of the solid angle of a first photodiode in the receiver array that received the digital message;
the time-of-flight pulse provides an absolute distance between the first vehicle and the second vehicle; and
the angle and the absolute distance are used by the processor to determine the relative distance between the first vehicle and the second vehicle.

US Pat. No. 10,218,447

FREQUENCY DEVIATION COMPENSATION SCHEME AND FREQUENCY DEVIATION COMPENSATION METHOD

NEC CORPORATION, Tokyo (...

1. A frequency deviation compensation device comprising:a frequency deviation compensator configured to compensate for a frequency deviation caused to a signal by frequency shifting; and
a phase offset compensator configured to compensate for a phase offset caused to the signal due to the frequency shifting.

US Pat. No. 10,218,446

METHOD AND APPARATUS FOR CHARACTERIZATION AND COMPENSATION OF OPTICAL IMPAIRMENTS IN INP-BASED OPTICAL TRANSMITTER

Finisar Corporation, Hor...

1. A method for characterizing and compensating for optical impairments in an optical transmitter, the method comprising:a) operating an optical transmitter comprising a first parent Mach-Zehnder (MZ) modulator and a second parent MZ modulator, wherein each of the first and second parent MZ modulators comprises a plurality of child MZ modulators;
b) biasing each of the plurality of child MZ modulators in the first and second parent MZ modulators at respective initial operating points;
c) generating an electro-optic RF transfer function for each of the plurality of child MZ modulators by measuring a plurality of optical output powers of the optical transmitter while sweeping characterizing RF input drive power levels applied to each of the plurality of child MZ modulators;
d) determining curve fitting parameters for each of the plurality of electro-optic RF transfer functions;
e) determining operating points of each of the plurality of child MZ modulators using the curve fitting parameters;
f) determining an IQ power imbalance at a particular operating point for each of the first and the second parent MZ modulators using the curve fitting parameters for each of the plurality of electro-optic RF transfer functions;
g) determining initial RF input drive power levels applied to each of the plurality of child MZ modulators that compensate for the determined IQ power imbalance for each of the first and the second parent MZ modulators;
h) determining XY power imbalance of the optical transmitter at the determined initial RF input drive power levels using the curve fitting parameters;
i) determining operating RF input drive power levels that at least partially compensate for the first and second IQ power imbalances and for the XY power imbalance of the optical transmitter; and
j) generating an optical signal comprising a Nyquist-pulse-shape at an output of the optical transmitter.

US Pat. No. 10,218,445

MINIMIZING POLARIZATION-DEPENDENT OPTICAL POWER FOR TRANSMITTERS

Juniper Networks, Inc., ...

1. A system, comprising:one or more devices to:
generate an alternating current bias voltage;
determine a first power level of a first signal output from a first modulator,
the first signal being a first optical signal associated with a particular polarization orientation;
determine a second power level of a second signal output from a second modulator,
the second signal being a second optical signal associated with the particular polarization orientation;
determine a relationship between the first power level and the second power level;
generate, based on the relationship between the first power level and the second power level, an error signal;
generate, based on the error signal, a direct current bias voltage;
generate, based on the alternating current bias voltage and the direct current bias voltage, a combined signal; and
set, based on the combined signal, a reverse bias voltage associated with the first modulator,
the reverse bias voltage being used to control the first power level of the first signal.

US Pat. No. 10,218,444

PAM4 TRANSCEIVERS FOR HIGH-SPEED COMMUNICATION

INPHI CORPORATION, Santa...

1. A transceiver system comprising:an input terminal for receiving input data stream, the input data stream being characterized by a first frequency;
a first voltage gain amplifier being configured to generate a first driving signal, the first voltage gain amplifier comprising an integrated equalizer, the first voltage gain amplifier being characterized by a bandwidth of at least 13 GHz and a gain range of at least 12 dB;
a track and hold (T/H) module comprising a first plurality of T/H circuits, the first plurality of T/H circuits being controlled by the first driving signal for holding the input data stream at a second frequency;
a shift and hold (SH) buffer comprising a first plurality of buffer units corresponding to the first plurality of T/H circuits, the first plurality of buffer units being configured to store a first plurality of samples based on the input data stream;
an analog-to-digital converter (ADC) module comprising a first plurality of ADC circuits being configured to convert the first plurality of samples; and
a digital signal processor (DSP) being configured to generate output data stream based at least one the first plurality of samples.

US Pat. No. 10,218,440

METHOD FOR VISIBLE LIGHT COMMUNICATION USING DISPLAY COLORS AND PATTERN TYPES OF DISPLAY

FOUNDATION FOR RESEARCH A...

1. A visible light communication (VLC) method in which a transmission device having a display transmits a signal to a reception device having a camera, the method comprising:modulating, by the transmission device, individual video frames of transmission data into modulated data by using different spreading codes according to variable transparent amplitude shape color (VTASC) modulation; and
including, by the transmission device, the modulated data in a visible light signal by using at least one of a color and a pattern, and outputting the visible light signal through the display; and
receiving, by the reception device, the visible light signal through the camera, and extracting the transmission data.

US Pat. No. 10,218,438

DISTRIBUTED ARRAY FOR DIRECTION AND FREQUENCY FINDING

Phase Sensitive Innovatio...

1. An optical imaging receiver comprising:a phased-array antenna including a plurality of antenna elements arranged in a first pattern configured to receive RF signals from at least one RF source;
a plurality of electro-optic modulators corresponding to the plurality of antenna elements, each modulator configured to modulate an optical carrier with a received RF signal to generate a plurality of modulated optical signals;
a plurality of optical channels configured to carry the plurality of modulated optical signals and configured to cause interference amongst the optical signals, each of the plurality of optical channels having an output to emanate the corresponding modulated optical signal out of the corresponding optical channel, the outputs of the plurality of optical channels arranged in a second pattern which does not correspond to the first pattern;
a plurality of photodetectors for recording the optical signal interference; and
a module for computationally reconstructing RF sources in k-space from the recorded interference.

US Pat. No. 10,218,437

COHERENT OPTICAL RECEIVER TESTING

Elenion Technologies, LLC...

1. An apparatus for measuring a characteristic of a coherent optical receiver (COR) that comprises one or more optical mixers followed by one or more differential photodetectors, the apparatus comprising:one or more coherent light sources configured to provide first and second lights with an optical frequency shift f therebetween, wherein the first light is modulated in amplitude at a first modulation frequency F1>f, and,
first and second output optical ports for coupling one of the first and second lights into a local oscillator (LO) port of the COR and the other of the first and second lights into an optical signal port of the COR.

US Pat. No. 10,218,435

MULTIPLE POLARIZATION FIBER OPTIC TELEMETRY

Halliburton Energy Servic...

1. An apparatus comprising:an input fiber optic cable configured to propagate a plurality of actively orthogonally polarized light beams;
an electro-optic modulator coupled to the input fiber optic cable and to a data stream, the electro-optic modulator configured to modulate the plurality of actively orthogonally polarized light beams in response to the data stream such that the plurality of actively orthogonally polarized light beams propagate the same data through an output fiber optic cable, wherein the electro-optic modulator comprises a first phase modulator configured to phase modulate a first actively orthogonally polarized light beam of the plurality of actively orthogonally polarized light beams;
a beam splitter coupled between the input fiber optic cable and the first phase modulator to split, from an input light beam, the plurality of actively orthogonally polarized light beams into the first and a second actively orthogonally polarized light beam, wherein the first phase modulator is coupled to the beam splitter and configured to generate a first modulated orthogonally polarized light beam;
a second phase modulator coupled to the beam splitter and configured to generate a second modulated orthogonally polarized light beam; and
a beam combiner coupled between the first and second phase modulators and the output fiber optic cable, the polarization beam combiner configured to combine the first and second modulated orthogonally polarized light beams into an output beam.

US Pat. No. 10,218,434

MONITORING OPTICAL FIBRE LINK

Telefonaktiebolaget LM Er...

1. A method of monitoring an optical fibre link, comprising:generating a monitoring signal used for monitoring the optical fibre link;
combining the generated monitoring signal with a data signal to be transmitted over the optical fibre link;
detecting backscattering of the monitoring signal from the optical fibre link;
comparing the detected backscattered monitoring signal with an estimated backscattered monitoring signal; and
determining, based on the comparison, at least one location along the optical fibre link where the monitoring signal is backscattered, and signal loss caused by the backscattering.

US Pat. No. 10,218,430

INTEGRATED MIXED-SIGNAL ASIC WITH DAC AND DSP

SEAKR ENGINEERING, INC., ...

1. An integrated digital to analog converting RF transmitter implemented in a satellite, comprising:a plurality of radiation tolerant high speed digital to analog converters (DACs) units, which each receive a sampled digital signal and output an RF signal;
a plurality of radiation tolerant digital inputs; and
one or more radiation tolerant digital signal processing (DSP) cores, which each process data from one or more of the radiation tolerant digital inputs and output the processed data to at least one radiation tolerant high speed DAC;
wherein one or more of the radiation tolerant high speed DACs, the one or more of the radiation tolerant digital inputs, and/or the one or more radiation tolerant DSP cores have been determined, by testing, to be radiation tolerant and have a heavy ion cross section less than or equal to 10?4 cm2 (square centimeters) at a linear energy transfer greater than or equal to 37 MeV-cm2/mg (mega-electronVolts-square centimeters per milligram).

US Pat. No. 10,218,427

DIVERSITY RECEIVER CONFIGURATION WITH COMPLEMENTARY AMPLIFIERS TO SUPPORT CARRIER AGGREGATION

SKYWORKS SOLUTIONS, INC.,...

1. A diversity receiver configuration configured to support carrier aggregation, the configuration comprising:a diversity receiver (DRx) module having an input that receives a diversity signal that includes data modulated onto multiple frequency bands; a splitter configured to split the diversity signal into a plurality of signals at a respective plurality of frequency bands propagated along a corresponding plurality of DRx paths; a plurality of bandpass filters, individual bandpass filters disposed along a corresponding one of the plurality of DRx paths and configured to filter a signal received at the bandpass filter to a respective frequency band; a plurality of DRx amplifiers, individual DRx amplifiers disposed along a corresponding one of the plurality of DRx paths and configured to amplify a signal received at the DRx amplifier; a combiner configured to combine amplified signals from the plurality of DRx amplifiers into a processed diversity signal; and an output that outputs the processed diversity signal;
a diversity radio frequency (DRF) module having an input that receives the processed diversity signal; a downstream multiplexer configured to provide a plurality of DRF paths for the processed diversity signal; a plurality of downstream amplifiers, each one of the plurality of downstream amplifiers disposed along a corresponding one of the plurality of DRF paths and configured to amplify a signal received at the downstream amplifier; and a corresponding plurality of outputs configured to couple outputs of individual downstream amplifiers to a transceiver; and
a controller configured to communicate with the DRx module and with the DRF module, the controller configured to change an amount of gain provided by a downstream amplifier in response to adjusting an amount of gain provided by a DRx amplifier.

US Pat. No. 10,218,424

REFERENCE SIGNAL INDICATIONS FOR MASSIVE MIMO NETWORKS

Nokia Technologies Oy, E...

1. A method comprising:transmitting a reference signal on a downlink beam to a user equipment;
receiving from the user equipment a reference signal sequence;
determining from the received reference signal sequence at least one preferred uplink beam to pair with the downlink beam, wherein the at least one preferred uplink beam is determined based on measurement results of a channel state information reference signal for the downlink beam;
sending downlink signaling to the user equipment on at least the downlink beam; and
receiving uplink signaling from the user equipment on the at least one preferred uplink beam.

US Pat. No. 10,218,423

METHOD FOR REPORTING CHANNEL STATE INFORMATION USING POLARIZATION CHARACTERISTICS OF ANTENNA IN WIRELESS COMMUNICATION SYSTEM AND DEVICE THEREFOR

LG ELECTRONICS INC., Seo...

1. A method for reporting channel state information to a base station (BS) by a user equipment (UE) in a wireless communication system, the method comprising:receiving, from the BS, a plurality of first reference signals (RSs) corresponding to rows or columns of an antenna array, and a second RS corresponding to only one antenna port pair among antenna port pairs included in the antenna array,
wherein two antenna ports for each of the antenna port pairs have different polarizations at a same position in the antenna array;
determining first precoders for each of the plurality of first RSs and linking coefficients between the first precoders;
measuring a phase difference between the two antenna ports for the only one antenna port pair based on the second RS; and
reporting, to the BS, channel state information including the first precoders, information on the linking coefficients, and information on the phase difference.

US Pat. No. 10,218,420

MILLIMETER-WAVE COMMUNICATION CONTROL METHOD AND MILLIMETER-WAVE COMMUNICATION CONTROL APPARATUS

Panasonic Corporation, O...

1. A millimeter-wave communication control method for a communication system including a microwave network and a millimeter-wave network having one or more millimeter-wave access points placed in the microwave network, the millimeter-wave communication control method comprising:receiving, by a millimeter-wave communication control apparatus belonging to the millimeter-wave network, a first signal from a microwave-communication control apparatus belonging to the microwave network, the first signal including location information of a first terminal belonging to the microwave network and a use request for the first terminal to use the millimeter-wave network;
setting, by the millimeter-wave communication control apparatus, a beam range for the first terminal and a first wireless resource that is included in one or more wireless resources of the one or more millimeter-wave access points and that is to be allocated to the first terminal, based on the location information of the first terminal; and
transmitting, by the millimeter-wave communication control apparatus, a use permission for the millimeter-wave network and first connection information for connection to a first millimeter-wave access point corresponding to the first wireless resource, to the microwave-communication control apparatus, wherein the first connection information is different from second connection information for a second terminal belonging to the millimeter-wave network,
the second terminal connects to the first millimeter-wave access point by using the second connection information, wherein:
the first connection information includes a validity period for the first terminal to use the millimeter-wave network; and
when the validity period expires, the millimeter-wave communication control apparatus issues a notification indicating that the first connection information is invalidated with respect to the first millimeter-wave access point.

US Pat. No. 10,218,417

COMMUNICATION DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD

FUJITSU LIMITED, Kawasak...

1. A communication device comprising:a memory; and
a processor connected to the memory, the processor being configured to:
compute reflected transmission weights based on timing correction coefficients to be applied to each of a plurality of antennas according to reception timings of uplink signals from a plurality of wireless terminals that receive multiplexed downlink signals transmitted from the plurality of antennas, and on respective channel estimation values between the plurality of antennas and the plurality of wireless terminals, the computed reflected transmission weights reflecting the timing correction coefficients and being computed at first frequency intervals;
compute interpolated transmission weights by interpolating between the computed reflected transmission weights at second frequency intervals that are narrower than the first frequency intervals; and
compute transmission weights to be applied to downlink signals by, based on the timing correction coefficients, correcting the interpolated transmission weights that have been interpolated such that the timing correction coefficients are reflected a second time.

US Pat. No. 10,218,414

SYSTEM AND METHOD FOR MULTIPLE POINT TRANSMISSION IN A COMMUNICATIONS SYSTEM

FUTUREWEI TECHNOLOGIES, I...

1. A method for operating a first transmission point, the method comprising:transmitting, by the first transmission point to a user equipment, information regarding a configuration indicating that a first portion of data of a bearer is transmitted from the first transmission point to the user equipment in a first packet stream, and that a second portion of the data of the bearer is transmitted from a second transmission point to the user equipment in a second packet stream concurrently with the first packet stream, and instructing the user equipment to process the first portion of data of the bearer with a first radio link control (RLC) entity at the user equipment, and process the second portion of the data of the bearer with a second RLC entity at the user equipment;
receiving, by the first transmission point, an acknowledgement of the configuration from the user equipment;
splitting, by a packet data convergence protocol (PDCP) entity at the first transmission point, the bearer into the first and second portions of data; and
sending the second portion of the data of the bearer from the PDCP entity at the first transmission point to the second RLC entity at the second transmission point without going through any PDCP entity at the second transmission point, with the PDCP entity operating at a PDCP layer and the first and second RLC entities operating at an RLC layer.

US Pat. No. 10,218,413

DEVICE DETECTION USING HARMONICS

NXP B.V., Eindhoven (NL)...

1. An apparatus comprising:a wireless-power-providing (WPP) circuit configured to provide wireless power to a WPP-compliant wireless device, the wireless-power-providing circuit including:
a transmitter circuit configured to:
generate, in a wireless-power-providing mode, a first radio frequency (RF) signal at a first frequency, the first RF signal inductively coupling the transmitter circuit to the compliant wireless device; and
generate a second RF signal at a second frequency;
a detection circuit configured to detect a presence of a WPP-noncompliant wireless device, the detection circuit including:
a receiver circuit configured to detect a third RF signal at a third frequency that is a harmonic of the second frequency; and
a control circuit configured to:
control, for the wireless-power-providing mode, the generation each of the first RF signal and the second RF signal by the transmitter circuit; and
reduce, in response to detecting the third RF signal, a signal strength for the first RF signal;
wherein the control circuit is further configured to cause the transmitter circuit to generate the second RF signal for a burst having a duration that is set based upon a setup time for generation of the third RF signal by the noncompliant wireless device and a hold time for the detection circuit to detect the third RF signal.

US Pat. No. 10,218,412

NEAR FIELD COMMUNICATION DEVICE CAPABLE OF OPERATING IN A POWERED OR UNPOWERED MODE

Capital One Services, LLC...

1. A near field communication (NFC) device, comprising:an internal power source;
a secure element;
an NFC antenna,
the NFC antenna being integrated with the secure element; and
one or more components, at least partially implemented in hardware, configured to:
determine whether the NFC device is to perform a contactless transaction in a powered mode or an unpowered mode;
selectively perform the contactless transaction in the powered mode or the unpowered mode based on determining whether the NFC device is to perform the contactless transaction in the powered mode or the unpowered mode,
the contactless transaction to be performed using power from the internal power source when the contactless transaction is performed in the powered mode, or
the contactless transaction to be performed using only power from an external NFC field when the contactless transaction is performed in the unpowered mode;
determine an amount of time to receive sufficient power from the external NFC field to power the contactless transaction;
determine to perform the contactless transaction in the power mode or the unpowered mode based on the amount of time; and
selectively load two or more applications, associated with performing the contactless transaction, onto the secure element,
the two or more applications being selectively loaded based on a remaining power level of the internal power source,
a first application of the two or more applications being selectively loaded when the remaining power level of the internal power source meets a first threshold for performing the contactless transaction using the first application, and
a second application of the two or more applications not being selectively loaded when the remaining power level of the internal power source does not meet a second threshold for performing the contactless transaction using the second application.

US Pat. No. 10,218,411

METHOD FOR PROVIDING OPERATION DATA TO A FLUID PROCESSING MEDICAL APPARATUS USING A MEDICAL ACCESSORY

Gambro Lundia AB, Lund (...

1. A method for providing operation data to a fluid processing medical apparatus, the method comprising:providing the medical apparatus comprising a readable element readable by at least one data acquisition unit;
acquiring configuration data associated to the readable element of the medical apparatus by relatively approaching a data acquisition unit of a medical accessory and the readable element of the medical apparatus;
establishing a wireless communication between the medical accessory and the medical apparatus based on the configuration data;
providing a medical component comprising a readable element different than the readable element of the medical apparatus;
acquiring operation data associated to the readable element of the medical component by relatively approaching the data acquisition unit of the medical accessory and the readable element of the medical component, wherein the medical component is configured to be operatively coupled to the medical apparatus; and
providing the operation data to the medical apparatus using the wireless communication.

US Pat. No. 10,218,410

INTERFACE CIRCUITS AND COMMUNICATION SYSTEM FOR COUPLING A HOST DEVICE TO AN ACCESSORY DEVICE AND METHOD FOR COMMUNICATION BETWEEN SUCH DEVICES

1. A host interface circuit to be implemented in a host device with a processing unit, wherein the host device is a mobile communication device and/or a sound reproducing device, the host interface circuit suitable for coupling the host device to an accessory device via a data cable, the host interface circuit comprising a power regulator and a legacy terminal and configured tooperate in a power mode of operation when connected to an accessory device being compatible with a power supply via a first line of the data cable;
to couple the power regulator to the first line when operating in the power mode;
to operate in a call mode of operation when connected to an accessory device being compatible with a power supply via the first line;
to couple the power regulator to the first line and the legacy terminal to a second line of the data cable when operating in the call mode;
to operate in a legacy mode of operation when connected to an accessory device being not compatible with a power supply via the first line; and
to couple the legacy terminal to the first line when operating in the legacy mode.

US Pat. No. 10,218,409

SYSTEMS AND METHODS FOR SMALL CELL PLACEMENT USING PNM METRICS

Cable Television Laborato...

1. A communication device in a communication network having at least one cable plant within an operational vicinity of a macro base station wirelessly transmitting a long term evolution (LTE) signal, the communication device comprising at least one processor configured to:obtain at least one proactive network maintenance (PNM) metric for a cable signal communicated over the at least one cable plant;
detect, at the communication device, a signature of the LTE signal based on the obtained PNM metric;
estimate, based on the detected LTE signature, an existing LTE signal power at a point of leakage in the at least one cable plant;
determine a carrier to noise ratio (CNR) of the at least one cable plant at the point of leakage based on a power of the cable signal and the estimated LTE signal power; and
calculate a minimum safe distance from the point of leakage in which a small cell base station operates without substantial interference from the LTE signal of the macro base station.

US Pat. No. 10,218,408

SYNCHRONIZED CPDMA (CODE PHASE DIVISION MULTIPLE ACCESS)

HIGHER GROUND LLC, Palo ...

1. A communications system comprising:a location determining module adapted to determine a location of one or more of a terminal and a geostationary communications satellite; and
an alignment module, the alignment module at least in communication with and at least using information corresponding to the determined location from the location determining module to align arrival code-phases of signals for a ground station receiver by altering a clock for a modulated signal transmitted from the terminal,
wherein the alignment module:
determines an alignment time and aligns a code-phase of a spreading code on a clock tick boundary, wherein the determining of the alignment time includes:
determining a geographic position of the terminal;
determining a position of the communications satellite;
determining a distance between the terminal and the communications satellite; and
adjusting a starting time of the spreading code by a function of a communications signal travel distance modulo predetermined time period.

US Pat. No. 10,218,407

RADIO FREQUENCY SYSTEM AND METHOD FOR WEARABLE DEVICE

INFINEON TECHNOLOGIES AG,...

1. A radio frequency (RF) system comprising:an RF integrated circuit (IC) die, the RF IC die comprising:
a first transmit circuit;
a second transmit circuit;
a first receive circuit;
a second receive circuit;
a third receive circuit;
a fourth receive circuit; and
a control circuit coupled to the first transmit circuit, the second transmit circuit, the first receive circuit, and the second receive circuit;
a first antenna coupled to the RF IC die, the first antenna being coupled to first transmit circuit and the first receive circuit using a first coupling structure, wherein the control circuit is configured to activate the first transmit circuit and deactivate the first receive circuit during a first operation mode;
a second antenna coupled to the RF IC die, the second antenna being coupled to second transmit circuit and the second receive circuit using a second coupling structure, wherein the control circuit is configured to activate the second transmit circuit and deactivate the second receive circuit during a second operation mode;
a third antenna coupled to the third receive circuit;
a fourth antenna coupled to the fourth receive circuit, wherein centers of the first antenna, the second antenna, the third antenna, and the fourth antenna are disposed at corners of a square; and
a molding material layer over the first antenna and the second antenna, the molding material layer surrounding the RF IC die.

US Pat. No. 10,218,403

SYSTEM AND METHOD FOR A MODULAR DYNAMIC WIRELESS POWER CONTROL SYSTEM IN A CONVERTIBLE INFORMATION HANDLING SYSTEM

Dell Products, LP, Round...

1. A convertible information handling system comprising:a wireless adapter for communicating on an antenna system;
a processor executing code instructions for a modular dynamic wireless power control system for detecting an active wireless link operating via a first antenna system and a first orientation mode, wherein the transmission power of the first antenna system is limited to a regulatory safety maximum depending on orientation;
the processor determining the permitted regulatory safety maximum transmission power for the first orientation mode for the information handling system;
the processor determining relative transmission activity levels for the information handling system relative to the first active wireless link and the second active wireless link, including a first wireless link data rate transmission level for the first antenna system and a second wireless link data rate transmission level for a second antenna system; and
the modular dynamic wireless power control system instructing the wireless interface adapter controller to increase transmission power to the first antenna and decrease transmission power to the second antenna relative to the regulatory safety maximum power level when the first wireless link data rate transmission level is greater than the second wireless link data rate transmission level.

US Pat. No. 10,218,399

SYSTEMS AND METHODS FOR ACTIVITY DETERMINATION BASED ON HUMAN FRAME

Zebra Technologies Corpor...

1. Apparel structured for wearing by an individual, the apparel comprising:a RF location tag supported by a first portion of the apparel associated with a first body position desirable for body motion kinetics information, the RF location tag configured to transmit blink data to at least one receiver, the blink data including first tag placement data indicative of placement of the RF location tag at the first body position, wherein the at least one receiver is configured to locate the RF location tag in a monitored area based on the blink data; and
a proximity sensor supported by a second portion of the apparel associated with a second body position desirable for proximity information indicative of proximity to an object, the proximity sensor to transmit proximity data including a second indication of the second body position.

US Pat. No. 10,218,397

SENSITIVITY RADIO FREQUENCY (RF) RECEIVER FRONT-END USING MEMS SWITCHES, RF COMMUNICATIONS DEVICE AND METHOD

LOCKHEED MARTIN CORPORATI...

1. A radio frequency (RF) front end device comprising:a plurality of micro-electro-mechanical system (MEMS) transfer switches having a plurality of parallel switch inputs and a plurality of parallel switch outputs; and
a plurality of banks of a plurality of parallel signal conditioning devices and each bank comprising a plurality of parallel paths having an input side and an output side, at least two of the banks of the plurality of signal conditioning devices couple the input side to the plurality of parallel switch outputs of a preceding MEMS transfer switch and the output side to the plurality of parallel switch inputs of a succeeding MEMS transfer switch, the MEMS transfer switches being controlled to condition a wideband RF signal through a selected set of signal conditioning devices to improve selection sensitivity of at least one frequency within a wideband,
wherein:
one or more of the MEMS transfer switches are bi-directional MEMS transfer switches; and
at least one of the parallel paths of each bank of the plurality of banks is bi-directional to selectively propagate a transmit signal in a reverse direction through the plurality of MEMS transfer switches and the plurality of banks.

US Pat. No. 10,218,396

ANTENNA DEVICE AND ELECTRONIC DEVICE INCLUDING SAME

Samsung Electronics Co., ...

1. An electronic device comprising:an external housing that comprises a first surface directed in a first direction, a second surface directed in a second direction opposite to the first direction, and a side surface configured to surround at least a part of a space between the first and second surfaces, wherein the side surface of the external housing comprises a first side surface and a second side surface perpendicular to the first side surface;
a printed circuit board (PCB) disposed within the external housing;
a communication circuit disposed on the PCB;
at least one ground member electrically coupled to the PCB;
a first antenna radiator electrically coupled to the communication circuit via a feed connection and that forms a first part of the first side surface;
a second antenna radiator electrically coupled to the communication circuit via a feed connection and that forms a second part of the first side surface and at least a part of the second side surface;
a non-conductive member disposed between the first antenna radiator and the second antenna radiator and wherein the non-conductive member electrically isolates the first antenna radiator from the second antenna radiator,
wherein the second antenna radiator comprises:
a first portion forming the second part of the first side surface and electrically coupled to the communication circuit; and
a second portion and a third portion forming the at least part of the second side surface, the second portion between the first portion and the third portion, wherein the second portion and the third portion are electrically coupled to the at least one ground member, respectively.

US Pat. No. 10,218,395

AMPLIFICATION SYSTEM FOR PUBLIC SAFETY

1. An amplification system for public safety, comprising:a radio frequency (RF) unit configured to perform, on a radio signal, gain level adjustment, frequency synthesis, and frequency conversion;
a channel unit configured to perform channel processing and spurious removal;
an amplification unit configured to perform high-power amplification;
a frequency separator configured to separate frequencies by band;
a controller configured to control and monitor an operation state of the amplification system;
a power supply configured to supply power; and
a dry contact interface connected to the controller and configured to provide state information.

US Pat. No. 10,218,394

ACTIVE DIFFERENTIAL RESISTORS WITH REDUCED NOISE

LINEAR TECHNOLOGY CORPORA...

1. An active differential resistor, comprising:an input node and an output node;
a field effect transistor (FET) having a drain coupled to the input node and a source coupled to the output node;
a first voltage source circuit coupled between the drain and the source of the FET; and
a second voltage source circuit coupled between a gate and the source of the FET, wherein the first and second voltage source circuits are configured to bias the FET into a saturation region, such that a Johnson-Nyquist noise of the active differential resistor is replaced by a shot noise.

US Pat. No. 10,218,393

PARALLEL USE OF SERIAL CONTROLS IN IMPROVED WIRELESS DEVICES AND POWER AMPLIFIER MODULES

Skyworks Solutions, Inc.,...

1. A radio frequency module comprising:a first radio frequency component;
a second radio frequency component;
a plurality of input signal pins configured to receive at least a data input signal; and
a controller including at least one output terminal, the output terminal connected to the first radio frequency component and to the second radio frequency component, the controller configured to, in a first operating mode of the radio frequency module, implement a synchronous communication protocol on the output terminal, and in a second operating mode of the radio frequency module, implement an asynchronous communication protocol on the output terminal.

US Pat. No. 10,218,392

WIDE BANDWIDTH DIGITAL PREDISTORTION SYSTEM WITH REDUCED SAMPLING RATE

Dali Systems Co. Ltd., G...

1. A method of operating a communications system, the method comprising:receiving a signal at a digital predistorter (DPD) having a DPD bandwidth;
introducing predistortion to the signal using the DPD to generate a predistorted signal;
filtering the predistorted signal using a digital filter to generate a filtered signal, wherein the predistorted signal is filtered over a filter bandwidth less than the DPD bandwidth;
amplifying the filtered signal to generate an amplified signal;
coupling a first portion of the amplified signal to provide a feedback signal; and
filtering the feedback signal using a band-pass filter to generate a filtered feedback signal, wherein the band-pass filter has a filter bandwidth less than the DPD bandwidth.

US Pat. No. 10,218,391

SYSTEMS AND METHODS PROVIDING A LOW-POWER MODE FOR SERIAL LINKS

QUALCOMM Incorporated, S...

1. A system comprising:a transmitter coupled to a link;
a receiver coupled to the link and configured to receive signals over the link from the transmitter;
a transmit control module configured to cause the transmitter to enter and exit a low-power mode; and
a clock module coupled to the transmitter and configured to provide a clock signal to the transmitter, wherein the clock module is further configured to provide the clock signal as a divided clock signal to the transmitter when the transmitter is in the low-power mode, further wherein the divided clock signal has a same phase as the clock signal before entry into the low-power mode, and further wherein the receiver is configured to halt performing adaptive equalization and variable gain control in response to the transmitter entering the low-power mode.

US Pat. No. 10,218,389

TRANSMITTER

HUAWEI TECHNOLOGIES CO., ...

1. A transmitter, comprising: a dual-band input circuit, a modulo circuit, a signal decomposition circuit, a modulation circuit, and a dual-band power amplifier, whereinthe dual-band input circuit comprises a first band input end, a second band input end, and two digital pre-distortion (DPD) components connected to the first band input end and the second band input end, and is configured to output a first baseband signal input by the first band input end and a second baseband signal input by the second band input end, wherein the first baseband signal and the second baseband signal are processed by the DPD components before being output;
the modulo circuit is configured to: perform modulo processing on the first baseband signal and the second baseband signal that are input, and output a corresponding first baseband signal modulus value and a corresponding second baseband signal modulus value;
the signal decomposition circuit comprises a memory storing a lookup table, and a multiplier, and is configured to: receive the first baseband signal and the second baseband signal that are input by the DPD components, and the first baseband signal modulus value and the second baseband signal modulus value that are from the modulo circuit, and separately perform signal decomposition processing based on the lookup table and the multiplier to obtain multiple decomposed signals; and
the modulation circuit is connected to the signal decomposition circuit, and is configured to receive the multiple decomposed signals output by the signal decomposition circuit, to perform combination processing on the multiple decomposed signals to obtain two corresponding processed signals, to modulate the two processed signals to corresponding working frequencies, and to output the two processed signals to the dual-band power amplifier.

US Pat. No. 10,218,388

TECHNIQUES FOR LOW COMPLEXITY SOFT DECODER FOR TURBO PRODUCT CODES

SK Hynix Inc., Gyeonggi-...

1. A method for decoding, comprising:obtaining a first message comprising a plurality of information bits and a plurality of parity bits from a memory via a channel;
decoding, using a Chase decoder the first message using an iterative decoding algorithm to generate a first bit sequence;
identifying locations of bits flipped by the Chase decoder based on the first bit sequence and the first message, the locations of the bits flipped corresponding to a first bit flip pattern;
generating a miscorrection metric based on reliability values corresponding to bits in the first message at the locations of the bits flipped; and
performing a miscorrection avoidance thresholding (MAT) decoding procedure by:
determining whether a miscorrection happened in an iteration of the iterative decoding algorithm by comparing the miscorrection metric with an adaptive threshold, wherein the adaptive threshold has a value that changes and is defined based on a counter of the iteration, and wherein the value increases with an increase to the counter;
upon determining that the miscorrection did happen based at least in part on the comparing of the miscorrection metric with the adaptive threshold:
declaring a decoded pattern to constitute an error
performing an additional decoding iteration by the Chase decoder of the first message based on a second bit flip pattern; and
increasing the value of the adaptive threshold; and
upon determining that the miscorrection did not happen, outputting the first bit sequence as a decoded message without repeating the decoding of the first message based on the second bit flip pattern.

US Pat. No. 10,218,382

DECOMPRESSION USING CASCADED HISTORY WINDOWS

Amazon Technologies, Inc....

1. An apparatus comprising:a decompression engine configured to decompress a compressed data stream, the compressed data stream comprising code words with references to a history of an uncompressed data stream used to generate the compressed data stream;
a first-level history buffer in communication with the decompression engine and configured to store decompressed data from the decompression engine in a first-in first-out order for storage in the first-level history buffer; and
a second-level history buffer in communication with the decompression engine and the first-level history buffer, the second-level history buffer configured to store decompressed data from the first-level history buffer in a first-in first-out order for storage in the second-level history buffer; and
wherein the decompression engine is configured to decompress the compressed data associated with a plurality of code words of the compressed data stream using decompressed data received by concurrently reading from the first-level history buffer and the second-level history buffer using a random access order.

US Pat. No. 10,218,380

HIGH SPEED DATA WEIGHTED AVERAGING ARCHITECTURE

STMicroelectronics Intern...

1. A circuit for generating a data weighted averaging signal from a thermometric code signal, comprising:a crossbar switch matrix having an input configured to receive the thermometric code signal and an output configured to output the data weighted averaging signal, wherein switching between the input and output by the crossbar switch matrix is controlled by a crossbar selection signal, and
a data weighted averaging control circuit configured to generate the crossbar selection signal, comprising:
a first logic circuit configured to determine from bits of the data weighted averaging signal a bit location where an ending logic transition occurs;
a load circuit configured to selectively load the bit location as the crossbar selection signal in response to assertion of a load signal; and
a load control circuit configured to inhibit assertion of the load signal if all bits of the thermometric code signal are either logic 0 or logic 1.

US Pat. No. 10,218,378

ANALOG CONVERTER FOR MOTOR ANGLE SENSOR

Robert Bosch GmbH, Stutt...

1. An analog converter for a motor angle sensor, comprising:at least two Gilbert Cells configured to receive a signal from a motor angle sensor,
an intermediate frequency signal source configured to provide an intermediate frequency signal to the at least two Gilbert Cells, and
a low-pass filter configured to receive an output from the at least two Gilbert Cells and output a converted signal to an electronic controller.

US Pat. No. 10,218,374

FREQUENCY MANAGEMENT FOR INTERFERENCE REDUCTION OF A/D CONVERTERS POWERED BY SWITCHING POWER CONVERTERS

TEXAS INSTRUMENTS INCORPO...

1. A system, comprising:a frequency generator configured to generate a second clock signal having a second frequency using a first clock signal having a first frequency, the second frequency offset from the first frequency and each of a plurality of harmonic frequencies of the second frequency offset from a harmonic frequency of the first frequency;
a power converter configured to produce a power signal that at least partially corresponds to the second frequency; and
an analog-to-digital converter (ADC) configured to sample and convert analog voltages at the first frequency, the ADC powered by the power signal;
wherein the system includes a multi-die package, and wherein the frequency generator is formed on a first die of the package, the ADC is formed on a second die of the package, and the power converter is distributed among the first die and a third die, the power converter comprising a transformer to achieve electrical isolation between the first die and the third die.

US Pat. No. 10,218,372

METHOD TO DETECT BLOCKER SIGNALS IN INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS

XILINX, INC., San Jose, ...

1. A time-skew adjustment circuit, comprising:an input to receive a series of samples of an input signal from a plurality of channels of an interleaved analog-to-digital converter (ADC);
a first subtractor to calculate distances between consecutive samples in the received series of samples;
a plurality of averaging circuits to calculate a plurality of first average distances, wherein each of the first average distances corresponds to an average of the distance between consecutive samples from a respective pair of channels of the interleaved ADC;
time-skew detection circuitry to calculate respective time skews between each of the pairs of channels by comparing each of the first average distances with an average of the distances between consecutive samples from the plurality of channels; and
divergence control circuitry to determine an accuracy of the time skews based at least in part on the first average distances and a Nyquist zone associated with the input signal.

US Pat. No. 10,218,371

COST EFFECTIVE DAC LINEARIZATION SYSTEM

Iowa State University Res...

1. An apparatus comprising:a digital-to-analog converter (DAC) configured to sequentially provide a first DAC output signal and a second DAC output signal based on a digital input signal, wherein both the first DAC output signal and the second DAC output signal include DAC integral nonlinearity (INL) from the DAC;
a summing buffer structure configured to sequentially provide a first summing output signal and a second summing output signal, wherein:
the first summing output signal is based on the first DAC output signal and a first offset signal, and the second summing output signal is based on the second DAC output signal and a second offset signal; and
the first offset signal is different from the second offset signal;
an analog-to-digital converter (ADC) configured to sequentially provide a first ADC output signal based on the first summing output signal and a second ADC output signal based on the second summing output signal;
a calculation system configured to calculate the DAC INL based on the first ADC output signal and the second ADC output signal;
an error look-up table configured to provide a correction signal mapping to the calculated DAC INL; and
an adder configured to provide a calibrated digital input signal to the DAC by calibrating the digital input signal with the correction signal, wherein the calibrated digital input signal ensures the DAC to generate an updated output signal that includes less DAC INL than the first DAC output signal and the second DAC output signal.

US Pat. No. 10,218,368

SYSTEM AND METHOD FOR IN-SITU OPTIMIZATION OF MICROWAVE FIELD HOMOGENEITY IN AN ATOMIC CLOCK

Honeywell International I...

1. A method of operating a cold atom clock to maintain a highly homogeneous microwave field, the method comprising:driving a subset of microwave feed lines to excite a microwave field in a resonator, while a power and a phase of at least one microwave feed line in the subset is held constant, and while the power or the phase of at least one other microwave feed line in the subset is changed;
measuring a strength of the atomic transition excited by the microwave field in the resonator while driving the subset of the microwave feed lines;
extracting a relative power and a relative phase between or among the subset of microwave feed lines by processing the strength of the atomic transitions excited by the microwave field measured in at least one auxiliary-measurement cycle; and
determining if an adjustment to one or more of the microwave feed lines in the subset of microwave feed lines is needed to improve the homogeneity of the microwave field phase and amplitude based on the extracting.

US Pat. No. 10,218,367

FREQUENCY SYNTHESIZING DEVICE AND AUTOMATIC CALIBRATION METHOD THEREOF

Raydium Semiconductor Cor...

1. A frequency synthesizing device, comprising:a voltage-controlled oscillator receiving an adjusting signal and generating an output signal according to the adjusting signal;
a feedback frequency divider having a plurality of divisor values, the feedback frequency divider receiving the output signal and generating a feedback signal after performing frequency dividing; and
an automatic frequency calibration circuit comprising:
a first frequency divider receiving a reference frequency and generating a frequency dividing reference frequency;
a second frequency divider receiving the feedback signal and generating a frequency dividing feedback signal;
a comparator receiving and comparing outputs from the first frequency divider and the second frequency divider in a predetermined period to generate a comparing result; and
a state machine outputting the adjusting signal according to the comparing result in a calibration mode;
wherein the calibration mode comprises a coarse adjusting mode; the state machine sets the feedback frequency divider to generate the feedback signal by using a first divisor value selected from the plurality of divisor values in the coarse adjusting mode; when the comparing result shows a phase of the frequency dividing feedback signal falling behind a phase of the frequency dividing reference frequency, the state machine sets the feedback frequency divider to generate the feedback signal by using a second divisor value selected from the plurality of divisor values different from the first divisor value;
wherein the calibration mode further comprises a fine adjusting mode; in the fine adjusting mode, a divisor value of the second frequency divider is set to be equal to the divisor value of the first frequency divider; when the comparing result shows the phase of the frequency dividing feedback signal falling behind the phase of the frequency dividing reference frequency, the state machine outputs the adjusting signal to change an input current and a working band of the voltage-controlled oscillator; when the comparing result shows the phase of the frequency dividing feedback signal leading the phase of the frequency dividing reference frequency, the fine adjusting mode is finished.

US Pat. No. 10,218,366

PHASE LOCKED LOOP CALIBRATION FOR SYNCHRONIZING NON-CONSTANT FREQUENCY SWITCHING REGULATORS

Linear Technology Holding...

1. A calibration circuit for synchronizing a switching regulator, the circuit comprising:a phase locked loop circuit configured to generate one or more control signals based on an output of the switching regulator;
a digital calibration circuit configured to provide a digital output signal comprising a plurality of bits based on the one or more control signals from the phase locked loop circuit; and
a timer configured to provide, to the switching regulator, one or more switching pulses having a width that is set based on a value represented by the plurality of bits, wherein the phase locked loop circuit is configured to adjust the one or more control signals based on a reference clock signal to synchronize a feedback signal of the switching regulator with the reference clock signal.

US Pat. No. 10,218,364

TIME TO DIGITAL CONVERTER, PHASE DIFFERENCE PULSE GENERATOR, RADIO COMMUNICATION DEVICE, AND RADIO COMMUNICATION METHOD

KABUSHIKI KAISHA TOSHIBA,...

1. A time to digital converter comprising:a counter to measure the number of cycles of a first signal;
a first phase difference detector to generate a phase difference signal having a pulse width corresponding to a phase difference between the first signal and a second signal having a frequency twice or more lower than the frequency of the first signal;
a first capacitor to be charged with an electric charge corresponding to the pulse width of the phase difference signal;
a second capacitor including capacitance N times the capacitance of the first capacitor, the N being a real number larger than 1;
a comparator to compare a charge voltage of the first capacitor and a charge voltage of the second capacitor;
a first charge controller to continue to charge the second capacitor until the comparator detects that the charge voltage of the second capacitor has reached the charge voltage of the first capacitor or more; and
the first phase difference detector to detect the phase difference between the first signal and the second signal, based on a value obtained by dividing a count value of the counter during a period of the charge to the second capacitor by the N.

US Pat. No. 10,218,363

BACKGROUND CALIBRATION FOR REAL-TIME CLOCK SYSTEMS

Verily Life Sciences LLC,...

1. A circuit, comprising:a reference clock terminal configured to receive a signal indicative of a reference clock;
a plurality of low power oscillators (LPOs), wherein each given LPO is operable in one of three states including: a sleep state in which the given LPO is powered off, a calibration state in which the given LPO undergoes calibration, and an active state in which the given LPO is configured to provide a real-time clock based on the reference clock; and
a controller coupled to the plurality of LPOs to control operations of the LPOs such that, at any time, at most a single LPO is in the active state.

US Pat. No. 10,218,362

METHOD AND APPARATUS FOR SUBSTATION FINGERPRINTING

Enphase Energy, Inc., Pe...

1. A method for mapping distributed generators (DGs) to corresponding power grid feeder lines, comprising:obtaining, by a controller communicatively coupled to a plurality of distributed generators (DGs), grid data pertaining to a power grid that comprises a plurality of feeder lines coupled to the plurality of DGs;
obtaining, by the controller, for each distributed generator (DG) of the plurality of DGs, DG data generated by and pertaining to the DG; and
determining, based on the grid data and the DG data, a mapping that identifies to which feeder line of the plurality of feeder lines each of the DGs of the plurality of DGs is coupled.

US Pat. No. 10,218,361

LOW-NOISE OSCILLATOR AMPLITUDE REGULATOR

Telefonaktiebolaget LM Er...

1. A frequency generation circuit comprising:an oscillator comprising an oscillator output, a first control input, and a second control input;
a detector configured to detect an amplitude of the oscillator output;
a first feedback path operatively connecting the detector to the first control input, the first feedback path configured to control the amplitude of the oscillator output responsive to the detected amplitude by continuously applying a first control signal to the first control input; and
a second feedback path operatively connecting the detector to the second control input, the second feedback path configured to control one or more amplitude regulating parameters of the oscillator responsive to the detected amplitude by applying a second control signal to the second control input;
wherein the second feedback path comprises a control circuit; and
wherein the control circuit is configured to prevent changes to the one or more amplitude regulating parameters when the oscillator is being used for wireless communications.

US Pat. No. 10,218,360

DYNAMIC CLOCK-DATA PHASE ALIGNMENT IN A SOURCE SYNCHRONOUS INTERFACE CIRCUIT

Altera Corporation, San ...

1. Clock-data phase alignment circuitry, comprising:clock phase adjustment circuitry that receives a differential clock with first and second clock signals that are complementary to each other;
a first clock distribution network that receives the first clock signal from the clock phase adjustment circuitry and propagates the first clock signal through a first branch that has a first delay and includes at least one first clock buffer to provide a delayed first clock signal and through a second branch that is parallel to the first branch, has a second delay that is substantially equal to the first delay, and provides a delayed second clock signal;
a first storage circuit that receives the delayed first clock signal and a first data signal and stores the first data signal based on the delayed first clock signal;
a second storage circuit that receives the delayed second clock signal and a second data signal and stores the second data signal based on the delayed second clock signal; and
a second clock distribution network coupled between the first clock distribution network and the clock phase adjustment circuitry, wherein the second clock distribution network receives the delayed first clock signal and propagates the delayed first clock signal through at least one second clock buffer to provide a further delayed first clock signal to the clock phase adjustment circuitry, wherein the first clock distribution network and the second clock distribution network reside externally and separately from the clock phase adjustment circuitry.

US Pat. No. 10,218,356

SEMICONDUCTOR DEVICE INCLUDING ELECTROSTATIC PROTECTION CIRCUIT

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a first power source pad supplied with a first power source voltage in a normal operation;
a first power source line connected to the first power source pad;
a first ground line;
an output circuit having an output end connected to a signal line, and being connected between the first power source line and the first ground line;
a second power source pad supplied with a second power source voltage in the normal operation;
a second power source line connected to the second power source pad;
a second ground line;
an input circuit having an input end connected to the signal line, and being coupled between the second power source line and the second ground line;
a first main protection unit configured to be connected between the first power source pad and the first ground line;
a second main protection unit configured to be connected between the first ground line and the second ground line;
a third main protection unit configured to be connected between the second power source pad and the second ground line;
a sub protection circuit unit having a first PMOS transistor, the first PMOS transistor having a gate and a back gate connected to the second power source line and a source-drain path connected between the signal line and the second ground line; and
at least one of a first resistor and a second resistor, the first resistor connected between the back gate of the first PMOS transistor and the second power source line, and the second resistor connected in series with the first PMOS transistor between the signal line and the second ground line,
wherein in the normal operation, a voltage value of the first power source voltage is equal to or lower than a voltage value of the second power source voltage and the potential of the back gate of the first PMOS transistor is higher than the potential of the source of the first PMOS transistor.

US Pat. No. 10,218,355

POWER SUPPLY CIRCUIT AND CONTROL METHOD THEREOF

Renesas Electronics Corpo...

1. A power supply circuit comprising:N (N?3) voltage sources;
first and second voltage control circuits that boost respective input voltages; and
a voltage source connection switch that connects each voltage source to either the first voltage control circuit or the second voltage control circuit based on a voltage of the voltage source,
wherein
the first voltage control circuit boosts an input voltage according to a duty ratio of a first clock signal supplied to the first voltage control circuit, and
the second voltage control circuit boosts an input voltage according to a duty ratio of a second clock signal supplied to the second voltage control circuit.

US Pat. No. 10,218,352

SEMICONDUCTOR INTEGRATED CIRCUIT

Kabushiki Kaisha Toshiba,...

1. A semiconductor integrated circuit, comprisingan output circuit comprising a plurality of switching elements and driven by a power voltage applied across a first power node and a second power node; and
a control circuit driven by the power voltage applied across the first power node and the second power node, the control circuit configured to control the output circuit to output a digital signal at a pad terminal, a logic value of the digital signal being set according to a signal supplied by a core circuit connected to the output circuit,
wherein the digital signal causes a voltage at the first power node to be a high level and causes a voltage at the second power node to be a low level when a predetermined power voltage, which is higher than a withstanding voltage of any one of the plurality of switching elements in the output circuit, is applied across the first power node and the second power node,
wherein the control circuit is configured to control a voltage across terminals of each switching element in the plurality of switching elements to be less than the withstanding voltage of each switching element and to prevent a current flowing from the pad terminal to the output circuit when the first power node is in a high impedance state, and
wherein the control circuit includes:
a voltage dividing circuit configured to divide a voltage applied between a voltage input node and the second power node, and
a switcher configured to either electrically connect the first power node to the voltage input node or electrically connect the pad terminal to the voltage input node.

US Pat. No. 10,218,348

CONTROL CIRCUIT

Mitsubishi Electric Corpo...

1. A control circuit comprising:an inverter circuit comprising a totem-pole configuration comprising a high-side MOSFET and a low-side MOSFET connected to form a totem-pole;
a first gate driver configured to switch the low-side MOSFET;
a second gate driver configured to switch the high-side MOSFET;
a bootstrap circuit configured to supply a voltage to the second gate driver; and
a detection section configured to issue an anomaly signal when a current larger than a predetermined value flows in the inverter circuit,
wherein in response to issuing of the anomaly signal, the first gate driver turns off the low-side MOSFET, and the second gate driver turns off the high-side MOSFET, and
after that, in a state in which a freewheeling current is flowing through a body diode of the low-side MOSFET, the first gate driver turns on the low-side MOSFET to execute protective operation for preventing a bootstrap capacitor of the bootstrap circuit from being overcharged.

US Pat. No. 10,218,347

HIGH FREQUENCY SWITCH

Samsung Electro-Mechanics...

1. A high frequency switch, comprising:a first signal circuit portion configured to transfer a high frequency signal from a first port to a common port;
a second signal circuit portion configured to transfer the high frequency signal from the common port to a second port; and
an electrostatic discharge (ESD) protecting unit comprising a protective transistor positioned between the common port and a ground and a diode element positioned between a control terminal of the protective transistor and the first port.

US Pat. No. 10,218,345

HIGH-SIDE GATE DRIVE CIRCUIT, SEMICONDUCTOR MODULE, AND THREE-PHASE INVERTER SYSTEM

Mitsubishi Electric Corpo...

1. A high-side gate drive circuit for driving a high-side switching element, the high-side gate drive circuit comprising:pulse generating circuits configured to generate a first pulse synchronized with an input signal; and
level shift circuits configured to shift a level of a reference voltage for the first pulse to a power supply voltage of the high-side switching element,
wherein the level shift circuits include MOSFETs to be driven by the first pulse,
the high-side gate drive circuit comprising:
a mask signal generating circuit configured to generate a mask signal that becomes a high level in a period in which source potential of the MOSFETs becomes a high level; and
reshot circuits configured, when the first pulse is input into the level shift circuits during a mask period that is a period in which the mask signal is a high level, to input a second pulse into the level shift circuits after the mask period.

US Pat. No. 10,218,344

VOLTAGE CONVERSION CIRCUIT AND CONTROL CIRCUIT THEREOF

Excelliance MOS Corporati...

1. A control circuit, configured to control a driver switch, wherein two ends of the driver switch respectively receive an input voltage and an output voltage, and the control circuit comprises:a voltage selection circuit, configured to receive the input voltage and the output voltage, and select a smaller voltage value as a selected voltage from the input voltage and the output voltage;
a buffer circuit, coupled to the voltage selection circuit, and configured to receive the selected voltage and provide the selected voltage as a reference voltage; and
a pull-down switch, wherein the pull-down switch is connected in series between a control end of the driver switch and the reference voltage, and a control end of the pull-down switch receives an enable signal, so that the pull-down switch is switched on or switched off based on the enable signal, wherein
the pull-down switch is switched on based on the enable signal, to pull down a voltage at the control end of the driver switch to the reference voltage and switch off the driver switch.

US Pat. No. 10,218,343

DUTY CYCLE CORRECTION SCHEME

SanDisk Technologies LLC,...

1. A circuit comprising:control circuitry configured to determine a corrective direction to change a duty cycle of a sample clock signal to correct for a duty cycle error of the sample clock signal;
delay circuitry configured to delay an input clock signal to generate a plurality of relative delay signals comprising different phases relative to each other;
selection circuitry configured to select a leading phase signal and a lagging phase signal from among the plurality of relative delay signals according to the corrective direction; and
output circuitry configured to generate an output clock signal in response to a combination of the leading phase signal and the lagging phase signal, the output clock signal comprising a duty cycle corresponding to the corrective direction.

US Pat. No. 10,218,340

ADJUSTABLE DELAY CIRCUIT FOR OPTIMIZING TIMING MARGIN

Micron Technology, Inc., ...

1. An apparatus, comprising:a signal line supplied with a signal;
an output circuit; and
a plurality of delay circuits each including an input node, an output node and a same number of transistors between the input node and the output node, and wherein a selected one of the plurality of delay circuits being connected at its input node to the signal line and at its output node to the output circuit with any of the input and output nodes of any one of the rest of the plurality of delay circuits being disconnected from any one of the signal line and the output circuit.

US Pat. No. 10,218,339

VOLTAGE MONITOR WITH A TRMIMMING CIRCUIT AND METHOD THEREFORE

NXP USA, Inc., Austin, T...

1. An integrated circuit device comprising:a substrate;
a voltage monitor circuit formed on the substrate;
a trimming circuit formed on the substrate including:
a successive approximation register circuit having an input coupled to an output of the voltage monitor circuit;
a beta multiplier circuit having:
an input coupled to an output of the successive approximation register circuit,
an output coupled to a first input of the voltage monitor circuit, and
a variable resistance circuit, wherein a resistance value of the variable resistance circuit is controlled by the output of the successive approximation register.

US Pat. No. 10,218,335

DUPLEXER

TAIYO YUDEN CO., LTD., T...

3. A duplexer comprising:a first filter that is connected between a common terminal and a first terminal, and includes a first series resonator and a first parallel resonator;
a second filter that has a passband higher than a passband of the first filter, is connected between the common terminal and a second terminal, and includes a second series resonator and a second parallel resonator;
a first chip on which the first series resonator and the second parallel resonator are located;
a second chip that differs from the first chip, and on which the first parallel resonator and the second series resonator are located, wherein
when a temperature coefficient of an antiresonant frequency of the first series resonator is represented by GA, a temperature coefficient of a resonant frequency of the first parallel resonator is represented by HGA, a temperature coefficient of an antiresonant frequency of the second series resonator is represented by HGB, and a temperature coefficient of a resonant frequency of the second parallel resonator is represented by GB, a magnitude relationship among GA, GB, HGA, and HGB is any one of GB

US Pat. No. 10,218,334

ACOUSTIC WAVE DEVICE

TAIYO YUDEN CO., LTD., T...

1. An acoustic wave device comprising:a substrate;
a plurality of acoustic wave resonators that are formed on an upper surface of the substrate;
a first wiring line that is formed on the upper surface of the substrate and is electrically coupled to at least one of the plurality of acoustic wave resonators; and
one or more second wiring lines that are electrically coupled to the first wiring line and connects regions located on the upper surface of the substrate, at least a part of the one or more second wiring lines being formed immediately above one or more of the plurality of acoustic wave resonators across an air gap,
wherein the one or more second wiring lines are not supported by any other substrate other than the substrate, and
each of the one or more of the plurality of acoustic wave resonators includes a first region overlapping with the one or more second wiring lines in a plan view and a second region not overlapping with the one or more second wiring lines in the plan view.

US Pat. No. 10,218,331

QUADRATURE HYBRID WITH MULTI-LAYER STRUCTURE

Telefonaktiebolaget LM Er...

1. A quadrature hybrid having a first, second, third and fourth ports, the quadrature hybrid comprising: a substrate having a plurality of dielectric layers; a first, second and third capacitors, each capacitor having a first predetermined number of layers each being arranged on a different one of the plurality of dielectric layers; and a first, second, third and fourth inductors, each inductor having a second predetermined number of layers each being arranged on a different one of the plurality of dielectric layers, wherein a first terminal lead of the first inductor and a first terminal lead of the first capacitor are connected to the first port, a first terminal lead of the second inductor and a second terminal lead of the first capacitor are connected to the second port, a first terminal lead of the third inductor and a second terminal lead of the third capacitor are connected to the third port, a first terminal lead of the fourth inductor and a first terminal lead of the third capacitor are connected to the fourth port, a second terminal lead of the first inductor and a second terminal lead of the fourth inductor are connected to a first terminal lead of the second capacitor, and a second terminal lead of the second inductor and a second terminal lead of the third inductor are connected to a second terminal lead of the second capacitor, wherein the first and second terminal leads of each inductor are arranged in a first direction, and the first and second terminal leads of each capacitor are arranged in a second direction orthogonal to the first direction.

US Pat. No. 10,218,326

SOURCE FOLLOWER BASED ENVELOPE TRACKING FOR POWER AMPLIFIER BIASING

QUALCOMM Incorporated, S...

1. A power amplifier bias circuit with embedded envelope detection comprising:an envelope detector circuit configured to generate a baseband envelope tracking bias signal to bias a power amplifier, the envelope detector circuit including:
a first source/emitter follower transistor,
a first current driver coupled to an output node of the first source/emitter follower transistor, and
a filter coupled to the output node of the first source/emitter follower transistor; and
a power amplifier bias circuit stage coupled to the envelope detector circuit, the power amplifier bias circuit stage including:
at least one replica transistor of the power amplifier,
an envelope detector replica transistor, and
a replica of the first current driver of the envelope detector circuit.

US Pat. No. 10,218,324

DIFFERENTIAL INPUT STAGE WITH WIDE INPUT SIGNAL RANGE AND STABLE TRANSCONDUCTANCE

TEXAS INSTRUMENTS INCORPO...

1. A system, comprising:a differential input transistor pair (DITP) comprising first and second transistors;
a first feedback loop coupled to the first transistor; and
a second feedback loop coupled to the second transistor,
wherein, when a differential voltage applied to the differential input transistor pair is within a first range, the first and second feedback loops control a tail current supplied to the DITP, the tail current at least partially determines a transconductance of the DITP,
wherein, when the differential voltage is within a second range, the transconductance of the DITP is at least partially determined by a first resistor in the first feedback loop or by a second resistor in the second feedback loop.

US Pat. No. 10,218,323

DIFFERENTIAL AMPLIFIER, RECEIVER, AND CIRCUIT

SONY CORPORATION, Tokyo ...

1. A differential amplifier, comprising:a differential amplification circuit; and
an output circuit configured to amplify a differential output from the differential amplification circuit and output the amplified differential output, wherein
the differential amplification circuit includes a first conductive type first differential pair configured to supply output currents according to a positive phase input signal and a reverse phase input signal to the output circuit, a second conductive type second differential pair configured to supply output currents according to a positive phase input signal and a reverse phase input signal to the output circuit, a detector configured to detect an operation state of the first conductive type first differential pair, and an alternative current supplying unit configured to supply an alternative current for the output current of the second conductive type second differential pair which has been turned off to the output circuit.

US Pat. No. 10,218,320

VACUUM TUBE AUDIO AMPLIFIER

ECHOWELL ELECTRONICS CO.,...

1. A vacuum tube audio amplifier for providing an output signal based on an input signal, the vacuum tube audio amplifier comprising an audio pre-amplifying portion and an audio output transforming portion, the audio pre-amplifying portion amplifying the input signal and transmitting the input signal to the audio output transforming portion, the audio output transforming portion providing the output signal to a loudspeaker, the vacuum tube audio amplifier being characterized in that:the audio output transforming portion includes an audio output transformer comprising a plurality of stacked E-shaped silicon steel sheets and a plurality of stacked I-shaped silicon steel sheets, wherein the stacked E-shaped silicon steel sheets and the stacked I-shaped silicon steel sheets have a same height which is smaller than or equal to 48 mm, and the audio pre-amplifying portion includes an equalizer for enhanced sound quality, which corrects high-frequency and low-frequency responses of the input signal; wherein the equalizer for enhanced sound quality is a CR-type equalizer and includes an input and an output, wherein the input is connected to a first terminal of a first resistor and a first terminal of a first capacitor; a second terminal of the first resistor is connected to a first terminal of a second capacitor and a first terminal of a third capacitor; a first variable resistor having a first center tap is connected between a second terminal of the first capacitor and a second terminal of the second capacitor, the first center tap being the output a second variable resistor is connected between the second terminal of the second capacitor and a second terminal of the third capacitor, the second variable resistor having a second center tap connected to the second terminal of the second capacitor; the second terminal of the third capacitor is connected to a first terminal of a second resistor; and a second terminal of the second resistor is connected to a signal ground terminal of the audio output transforming portion.

US Pat. No. 10,218,318

AMPLIFIER WITH DIGITAL LINEARIZATION AND MULTIPLE OUTPUT STAGES

ARRIS Enterprises LLC, S...

1. A node for a CATV distribution system, the node providing a common signal to a plurality of amplifiers, each amplifier amplifying the common signal and delivering the amplified signal to a respective set of one or more subscribers, the node comprising:a first controller that controls pre-distortion of the common signal so as to cancel at least a portion of a distortion caused by each of the plurality of amplifiers; and
a plurality of second controllers, each second controller associated with a respective one of the plurality of amplifiers and modifying at least one of a gain, a frequency response, and a balance of its respective amplifier in response to a feedback signal of the output of the respectively associated one of the plurality of amplifiers;
where at least one of the first controller and the plurality of second controllers store predetermined performance characteristics of the plurality of amplifiers,
where the respective modifications by the respective controllers equalize the distortion among the plurality of amplifiers; and
at least one temperature sensor and where at least one of the first controller and the plurality of second controllers use the output of the at least one temperature sensor and the stored performance characteristics to equalize the distortion among the plurality of amplifiers.

US Pat. No. 10,218,317

HIGH-FREQUENCY AMPLIFIER MODULE

MURATA MANUFACTURING CO.,...

1. A high-frequency amplifier module comprising:a semiconductor substrate including a plurality of high-frequency amplifying transistors, the plurality of high-frequency amplifying transistors amplifying a single high frequency signal; and
an insulating substrate having a front surface and a back surface, the front surface facing the back surface,
wherein the semiconductor substrate includes a plurality of emitter electrodes, each of the plurality of emitter electrodes being coupled to an emitter of a corresponding one of the plurality of high-frequency amplifying transistors, and
wherein the insulating substrate includes
a common ground electrode provided on or near the front surface and joined to the plurality of emitter electrodes,
a ground terminal electrode provided on the back surface, and
at least one thickness-direction coupling electrode coupling the common ground electrode to the ground terminal electrode.

US Pat. No. 10,218,316

FLIP CHIP CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A flip chip circuit comprising:a semiconductor substrate;
a power amplifier provided on the semiconductor substrate;
a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry;
wherein at least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate;
a temperature sensor having a temperature sensitive component provided proximal to the power amplifier, and
a controller, configured to control the power amplifier based on a temperature determined by the temperature sensor.

US Pat. No. 10,218,312

DYNAMIC VOLUME MANAGEMENT IN AUDIO AMPLIFIERS

QUALCOMM Incorporated, S...

1. A method for overload protection, comprising:detecting an overload condition of an amplifier based on a signal at a node of the amplifier; and
controlling a parameter of an input signal of the amplifier such that the parameter of the input signal is maintained at or below a first threshold until the overload condition is no longer detected, wherein controlling the parameter comprises decreasing the parameter of the input signal while the amplifier is in the overload condition, wherein the parameter of the input signal comprises a voltage level of the input signal or a duty cycle of the input signal.

US Pat. No. 10,218,309

FAST START-UP SINGLE PIN CRYSTAL OSCILLATION APPARATUS AND OPERATION METHOD THEREOF

TRITAN TECHNOLOGY INC., ...

1. A fast start-up single pin crystal oscillation apparatus, comprising: a comparator, an envelope detector, a trigger, a crystal, a finite state machine, an amplifier gain module, a load capacitor module and a bias resistor; wherein:the comparator having a positive input end, a negative input end and an output end, with the positive input end for receiving a detection voltage signal, the negative input end for receiving a reference voltage signal, the comparator comparing the detection voltage signal and the reference voltage signal and the output end outputting a comparison voltage signal;
the envelope detector being coupled to the comparator, for generating the detection voltage signal;
the trigger being coupled to the envelope detector, for generating a clock signal;
the crystal being coupled to the trigger, for generating an oscillation signal with an oscillation frequency;
the finite state machine being coupled to the trigger, the comparator, the load capacitor module, and the amplifier gain module, for receiving the clock signal and the comparison voltage signal and outputting a load capacitor calibration signal and a gain amplifier calibration signal;
the load capacitor module being coupled to the amplifier gain module; and
the bias resistor being coupled in parallel to the crystal and the load capacitor module.

US Pat. No. 10,218,308

PHOTOVOLTAIC JUNCTION BOX PROVIDING QUICK HEAT DISSIPATION

Tyco Electronics Holdings...

1. A photovoltaic junction box, comprising:a box body is a single integrally-molded part having a housing portion defining a receiving chamber and a packaging portion having a first packaging portion located inside the receiving chamber and a second packaging portion located outside the receiving chamber;
a plurality of conductive terminals positioned along the box body; and
at least one diode chip disposed in a portion of the box body outside of the receiving chamber.

US Pat. No. 10,218,303

TEMPERATURE CALCULATION SYSTEM FOR A MOTOR USING A THERMAL EQUIVALENT CIRCUIT

Hyundai Motor Company, S...

1. A temperature calculation system for a motor using a thermal equivalent circuit, wherein a yoke is disposed to be fixed onto an inner circumferential surface of a housing of the motor, a coolant chamber in which a coolant flows is formed in a circumferential direction in the housing, and the thermal equivalent circuit, which includes thermal resistance coefficients and temperatures, is used, andan endothermic amount of the coolant flowing in the coolant chamber of the housing is calculated by using an average temperature of the housing and a preset equation,
wherein a temperature of an inner one side of the housing is calculated by using a temperature of an outer circumferential surface of the yoke, a contact thermal resistance between the housing and the yoke, and a conduction resistance of the housing, and by using a temperature of air outside the housing, a convection resistance, and the conduction resistance of the housing,
wherein the average temperature of the housing is calculated by using the temperature of the inner one side of the housing and a compensation resistance,
wherein the preset equation is configured to calculate the endothermic amount by using a mass flow rate of the coolant flowing in the coolant chamber, a specific heat of the coolant, an inflow temperature of the coolant, the average temperature of the housing, a convection coefficient of the coolant, and a contact surface area of the coolant,
wherein power input to the motor is controlled by the endothermic amount,
wherein the endothermic amount of the coolant is converted into a current value, and the current value is used as a factor for controlling power input to the motor,
wherein the thermal equivalent circuit is used to calculate the temperature of the inner one side of the housing and to calculate the average temperature of the housing, and
wherein the preset equation includes
Mass Flow Rate×Specific Heat of Coolant×(Average Temperature of Housing?Inflow Temperature of Coolant)×(exp

US Pat. No. 10,218,302

CONTROLLER AND CONTROL METHOD FOR ELECTRIC MOTOR

HITACHI AUTOMOTIVE SYSTEM...

1. A controller for an electric motor equipped with a plurality of energization systems each composed of an inverter and coils corresponding to a plurality of phases, the controller comprising:a control unit configured to
receive a detection value of a current in each of the energization systems and output a control signal to the respective inverter of each of the energization systems;
execute a first diagnosis to detect an occurrence of an abnormality in each of the energization systems under energization control; and
execute a second diagnosis to detect an occurrence of an abnormality in each of the energization systems not under energization control,
wherein when (i), in the first diagnosis, the control unit detects an abnormality in one of the energization systems and, in the second diagnosis, the control unit detects no abnormality in the one of the energization systems, or (ii) when, in the first diagnosis, the control unit detects an abnormality in one of the energization systems, the control unit is configured to
stop energization control over the one of the energization systems, and, in such a state, following detection of an abnormality in another of the energization systems, restart energization control over the one of the energization systems so as to drive the electric motor;
wherein when, in the second diagnosis, the control unit detects no abnormality in the one of the energization systems and detects an abnormality in another of the energization systems, the control unit restarts energization control over the one of the energization systems where no abnormality is detected in the second diagnosis; and
wherein the control unit is configured to perform the second diagnosis on a part of the energization systems, and the electric motor is supplied with current from another of the energization systems not subject to the second diagnosis.

US Pat. No. 10,218,300

TRANSFORMER PHASE PERMUTATION CAUSING MORE UNIFORM TRANSFORMER PHASE AGING AND GENERAL SWITCHING NETWORK SUITABLE FOR SAME

International Business Ma...

1. An apparatus comprising:a first sorting network comprising a first logic circuit configured to sort input signals A, B, C, wherein the sorting is performed so the signals A, B, C are always in a first particular order based on values of the signals A, B, C, and wherein the first logic circuit is further configured to connect the input signals A, B, C to first outputs based on the first particular order;
a second sorting network comprising a second logic circuit configured to sort output signals A0, B0, C0 to second outputs based on values of the output signals A0, B0, C0, wherein the sorting is performed so the second outputs are always in a second particular order based on the values of the output signals A0, B0, C0, and wherein the second logic circuit is further configured to connect the second outputs to the output signals A0, B0, C0, based on the second particular order; and
connection circuitry configured so that first outputs and the second outputs are connected so the first outputs with lower input-signal values in the first particular order are connected to second outputs with higher output-signal values in the second particular order and the first outputs with higher input-signal values in the first particular order are connected to second outputs with lower output-signal values in the second particular order, wherein:
the first logic circuit is configured to sort input transformer phases to age-sorted phases based on historical aging information for the input transformer phases, wherein the sorting is performed so the age-sorted phases are always in a first particular order based on corresponding ages of the input transformer phases, the first logic circuit further configured to connect the transformer input phases to outputs for the age-sorted phases based on the first particular order;
the second logic circuit is configured to sort transformer output phases to load-sorted phases based on output load for each of the transformer output phases, wherein the sorting is performed so the load-sorted phases are always in a second particular order based on the output loads, wherein the second logic circuit is further configured to connect the inputs for the load-sorted phases to the output transformer phases based on the second particular order; and
the connection circuitry is configured so that load-sorted phases and the age-sorted phases are connected so the outputs for the age-sorted phases with lower age are connected to inputs for load-sorted phases with higher output loads and the outputs for the age-sorted phases with higher age are connected to inputs for load-sorted phases with lower output loads.

US Pat. No. 10,218,299

PHASE VOLTAGE DETECTION CIRCUIT AND POWER GENERATION CONTROL DEVICE

Mitsubishi Electric Corpo...

3. A phase voltage detection circuit that detects a phase voltage signal generated by an armature coil of an alternating current (AC) power generator, the phase voltage detection circuit comprising:a peak hold circuit that determines an envelope of the phase voltage signal using an operational amplifier;
a voltage offsetting circuit that shifts an output voltage from the peak hold circuit by a preset offset amount;
a comparator that compares the phase voltage signal with the shifted output voltage from the voltage offsetting circuit, and outputs a phase voltage detection signal,
wherein the peak hold circuit includes:
the operational amplifier including an inverting input terminal to which the phase voltage signal is inputted;
a PMOS transistor having a gate, a source, and a drain that are connected respectively to an output terminal of the operational amplifier, a power supply, and a non-inverting input terminal of the operational amplifier; and
a capacitor and a diode that are connected between the drain of the PMOS transistor and a reference potential.

US Pat. No. 10,218,296

ROTOR POSITION SENSING SYSTEM FOR THREE PHASE MOTORS AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. A method for sensing rotor position of a motor, the method comprising:coupling a controller with a three phase permanent magnet synchronous motor (PMSM);
applying, using the controller, a plurality of current vectors to the PMSM, the plurality of current vectors comprising a plurality of dummy current vectors and a plurality of measured current vectors, wherein at least one measured current vector is applied quadrature to a dummy current vector from the plurality of dummy current vectors immediately preceding each measured current vector;
measuring, with a measurement circuit, a plurality of values from a three-phase inverter coupled with the PMSM, each value of the plurality of values corresponding with one of the plurality of measured current vectors, and;
calculating, with one or more logic elements coupled with the PMSM, based on the plurality of values and using one or more position algorithms, a position of a rotor of the PMSM relative to a stator of the PMSM.

US Pat. No. 10,218,292

ACTIVE POSITIONING ENCODER AND OPERATING METHOD THEREFOR

Shanghai Jiaotong Univers...

1. An active position encoder, comprising:a display device, said display device being used for displaying at least a first pattern;
a reading device, said reading device comprising at least a first read head, wherein said first read head is used for reading said first pattern so as to obtain an image signal; and
a signal processing device, said signal processing device executing signal processing on the image signal of said first read head so as to determine a single-dimensional position of said first read head relative to said display device,
wherein said first pattern is a first periodic pattern which changes periodically in a first direction, said first read head reads said first periodic pattern so as to obtain said image signal of a part of the periodic pattern in the first direction, and said signal processing device executes said signal processing on said image signal of said first read head so as to determine a single-dimensional position of said first read head in said first direction relative to said display device.

US Pat. No. 10,218,290

INVERTER HAVING AT LEAST ONE INVERTER BRIDGE BETWEEN TWO BUSBARS

SMA Solar Technology AG, ...

1. An inverter comprising a single phase inverter bridge, which is connected on an input side thereof between two DC busbars and on an output side thereof to an AC output,wherein the two DC busbars extend, overlapping one another, in mutually parallel planes,
wherein the single phase inverter bridge comprises a subcircuit between the AC output and each DC busbar, thereby defining two subcircuits,
wherein semiconductor modules, which form the two subcircuits, are arranged next to one another,
wherein the semiconductor modules are connected to the two DC busbars and the AC output via connections, and
wherein a connection element, which leads to the AC output, connects the semiconductor modules of the two subcircuits to one another in a region overlapped by the DC busbars,
wherein each subcircuit provided between the AC output and one of the DC busbars comprises a plurality of semiconductor switches, and
wherein the connection element, which leads to the AC output, begins in the region overlapped by the DC busbars on a side of the DC busbars that faces the semiconductor modules, connects the semiconductor modules of the two subcircuits to one another there, and emerges beneath the DC busbars.

US Pat. No. 10,218,289

STACKED SWITCHED CAPACITOR ENERGY BUFFER CIRCUIT

MASSACHUSETTS INSTITUTE O...

1. A stacked switched capacitor (SSC) energy buffer circuit comprising:two sub-circuits having terminals that are serially coupled during a first operating mode wherein each sub-circuit comprises one or more capacitors, and at least one sub-circuit further comprises a plurality of switches disposed and operable to selectively couple the one or more capacitors of the at least one sub-circuit to: (a) enable dynamic reconfiguration of how the one or more capacitors of the at least one sub-circuit are coupled to the terminals of the at least one sub-circuit; and (b) dynamically reconfigure one or more interconnections among the one or more capacitors within the at least one sub-circuit; wherein the SSC energy buffer circuit provides a total peak energy buffering capability and wherein the peak energy buffered by one of the two sub-circuits is greater than 66% of the total peak energy buffering capability of the SSC energy buffer circuit.

US Pat. No. 10,218,288

POWER CONVERSION CIRCUIT BOARD, AND ELECTRIC COMPRESSOR

MITSUBISHI HEAVY INDUSTRI...

1. A power conversion circuit board on which a power conversion circuit configured to convert direct current to alternating current is mounted,wherein a low voltage circuit to which a low voltage is applied and a high voltage circuit to which a high voltage is applied are separately disposed in different areas on the same board surface, and
in the high voltage circuit, a wiring from a high voltage input terminal to a switching element is formed on the board surface, and a wiring from the switching element to a high voltage output terminal comprises a bus bar which is provided at a predetermined distance from the board surface, and
wherein the wiring from the high voltage input terminal to the switching element and the wiring from the switching element to the high voltage output terminal are disposed to three-dimensionally intersect with each other.

US Pat. No. 10,218,286

MULTIPLE STAGE GATE DRIVE FOR CASCODE CURRENT SENSING

Power Integrations, Inc.,...

1. A power converter, comprising;an energy transfer element coupled between an input of the power converter and an output of the power converter;
a cascode circuit including a low voltage switch coupled to a normally-on switch, wherein the cascode circuit is coupled to the input of the power converter and the energy transfer element; and
a controller coupled to control switching of the cascode circuit to control a transfer of energy from the input of the power converter to the output of the power converter, wherein the controller includes:
a current sense circuit coupled to generate a current limit signal and an overcurrent signal in response to a source signal, a first sense finger signal, and a second sense finger signal coupled to be received from the cascode circuit;
a control circuit coupled to generate a control signal in response to the current limit signal and the overcurrent signal; and
a drive circuit coupled to generate a drive signal with a multiple stage gate drive in response to the control signal to control switching of the low voltage switch, wherein the drive signal provided by a first stage of the multiple stage gate drive is coupled not to fully enhance the low voltage switch, and wherein the drive signal provided by a second stage of the multiple stage gate drive is coupled to fully enhance the low voltage switch.

US Pat. No. 10,218,283

INSULATED SYNCHRONOUS RECTIFICATION DC/DC CONVERTER

ROHM CO., LTD., Kyoto (J...

1. A synchronous rectification controller to be arranged on a secondary side of an insulated synchronous rectification DC/DC converter, and structured to control a synchronous rectification transistor, and, the synchronous rectification controller comprising:a drain pin coupled to a drain of the synchronous rectification transistor;
a ground pin coupled to a source of the synchronous rectification transistor;
a first comparator structured to compare a drain voltage at the drain pin with a first threshold voltage, and structured to assert a set signal when the drain voltage becomes lower than the first threshold voltage;
a second comparator structured to compare the drain voltage with a second threshold voltage, and structured to assert a reset signal when the drain voltage becomes higher than the second threshold voltage;
a forced turn-off circuit coupled to receive the reset signal second comparator, and structured to start a time measurement operation in response to an assertion of the reset signal and to assert a forced turn-off signal so as to forcibly turn off the synchronous rectification transistor after a predetermined time-up period elapses after the assertion of the reset signal;
a flip-flop structured to generate a pulse signal which is switched to an on level in response to an assertion of the set signal, and which is switched to an off level in response to an assertion of the reset signal and an assertion of the forced turn-off signal; and
a third comparator structured to compare the drain voltage with a third threshold voltage configured as a predetermined positive voltage,
wherein the synchronous rectification transistor turns on in response to an assertion of the set signal and turns off in response to the assertion of the reset signal, and wherein, the forced turn-off circuit is coupled to receive an output signal from the third comparator, and when the drain voltage crosses the third threshold voltage, the time measurement operation of the forced turn-off circuit is reset so as to ensure a switching operation of the synchronous rectification transistor during a discontinuous mode.

US Pat. No. 10,218,282

METHOD AND APPARATUS FOR SEQUENCING OUTPUTS IN A MULTI-OUTPUT POWER CONVERTER SYSTEM

Power Integrations, Inc.,...

1. A method of sequencing output voltages in a multi-output switch-mode converter system comprising:providing a power source to a primary of the multi-output switch-mode converter system;
transferring energy from the primary to a highest voltage secondary output so as to increase a voltage of the highest voltage secondary output;
transferring energy from the primary to a lowest voltage secondary output so as to concurrently increase a voltage of the lowest voltage secondary output while regulating the voltage of the highest voltage secondary output, the voltage of the highest voltage secondary output greater than the voltage of the lowest voltage secondary output; and
transferring energy from the primary to the highest voltage secondary output and the lowest voltage secondary output so as to concurrently increase the voltage of the highest voltage secondary output and the voltage of the lowest voltage secondary output.

US Pat. No. 10,218,281

SWITCH MODE POWER SUPPLIES, CONTROL ARRANGEMENTS THEREFOR AND METHODS OF OPERATING THEREOF

NXP B.V., Eindhoven (NL)...

1. A control arrangement for a switch mode power supply (“SMPS”) operable in a burst mode, comprising:an opto-coupler connected to a proportional-integrating error amplifier configured to transfer, from a secondary side to a primary side of the SMPS through an LED current, a control signal indicative of a time-varying error between a reference signal and a signal indicative of an actual value of an output parameter,
the proportional-integrating error amplifier connected to a ground side of the opto-coupler configured to determine the LED current from the time-varying error; and
a feedback loop including a resistor connected between a ground connection of the proportional-integrating error amplifier and a ground connection configured to reduce a magnitude of the LED current between bursts in the burst mode by modifying a reference signal portion of the time-varying error by using an adder to add a time-dependent offset to the reference signal portion derived in the proportional-integrating error amplifier from the LED current to prevent the LED current from increasing during a normal mode.

US Pat. No. 10,218,280

POWER CONVERTER, SWITCH CONTROL CIRCUIT AND SHORT CIRCUIT DETECTION METHOD FOR CURRENT SENSING RESISTOR OF THE POWER CONVERTER

RICHTEK TECHNOLOGY CORPOR...

1. A power converter, configured to operably convert an input voltage to an output voltage, the power converter comprising:an energy storing/releasing unit;
a power switch, configured to be operably turned ON or OFF according to an operation signal, to control the energy storing/releasing unit, so that the input voltage is converted to the output voltage;
a current sensing resistor having one end coupled to the power switch and having another end coupled to ground; and
a switch control unit, configured to operably generate the operation signal, to control the power switch, wherein the switch control unit is coupled to the current sensing resistor, to receive a current sensing signal, so that the switch control unit samples-and-holds the current sensing signal to generate a first sample-and-hold voltage at a first time point and samples-and-holds the current sensing signal to generate a second sample-and-hold voltage at a second time point, the second time point being after the first time point, wherein the first sample-and-hold voltage indicates a first condition of the current sensing signal at the first time point, and the second sample-and-hold voltage indicates a second condition of the current sensing signal at the second time point;
wherein the switch control unit includes a current sensing resistor short circuit detection circuit, and when it is determined that a short circuit occurs in the current sensing resistor, the current sensing resistor short circuit detection circuit generates a current sensing resistor short circuit signal, wherein the current sensing resistor short circuit detection circuit compares a voltage difference between the first sample-and-hold voltage generated at the first time point and the second sample-and-hold voltage generated at the second time point with a reference voltage to determine whether a short circuit occurs in the current sensing resistor, whereby when the voltage difference between the first sample-and-hold voltage and the second sample-and-hold voltage is smaller than the reference voltage, it is determined that the short circuit occurs in the current sensing resistor.

US Pat. No. 10,218,279

METHODS AND CIRCUITRY FOR OPERATING SWITCHING POWER SUPPLIES BASED ON SWITCHING FREQUENCY COMPARISON

Texas Instruments Incorpo...

1. A controller for a switching power supply, the controller comprising:comparison circuitry operable to compare a switching frequency for the switching power supply to a predetermined switching frequency;
voltage measuring circuitry operable to measure the output voltage of the power supply; and
disabling circuitry operable to disable at least one component in the power supply in response to the switching frequency being less than the predetermined switching frequency and the output voltage being greater than a predetermined output voltage.

US Pat. No. 10,218,278

ISOLATED DC-DC VOLTAGE CONVERTERS

Infineon Technologies Aus...

1. A voltage converter, comprising:a power stage comprising one or more power switches;
a conditioning circuit operable to supply power to a load of the voltage converter;
a transformer configured to couple the power stage to the conditioning circuit; and
a controller operable to:
measure a voltage across a secondary winding of the transformer or a voltage within the conditioning circuit, thereby providing a measured voltage;
estimate magnetic flux within the transformer based upon the measured voltage, thereby providing an estimated magnetic flux; and
generate control signals that drive the one or more power switches based upon the estimated magnetic flux.

US Pat. No. 10,218,276

ISOLATED MULTI-LEVEL RESONANT TOPOLOGIES FOR WIDE-RANGE POWER CONVERSION AND IMPEDANCE MATCHING

The Board of Trustees of ...

1. A DC to DC electric power converter comprising:a resonant power inverter configured to receive a DC input and to provide an AC output having a frequency fout, wherein an output impedance of the power inverter is Zout;
two or more resonant rectifier circuits directly connected to the AC output provided by the power inverter without a transformation stage between the power inverter and rectifier impedance provided by the two or more resonant rectifier circuits, wherein the resonant rectifier circuits are tuned to operate resonantly at fout, and wherein the resonant rectifier circuits are each configured to receive the AC output and to provide a DC output;
wherein DC electrical isolation between the two or more resonant rectifier circuits is provided exclusively with capacitors; and
wherein impedance matching is provided either by parallel connections of the resonant rectifier circuits to the power inverter or by series connections of the resonant rectifier circuits to the power inverter.

US Pat. No. 10,218,275

MULTI-STAGE VOLTAGE MULTIPLICATION CIRCUIT FOR INVERTING A DIRECT CURRENT POWER SIGNAL

Smart Prong Technologies,...

1. A system, comprising:a boost circuit configured to:
receive a direct current (DC) signal at a first DC voltage, a duty clock signal, and a reference DC signal at a second DC voltage, wherein the duty clock signal controls a duty cycle of components within the boost circuit;
generate a first intermediate DC signal at a third DC voltage based on the duty clock signal and a comparison of the reference DC signal and a second intermediate DC signal received at a fourth DC voltage, wherein the boost circuit is further configured to adjust the third DC voltage of the first intermediate DC signal to cause the fourth DC voltage of the second intermediate DC signal to approach the second DC voltage of the reference DC signal based on the comparison of the reference DC signal and the second intermediate DC signal;
a voltage converter circuit electrically coupled to the boost circuit and configured to:
receive the first intermediate DC signal at the third DC voltage;
receive a clock signal; and
generate the second intermediate DC signal at the fourth DC voltage, wherein the fourth DC voltage of the second intermediate DC signal is greater than the third DC voltage of the first intermediate DC signal;
a voltage driver circuit electrically coupled to the voltage converter circuit and configured to:
receive the second intermediate DC signal at the fourth DC voltage; and
generate an alternating current (AC) signal at an AC voltage based on the second intermediate DC signal at the fourth DC voltage;
a low voltage circuit electrically coupled to the boost circuit, the voltage converter circuit, and the voltage driver circuit and configured to:
determine a current of the first intermediate DC signal;
determine the fourth DC voltage of the second intermediate DC signal;
generate the duty clock signal based on the second intermediate DC signal at the fourth DC voltage, wherein the duty clock signal adjusts a duty cycle of the boost circuit;
generate the clock signal based on the current of the first intermediate DC signal and the fourth DC voltage of the second intermediate DC signal, wherein the clock signal adjusts a clock rate within the voltage converter circuit; and
transmit the clock signal to the voltage converter circuit.

US Pat. No. 10,218,218

SOLID-STATE LIGHTING SYSTEM OPERATED WITH A HIGH DC VOLTAGE

ALEDDRA INC., Renton, WA...

1. A light-emitting diode (LED) lighting system, comprising:a luminaire, comprising:
at least two electrical conductors configured to couple to a line voltage from alternate-current (AC) mains or a direct-current (DC) voltage from a DC power source;
one or more LED arrays;
a first full-wave rectifier connected to the at least two electrical conductors and configured to convert the line voltage from the AC mains into a first DC voltage or to receive and to pass the DC voltage from the DC power source;
an input filter configured to suppress a radio-frequency interference (RFI) noise; and
a Buck circuit coupled to the first full-wave rectifier via the input filter, the Buck circuit configured to provide a power factor correction and to convert the first DC voltage into a second DC voltage that powers up the one or more LED arrays and to meet LED luminaire efficacy and power factor requirements when the line voltage from the AC mains is available;
a rechargeable battery;
a second full-wave rectifier connected to unswitched AC mains and configured to convert a line voltage from the unswitched AC mains into a third DC voltage;
a first driver comprising an isolated step-down converter, a first ground reference, and a second ground reference electrically isolated from the first ground reference, wherein the first driver is coupled to the second full-wave rectifier and configured to convert the third DC voltage into a fourth DC voltage that charges the rechargeable battery to reach a fifth DC voltage;
a second driver comprising a step-up converter comprising a first electronic switch, a second electronic switch, and a center-tapped transformer, the second driver configured to receive the fifth DC voltage from the rechargeable battery and to convert the fifth DC voltage into a sixth DC voltage when the line voltage from the unswitched AC mains is unavailable; and
a voltage sensing and control circuit comprising a first voltage sensing circuit and a relay switch configured to connect either the line voltage from the unswitched AC mains or the sixth DC voltage to the at least two electrical conductors to operate the luminaire, the voltage sensing and control circuit configured to enable the second driver when a rechargeable battery test is performed,
wherein:
the first voltage sensing circuit is configured to detect whether the line voltage from the unswitched AC mains is available and to control the relay switch to couple the sixth DC voltage to the at least two electrical conductors when the line voltage from the unswitched AC mains is unavailable or when the rechargeable battery test is performed, and
the rechargeable battery test is performed to ensure that the rechargeable battery is in a working condition.

US Pat. No. 10,218,207

RECEIVER CHIP FOR ROUTING A WIRELESS SIGNAL FOR WIRELESS POWER CHARGING OR DATA RECEPTION

Energous Corporation, Sa...

1. A method for charging an electronic device, the method comprising:receiving, by an antenna of the electronic device, a wireless signal, wherein:
a receiver chip is embedded in the electronic device and connected to the antenna, the receiver chip including a switch and rectifier circuitry, and
the switch is configured to route the wireless signal to either the rectifier circuitry or a transceiver of the electronic device;
in response to determining that the antenna is receiving power above a threshold level from the wireless signal, routing, via the switch, the received wireless signal to the rectifier circuity, the rectifier circuitry being configured to convert the wireless signal into usable energy for charging a battery of the electronic device connected to the rectifier circuitry, wherein the wireless signal routed to the rectifier circuitry is received from a wireless power transmitter positioned in a near-field distance from the antenna; and
in response to determining that the antenna is not receiving power above the threshold level from the wireless signal, routing, via the switch, the received wireless signal to the transceiver, the transceiver being configured to process the wireless signal as data from the wireless power transmitter or another electronic device, wherein the transceiver is not connected to the battery of the electronic device or the rectifier circuity of the receiver chip.

US Pat. No. 10,218,191

RECHARGEABLE BATTERY

LEAPFROG ENTERPRISES, INC...

1. A rechargeable battery pack configured to provide power to a device that also accepts at least one standard non-rechargeable battery, the rechargeable battery pack comprising:a housing including:
a main housing portion having a form factor of the at least one standard non-rechargeable battery for housing at least one battery cell; and
a recharging circuitry housing portion molded integrally as part of the housing and extending laterally outward from a side of the main housing portion for housing a recharging circuitry;
the recharging circuitry coupled with the at least one battery cell, the recharging circuitry configured to charge the at least one battery cell when the rechargeable battery pack is inserted into the device that also accepts the at least one non-rechargeable battery;
a protection circuit coupled with the recharging circuitry;
power contacts on the main housing portion configured to provide power from the at least one battery cell to the device; and
one or more circuitry on the recharging circuitry housing portion configured to electrically couple the recharging circuitry to the device.

US Pat. No. 10,218,147

GAS OPTIMIZATION IN A GAS DISCHARGE LIGHT SOURCE

Cymer, LLC, San Diego, C...

1. A method of adjusting one or more operating characteristics of a light source comprising a first stage with a first gas discharge chamber filled with a first gas mixture and including a first pulsed energy source and a second stage with a second gas discharge chamber filled with a second gas mixture and including a second pulsed energy source, the method comprising:performing a refill procedure on the first gas discharge chamber including replacing the first gas mixture in the first gas discharge chamber and performing a refill procedure on the second gas discharge chamber including replacing the second gas mixture in the second gas discharge chamber;
after the refill procedures are completed, performing a first gas adjustment procedure on the first gas discharge chamber, the first gas adjustment procedure comprising adjusting one or more operating characteristics of the first gas discharge chamber while supplying energy to the first gas discharge chamber using the first pulsed energy source until a pulsed amplified light beam is output from the first stage and directed toward the second stage, the adjustment being based on a measured value of an operating parameter of the first gas discharge chamber; and
after it is determined that the operating characteristic of the first gas discharge chamber no longer should be adjusted and the first gas adjustment procedure on the first gas discharge chamber is thereby completed, applying a margin-based adjustment procedure on the second gas discharge chamber, the margin-based adjustment procedure comprising:
estimating extreme values of operating parameters associated with the second gas discharge chamber while operating the second gas discharge chamber under a set of extreme test conditions,
determining whether to adjust one or more operating characteristics of the second gas discharge chamber based on the estimated extreme values of the operating parameters, and
adjusting the operating characteristics of the second gas discharge chamber if it is determined that an operating characteristic of the second gas discharge chamber should be adjusted.

US Pat. No. 10,218,142

PACKAGING OF AN OPTICAL FIBER COMBINER NOT IMMERSED IN COOLING WATER IN HIGH-POWER LASER APPLICATIONS

LIGHTEL TECHNOLOGIES, INC...

1. A water-cooled package of an optical fiber combiner, comprising:an optical fiber combiner assembly comprising:
a combiner mount comprising a first submount and a second submount each respectively comprising a U-groove in a lengthwise direction and two flat portions symmetrically connected to the U-groove in a widthwise direction, wherein the two flat portions of the first submount and the two flat portions of the second submount are mechanically coincident in a way to form a combiner cavity between the U-groove of the first submount and the U-groove of the second submount; and
an optical fiber combiner with multiple input optical fibers and an output optical fiber, wherein the optical fiber combiner is fixed in the combiner cavity;
a front end cap and a rear end cap each respectively comprising an end cap inner wall and an end cap outer wall, the end cap inner wall of each of the front end cap and the rear end cap configured to accommodate the optical fiber combiner assembly; and
a housing comprising an internally hollow space and a housing inner wall, the housing configured to hold and fix the front end cap and the rear end cap and to accommodate a cooling water to facilitate thermal dispersion, wherein a water-cooled cavity is formed by an enclosure of the front end cap, the rear end cap, the optical fiber combiner assembly, and the housing inner wall,
wherein the housing is waterproof at each of interfaces between the front end cap and the combiner mount, between the combiner mount and the rear end cap, between the front end cap and the housing, and between the rear end cap and the housing;
wherein the optical fiber combiner is configured to receive optical energy from multiple pump lasers inputted via the multiple input optical fibers, combine the multiple pump lasers, and couple the multiple input optical fibers into the output optical fiber; and
wherein the multiple input optical fibers and the output optical fiber are partially stripped for a stripped portion substantially in a middle area of the optical fiber combiner and two non-stripped portions out of the stripped portion.

US Pat. No. 10,218,120

CONNECTOR DEVICE

AutoNetworks Technologies...

1. A connector device, comprising:device-side connectors respectively installed on outer surfaces of electrical devices juxtaposed in a width direction;
holding-side connectors connectable respectively to the corresponding device-side connectors by moving forward from behind the respective device-side connectors and allowed to relatively rotate about axes along a front-rear direction with respect to the device-side connectors;
a holder configured to couple the respective holding-side connectors in a state juxtaposed in the width direction and enabling the respective holding-side connectors to be connected collectively to the corresponding device-side connectors;
provided for the respective holding-side connectors on a side where the holding-side connectors are located;
guiding portions provided to extend in the front-rear direction behind the respective device-side connectors on the outer surfaces of the electrical devices and configured to guide the connection of the holding-side connectors and the device-side connectors by being fit to the respective guide; andcoupling members provided between the respective holding-side connectors and the holder and configured to couple the respective holding-side connectors to the holder.

US Pat. No. 10,218,112

ELECTRICAL PLUG CONNECTOR WITH A CABLE FIXING ARRANGEMENT

HARTING Electronics GmbH,...

1. An electrical plug connector, comprising:an insulating plug connector housing; and
at least one electrical contact element that is received in the plug connector housing,
wherein the plug connector housing forms a mating side and a connection side,
wherein at least one contact opening is formed in the plug connector housing, said contact opening extending from the mating side through the plug connector housing as far as the connection side,
wherein the electrical contact element is received in the contact opening and is fixed therein,
wherein the plug connector housing comprises a cable fixing arrangement on the connection side,
wherein the cable fixing arrangement is formed from a first fixing element, which is formed as one on the plug connector housing, and a second fixing element that cooperates with the first fixing element,
wherein the first fixing element and the second fixing element can latch with one another by way of a guide in a linear manner transverse with respect to the at least one contact opening,
wherein the second fixing element comprises at least one first slot, wherein the first slot has an inner face and is open towards the first fixing element, and
wherein the first slot comprises at least two webs on the inner face, wherein the webs are oriented parallel, in the direction of the open side, towards the first fixing element.

US Pat. No. 10,218,111

IMPLANTABLE PLUG CONNECTOR

CORTEC GMBH, Freiburg (D...

1. An implantable plug connector, comprising:an inner portion (1), comprising a number of contact surfaces (9), which are embedded in at least one surface (81) of a first substrate (8),
an outer portion (2), comprising a number of contact surfaces (9), which are embedded in at least one surface (82) of a second substrate (8),
wherein the outer portion (2) defines a space, in which the inner portion (1) is receivable in an assembled state,
wherein the contact surfaces (9) embedded in the at least one surface of the first substrate and the contact surfaces embedded in the at least one surface of the second substrate, in pre-assembled state, are set back with respect to the corresponding surface (81, 82) of the respective substrate (8),
and wherein, in the assembled state, the inner portion (1) is pressed against the outer portion (2) such that contact surfaces (9) corresponding to each other contact each other.

US Pat. No. 10,218,108

ELECTRICAL CONNECTOR ASSEMBLY

FCI USA LLC, Etters, PA ...

1. An electrical connector comprising:an electrically insulative connector housing including i) a first housing member, ii) a second housing member separate from the first housing member, opposite the first housing member, and attached to the first housing member, and iii) an inner housing member between the first housing member and the second housing member, wherein the first housing member defines a receptacle configured to receive a paddle card;
a plurality of leadframe assemblies supported by, at least, the inner housing member of the connector housing, each of the leadframe assemblies including an electrically insulated leadframe housing and a plurality of electrical contacts supported by the leadframe housing, each of the electrical contacts defining a mating portion at the receptacle so as to be configured to contact the received paddle card, and a mounting portion opposite the mating portion; and
a plurality of ground plates disposed between respective ones of the leadframe assemblies, the grounds each defining a ground mating portion at the receptacle so as to be configured to contact the received paddle card, and a ground mounting portion opposite the ground mating portion.

US Pat. No. 10,218,104

CONNECTOR WITH A SPRING TERMINAL ENSURING RELIABLE CONNECTION TO A MATING TERMINAL

AutoNetworks Technologies...

1. A connector, comprising:a body;
a wire with a conductive core including a held portion having conductivity and held in the body, a coating covering the held portion of the core, the core further having a flexible portion extending from the held portion toward a mating terminal and having flexibility, and a connecting portion provided on a leading end part of the flexible portion;
a metal plate fixed to the core at the connecting portion and being on a side of the core facing toward the mating terminal; and
a spring having a spring property, the spring being held in the body and extending from the body toward the connecting portion, the spring including a contact portion held in contact with the connecting portion of the wire and thereby causing the metal plate to be pressed into contact with the mating terminal.

US Pat. No. 10,218,100

CONNECTOR FOR ZERO-FORCE CONTACTING ON A PRINTED CIRCUIT BOARD

HARTING ELECTRONICS GMBH,...

1. A connector for installation on a printed circuit board,wherein the connector comprises a contacting part which includes at least two contact elements, each of which can be connected, on a connection side, to an individual conductor and, on a plug-in side, to a conductive track of the printed circuit board,
wherein the connector comprises a connection part which encloses the individual conductors and, in the region of each individual conductor, has a recess, into each of which a contact element engages for the electrical connection between individual conductor and contact element, and
wherein the connection part and the contacting part are connected to each other via precisely one screw and the screw is situated in the center.

US Pat. No. 10,218,088

CABLE CONNECTOR ASSEMBLY

LOTES CO., LTD, Keelung ...

1. A cable connector assembly, comprising:an insulating body;
a first terminal group and a second terminal group received in the insulating body and respectively arranged into an upper row and a lower row, wherein the first terminal group comprises at least one first ground terminal, the at least one first ground terminal has a first soldering portion, the second terminal group comprises at least one second ground terminal, the at least one second ground terminal has a second soldering portion, and the second soldering portion and the first soldering portion are arranged oppositely;
a shielding sheet, fixed in the insulating body and located between the first terminal group and the second terminal group; and
a cable comprising at least one ground core wire, wherein the at least one ground core wire is located between the first soldering portion and the second soldering portion and is in electrical contact with the first soldering portion, the second soldering portion and the shielding sheet.

US Pat. No. 10,218,062

WIRELESS TRAIN COMMUNICATION SYSTEM

ICOMERA AB, Gothenburg (...

1. A wireless communication system for a train, comprising:a plurality of antennas arranged on the train;
at least one router in the train for receiving and transmitting wireless data communication to and from a stationary communication server outside said train through at least one exterior mobile network via said plurality of antennas;
wherein the antennas are window antennas, arranged integrated in or connected to windowpanes of the train, wherein each windowpane comprises a heat resistant, metallized layer, and wherein the window antennas are distributed over at least two windows on each side of the train.

US Pat. No. 10,218,058

ELECTRONIC DEVICE INCLUDING ANTENNA

SAMSUNG ELECTRONICS CO., ...

1. An electronic device comprising:a housing comprising a first surface facing a first direction, a second surface facing a second direction opposite the first direction, and a side surface at least partially surrounding a space between the first surface and the second surface;
a touch screen display positioned inside the housing and exposed through the first surface, wherein the display comprises a display panel and a touch panel that is separated from or integrated with the display panel;
a conductor forming at least a portion of the side surface;
at least one substantially transparent conductive pattern integrated into the display;
a ground interposed between the first surface and the second surface;
a wireless communication circuit including a port electrically coupled to the conductor; and
a processor electrically coupled to the display and the wireless communication circuit,
wherein the substantially transparent conductive pattern is electrically coupled to at least one of the port of the wireless communication circuit and the ground.

US Pat. No. 10,218,056

WIRELESS COMMUNICATION DEVICE AND WIRELESS COMMUNICATION SYSTEM

SONY CORPORATION, Tokyo ...

1. A wireless communication system comprising:a first radio including
a first circular array antenna including a plurality of transmission polarized patch antennas, the first circular array antenna being configured to transmit a first whirl of waves in a first orbital angular momentum (OAM) state, and
a second circular array antenna including a plurality of reception polarized patch antennas provided separately from the first circular array antenna, the second circular array antenna being configured to receive a second whirl of waves in a second OAM state, the second whirl of waves in the second OAM state being orthogonal to the first whirl of waves in the first OAM state; and
a second radio including
a third circular array antenna including a plurality of transmission polarized patch antennas, the third circular array antenna being configured to transmit the second whirl of waves to the first radio in the second OAM state, and
a fourth circular array antenna including a plurality of reception polarized patch antennas provided separately from the third circular array antenna, the fourth circular array antenna being configured to receive the first whirl of waves in the first OAM state,
wherein the first circular array antenna of the first radio transmits the first whirl of waves in the first OAM state to the fourth circular array antenna of the second radio,
wherein the first whirl of waves received by the fourth circular array antenna of the second radio reaches the third circular array antenna of the second radio via coupling between the third circular array antenna of the second radio and the fourth circular array antenna of the second radio, and
wherein the third circular array antenna of the second radio transmits the second whirl of waves in the second OAM state to the second circular array antenna of the first radio.

US Pat. No. 10,218,021

FLOW BATTERY ELECTROLYTE COMPOSITIONS CONTAINING AN ORGANOSULFATE WETTING AGENT AND FLOW BATTERIES INCLUDING SAME

PRIMUS POWER CORPORATION,...

1. A flow battery system, comprising:a stack of flow battery cells that do not contain a separator in reaction zones formed between anode and cathode electrodes of each flow battery cell;
a reservoir connected to the reaction zones of the stack; and
an electrolyte disposed in the reservoir, the electrolyte comprising:
aqueous ZnBr2 or aqueous ZnBr2 and ZnCl2;
bromine;
a bromine complexing agent;
an anti-dendrite agent;
a chelating agent; and
sodium dodecyl sulfate (SDS) at a concentration ranging from about 2 mM to about 35 mM,
wherein:
the electrolyte maintains a pH of from about 1.5 to about 3, after 50 charge and discharge cycles; and
the electrolyte does not comprise a pH stabilizer.

US Pat. No. 10,218,017

WATER MANAGEMENT SYSTEM IN ELECTROCHEMICAL CELLS WITH VAPOR RETURN COMPRISING AIR ELECTRODES

NANTENERGY, INC., Scotts...

1. A system for managing water content in one or more electrochemical cells, each electrochemical cell comprising a plurality of electrodes and a liquid ionically conductive medium, the system comprising:a desiccator unit having an input connected to the one or more electrochemical cells, the desiccator unit being configured for extracting and capturing water from a humid gas-phase exiting from the one or more electrochemical cells;
a heater for selectively heating the desiccator unit to selectively release captured water from the desiccator unit to provide an output humid gas-phase through an output; and
a carbon dioxide scrubber configured to absorb carbon dioxide,
wherein, during a water capture mode, the system is configured to extract and capture water at the desiccator unit from the humid gas-phase exiting from the one or more electrochemical cells; and, wherein, during a cell humidification mode, the system is configured to release at least a portion of the captured water in the desiccator unit, via actuation of the heater, to produce the output humid gas-phase that is transported into the one or more electrochemical cells; and
wherein the desiccator unit and the carbon dioxide scrubber are also configured to be selectively coupled in a scrubber humidification mode to deliver at least part of the output humid gas-phase from the desiccator unit to the carbon dioxide scrubber.

US Pat. No. 10,218,009

COOLANT PURIFICATION

INTELLIGENT ENERGY LIMITE...

1. A fuel cell system comprising:a fuel cell stack;
an ozone generator configured to introduce ozone into a coolant in the fuel cell system;
a deionisation apparatus coupled to the fuel cell stack;
a bypass conduit arranged in parallel with the deionisation apparatus; and,
a controller configured to control flow of the coolant to the fuel cell stack through either the deionisation apparatus or the bypass conduit based on the operating state of the ozone generator; and,
wherein the controller is configured such that coolant passes through the bypass conduit when a level of ozone in the coolant is determined to be above a predetermined threshold, and such that coolant passes through the deionisation apparatus when the level of ozone in the coolant is determined to be below a predetermined threshold.

US Pat. No. 10,217,972

BATTERY PACK

Sony Corporation, Tokyo ...

1. A battery comprising:a pack main body having a front side and a back side in a length direction, a top side and bottom side in a height direction, and opposite sides in a width direction in which a battery cell is embedded; and
a terminal portion provided on the front side of the pack main body,
wherein the pack main body includes first bevelled portions at corner portions formed by the top side and the opposite sides and second bevelled portions at corner portions formed by the bottom side and the opposite sides, and
wherein the terminal portion protrudes from the front side of the pack main body at a position biased to one side with respect to center lines in the width direction and the height direction, and
wherein third bevelled portions are formed at corner portions formed by the front side, and the top side, and the bottom side of the pack main body and a fourth bevelled portions are formed at corner portions formed by the back side, and the top side, and the bottom side of the pack main body, and
wherein the fourth bevelled portions are smaller than the third bevelled portions, and
wherein the first bevelled portions and the second bevelled portions are differently shaped.

US Pat. No. 10,217,899

LIGHT EMITTING DIODE WITH REFLECTIVE PART FOR UVA AND BLUE WAVELENGTHS

Lumens Co., Ltd., Yongin...

1. A light emitting diode comprising:a first conductivity type semiconductor layer having a front side and a back side;
a second conductivity type semiconductor layer having a front side and a back side;
an active layer formed between the back side of the first conductivity type semiconductor layer and the front side of the second conductivity type semiconductor layer;
a first reflective layer formed on the back side of the second conductivity type semiconductor layer; and
a reflective part formed on the back side of the first reflective layer opposite the second conductivity type semiconductor layer to reflect light of a short wavelength (UVA wavelength) band and light of a blue wavelength,
wherein the first reflective layer comprises distributed Bragg reflector (DBR) unit layers for reflecting light of a short wavelength band of 315 nm to 420 nm, each of the DBR unit layers comprises a low refractive index layer and a high refractive index layer adjacent to the low refractive index layer,
wherein the reflective part comprises a second conductivity type intermediate layer for improving ohmic contact and a reflective metal layer for reflecting light of a short wavelength band and light of a blue wavelength band.

US Pat. No. 10,217,823

SEMICONDUCTOR DEVICE

SUMITOMO ELECTRIC INDUSTR...

1. A semiconductor device, comprising:a substrate;
a channel layer made of graphene and provided on the substrate;
a source electrode and a drain electrode provided on the channel layer;
an insulating film provided on the channel layer between the source electrode and the drain electrode;
a first gate electrode provided on the insulating film between the source electrode and the gate electrode; and
a second gate electrode provided within the substrate and between the first gate electrode and the drain electrode,
wherein the first gate electrode is closer to the source electrode than the second gate electrode and partially overlaps the second gate electrode.

US Pat. No. 10,217,710

WIRING BOARD WITH EMBEDDED COMPONENT AND INTEGRATED STIFFENER, METHOD OF MAKING THE SAME AND FACE-TO-FACE SEMICONDUCTOR ASSEMBLY USING THE SAME

BRIDGE SEMICONDUCTOR CORP...

1. A wiring board, comprising:an electronic component that includes a first semiconductor device having an active surface, an encapsulant, an array of vertical connecting elements each having a first end and a second end, a first routing circuitry and a second routing circuitry, wherein (i) the encapsulant laterally covers the first semiconductor device and the vertical connecting elements and has a first surface facing the first routing circuitry and a second surface opposite to the first surface, (ii) the first routing circuitry extends over the first surface of the encapsulant, the active surface of the first semiconductor device, and the first ends of the vertical connecting elements, thereby electrically coupling the first semiconductor device and the vertical connecting elements to the first routing circuitry, and (iii) the second routing circuitry is disposed on the second surface of the encapsulant and on the second ends of the vertical connecting elements so that the second routing circuitry is electrically connected to the first routing circuitry through the vertical connecting elements;
a stiffener that laterally surrounds the electronic component and has an interior sidewall surface adjacent to peripheral edges of the electronic component; and
a third routing circuitry that is disposed over the second routing circuitry and laterally extends over the stiffener, wherein the third routing circuitry is electrically coupled to the second routing circuitry.

US Pat. No. 10,217,709

FAN-OUT SEMICONDUCTOR PACKAGE

Samsung Electro-Mechanics...

1. A semiconductor package comprising:a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an insulating layer having openings exposing portions of the connection pads of the semiconductor chip;
interconnection members disposed in the openings of the insulating layer and attached to the connection pads of the semiconductor chip, respectively, lower surfaces of the interconnection members being coplanar with a lower surface of the insulating layer; and
a first connection member disposed on the active surface of the semiconductor chip,
wherein the first connection member includes a redistribution layer including conductive patterns electrically connected to the connection pads of the semiconductor chip at least through the interconnection members,
one of the conductive patterns of the redistribution layer is in physical contact with the lower surface of the insulating layer and a lower surface of one of the interconnection members, and extends from the lower surface of the insulating layer onto the lower surface of the one of the interconnection members, and
in a view along a direction perpendicular to the active surface of the semiconductor chip, a width of the one of the interconnection members is greater than a width of the one of the conductive patterns of the redistribution layer.

US Pat. No. 10,217,693

METHODS AND SYSTEMS FOR HIGH VOLTAGE COMPONENT COOLING IN ELECTRIC VEHICLE FOR FAST CHARGE

NIO USA, Inc., San Jose,...

1. A junction box of a vehicle, the junction box comprising:one or more relays;
one or more bus bars connected to one or more of the one or more relays;
one or more terminals that interconnect with a battery of the vehicle and one of the one or more relays; and
one or more phase change materials contained in one or more malleable plastic containers, wherein the one or more malleable plastic containers are attached to at least one of the relays, bus bars, and/or terminals, wherein the one or more phase change materials limit heat generation during a charging of a battery of the vehicle.

US Pat. No. 10,217,651

WASHING DEVICE

LG Display Co., Ltd., Se...

1. A washing device comprising:a plasma irradiating cleaner having a plasma irradiating unit and an air jetting unit spaced apart from the plasma irradiating unit, and configured to receive a substrate, the plasma irradiating unit further configured to remove dirt from the substrate by irradiating the substrate with plasma, and the air jetting unit having a first plurality of air output nozzles positioned adjacent to the plasma irradiating unit, the plurality of first air output nozzles configured to jet air upward against the substrate with sufficient force to assist to support the substrate in the plasma irradiating cleaner and position the substrate spaced apart from the plurality of first air output nozzles while the substrate is within the plasma irradiating cleaner;
a dirt washing assembly configured to receive the substrate from the plasma irradiating cleaner, having an upper dirt washing unit and a lower dirt washing unit separated by a space sized and dimensioned to receive the substrate and the upper and lower dirt washing units further configured to remove dirt remaining on the substrate, the upper and lower dirt washing units including a second plurality of air output nozzles positioned to jet air against the upper and lower surfaces of the substrate to assist to support the substrate in the dirt washing assembly and position the substrate spaced apart from the upper dirt washing unit and the lower dirt washing unit;
a finishing washing assembly configured to receive the substrate from the dirt washing assembly, and the finishing washing assembly further configured to wash the substrate;
a drying assembly configured to receive the substrate from the finishing washing assembly, and the drying assembly further configured to dry the substrate and to jet air upward against the substrate;
a substrate unloading assembly configured to receive the substrate from the drying assembly, and the substrate unloading assembly further configured to unload the substrate; and
a plurality of transfer rollers configured to transfer the substrate by applying a longitudinal force thereto, the plurality of transfer rollers comprising:
a first transfer roller mounted to transfer the substrate to the plasma irradiating cleaner, the first transfer roller being disposed outside the plasma irradiating cleaner;
a second transfer roller mounted between the plasma irradiating cleaner and the dirt washing assembly to transfer the substrate from the plasma irradiating cleaner to the dirt washing assembly, the second transfer roller being disposed outside the plasma irradiating cleaner;
a third transfer roller mounted between the dirt washing assembly and the drying assembly to transfer the substrate from the dirt washing assembly to the drying assembly; and
a fourth transfer roller mounted to the substrate unloading assembly to transfer the substrate from the drying assembly to the outside,
wherein the finishing washing assembly is disposed above the third transfer roller and there are no transfer rollers within the plasma irradiating cleaner or the dirt washing assembly.

US Pat. No. 10,217,618

CURRENT THRESHOLD RESPONSE MODE FOR ARC MANAGEMENT

Advanced Energy Industrie...

1. A power supply comprising:a power controller configured to apply DC or pulsed DC power to a plasma processing chamber;
an arc management portion including a non-transitory, tangible computer readable storage medium, encoded with processor readable instructions to extinguish one or more arcs in the plasma processing chamber, the instructions including instructions for:
detecting an arc in the plasma processing chamber;
reducing, responsive to detection of the arc, a voltage provided to the plasma processing chamber to at least one reduced level;
monitoring a current provided by the power controller to detect when the current falls to a current threshold that is a percentage of a steady state current being applied to the plasma processing chamber just before the arc, and where the current threshold is less than the steady state current; and
raising, from the at least one reduced level, the voltage provided to the plasma processing chamber when the current falls to the current threshold, thereby effecting a dynamic quench period having a duration dependent upon the current.

US Pat. No. 10,217,597

X-RAY GENERATOR AND X-RAY ANALYZER

RIGAKU CORPORATION, Toky...

1. An X-ray generator comprising:a cathode for generating electrons;
an anode provided facing the cathode, and provided with at least two X-ray generation zones lined up adjacent to one another;
a casing that has an interior space for accommodating the cathode and the anode and that is integral with the cathode;
a plurality of driving means for causing the anode to move with respect to the casing;
a plurality of guiding means for guiding the movement of the anode with respect to the casing; and
a seal member for keeping the interior space of the casing airtight, the center axis of the seal member extending in a direction parallel to the direction in which the two or more X-ray generation zones are lined up;
wherein the plurality of driving means are provided to different positions in the surface orthogonal to the center axis of the seal member;
the plurality of driving means are provided uniformly in relation to the center axis of the seal member;
the plurality of guiding means are provided to different positions in the surface orthogonal to the center axis of the seal member; and
the plurality of guiding means are provided uniformly in relation to the center axis of the seal member.

US Pat. No. 10,217,587

PULSE SOLENOID CONTROL CIRCUIT

WCM INDUSTRIES, INC., Co...

1. A method for controlling an electrically latching load, the method comprising:receiving a switch control signal in an on state;
providing an on input signal in response to receiving the switch control signal in the on state;
generating an on pulse control signal in response to the on input signal, the on pulse control signal having a first pulse duration;
in response to the on pulse control signal, providing an output on pulse to an output, wherein the output on pulse is configured to cause the electrically latching load to latch in an on position;
receiving a switch control signal in an off state;
providing an off input signal in response to receiving the switch control signal in the off state;
generating an off pulse control signal in response to the off input signal, the off pulse control signal having a second pulse duration, wherein at least one of the first pulse duration and the second pulse duration are adjustable duration based on an adjustable resistance configured to be adjusted by a jumper; and
in response to the off pulse control signal, providing an output off pulse to the output.

US Pat. No. 10,217,581

ACTUATION SYSTEM OF A VACUUM BOTTLE

SCHNEIDER ELECTRIC INDUST...

1. An actuation system of a vacuum bottle for an electrical connection device, the vacuum bottle including one movable electrode and one fixed electrode, the movable electrode being movable longitudinally between a closed position in which the two electrodes are in contact with each other and an open position in which the two electrodes are separated, the actuation system comprising:an adjusting nut linked to the movable electrode and capable of rotation so as to adjust a position of the adjusting nut in relation to the movable electrode and thereby to vary an instant at which the movable electrode begins a movement towards the open position;
a driving device acting on the adjusting nut for driving the movable electrode towards the open position;
a locking device for locking the position of the adjusting nut in relation to the movable electrode; and
a threaded collar and a sleeve, the sleeve being fixed to the movable electrode and driven by the threaded collar, the threaded collar being provided with an external thread engaging with an internal thread of the adjusting nut for adjusting the position of the adjusting nut in relation to the movable electrode.

US Pat. No. 10,217,563

METHOD OF MANUFACTURING MULTI-LAYER COIL AND MULTI-LAYER COIL DEVICE

CYNTEC CO., LTD., Hsinch...

1. A method of manufacturing a multi-layer coil comprising:providing a substrate;
forming a seed layer on the substrate, wherein the seed layer comprises a plurality of winding turns of a conductive wire, wherein each two adjacent winding turns of the conductive wire are separated by a gap; and
plating N metal layers on the seed layer to encapsulate the plurality of winding turns of the conductive wire to form a multi-layer coil with N different current densities respectively, N being a positive integer not less than 3, wherein each metal layer is in contact with a different area of the top surface of the substrate to encapsulate a corresponding winding turn of the conductive wire, wherein the current density used for plating each metal layer increases as the level of the metal layer increases, and the current density difference between each two adjacent metal layers decreases as the level of the metal layer increases.

US Pat. No. 10,217,555

COMPACT INDUCTOR

Rockwell Automation Techn...

1. An inductor comprising:a first planar core with a first core thickness along a first axis orthogonal to a plane of the first planar core;
a second planar core disposed parallel to the first planar core with a second core thickness along the first axis; and
three electrical windings comprising insulated electrical wires and disposed between and adjacent to an inside plane of the first planar core and an inside plane of the second planar core so that so that a magnetic axis region of each of the three electrical windings overlaps a portion of each other magnetic axis region of each other electrical winding, wherein the electrical windings are disposed adjacent to other electrical windings and orthogonal to a plane substantially parallel to a first axis and each electrical winding crosses at least one other electrical winding with a crossover bend, wherein no magnetic teeth are disposed between the first planar core and the second planar core and the first axis is parallel to a magnetic axis of each electrical winding.

US Pat. No. 10,217,554

BISTABLE ELECTROMAGNETIC ACTUATOR DEVICE

ETO Magnetic GmbH, Stock...

1. A bistable electromagnetic actuator device, comprising:a permanent magnet means (12; 12a, 12b), as well as an armature unit (18) with an elongate plunger unit (10) extending along a moving direction,
wherein said armature unit can be moved into at least one of two end and/or stop positions that are stable in the deenergized state by means of stationary electromagnetic driving means (22),
wherein stationary magnetic field detector means (34; 34a, 34b) are positioned relative to a housing (20), which at least sectionally encloses the armature unit, for contactless interaction with the permanent magnet means in at least one of the end or stop positions provided for armature position detection,
wherein the plunger unit features a terminal contact and/or engagement section (28) for interacting with an actuating partner such that contact and/or actuation by the actuating partner causes a motion of the armature unit into one of the end or stop positions, in which the armature unit remains in a stable fashion in the deenergized state, when the electromagnetic driving means are deactivated,
wherein the magnetic field detector means are arranged and wired for generating and outputting a detector signal corresponding to this end or stop position,
wherein the driving means are realized in the form of a stationary coil unit that is provided on or in the housing and assigned a stationary core unit, which forms a stopping face (26) for a stopping section of the armature unit, and
wherein the plunger unit (10) extends into and is guided in the core unit or through the core unit.

US Pat. No. 10,217,537

CONTAINER FOR RADIOACTIVE WASTE

HOLTEC INTERNATIONAL

1. A radioactive waste container system comprising:a canister having an interior chamber for holding radioactive waste and an open top;
a lid assembly comprising:
a confinement lid having a top surface and a bottom surface opposite the top surface, the confinement lid coupled to the canister and closing the open top of the canister with the bottom surface of the confinement lid facing the interior chamber; and
a lifting lid including a lifting attachment, the lifting lid detachably coupled to the confinement lid and concealing the top surface of the confinement lid; and
wherein the lifting lid is configured to be detached from the confinement lid while the confinement lid remains coupled to the canister.

US Pat. No. 10,217,465

WEARABLE DEVICE, SYSTEM AND METHOD FOR NAME RECOLLECTION

Sony Corporation, Tokyo ...

1. A wearable device worn by a first person comprising:a sensor adapted for sensing a predefined movement of a body part of the first person, wherein the predefined movement of the body part is a greeting movement performed by the first person when greeting a second person;
a controller unit adapted for sampling and processing data received from the sensor in order to detect the movement of the body part, wherein the controller unit is configured to generate a trigger signal to trigger a voice recording of the second person upon detection of the movement of the body part of the first person;
a microphone arranged for capturing the voice recording of the second person upon reception of the trigger signal from the controller unit, wherein the capturing renders the voice recording;
a processor adapted for performing voice profiling and speech recognition on the voice recording of the second person, wherein the voice profiling renders a voice profile for the second person based on the voice recording of the second person, wherein the speech recognition renders a name spoken by the second person when being greeted by the first person, and wherein the voice profile of the second person that was rendered and the name of the second person that was rendered are associated together and stored in a database comprising a plurality of voice profiles and their respective associated names; and
a name presentation device configured to present the name of the second person out of the names stored in the database based on matching a later created voice profile based on a later captured voice with a previously stored voice profile of the second person out of the plurality of voice profiles stored in the database.