US Pat. No. 10,340,369

TUNNELING FIELD EFFECT TRANSISTOR

GLOBALFOUNDRIES Inc., Gr...

1. A tunneling field effect transistor device comprising a drain region, a source region and a gate region, the device comprising:a semiconductor substrate;
a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above said substrate, said body having an axis that is oriented substantially perpendicular to an upper surface of said substrate, said body having two side surfaces and an upper surface, said body extending a full length of said drain region, said gate region and said source region, wherein said first semiconductor material is part of said drain region;
a second semiconductor material positioned above at least a portion of said gate region and above said source region, wherein said second semiconductor material defines said channel region;
a third semiconductor material positioned above said second semiconductor material and above at least a portion of said gate region and above said source region, said third semiconductor material being doped with a second type of dopant material that is opposite to said first type of dopant material, wherein said third semiconductor material is part of said source region; and
a gate structure positioned above said first, second and third semiconductor materials in said gate region, wherein said gate structure includes a gate insulation layer and said third semiconductor material has an uppermost surface having a height greater than a height of an uppermost surface of said gate insulation layer.

US Pat. No. 10,340,368

FIN FORMATION IN FIN FIELD EFFECT TRANSISTORS

International Business Ma...

1. A method of forming a semiconductor device, the method comprising:forming a plurality of fins from a first material;
depositing a semiconductor layer formed from a second material over the plurality of fins;
depositing dielectric material covering the plurality of fins and the semiconductor layer, the dielectric material defining dielectric regions; and
diffusing the second material from the semiconductor layer into an entirety of each fin of the plurality of fins.

US Pat. No. 10,340,367

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:forming a spacer layer over a dummy gate, formed over a first portion of a fin structure, and a second portion of the fin structure;
forming a dielectric layer over the spacer layer;
removing the dielectric layer and the spacer layer formed over the dummy gate to expose the first portion of the fin structure;
forming a gate stack over the exposed first portion of the fin structure;
forming trenches by removing the dielectric layer formed over a remaining portion of the spacer layer and a portion of a height of the fin structure underneath the dielectric layer; and
forming source and drain contacts by filling the trenches with a metal.

US Pat. No. 10,340,366

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device including a Fin FET, the method comprising:forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, a part of the upper layer being exposed from an isolation insulating layer;
forming a dummy gate structure over a part of the fin structure, the dummy gate structure extending in a second direction crossing the first direction;
removing the dummy gate structure and forming a gate structure in a region in which the dummy gate structure is removed;
forming an interlayer dielectric layer over the fin structure and the gate structure;
forming a contact hole in the interlayer dielectric layer so that a part of the fin structure is exposed;
forming a source/drain structure on the exposed fin structure;
directly depositing a cap layer, by using a first gas and a second gas, on the source/drain structure, the cap layer covering a bottom surface and sidewalls of the contact hole;
forming a dielectric layer over the cap layer; and
forming a contact metal layer over the dielectric layer.

US Pat. No. 10,340,365

METHOD OF MANUFACTURING A THIN FILM TRANSISTOR

SHENZHEN CHINA STAR OPTOE...

1. A method of manufacturing a thin film transistor, comprising:providing a substrate;
depositing a buffer layer on the substrate and patterning the buffer layer, so as to form an active area of a thin film transistor;
sequentially depositing an insulation layer and a first metal layer on the substrate;
coating a photoresist on a gate region and a lightly doped region of the first metal layer, wherein the gate region and the lightly doped region are covered by a projection of the active area on the first metal layer;
metal etching the first metal layer excluding the gate region and the lightly doped region for exposing the insulation layer;
ashing the photoresist for exposing the lightly doped region of the first metal layer;
metal etching the first metal layer at the lightly doped region for forming a metal half tone mask;
implanting ions to the active area for forming a source region, a source lightly doped region, a channel region, a drain lightly doped region, and a drain region of the thin film transistor;
removing the photoresist;
depositing a media layer over the substrate, and forming a source through-hole and a drain through-hole on the media layer;
depositing a second metal layer over the substrate, and patterning the second metal layer, so as to form a source and a drain of the thin film transistor through the source through-hole and the drain through-hole;
depositing an organic planarization layer over the substrate, and forming a pixel electrode through-hole on the organic planarization layer; and
depositing a pixel electrode layer over the substrate, and patterning the pixel electrode layer, so as to form a corresponding pixel electrode through the pixel electrode through-hole;
wherein the step of depositing the buffer layer on the substrate and patterning the buffer layer, comprises:
depositing an amorphous silicon buffer layer on the substrate;
annealing the amorphous silicon buffer layer to form a polycrystalline silicon buffer layer; and
patterning the polycrystalline silicon buffer layer.

US Pat. No. 10,340,364

H-SHAPED VFET WITH INCREASED CURRENT DRIVABILITY

International Business Ma...

1. A method of forming a fin structure for a vertical field effect transistor (VFET), the method comprising the steps of:depositing a hardmask onto a substrate;
depositing a mandrel material onto the hardmask;
patterning the mandrel material along a first direction to form first mandrels;
forming first spacers alongside the first mandrels;
filling gaps between the first mandrels with additional mandrel material to form second mandrels in between the first mandrels;
patterning the first mandrels, the first spacers and the second mandrels along a second direction, wherein the second direction is perpendicular to the first direction;
forming second spacers, perpendicular to the first spacers, alongside the first mandrels and the second mandrels;
selectively removing the first mandrels and the second mandrels leaving behind a ladder-shaped pattern formed by the first spacers and the second spacers;
transferring the ladder-shaped pattern to the hardmask; and
transferring the ladder-shaped pattern from the hardmask to the substrate to form a first fin adjacent to a second fin, and at least one cross fin interconnecting the first fin and the second fin; and
cutting the ladder-shaped pattern in the substrate into individual fin structures, wherein cuts made during the cutting are located to form each individual fin structure comprising: a first cross fin interconnecting the first fin and the second fin at one end of the individual fin structure, and a second cross fin interconnecting the first fin and the second fin at another end of the individual fin structure in an O-shaped fin structure.

US Pat. No. 10,340,363

FABRICATION OF VERTICAL FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED BOTTOM INSULATING SPACERS

International Business Ma...

18. A semiconductor device, comprising:a vertical field effect transistor (FET) device on a semiconductor substrate, wherein the vertical FET device comprises:
a semiconductor fin formed on a recessed surface of a semiconductor substrate;
a lower source/drain region formed on the recessed surface of the semiconductor substrate in contact with a bottom portion of the semiconductor fin, wherein the lower source/drain region comprises a first type of epitaxial semiconductor material;
a self-aligned bottom insulating spacer formed on the lower source/drain region, the self-aligned bottom insulating spacer comprising an oxide layer formed from oxidation of a second type of epitaxial semiconductor material epitaxially grown on the lower source/drain region, which is different from the first type of epitaxial semiconductor material;
a gate structure formed in contact with sidewalls of the semiconductor fin;
an upper insulating spacer formed on the gate structure; and
an upper source/drain region formed on an upper portion of the semiconductor fin;
wherein the self-aligned bottom insulating spacer electrically insulates the lower source/drain region from the gate structure;
wherein the upper insulating spacer electrically insulates the upper source/drain region from the gate structure; and
wherein the first type of epitaxial semiconductor material comprises crystalline silicon germanium with a first concentration of germanium, and wherein the second type of epitaxial semiconductor material comprises crystalline silicon germanium with a second concentration of germanium that is greater than the first concentration of germanium.

US Pat. No. 10,340,362

SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS

GLOBALFOUNDRIES Inc., Gr...

1. A structure comprising:a semiconductor body having a top surface;
an epitaxial layer of semiconductor material on the semiconductor body;
a first gate structure on the semiconductor body, the first gate structure having a sidewall;
a first spacer adjacent to the sidewall of the first gate structure, the first spacer having a first section and a second section vertically between the first section and the top surface of the semiconductor body, the first section of the first spacer having a first thickness, and the second section of the first spacer having a second thickness different from the first thickness; and
a conformal layer on the first spacer and the epitaxial layer of semiconductor material,
wherein the second section of the first spacer is located between the epitaxial layer of semiconductor material and the sidewall of the first gate structure, the first spacer is composed of SiBCN having a first dielectric constant, and the conformal layer is composed of SiBCN having a second dielectric constant that is less than the first dielectric constant of the SiBCN of the first spacer.

US Pat. No. 10,340,361

FORMING OF A MOS TRANSISTOR BASED ON A TWO-DIMENSIONAL SEMICONDUCTOR MATERIAL

1. A MOS transistor manufacturing method, comprising the successive steps of:a) forming a first layer made of a conductive or semiconductor material on a surface of a support substrate;
b) forming a sacrificial gate on the upper surface of the first layer, and a second layer made of an insulating material laterally surrounding the sacrificial gate;
c) forming, on either side of the sacrificial gate, source and drain electric connection elements made of a conductive material, crossing the second layer and contacting the first layer;
d) removing the sacrificial gate and the portion of the first layer located vertically in line with the sacrificial gate;
e) depositing a third layer made of a two-dimensional semiconductor material on the sides and on the bottom of an opening formed at step d) by the removal of the sacrificial gate and of the first layer);
f) depositing a fourth layer made of an insulating material on the third layer; and
g) forming a conductive gate in the opening, on the fourth layer.

US Pat. No. 10,340,360

NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A nitride semiconductor device comprising:an electron transit layer including GaxIn1-xN (0 an electron supply layer formed on the electron transit layer and including AlaGabIncN (0?a?1, 0?b?1, 0?c?1 and a+b+c=1);
a gate insulating film formed to pass through the electron supply layer to contact the electron transit layer; and
a gate electrode facing the electron transit layer with the gate insulating film interposed therebetween,
wherein the gate insulating film includes an oxide of the electron supply layer.

US Pat. No. 10,340,359

GATE STRUCTURE WITH DUAL WIDTH ELECTRODE LAYER

GLOBALFOUNDRIES Inc., Gr...

1. A high-k dielectric metal gate (HKMG) transistor, comprising:a substrate;
an HKMG gate stack with a gate dielectric layer and a gate electrode layer positioned above said substrate, wherein said gate electrode layer has an upper portion and a lower portion;
a first liner contacting a sidewall portion of said upper portion;
a spacer contacting said first liner and a sidewall portion of said lower portion; and
raised source and drain regions adjacent said spacer, wherein a height of an uppermost surface of said spacer is greater than a height of an uppermost surface of said raised source and drain regions, and a width of said upper portion between said raised source and drain regions is smaller than a width of said lower portion between said raised source and drain regions.

US Pat. No. 10,340,356

LAMINATED ARTICLE

IDEMITSU KOSAN CO., LTD.,...

1. A laminated body comprising a substrate, an ohmic electrode layer, a metal oxide semiconductor layer, a Schottky electrode layer and a buffer electrode layer in this order, whereina reduction suppressing layer is provided between the Schottky electrode layer and the buffer electrode layer.

US Pat. No. 10,340,355

METHOD OF FORMING A DUAL METAL INTERCONNECT STRUCTURE

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming source/drain regions on opposite sides of at least one gate structure located over a channel region of a semiconductor fin;
forming a single interlevel dielectric (ILD) layer overlying the source/drain regions and the at least one gate structure;
forming source/drain contact trenches through the ILD layer, each of the source/drain contact trenches exposing at least a portion of one of the source/drain regions; and
forming a source/drain contact structure within each of the source/drain contact trenches, wherein each of the source/drain contact structures comprises a first contact conductor portion located at a bottom portion of each of the source/drain contact trenches and contacting one of the source/drain regions, and a second contact conductor portion overlying the first contact conductor portion, wherein the first contact conductor comprises a first metal and the second contact conductor portion comprises a second metal having a lower electromigration resistance and a lower electrical resistance than the first metal, and wherein each of the source/drain contact structures further comprises an elemental metal liner located on sidewalls of each of the source/drain contact trenches, a metal nitride liner located on the elemental metal liner and a bottom surface of each of the source/drain contact trenches, wherein the metal nitride liner contacts sidewalls and a bottommost surface of the first contact conductor portion, a contact liner located over the metal nitride liner and directly contacting a top surface of the first contact conductor portion, and an adhesion layer portion located on the contact liner and contacting sidewalls and a bottommost surface of the second contact conductor portion, wherein the elemental metal liner has a bottommost surface that is coplanar with a bottommost surface of the metal nitride liner.

US Pat. No. 10,340,354

MANUFACTURING METHOD OF THIN-FILM TRANSISTOR (TFT) ARRAY SUBSTRATE

BOE TECHNOLOGY GROUP CO.,...

1. A method of manufacturing a thin-film transistor (TFT) array substrate, comprising:forming a gate layer, a gate insulating layer, an oxide semiconductor layer, a source/drain electrode layer and a transparent conductive layer on a base substrate,
wherein the forming of the source/drain electrode layer and the transparent conductive layer includes:
forming a transparent conductive film and a first metallic film on the oxide semiconductor layer in sequence, to form a stack layer of the transparent conductive film and the first metallic film, in which the transparent conductive film contacts the oxide semiconductor layer;
forming source electrodes, drain electrodes and pixel electrodes by performing a single patterning process on the stack layer of the transparent conductive film and the first metallic film; and
forming a protective layer film on the first metallic film, and forming the pixel electrodes, the source electrodes, the drain electrodes, and the protective layer by performing a single patterning process on the transparent conductive film, the first metallic film, and the protective layer film;
wherein the protective layer film includes at least one of ITO IZO, IGZO, GZO, or carbon nanotube conductive films.

US Pat. No. 10,340,353

EPITAXIAL METALLIC TRANSITION METAL NITRIDE LAYERS FOR COMPOUND SEMICONDUCTOR DEVICES

The United States of Amer...

9. A semiconductor device, comprising:a substrate;
an epitaxial metal layer selected from the group consisting of TaNx, NbNx, WNx, MoNx, TMN ternary compounds, and combinations thereof; and
at least one epitaxial semiconductor layer comprising a semiconductor material selected from the group consisting of SiC or AlN;
wherein the in-plane lattice constants of the substrate, the epitaxial metal layer, and the epitaxial semiconductor layer are within 2% of one another; and
wherein the epitaxial metal layer is in direct contact with the substrate and the at least one epitaxial semiconductor layer is in direct contact with the epitaxial metal layer to form an epitaxial metal/semiconductor heterostructure, or the at least one epitaxial semiconductor layer is in direct contact with the substrate and the epitaxial metal layer is in direct contact with the at least one epitaxial semiconductor layer to form an epitaxial metal/semiconductor heterostructure.

US Pat. No. 10,340,352

FIELD-EFFECT TRANSISTORS WITH A T-SHAPED GATE ELECTRODE

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a field-effect transistor, the method comprising:forming a first dielectric layer on a semiconductor layer;
forming a second dielectric layer on the first dielectric layer;
forming a first opening extending vertically through the first dielectric layer and the second dielectric layer;
after the first opening is formed, laterally recessing the second dielectric layer relative to the first dielectric layer with a selective etching process so as to widen a first portion of the first opening extending vertically through the second dielectric layer relative to a second portion of the first opening extending vertically through the first dielectric layer;
after the second dielectric layer is laterally recessed, forming a gate dielectric layer on an area of a top surface of the semiconductor layer exposed through the first portion of the first opening in the first dielectric layer; and
after forming the gate dielectric layer, forming a gate electrode that includes a wide section in the first portion of the first opening and a narrow section in the second portion of the first opening,
wherein the narrow section of the gate electrode is in contact with the gate dielectric layer, and the gate dielectric layer is arranged between the narrow section of the gate electrode and the top surface of the semiconductor layer.

US Pat. No. 10,340,351

SEMICONDUCTOR DEVICE

ROHM CO., LTD, Kyoto (JP...

1. A semiconductor device comprising:a first conductivity type SiC substrate;
a first conductivity type epitaxial layer formed on a side of one surface of the SiC substrate;
a second conductivity type body region formed at a surface portion of the epitaxial layer;
a gate trench formed in the epitaxial layer so as to penetrate the body region from a surface of the epitaxial layer;
a gate insulating film formed on an inner surface of the gate trench; and
a gate electrode formed on the gate insulating film, wherein
the gate electrode is made of a same material as the body region.

US Pat. No. 10,340,350

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:an isolation layer on a substrate, the isolation layer having a first gate trench;
a gate dielectric layer in the first gate trench;
a tantalum nitride layer on the gate dielectric layer;
a tantalum oxynitride layer on the tantalum nitride layer;
an n type work function metal layer formed on the tantalum oxynitride layer in the first gate trench; and
a filling metal formed on the n type work function metal layer in the first gate trench;
wherein the tantalum oxynitride layer has a gradient oxygen concentration decreased from a top surface of the tantalum oxynitride layer toward the tantalum nitride layer.

US Pat. No. 10,340,349

METHOD OF FORMING SEMICONDUCTOR STRUCTURE

United Microelectronics C...

1. A method of forming a semiconductor structure, comprising:providing a substrate having a first area and a second area, wherein a first surface of the first area is lower than a second surface of the second area;
sequentially forming a first insulating layer, a first gate, a first dielectric layer and a first dummy gate on the first surface of the first area;
forming a second dielectric layer and a second dummy gate on the second surface of the second area;
forming an inter-layer dielectric layer around the first gate, the first dummy gate and the second dummy gate;
removing the first dummy gate and the second dummy gate, so as to form a first trench and a second trench in the inter-layer dielectric layer; and
filling a second gate and a third gate respectively in the first trench and the second trench,
wherein the method further comprises forming a fourth gate on the first surface at one side of the first gate, and the fourth gate and the first gate are formed simultaneously, and
wherein the method of forming the first gate, the first dummy gate, the second dummy gate and the fourth gate comprises:
sequentially forming a first insulating material layer and a first conductive layer on the substrate in the first area;
forming a first dielectric material layer on the first conductive layer in the first area and forming a second dielectric material layer on the substrate in the second area;
forming a second conductive layer on the first dielectric material layer and on the second dielectric material layer;
performing a first patterning step, so as to form a first stacked structure and a second stacked structure on the substrate in the first area, wherein the first stacked structure comprises the first insulating layer, the first gate, the first dielectric layer and the first dummy gate; and
performing a second patterning step, so as to form the second dielectric layer and the second dummy gate on the substrate in the second area, wherein during the second patterning step, a portion of the second stacked structure is simultaneously removed and the fourth gate remains.

US Pat. No. 10,340,346

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a drain layer of a first conductivity type extending in a first direction and a second direction crossing the first direction;
a drift layer of the first conductivity type formed on a surface that is one surface perpendicular to a third direction crossing the first direction and the second direction of the drain layer;
a base region of a second conductivity type formed on a surface of the drift layer;
a source region of the first conductivity type formed on a surface of the base region;
a plurality of trenches formed in an array in the first direction and the second direction, the plurality of trenches each reaching the drift layer through the base region along the third direction from a surface of the source region;
a base contact region of the second conductivity type formed along the second direction in a region in which the plurality of trenches do not contiguously exist along the second direction between the plurality of trenches along the first direction, the base contact region being formed in the source region to electrically connect the source region to the base region being separate from the plurality of trenches;
a plurality of gate regions each formed along an inner wall of corresponding one of the plurality of trenches, via an insulating film, inside the corresponding one of the plurality of trenches;
a plurality of field plate electrodes each formed in an adjacent from corresponding one of the gate regions, via the insulating film, inside the corresponding one of the plurality of trenches along the third direction, and formed longer than the corresponding one of the gate regions in the third direction;
a plurality of first source contacts each formed on the base contact region and the source region along the second direction between the plurality of trenches along the first direction, the first source contacts electrically connect the base contact region to the source region;
a plurality of second source contacts on each of the field plate electrode connected the corresponding one of the field plate electrodes;
a plurality of gate contacts on the corresponding one of the gate regions, electrically connected the corresponding gate region;
a first metal layer being connected to the base contact region and the source region via a first source contact, and being connected to corresponding one of the field plate electrodes via a second source contact;
a second metal layer being insulated via the insulating film from the first metal layer, and being connected to corresponding one of the gate regions via a gate contact; and
a third metal layer formed to be layered in the third direction of the first metal layer and the second metal layer, to be connected to the first metal layer and to be insulated from the second metal layer via the insulating film.

US Pat. No. 10,340,345

NITRIDE SEMICONDUCTOR EPITAXIAL WAFER AND FIELD EFFECT NITRIDE TRANSISTOR

SUMITOMO CHEMICAL COMPANY...

1. A nitride semiconductor epitaxial wafer, comprising:a substrate;
a GaN layer configured to be an electron transit layer provided over the substrate;
an AlGaN layer configured to be an electron feed layer provided over the GaN layer;
wherein the GaN layer comprises a wurtzite crystal structure, and a measured ratio c/a of the lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in the a-axis orientation of the GaN layer is not more than 1.6266 despite the application of lattice mismatch stresses at interfaces between the GaN layer and the substrate and the AlGaN layer, and
wherein the measured ratio c/a allows the occurrence of only negative charges on the surface of the GaN layer on which a two-dimensional electron gas is induced spatially due to the lattice mismatch stresses to suppress current collapse.

US Pat. No. 10,340,344

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Sumitomo Electric Industr...

1. A method for manufacturing a silicon carbide semiconductor device, comprising the steps of:preparing an intermediate substrate including one main surface and the other main surface opposite to the one main surface;
arranging a sodium blocking member as being in contact with the one main surface of the intermediate substrate;
annealing the intermediate substrate while the sodium blocking member is in contact with the one main surface; and
removing the sodium blocking member from the one main surface after the step of annealing the intermediate substrate,
the intermediate substrate including a silicon carbide substrate having a first main surface facing the one main surface and a second main surface opposite to the first main surface, which forms the other main surface of the intermediate substrate, a gate insulating film partially in contact with the first main surface of the silicon carbide substrate, and a source electrode in contact with the first main surface exposed through the gate insulating film, and
the sodium blocking member being composed of a material having a diffusion constant of sodium not greater than a diffusion constant of sodium into the silicon carbide substrate.

US Pat. No. 10,340,343

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a gate electrode over the semiconductor substrate;
a channel region between the semiconductor substrate and the gate electrode;
a pair of source/drain regions adjacent to two opposing sides of the channel region in a channel length direction; and
a threshold voltage adjusting region adjacent to two opposing sides of the channel region in a channel width direction, wherein the threshold voltage adjusting region and the channel region have the same doping type, and a depth of the threshold voltage adjusting region is greater than a depth of the pair of source/drain regions.

US Pat. No. 10,340,342

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising:a collection region;
a base region adjacent to the collection region;
an emission region adjacent to the base region, wherein the base region comprises:
a first base region; and
a second base region, wherein the collection region is located on a first side of the first base region, the second base region is located on a second side of the first base region opposite the first side of the first base region, the second base region is located between the emission region and the first base region, is adjacent to the emission region, and has a width smaller than the width of the first base region; and
a doped semiconductor layer on the emission region, wherein the width of the doped semiconductor layer is larger than the width of the emission region, a conductive type of the doped semiconductor layer is the same as a conductive type of the emission region.

US Pat. No. 10,340,341

SELF-LIMITING AND CONFINING EPITAXIAL NUCLEATION

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a semiconductor device, the method comprising:forming a fin in a substrate, the fin comprising a first semiconductor material;
depositing a spacer material on the fin;
recessing the spacer material so that a surface of the fin is exposed;
removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the first semiconductor material of the fin on the lateral sidewalls; and
depositing a second semiconductor material within the recess.

US Pat. No. 10,340,340

MULTIPLE-THRESHOLD NANOSHEET TRANSISTORS

International Business Ma...

1. A method of forming a semiconductor device, comprising:forming a stack of alternating layers of channel material and sacrificial material;
etching away the sacrificial material to free the layers of channel material;
forming a gate stack around the layers of channel material;
forming source and drain regions by epitaxially growing the source and drain regions from sidewalls of each layer of channel material; and
deactivating at least one layer of channel material by etching back the source and drain regions, such that the etched source and drain regions do not contact the at least one deactivated layer of channel material.

US Pat. No. 10,340,338

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a first surface;
an insulating isolation structure disposed at a side of the first surface and composed of an insulator having a first depth; and
a gate electrode,
the semiconductor substrate having a source region disposed in contact with the first surface, a drain region disposed in contact with the first surface, a reverse conductivity region disposed in contact with the first surface and having a second depth, a body region disposed in contact with the first surface so as to surround the source region, and a drift region disposed in contact with the first surface so as to surround the drain region and the reverse conductivity region and sandwich the body region between the source region and the drift region,
the source region, the drift region, and the drain region being of a first conductivity type,
the body region and the reverse conductivity region being of a second conductivity type which is opposite to the first conductivity type,
the reverse conductivity region being disposed between the source region and the drain region,
the insulating isolation structure being disposed between the drain region and the reverse conductivity region,
the gate electrode facing and being insulated from a portion of the body region which is sandwiched by the source region and the drift region,
the first depth being larger than the second depth.

US Pat. No. 10,340,337

DIODE STRUCTURE OF A POWER SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A power semiconductor device comprising a semiconductor body coupled to each of a first load terminal and a second load terminal, wherein the semiconductor body comprises:a drift region with dopants of a first conductivity type;
at least a diode structure configured to conduct a load current between the terminals and comprising an anode port electrically connected to the first load terminal and a cathode port electrically connected to the second load terminal;
a field stop region with dopants of the first conductivity type at a higher dopant concentration than the drift region, the field stop region being arranged between the cathode port and the drift region;
wherein the cathode port comprises:
first port sections with dopants of the first conductivity type and second port sections with dopants of a second conductivity type complementary to the first conductivity type, a transition between each of the second port sections and the field stop region forming a respective pn-junction that extends along a first lateral direction, wherein a diffusion voltage of a respective one of the pn-junctions in an extension direction perpendicular to the first lateral direction is greater than a lateral voltage drop laterally overlapping with the lateral extension of the respective pn-junction.

US Pat. No. 10,340,336

POWER SEMICONDUCTOR DEVICE HAVING FULLY DEPLETED CHANNEL REGIONS

Infineon Technologies AG,...

1. A power semiconductor device, comprising:a semiconductor body coupled to a first load terminal structure and a second load terminal structure;
an active cell field implemented in the semiconductor body and configured to conduct a load current;
a plurality of first cells and a plurality of second cells provided in the active cell field, each being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type;
wherein:
each first cell comprises a first mesa, the first mesa including: a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region;
each second cell comprises a second mesa, the second mesa including: a second port region having the second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region;
wherein the first channel region has the first conductivity type and wherein the second channel region has the second conductivity type;
each first cell is configured to induce a current path for charge carriers of the first conductivity type within the first channel region; and
each second cell is configured to induce an accumulation channel for charge carriers of the second conductivity type within the second channel region.

US Pat. No. 10,340,335

METHOD OF FORMING A SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A method of forming a semiconductor device, the method comprising:forming a trench in a semiconductor body at a first surface of the semiconductor body;
introducing first dopants into a first region at a bottom side of the trench by ion implantation;
subsequent to introducing the first dopants, forming a first filling material in the trench, wherein the first filling material is formed over the first region including the first dopants;
introducing second dopants into a second region at a top side of the first filling material, wherein introducing the second dopants into the second region includes introducing the second dopants into the first filling material at an entire top surface of the first filling material located at the top side of the first filling material, and introducing the second dopants is performed subsequent to forming the first filling material in the trench; and
thermal processing of the semiconductor body configured to intermix, within the first filling material, the first and the second dopants from the first and the second regions by a diffusion process along a vertical direction perpendicular to the first surface;
wherein the semiconductor body is a silicon carbide semiconductor body and the first and the second dopants comprise boron or gallium; and
wherein a ratio of a diffusion coefficient of the first and the second dopants in the first filling material and a diffusion coefficient of the first and the second dopants in the semiconductor body is greater than two with respect to a temperature of 1100° C.

US Pat. No. 10,340,334

SEMICONDUCTOR DEVICE INCLUDING AN LDMOS TRANSISTOR AND A RESURF STRUCTURE

Infineon Technologies AG,...

1. A semiconductor device, comprising:a semiconductor substrate having a bulk resistivity ??100 Ohm.cm, a front surface and a rear surface;
an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate; and
a RESURF (REduced SURface Field structure) structure comprising a doped buried layer arranged in the semiconductor substrate,
wherein the LDMOS transistor comprises a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type,
wherein the source region comprises a first well and a second well of the same second conductivity type,
wherein the first well is more highly doped than the second well,
wherein the first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.

US Pat. No. 10,340,333

III-NITRIDE POWER SEMICONDUCTOR DEVICE

Infineon Tecimologies Ame...

1. A power semiconductor device, comprising:a III-nitride heterojunction body that includes a first III-nitride body and a second III-nitride body having a different band gap than that of said first III-nitride body;
a first power electrode comprising a conductive material coupled to said second III-nitride body;
a second power electrode comprising said conductive material coupled to said second III-nitride body;
a gate arrangement including a gate electrode disposed between said first and said second power electrodes;
a conductive channel that includes a two-dimensional electron gas (2DEG) that in a conductive state includes a reduced charge region produced by an implanted region in said second III-nitride body under said gate electrode, wherein said reduced charge region is less conductive than regions of said 2DEG adjacent each side of said reduced charge region;
said implanted region having implanted charge in said second III-nitride body, said implanted charge configured to repel electrons in said 2DEG under and beyond edges of said gate electrode;
said reduced charge region extending beyond at least one of said edges of said gate electrode and comprising negative charge which repels negative carriers in a region below said gate arrangement, said conductive channel being devoid of said negative charge in said regions of said 2DEG adjacent each side of said reduced charge region.

US Pat. No. 10,340,331

METHODS OF FORMING AN ARRAY OF CAPACITORS, METHODS OF FORMING AN ARRAY OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR, ARRAYS OF CAPACITORS, AND ARRAYS OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR

Micron Technology, Inc., ...

1. A method of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor, comprising:forming elevationally-extending transistors over columns of data/sense lines, individual of the transistors comprising a lower source/drain region directly electrically coupled to one of the data/sense lines, the transistors comprising rows of access lines above the data/sense lines, individual of the access lines extending laterally across and operatively laterally adjacent a lateral side of transistor channels and interconnecting the transistors in that row;
forming elevationally-extending and longitudinally-elongated capacitor electrode lines, individual of the capacitor electrode lines being common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed longitudinally along a line of the transistors;
forming a capacitor insulator over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines and over the tops of the individual capacitor electrode lines;
forming an elevationally-extending conductive line over the capacitor insulator longitudinally along each of a pair of laterally-opposing sides of the individual capacitor electrode lines, individual of the conductive lines on one of the laterally-opposing sides of the individual capacitor electrode lines being directly electrically coupled to upper source/drain regions of individual transistors longitudinally along that line of transistors, laterally-extending conductive material atop the capacitor insulator that is over the tops of the respective individual capacitor electrode lines directly electrically coupling together the conductive lines that are along each of a pair of laterally-opposing sides of the respective individual capacitor electrode lines; and
cutting laterally through the conductive lines on each of the laterally-opposing sides of the individual capacitor electrode lines and through the laterally-extending conductive material to form spaced individual other of the two capacitor electrodes of the individual capacitors, the cutting forming individual of the other capacitor electrodes to comprise an elevationally-extending first member directly electrically coupled to and extending elevationally upward from the upper source/drain regions of the individual transistors longitudinally along that line of transistors on the one laterally-opposing side of the individual capacitor electrode lines, the cutting forming individual of the other capacitor electrodes to comprise an elevationally-extending second member laterally spaced from the first member on the other laterally-opposing side of the individual capacitor electrode lines, and the cutting forming the laterally-extending conductive material as part of the spaced individual other of the two capacitor electrodes of the individual capacitors.

US Pat. No. 10,340,330

PRECISION BEOL RESISTORS

International Business Ma...

1. A semiconductor structure comprising:a lower interconnect level including first metal-containing structures embedded within a first interconnect dielectric material layer;
an upper interconnect level located above the lower interconnect level and comprising second metal-containing structures embedded within a second interconnect dielectric material layer;
a resistor present in the upper interconnect level, wherein the resistor has a bottommost surface that is coplanar with a topmost surface of the first interconnect dielectric material layer and a topmost surface that is located entirely beneath a topmost surface of the second interconnect dielectric material layer; and
a continuous dielectric cap located directly on an entirety of the topmost surface of the resistor, directly on a topmost surface of the second interconnect dielectric material layer, and directly on a topmost surface of the second metal-containing structures.

US Pat. No. 10,340,329

DISPLAY PANEL INCLUDING POWER SUPPLY COMPENSATION FILM HAVING REDUCED SHEET RESISTANCE ARRANGED ON OPPOSITE SURFACE OF SUBSTRATE FROM POWER SUPPLY LINE LAYER

Shanghai Tianma Micro-Ele...

1. A display panel, comprising:a substrate, a power supply line layer and a power supply compensation film, wherein the power supply compensation film is arranged on a back surface of the substrate, the power supply line layer is arranged on a front surface of the substrate, and the back surface of the substrate is a surface opposite to a light emitting surface of the display panel;
the display panel comprises:
a display area and a non-display area surrounding the display area, and the non-display area comprises a first frame area and a second frame area positioned on two opposite sides of the display area;
the power supply line layer comprises:
a first power supply line arranged in the first frame area and the second frame area, and a plurality of second power supply lines arranged in the display area, and the first power supply line is electrically connected with the plurality of second power supply lines; and
the power supply compensation film is electrically connected with the first power supply line, and a sheet resistance of the power supply compensation film is smaller than a sheet resistance of the power supply line layer.

US Pat. No. 10,340,328

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a first layer having a first surface and a second surface, the second surface being an opposite side surface of the first surface of the first layer, the first layer arranged with a plurality of pixels on the first surface of the first layer, the plurality of pixels having a display element including a transistor and a first wiring connected to the transistor;
a second layer having a third surface, the third surface facing the second surface;
a first contact hole reaching the first surface from the second surface;
a first electrode arranged in the first contact hole;
a second contact hole arranged in the second layer;
a second electrode arranged in the second contact hole;
a third contact hole arranged in the second layer; and
a third electrode arranged in the third contact hole, wherein
the transistor is located without overlapping the first wiring in a plan view,
at least a part of the first wiring is located directly on the first contact hole,
the first wiring and the first electrode are connected,
the first electrode reaches the first surface from the second surface,
the first electrode and the second electrode are electrically connected, and
the second electrode and the third electrode are electrically connected.

US Pat. No. 10,340,324

ORGANIC LIGHT-EMITTING DIODE DISPLAY

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting diode (OLED) display, comprising:a substrate;
a scan line formed over the substrate and configured to provide a scan signal;
a data line crossing the scan line and configured to provide a data voltage;
a driving voltage line crossing the scan line and configured to provide a driving voltage;
a switching transistor electrically connected to the scan line and the data line;
a driving transistor electrically connected to the switching transistor and including a driving gate electrode and a driving channel overlapping each other in a depth dimension of the OLED display;
a first storage capacitor overlapping the driving channel in the depth dimension and including a first lower storage electrode and a portion of the driving voltage line;
a second storage capacitor separated from the first storage capacitor, overlapping the portion of the driving voltage line in the depth dimension, and including a second lower storage electrode and a second upper storage electrode overlapping the second lower storage electrode in the depth dimension, wherein the second upper storage electrode is formed on the same layer as the first lower storage electrode; and
an OLED electrically connected to the driving transistor.

US Pat. No. 10,340,291

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate including a main surface and a back surface;
a first semiconductor region of a first conductivity type formed in the semiconductor substrate;
a first active region and a second active region whose peripheries are defined by an element isolation region, in the first semiconductor region;
a first semiconductor layer formed on the main surface of the semiconductor substrate via a first insulating film, in the first active region;
a first gate electrode formed on a surface of the first semiconductor layer via a first gate insulating film;
a first sidewall spacer formed on a side wall of the first gate electrode;
first epitaxial layers formed on the first semiconductor layer at both sides of the first gate electrode;
a second semiconductor region and a third semiconductor region of a second conductivity type formed in the first semiconductor layer and the first epitaxial layers at both sides of the first gate electrode, the second conductivity type being a conductivity type opposite to the first conductivity type;
a fourth semiconductor region of the first conductivity type formed below the first insulating film, in the first active region;
a first silicide layer formed on a surface of the first semiconductor region, in the second active region;
an interlayer insulating film covering the first gate electrode; and
a first power supply wiring formed over the interlayer insulating film,
wherein, in a plan view, the second active region extends in a first direction,
wherein, in a plan view, the first power supply wiring extends in the first direction so as to overlap with the second active region,
wherein the first power supply wiring is connected to the second semiconductor region,
wherein the first gate electrode extends in a second direction perpendicular to the first direction, and lies on the element isolation region between the first active region and the second active region, and
wherein the first silicide layer is connected to the first power supply wiring.

US Pat. No. 10,340,282

SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF

United Microelectronics C...

1. A semiconductor memory device, comprising:a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction;
a plurality of shallow trench isolation (STI) structures, disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions;
a selection gate line, extending along a second direction and crossing over the cell regions and the STI structures; and
a control gate line, adjacent to the selection gate line in parallel extending along the second direction, also crossing over the cell regions and the STI structures, wherein the selection gate line and the control gate line together form a two-transistor (2T) memory cell.

US Pat. No. 10,340,275

STACKABLE THIN FILM MEMORY

Intel Corporation, Santa...

1. A memory, comprising:a thin film transistor over a first metal layer over a substrate, the thin film transistor comprising:
a thin film transistor layer having an upper surface and a lower surface;
a gate dielectric layer on the lower surface of the thin film transistor layer;
a gate electrode on the gate dielectric layer;
a source region on the upper surface of the thin film transistor layer; and
a drain region on the upper surface of the transistor layer; and
a memory element coupled to the thin film transistor.

US Pat. No. 10,340,247

METHOD FOR FORMING HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device structure, comprising:forming a first conductive material in a first polymer material in a first wafer;
forming a second conductive material in a second polymer material in a second wafer;
hybrid bonding the first wafer and the second wafer to form a hybrid bonding structure, wherein the hybrid bonding structure comprises a metallic bonding interface and a polymer-to-polymer bonding structure; and
forming at least one through-substrate via (TSV) through the second wafer, wherein the TSV extends from a bottom surface of the second wafer to a metallization structure of the first wafer, wherein the metallization structure is in direct contact with the polymer-to-polymer bonding structure.

US Pat. No. 10,340,235

SEMICONDUCTOR PACKAGE WITH THREE-DIMENSIONAL ANTENNA

MEDIATEK INC., Hsin-Chu ...

1. A semiconductor package, comprising:a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region;
a semiconductor die disposed on the package substrate in the first region;
a conductive shielding element disposed on the package substrate and covering the semiconductor die; and
a three-dimensional (3D) antenna, comprising:
a planar structure portion disposed on the package substrate in the second region; and
a bridge structure portion above the planar structure portion and connected thereto,
wherein the first bar pattern has an end in the first region to serve as a feeding point of the 3D antenna, and
wherein the conductive shielding element has an opening formed in a sidewall thereof, such that the first bar pattern passes through the conductive shielding element via the opening.

US Pat. No. 10,340,232

WIRING SUBSTRATE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate comprising:a coil wiring;
a magnetic layer that is in contact with a lower surface of the coil wiring, wherein the magnetic layer includes an opening extending through in a thickness-wise direction;
a first insulation layer covering the coil wiring, an upper surface of the magnetic layer, and a wall surface of the opening; and
a signal wiring structure that transmits a signal of a semiconductor element in the wiring substrate when the semiconductor element is mounted on the wiring substrate, wherein the signal wiring structure is formed so that the signal of the semiconductor element travels through the opening of the magnetic layer, wherein
the signal wiring structure includes
a first wiring portion located on an upper surface of the first insulation layer, and
a first via wiring located inward from the opening of the magnetic layer and connected to the first wiring portion, wherein
the first insulation layer includes an opening extending through in the thickness-wise direction and located inward from the opening of the magnetic layer,
the first via wiring is filled in the opening of the first insulation layer,
the first insulation layer is filled in a gap between the first via wiring and the wall surface of the opening of the magnetic layer, and
the magnetic layer is not in contact with the signal wiring structure.

US Pat. No. 10,340,212

SEMICONDUCTOR PACKAGE STRUCTURE HAVING A HEAT DISSIPATION STRUCTURE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor substrate, comprising:a dielectric layer having a surface;
a heat dissipation structure surrounded by the dielectric layer, the heat dissipation structure defining a space and including a liquid in the space; and
a first patterned conductive layer disposed adjacent to the surface of the dielectric layer and thermally connected with the heat dissipation structure.

US Pat. No. 10,340,195

METHOD TO CO-INTEGRATE SIGE AND SI CHANNELS FOR FINFET DEVICES

STMICROELECTRONICS, INC.,...

1. A device, comprising:a substrate;
an array of n-type fins extending from a surface of the substrate, the n-type fins including a first semiconductor material having n-type conductivity;
an array of p-type fins extending from the surface of the substrate, the array of p-type fins being adjacent to the array of n-type fins, the p-type fins including a second semiconductor material that is different from the first semiconductor material, the second semiconductor material having p-type conductivity; and
an insulator on the surface of the substrate, the insulator separating adjacent fins from one another.

US Pat. No. 10,340,177

DEVICES AND METHODS OF REDUCING DAMAGE DURING BEOL M1 INTEGRATION

GLOBALFOUNDRIES Inc., Gr...

1. A method comprising:obtaining a wafer comprising at least one contact region and at least one etch stop layer disposed directly on a substrate of the wafer;
depositing directly on the wafer a thin film stack comprising at least one first dielectric layer disposed directly on the wafer, at least one second dielectric layer disposed directly on the at least one first dielectric layer, at least one hard mask layer disposed directly on the at least one second dielectric layer, wherein the at least one hard mask layer is an amorphous silicon (a-Si) layer, and at least one third dielectric layer disposed directly on the at least one hardmask layer, wherein the at least one second dielectric layer and the at least one third dielectric layer comprise silicon oxynitride;
performing lithography to pattern at least one opening;
performing lithography to pattern at least one via opening and at least one trench opening and removing the at least one third dielectric layer;
removing the at least one hard mask layer such that no hard mask remains;
performing metallization over the wafer with no liner in the at least one opening, the at least one via opening, and the at least one trench opening; and
planarizing the wafer, wherein planarizing includes removing the at least one second dielectric layer.

US Pat. No. 10,340,176

SUBSTRATE MOUNTING METHOD AND SUBSTRATE MOUNTING DEVICE

TOKYO ELECTRON LIMITED, ...

8. A substrate mounting device comprising:a mounting table; and
a plurality of projections configured to protrude from a substrate-mounting surface of the mounting table and to support a substrate,
wherein the substrate is mounted on the mounting table by descending the plurality of projections toward the mounting table,
wherein an operation of descending the plurality of projections is halted after at least a portion of the substrate is brought into contact with the substrate-mounting surface, and the operation of descending the plurality of projections is resumed after the operation of descending the plurality of projections is halted.

US Pat. No. 10,340,137

MONOLAYER FILM MEDIATED PRECISION FILM DEPOSITION

TOKYO ELECTRON LIMITED, ...

1. A method of forming a thin film, comprising:forming a functionalized surface by treating at least a portion of an exposed surface on a substrate with an adsorption-promoting agent to alter a functionality of the exposed surface and cause subsequent adsorption of an organic precursor;
thereafter, adsorbing the organic precursor to the functionalized surface to form a carbon-containing film; and
forming a mixed film by exposing at least a portion of a surface of the carbon-containing film to an ion flux to mix the carbon-containing film with a material of the substrate, wherein the material of the substrate is located underneath the carbon-containing film.

US Pat. No. 10,340,133

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A method for fabricating a semiconductor device comprising:forming a silicon oxide film having at least one opening, on a silicon substrate;
forming a structural member formed of a material less prone to be etched by hydrofluoric acid than said silicon oxide film, said structural member being provided on said silicon oxide film and reaching said silicon substrate in said opening; and
performing wet etching using hydrofluoric acid, on said silicon substrate on which said silicon oxide film and said structural member are provided, an interface between said silicon oxide film and said structural member being exposed to hydrofluoric acid in said performing wet etching,
wherein
said structural member includes an insulation film,
an interface between said silicon oxide film and said insulation film is exposed to hydrofluoric acid in said performing wet etching, and
performing said wet etching results in a portion of an upper surface of said silicon oxide film to one side of said opening being etched, and another portion of said upper surface of said silicon oxide film to another side of said opening not being etched.

US Pat. No. 10,340,088

THIN-FILM CAPACITOR

TDK CORPORATION, Tokyo (...

1. A thin-film capacitor comprising:a substrate made of a metal material;
a capacitor portion formed partially on one surface of the substrate, the capacitor having a stacked structure from stacking an electrode layer and a dielectric layer alternately;
an insulating layer covering a forming region and a non-forming region, the capacitor portion formed in the forming region and not formed in the non-forming region on the one surface of the substrate;
an electrode terminal disposed on the insulating layer; and
a via conductor configured to penetrate the insulating layer in a thickness direction of the insulating layer and connect the electrode terminal to one of the substrate and the electrode layer of the capacitor portion,
wherein: the substrate is divided into a plurality of parts by a penetration portion penetrating the substrate in a thickness direction of the substrate, and includes a frame portion along an outer edge of the substrate and an electrode portion located inside the frame portion when viewed from the other surface side of the substrate, the electrode portion facing the electrode layer of the capacitor portion through the dielectric layer of the capacitor portion; and
the frame portion includes a communicating channel that extends in a direction orthogonal to the thickness direction of the substrate to connect a frame inside and a frame outside.

US Pat. No. 10,340,083

ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. An electronic component that is able to be mounted on a mounting substrate including a pair of first edge portions that faces each other, and a pair of second edge portions that is perpendicular or substantially perpendicular to the pair of first edge portions and faces each other, the mounting substrate including a structure that allows at least any one of the electronic component, a first electronic component, and a second electronic component to be mounted thereon;the first electronic component including:
a first laminate including a plurality of first dielectric layers and a plurality of first inner electrode layers, which are laminated, a pair of first principal surfaces facing each other in a lamination direction, a pair of first side surfaces facing each other in a width direction perpendicular or substantially perpendicular to the lamination direction, and a pair of first end surfaces facing each other in a length direction perpendicular or substantially perpendicular to the lamination direction and the width direction; and
a pair of first external electrodes each extending from a corresponding one of the pair of first end surfaces to a portion of the pair of first principal surfaces and to a portion of the pair of first side surfaces;
the second electronic component including:
a second laminate including a plurality of second dielectric layers and a plurality of second inner electrode layers, which are laminated, a pair of second principal surfaces facing each other in a lamination direction, a pair of second side surfaces facing each other in a width direction perpendicular or substantially perpendicular to the lamination direction, and a pair of second end surfaces facing each other in a length direction perpendicular or substantially perpendicular to the lamination direction and the width direction; and
a pair of second external electrodes each extending from a corresponding one of the pair of second end surfaces to a portion of the pair of second principal surfaces and to a portion of the pair of second side surfaces; wherein
a dimension of the first electronic component in the length direction is designated as L1, a dimension of the first electronic component in the width direction is designated as W1, a dimension of the second electronic component in the length direction is designated as L2, and a dimension of the second electronic component in the width direction is designated as W2;
a length W3 of the pair of first edge portions is a least common multiple of the W1 and the W2; and
a length L3 of the pair of second edge portions is a least common multiple of the L1 and the L2;
the electronic component including:
a third laminate including a plurality of third dielectric layers and a plurality of third inner electrode layers, which are laminated, a pair of third principal surfaces facing each other in a lamination direction, a pair of third side surfaces facing each other in a width direction perpendicular or substantially perpendicular to the lamination direction, and a pair of third end surfaces facing each other in a length direction perpendicular or substantially perpendicular to the lamination direction and the width direction; and
a pair of third external electrodes each extending from a corresponding one of the pair of third end surfaces to a portion of the pair of third principal surfaces and to a portion of the pair of third side surfaces; wherein
a dimension of the electronic component in the width direction is any one of the W1 and the W2; and
a dimension of the electronic component in the length direction is the L2 when the dimension of the electronic component in the width direction is the W1; and
a dimension of the electronic component in the length direction is the L1 when the dimension of the electronic component in the width direction is the W2.

US Pat. No. 10,340,071

MAGNETIC CIRCUIT FOR CARRYING AT LEAST ONE COIL

1. A magnetic circuit for carrying at least one coil, the circuit comprising:at least one inner leg and at least two outer legs; and
a connecting part serving to guide the magnetic flux from the inner leg to each outer leg,
each outer leg having no non-magnetic gap and the inner leg being at least partially made from one or more materials that have a relative magnetic permeability that is lower than that of the material or materials of which the outer legs are formed,
each outer leg being made as a single piece in one and the same material from one outer leg to the other and the relative magnetic permeability of the material of a portion of the inner leg being lower than the relative magnetic permeability of the material of the outer legs,
the ratio between the relative magnetic permeability of the material of said portion of the inner leg and the relative magnetic permeability of the material of the outer legs being comprised between 0.001 and 0.033, and
wherein the inner leg comprises a plurality of successive transverse sections that are homothetic images of one another, having a ratio of less than one from one section to an adjacent section of the plurality of successive transverse sections with increasing proximity to the connecting part.

US Pat. No. 10,340,057

UNIFIED POWER AND DATA CABLE

CISCO TECHNOLOGY, INC., ...

1. A cable comprising:a data transmission path disposed about an axial center of the cable, the data transmission path including:
a plurality of insulated conductive paths, wherein the plurality of insulated conductive paths extend along a longitudinal axis of the cable; and
a divider that separates the plurality of insulated conductive paths from each other;
a power transmission path sheathing the data transmission path, wherein the power transmission path includes
a power layer that is a solid conductor plane as a current source path,
a ground layer that is a ground plane as a current return path for bidirectional power transmission, and
a dielectric layer located between the power layer and the ground layer, wherein a capacitance value of the power transmission path satisfies a threshold capacitance value within a predefined tolerance range at frequencies above a first frequency level based on a function of (A) a thickness of the dielectric layer that is less than a predetermined thickness threshold and (B) a permittivity value corresponding to a material of the dielectric layer that meets a predetermined permittivity threshold;
a shield layer located between the data transmission path and the power transmission path; and
a first connector terminating a first end of the cable and a second connector terminating a second end of the cable, wherein the first and the second connectors are configured to connect to first and second devices, respectively, for coupling the data transmission path between the first and the second devices for bidirectional data transmission and for coupling the power transmission path between the first and the second devices for redundant bidirectional power transmission.

US Pat. No. 10,340,017

ERASE-VERIFY METHOD FOR THREE-DIMENSIONAL MEMORIES AND MEMORY SYSTEM

MACRONIX INTERNATIONAL CO...

1. An erase-verify method for a three-dimensional (3D) memory, the 3D memory including at least one memory cell string including a plurality of memory cells, the memory cells including a first group of memory cells and a second group of memory cells, each of the memory cells coupled to a word line, the erase-verify method comprising:performing a first erase-verify operation on the first group of memory cells, wherein the first erase-verify operation comprises:
applying an erase-verify voltage to the word lines coupled to a first portion of the first group of memory cells and a first pass voltage to the word lines coupled to a second portion of the first group of memory cells in a first phase of the first erase-verify operation, the second portion of the first group of memory cells is different from the first portion of the first group of memory cells; and
after the first phase of the first erase-verify operation, applying the erase-verify voltage to the word lines coupled to the memory cells in the second portion of the first group of memory cells and the first pass voltage to the word lines coupled to the memory cells in the first portion of the first group of memory cells in a second phase of the first erase-verify operation; and
after performing the first erase-verify operation on the first group of memory cells, performing a second erase-verify operation on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully, wherein the second erase-verify operation comprises:
applying the erase-verify voltage to the word lines coupled to a first portion of the second group of memory cells and a second pass voltage to the word lines coupled to a second portion of the second group of memory cells in a first phase of the second erase-verify operation, the second portion of the second group of memory cells is different from the first portion of the second group of memory cells; and
after the first phase of the first erase-verify operation, applying the verify voltage to the word lines coupled to the second portion of the second group of memory cells and the second pass voltage to the word lines coupled to the first portion of the second group of memory cells in a second phase of the second erase-verify operation.

US Pat. No. 10,340,003

INPUT-PATTERN AWARE REFERENCE GENERATION SYSTEM AND COMPUTING-IN-MEMORY SYSTEM INCLUDING THE SAME

National Tsing Hua Univer...

1. An input-pattern aware reference generation system for a memory cell array having a plurality of word lines crossing a plurality of bit lines, the plurality of word lines being selectively activated by an input signal such that each of the plurality of bit lines generates a computational result of multiply-and-accumulate (MAC) computation, the system comprising:an input counting circuit, receiving the input signal of the memory cell array, discovering input activated word lines according to the input signal and generating a number signal representing a number of the input activated word lines;
a reference array, comprising a plurality of reference memory cells storing a predetermined set of weights; and
a reference word line control circuit, electrically connected between the input counting circuit and the reference array, the reference word line control circuit controlling the reference array to generate a plurality of reference signals being able to distinguish candidates of the computational result of the bit lines in the memory cell array according to the number signal.

US Pat. No. 10,340,002

IN-CELL DIFFERENTIAL READ-OUT CIRCUITRY FOR READING SIGNED WEIGHT VALUES IN RESISTIVE PROCESSING UNIT ARCHITECTURE

International Business Ma...

1. A resistive processing unit (RPU) device, comprising:a weight storage device configured to store a weight voltage which corresponds to a weight value of the RPU device;
a read transistor comprising a gate terminal, a first source/drain terminal, and a second source/drain terminal, wherein the gate terminal is connected to the weight storage device, wherein the first source/drain terminal is connected to a first control port of the RPU device, and wherein the second source/drain terminal is connected to a second control port of the RPU device; and
a current source connected to the second source/drain terminal of the read transistor, wherein the current source is configured to generate a fixed reference current;
wherein the read transistor is configured to generate a weight current in response to the weight voltage applied to the gate terminal of the read transistor;
wherein the RPU device is configured to output a read current from the second control port, wherein the read current comprises a magnitude and sign which represents a signed weight value of the RPU device;
wherein the magnitude of the read current is equal to a difference between the weight current generated by the read transistor and the fixed reference current of the current source;
wherein the sign of the read current is deemed positive when the weight current is greater than the fixed reference current; and
wherein the sign of the read current is deemed negative when the weight current is less than the fixed reference current.

US Pat. No. 10,340,000

OPERATING METHOD OF MEMORY DEVICE

Samsung Electronics Co., ...

1. An operating method of a memory device, comprising:determining a resistance Rdyn of a variable resistor of a memory cell and a variation ?Rdyn of the resistance Rdyn based on a statistical model;
determining an average resistance Rdyn_avg and a beta value of the variable resistor using the resistance Rdyn and the variation ?Rdyn of the resistance Rdyn;
determining a resistance Ra of an insertion resistor, connected in series between the memory cell and a power supply generator for generating a power supply voltage VPGM, using the average resistance Rdyn_avg and the beta value;
determining, using the resistance Ra, a level of the power supply voltage VPGM according to a target amount of heat generated in the memory cell; and
providing the level of the power supply voltage VPGM to the memory cell by using the power supply generator.

US Pat. No. 10,339,999

VARIABLE WIDTH MEMORY MODULE SUPPORTING ENHANCED ERROR DETECTION AND CORRECTION

Rambus Inc., Sunnyvale, ...

1. A memory module with an anterior module side and a posterior module side, the memory module comprising:a first memory component on the anterior module side;
a second memory component on the posterior module side;
a data-buffer component having:
a primary data link of a first data width;
a first secondary data link, of a second data width, coupled to the first memory component; and
a second secondary data link, of the second data width, coupled to the second memory component;
the data-buffer component to time-division multiplex data from the first memory component on the first secondary data link and the second memory component on the second secondary data link onto the primary data link.

US Pat. No. 10,339,998

APPARATUSES AND METHODS FOR PROVIDING CLOCK SIGNALS IN A SEMICONDUCTOR DEVICE

Micron Technology, Inc., ...

1. An apparatus comprising:a clock generating circuit configured to:
generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted relative to each other; and
generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode;
first, second, third and fourth buses on which the first, second, third and fourth clock signals are driven in the first mode; and
fifth and sixth buses on which the fifth and sixth clock signals are driven in the second mode, wherein each of the fifth and sixth buses is electrically decoupled from each of the first, second, third and fourth buses.

US Pat. No. 10,339,997

MULTI-PHASE CLOCK DIVISION

Micron Technology, Inc., ...

1. A semiconductor device comprising:memory;
a command interface configured to receive a write command to write data to the memory;
a data strobe pin configured to receive a data strobe to assist in writing the data to the memory; and
phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein the phase division circuitry comprises:
count detection circuitry configured to count bits received for a phase of the plurality of phases; and
phase detection circuitry configured to identify which phase of the plurality of phases received a pulse of the data strobe first.

US Pat. No. 10,339,996

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A semiconductor memory device, comprising:a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines;
a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks; and
a control logic configured to control the peripheral circuit, during the erase operation, to apply an erase permission voltage to the dummy word lines and the normal word lines for a preset time and to apply an erase prohibition voltage to the dummy word lines after the preset time,
wherein the preset time is determined based on Erase-Write (EW) cycling information and is determined regardless of a time for the erase operation, and
wherein the EW cycling information indicates a number of erase-write cycles of the selected memory block.

US Pat. No. 10,339,995

MEMORY DEVICE FOR CONTROLLING REFRESHING OPERATION

Samsung Electronics Co., ...

1. A memory device comprising:a plurality of memory cells; and
a self refresh controller configured to perform a refreshing cycle a plurality of times, the refreshing cycle including,
a burst refreshing operation performed during a first time interval, and
a power supply controlling operation performed during a second time interval, the second time interval being longer than the first time interval,
wherein the self refresh controller is configured to increase the second time interval in response to a deep sleep signal.

US Pat. No. 10,339,994

SEMICONDUCTOR DEVICE

Micron Technology, Inc., ...

1. An apparatus comprising:a row decoder configured to receive a refresh address and to selectively perform a row-copy operation, wherein during the row-copy operation data in a first word line corresponding to the refresh address is copied to a second word line in a same section of a memory as the first address, wherein the row decoder comprises a row-copy control circuit configured select a type of row-copy operation and to provide a source address corresponding to the first word line and a destination address corresponding to the second word line based on the type of row-copy operation, and wherein the row-cop control circuit is further configured to mark the region of the second word line where the data was copied as unusable for subsequent row-copy operations.

US Pat. No. 10,339,993

PERPENDICULAR MAGNETIC TUNNEL JUNCTION DEVICE WITH SKYRMIONIC ASSIST LAYERS FOR FREE LAYER SWITCHING

Spin Memory, Inc., Fremo...

1. A magnetic device, comprising:a first synthetic antiferromagnetic structure in a first plane having a magnetization vector that is perpendicular to the first plane and having a fixed magnetization direction;
an antiferromagnetic coupling layer in a second plane and disposed above the first synthetic antiferromagnetic structure;
a second synthetic antiferromagnetic structure in a third plane and disposed over the antiferromagnetic coupling layer;
a magnetic reference layer in a fourth plane and disposed over the second synthetic antiferromagnetic structure, the magnetic reference layer having a magnetization vector that is perpendicular to the fourth plane and having a fixed magnetization direction;
a non-magnetic tunnel barrier layer in a fifth plane and disposed over the magnetic reference layer;
a free magnetic layer disposed in a sixth plane over the non-magnetic tunnel barrier layer, the free magnetic layer having a magnetization vector that is perpendicular to the sixth plane and having a magnetization direction that can switch between a first magnetization direction to a second magnetization direction, the magnetic reference layer, the non-magnetic tunnel barrier layer and the free magnetic layer forming a magnetic tunnel junction; and
a skyrmionic enhancement layer disposed in a seventh plane over the free magnetic layer and being formed from a heavy metal with large spin-orbit coupling such that the skyrmionic enhancement layer induces a Dzyaloshinskii-Moriya interaction at an interface between the free magnetic layer and the skyrmionic enhancement layer thereby creating a non-collinear magnetic texture in the free magnetic layer near the interface.

US Pat. No. 10,339,992

SEMICONDUCTOR SYSTEM

SK hynix Inc., Icheon-si...

1. A semiconductor system comprising:a controller configured to provide a command clock, a data clock, an external command and an external address to a semiconductor memory device; and
the semiconductor memory device configured to transmit/receive external data to/from the controller and provide a read data strobe signal to the controller,
wherein the read data strobe signal comprises a first read data strobe signal and a second read data strobe signal, and
the semiconductor memory device transmits both of the first and second read data strobe signals to the controller or transmits one of the first and second read data strobe signals to the controller, based on an operation select signal.

US Pat. No. 10,339,991

MEMORY SYSTEM HAVING OPTIMAL THRESHOLD VOLTAGE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A semiconductor memory system comprising:a memory device; and
a memory controller including a sequence generator, a sequence analyzer, and a processor, the memory controller being coupled to the memory device and containing instructions for execution by the processor to
generate a training sequence, using the sequence generator, for analysis of user data, wherein the training sequence comprises a sequence of digital data that is randomly generated, has a length indicative of a level of accuracy of analysis and is known to the memory system,
write the training sequence with the associated user data to the memory device,
read out the training sequence and the associated user data,
analyze the training sequence, using the sequence analyzer, to understand characters of the user data and create an analysis result,
identify an optimal threshold voltage in accordance with the analysis result, and
use the optimal threshold voltage in an error correction coding process.

US Pat. No. 10,339,990

STROBE ACQUISITION AND TRACKING

RAMBUS INC., Sunnyvale, ...

1. A memory controller, comprising:an interface to receive a data strobe signal and corresponding read data, wherein the data strobe signal and the read data correspond to a read command issued by the memory controller, and wherein the read data is received in accordance with the data strobe signal;
a comparison circuit to determine a current timing offset between the data strobe signal and an internally generated data strobe enable signal, internally generated by the memory controller;
data receive circuitry, including gate logic to gate the data strobe signal with the internally generated data strobe signal to generate a clean data strobe signal, and data capture logic responsive to the clean data strobe signal to capture the read data; and
a circuit to dynamically determine a mode of operation of the memory controller in accordance with the determined current timing offset, wherein the mode of operation is selected from among a set of modes of operation that include a first mode of operation in which the memory controller synchronizes the internally generated data strobe enable signal with the received read data and data strobe signal, and a second mode of operation in which the memory controller maintains synchronization between the internally generated data strobe enable signal and the received read data and data strobe signal.

US Pat. No. 10,339,989

PAGE BUFFER, A MEMORY DEVICE INCLUDING THE SAME AND A READ OPERATION METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A page buffer, comprising:a pre-charge unit for pre-charging a bit line of a selected memory cell of a memory cell array via a first pre-charge line and pre-charging a sensing node via a second pre-charge line, wherein the bit line of the selected memory cell and the sensing node are pre-charged during a pre-charge time;
a bit line connection unit connected between the bit line and the sensing node and comprising a connecting node directly connected to the first pre-charge line, wherein the bit line connection unit controls a voltage of the sensing node, during a develop time, based on a bit line connection control signal and a sensing node voltage control signal, wherein the bit line connection unit includes a pair of transistors connected in series between the bit line and the sensing node, and wherein the connecting node is disposed between the pair of transistors; and
a data input and output unit for generating sensing data by sensing a level of the voltage of the sensing node, during a sensing time,
wherein the pre-charge unit comprises:
a bit line pre-charge transistor comprising a first terminal, a second terminal, and a gate terminal, wherein the first terminal receives a pre-charge voltage, the second terminal is connected to the connecting node, and the gate terminal receives a bit line pre-charge control signal; and
a sensing node pre-charge transistor comprising a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the second terminal of the bit line pre-charge transistor, the second terminal is connected to the sensing node, and the gate terminal receives a sensing node pre-charge control signal,
wherein the pre-charge unit controls a start time at which the bit line is pre-charged and a start time at which the sensing node is pre-charged to be different from each other, based on the bit line pre-charge control signal and the sensing node pre-charge control signal.

US Pat. No. 10,339,988

INPUT BUFFER CIRCUIT

Micron Technology, Inc., ...

1. An apparatus comprising:a first amplifier configured to be activated by a first power supply voltage to provide a first intermediate voltage on a first node and a second intermediate voltage on a second node;
a voltage switch configured to be activated by one of first and second precharge voltages from a third node; the voltage switch coupled to a fourth node; and
a second amplifier comprising first and second inverters coupled to the fourth node, the second amplifier configured to be activated by a second power supply voltage from the voltage switch to provide an output voltage when the voltage switch is activated, responsive to the one of the first and second precharge voltages,
wherein the first amplifier is configured to receive a data input signal and a reference voltage.

US Pat. No. 10,339,987

METHOD AND DEVICE FOR ADJUSTING HARDWARE REFRESH RATE OF TERMINAL

ZTE CORPORATION, Guangdo...

1. A method for adjusting a hardware refresh rate of a terminal, comprising:predicting a frame rate of currently operating software of the terminal in a future preset time period; and
adjusting the hardware refresh frequency of the terminal according to the predicted frame rate,
wherein the step of predicting the frame rate of the currently operating software of the terminal in the future preset time period comprises:
collecting at least one information of a real-time frame rate of the software, related information of a software graphic processing unit in the terminal and historical frame rate information of the software when operating in a foreground, the related information of the software graphic processing unit comprising: frequency information and load information of the software graphic processing unit; and
predicting the frame rate of the currently operating software of the terminal in the future preset time period according to at least one information of the real-time frame rate of the software, the related information of the software graphic processing unit and the historical frame rate information,
wherein;
the collecting at least one information of the real-time frame rate of the software, the related information of the software graphic processing unit in the terminal and the historical frame rate information of the software when operating in the foreground comprises:
collecting the related information of the software graphic processing unit in the terminal; and
the predicting the frame rate of the currently operating software of the terminal in the future preset time period according to at least one information of the real-time frame rate of the software, the related information of the software graphic processing unit and the historical frame rate information comprises:
judging a current frame rate scene of the software according to the frequency information and the load information; and
predicting the frame rate of the software in the future preset time period according to a judgment result.

US Pat. No. 10,339,986

DATA LATCH CIRCUIT AND PULSE SIGNAL GENERATOR THEREOF

DigWise Technology Corpor...

1. A pulse signal generator, comprising:a first buffer, receiving an input signal and a feedback signal, and generating a first buffering signal according to the input signal and the feedback signal;
a second buffer, receiving the input signal and the first buffering signal, and generating a second buffering signal according to the input signal and the first buffering signal;
a pull-up switch, coupled to an output end of the second buffer, receiving the first buffering signal, and pulling up the second buffering signal according to the first buffering signal; and
an output buffer, coupled to the first buffer and the second buffer, generating at least one output pulse signal according to the second buffering signal, the output buffer transmitting the at least one output pulse signal to the first buffer to be the feedback signal.

US Pat. No. 10,339,985

SENSE AMPLIFIER CONSTRUCTIONS

Micron Technology, Inc., ...

1. A sense amplifier construction comprising:a first n-type transistor and a second n-type transistor vertically offset above the first n-type transistor;
a third p-type transistor and a fourth p-type transistor vertically offset above the third p-type transistor;
a lower voltage activation line electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors; and
a higher voltage activation line electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.

US Pat. No. 10,339,984

DEVICE HAVING MULTIPLE CHANNELS WITH CALIBRATION CIRCUIT SHARED BY MULTIPLE CHANNELS

Micron Technology, Inc., ...

1. An apparatus comprising:a first output circuit;
a second output circuit; and
a calibration circuit coupled in parallel to the first output circuit and the second output circuit, the calibration circuit configured to perform a first calibration operation responsive to a first calibration command to produce a first calibration code, supply the first calibration code to the first output circuit responsive to a first latch command and supply the first calibration code to the second output circuit responsive to a second latch command.

US Pat. No. 10,339,983

TEMPERATURE-BASED MEMORY OPERATIONS

Micron Technology, Inc., ...

1. An apparatus, comprising:a memory device; and
a controller coupled to the memory device and configured to:
determine an operating temperature of the apparatus;
determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus, wherein the plurality of designated open blocks includes:
a first block corresponding to a first operating temperature range below a first temperature threshold;
a second block corresponding to a second operating temperature range above a second temperature threshold;
a third block corresponding to a third operating temperature range above the first temperature threshold and below the second temperature threshold; and
a fourth block corresponding to the third operating temperature range; and
write the data in the determined one of the plurality of designated blocks of the memory device.

US Pat. No. 10,339,982

MEMORY ELEMENTS AND CROSS POINT SWITCHES AND ARRAYS OF SAME USING NONVOLATILE NANOTUBE BLOCKS

Nantero, Inc., Woburn, M...

1. A circuit for routing electrical signals, said circuit comprising:a first plurality of wires;
a second plurality of wires; and
a plurality of nonvolatile nanotube block switches, wherein each nonvolatile nanotube block switch is in electrical communication with at least one wire of said first plurality of wires and at least one wire of said second plurality of wires, wherein each nonvolatile nanotube block switch is programmable to an on state and an off state, and wherein each nonvolatile nanotube block switch is dimensioned such that said on state has a resistance value suitable for electric signal flow between at least one wire of said first plurality of wires and at least one wire of said second plurality of wires.

US Pat. No. 10,339,981

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device comprising:a first nonvolatile semiconductor element;
a second nonvolatile semiconductor element;
a resistive element;
a controller that controls the first nonvolatile semiconductor element and the second nonvolatile semiconductor element;
a first signal line that connects the controller to the resistive element;
a second signal line that connects the resistive element to the first nonvolatile semiconductor element;
a third signal line that branches from the second signal line, the third signal line being connected to the second nonvolatile semiconductor element, at least one of the second signal line and the third signal line including a signal line formed on a first wiring layer and a signal line formed on a second wiring layer;
a connector that allows connection to an external device; and
a substrate on which the first nonvolatile semiconductor element, the second nonvolatile semiconductor element, the resistive element, the controller, and the connector are mounted, the first nonvolatile semiconductor element and the second nonvolatile semiconductor element being disposed symmetrically on opposite sides of the substrate, the substrate including:
a front surface layer that includes a wiring pattern formed on a front surface of the substrate, the front surface layer being a layer on which the first nonvolatile semiconductor element and the resistive element are mounted,
a rear surface layer that includes a wiring pattern formed on a rear surface of the substrate, the rear surface layer being a layer on which the second nonvolatile semiconductor element is mounted, and
a plurality of internal wiring layers that is provided between the front surface layer and the rear surface layer, the plurality of internal wiring layers including a wiring pattern, the first wiring layer being one of the plurality of internal wiring layers, the second wiring layer being one of the plurality of internal wiring layers, the second wiring layer being a different wiring layer from the first wiring layer.

US Pat. No. 10,339,980

APPARATUSES AND METHODS FOR CONTROLLING WORDLINES AND SENSE AMPLIFIERS

Micron Technology, Inc., ...

1. A memory array comprising:a column decoder circuit configured to provide bit line selections for the memory array;
a plurality of column selection lines coupled to the column decoder circuit; and
a plurality of bleeder transistors, each bleeder transistor configured to be coupled to a respective column selection line of the plurality of column selection lines,
wherein each bleeder transistor of the plurality of bleeder transistors further comprises:
a gate configured to receive a first voltage; and
a drain configured to receive a second voltage;
wherein the drain of each bleeder transistor is located along a word line direction of the memory array.

US Pat. No. 10,339,979

SECURE PROTECTION BLOCK AND FUNCTION BLOCK SYSTEM AND METHOD

Intel Corporation, Santa...

1. An apparatus comprising:power supply pins to couple to a power supply; and
a protection block, including a first transistor, to: (a) determine whether voltage from at least one of the power supply pins meets a predetermined condition, and (b) in response to determining whether the predetermined condition is met, communicate a first communication to at least one of first or second function blocks;
wherein the first function block, coupled to the protection block and the power supply pins, includes a second transistor and at least one fuse that corresponds to a security key;
wherein the first transistor has a first gate oxide breakdown voltage that is greater than a second gate oxide breakdown voltage of the second transistor;
wherein the protection block is configured such that when the voltage from at least one of the power supply pins exceeds the second gate oxide breakdown voltage but not the first gate oxide breakdown voltage, the protection block enters a secure mode of operation.

US Pat. No. 10,339,978

MULTI-SENSOR EVENT CORRELATION SYSTEM

BLAST MOTION INC., Carls...

1. A multi-sensor event correlation system comprising:at least one motion capture element configured to couple with a user or piece of equipment or mobile device coupled with the user, wherein said at least one motion capture element comprises
a sensor data memory;
a sensor configured to capture one or more values associated with an orientation, position, velocity, acceleration, angular velocity, and angular acceleration of said at least one motion capture element;
a first communication interface configured to receive communications, or one or more other values associated with an environmental sensor, a physiological sensor or both said environmental sensor and said physiological sensor or said communications and said one or more other values
or
at least one other sensor configured to locally capture said one or more other values associated with said environmental sensor, said physiological sensor or both said environmental sensor and said physiological sensor
or both said first communication interface and said at least one other sensor; and,
a microprocessor coupled with said sensor data memory, said sensor and said first communication interface, wherein said microprocessor is configured to
collect data that comprises sensor values that include said one or more values from said sensor;
store said data in said sensor data memory
or
analyze said data and recognize an event within said data to determine event data
or
store said data in said sensor data memory and analyze said data and recognize said event within said data to determine said event data; and,
transmit said data or said event data or both said data and said event data, and
process said communications
or
transmit said one or more other values associated with said environmental sensor, said physiological sensor or both said environmental sensor and said physiological sensor,
or
process said communications and transmit said one or more other values to
a computer, said computer comprising
a computer memory; and,
a second communication interface configured to communicate with said first communication interface to obtain
said data or said event data associated with said event or both said data and said event data
or
said one or more other values associated with said environmental sensor, said physiological sensor or both said environmental sensor and said physiological sensor
or both said data or said event data and
said one or more other values;
wherein said computer is coupled with said computer memory and is coupled with said second communication interface;
wherein said microprocessor is, or said computer is, or both said microprocessor and said computer are configured to
correlate said data or said event data with said one or more other values associated with said environmental sensor, said physiological sensor or both said environmental sensor and said physiological sensor to differentiate a first type of event with respect to a second type of event or a first type of activity with respect to a second type of activity or a first type of equipment with respect to a second type of equipment to determine at least one of
a type of event or true event or a false positive event selected from a plurality of types of events or
a type of equipment that said at least one motion capture element is coupled with selected from a plurality of types of equipment or
a type of activity indicated by said data or said event data selected from a plurality of types of activities.

US Pat. No. 10,339,977

INFORMATION PROCESSING APPARATUS DISPLAYING INDICES OF VIDEO CONTENTS, INFORMATION PROCESSING METHOD AND INFORMATION PROCESSING PROGRAM

KYOCERA CORPORATION, Kyo...

1. An information processing apparatus comprising:a memory configured to store video data;
a controller configured to generate first and second thumbnails by decoding respective portions of the video data; and
a display configured to display the first thumbnail or the second thumbnail,
wherein if a scroll instruction is received prior to completion of generation of the first thumbnail, the controller is configured to stop generating the first thumbnail and start generating the second thumbnail, and the display is configured to display the second thumbnail instead of the first thumbnail.

US Pat. No. 10,339,976

AUDIO DEVICE WHICH SYNCHRONIZES AUDIO DATA

Yamaha Corporation, Shiz...

1. An audio device which is configured to wirelessly receive audio data from another audio device, comprising:a memory which stores instructions and pulse data having a starting point and a predetermined length,
a clock which outputs an audio clock that indicates a timing of playback of the audio data, and
a processor that is configured to execute the instructions stored in the memory to:
wirelessly receive the audio data and a time stamp attached to the audio data from the other audio device,
output the pulse data having the starting point and the predetermined length in the audio device, the pulse data being output when the audio device receives the audio data,
detect start time of the pulse data based on the starting point by referring to the clock and end time of the pulse data by referring to the predetermined length and the start time,
compare the end time of the pulse data and the time stamp,
adjust the audio clock based on the comparing result, thereby adjusting the audio data, and
output the adjusted audio data synchronized with the other audio device, the adjusted audio data being output after the pulse data is output.

US Pat. No. 10,339,975

VOICE-BASED VIDEO TAGGING

GoPro, Inc., San Mateo, ...

1. A method for identifying an event of interest in a video, the method performed by a camera including one or more processors, the method comprising:accessing, by the camera, a captured speech pattern, the captured speech pattern captured from a user at a moment during capture of the video;
matching, by the camera, the captured speech pattern to a given stored speech pattern of multiple stored speech patterns, the multiple stored speech patterns corresponding to a command for identifying the event of interest within the video, individual ones of the multiple stored speech patterns stored based on a number of times the individual ones of the multiple stored speech patterns are captured by the camera from a user while the camera is operating in a training mode, wherein the individual ones of the multiple stored speech patterns correspond to an identification of the event of interest as occurring before, during, or after the moment; and
in response to matching the captured speech pattern to the given stored speech pattern, storing, by the camera, event of interest information associated with the video, the event of interest information identifying an event moment during the capture of the video at which the event of interest occurs, the event moment being determined to occur before, during, or after the moment based on the matching of the captured speech pattern to the given stored speech pattern.

US Pat. No. 10,339,974

AUDIO CONTROLLER DEVICE AND METHOD OF OPERATION THEREOF

MOTOROLA SOLUTIONS, INC.,...

1. An audio controller device, comprising:a memory for storing audio data;
a plurality of primary audio control interfaces; and
an electronic processor coupled to the primary audio control interfaces and the memory, the electronic processor configured to:
identify a plurality of audio segments from the audio data based on a plurality of contextual parameters associated with the audio data, wherein each of the plurality of audio segments includes a set of audio frames from the audio data, wherein each set of audio frames included in a respective one of the audio segments is uniquely identified by a combination of one or more of the contextual parameters;
associate each of the plurality of audio segments to a respective one of the primary audio control interfaces to enable each of the audio segments to be independently controlled through the respective one of the primary audio control interfaces to which the audio segment is associated; and
control a playback operation for all the audio frames included only in the respective one of the audio segments when an input is received at one or more of the primary audio control interfaces.

US Pat. No. 10,339,973

SYSTEM AND METHOD FOR AUDIO DUBBING AND TRANSLATION OF A VIDEO

International Business Ma...

1. A method of converting a first language of a soundtrack of a person speaking in a video to a second language, said method comprising:defining, by one or more processors of a computer system, outlines of shapes of mouth openings of the person speaking syllables of a word of the first language in the video;
translating, by the one or more processors of the computer system, a meaning of the word of the first language and locating one or more synonym words in the second language stored in a database of the computer system, said first and second languages being different languages;
comparing, by the one or more processors, outlines of the shapes of mouth openings of the one or more synonym words in the second language with the outlines of the shapes of mouth openings of the word of the first language; and
selecting, by the one or more processors, a synonym word of the one or more synonym words translated from the second language into the first language having mouth openings with a smallest difference from the mouth openings of the word of the first language.

US Pat. No. 10,339,972

SYSTEMS AND METHODS OF INTERACTIVE EXERCISING

OUTSIDE INTERACTIVE VISUA...

1. A computer system comprising:a memory;
at least one processor coupled to the memory; and
a user interface component executable by the at least one processor and configured to:
receive information from a sensor coupled to a user descriptive of a pace at which the user is exercising;
determine a playback speed for previously filmed video content captured contemporaneously with an audio component, the playback speed determined with reference to the pace at which the user is exercising;
present the video content at the playback speed;
generate a plurality of audio frames from the audio component, the plurality of audio frames being generated with reference to the pace at which the user is exercising; and
present the plurality of audio frames to the user.

US Pat. No. 10,339,971

SEQUENTIAL DATA STORAGE WITH REWRITE USING DEAD-TRACK DETECTION

International Business Ma...

1. A system, comprising:a magnetic head having a plurality of write transducers and a plurality of read transducers, each read transducer being configured to read data from a sequential access medium after being written thereto by a corresponding write transducer; and
a controller and logic integrated with and/or executable by the controller, the logic being configured to:
read, using the plurality of read transducers, encoded data from a plurality of tracks of the sequential access medium simultaneously;
determine that one or more tracks of the sequential access medium are dead within a sliding window; and
rewrite a set of encoded data from the one or more dead tracks to one or more live tracks in a rewrite area of the sequential access medium,
wherein a first track of the plurality of tracks is determined to be dead in response to a determination that an output from a first read transducer is insufficient, wherein the first read transducer is aligned with a first write transducer configured to store data to the first track, wherein the output of the first read transducer is produced during read-while-write, and wherein the live tracks comprise all of the plurality of tracks of the sequential access medium except for the one or more dead tracks.

US Pat. No. 10,339,970

VIDEO RECORDING APPARATUS WITH PRE-EVENT CIRCULATION RECORDING FUNCTION

IDIS Co., Ltd., Daejeon-...

1. A video recording apparatus with a pre-event circulation recording function, the video recording apparatus comprising:a video receiver configured to receive a video captured in real time by at least one camera;
a nonvolatile storage unit configured to store the received video; and
a recording controller configured to control a pre-event video generated before an event occurs to be circulation recorded on a pre-event storage region of the nonvolatile storage unit while complying with a pre-event storage period, and control a post-event video generated after the event occurs to be recorded on a post-event storage region allocated separately from the pre-event storage region,
wherein, when the pre-event storage period is temporarily not complied with due to the circulation recording of the pre-event video, the recording controller allocates a spare storage region after the pre-event storage region for complying with the pre-event storage period, and
wherein, when returning to a start of the pre-event storage region after recording the pre-event video which has a length satisfying the pre-event storage period, the recording controller records the pre-event video on the spare storage region prior to returning to the start of the pre-event storage region in order to comply with the pre-event storage period irrespective of initial data of the pre-event storage region being overwritten when returning to the start of the pre-event storage region.

US Pat. No. 10,339,969

DETERMINING BIT ASPECT RATIOS FOR PARTIALLY-OVERLAPPING MAGNETIC RECORDING TRACKS

Seagate Technology LLC, ...

1. A method, comprising:writing isolated test tracks to determine a first areal density function for top tracks of a magnetic recording medium, the first areal density function based on write-plus-erase track widths obtained using different first laser powers and first linear bit densities that achieve a first target bit error rate for the isolated test tracks;
selecting a value LDItop of the first laser powers and a value BPItop of the first linear bit densities that result in a first target value of the areal density function;
writing partially-overlapping test tracks to determine a second areal density function of bottom tracks based on squeezed track widths written using different second laser powers and second linear bit densities that achieve a second target bit error rate for bottom test tracks of the partially-overlapping test tracks, top test tracks of the partially-overlapping test tracks being written at LDItop and BPItop; and
selecting a value LDIbottom of the second laser powers and a value BPIbottom of the second linear bit densities that result in a second target value of the second areal density function, the LDItop, BPItop, LDIbottom, and BPIbottom subsequently being used to respectively record top tracks partially overlapping bottom tracks.

US Pat. No. 10,339,968

BASE UNIT, SPINDLE MOTOR, AND DISK DRIVE APPARATUS

NIDEC CORPORATION, Kyoto...

1. A base unit for use in a disk drive apparatus including a motor arranged to be capable of rotating about a central axis extending in a vertical direction, the base unit comprising:a base member arranged to extend radially to support the motor, and including a predetermined adhesion region and an outside region outside of the adhesion region; and
a connector electrically connected to a wire arranged on the base member; wherein
the connector is adhered to the base member through an adhesive at the adhesion region of the base member;
a wettability of the adhesive on the adhesion region is higher than a wettability of the adhesive on the outside region of the base member; and
the base member includes a connector housing portion recessed in an axial direction and arranged to house the connector;
the adhesion region is arranged in a bottom surface of the connector housing portion; and
a distance between a side wall of the connector housing portion and the adhesion region measured in a direction perpendicular to the axial direction is in a range of 0.1 mm to 2.0 mm inclusive.

US Pat. No. 10,339,967

REPRODUCING APPARATUS AND REPRODUCING METHOD

SONY CORPORATION, Tokyo ...

1. A reproducing apparatus comprising:an optical system that irradiates a recording medium on which signals are each recorded on a land and a groove with a light beam emitted from a light source to obtain a signal light beam reflecting each of the recording signals of the land and the groove, generates a reference light beam from the light beam emitted from the light source, and generates a set of a first signal light beam and a reference light beam which give a phase difference of approximately 0° to a superimposed light beam obtained by superimposing the signal light beam and the reference light beam, a set of a second signal light beam and a second reference light beam which give a phase difference of approximately 180° to the superimposed light beam, a set of a third signal light beam and a third reference light beam which give a phase difference of approximately 90° to the superimposed light beam, and a set of a fourth signal light beam and a fourth reference light beam which give a phase difference of approximately 270° to the superimposed light beam;
a light receiving unit that uses a first light receiving element to receive the set of the first light beam and the first reference light beam, a second light receiving element to receive the set of the second signal light beam and the second reference light beam, a third light receiving element to receive the set of the third signal light beam and the reference, and a fourth light receiving element to receive the set of the fourth signal light beam and the fourth reference light beam;
a reproduction signal generating circuit that calculates a first difference signal a which is a difference between a first light receiving signal obtained by the first light receiving element and a second light receiving signal obtained by the second light receiving element, and a second difference signal b which is a difference between a third light receiving signal obtained by the third light receiving element and a fourth light receiving signal obtained by the fourth light receiving element, and
uses the first difference signal a, the second difference signal b, a phase difference ? between a crosstalk component and an average phase of the signal light beam, and an optical path length difference ? between the signal light beam and the reference light beam to carry out an arithmetic operation of
a·sin(???(t))?b·cos(???(t))
to obtain a reproduction signal; and
a phase extraction circuit that obtains a successive change amount ?? of ? and updates ? with the successive variation ??.

US Pat. No. 10,339,965

THERMALLY ASSISTED MAGNETIC RECORDING HEAD HAVING PLASMON GENERATOR IN WHICH DIELECTRIC LAYER IS SURROUNDED BY METAL LAYER

TDK Corporation, Tokyo (...

1. A thermally assisted magnetic recording head, comprising:a waveguide that propagates laser light as propagating light,
a main pole that includes a first end portion on an air bearing surface (ABS) facing a magnetic recording medium and that emits a magnetic flux to the magnetic recording medium,
a metal layer that is positioned between the main pole and the waveguide, that extends from a second end portion positioned on the ABS in a height direction, that generates surface plasmons from the propagating light, and that generates near-field light (NF light) from the surface plasmons at the second end portion, and
a dielectric body layer that is surrounded on both sides of the dielectric body layer in a down-track direction by the metal layer and that extends from a third end portion positioned on the ABS in a height direction, wherein a dimension of the metal layer in a cross-track direction is greater than that of the waveguide in the cross-track direction on the ABS.

US Pat. No. 10,339,964

PERPENDICULAR MAGNETIC RECORDING (PMR) WRITE HEAD WITH PATTERNED HIGH MOMENT TRAILING SHIELD

Headway Technologies, Inc...

1. A perpendicular magnetic recording (PMR) writer, comprising:(a) a main pole (MP) with a top surface that is aligned orthogonal to an air bearing surface (ABS), and having a MP tip with a trailing side at the ABS wherein the trailing side is bisected by a center plane;
(b) a trailing shield comprised of a high moment trailing shield (HMTS) layer with a magnetization saturation value from 16 kiloGauss (kG) to about 24 kG, and having a front portion formed on a write gap at the ABS; the HMTS layer comprises:
(1) the front portion that extends to a first height (h1) from the ABS;
(2) a middle portion that adjoins a backside of the front portion at h1 and extends to a second height (h2) from the ABS where h2>h1, and the middle portion at h2 is a greater down-track distance from the MP than at h1; and
(3) a back portion that adjoins a backside of the middle portion at h2 and extends to a backend at a third height (h3) from the ABS, and has a top surface formed parallel to the MP top surface, and wherein the back portion has a first down-track (DT) thickness d1 in at least a region adjacent to an outer side thereof on each side of the center plane, and behind a first plane at a pattern height (h) where h>h2, and in regions in front of the first plane that are outside of a trapezoidal shape having a first side at the first plane, a second side at a backside of the front portion or middle portion, a first inner side formed at an angle ? with respect to a second plane that intersects the first plane at width w/2 from the center plane, and a second inner side formed at angle ? with respect to a third plane at width w/2 on an opposite side of the center plane, wherein the second and third planes are parallel and the first and second inner sides have increasing separation with decreasing height from the ABS, and wherein the back portion has a second DT thickness d within the trapezoid shape where d (c) a dielectric layer formed between the HMTS back portion and the MP top surface wherein the dielectric layer has a DT thickness g in portions thereof formed below the HMTS back portion having thickness d, and a DT thickness g1, where g>g1, below the HMTS back portion having thickness d1.

US Pat. No. 10,339,963

DETERMINING THERMAL GRADIENT OF A HAMR HOTSPOT USING PSEUDO-RANDOM BIT SEQUENCES RECORDED AT A STEPPED LASER POWER

Seagate Technology LLC, ...

1. A method, comprising:recording pseudorandom bit sequences to a heat-assisted recording medium at a laser power that is stepped while recording the pseudorandom bit sequences;
reading the pseudorandom bit sequences from the heat-assisted recording medium to determine timing differences between bits written before and after the laser power is stepped; and
determining a thermal gradient of bits written to the heat-assisted recording medium based on the timing differences.

US Pat. No. 10,339,962

METHODS AND APPARATUS FOR LOW COST VOICE ACTIVITY DETECTOR

TEXAS INSTRUMENTS INCORPO...

10. A method of detecting voice in a first input signal, the method comprising:in a noise state, sampling a second input signal to form noise samples, and computing a noise value as a covariance matrix of the noise samples, the second input signal containing noise and no voice;
in the noise state, sampling the first input signal to form first signal samples, and computing a first voice value from the first signal samples;
in the noise state, detecting potential voice activity in the first signal samples;
responsive to the detecting, transitioning to a voice state;
in the voice state, sampling the first input signal to form second signal samples, and computing a second voice value as a covariance matrix of the second signal samples;
in the voice state, computing a first ratio as a log likelihood ratio of the second voice value to the noise value;
in the voice state, if the first ratio exceeds a threshold, indicating a voice activity detection, and remaining in the voice state;
in the voice state, if the first ratio does not exceed the threshold, transitioning to an interim state;
in the interim state, sampling the first input signal to form third signal samples, and computing a third voice value from the third signal samples;
in the interim state, computing a second ratio of the third voice value to the noise value;
in the interim state, if the second ratio exceeds the threshold, transitioning to the voice state; and
in the interim state, if the second ratio does not exceed the threshold, transitioning to the noise state.

US Pat. No. 10,339,961

VOICE ACTIVITY DETECTION METHOD AND APPARATUS

ZTE CORPORATION, Shenzhe...

10. A Voice Activity Detection (VAD) apparatus, comprising a hardware processor arranged to execute the following program units:an acquisition component, arranged to acquire at least one first class feature in a first feature category, at least one second class feature in a second feature category and at least two existing VAD judgment results, wherein the first class feature and the second class feature are features used for VAD detection; and
a detection component, arranged to carry out, according to the first class feature, the second class feature and the at least two existing VAD judgment results, VAD to obtain a combined VAD judgment result;
wherein the acquisition component comprises the following program subunits:
a first acquisition unit, arranged to acquire the first class feature in the first feature category which comprises at least one of: a number of continuous active frames, an average total signal-to-noise ratio (SNR) of all sub-bands and a tonality signal flag, wherein the average total SNR of all sub-bands is an average of SNR over all sub-bands for a predetermined number of frames; and
a second acquisition unit, arranged to acquire the second class feature in the second feature category which comprises at least one of: a flag of noise type, a smoothed average long-time frequency domain SNR, a number of continuous noise frames and a frequency domain SNR.

US Pat. No. 10,339,960

PERSONAL DEVICE FOR HEARING DEGRADATION MONITORING

INTERNATIONAL BUSINESS MA...

1. A computer implemented method to monitor a user's hearing and comprehension, the method comprising:receiving, by an audio capture device, a first audio input;
receiving, by the audio capture device, a second audio input, wherein the first audio input includes a voice of the user and wherein the second audio input includes a voice of a person having a conversation with the user;
converting the first and second audio inputs into respective first and second audio signals;
transmitting said first and second audio signals to a remote resource;
transcribing the first and second audio signals into respective first and second transcriptions;
analyzing, by a processor of the remote resource, the first and second transcriptions to determine if a content of the second transcription semantically matches a content of the first transcription, wherein the analysis includes an identification of cognitive breaks in the conversation between the user and the person and the identification of concepts within the content of the transcriptions, wherein a determination that the content of the second transcription is not related to the content of the first transcription will indicate possible degradation of hearing of the user;
recording the analysis to track a hearing and comprehension ability of the user; and
transmitting the recorded analysis to a healthcare provider.

US Pat. No. 10,339,959

PERCEPTION BASED MULTIMEDIA PROCESSING

Dolby Laboratories Licens...

1. A method to steer multimedia processing algorithms comprising a perceptual clusters of multimedia signals where a vector of parameters is assigned to each cluster and the multimedia signals being processed are assigned to one or more perceptual clusters generated by clustering training data based on subjective user perception based on similar or same perception or preference, wherein an algorithm calculates one or more probabilities that the signal belongs to a specific perceptual cluster, and wherein an optimal parameter configuration of the vector parameters for a target segment of the signal is determined through a steering function that calculates a weighted average of individual probabilities each applied to respective configuration parameters, and further wherein the probabilities of the segment belonging to a perceptual cluster is one of a posterior probably calculated as a Gaussian-based probability (GMM), a locality preserving projection (LPP), or a largest margin nearest neighbor (LMNN).

US Pat. No. 10,339,958

IN-HOME LEGACY DEVICE ONBOARDING AND PRIVACY ENHANCED MONITORING

ARRIS Enterprises LLC, S...

1. A method, comprising:obtaining a first user input identifying a device;
collecting from at least one ambient sensor, one or more feature data sets related to monitored usage of the device, wherein collecting one or more feature data sets comprises:
capturing, via an audio sensor, audio data from a space in which the device is located, the captured audio data including audio data generated by the device;
analyzing the captured audio data to detect a frequency of use of the device;
analyzing the captured audio data to generate the one or more feature data sets; and
comparing the one or more feature data sets to reference feature data using a statistical model;
identifying, based on the first user input and the one or more feature data sets, a set of device models, the device being represented by at least one device model of the set of device models;
determining that additional information is needed to distinguish the at least one device model representing the device from the one or more other device models of the set of device models;
requesting, based on the set of device models, a second user input;
retrieving, based on the second user input, information about the device; and
presenting the retrieved information to the user.

US Pat. No. 10,339,957

ENDING COMMUNICATIONS SESSION BASED ON PRESENCE DATA

Amazon Technologies, Inc....

1. A method, comprising:receiving, during a communications session including a first device and a second device, first data indicating that first sounds were detected by the first device, the first sounds corresponding to speech;
receiving, from the first device, second data indicating that second sounds were detected by the first device during a first amount of time after a temporal end of the speech;
determining that the second sounds correspond to non-speech;
determining the first amount of time is greater than a threshold amount of time;
receiving, from the second device, third data indicating that third sounds were received by the second device during a second amount of time after the temporal end;
determining that the third sounds correspond to non-speech;
determining that the second amount of time is greater than the threshold amount of time; and
causing the communications session to end based, at least in part, on the first amount of time and the second amount of time being greater than the threshold amount of time.

US Pat. No. 10,339,956

METHOD AND APPARATUS FOR DETECTING AUDIO SIGNAL ACCORDING TO FREQUENCY DOMAIN ENERGY

Huawei Technologies Co., ...

1. A method for detecting an audio signal according to frequency domain energy, the method comprising:receiving an audio signal frame;
acquiring frequency domain energy distribution of the audio signal frame, the frequency domain energy distribution representing an energy distribution characteristic of the audio signal frame in a frequency domain;
obtaining a maximum value distribution characteristic of a frequency domain energy distribution derivative of the audio signal frame according to the frequency domain energy distribution of the audio signal frame;
using the audio signal frame and each frame in a preset neighborhood range of the audio signal frame as a frame set, the frame set comprising a to-be-detected frame;
detecting the to-be-detected frame according to a maximum value distribution characteristic of a frequency domain energy distribution derivative of the frame set;
determining whether the audio signal is a ringtone by analyzing the maximum value distribution characteristic of the frequency domain energy distribution derivative; and
identifying a country of origin of the audio signal based on the frequency domain energy distribution of the audio signal frame when the audio signal is a ringtone.

US Pat. No. 10,339,955

INFORMATION PROCESSING DEVICE AND METHOD FOR DISPLAYING SUBTITLE INFORMATION

SONY CORPORATION, Tokyo ...

1. An information processing system, comprising:circuitry configured to:
read a current playback time of content, wherein the content is reproduced by an output device;
control a display screen to display subtitle information corresponding to the content,
wherein the subtitle information includes a plurality of text characters corresponding to the content;
determine audio feature information based on the current playback time of the content, wherein the audio feature information indicates at least a tempo of the content; and
control the display screen to:
increase a space between a first text character of the plurality of text characters and a second text character of the plurality of text characters based on the tempo of the content;
display a cursor on the subtitle information based on the audio feature information; and
display at least one of a first visual effect or a second visual effect at the cursor based on the audio feature information.

US Pat. No. 10,339,954

ECHO CANCELLATION AND SUPPRESSION IN ELECTRONIC DEVICE

Motorola Mobility LLC, C...

5. A portable device comprising:a memory;
an echo cancellation and echo suppression system having an acoustic echo correction stage and configured for audio signal processing and playback; and
a processor communicatively coupled to the echo cancellation and echo suppression system and the memory and which:
obtains an audio echo signal and an audio desired signal from the acoustic echo correction stage;
converts the echo signal and the desired signal to the frequency domain;
groups frequency bin results of respective frequency domain converted echo and desired signals into respective echo and desired sub-bands;
estimates a sub-band suppressor gain based on an estimated sub-band energy for the echo and desired sub-bands;
modulates the frequency domain converted desired signal to compensate for residual echo, the modulating based, at least in part, on the estimated sub-band suppressor gain, and the modulating producing a compensated frequency domain converted desired signal; and
converts the compensated frequency domain converted desired signal into time domain converted audio output signal.

US Pat. No. 10,339,953

HOWLING DETECTION METHOD AND APPARATUS

TENCENT TECHNOLOGY (SHENZ...

1. A howling detection method performed by a howling detection apparatus, comprising:performing, by at least one processor of the howling detection apparatus, window separation processing on an audio signal to obtain a plurality of analysis windows;
obtaining, by the at least one processor of the howling detection apparatus, a signal energy indicator value of each preset frequency in at least one analysis window by using a perceptual coefficient corresponding to each frequency, to obtain a perceptual energy indicator value of each frequency, the perceptual coefficient corresponding to each frequency indicating a sensitivity of a human ear to a sound of each frequency; and
determining, by the at least one processor of the howling detection apparatus, whether howling occurs according to the perceptual energy indicator value of each frequency in the at least one analysis window.

US Pat. No. 10,339,769

SERVER-PROVIDED VISUAL OUTPUT AT A VOICE INTERFACE DEVICE

GOOGLE LLC, Mountain Vie...

1. A method, comprising:at an electronic device with one or more microphones, a speaker, an array of indicator lights, one or more processors, and memory storing one or more programs for execution by the one or more processors:
obtaining first visual output instructions stored at the electronic device, wherein the first visual output instructions control operation of the array of indicator lights based on operating state of the electronic device, including operating states of applications executing thereon;
receiving a voice input;
obtaining from a remote system a response to the voice input and second visual output instructions, wherein the second visual output instructions are provided by the remote system along with the response in accordance with a determination that the voice input satisfies one or more criteria;
executing the response;
in response to obtaining the second visual output instructions, changing operation of the array of indicator lights to respond to the second visual output instructions instead of the first visual output instructions; and
in response to a determination of an absence of the second visual output instructions, displaying visual output on the array of indicator lights in accordance with the first visual output instructions.

US Pat. No. 10,339,748

VENDING MACHINE HAVING MECHANISMS FOR EXECUTING LOCKING, INDEXING AND DISPENSING OPERATIONS

1. A vending machine, comprising:a hopper having a central platform and a dispensing opening defined therein, said central platform having a top surface and a circular groove defined in said top surface;
a container storage carousel disposed upon, spaced and extending above said central platform of said hopper and being rotatable about a first axis extending longitudinally of said carousel, said carousel having at least a lower plate and a plurality of tubular storage columns extending upright upon said lower plate so as to define a plurality compartments containing stacks of multiple containers therein, said lower plate having a plurality of spaced apart openings defined radially outward from a central location on said lower plate, said columns being open at least at bottoms thereof and angularly spaced apart from one another in a circular row such that said columns are aligned with said openings of said lower plate and the container stacks in said columns at lowermost containers in the stacks rest on said central platform of said hopper except for one of the container stacks at a time that is placed at a dispensing position overlying said dispensing opening of said hopper as said carousel is rotated relative thereto about said first axis;
a plurality of ribs each being attached on said lower plate of said carousel at locations between adjacent ones of said spaced apart openings of said lower plate and extending therebelow to a lower end that extends into said circular groove defined in said top surface of said central platform of said hopper so as to allow for rotation of said carousel relative to said hopper, each of said ribs serving to prevent the occurrence of a condition of overlapping interference between portions of adjacent ones of the lowermost containers in adjacent ones of said columns that extend below said lower plate of said carousel and rest on said central platform of said hopper, said condition of overlapping interference being where a rim of one of the adjacent containers becomes lodged below or under a rim of the other of the adjacent containers, due to back and forth rotation of said carousel by users in selecting a particular column to align over said dispensing opening, so as to prevent dispensing of the upper container through the underlying dispensing opening of said hopper;
a dispensing mechanism disposed below said dispensing opening of said hopper and operable through a dispensing cycle to receive a lowermost container of the container stack of said column and deliver the lowermost container to a discharge location accessible to exterior of said housing; and
an actuation mechanism disposed adjacent to said dispensing mechanism that, in response to insertion of a prescribed monetary value into said actuation mechanism, is adapted to operate through an actuation cycle, causing said dispensing mechanism to operate through a dispensing cycle that delivers the lowermost container of the container stack to below said dispensing opening of said hopper and therefrom to an accessible discharge location.

US Pat. No. 10,339,731

IN-VEHICLE UNIT AND IN-VEHICLE UNIT DIAGNOSIS SYSTEM

DENSO CORPORATION, Kariy...

1. An in-vehicle unit that is mounted on each of a plurality of host vehicles including a subject vehicle and at least one nearby vehicle near the subject vehicle, the in-vehicle unit being used in a system to perform inter-vehicle communication,the in-vehicle unit in each host vehicle, comprising:
a wireless communicator that transmits and receives information using inter-vehicle communication;
a system information acquisition section that acquires information indicating a state of a control system to control operation of the in-vehicle unit in each host vehicle; and
an index data generation section that generates an index data-item including an index value indicating a state of the control system based on the information acquired by the system information acquisition section, the generated index data-item being transmitted via the wireless communicator,
wherein a subject in-vehicle unit being the in-vehicle unit used in the subject vehicle further includes:
a communication processing section that acquires, via the wireless communicator, an index data-item transmitted from at least one nearby in-vehicle unit being the in-vehicle unit used in the at least one nearby vehicle;
a determination criterion specification section that successively specifies a self-unit determination criterion being a determination criterion to determine whether the control system in the subject in-vehicle unit operates normally, based on the index data-item acquired by the communication processing section from the at least one nearby in-vehicle unit; and
a self-unit diagnosis test section that determines whether the control system in the subject in-vehicle unit operates normally by comparing the self-unit determination criterion specified by the determination criterion specification section with the index data-item in the subject in-vehicle unit.

US Pat. No. 10,339,671

ACTION RECOGNITION USING ACCURATE OBJECT PROPOSALS BY TRACKING DETECTIONS

NEC Corporation, (JP)

1. An action recognition system, comprising:an image capture device configured to capture a video sequence formed from a set of input image frames and depicting a set of objects;
a processor configured to
detect the objects to form a set of object detections;
track the set of object detections over one or more of the input frames to form tracked detections over the one or more input frames;
generate for a current input frame, responsive to a set of conditions, a set of sparse object proposals for a current location of one or more of the objects in the set based on: (i) the tracked detections of the one or more of the objects from an immediately previous one of the input frames; and (ii) detection proposals for the one or more objects derived from the current frame; and
control a hardware device to perform a response action in response to an identification of an action type of an action performed by the one or more of the objects, wherein the identification of the action type is based on the set of sparse object proposals,
wherein the set of sparse object proposals is determined using a function g that produces the sparse object proposals for the current frame only when a given condition in the set of conditions is unsatisfied, the given condition being that the tracked detections lack inclusion of the one or more of the objects, and
wherein the tracked detections include a set of n tracked detections t-1={1; . . . ; n} from the immediately previous one of the input frames, and the detection proposals from the current frame include a set of m sparse object proposals Pt={P1; . . . ; Pm} from the current frame, such that the function is implemented by g(Pt,t-1).

US Pat. No. 10,339,659

SYSTEM, METHOD, AND RECORDING MEDIUM FOR WORKFORCE PERFORMANCE MANAGEMENT

INTERNATIONAL BUSINESS MA...

1. A break recommendation system, comprising:a document identification and difficulty measuring circuit configured to identify a document type of a document;
a cognitive state tracking circuit configured to track on a continuous basis a cognitive state of a user viewing and working on the document via an imagine device, the imagine device being controlled by:
a gaze tracking circuit configured to track an eye gaze movement of the user over time relative to the document to determine the cognitive state of the user; and
an emotional and facial expression tracking circuit configured to monitor a facial and emotional expression of the user over time relative to the document to determine the cognitive state of the user;
a deviation detecting circuit configured to detect a deviation between a current cognitive state of the user and a past cognitive state of the user during a predetermined amount of time for the identified document type based on a change in the eye gaze movement and the facial and emotion expression; and
a recommending circuit configured to recommend that the user takes a break from viewing the document for a predetermined amount of time based on the deviation being greater than a predetermined threshold value, wherein the cognitive state of the user is determined based on the viewing of the document by the user, and wherein the deviation is in a relation to the user viewing the document and the identified document type of the document.

US Pat. No. 10,339,658

METHOD FOR PERFORMING SEGMENTATION IN AN ORDERED SEQUENCE OF DIGITAL DATA

Oculus Machina S.P.A., L...

1. A method for performing segmentation in a sorted sequence of digital data, characterized in that it comprises:applying to a first matrix (11), which is the first of a sequential stream of sorted input data (10), a first transformation that has three options: reduction, maintenance, or amplification, and as a result of which a second matrix (12) is obtained, where the first option of a first reduction transformation comprises each element of the first matrix (11) being linked in a p:q ratio with the second matrix (12), where p elements of the first matrix (11) con project into q elements of the second matrix (12); the first reduction transformation being applied in a stationary way, i.e. each sector of p elements of the first matrix (11) generate an element q in the second matrix (12); the second option of a first maintenance transformation comprises each element of the first matrix (11) being copied in the second matrix (12); the third option of a first amplification transformation comprises each element of the first matrix (11) being linked in a p:q ratio with the second matrix (12), where p elements of the first matrix (11) can project themselves into q elements of the second matrix (12); where each element p of the first matrix (11) generates q new elements in the second matrix (12);
applying a second transformation, consisting of a truncated ramp function, to the second matrix (12), which results in obtaining a third matrix (13);
applying a third transformation to the third matrix (13) to generate a fourth matrix (14), where the third transformation comprises the application of a discretized Gaussian filter; where each element of the third matrix (13) generates a new element in the fourth matrix (14);
applying a fourth reduction transformation to the fourth matrix (14) to obtain a fifth matrix (15);
applying a fifth binarization transformation to the fifth matrix (15) to obtain a sixth matrix (16); where the binarization transformation comprises binarizing each element of the fifth matrix (15) into the corresponding element in the sixth matrix (16), based on whether the element's value is greater than or less than 50% of the fifth matrix's (15) maximum value, which comprises taking a 1 or 0 value of the fifth matrix (15) element to the corresponding element in the sixth matrix (16), based on whether the element's value is greater than or less than 50% of the maximum fifth matrix's (15) value;
applying a sixth reduction transformation to the sixth matrix (16) to obtain a seventh matrix (17);
applying a seventh transformation to the seventh matrix (17) to obtain an eighth matrix (18), which comprises binarizing each element of the seventh matrix (17) to take a 1 or 0 value of the seventh matrix (17) element to the corresponding element in the eighth matrix (18), based on whether the element's value is greater than or less than 50% of the maximum seventh matrix's (17) value; and
where the eighth matrix (18) becomes the output matrix for the sequential stream of sorted output data (30), and the information contained in the eighth matrix (18) of the sequential stream of sorted output data (30) represents the zones or segments containing information delimiting the image's constituent elements, or the sequential stream of sorted output data (30).

US Pat. No. 10,339,657

CHARACTER DETECTION APPARATUS AND METHOD

Kabushiki Kaisha Toshiba,...

1. A character detection apparatus, comprising:a memory; and
processing circuitry configured to:
extract a feature value of an image region including one or more character strings, wherein the feature value is a luminance or a length of the image region in a longitudinal direction;
determine, based on the feature value, which one of a plurality of character detection schemes has a higher character detection accuracy for the image region; and
select a text candidate region detected by the determined character detection scheme if a superimposition degree among a plurality of text candidate regions detected by the plurality of character detection schemes is no less than a first threshold;
wherein
if the superimposition degree is less than the first threshold and if an inclusive relationship exists, a maximum text line candidate having a largest region among superimposed text line candidates is selected as a text line, and
if a ratio of a superimposed region occupying a minimum text line candidate is less than a second threshold value, each of the superimposed text line candidates is selected as a text line.

US Pat. No. 10,339,656

INFERRING COUNT OF ITEMS USING IMAGE

AMAZON TECHNOLOGIES, INC....

1. A system comprising:a memory, storing computer-executable instructions; and
a hardware processor to execute the computer-executable instructions to:
access image data representative of a fixture;
access data indicative of a type of item associated with the fixture;
access two-dimensional (2D) data indicative of at least a portion of a top of the type of item;
access three-dimensional (3D) data associated with the type of item;
determine, using the image data, one or more estimated tops of the type of item at the fixture;
determine one or more estimated item locations associated with the one or more estimated tops of the type of item at the fixture, wherein the one or more estimated item locations are indicative of points in 3D space;
determine a first set of the one or more estimated item locations that comprises those estimated item locations that are within a working volume of the fixture, the working volume comprising a volume where the type of item could be physically present;
determine one or more estimated dimensions based at least in part on the first set of one or more the estimated item locations; and
determine a quantity of the type of item at the fixture using the one or more estimated dimensions and the 3D data associated with the type of item.

US Pat. No. 10,339,655

AUTOMATED IMAGE EVALUATION IN X-RAY IMAGING

Siemens Healthcare GmbH, ...

1. A method for automated evaluation of x-ray image data from an examination region of a patient, which comprises the steps of:receiving the x-ray image data from the examination region;
segmenting the x-ray image data resulting in segmented x-ray image data, the x-ray image data being segmented based on anatomical structures detected in individual segments of the x-ray image data;
determining reference image data coming closest to the segmented x-ray image data on a basis of a comparison of the segmented x-ray image data with the reference image data from a reference database, wherein the reference image data of the reference database having quality information relating to image quality of the reference image data; and
deciding whether the x-ray image data will be retained or rejected, based on the quality information of the reference image data determined.

US Pat. No. 10,339,651

SIMULTANEOUS FEATURE EXTRACTION AND DICTIONARY LEARNING USING DEEP LEARNING ARCHITECTURES FOR CHARACTERIZATION OF IMAGES OF HETEROGENEOUS TISSUE SAMPLES

International Business Ma...

1. An autoencoder comprising:an input component comprising a convolutional stack and configured to receive an image; and
an output component coupled to the input component and comprising a deconvolutional stack,
wherein the input component and the output component are configured to simultaneously learn a set of descriptive features and a dictionary of representative atoms,
wherein the output component is further configured to assign to the image at least one representative atom of the dictionary of representative atoms, and
wherein the input component is trained by tiling a patch of the image in subpatches and keeping a set of s highest activation values per subpatch and setting remaining activations of each subpatch to zero thereby not changing a size of an output of the input component.

US Pat. No. 10,339,649

METHOD AND SYSTEM FOR HYBRID MESH SEGMENTATION

Carestream Dental Technol...

1. A computer-implemented method for generating a digital model of an individual intraoral component from a digital model of a patient's dentition, the method comprising:obtaining a 3-D digital mesh model of the patient's dentition;
performing a first automatic tooth component segmentation on the obtained 3-D digital mesh model and displaying first automated tooth segmentation results;
performing a second interactive tooth segmentation on said displayed first automated tooth segmentation results according to an operator instruction to adjust a segmentation parameter of the first automatic tooth component segmentation method;
displaying and storing second tooth segmentation results that combine the first automatic tooth component segmentation and the second interactive tooth segmentation;
performing a third interactive tooth segmentation on said second tooth segmentation results according to at least one second operator instruction to select a different second type segmentation method and adjust a segmentation parameter of the different second type segmentation method;
displaying and storing third tooth segmentation results that combine the first automatic tooth component segmentation, the second interactive tooth segmentation, and the third interactive tooth segmentation;
accepting a third operator instruction to modify the displayed third segmentation results and then perform a fourth interactive tooth component segmentation using the modified third segmentation results; and
displaying and storing combined segmentation results that combine the first automatic tooth component segmentation, the second interactive tooth component segmentation, the third interactive tooth component segmentation, and the fourth interactive tooth component segmentation.

US Pat. No. 10,339,647

METHODS, SYSTEMS, AND MEDIA FOR QUALITATIVE AND/OR QUANTITATIVE INDENTATION DETECTION

1. A method of verifying glass bead indentations within an inner automotive door panel and an outer automotive door panel, the method comprising:separating the panels previously joined together by an adhesive comprising beads;
placing an indented surface from each panel, each indented surface having been indented by the beads, in front of an image capturing device;
receiving imaging data from the image capturing device, the imaging data comprising a plurality of indentations within a region on a surface of the inner automotive door panel or the outer automotive door panel;
identifying, through an imaging algorithm, a plurality of indentations in each indented panel surface;
obtaining a size measurement for each indentation of the identified plurality of indentations in each indented panel surface; and
calculating a number of indentations within the region that are equal to or above a minimum size.

US Pat. No. 10,339,646

IMAGE PROCESSING OF AERIAL IMAGERY FOR ENERGY INFRASTRUCTURE ANALYSIS USING PRE-PROCESSING IMAGE SELECTION

SOURCEWATER, INC., Houst...

1. A computer-implemented method for selecting aerial images for image processing to identify Energy Infrastructure (EI) features, the method to be carried out by at least one processor executing computer instructions, the method comprising:receiving a first plurality of aerial images spanning a portion of global terrain, the first plurality of aerial images associated with a first time of image capture;
receiving a second plurality of aerial images spanning the portion of global terrain, the second plurality of aerial images associated with a second time of image capture;
identifying one or more differences in terrain content between the first time of image capture and the second time of image capture according to a comparison of image content in at least one aerial image from the first plurality of aerial images and image content in at least one aerial image from the second plurality of aerial images;
identifying one or more geographical locations at which the respective one or more differences in terrain content have been identified;
selecting a set of aerial images from the first plurality of aerial images, the second plurality of aerial images, or a third plurality of aerial images based on the one or more geographical locations having a difference in terrain content;
applying an EI feature recognition model to the set of aerial images to identify at least one EI feature.

US Pat. No. 10,339,645

DEFECT DETECTION DEVICE AND PRODUCTION SYSTEM

Nissan Motor Co., Ltd., ...

1. A defect detection device comprising:a camera configured to image an image of an inspection object;
a binarization processor configured to subject the image to first and second binarization processing by use of a first binarization threshold and a second binarization threshold different from the first binarization threshold, so as to calculate first and second sizes for an identical defect in the image;
a ratio calculation processor configured to calculate a first ratio of the second size to the first size; and
a depth determination processor configured to determine a depth of the defect depending on the first ratio,
wherein the first binarization threshold is larger than the second binarization threshold, and
a size of the identical defect includes at least one of a defect area and a defect length.

US Pat. No. 10,339,611

SYSTEMS AND METHODS FOR PAGE RECOMMENDATIONS

Facebook, Inc., Menlo Pa...

1. A computer-implemented method comprising:determining, by a computing system, seed content items based on interests of a user;
determining, by the computing system, candidate content items for potential presentation to the user based at least in part on the seed content items, wherein the seed content items and the candidate content items are, respectively, seed pages and candidate pages of a social networking system;
extracting, by the computing system, features associated with the candidate content items and related online user behavior;
processing, by the computing system, the features to generate probabilities that the user will perform interactions with the candidate content items, wherein the processing the features further comprises applying machine learning models based on the features to generate the probabilities;
assigning, by the computing system, values to the candidate content items based at least in part on the probabilities that the user will perform interactions with the candidate content items and importance of the interactions;
providing, by the computing system, the values as bid values to an auction system to determine constraints regarding presentation of the candidate content items, wherein the constraints include at least one of a time constraint and a space constraint;
optimizing, by the computing system, presentation of the candidate content items; and
presenting, by the computing system, to the user at least a first candidate content item having a highest value.

US Pat. No. 10,339,534

SEGREGATION OF CHAT SESSIONS BASED ON USER QUERY

1. A computer implemented chat analysis method, comprising:providing a processor, said processor creating and using a model for classifying
resolutions in a chat session in phases comprising a model training phase, a model testing phase, and a model application phase;
during said model training phase, a first chat filter extracting relevant portions of a chat session;
said processor performing feature extraction on said relevant portions of said chat session to obtain feature vectors;
said processor determining said feature vectors according to category relevancy;
said processor scoring said feature vectors based on a probability or likelihood of classifying said feature into a particular one of a plurality of categories;
said processor ranking said categories by their scores; and
based on a most likely category, as determined by said ranking, said processor making a final assignment of a predicted classification of said feature;
during said model testing phase, a second chat filter extracting relevant portions of a chat session;
said processor analyzing said chat session;
said processor validating said model against labeled data; and
during said model application phase, said processor receiving user chat information comprising a user interaction during a chat session across a computer network from a computer chat system or a system for real time communication across said computer network;
said processor extracting unlabeled data from said user chat information;
said processor scoring said unlabeled data with said model;
during said chat session, said processor analyzing said user interaction with said model to predict a type of chat session;
said processor determining whether said chat session comprises an information based chat query or an action request-based chat query;
based upon said type determination, said processor determining an action to take in connection with said chat session;
when said chat session comprises an information based chat query, providing responsive information to said user; and
when said chat session comprises an action request-based chat query, performing a responsive action on behalf of the user.

US Pat. No. 10,339,533

METHODS AND SYSTEMS FOR SCALABLE SESSION EMULATION

Spirent Communications, I...

1. A method of emulating a plurality of virtual users sending test messages to a server under test, the method comprising:executing a test program on a computer system, the computer system communicatively coupled to the server, the test program emulating the plurality of virtual users by:
instantiating a first virtual user instance by calling a first reentrant function, including creating a first set of local variables in a first instance memory,
the first virtual user instance executing, accessing at least one local variable in the first set of local variables, sending a first test message to the server, and exiting the first reentrant function upon encountering a first blocking statement defined in the first reentrant function; and
instantiating a second virtual user instance by calling the first reentrant function, including creating a second set of local variables in a second instance memory,
the second virtual user instance executing, accessing at least one local variable in the second set of local variables, sending a second test message to the server, and exiting the first reentrant function upon encountering a second blocking statement defined in the first reentrant function;
again calling the first reentrant function to reenter as the first virtual user instance and resuming execution at a point in the first reentrant function after the first blocking statement; and
again calling the first reentrant function to reenter as the second virtual user instance and resuming execution at a point in the first reentrant function after the second blocking statement.

US Pat. No. 10,339,516

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, AND CONTROL METHOD OF AN INFORMATION PROCESSING DEVICE

Seiko Epson Corporation, ...

1. An information processing device capable of communicating with a printer that produces receipts printed with transaction information related to a transaction, and has a plurality of application programming interfaces (APIs) registered thereon, the information processing device comprising:a storage storing a database; and
a processor configured to
receive print data of the printed receipts from the printer that receives the print data from a host computer and produces the receipts based on the received print data, the print data including a control command in a command language of the printer,
extract, from the received print data, the transaction information that is predefined information without the control command, and store the extracted transaction information in the database, and
execute, when response request information requesting a response and including API call information specifying an API is received from an external device, a process through the API specified by the API call information based on the transaction information stored in the database, and send information indicating a process result to the external device.

US Pat. No. 10,339,513

CLOSED-LOOP TESTING OF INTEGRATED CIRCUIT CARD PAYMENT TERMINALS

Worldpay, LLC, Symmes To...

1. A method for closed-looped testing of integrated circuit device terminals in a first network environment, the method comprising:loading, by a data transfer simulation server of the first network environment, a test data transfer profile onto an integrated circuit device, wherein the test data transfer profile comprises test parameters defining a test data transaction to be processed in the first network environment;
receiving, by the data transfer simulation server and from a merchant transaction server of the first network environment, a first authorization request message for the test data transaction, wherein the first authorization request message is generated by the merchant transaction server and corresponds to the test data transfer profile, and wherein the merchant transaction server is one of one or more integrated circuit device terminals in the first network environment;
generating, by the data transfer simulation server, an authorization response message for the test data transaction based on the test data transfer profile;
transmitting, by the data transfer simulation server, the authorization response message to the merchant transaction server of the first network environment;
receiving, by the data transfer simulation server and from the integrated circuit device, test log data, wherein the test log data corresponds to the test data transaction and comprises the first authorization request message, the authorization response message, and timestamps associated with the first authorization request message and the authorization response message; and
determining whether one or more integrated circuit device terminals may operate outside of the first network environment based on an analysis of the test log data.

US Pat. No. 10,339,503

VARIABLE ACCESS TO TIME BLOCK INFORMATION

Amazon Technologies, Inc....

1. A computer-implemented method for providing access to calendar information, the method comprising:receiving, by a computer system, parameters for a calendar appointment that include one or more identity conditions specific to the calendar appointment;
modifying, by the computer system, access control information in accordance with the one or more conditions;
receiving, from a requestor device, a request for access to calendar information for a block of time that at least partially intersects a block of time for the calendar appointment;
in response to the request:
determining, by the computer system, information that identifies that the block of time for the calendar appointment is occupied instead of identifying that the block of time for the calendar appointment is unoccupied based at least in part on an identity associated with a requestor of the requestor device and the modified access control information; and
providing, to the requestor device, a response causing a graphical update to a user interface displayed on the requestor device, the user interface configured to present the calendar information, the response identifying the block of time for the calendar appointment as occupied based at least in part on the determined information and the modified access control information thereby enabling the requestor associated with the requestor device to more efficiently identify another block of time for another calendar appointment.

US Pat. No. 10,339,467

QUANTITATIVE DISCOVERY OF NAME CHANGES

International Business Ma...

1. A method, comprising:maintaining, on a storage device, historical performance data for one or more contracts, wherein the historical performance data comprises a date, a data value and a name for the one or more contracts;
classifying, on at least one hardware processor, a name replacement pair as a name change, wherein each name replacement pair comprises a pair of names, each name change represents a change in descriptor that does not affect a behavior of the one or more contracts, the classifying comprises:
obtaining a sample of known name replacement pairs included in the historical performance data, wherein each known name replacement pair included in the sample is a known name change;
for each known name replacement pair included in the sample:
based on a first set of quantitative features of a first time series model included in the historical performance data and comprising performance data for a first name and a second name of the known name replacement pair, determining a first window of time for the known replacement pair that covers a most recent appearance of the first name of the known name replacement pair, wherein the known name replacement pair is one of a positive example or a negative example of a name change; and
training a machine learning classifier based on a second set of quantitative features computed using a portion of the first time series model that is within the first window of time;
generating, on the at least one hardware processor, a first predicted name replacement pair based on a first known name replacement pair of the sample and a second known name replacement pair of the sample, wherein the first known replacement pair and the second known replacement pair are known name changes that occur at the same time, and an average of first performance data for the first known replacement pair differs from an average of second performance data for the second known replacement pair;
applying the trained machine learning classifier to the first predicted name replacement pair; and
adding the first predicted name replacement pair to the sample of known name replacement pairs in response to the trained machine learning classifier classifying the first predicted name replacement pair as a name change; and
based on the sample of known name replacement pairs, detecting a name change in the historical performance data, and identifying data included in the historical performance data and associated with the name change as a continuation of a contract instead of a start of a different contract, wherein one or more long running models of the one or more contracts for use in predicting one or more behaviors related to the one or more contracts are constructed based on the data identified.

US Pat. No. 10,339,466

PROBABILISTIC INFERENCE IN MACHINE LEARNING USING A QUANTUM ORACLE

Google LLC, Mountain Vie...

1. A method performed by a system of one or more computers for probabilistic inference in a model for use in machine learning, the method comprising:receiving data for training the model, the data comprising observed data for training and validating the model, and wherein the model is a modified restricted Boltzmann machine that includes interactions among hidden units of the restricted Boltzmann machine, wherein the interactions are based on hardware connections of a quantum oracle implemented using a quantum machine comprising an adiabatic quantum computing system, the hardware connections comprising couplers that connect qubits included in the quantum oracle;
deriving input to the quantum oracle using the received data and a state of the model, the input mapping at least some interactions of different interconnected units of the model to connections between qubits in the quantum oracle;
providing the input to the quantum oracle for learning the inference in the model; and
receiving from the quantum oracle data representing the learned inference.

US Pat. No. 10,339,465

OPTIMIZED DECISION TREE BASED MODELS

Amazon Technologies, Inc....

1. A system, comprising:one or more computing devices configured to:
identify one or more run-time optimization goals for a decision-tree based machine learning model to be trained using a data set, including at least a goal for a memory footprint of an execution of the machine learning model subsequent to a training phase of the machine learning model;
store, at one or more persistent storage devices during a tree-construction pass of the training phase, respective representations of a plurality of nodes of a particular decision tree generated using at least a portion of the data set, wherein the representations of nodes of the particular decision tree are streamed to and stored in the persistent storage devices in a depth-first order of the particular decision tree as the nodes are being generated;
determine, for one or more nodes of the particular decision tree during the tree-construction pass, a respective value of a predictive utility metric (PUM), wherein a particular PUM value associated with a particular node of the one or more nodes is a measure of an expected contribution of the particular node to a prediction generated using the machine learning model;
generate, during a tree-pruning pass of the training phase, a modified version of the particular decision tree, wherein to generate the modified version, at least the particular node is removed from the particular decision tree, wherein the particular node is selected for removal based at least in part on the one or more run-time optimization goals for the execution of the machine learning model subsequent to the training phase of the machine learning model and based at least in part on the particular PUM value;
store a representation of the modified version of the particular decision tree; and
subsequent to the training phase, execute the machine learning model using at least the modified version of the particular decision tree to obtain a particular prediction.

US Pat. No. 10,339,463

METHOD AND DEVICE FOR CREATING A FUNCTION MODEL FOR A CONTROL UNIT OF AN ENGINE SYSTEM

ROBERT BOSCH GMBH, Stutt...

1. A method, performed via a processor, for generating a function model, for emulating route and system functions in a control unit for a combustion engine system, based on a non-parametric, data-based model, the method comprising:providing training data including measuring points having at least one input variable, the measuring points each being assigned an output value of an output variable;
providing a basic function;
modifying the training data based on a difference between the function values of the basic function and the output values at the measuring points of the training data;
generating the data-based model based on the modified training data;
generating the function model as a function of the data-based model and the basic function; and
providing the function model, for emulating the route and system functions in the control unit for the combustion engine system; and
controlling the combustion engine system based on the function model;
wherein the training data improves the function model used by the processor,
wherein the basic function is one of (i) predefined as a D-dimensional hyperplane, or (ii) defined by predefining target values at target value points, the basic function being defined by a number D+1 target values for a number of D input variables, and
wherein the function model provides improved control of the combustion engine system, since the function model converges in an extrapolation range against a predefined basic function.

US Pat. No. 10,339,462

SYSTEM AND METHOD FOR EXECUTING A HIGH BANDWIDTH NETWORK ACTIVITY AS A BACKGROUND ACTIVITY IN A VIRTUAL DESKTOP ENVIRONMENT

Dell Products, LP, Round...

1. An information handling system comprising:a plurality of memories; and
a plurality of processors including a first processor, portions of the processors and the memories being allocatable as a virtual machine to a second information handling system, the first processor to monitor a high bandwidth network activity of the second information handling system during a learning phase, to store an event associated with the high bandwidth network activity, to detect whether the high bandwidth network activity is executed at set intervals after the event is detected during the learning phase, to detect the event during an operating phase, to determine based upon a predictive analytics algorithm a correlation score that the event predicts the occurrence of high bandwidth network activity, and to transfer data associated with the high bandwidth network activity as a background activity based on available bandwidth between the information handling system and the second information handling system and on the correlation score;
wherein the event comprises one of plugging a USB device into the second information handling system and printing a file from the information handling system to the second information handling system.

US Pat. No. 10,339,461

SYSTEM FOR MAINTENANCE OF A MANUFACTURED PRODUCT

The Boeing Company, Chic...

1. An apparatus for implementation of a system for maintenance of a manufactured product composed of a plurality of physical parts including a multiple quantity of a physical part of the plurality of physical parts, the apparatus including a processor and a memory storing executable instructions that, in response to execution by the processor, cause the apparatus to implement at least:a data collection engine configured to receive failure data for the plurality of physical parts in which the failure data indicates individual instances of failure of at least two of the multiple quantity of the physical part, each of the at least two of the multiple quantity being located at a respective distinct location in the manufactured product;
a modeling engine configured to generate a superimposed failure model (SFM) for the physical part based at least partially on the failure data, including the modeling engine being configured to determine a lifetime distribution of the physical part based at least partially on application of a lifetime distribution model to the SFM; and
a maintenance engine coupled to the modeling engine and configured to perform a maintenance activity for the physical part, including the maintenance engine being configured to determine a maintenance interval for the physical part according to the lifetime distribution of the physical part, wherein the maintenance engine is further configured to automatically schedule the physical part for removal or replacement based at least partially on the maintenance interval determined for the physical part; and communicate the schedule to a user.

US Pat. No. 10,339,460

METHOD AND APPARATUS FOR AUTONOMOUS SYNCHRONOUS COMPUTING

SimpleRose, Inc., St. Lo...

1. A special purpose computer for processing a linear optimization problem capable of being represented in the form [A][X]+[I][Y]=[B] and wherein the linear optimization problem can also be represented in the form [E][A][X]+[E][I][Y]=[E][B], the computer comprising:a first processor;
a plurality of row processors not addressed by the first processor and each of the plurality of row processors configured to store a row of the matrix [E];
a computer memory in communication with the first processor and in communication with each row processor so that each row processor can read from the computer memory and write to the computer memory;wherein the first processor is configured to signal all of the row processors to process data related to the linear optimization problem.

US Pat. No. 10,339,459

SYSTEM AND METHOD FOR RAPID AND ROBUST UNCERTAINTY MANAGEMENT DURING MULTIDISCIPLINARY ANALYSIS

THE BOEING COMPANY, Chic...

1. A method of conducting a trade study for an aircraft design by estimating uncertainty for a data dependent constraint network while avoiding intermixing planning and computation, the method comprising:accessing an electronically stored bipartite graph representing the data dependent constraint network, the bipartite graph comprising variable nodes representing a plurality of variables representing aircraft parameters, compound-valued variable nodes representing a plurality of compound-valued variables representing aircraft design alternatives, relation nodes representing a plurality of relations for the aircraft parameters, and arcs interconnecting a plurality of the variable nodes, the compound-valued variable nodes, and the relation nodes, the plurality of variables comprising a set S of variables that have uncorrelated errors, a set I of variables for which a user may specify values, and a set V of variables for which a user may specify uncertainties, wherein at least one of the following occurs: the set S is not equal to the set V, the set V is not equal to the set I, or the set S is not equal to the set I;
obtaining a user selection electronically, the user selection comprising at least one of: values for variables in the set I or uncertainties for variables in the set V;
propagating electronically at least one gradient related to the user selection through the data dependent constraint network configured with a flow state in which nodes for variables in S have only outgoing arcs;
recording electronically variables that are touched by the propagating electronically at least one gradient related to the user selection;
propagating electronically, through the data dependent constraint network configured in a flow state in which nodes for variables in the set S have only outgoing arcs, at least one uncertainty for the variables that are touched by the propagating electronically at least one gradient related to the user selection;
outputting electronically at least one outputted uncertainty for at least one variable not in the set V, whereby setting an uncertainty for the at least one variable not in the set V to the at least one outputted uncertainty for the at least one variable not in the set V causes the user selection to be consistent for the data dependent constraint network;
conducting the trade study based at least in part on the user selection and on the at least one outputted uncertainty for the at least one variable not in the set V; and
designing the aircraft based on results of the trade study.

US Pat. No. 10,339,458

SYSTEM AND METHOD FOR RAPID AND ROBUST UNCERTAINTY MANAGEMENT DURING MULTIDISCIPLINARY ANALYSIS

The Boeing Company, Chic...

1. A method of conducting a trade study for an aircraft design by estimating uncertainty for a data dependent constraint network while avoiding intermixing planning and computation, the method comprising:accessing an electronically stored bipartite graph representing the data dependent constraint network, the bipartite graph comprising variable nodes representing a plurality of variables representing aircraft parameters, relation nodes representing a plurality of relations for the aircraft parameters, and arcs interconnecting a plurality of the variable nodes and the relation nodes, the plurality of variables comprising a set S of variables that have uncorrelated errors, a set I of variables having user specifiable values, and a set V of variables having user specifiable uncertainties, wherein at least one of the following occurs: the set S is not equal to the set V, the set V is not equal to the set I, or the set S is not equal to the set I;
obtaining a user selection electronically, the user selection comprising at least one of: values for the variables in the set I or uncertainties for the variables in the set V;
propagating electronically at least one gradient related to the user selection through the data dependent constraint network configured with a flow state in which nodes for the variables in the set S have only outgoing arcs;
recording electronically variables that are touched by the propagating electronically at least one gradient related to the user selection;
propagating electronically, through the data dependent constraint network configured in a flow state in which the nodes for the variables in the set S have only outgoing arcs, at least one uncertainty for the variables that are touched by the propagating electronically at least one gradient related to the user selection;
outputting electronically at least one outputted uncertainty for at least one variable not in the set V, whereby setting an uncertainty for the at least one variable not in the set V to the at least one outputted uncertainty for the at least one variable not in the set V causes the user selection to be consistent for the data dependent constraint network;
conducting the trade study based at least in part on the user selection and on the at least one outputted uncertainty for the at least one variable not in the set V; and
designing the aircraft based on results of the trade study.

US Pat. No. 10,339,457

APPLICATION PERFORMANCE ANALYZER AND CORRESPONDING METHOD

New Relic, Inc., San Fra...

1. An application performance management system adapted to analyze the performance of one or more applications running on information technology (IT) infrastructure, said application performance management system comprising:a data collector adapted to collect performance metrics for said one or more applications running on said IT infrastructure and adapted to collect communication path data being indicative of communication paths between nodes of said IT infrastructure; and
an anomaly detector adapted to analyze said performance metrics and to detect anomalies,
wherein said application performance management system further comprises:
an anomaly correlator adapted to detect dependencies between plural anomalies based on said communication path data and to generate anomaly clusters, each anomaly cluster including anomalies that are correlated through one or more of said dependencies;
an anomaly ranking unit adapted to rank anomalies within an anomaly cluster based on said communication path data; and
a source problem detector adapted to pinpoint a problem source from the lowest ranked anomaly in said anomaly cluster.

US Pat. No. 10,339,456

MACHINE LEARNING-BASED TROUBLESHOOTING OF VOLTE CALLS

T-Mobile USA, Inc., Bell...

1. One or more non-transitory computer-readable media storing computer-executable instructions that upon execution cause one or more processors to perform acts comprising:receiving Voice over LTE (VoLTE) call records of VoLTE calls that are carried by a wireless carrier network for multiple user devices, the VoLTE call records including internet protocol (IP) multimedia subsystem (IMS) messages, performance indicators, and call features for the voice calls, each call feature of a VoLTE call representing a circumstance under which the VoLTE call is established and ended;
labeling each of the VoLTE calls as a call with a Quality of Experience (QoE) problem or a call without a QoE problem based on IMS message information of the VoLTE calls included in the VoLTE call records;
applying a decision tree to the VoLTE call records to identify critical features of one or more call conditions that lead to QoE problems for the VoLTE calls captured in the VoLTE call records, each call condition including a subset of the call features, wherein applying the decision tree to the VoLTE call records includes:
designating a first call feature of the subset of call features included in a corresponding first call condition to assess an effect of the first call feature on the QoE problem;
determining a first number of the VoLTE calls that experienced the QoE problem and were made with the first call condition;
determining a second total number of the VoLTE calls that were made with the first call condition;
determining a third total number of the VoLTE calls that were made with the first call condition but without the first call feature;
determining that the first call feature is a critical feature in causing the QoE problem in response to a difference between a first ratio and a second ratio being larger than zero, wherein the first ratio is a ratio between the first number and the second total number, and wherein the second ratio is a ratio between the first number and the third total number; and
applying a classifier on the critical features to determine a root cause of a corresponding QoE problem for at least one call condition.

US Pat. No. 10,339,455

TECHNIQUES FOR DETERMINING WORKLOAD SKEW

EMC IP Holding Company LL...

1. A method for predicting cumulative skew curves comprising:determining, using a processor, a first model that generates a predicted destination cumulative skew curve for a specified data set in a destination data storage system having a destination data movement granularity, said predicted destination cumulative skew curve being predicted by the first model in accordance with one or more inputs including a source cumulative skew curve for the specified data set in a source data storage system that uses a source data movement granularity that is different from the destination data movement granularity, wherein said source cumulative skew curve includes a plurality of observed data points each having a first coordinate and a second coordinate, the first coordinate representing a first ratio of a first aggregated capacity with respect to a total capacity, said total capacity representing a total size of a total set of data portions, said first aggregated capacity representing a capacity of a first set of one or more data portions of the total set, each data portion of the first set having a higher workload than any other data portion of the total set that is not included in the first set, the second coordinate representing a second ratio of an aggregated workload with respect to a total workload directed to the total set of data portions whereby the aggregated workload is directed to the first set of one or more data portions;
determining, using a processor, the source cumulative skew curve for the specified data set based on observed data;
performing, using a processor, first processing using the first model that generates as an output the predicted destination cumulative skew curve having the destination data movement granularity that is different from the source data movement granularity, said first processing including providing the one or more inputs to the first model;
performing, using a processor and in accordance with the predicted destination cumulative skew curve for the destination data storage system, capacity planning for the destination data storage system having the destination data movement granularity that is different from the source data movement granularity; and
migrating, using a processor, the specified data set from the source data storage system to the destination data storage system that has a configuration based on the capacity planning.

US Pat. No. 10,339,454

BUILDING A HYBRID REACTIVE RULE ENGINE FOR RELATIONAL AND GRAPH REASONING

Red Hat, Inc., Raleigh, ...

1. A method comprising:receiving a first object by a processing device executing a rule engine;
determining, by the processing device, whether the first object is represented by a relational model or an object-oriented model, wherein the first object is determined to be represented by the relational model responsive to the first object lacking a reference to a nested object, and wherein the first object is determined to be represented by the object-oriented model responsive to the first object comprising a reference to a nested object;
responsive to determining that the first object is represented by the relational model, performing a join between the first object and a second object based on a relationship between the first object and the second object using a first node, wherein the first node comprises a left input that receives the first object and a right input that receives the second object; and
responsive to determining that the first object is represented by the object-oriented model, evaluating an expression of the first object to navigate to a third object that is a first nested object of the first object using a second node, wherein the second node comprises a single input that receives the first object.

US Pat. No. 10,339,453

AUTOMATICALLY GENERATING TEST/TRAINING QUESTIONS AND ANSWERS THROUGH PATTERN BASED ANALYSIS AND NATURAL LANGUAGE PROCESSING TECHNIQUES ON THE GIVEN CORPUS FOR QUICK DOMAIN ADAPTATION

International Business Ma...

1. A method, in a data processing system configured with a computer readable program that causes the data processing system to implement a question and answer creation system executing on a processor of the data processing system for automatically generating question and answer pairs for training a question answering system for a given domain, the method comprising:automatically identifying, by the question and answer creation system executing on the processor of the data processing system, a set of most frequently occurring patterns of components in passages within a corpus of documents for the given domain using an unsupervised technique;
automatically filtering the set of most frequently occurring patterns to remove frequently occurring patterns that are unlikely to result in meaningful questions based on a domain dictionary to form a filtered set of patterns;
identifying, by the question and answer creation system, a set of rules that correspond to the filtered set of patterns for generating question and answer pairs from the passages within the corpus of documents;
storing, by the question and answer creation system, the filtered set of patterns in association with the set of rules in a pattern-rules mapping storage;
identifying, by the question and answer creation system, an identified set of passages in the corpus that match the filtered set of patterns in the pattern-rules mapping storage;
performing, by the question and answer creation system, pre-processing on the set of passages to select a subset of the passages in the identified set of passages to be used for generating question and answer pairs to form a selected set of passages, wherein the pre-processing collects metadata attributes of the identified set of passages to select the selected set of passages;
applying, by the question and answer creation system, the set of rules in the pattern-rules mapping storage to the selected set of passages to generate a set of question and answer pairs;
performing, by the question and answer creation system, post-processing on the set of question and answer pairs using the metadata attributes to form a final set of question and answer pairs, wherein performing post-processing comprises ordering questions by similarity; merging similar questions with the same answer; scoring similar questions with different answers; and applying an analytic algorithm to the similar questions to resolve conflicts and generate new questions; and
training a question answering system using the final set of question and answer pairs.

US Pat. No. 10,339,451

SYSTEM AND METHOD OF DEVELOPING COMPOSITION FOR POWDER MOLDING

KYUNGPOOK NATIONAL UNIVER...

8. A method of developing a composition for powder molding capable of extracting optimal compositional information on the composition in terms of a viscosity of the composition for powder molding and ratios of residual binder materials after a degreasing process, the method comprising:randomly generating ‘N’ first parent solutions, synthesizing and analyzing compositions corresponding to each of the first parent solutions and generating measurement information on viscosities of the compositions and ratios of residual binder materials after a degreasing process (first step);
generating ‘N’ first offspring solutions from the first parent solutions based on the first parent solutions and the measurement information thereon, synthesizing and analyzing compositions corresponding to each of the first offspring solutions and generating measurement information on viscosities of the respective compositions and ratios of residual binder materials after a degreasing process (second step); and
selecting ‘N’ second parent solutions based on the first parent solutions and the measurement information thereon and the first offspring solutions and the measurement information thereon, and determining whether the measurement information on the ‘N’ second parent solutions converges within a preset target range (third step),
wherein, when the measurement information on the second parent solutions converges within the preset target range, the second parent solutions are output as the optimal compositional information, and when the measurement information on the second parent solutions does not converge within the preset target range, the second and third steps are repeatedly performed based on the second parent solutions.

US Pat. No. 10,339,449

METHOD AND APPARATUS FOR ARTIFICIAL INTELLIGENCE ACCELERATION

Pure Storage, Inc., Moun...

1. An apparatus for artificial intelligence acceleration, comprising:a storage and compute system having a distributed, redundant key value store for metadata; and
the storage and compute system having distributed compute resources configurable to access, through a plurality of authorities, data in the solid-state memory, run inference with a deep learning model, generate vectors for the data and store the vectors in the key value store, the distributed compute resources configurable to store metadata for one or more buckets containing the data and create bucket views containing links to objects within the data that are contained in the one or more buckets and stored in the solid-state memory.

US Pat. No. 10,339,448

METHODS AND DEVICES FOR REDUCING DEVICE TEST TIME

Seagate Technology LLC, ...

1. A method for testing a group of electronic devices, the method comprising:receiving a first set of testing data associated with a first group of electronic devices, wherein the first set of testing data is generated during a tuning test applying a first range of testing parameters;
receiving a second set of testing data associated with the first group of electronic devices;
determining, based on the first set of testing data and the second set of testing data, a second range of testing parameters that is less than the first range of testing parameters; and
subjecting a second group of electronic devices through a tuning test applying the second range of testing parameters.

US Pat. No. 10,339,447

CONFIGURING SPARSE NEURONAL NETWORKS

QUALCOMM Incorporated, S...

1. A computer-implemented method for selecting model neurons in an artificial neural network, comprising:generating a first sparse set of decoding weights, each decoding weight corresponding to a synapse between a first neuron layer and a second neuron layer;
selecting, from the first neuron layer, a first set of model neurons corresponding to a first set of non-zero decoding weights selected from the first sparse set of decoding weights;
updating the first neuron layer to consist of the first set of model neurons; and
operating the artificial neural network with the updated first neuron layer.

US Pat. No. 10,339,446

NEUROMORPHIC DEVICE

SK HYNIX INC., Icheon (K...

1. A method of learning a synapse having a transistor of a neuromorphic device comprising:applying a first signal to a row line, the row line being electrically connected to a gate of the transistor,
applying a second signal to an additional row line, the additional row line being electrically connected to a drain of the transistor, and
applying a third signal to a column line, the column line being electrically connected to a source of the transistor,
wherein a first voltage difference between the first signal and the third signal is equal to or greater than a set voltage to change a threshold voltage of the transistor, and a second voltage difference between the second signal and the third signal is equal to or greater than the set voltage.

US Pat. No. 10,339,444

MONITORING POTENTIAL OF NEURON CIRCUITS

International Business Ma...

1. A neuromorphic electric system comprising a network of a plurality of neuron circuits, the plurality of neuron circuits being connected in series and in parallel to form a plurality of layers, whereineach of the plurality of neuron circuits includes:
a soma circuit configured to store a charge supplied thereto and to output a spike signal if a neuron potential of the soma circuit caused by the stored charge exceeds a predetermined threshold; and
a plurality of synapse circuits each configured to supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plurality of synapse circuits being one more than a plurality of neuron circuits in a prior layer that output the spike signal to the synapse circuits, with one of the plurality of synapse circuits being a control circuit,
the control circuit is configured to supply a charge to the soma circuit in response to receiving a series of pulse signals and has a same resistance value as control circuits in each of the plurality of neurons, and
the others of the plurality of synapse circuits are configured to supply a charge to the soma circuit in response to receiving a spike signal from respective corresponding neuron circuits in the prior layer.

US Pat. No. 10,339,443

SYSTEMS AND METHODS FOR PROCESSING CONVOLUTIONAL NEURAL NETWORK OPERATIONS USING TEXTURES

GoPro, Inc., San Mateo, ...

1. A system for processing convolutional neural network operations using textures, the system comprising:physical storage media storing convolutional neural network information, the convolutional neural network information defining a convolutional neural network, the convolutional neural network including layers, the layers defining operations on an input to the convolutional neural network, wherein the layers in the convolutional neural network information are formatted as shaders; and
one or more physical processors configured by machine-readable instructions to:
access the input to the convolutional neural network;
format the input as an array of textures;
store the array of textures as input information;
access the input information, the input information defining the input to the convolutional neural network, the input information formatted as the array of textures, the textures characterized by a width, a height, and a number of channels;
apply the shaders to the array of textures, wherein applying the shaders to the array of textures effectuates processing the input to the convolutional neural network through the layers of the convolutional neural network; and
obtain one or more results from applying the shaders to the array of textures.

US Pat. No. 10,339,442

CORRECTED MEAN-COVARIANCE RBMS AND GENERAL HIGH-ORDER SEMI-RBMS FOR LARGE-SCALE COLLABORATIVE FILTERING AND PREDICTION

NEC Corporation, (JP)

1. In a system comprising a processor and a memory that includes a plurality of components that are executable by the processor, the plurality of components having a data receiver component that receives training data, and a training component that trains a generative stochastic artificial neural network including hidden units u and visible units v that can learn a probability distribution over its set of inputs, said system operating according to a method comprising the following computer-executable acts:determining a corrected energy function of high-order semi-Restricted Boltzmann Machines (hs-RBMs), said determination made without self-interaction;
performing distributed pre-training of the hs-RBM by a pseudo-log likelihood method using alternating direction of multipliers (ADMM);
adjusting weights of the hs-RBM using contrastive divergence;
generating predictions by Gibbs Sampling or by determining conditional probabilities with hidden units integrated out; and
outputting the predictions so generated;
wherein the training includes a mean-covariance RBM (mcRBM) that defines a joint distribution over configurations of the visible units u and the hidden units h by an energy function in which there is no connection between hidden units and the energy function is defined by the following relationship:

where hm and hg, respectively, denotes mean hidden units and covariance hidden units.

US Pat. No. 10,339,440

SYSTEMS AND METHODS FOR NEURAL LANGUAGE MODELING

Digital Reasoning Systems...

1. computer-implemented neural network, comprising:a plurality of input neural nodes receiving input comprising an ordered list of a plurality of linguistic units with a linguistic unit omitted, each input neural node of the plurality of input neural nodes corresponding to a linguistic unit selected from the ordered list of a plurality of linguistic units, and wherein the input received by the input neural nodes is one-hot encoded;
an embedding layer comprising a plurality of embedding node partitions, wherein each of the embedding node partitions corresponds to a position in the ordered list relative to a focus term and comprises a plurality of neural nodes, wherein the focus term is an omitted linguistic unit from the ordered list of the plurality of linguistic units, the plurality of neural nodes of each of the embedding node partitions receiving an input from a separate set of the input neural nodes and generating an output by at least multiplying the input from each input neural node by one of a plurality of input weights; and
a classifier layer comprising a plurality of neural nodes, each neural node in the classifier layer configured to receive the output from each of the neural nodes of the embedding layer, to generate an output by at least multiplying the output from each neural node of the embedding layer by one of a plurality of input weights, and wherein the output corresponds to a probability that a particular linguistic unit is the focus term;
wherein the input weights for each neural node of a partition of the embedding layer are trained independently of other partitions.

US Pat. No. 10,339,439

EFFICIENT AND SCALABLE SYSTEMS FOR CALCULATING NEURAL NETWORK CONNECTIVITY IN AN EVENT-DRIVEN WAY

Thalchemy Corporation, M...

1. A scalable system for recalculating, in an event-driven manner, property parameters including connectivity parameters of a neural network, the system comprising:an input component that receives a time varying input signal;
a state machine comprising a pseudo-random number generator with a seed value, wherein the state machine is capable of recalculating property parameters of the neural network using the seed value, wherein the property parameters include connectivity among neurons of the neural network, and wherein the connectivity is deterministically generated by the pseudo-random number generator without reference to preexisting connectivity stored in memory, wherein the state machine is capable of generating a unique identifying number for each neuron in the neural network, and, wherein the state machine comprises a neuron identification counter with a first predefined initial value and a neuron connectivity counter with a second predefined initial value, wherein both the first predefined initial value and the second predefined initial value are utilized to update the state machine, and, wherein the pseudo-random number generator of the state machine comprises a Linear Feedback Shift Register (LSFR);
a storage component containing a plurality of predefined seed values from which a particular seed value is chosen for the pseudo-random number generator, wherein the number of seed values is less than the number of property parameters to be recalculated; and
an output component that generates output signals reflective of the calculated property parameters of the neural network and the input signal.

US Pat. No. 10,339,438

METHOD AND SYSTEM TO COUNT MOVEMENTS OF PERSONS FROM VIBRATIONS IN A FLOOR

1. A method of counting persons comprising:(a) producing signals from a sensor adapted to detect vibrations made by persons crossing a floor under an area connecting at least three passageways;
(b) evaluating the signals with a machine learning system trained to detect patterns of movement of persons between the passageways from vibrations in the floor;
(c) determining from outputs of the machine learning system produced on the basis of the signals that a person has entered the area by an identified passageway and that the person has exited the area by an identified passageway; and
(d) producing a count of the number of persons that have passed through the area using the combination of passageways identified by the outputs.

US Pat. No. 10,339,437

RF TAG ANTENNA AND METHOD FOR MANUFACTURING SAME, AND RF TAG

PHOENIX SOLUTION CO., LTD...

1. An RF tag antenna, comprising:a first insulating substrate having a first principal surface and a second principal surface that is opposite to the first principal surface;
a first waveguide device provided on the first principal surface;
a second waveguide device provided on the second principal surface;
a power feeding part that is provided on a side surface of the first insulating substrate and electrically connected to the second waveguide device at one end thereof; and
a short-circuit part that is provided on the side surface of the first insulating substrate and electrically connected to the first waveguide device at one end thereof and to the second waveguide device at another end thereof,
wherein the first insulating substrate, the first waveguide device, the second waveguide device, the power feeding part and the short-circuit part form a plate-shaped inverted-F antenna that receives a radio wave transmitted from a reader,
an inductor pattern formed by the first waveguide device, the short-circuit part, the second waveguide device and the power feeding part and a capacitor formed by the first waveguide device, the second waveguidedevice and the first insulating substrate form a resonantcircuit that resonates in a frequency band of the radio wave,the first insulating substrate is formed of a dielectric material having a shape of a rectangular parallelepiped that has a long side, a short side and a height,
the power feeding part and the short-circuit part are each provided on a side surface of the first insulating substrate on the short side, and
an IC chip mounting part on which an IC chip ismounted is provided on the first principal surface of thefirst insulating substrate on the short side, between the power feeding part and the first waveguide device.

US Pat. No. 10,339,435

RADIOFREQUENCY TRANSPONDER FOR A TIRE

Compagnie Generale des Et...

1. A radiofrequency transponder useable in a mass of an elastomer mixture, the radiofrequency transponder comprising:an electronic chip;
a radiating antenna structured to communicate with a radiofrequency reader, the radiating antenna being a dipole antenna formed of a single-strand, helical spring; and
a primary antenna connected electrically to the electronic chip, the primary antenna being electromagnetically coupled to the radiating antenna,
wherein the primary antenna and the electronic chip are disposed within a cylindrical cavity of the helical spring.

US Pat. No. 10,339,433

INTEGRATED POWER SOURCE ON A PAYMENT DEVICE

VISA INTERNATIONAL SERVIC...

1. A payment device comprising:an integrated power source including a piezoelectric accelerometer;
a processor in communication with the integrated power source;
an input/output circuit in communication with the processor; and
a memory in communication with the processor, the memory storing instructions that, upon execution by the processor:
activate payment functions of the payment device upon receipt of a first input by the processor from the input/output circuit,
deactivate the payment functions of the payment device after a threshold amount of time without receiving a second input by the processor from the input/output circuit,
determine a pattern of kinetic energy translation to the integrated power source,
determine the pattern matches a passcode motion stored in the memory, and
activate the payment device in response to the pattern matching the passcode motion;
wherein kinetic energy translation to the integrated power source powers the processor, memory, and input/output circuit, and causes the processor to execute the instructions, the input/output circuit comprises a heat sensitive region on the payment device, and the memory stores further instructions that, upon execution by the processor:
receive warming input from the input/output circuit via the heat sensitive region,
activate payment functions of the payment device upon receiving the warming input, and
translate kinetic energy to the integrated power source to determine that the input/output circuit has been actuated.

US Pat. No. 10,339,432

COMMUNICATION DEVICE

SONY CORPORATION, Tokyo ...

1. A communication device, comprising:a solar cell including a light receiving surface configured to receive radiated light;
an electric storage device on a back surface of the light receiving surface of the solar cell; and
a circuit board that includes a communication antenna and is on a back surface of a surface of the electric storage device which is opposite to the back surface of the light receiving surface of the solar cell.

US Pat. No. 10,339,431

INFORMATION REPRODUCTION/I/O METHOD USING DOT PATTERN, INFORMATION REPRODUCTION DEVICE, MOBILE INFORMATION I/O DEVICE, AND ELECTRONIC TOY USING DOT PATTERN

1. A voice information recording/reproducing device comprising:voice information inputting means for inputting voice information;
optical scanning means for scanning a dot pattern superimposed and printed in accordance with a given arrangement rule with a text or an illustration on a medium surface;
means for receiving an operation for associating the voice information input by the voice information inputting means to the dot pattern scanned by the optical scanning means;
storing means for storing the voice information associated by the operation; and
voice outputting means, when the dot pattern is scanned again by the optical scanning means, for reading the voice information associated with the dot pattern out of the storing means and outputting the voice information,
wherein the dot pattern comprises:
horizontally arranged dots, a predetermined number of which are equally spaced and arranged in a horizontal direction;
vertically arranged dots, a predetermined number of which are equally spaced and arranged in a vertical direction starting from the dot located at an end point of the horizontally arranged dots; and
information dots, by defining intersections of vertical lines virtually set from the horizontally arranged dots and horizontal lines virtually set from the vertically arranged dots in a horizontal direction, as lattice points, a data content of which is defined by how the information dots are shifted from the lattice points, and
wherein, an orientation of the dot pattern is signified by how one of the vertically arranged dots is shifted from the original position of the dot.

US Pat. No. 10,339,430

THREE-DIMENSIONAL PRINTING METHOD

Ricoh Company, Ltd., Tok...

1. A three-dimensional printing method for printing an image having continuity as a whole by adjacently printing a plurality of images on a print-target surface including a non-plane portion by an inkjet nozzle attached to an XY table, the method comprising:capturing a plurality of subdivided images by capturing a predetermined area of the print-target surface at fixed intervals to include an end edge portion of a previously printed image on the print-target surface, the end edge portion serving as a connection portion with an image to be printed contiguous to the printed image while causing a capture unit attached to the XY table to scan the print-target surface in XY directions in a state where the capture unit is disposed opposite to the print-target surface;
creating a composite print surface which is a plane projection of the print-target surface which is non-plane, by compositing the plurality of subdivided images captured by the capture unit;
superimposing the image to be printed contiguous to the printed image (hereinafter, the image is referred to as “image to be drawn”) on the composite print surface, and editing the image to be drawn to be continuous with the end edge portion of the printed image; and
discharging an ink on the print-target surface to perform printing by a print head attached to the XY table on the basis of an edited image to be drawn which is obtained by editing the image to be drawn.

US Pat. No. 10,339,428

INTELLIGENT SCORING METHOD AND SYSTEM FOR TEXT OBJECTIVE QUESTION

IFLYTEK CO., LTD., Hefei...

1. A method comprising:acquiring, by a processing device, an answer image of a text objective question;
segmenting, by the processing device, the answer image to obtain one or more segmentation results of an answer string to the text objective question;
determining, by the processing device, whether any of the segmentation results comprises a same number of characters as that of a standard answer to the text objective question;
if not, determining, by the processing device, that the answer is incorrect;
otherwise, based on an acoustical model of a complete character set and a general language model, performing, by the processing device, at least one of handwriting decoding and identification on the segmentation result having the same number of characters as that of the standard answer to obtain an identification confidence or the handwriting decoding and the identification on each character in the segmentation result having the same number of characters as that of the standard answer to obtain the identification confidence; and
determining, by the processing device, whether the answer is correct according to the identification confidence.

US Pat. No. 10,339,427

SUBJECT EVALUATION SYSTEM, SUBJECT EVALUATION METHOD AND RECORDING MEDIUM STORING SUBJECT EVALUATION PROGRAM

FUJIFILM Corporation, To...

1. A subject evaluation system comprising:a processor, configured to:
execute principal-subordinate relationship decision processing with regard to multiple images, wherein the principal-subordinate relationship decision processing decides a principal-subordinate relationship, which concerns two of the images, with regard to multiple subjects included in each of the two images, the principal-subordinate relationship being obtained by the processor evaluating two of the subjects based on a fixed criterion pertaining to the two images to calculate rankings or numerical values with regard to the two of the subjects in accordance with the fixed criterion, identifying one of the two subjects for which the ranking or numerical value is highest as a principal subject, and identifying the other one of the two subjects as a subordinate subject;
generate a link matrix representing link relationships of a directed graph showing the principal-subordinate relationship;
calculate components of eigenvectors based upon the generated link matrix;
calculate a subject evaluation value for every one of the subjects based upon the calculated components of the eigenvectors; and
decide an important subject from the calculated subject evaluation value.

US Pat. No. 10,339,426

INDUCTION SYSTEM FOR CROWD MONITORING

1. A system for monitoring an area, the system comprising:a processor;
an electromagnetic radiation source in communication with the processor, wherein the electromagnetic radiation source is configured to emit radiation to heat a metallic object that is in or carried by a target;
an array of temperature sensors in communication with the processor, wherein the array of temperature sensors is configured to detect a first temperature associated with the target and a second temperature associated with the target, wherein the first temperature is detected prior to emission of the radiation and the second temperature is detected subsequent to emission of the radiation; and
wherein the processor is configured to determine whether to trigger an alert based at least in part on a difference between the first temperature and the second temperature.

US Pat. No. 10,339,425

SYSTEM AND METHOD FOR CELL RECOGNITION

IMEC VZW, Leuven (BE)

1. A method for recognizing a cell, comprising:receiving an image of the cell, wherein receiving the image of the cell comprises reconstructing the image of the cell from a first hologram with its background removed;
performing edge detection on the reconstructed image of the cell;
detecting ridges within the reconstructed image of the cell; and
quantifying an internal complexity of the cell by gauging a contrast of the ridges with an average of a Laplacian on the detected ridges.

US Pat. No. 10,339,423

SYSTEMS AND METHODS FOR GENERATING TRAINING DOCUMENTS USED BY CLASSIFICATION ALGORITHMS

Symantec Corporation, Mo...

1. A computer-implemented method for generating training documents used by classification algorithms, at least a portion of the method being performed by a computing device comprising at least one processor, the method comprising:identifying a set of training documents used by a classification system to classify documents written in a first language;
generating a list of tokens from within the training documents that indicate critical terms representative of classes defined by the classification system;
determining linguistic properties of at least one token by analyzing a context in which the token is used within the set of training documents;
translating, while retaining the linguistic properties of the token, the list of tokens from the first language to a second language;
creating, based on the translated tokens, a set of simulated training documents that enables the classification system to classify documents written in the second language; and
classifying an additional document written in the second language based on the set of simulated training documents.

US Pat. No. 10,339,422

OBJECT DETECTION DEVICE, OBJECT DETECTION METHOD, AND RECORDING MEDIUM

NEC CORPORATION, Minato-...

1. An object detection device comprising:one or more processors acting as a detecting unit configured to detect an object from an input image by referring to a dictionary;
the one or more processors acting as an accepting unit configured to display, on a display device, the input image with indication that emphasizes a partial region of the detected object and accepting a selection of the partial region and an input of a class for the selected partial region through one operation of an input device;
the one or more processors acting as a generating unit configured to generate teacher data from an image of the selected partial region and the input class; and
the one or more processors acting as a learning unit configured to learn the dictionary based on the teacher data,
wherein the accepting unit accepts the selection of the partial region based on a location on the input image subjected to the one operation.

US Pat. No. 10,339,421

RGB-D SCENE LABELING WITH MULTIMODAL RECURRENT NEURAL NETWORKS

1. A system for evaluating multimodal data comprising:a multimodal data input comprising the multimodal data, the multimodal data comprising a first modality and a second modality; and
a multimodal processing module configured to:
receive the multimodal data comprising the first modality and the second modality;
evaluate the first modality using a first recursive neural network comprising a first transformation matrix;
evaluate the second modality using a second recursive neural network comprising the first transformation matrix, wherein the first transformation matrix shares memory of the first modality and the second modality between the first recursive network and the second recursive network to inform the first recursive network and the second recursive network of inter-correlations between the first modality and the second modality; and
determine an output based, at least in part, on evaluating the first modality and the second modality.

US Pat. No. 10,339,420

ENTITY RECOGNITION USING MULTIPLE DATA STREAMS TO SUPPLEMENT MISSING INFORMATION ASSOCIATED WITH AN ENTITY

Accenture Global Solution...

1. A method, comprising:receiving, by a device, a first data stream and a second data stream;
determining, by the device, that a plurality of entities are present in image data of the first data stream based on applying an object recognition technique to the image data;
analyzing, by the device, the first data stream to determine that an entity, of the plurality of entities, is unrecognizable in the image data of the first data stream based on a facial recognition technique not detecting a face of the entity;
obtaining, by the device, a common knowledge graph associated with the first data stream and the second data stream,
wherein the common knowledge graph includes information regarding the plurality of entities;
annotating, by the device, the common knowledge graph with first corresponding recognizable characteristics of the plurality of entities in the first data stream to generate a first annotated knowledge graph;
annotating, by the device, the common knowledge graph with second corresponding recognizable characteristics of the plurality of entities in the second data stream to generate a second annotated knowledge graph;
determining, by the device, whether the entity is recognizable based on the first annotated knowledge graph and the second annotated knowledge graph;
generating, by the device, metadata for the entity based on the first annotated knowledge graph and the second annotated knowledge graph; and
appending, by the device, the metadata to the first data stream to at least one of:
overlay information for the entity on the image data of the first data stream, or
replace an unrecognizable characteristic of the entity with a recognizable characteristic of the entity.

US Pat. No. 10,339,419

FINE-GRAINED IMAGE SIMILARITY

Google LLC, Mountain Vie...

1. A computer-implemented method, comprising:training an image embedding function to operate on an input image to produce as output a representation of features of the input image by at least:
selecting one or more image triplets, each image triplet of the one or more image triplets being a combination of a first image, a second image and a third image, wherein a first pairwise relevance score that measures a similarity of the first image to the second image is greater than a second pairwise relevance score that measures the similarity of the first image to the third image; and
for an image triplet of the one or more image triplets:
providing each of the first, second and third images as input to the image embedding function;
determining a performance measure of the image embedding function for the image triplet; and
adjusting the image embedding function based on the performance measure for the image triplet.

US Pat. No. 10,339,418

COMPUTER-READABLE STORAGE MEDIUM STORING IMAGE PROCESSING PROGRAM AND IMAGE PROCESSING APPARATUS

FUJITSU LIMITED, Kawasak...

1. A non-transitory computer-readable storage medium storing a program that causes a computer to perform a procedure comprising:calculating luminance differences of individual pixel pairs defined in a feature area in a source picture, the luminance differences each being a difference in luminance between pixels constituting a corresponding one of the pixel pairs;
calculating a local feature value of the feature area, based on the calculated luminance differences of the individual pixel pairs, the local feature value being a collection of bit values respectively corresponding to the individual pixel pairs,
wherein the calculating of the local feature value includes:
comparing a specific luminance difference with a specified range between a lower bound and an upper bound, the specified range including a zero point of luminance difference, the specific luminance difference having been calculated for a specific pixel pair corresponding to a specific bit value in the local feature value,
assigning a first value to the specific bit value when the specific luminance difference is greater than the upper bound of the specified range,
assigning a second value to the specific bit value when the specific luminance difference is smaller than the lower bound of the specified range, and
assigning a predetermined one of the first and second values to the specific bit value when the specific luminance difference falls in the specified range; and
defining the specified range, based on distribution of luminance differences of pixel pairs placed in one or more sample pictures at identical positions as in the source picture.

US Pat. No. 10,339,417

LEARNING CONTOUR IDENTIFICATION SYSTEM USING PORTABLE CONTOUR METRICS DERIVED FROM CONTOUR MAPPINGS

1. A computer implemented method for identifying contour groupings, within contour maps, and within at least one learning contour identification system, comprising the steps of:prepare at least one learning contour identification system for processing data types that are internal, and retrieving data types that are both internal and external, with file type format being external containers of data format described by data format in information technology, and where reading data types of whether data recalled was from internal or external format of the data type is dependent upon what stage the learning contour system resides in method execution,
provide training cases of data instances of format numerical data type for at least one learning contour identification system iteratively reading and processing same, or converting at least one training case to a system readable plurality of formatted data types for same system purpose,
transform at least one of the training cases into at least one contour map, of at least one contour, with each contour of the mapping further transformed into having at least one training contour pattern metric set, each defined entirely between two memory addresses when stored, with each contour a contour pattern metric set containing a possibility of at least one: plurality label sets, plurality coordinate point sets, plurality statistical outcome point sets, plurality calculated outcome point-sets, plurality metric instruction code-sets, and plurality of grouping contours and mappings and their sub-pattern metric sets of same,
store and label each metric of each contour into individual memory addressed locations, wherein managing appending to and removal from the memory being as determined necessary by at least one learning contour identification system's pattern identification process,
retrieve from memory, iteratively, a portion of the total finite set of stored training contour pattern metric sets, each training contour pattern metric set retrieved for the purpose of grouping contour pattern metric sets for determining a black boxed or rule-based machine instruction code set, for the classifier of at least one learning contour identification system, that when the instruction code set is tested against the remaining set of labeled and known training contour pattern metric sets, a desired level of performance presented by a confusion matrix is achieved,
store instruction code set and label as a black boxed or rule-based learned instruction set sequence, and store confusion matrix values,
provide test cases of data instances of format numerical data type for at least one learning contour identification system iteratively reading and processing same, or converting at least one test case to a system readable plurality of formatted data types for same system purpose,
transform at least one of the test cases into at least one contour map, of at least one contour, with each contour of the mapping further transformed into having at least one test contour pattern metric set, each defined entirely between two memory addresses when stored, with each contour a contour pattern metric set containing a possibility of at least one: plurality label sets, plurality coordinate point sets, plurality statistical outcome point sets, plurality calculated outcome point sets, plurality metric instruction code sets, and plurality of grouping contours and mappings and their sub-pattern metric sets of same,
store and label each metric of each contour into individual memory addressed locations, wherein managing appending to and removal from the memory being as determined necessary by at least one learning contour identification system's pattern identification process,
retrieve from memory the black boxed or rule-based labeled instruction code set, determined from the learning contour identification system, and retrieve from memory in an iterative process, test contour pattern metrics, to finalize the identification of the unknown test labeled contour pattern metric set combinations optimized in training and captured in the instruction set used to identify contour pattern of interest,
label at least one matched contour pattern metric set as an data item group of interest and compare performance to confusion matrix performance and repeat training and testing with increases or decreases in the number of contours in either test or training transformations, or both, and stop iterations of increases in contours when maximum percentage of success is achieved based on training confusion matrix performance readings,
output to display interfaces the identification of the test contour pattern of the classifier, and output the success reading for that classification from the confusion matrix along with other information pertinent to understanding output by user.

US Pat. No. 10,339,416

DATABASE SYSTEMS AND USER INTERFACES FOR DYNAMIC AND INTERACTIVE MOBILE IMAGE ANALYSIS AND IDENTIFICATION

Palantir Technologies Inc...

1. A system for matching images and interacting with an external mobile device, the system comprising:one or more computer-readable mediums configured to store computer-executable instructions; and
one or more processors, wherein the computer-executable instructions, when executed by the one or more processors, cause the system to:
receive, from an external mobile device, an image;
access a data store storing images and information associated with the images;
determine, from among the images stored in the data store, one or more closest matching images to the received image;
retrieve, from the data store, information associated with the one or more closest matching images;
transmit, to the external mobile device, the one or more closest matching images and the associated information;
receive, from the external mobile device, a request for additional information associated with a first image selected from among the one or more closest matching images; and
transmit, to the external mobile device, additional information associated with the first image, wherein the additional information comprises, at least in part, information that was not previously transmitted to the external mobile device as part of the associated information.

US Pat. No. 10,339,414

METHOD AND DEVICE FOR DETECTING FACE, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM FOR EXECUTING THE METHOD

INTEL CORPORATION, Santa...

1. A face detection device, comprising:an image dividing unit to divide an input image into a plurality of divided input image portions, the input image including a frame from among a plurality of frames of input images sequentially received during a predetermined time period;
a mode change unit to transmit the plurality of divided input image portions of a first frame in parallel when a full detection mode signal is generated for the first frame, transmit a divided input image portion including a specific region in a second frame corresponding to a specific region of the first frame at which a face is detected when a face tracking mode signal is generated for the second frame temporally succeeding the first frame, and transmit a divided input image portion including a specific region in a third frame corresponding to the specific region of the first frame in which the face is detected when a partial detection mode signal is generated for the third frame temporally succeeding the second frame;
one or more face detection units for detecting a face by resizing the plurality of divided input image portions of the first or third frame transmitted through the mode change unit and performing a face detection operation on the plurality of resized divided input image portions of the first or third frame;
one or more face tracking units for performing a face tracking operation on a surrounding area of the specific region in the divided input image portion of the second frame transmitted through the mode change unit; and
a mode change signal generation unit for generating the face tracking mode signal when the one or more face detection units indicate that a face is detected in at least one divided and resized input image portion from among the plurality of divided and resized input image portions of the first frame, and generating the partial detection mode signal when the one or more face tracking units indicate that a face is not detected in the divided input image portion of the second frame.

US Pat. No. 10,339,413

WARNING SIGN PLACING APPARATUS AND CONTROL METHOD THEREOF

Wistron Corporation, New...

1. A warning sign placing apparatus comprising:a warning sign equipment;
at least two camera units, capturing a plurality of images in a preset direction, wherein the at least two camera units have at least two different fields of view;
a control unit, coupled to the at least two camera units; and
a vehicle, having drive elements and carrying the warning sign equipment, the at least two camera units and the control unit,
wherein the warning sign placing apparatus is initially placed within a car,
wherein the control unit identifies a traveling direction of a road based on the images captured by the at least two camera units, distinguishes at least one object on the road, plans a route from the car to a target point along the road for the vehicle according to the at least one object, and controls the vehicle to travel along the route away from the car to place the warning sign equipment at the target point through the drive elements,
wherein the control unit enters its sleep state after transmitting the route to the vehicle, and the vehicle travels along the route by itself.

US Pat. No. 10,339,412

IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND STORAGE MEDIUM

Canon Kabushiki Kaisha, ...

1. An image processing apparatus comprising:at least one processor programmed to cause the image processing apparatus to:
input an image;
extract an image feature of the input image;
store a plurality of registered images that serve as search targets for a query image;
search for an image similar to the query image from among the plurality of registered images based on the extracted image feature extracted from the query image to acquire a search result image; and
if a plurality of search result images is acquired, compare a difference area between the plurality of search result images with an area of the query image corresponding to a position of the difference area.

US Pat. No. 10,339,411

SYSTEM TO REPRESENT THREE-DIMENSIONAL OBJECTS

AMAZON TECHNOLOGIES, INC....

1. A computer-implemented method comprising:accessing a query image;
determining a query feature of the query image using a scale-invariant feature transform (SIFT) algorithm;
determining a query local descriptor value produced by the SIFT algorithm with respect to the query feature;
accessing object data comprising:
an object identifier indicative of a three-dimensional (3D) object,
a feature identifier indicative of a feature on the 3D object,
a distribution identifier indicative of a type of probability distribution descriptive of a plurality of local descriptor values of the feature, each of the plurality of local descriptor values indicative of the feature as viewed from a particular camera pose,
a distribution parameter associated with the distribution identifier, wherein the distribution parameter is indicative of a constant value used to define one or more characteristics of the type of probability distribution;
determining, using the type of probability distribution and the distribution parameter, a probability that the query local descriptor value is represented by the object data;
determining the probability of the query local descriptor value exceeds a threshold value; and
generating data indicative of a match between the query feature and the feature on the 3D object.

US Pat. No. 10,339,410

COLOR EXTRACTION OF A VIDEO STREAM

Snap Inc., Santa Monica,...

1. A computer implemented method, comprising:receiving, by one or more processors, a set of images of a video stream, the set of images depicting at least a portion of a face within the video stream;
converting, by the one or more processors, a first portion of images of the set of images to a set of cylindrical coordinate representations as the set of images is being captured;
performing a first histogram equalization on the set of cylindrical coordinate representations;
detecting an area of interest for the first portion of images of the set of images, the area of interest positioned on the portion of the face within the video stream;
identifying one or more colors of the set of cylindrical coordinate representations based on the area of interest, the one or more colors identified within the portion of the face;
determining a prevailing color of the one or more colors within the area of interest;
comparing pixel values within the area of interest to a set of predetermined pixel value ranges selected from a plurality of sets of pixel value ranges each associated with an object type;
converting the prevailing color from the cylindrical coordinate representation to a color space associated with the set of images of the video stream while the set of images are being captured;
applying the prevailing color to a second portion of images of the set of images of the video stream while the set of images are being captured; and
generating a modified set of images by performing a second histogram equalization on the set of cylindrical coordinate representations of the second portion of images after applying the prevailing color.

US Pat. No. 10,339,408

METHOD AND DEVICE FOR QUASI-GIBBS STRUCTURE SAMPLING BY DEEP PERMUTATION FOR PERSON IDENTITY INFERENCE

TCL RESEARCH AMERICA INC....

1. A method for visual appearance based person identity inference, comprising:obtaining a plurality of input images, wherein the input images include a gallery set of images containing persons-of-interest and a probe set of images containing person detections, and one input image corresponds to one person;
extracting N feature maps from the input images using a Deep Neural Network (DNN), N being a natural number;
constructing N structure samples of the N feature maps using conditional random field (CRF) graphical models, comprising:
for a feature map, constructing an initial graph structure by K Nearest Neighbor (KNN) based on feature similarity in a feature space corresponding to the feature map, the graph model including nodes and edges, a node representing one person;
performing structure permutations by a plurality of iterations of KNN computation in N feature spaces with a Quasi-Gibbs Structure Sampling (QGSS) process;
assigning labels to the nodes that minimize a conditional random field (CRF) energy function over all possible labels, wherein the all possible labels represent all different persons-of-interest in the gallery set; and
deriving the N structure samples from the plurality of iterations and the assigned labels;
learning the N structure samples from an implicit common latent feature space embedded in the N structure samples; and
according to the learned structures, identifying one or more images from the probe set containing a same person-of-interest as an image in the gallery set.

US Pat. No. 10,339,407

NOISE MITIGATION IN VECTOR SPACE REPRESENTATIONS OF ITEM COLLECTIONS

MAXIM ANALYTICS, LLC, Re...

1. A computer-implemented method to mitigate noise in vector space representations of item collections, the method comprising:receiving, by one or more computing devices, a collection of items, each item characterized by a plurality of features;
preparing, by the one or more computing devices, a first vector space representative of the collection, wherein each item in the first vector space is represented by a vector that is a function of the features characterizing the item;
first identifying, by the one or more computing devices and based on information characteristic of the first vector space, only a first one of: items contributing to first vector space noise, and features contributing to first vector space noise;
first weighting, by the one or more computing devices, the first identified items and features to decrease the influence of the first identified items and features on vector spaces representative of the collection;
preparing, by the one or more computing devices, a second vector space representative of the collection based on the first weighted items and features;
second identifying, based on information characteristic of the second vector space, the first one of:
items contributing to second vector space noise and
features contributing to second vector space noise;
second weighting the second identified items and features to decrease the influence of the second identified items and features on vector spaces representative of the collection; and
preparing a third vector space representative of the collection based on the cumulatively weighted items and features, wherein each item is represented by a vector that is sum of the vectors of the features comprising the item.

US Pat. No. 10,339,406

APPARATUS AND METHOD FOR USING BACKGROUND CHANGE TO DETERMINE CONTEXT

OrCam Technologies Ltd., ...

1. An apparatus for providing feedback to a user, the apparatus comprising:an image sensor configured to be positioned for movement with a head of the user as the head moves, and to capture real time images from an environment of the user; and
at least one processor device for determining contextual information based on the real time images, the processor device being configured to:
monitor a plurality of the real time images captured by the image sensor to determine that relative motion occurs between a first portion of a scene captured in the plurality of real time images and other portions of the scene captured in the plurality of real time images;
determine that an object appears to be stationary in the first portion of the scene across the monitored real time images while the other portions of the scene appear to be moving across the monitored real time images;
determine, based on the stationary appearance of the object in the first portion of the scene across the monitored real time images while the other portions of the scene appear to be moving across the monitored real time images, that the head of the user is tracking the object included in the first portion of the scene;
obtain contextual information associated with the object that the head of the user is tracking; and
provide the feedback to the user based on at least part of the contextual information.

US Pat. No. 10,339,404

AUTOMATED FILTERING OF ITEM COMMENTS

International Business Ma...

1. A computer-implemented method for automated filtering of comments associated with a published item element, comprising executing on a computer processor the steps of:analyzing via image analysis an item that is a photograph published to an account of a user of a social network service to identify and distinguish an element that is an image of an object that is visible within the photograph item from other elements that are visible within graphic content of the published photograph item and from surrounding contextual visual image pixel data, wherein the item is published with a plurality of comments that are posted by a plurality of users of the social network service that is inclusive of the user, and wherein the surrounding contextual visual image pixel data defines a background element or a foreground element;
in response to a selection of the distinguished element of the item, analyzing text content of the plurality of comments to identify associations of the analyzed text content of the plurality of comments to the selected element; and
differentially displaying a subset of the plurality of comments to the user account of the social network in association with the published item, relative to displays of remaining others of the plurality of comments that are not within the subset, in response to determining that the or analyzed text content of each of the subset plurality of comments comprises a string text content identification of the object, and that the analyzed text content of each of the remaining others of the plurality of comments does not comprise the string text content identification of the object, wherein the string text content identification of the object is selected from the group consisting of a name of the object, a type of the object, and a category of the object.