US Pat. No. 10,341,443

MULTIMODAL CONVERSATION TRANSFER

Microsoft Technology Lice...

1. A method for managing a multimodal conversation across multiple points of presence on a communication network, the method comprising:pairing a first device with a second device;
receiving, at the first device, a multimodal conversation identifier based on the pairing, wherein the multimodal conversation identifier identifies the multimodal conversation that comprises a first communication session and a second communication session, which are executing on the second device;
accessing the multimodal conversation based on the received multimodal conversation identifier; and
updating, using the first device, one or more of the first communication session and the second communication session of the multimodal conversation.

US Pat. No. 10,341,442

DEVICE AND METHOD OF CONTROLLING THE DEVICE

Samsung Electronics Co., ...

1. A device comprising:a detector configured to detect current driving conditions of a vehicle or a user;
a communicator configured to receive a phone call or a message from a counterpart; and
at least one processor configured to:
limit notifications with respect to events that occur in the device based on the current driving conditions,
when the phone call or the message is received, determine a condition among a plurality of conditions for changing the current driving conditions, the condition being determined based on the current driving conditions detected by the detector and destination information configured by the user, the destination information corresponding to information regarding a predetermined location of an end of travel, acquired from an application installed in the device, the vehicle, or a wearable device connected to the device, and provide a state change guide corresponding to the condition for changing the current driving conditions, the state change guide comprising at least one of information informing the user of the current driving conditions or an action for the user to perform to change the current driving conditions,
limit a receiving notification with respect to the phone call or the message based on the current driving conditions,
predict a future situation based on the current driving conditions,
control the communicator to provide a response message, including a current situation based on the current driving conditions, and the predicted future situation, to the counterpart, and
when the current driving conditions change, provide the limited notifications.

US Pat. No. 10,341,441

DEVICE, SYSTEM, AND METHOD FOR GENERATING INFORMATION REPRESENTING A CONDITION OF AN AUTOMATIC DOOR

KONE CORPORATION, Helsin...

1. A device for generating information representing a condition of an automatic door, the device being arranged to the automatic door, the device comprising:an accelerometer comprising at least one internal buffer for storing data, the accelerometer being configured to obtain and buffer at least one acceleration value representing acceleration of the automatic door; and
a control unit comprising at least one processor and at least one memory for storing at least one portion of system code and any data values, the at least one processor being configured to cause the control unit at least to:
read and store the obtained at least one acceleration value from the at least one internal buffer-of the accelerometer; and
generate at least one piece of information representing the condition of the automatic door based on the at least one acceleration value for communicating the generated at least one piece of information to an external server.

US Pat. No. 10,341,440

METHOD AND DEVICE FOR TRANSFERRING MESSAGES IN A COMPUTER NETWORK

ROBERT BOSCH GMBH, Stutt...

17. A method for transferring messages in an on-board computer network of a vehicle, the method comprising:initiating a synchronization of slave nodes of an on-board computer network of a vehicle, the slave nodes including vehicle control devices which are connected to each other by data lines, and after the initiating, the synchronization of the slave nodes proceeding through a first bridge on the computer network based on synchronization messages;
receiving, by a transmitter in the first bridge, a plurality of messages, the messages including (i) the synchronization messages, and (ii) other messages which are not the synchronization messages, the synchronization messages including first synchronization messages sent from a Grand Master node on the computer network to the slave nodes for the synchronization of the slave nodes, and second synchronization messages sent from the slave nodes to the Grand Master node in response to the first synchronization messages for the synchronization of the slave nodes, wherein the slave nodes are synchronized by the Grand Master node using the synchronization messages;
storing, by the transmitter, only the synchronization messages of the received plurality of message in a first queue, and storing, by the transmitter, the other messages of the received plurality of messages which are not the synchronization messages in a second queue different from the first queue;
operating the transmitter in a first mode until the synchronization of the slave nodes has completed, wherein during the operating in the first mode, the transmitter performs:
(i) checking whether the first queue is empty or not empty,
(ii) determining the first queue is not empty, and
(iii) based on determining the first queue is not empty: (a) transmitting in the computer network, by the transmitter, only the synchronization messages, and (b) blocking, by the transmitter, the other messages which are not the synchronization messages, so that a course of the synchronization of the nodes is deterministic;
detecting, by the transmitter, that the synchronization of the slave nodes has completed; and
after the detecting, switching the transmitter from operating in the first mode to operating in a second mode, wherein in the second mode, the transmitter does not block the other messages which are not the synchronization messages.

US Pat. No. 10,341,438

DEPLOYING AND MANAGING CONTAINERS TO PROVIDE A HIGHLY AVAILABLE DISTRIBUTED FILE SYSTEM

Verizon Patent ad Licensi...

1. A device, comprising:one or more processors, implemented at least partially in hardware, to:
receive information indicating a set of instructions associated with a microservices application,
the microservices application being associated with one or more microservices;
generate a deployment specification based on receiving the information indicating the set of instructions;
deploy one or more containers and one or more replicate containers based on generating the deployment specification,
the one or more containers and the one or more replicate containers being associated with the one or more microservices, and
the one or more containers and the one or more replicate containers being associated with a distributed file system;
provide an instruction to one or more computing nodes that are associated with the one or more replicate containers,
the instruction causing the one or more replicate containers to manage traffic flow associated with the one or more microservices, and
the instruction causing the one or more replicate containers to synchronize to the one or more containers to provide the one or more containers with metadata and data associated with the traffic flow;
receive information associated with modifying the one or more microservices based on deploying the one or more containers and the one or more replicate containers;
modify the one or more microservices, as one or more modified microservices, based on receiving the information associated with modifying the one or more microservices; and
deploy the one or more modified microservices.

US Pat. No. 10,341,437

ADDING LOGICAL SHARDING TO A DISTRIBUTED SYSTEM WITH ONLY PHYSICAL SHARDING

Nicira, Inc., Palo Alto,...

1. A method for processing domain objects in a distributed system using logical sharding, the method comprising:receiving, by a central control plane (CCP) node of a plurality of CCP nodes, a domain object;
determining, by the CCP node, whether the domain object is present in a shared data store by comparing an object identifier of the domain object to object identifiers in the shared data store;
upon determining the domain object is present in the shared data store, determining whether a correlation identifier of the domain object matches a respective correlation identifier corresponding to the domain object in the shared data store;
upon determining the domain object is not present in the shared data store or upon determining the correlation identifier does not match the respective correlation identifier:
determining, by the CCP node, whether the CCP node is a logical master of the domain object;
upon determining the CCP node is the logical master of the domain object:
generating, by the CCP node, a status for the domain object based on the domain object; and
storing the status and the domain object in the shared data store, wherein the shared data store is configured to notify the plurality of CCP nodes of the stored status and domain object.

US Pat. No. 10,341,436

USING CLOUD STORAGE AS TEMPORARY CACHE FOR BACKUP

Dell Products L.P., Roun...

1. A computer-implemented method, comprising:storing content on a computing device;
determining that a private network is inaccessible to the computing device;
determining that a plurality of cloud storage services, including a first cloud storage service and a second cloud storage service, are accessible by the computing device;
determining, based on an available storage capacity of the cloud storage service, that the content is greater than a size threshold associated with the first cloud storage service;
dividing the content into a plurality of portions, wherein a size of each portion of the plurality of portions is less than the size threshold;
storing a first portion of the content from the computing device to the first cloud storage service, wherein a size of the first portion is less than the size threshold;
storing a remaining portion of the content from the computing device to the second cloud storage service;
accessing a first manifest file stored on the first cloud storage service, and a second manifest file stored on the second cloud storage service;
determining from the first manifest file that the content has been downloaded from the first cloud storage service;
determining from the second manifest file that the content has been downloaded from the second cloud storage service; and
deleting the content from the computing device.

US Pat. No. 10,341,435

HIGH PERFORMANCE CLOUD STORAGE

CenturyLink Intellectual ...

1. A method of providing storage within a cloud-computing environment to meet storage performance criteria of a customer, the method comprising:providing, with a provisioning computer, an application programming interface (“API”) for provisioning cloud storage for a host computer;
receiving, with the provisioning computer and via the API, a set of information defining storage needs of the host computer;
determining, with the provisioning computer, a storage type based on the storage needs of the host computer, the storage type including a performance dimension, a capacity dimension, and a cost dimension;
accessing the host computer with the provisioning computer using the API;
provisioning storage, with the API, from a cloud storage array to allocate a portion of the cloud storage array to the host computer, the portion of the cloud storage array having the determined storage type, wherein the cloud storage array comprises multiple tiers of storage, each tier of storage having a different performance capability, wherein the allocated portion of the cloud storage array comprises at least a first sub-portion from a first tier of the cloud storage array and a second sub-portion from a second tier of the cloud storage array, wherein provisioning storage comprises reserving the portion of the cloud storage array for use by the host computer, instead of providing the host computer with shared usage of a storage pool;
provisioning, via the provisioning computer, a first connection between the host computer and the first sub-portion, the first connection configured to support a performance capability associated with the first tier of the cloud storage array;
provisioning, via the provisioning computer, a second connection between the host computer and the second sub-portion, the second connection configured to support a performance capability associated with the second tier of the cloud storage array, the second connection having a bandwidth that is lower than a bandwidth of the first connection; and
storing, with the provisioning computer, a provisioning record indicating the portion of the cloud storage array allocated to the host computer;
wherein at least one of the first sub-portion from the first tier of the cloud storage array or the second sub-portion from the second tier of the cloud storage array had not previously been provisioned to the host computer, and the at least one of the first sub-portion or the second sub-portion is newly provisioned to the host computer without rebooting the host computer, wherein the host computer is a discrete physical computer.

US Pat. No. 10,341,434

METHOD AND SYSTEM FOR HIGH AVAILABILITY TOPOLOGY FOR MASTER-SLAVE DATA SYSTEMS WITH LOW WRITE TRAFFIC

OATH INC., New York, NY ...

1. A method implemented on a computer having at least one processor, a storage, and a communication platform for a data system, comprising:receiving, by a data access request receiver, a data access request to access data in the data system, wherein the data system comprises a plurality of data centers with one read/write master server designated to handle write and consistent read requests and a plurality of read master servers designated to handle normal read requests, wherein the read/write master server and the plurality of read master servers in the data system form a ring structure and each is connected to a corresponding slave server;
invoking, by a read master communication unit, one of the plurality of read master servers if the received data access request is a normal read request;
invoking, by a main master communication unit, the read/write master server if the received data access request is either a write request or a consistent read request;
receiving, by a response processing unit, a response from a master invoked to handle the received data access request; and
responding, by the response processing unit, to the data access request based on the received response.

US Pat. No. 10,341,433

COPY AND PASTE BETWEEN DEVICES

CA, Inc., New York, NY (...

1. A method comprising:detecting a copy operation to copy content from a first application on a first device;
based on detection of the copy operation to copy the content from the first application, publishing the content to a web server running on the first device and the web server indicating a universal resource locator for retrieving the content;
after the web server indicates the universal resource locator, a second device detecting a paste operation for a second application on the second device; and
based on detecting the paste operation, the second application retrieving the content from the web server via the universal resource locator to perform the paste operation with the retrieved content, wherein the retrieving is directly between the first and second devices without an intermediary device.

US Pat. No. 10,341,432

SYSTEM FOR OPTIMIZING WEB PAGE LOADING

Honeywell International I...

1. A system for optimizing web application loading, comprising:a web browser stored on a computing device configured to make a request to a web server for resources to create a web application; and
an embedded device communicatively coupled to the web server, the embedded device including:
a special-purpose computing system having a processor and a plurality of modules, wherein each of the plurality of modules comprises one or more software components having a plurality of resources and instructions and the processor is configured to:
receive a request from the web server for a first resource from a first module of the plurality of modules;
obtain the instructions from the first module in response to receiving the request for the first resource
identify a second resource from a second module of the plurality of modules that is needed by the web browser to create the web application, wherein the instructions disclose to the processor that the second module has the second resource that is needed based on the first resource that is requested by the web server;
obtain the first resource from the first module and the second resource from the second module;
group the first resource and the second resource into a smaller single resource or into one file;
send a response that includes the smaller resource or the one file to the web server to be forwarded to the computing device; and
automatically send an updated smaller single resource or an updated one file to the web server to be forwarded to the computing device when the first resource or the second resource is upgraded; and
wherein:
the embedded device is configured to receive an upgrade for the first resource or the second resource from the web server and in response, the processor is further configured to:
identify the upgrade for the first resource or the second resource;
group the first resource or the second resource-into the updated smaller single resource or into the updated one file; and
the updated smaller single resource or the updated one file is forwarded to the computing device without receiving another request for the first resource or the second resource from the computing device.

US Pat. No. 10,341,431

SYSTEM AND METHOD FOR ANNOUNCING CRYPTOGRAPHIC KEYS ON A BLOCKCHAIN

1. A method for a proof-of-work based announcement of a public/private key pair used in a shared ledger distributed through a peer-to-peer network comprising the following steps:(A) generating a key announcement message for the public/private key pair;
(B) constructing a data message comprising the key announcement message and a nonce;
(C) applying one or more hash functions to the data message to produce an output;
(D) determining whether the output meets or fails to meet a target;
(E) if the output fails to meet the target selecting a new nonce, replacing the nonce in the data message with the new nonce, and repeating steps (C)-(D) until the output meets the target;
(F) transmitting the data message to the peer-to-peer network;
(G) appending the data message, by the peer-to-peer network, to the shared ledger; and
(H) rejecting, by the peer-to-peer network, any request to append to the shared ledger a further message signed by the private key of the public/private key pair prior to publication of the key announcement message.

US Pat. No. 10,341,430

SYSTEM AND METHOD FOR PEER GROUP DETECTION, VISUALIZATION AND ANALYSIS IN IDENTITY MANAGEMENT ARTIFICIAL INTELLIGENCE SYSTEMS USING CLUSTER BASED ANALYSIS OF NETWORK IDENTITY GRAPHS

SailPoint Technologies, I...

1. An identity management system, comprising:a graph data store;
a processor;
a non-transitory, computer-readable storage medium including computer instructions for:
obtaining identity management data from one or more identity management systems in a distributed enterprise computing environment, the identity management data comprising data on a set of identities and a set of entitlements associated with the set of identities utilized in identity management in the distributed enterprise computing environment;
evaluating the identity management data to determine the set of identities and a set of entitlements associated with the set of identities;
generating a first identity graph from the identity management data by:
creating a node of the first identity graph for each of the determined set of identities,
for each first identity and second identity that share at least one entitlement of the set of entitlements, creating an edge of the first identity graph between a first node representing the first identity and a second node of the identity graph representing the second identity, and
generating a similarity weight for each edge of the first identity graph between each first node and second node based on a number of the set of entitlements shared between the first identity represented by the first node and the second identity represented by the second node;
storing the first identity graph in the graph data store;
pruning the set of edges of the first identity graph to generate a second identity graph based on the similarity weight associated with each edge of the first identity graph and a pruning threshold;
storing the second identity graph in the graph data store;
clustering the set of identities represented by the nodes of the second identity graph into a set of peer groups based on the second identity graph, including the nodes of the second identity graph representing the set of identities, the edges of the second identity graph and the similarity weights of each of the edges of the second identity graph;
associating each of the set of identities with a corresponding peer group; and
generating an interface based on the second identity graph and the association between each of the set of identities and the corresponding peer group.

US Pat. No. 10,341,429

APPARATUS AND METHOD FOR CONFIGURING SERVICE FUNCTION PATH OF SERVICE FUNCTION CHAIN BASED ON SOFTWARE DEFINED NETWORK

ELECTRONICS AND TELECOMMU...

1. An apparatus for configuring a service function path (SFP) for a software defined network (SDN) based service function chain (SFC), comprising at least one processor configured to execute instructions to implement:an SFC configuration unit configuring an SFC, which is a set of ordered service functions (SFs), by reflecting requirements of a flow flowing into a network;
a primary SFP generation unit generating a primary SFP through which the flow is to be actually transmitted in the network according to the SFC;
a secondary SFP generation unit generating a secondary SFP against an error of the primary SFP; and
a flow transmission control unit controlling a transmission path through which the flow is transmitted to be at least one of the primary SFP or the secondary SFP;
wherein the flow transmission unit comprises:
an SF and SFP error detection unit checking whether a network link error or an SF operation error occurs on the primary SFP while the flow is being transmitted through the primary SFP, and notifying of the network link error or the SF operation error to an SF and SFP management unit and an SF and SFP replacement and reconfiguration unit in response to a determination that the network link error or the SF operation error has occurred on the primary SFP;
the SFP replacement and reconfiguration unit performing a task of replacing the transmission path of the flow from the primary SFP in which the network link error or the SF operation error has occurred to the secondary SFP;
the SF and SFP management unit instructing the SFP replacement and reconfiguration unit to substitute the primary SFP with the secondary SFP such that a flow to be transmitted through the primary SFP is transmitted through the secondary SFP and the secondary SFP is configured to be a new primary SFP, and to generate a new secondary SFP for the new primary SFP; and
a flow forwarding rule provision unit reconfiguring a flow forwarding rule according to the new primary SFP when configuration for the new primary SFP is completed.

US Pat. No. 10,341,428

SYNCHRONIZED RELEASE OF RESOURCES USED IN DEFERENTIAL CLOUD SERVICES

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method of using a set of servers to provide deferential services that have a pre-negotiated time for notice to release the servers, the method comprising:defining, by a deferential cloud service broker, a virtual checkpoint frame interval that is constrained to a duration of up to half of the pre-negotiated time for notice to release the servers;
collecting, by a flow controller, packets and transactions occurring during the virtual checkpoint frame interval that are processed by a current one of the servers;
responsive to an end of the virtual checkpoint frame interval,
(i) writing, by the flow controller to a shared state database, a state of processing of the packets and transactions occurring during the virtual checkpoint frame interval, and
(ii) releasing, by the flow controller, the packets and transactions occurring during the virtual checkpoint frame interval; and
copying, by the flow controller, the packets and transactions occurring during the virtual checkpoint frame interval, and the state, from the current one of the servers to another one of the servers for subsequent processing, responsive to an indication of an instance loss on the current one of the servers.

US Pat. No. 10,341,427

FORWARDING POLICIES ON A VIRTUAL SERVICE NETWORK

A10 Networks, Inc., San ...

1. A method for processing a client service session of a network service and forwarding the client service session to a pool of service load balancers using at least one packet forwarding policy in a virtual service network, the virtual service network comprising at least one network node and the pool of service load balancers serving a virtual service associated with a virtual service network address, comprising:receiving a virtual service session request from a client device by the at least one network node, the virtual service session request comprising the virtual service network address for the virtual service served by the pool of service load balancers and a client device network address;
selecting a service load balancer based on the at least one packet forwarding policy by the at least one network node, wherein the selecting comprises:
determining whether a first packet forwarding policy or a second packet forwarding policy is applied to the virtual service session request, wherein a client network address of the first packet forwarding policy is different from a client network address of the second packet forwarding policy, the determining comprising:
comparing the client network address and a virtual service network address of the second packet forwarding policy with the client device network address and the virtual service network address of the virtual service session request;
in response to not finding a match between the client network address of the second packet forwarding policy and the client device network address, comparing the client network address and a virtual service network address of the first packet forwarding policy with the client device network address and the virtual service network address of the virtual service session request; and
in response to finding a match between the client network address and the virtual service network address of the first packet forwarding policy with the client device network address and the virtual service network address of the virtual service session request, applying the first packet forwarding policy to the virtual service session request;
sending the virtual service session request to a selected service load balancer by the at least one network node;
establishing a virtual service session with the client device by the selected service load balancer;
sending a virtual service request through the established virtual service session to the selected service load balancer by the client device; and
sending a virtual service data packet from the client device to a server by the selected service load balancer.

US Pat. No. 10,341,426

MANAGING LOAD BALANCERS ASSOCIATED WITH AUTO-SCALING GROUPS

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:receiving a request to adjust a quantity of load balancers assigned to an auto-scale group, the auto-scale group comprises a set of computer instances, wherein a size of the auto-scale group is managed in accordance with one or more attributes determined by a customer;
updating a load balancer database with identifiers for one or more load balancers and assigning, in the load balancer database, a state to each of the one or more load balancers;
executing a background process configured to fulfill at least a portion of the request by at least modifying an assignment of the set of computer instances with a load balancer;
determining resource utilization of the set of computer instances assigned to the load balancer; and
updating, based at least in part on the determination and the assignment modifications of the set of computer instances, the state of the load balancer in the load balancer database.

US Pat. No. 10,341,425

SYSTEMS, METHODS, AND COMPUTER READABLE MEDIA FOR SHARING AWARENESS INFORMATION

Apple Inc., Cupertino, C...

1. A portable device comprising:a plurality of sensors including:
a first set of one or more environment sensors that measure information of an environment, and
a second set of one or more motion sensors comprising an accelerometer configured to measure acceleration of the portable device as a user moves with the portable device;
wireless communications circuitry; and
control circuitry coupled to the accelerometer and the wireless communications circuitry, the control circuitry operative to:
receive a request for sensor information from a mobile phone,
determine the request is for acceleration information,
based on the request being for acceleration information and the plurality of sensors including the accelerometer, detect the acceleration information using the accelerometer,
display, at a user interface of the portable device, a prompt for a user to allow or disallow transmission of the acceleration information to the mobile phone; and
in response to receiving an input from the user allowing the transmission of the acceleration information, transmit, via the wireless communications circuitry, the acceleration information to the mobile phone.

US Pat. No. 10,341,424

ANNOTATIONS OF OBJECTS IN MULTI-DIMENSIONAL VIRTUAL ENVIRONMENTS

GOOGLE LLC, Mountain Vie...

1. A method comprising:enabling participation by a first client in a first multi-dimensional virtual environment of
a virtual system including a plurality of multi-dimensional virtual environments;
determining a search query from a communication between the first client and a second client participating in a second multi-dimensional virtual environment;
searching a database to identify an object that has object information satisfying the search query, the database including virtual environment data describing the plurality of multi-dimensional virtual environments; and
transmitting the object information to the first client.

US Pat. No. 10,341,423

METHOD AND APPARATUS FOR DISTRIBUTING CONTENT USING A MOBILE DEVICE

MOTOROLA MOBILITY LLC, C...

1. A method performed by a server for enabling distribution of content using a mobile device, the method comprising:receiving, from a first mobile device, a first request for first content identified by a first resource identifier, wherein the first content comprises a first object referred to in the first request, and wherein the first request also refers to a second object;
receiving, with the first request for the first content, a set of presence codes that each indicate proximity of a mobile device without identifying a user of the mobile device, wherein the set of presence codes includes a first presence code for the first mobile device and at least one other presence code for one or more mobile devices in proximity to the first mobile device;
selecting a set of allocated resource identifiers associated with one or more presence codes, in the set of presence codes, for one or more of the mobile devices in proximity to the first mobile device having the first content cached therein, wherein each allocated resource identifier in the set is different than the first resource identifier, and wherein the set of allocated resource identifiers includes second and third allocated resource identifiers and associated second and third presence codes, of the set of presence codes, to retrieve the first and second objects from two different mobile devices in proximity to the first mobile device;
sending, to the first mobile device, the set of allocated resource identifiers and associated presence codes to retrieve the first content cached in the one or more mobile devices in proximity to the first mobile device.

US Pat. No. 10,341,422

ENTITY PAIRING FOR A MULTI-USER CAX ENVIRONMENT

UNITED TECHNOLOGIES CORPO...

1. A system for collaborating on a component, comprising:a computing device configured to execute a first multi-user computer-aided technologies (CAx) environment including a synchronization module;
wherein the first multi-user computer-aided technologies (CAx) environment includes a data module configured to access data relating to a component design from at least one database and configured to store a local copy of the component design in the first multi-user computer-aided technologies (CAx) environment; and
wherein the synchronization module is configured to cause a first entity in the component design to update in the first multi-user computer-aided technologies (CAx) environment according to at least one pairing criterion in response to a predetermined time threshold being met, the predetermined time threshold being an elapsed time since the data module last accessed data corresponding to the first entity in the at least one database and/or the local copy, the at least one pairing criterion relating to a second entity in the component design, wherein the first entity and the second entity are separate and distinct geometric features in a single instance of the component design, and the at least one pairing criteria is set prior to creation of the first entity.

US Pat. No. 10,341,421

ON-DEVICE SOCIAL GROUPING FOR AUTOMATED RESPONSES

SAMSUNG ELECTRONICS CO., ...

1. A method, comprising:determining, by a device, a set of attributes associated with interactions between a user and a set of contacts, the set of attributes associated with the interactions related to the device;
wherein the set of attributes includes ratios of incoming to outgoing calls between the user and the set of contacts;
classifying, using the device, the set of contacts into a plurality of groups by processing the set of attributes for the set of contacts through a plurality of ordered classification stages, wherein the plurality of groups are hierarchically ordered with at least one group of the plurality of groups being a subgroup of another group of the plurality of groups;
associating, using the device, an action rule with a selected group of the plurality of groups, wherein the action rule specifies a plurality of automatic responses performed by the device applied to communications received from contacts belonging to the selected group;
presenting, on a display screen of the device, the plurality of automatic responses as options in response to receiving a selected communication in the device from a contact belonging to the selected group and applying, using the device, the action rule to the selected communication; and
performing a particular automatic response from the plurality of automatic responses, using the device, in response to the device receiving the selected communication from the contact in the selected group and receiving a user selection of the particular automatic response from the plurality of automatic responses presented as options.

US Pat. No. 10,341,420

APPROACHES FOR PREPARING AND DELIVERING BULK DATA TO CLIENTS

AMAZON TECHNOLOGIES, INC....

1. A computer-implemented method comprising:generating, at a multi-tenant computing environment, a first database having a first schema and a first data model;
receiving, from a client computing device, a request to create a second database having a second schema and a second data model, wherein the second schema differs from the first schema and the second data model differs from the first data model;
receiving, from the client computing device, a first transformation specification comprising a description of the second schema;
receiving, from the client computing device, a second transformation specification comprising a mapping between the first data model and the second data model;
determining, at the multi-tenant computing environment, a transformation between the first schema and the second schema, the transformation being based at least on the first transformation specification and the second transformation specification;
generating, at the multi-tenant computing environment, the second database based on the transformation, the second database compatible with the second schema and the second data model;
storing the second database at the multi-tenant computing environment;
generating a link to the second database; and
transmitting the link from the multi-tenant computing environment to the client computing device in response to a request from the client computing device.

US Pat. No. 10,341,419

TRANSFORMATION OF A CONTENT FILE INTO A CONTENT-CENTRIC SOCIAL NETWORK

TNQ BOOKS AND JOURNALS PR...

1. A computer implemented method for transforming a content file into a content-centric social network with managed connectivity and indexable touchpoints, the method employing a file networking system comprising at least one processor configured to execute computer program instructions for performing the method comprising:injecting a tracking code with widgets for user activities into each of one or more portable copies of the content file by the file networking system based on preconfigured criteria in response to a request to access the content file from one or more first user devices, wherein the file networking system transforms said each of said one or more portable copies of the content file into one or more homed portable copies of the content file by embedding the tracking code into said each of said one or more portable copies of the content file, and wherein the file networking system radio collars said each of said one or more portable copies of the content file for tracking said each of said one or more portable copies;
distributing the one or more portable copies of the content file with the injected tracking code in the each of the one or more portable copies of the content file to one or more second user devices through a network by the file networking system based on invite information received by the file networking system with the request to access the content file, wherein the one or more second user devices comprise the one or more first user devices and invitee user devices addressed in the invite information;
establishing a bidirectional communication between the file networking system and the distributed one or more portable copies of the content file on the one or more second user devices through the network by the file networking system;
receiving tracking information comprising touchpoints by the file networking system based on usage of the distributed one or more portable copies of the content file via the established bidirectional communication while managing to cover for loss of connectivity over the network, wherein the touchpoints are defined by user interactions with the distributed one or more portable copies of the content file on the one or more second user devices and are identified by the injected tracking code in each of the distributed one or more portable copies of the content file on the one or more second user devices, wherein the file networking system inserts hidden inline frame tags automatically into a source file from which the distributed one or more portable copies of the content file is downloaded to the one or more second user devices, wherein the file networking system establishes RESTful services for receiving the tracking information from said each of the distributed one or more portable copies of the content file stored on the one or more second user devices, wherein the file networking system establishes a signaling handshake between the inline frame tag in said each of the distributed one or more portable copies of the content file and the RESTful services established on the file networking system, wherein when any of said distributed one or more portable copies of the content file is in use, the file networking system receives a signal from the inline frame tag in said distributed one or more portable copies of the content file being used through the RESTful services, wherein the received signal comprises the tracking information of said distributed one or more portable copies of the content file being used;
indexing the touchpoints in the received tracking information by the file networking system for tracking the usage of the distributed one or more portable copies of the content file;
creating a satellite internet of users of the distributed one or more portable copies of the content file on the one or more second user devices by the file networking system based on the invite information and the tracked usage of the distributed one or more portable copies of the content file; and
establishing communication between users of the distributed one or more portable copies of the content file on the one or more second user devices in the created satellite internet of users by the file networking system using one or more of the widgets for the user activities through the injected tracking code in the each of the distributed one or more portable copies of the content file and the indexed touchpoints, thereby transforming the content file into the content-centric social network with the managed connectivity and the indexable touchpoints.

US Pat. No. 10,341,395

MODIFYING SIGNAL ASSOCIATIONS IN COMPLEX COMPUTING NETWORKS

1. An apparatus for modifying a temporal signal association in a complex computing network such that a future computing operation is executed based on the modified temporal signal association, the modification of the temporal signal association being necessarily rooted in computing technology, the apparatus for:determining association of a movable matching signal with a first signal;
receiving registration of a second signal from a signal matching server;
in response to receiving the registration of the second signal from the signal matching server, disassociating the movable matching signal from the first signal and associating the movable matching signal to the second signal, wherein:
a computing operation is executed using the second signal;
in response to determining the computing operation being executed using the second signal, a determination is made whether a matching signal is associated with the second signal; and
in response to determining the movable matching signal is associated with the second signal, the computing operation is executed based on the movable matching signal and the second signal,
wherein the movable matching signal is disassociated from the second signal upon execution of the computing operation in response to determining an attribute associated with the movable matching signal is extinguished,
wherein the computing operation is a real-time computing operation conducted at an input signal system comprising a real-time sensor,
wherein:
a second computing operation is executed using the first signal;
in response to determining the second computing operation being executed using the first signal, a determination is made whether a matching signal is associated with the first signal, and
in response to determining the movable matching signal is not associated with the first signal, the second computing operation is executed based on the first signal, and not based on the movable matching signal,
wherein the second computing operation is a second real-time computing operation conducted at a second input signal system comprising a second real-time sensor, and
wherein the first signal and the second signal are not temporal.

US Pat. No. 10,341,392

METHOD AND APPARATUS FOR CONTROLLING SESSION BETWEEN DEVICES ON NETWORK INCLUDING MULTIPLE DEVICES

LG ELECTRONICS INC., Seo...

1. A session controlling method of a first switch device between devices on a plurality of networks, the session controlling method comprising:receiving, using a first protocol, a session control request message from a control device;
transmitting, using a second protocol, a triggering message for a specific control operation to a source device based on the received session control request message;
performing session control between the source device and a sink device by transmitting and receiving at least one message based on the triggering message;
receiving, using the second protocol, a triggering response message for indicating a result of the performing the session control from the source device;
transmitting, using the first protocol, a session control response message corresponding to the session control request message to the control device; and
determining whether the session control request message represents a session creation request message, a session termination request message or a session status request message,
wherein, in response to determining that the session control request message represents the session creation request message, the performing the session control between the source device and the sink device comprises:
transmitting a first message for a session route query to a second switch device; and
receiving a second message for a session route set from the second switch device in response to the first message,
wherein the second switch device is connected to the sink device using a High Definition Multimedia Interface (HDMI), wherein the first switch device, the sink device and the control device are included in an HDBaseT Plug & Play (HPnP) network and the source device is not included in the HPnP network, and
wherein the first switch device represents the source device in the HPnP network and takes a role of proxy to communicate between the source device and the control device.

US Pat. No. 10,341,352

GAZE INITIATED INTERACTION TECHNIQUE

1. A method for enabling a network service to enhance user anonymity whilst mediating interaction between users of personal point-of-interest beacons, the method comprising:linking an account of a first social network user to a unique identifier relating to a personal point-of-interest beacon of a second social network user, wherein the unique identifier is broadcast as an anonymous unique identifier that continuously changes while it is active;
accessing a first user profile of the first social network user, wherein the first user profile includes a plurality of inclusion criteria, a plurality of exclusion criteria, and interaction preferences;
accessing a second user profile of the second social network user, wherein the second user profile includes profile filtering parameters and personal data;
mediating communication authorization between the first social network user and the second social network user based on matching the plurality of inclusion and exclusion criteria of the first user profile with the profile filtering parameters of the second user profile;
receiving an authorization request from the second social network user to interact with the first social network user; and
selecting an interface for interaction between the second social network user and the first social network user, wherein the selection is based on the interaction preferences.

US Pat. No. 10,341,344

METHODS AND SYSTEMS FOR PERSISTENT CROSS-APPLICATION MOBILE DEVICE IDENTIFICATION

The 41st Parameter, Inc.,...

1. A system for persistently identifying a mobile device across applications, the system comprising:a memory which comprises:
a first sandbox associated with a first application;
a second sandbox associated with a second application; and
a persistent shared storage configured to store a universal device identifier which identifies a mobile device across the first application and the second application; and
a processor programmed to:
execute the first application in the first sandbox, wherein the first application is restricted from accessing the second sandbox;
execute the second application in the second sandbox, wherein the second application is restricted from accessing the first sandbox;
receive a first request from the first application to access information associated with the mobile device, wherein the first request comprises the universal device identifier;
receive a second request from the second application to access the information associated with the mobile device, wherein the second request comprises the universal device identifier;
identify data associated with the first application indicative of a fraud;
link the data associated with the first application indicative of the fraud with the universal device identifier;
store the data associated with the first application indicative of the fraud in the persistent shared storage associated with the universal device identifier; and
in response to the second request from the second application to access information associated with the mobile device, access the persistent shared storage associated with the universal device identifier and return a data packet comprising the data associated with the first application indicative of the fraud to the second application.

US Pat. No. 10,341,299

COLLECTING FIREWALL FLOW RECORDS OF A VIRTUAL INFRASTRUCTURE

Nicira, Inc., Palo Alto,...

1. A computer-implemented method for collecting firewall flow records, the method comprising:receiving firewall flow records from a plurality of data end nodes of a virtualized infrastructure comprising a distributed firewall according to a collection schedule, wherein the collection schedule defines which data end nodes of the plurality of data end nodes from which firewall flow records are collected, a frequency of collection of firewall flow records from the data end nodes, and an amount of firewall flow records collected from the data end nodes;
processing received firewall flow records received at a firewall flow record collection queue, such that the received firewall flow records are prepared for storage at a flow record data store; and
dynamically adapting the collection schedule based at least in part on the processing of the received firewall flow records to control data loss based on available system resources, such that the firewall flow record collection queue is available for processing firewall flow records prior to receiving additional firewall flow records from the data end nodes.

US Pat. No. 10,341,279

ACTION LINKS

salesforce.com, inc., Sa...

1. A method of delivering customized action options that integrate a feed system with a non-feed system, the method including:storing an action-link-group, the action-link-group including a plurality of action links, an executions-allowed parameter, and a category parameter indicating a display attribute of the plurality of action links within the feed system, wherein an action link of the plurality of action links is stored with information including:
a label for the action link,
an action-link-URL referencing an API entry of the non-feed system,
an action type indicating a type of action to be taken with respect to the action-link-URL in response to invoking the action link, and
authorization data to be passed during invocation of the action link;
integrating the action-link group as a feed item of the feed system based on the category parameter, wherein an execution status of the action link is maintained with the feed item for comparison with the executions-allowed parameter;
receiving an invocation request, from a user authenticated with a host-user ID, the invocation request including the action link of the plurality of action links;
invoking the action-link-URL with the authorization data;
receiving third-party data from the non-feed system generated responsive to invoking the action-link-URL; and
causing display of the third-party data from the non-feed system as a feed item of the feed system.

US Pat. No. 10,341,241

HISTORY-BASED CLASSIFICATION OF TRAFFIC INTO QOS CLASS WITH SELF-UPDATE

HUGHES NETWORK SYSTEMS, L...

1. A method of traffic classification, comprising:receiving, at a traffic classifier, a first flow packet of a current traffic flow;
identifying, by the traffic classifier, a target destination of the current traffic flow based on the first flow packet;
checking a history, by the traffic classifier, wherein the history associates a plurality of target destinations with an associated classification type, wherein the history comprises a lookup table mapping one or more IP addresses to one or more FQDNs, and a lookup table mapping each FQDN of the one or more FQDNs to a quality of service (“QoS”) class, wherein the lookup table mapping each FQDN of the one or more FQDNs to a QoS class is updated over time using received traffic flows; and
using at least the check of the history, tagging, by the traffic classifier, the current traffic flow as belonging to the classification type associated with the target destination;
wherein the classification type comprises one of a plurality of QoS classes having one or more QoS requirements.

US Pat. No. 10,341,240

EQUATION-BASED RATE CONTROL USING NETWORK DELAY FOR VARIABLE BITRATE SCENARIOS

Microsoft Technology Lice...

1. A computing device comprising:a processing unit;
memory; and
a network interface;
the processing unit executing computer instructions performing equation-based rate control using delay for network communications, the operations comprising:
obtaining an observed network data rate for a network communication occurring between computing devices based on a current target network data rate, wherein the observed network data rate is an actual bitrate observed for the network communication;
obtaining a queueing delay for the network communication;
calculating an updated target network data rate based on the observed network data rate and the queueing delay, wherein the updated target network data rate:
increases as the observed network data rate increases; and
decreases as the queueing delay increases; and
setting the current target network data rate for the network communication to the calculated updated target network data rate.

US Pat. No. 10,341,239

EFFICIENT POLICY ENFORCEMENT FOR DOWNLINK TRAFFIC USING NETWORK ACCESS TOKENS—CONTROL-PLANE APPROACH

QUALCOMM Incorporated, S...

1. A method, operational at a gateway device, comprising:detecting, at the gateway device, a trigger associated with a device;
identifying an application service, associated with an application server hosting the application service and including an application function, and associated with the device, responsive to detecting the trigger;
obtaining a traffic network policy associated with the application service;
obtaining a network access token based on the traffic network policy, wherein the network access token is sent from the gateway device to the application function of the application server in control-plane signaling and returned, from the application server to the gateway device with a downlink data packet that includes the network access token in user-plane traffic that is destined for the device, and the network access token facilitates validating and/or mapping the downlink data packet that includes the network access token.

US Pat. No. 10,341,208

FILE BLOCK PLACEMENT IN A DISTRIBUTED NETWORK

Taiwan Semiconductor Manu...

1. A method for a file block placement by predicting available bandwidth for a candidate flow on a link in a distributed network, the method comprising:obtaining information about a plurality of flows carried by the link, the information about the plurality of flows carried by the link including a current bandwidth consumption for each flow of the plurality of flows carried by the link;
identifying whether each flow of the plurality of flows has a local constraint or a remote constraint, wherein the local constraint is a throughput constraint of the each flow of the link and the remote constraint is a throughput constraint of each flow of another physical link other than the link; and
computing the available bandwidth for the candidate flow based at least in part on the information about the plurality of flows carried by the link and the identification of whether each flow of the plurality of flows has a local constraint or a remote constraint to generate a predicted available bandwidth for the candidate flow;
selecting one of a plurality of file block placement options based at least in part on the predicted available bandwidth which meets a particular quality of service (QoS) requirement;
determining a set of storage nodes which correspond to the one of the plurality of file block placement options as selected; and
performing the file block placement to the set of storage nodes, wherein computing the available bandwidth for the candidate flow comprises:
subtracting a sum of the current bandwidth consumption of the flows carried by the link having a remote constraint from a capacity of the link; and
dividing the difference by the number of flows carried by the link plus one minus the number of flows carried by the link having a remote constraint.

US Pat. No. 10,341,183

COMPOSITE NAVIGATION METHOD AND SYSTEM FOR AUTOMATIC CONFIGURATION MANAGEMENT OF APPLICATION SOFTWARE

CONDUENT BUSINESS SERVICE...

1. A composite navigational method for configuration management of application software by a computing server, said method comprising:receiving a request, from a user-computing device, for automatic configuration of said application software;
extracting, by a data extraction processor at said computing server, a plurality of previous configuration values corresponding to a plurality of configuration parameters from a storage device, wherein a previous configuration value in said plurality of extracted previous configuration values corresponds to a logic fragment of said application software at said user-computing device communicatively coupled to said computing server over a communication network;
generating, by a tree generating processor at said computing server, a plurality of abstract syntax trees (ASTs) based on parsing of said plurality of previous configuration values;
performing, by a processor at said computing server, one or more pre-specified operations on said generated plurality of ASTs;
determining, by said processor, a configuration value of a current configuration parameter based on a navigation pattern, wherein said navigation pattern is determined using said performed one or more pre-specified operations based on at least user preferences and said extracted plurality of previous configuration values; and
controlling, by said processor, configuration of said application software at said user-computing device over said communication network, based on said determined configuration value of said current configuration parameter.

US Pat. No. 10,341,170

METHOD FOR DIAGNOSING LINK STATUS IN NETWORK

Hyundai Motor Company, S...

1. A method for diagnosing a link status, performed in a first communication node of an Ethernet-based vehicle network, the method comprising:identifying, by the first communication node, a type of a fault occurring in a link connected to the first communication node by monitoring a frame or a pulse signal transmitted from a second communication node connected to the link, wherein the type of the fault is one of a port fault in a local communication node, a port fault in a remote communication node, and a link disconnection fault;
generating, by the first communication node, a first pulse signal including capability information which indicates at least one of transmission speeds and supported duplex modes of the first communication node and further including a link fault type indicator indicating the type of the fault; and
transmitting, by the first communication node, the first pulse signal,
wherein the first pulse signal is generated and transmitted according to an auto negotiation protocol.

US Pat. No. 10,341,169

METHOD AND A SYSTEM FOR GENERATING A NOTIFICATION FOR AN EVENT

Wipro Limited, Bangalore...

1. A method for generating a notification for an event, the method comprising:receiving, by a notification generation system, a recovery notification indicating recovery from the event, from a service provider;
receiving, by the notification generation system, contextual data, from the service provider, comprising state of the event in a first electronic device associated with a user, one or more predefined rules associated with the event and availability of at least one of the first electronic device and one or more second electronic devices associated with the user; and
generating, by the notification generation system, a notification upon analysis of the recovery notification, the contextual data and predefined profile settings of the users;
wherein the one or more predefined rules are related to at least one of time elapsed since occurrence of the event, priority of the event or re-occurrence of the event, and
wherein the predefined profile settings of the user comprise at least one of “notification enabling status”, “notification level” or “preferred electronic device” to receive the notification.

US Pat. No. 10,341,168

TOPOLOGY MANAGER FOR FAILURE DETECTION IN A DISTRIBUTED COMPUTING SYSTEM

SAP SE, Walldorf (DE)

1. A computer-implemented method comprising:receiving, by a topology manager of a distributed computing system, notification that a destination computing node in the distributed computing system is not responding to a communication request, the topology manager being implemented on a data partition of the distributed computing system, the distributed computing system comprising a plurality of computing nodes, the plurality of nodes comprising the destination computing node;
determining, by the topology manager, that the destination computing node is dead and/or has a loss of communication with one or more other computing nodes in the plurality of computing nodes by querying at least a subset of other computing nodes of the plurality of computing nodes regarding liveness of the destination computing node and receiving confirmation from a quorum of the queried computing nodes;
retiring, by the topology manager in response to the determining, the destination computing node, the retiring causing the destination computing node to become a retired computing node; and
causing, by the topology manager, a load balancing of replicas of data partitions in the distributed computing system to compensate for loss of the retired computing node, the load balancing comprising re-assigning one or more of the replicas of data partitions among one or more surviving computing nodes in the plurality of computing nodes.

US Pat. No. 10,341,152

INTERFERENCE PARAMETER SIGNALING FOR EFFICIENT INTERFERENCE CANCELLATION AND SUPPRESSION

Panasonic Intellectual Pr...

1. An integrated circuit, comprising:circuitry which, in operation, controls a process of an apparatus for receiving data from a serving base station in a cellular communication system, the circuitry controls the process by:
blind decoding downlink control information transmitted by the serving base station,
extracting from a first field of the downlink control information scheduling control information and from a second field of the downlink control information interference information, and
receiving or transmitting data on resources specified by the scheduling control information while taking into account the interference information to reduce interference caused by transmitters other than the serving base station.

US Pat. No. 10,341,132

PERFORMANCE ASSESSMENT DEVICE FOR EVALUATING A PERFORMANCE OF A BUILDING MANAGEMENT SYSTEM

Johnson Controls Technolo...

1. A performance assessment device for evaluating a building management system (BMS) installed in a building, the device comprising:a communication interface configured to communicate with a BMS network; and
a processing circuit configured to:
receive performance data related to the building via the communication interface;
evaluate the performance data related to the building to generate a performance assessment for the building, the performance assessment comprising an indication of one or more HVAC devices that do not have an operating schedule associated therewith and an indication of potential savings predicted to result from configuring the operating schedule for the one or more HVAC devices; and
provide a user interface to a user that allows the user to view the performance assessment and perform an action to initiate configuring the operating schedule for the one or more HVAC devices.

US Pat. No. 10,341,105

BLOCKCHAIN-BASED SOCIAL MEDIA HISTORY MAPS

1. A system, comprising:a distributed blockchain database comprising:
a primary head node for a first subscriber to a social media history map service;
two or more blocks in a first chain beginning from the primary head node, each block in the first chain representing a respective online transaction for the first subscriber;
a follower head node for a second subscriber to the social media history map service, the second subscriber being a follower of the first subscriber on one or more social media platforms, and the follower head node being linked to the primary head node; and
two or more blocks in a second chain beginning from the follower head node, each block in the second chain representing a respective online transaction for the second subscriber; and
one or more processors having access to a memory subsystem, wherein the memory subsystem stores instructions executable by the one or more processors that, when executed by the one or more processors, cause the one or more processors to implement a transaction history controller, the transaction history controller configured to:
format data representing a first online transaction made on behalf of the second subscriber for compatibility with the distributed blockchain database, the data representing the first online transaction being from a first social media application;
store the formatted data representing the first online transaction in the distributed blockchain database as a first new block appended at the end of the second chain, the first new block representing the first online transaction; and
generate, in response to a request to generate a trend report for a cluster of subscribers to the social media history map service, the trend report dependent on the two or more blocks in the first chain and the two or more blocks in the second chain, the cluster of subscribers including at least the first subscriber and the second subscriber.

US Pat. No. 10,340,903

SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF

1. A semiconductor device comprising:a target circuit including a transistor;
a monitoring circuit configured to measure a temperature of the target circuit and a delay time between an input and an output of the target circuit; and
a voltage controller configured to:
adjust, according to the measurement of the temperature and the measurement of the delay time, 1) a driving voltage for driving the target circuit to be less than or equal to a critical voltage and 2) a back-bias voltage for adjusting a threshold voltage of the transistor, and
provide the driving voltage and the back-bias voltage to the target circuit,
wherein when the driving voltage is less than or equal to the critical voltage, as the temperature increases, the delay time decreases, and
wherein when the driving voltage is greater than the critical voltage, as the temperature increases, the delay time increases.

US Pat. No. 10,340,901

RANDOM NUMBER GENERATOR, RANDOM NUMBER GENERATION DEVICE, NEUROMORPHIC COMPUTER, AND QUANTUM COMPUTER

TDK CORPORATION, Tokyo (...

1. A random number generator comprising:a ferromagnetic metal layer;
a spin-orbit torque wiring extending in a first direction intersecting a lamination direction of the ferromagnetic metal layer and being joined to the ferromagnetic metal layer; and
an external magnetic field applying part configured to apply a magnetic field to the ferromagnetic metal layer;
wherein a direction of spin injected from the spin-orbit torque wiring into the ferromagnetic metal layer and an easy magnetization direction of the ferromagnetic metal layer intersect each other.

US Pat. No. 10,340,900

SENSE AMPLIFIER FLIP-FLOP WITH EMBEDDED SCAN LOGIC AND LEVEL SHIFTING FUNCTIONALITY

Apple Inc., Cupertino, C...

1. An apparatus, comprising:a first latch circuit including a first discharge node, a second discharge node, a true storage node and a complement storage node, wherein the first latch circuit is configured to pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal;
a discharge circuit including:
a first transconductance device located in a first discharge path between the first discharge node and a ground reference; and
a second transconductance device in a second discharge path between the first discharge node and the ground reference;
wherein the discharge circuit is configured to:
in response to a determination that a scan mode signal is asserted, selectively discharge, based on a value of a scan data signal on a gate terminal of the first transconductance device, either the true storage node via the first discharge node, or the complement storage node via the second discharge node, wherein the scan data signal transitions between a ground voltage level and a second voltage level different than the first voltage level;
otherwise selectively discharge, based on a value of a data signal on a gate terminal of the second transconductance device, either the true storage node via the first discharge node, or the complement storage node via the second discharge node, wherein the data signal transitions between the ground voltage level and a third voltage level different than the first and second voltage levels;
a second latch circuit coupled to the first latch circuit, wherein the second latch circuit is configured to store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node; and
at least one logic gate coupled to a respective output node of at least one output node of the second latch circuit, the logic gate configured to block propagation of a respective output signal in response to a determination that the scan mode signal is de-asserted.

US Pat. No. 10,340,899

HIGH PERFORMANCE LOW RETENTION MODE LEAKAGE FLIP-FLOP

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:a retention circuit configured to retain the state of a circuit node, the retention circuit including:
a first inverter having an input and an output;
a second inverter having an input and an output, wherein the input of the second inverter is connected to the output the first inverter and the output of the second inverter is connected to the input of the first inverter;
a transmission gate having a first terminal connected to the circuit node and a second terminal connected to the input of the first inverter, wherein the transmission gate is configured to be controlled by a retention mode signal that indicates whether a retention mode is active or inactive to isolate the first terminal and the second terminal from each other when the retention mode signal indicates that the retention mode is active and to connect the first terminal and the second terminal to each other when the retention mode signal indicates that the retention mode is inactive; and
a third inverter having an input and an output, wherein the third inverter is a tristate inverter, wherein the input of the third inverter is connected to the output of the first inverter, wherein the output of the third inverter is connected to the circuit node by a signal path that extends between the output of the third inverter and the circuit node and does not include another inverter, and wherein the tristate inverter is configured to be controlled by the retention mode signal to isolate the output of the third inverter from the circuit node when the retention mode signal indicates that the retention mode is inactive and to supply an output signal to the circuit node when the retention mode signal indicates that the retention mode is active, the output signal supplied by the output of the third inverter being an inverse of an output signal supplied by the output of the first inverter.

US Pat. No. 10,340,898

CONFIGURABLE LATCH CIRCUIT

XILINX, INC., San Jose, ...

1. A pulsed latch circuit, comprising:first and second latch circuits, each latch circuit having a respective data input node, a respective data output node, and a respective clock input node, the data output node of the first latch circuit being coupled to the data input node of the second latch circuit; and
a clock control circuit coupled to the first and second latch circuits and configured to:
selectively provide, in response to a first state of a control signal, a first clock pulse that is based on an input clock signal to the clock input node of the second latch circuit and a second clock pulse that is based on an inversion of the first clock pulse to the clock input node of the first latch circuit to cause the first and second latch circuits to store values from two successive clock cycles,
wherein in a single cycle of the input clock signal, the second latch circuit, responsive to the first clock pulse, opens and stores state of the signal at the output node of the first latch circuit, and the first latch circuit, responsive to the second clock pulse, opens and stores state of a signal at the input node of the first latch; and
selectively provide, in response to a second state of the control signal, the input clock signal to the clock input nodes of the first and second latch circuits to cause the first and second latch circuits to cooperate to store a value from a single clock cycle.

US Pat. No. 10,340,897

CLOCK GENERATING CIRCUIT AND METHOD OF OPERATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A clock circuit, comprising:a first latch configured to generate a first latch output signal based on a first control signal, an enable signal and an output clock signal;
a second latch coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal;
a first trigger circuit coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal; and
a clock trigger circuit coupled to the first latch and the first trigger circuit by a first node, configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.

US Pat. No. 10,340,895

REDUCED-POWER ELECTRONIC CIRCUITS WITH WIDE-BAND ENERGY RECOVERY USING NON-INTERFERING TOPOLOGIES

Rezonent Corporation, Lo...

1. A digital driver having a wide operating frequency range, comprising:a pulldown switch;
a pullup switch;
an energy saving component coupled in series with the pulldown switch and the pullup switch; and
a reference supply connected in series with the energy saving component that is configured to enable the digital driver to resonate with a load capacitance and reuse electrical energy at the load capacitance without interfering with a signal path of the digital driver having the wide operating frequency range due to the energy saving component being electrically coupled to the signal path periodically, wherein the pullup switch is designed with a first ratio of width to length that is less than a second ratio of width to length of the pulldown switch due to functionality of the pullup switch being partially performed with energy recycling resonance when the driver resonates with the load capacitance.

US Pat. No. 10,340,894

STATE RETENTION CIRCUIT THAT RETAINS DATA STORAGE ELEMENT STATE DURING POWER REDUCTION MODE

Silicon Laboratories Inc....

1. A state retention circuit for retaining the state of a data storage element during a power reduction mode, comprising:a storage latch powered by a retention supply voltage that remains powered during the power reduction mode, having a data input for coupling to an output node of the data storage element, and having a retention input coupled to a retention node that is toggled from a first state to a second state and back to said first state to cause said storage latch to store a state of the data storage element during a normal mode before entering the power reduction mode; and
a retention latch, comprising:
a retention transistor having a first current terminal coupled to said retention node, having a second current terminal coupled to a supply voltage having a same voltage during the power reduction mode as said normal mode, and having a control terminal; and
a retention inverter powered by said retention supply voltage, having an input coupled to said retention node and having an output coupled to said control terminal of said retention transistor.

US Pat. No. 10,340,893

SYSTEMS AND METHODS FOR PROVIDING COMPENSATION OF ANALOG FILTER BANDEDGE RIPPLE USING LPF

Marvell International Ltd...

11. A system for compensating the bandedge ripple of an analog filter, using a low pass filter, the system comprising control circuitry configured to:receive, at the analog filter, a plurality of tones of different frequencies from a tone generator;
measure, an amplitude of each tone in the plurality of tones after each tone is processed by the analog filter;
store the measured amplitudes and frequencies in a database;
measure a bandedge ripple by measuring a difference in amplitude between a first tone and a second tone from the plurality of tones; and
select a low pass filter, from a plurality of low pass filters, based on the measured difference.

US Pat. No. 10,340,892

MULTI-CHANNEL DIGITAL STEP ATTENUATOR ARCHITECTURE

pSemi Corporation, San D...

1. A multi-channel digital step attenuator comprising a two-dimensional array of N channels of B selectable attenuator cells series-connected between an input port and an output port, where N is an integer greater than one and n is a channel number within the N channels, and B is an integer greater than one and b is a bit position within the B selectable attenuator cells, wherein more than one channel of B selectable attenuator cells can be active at one time.

US Pat. No. 10,340,890

HIGH ORDER FILTER CIRCUIT

NUVOTON TECHNOLOGY CORP.,...

1. A high order filter circuit including:a plurality of second order filter units for filtering inputted signals;
a plurality of switch units for connecting the plurality of second order filter units in a cascade to form a high order filter unit when the switch units are closed, and for restoring the high order filter unit to the plurality of second order filter units when the switch units are opened;
an analog-to-digital converter (ADC) having a first working status and a second working status, for detecting peaks of predetermined band signals outputted from the second order filter units and digitalizing the peaks when the ADC is in the first working status, and for detecting and converting the predetermined band signals from the second order filter units to digital signals and outputting the digital signals when the ADC is in the second working status; and
a digital correction unit for comparing the digitalized peaks with a default value and generating comparison results, and according to the comparison results, the digital correction unit generating frequency control signals and working status control signals and sending them as feedbacks respectively to the second order filter units for adjusting their working frequencies and to the ADC for switching its working status.

US Pat. No. 10,340,889

LOW NOISE NON-FOSTER CIRCUIT

HRL Laboratories, LLC, M...

1. A bias circuit for a non-Foster circuit, the non-Foster circuit being coupled in use with a DC power supply, the non-Foster circuit having a pair of transistors, one of the transistors of said pair being coupled to an input of said non-Foster circuit and the other one of the transistors of said pair being coupled to an output of said non-Foster circuit, the bias circuit including:(a) first inductors connected with (i) current carrying electrodes of the one of the transistors coupled to an input of said non-Foster circuit and (ii) said DC power supply;
(b) second inductors connected with (i) current carrying electrodes of the other one of the transistors coupled to an output of said non-Foster circuit and (ii) said DC power supply; and wherein a sum of the inductances of the first inductors is greater than a sum of the inductances of the second inductors.

US Pat. No. 10,340,888

ELASTIC WAVE FILTER, DUPLEXER, AND ELASTIC WAVE FILTER MODULE

MURATA MANUFACTURING CO.,...

1. An elastic wave filter comprising:a piezoelectric substrate;
an IDT electrode provided on the piezoelectric substrate;
a first shield electrode provided on the piezoelectric substrate;
a first insulating film laminated on the piezoelectric substrate and extending onto the first shield electrode;
a first signal terminal provided on the first insulating film;
a second signal terminal provided on the piezoelectric substrate; and
a ground terminal provided on the piezoelectric substrate and connected to a ground potential; wherein
the first shield electrode is not electrically connected to the IDT electrode and the first and second signal terminals;
the first signal terminal is included in the first shield electrode when seen from above; and
one of the first signal terminal and the second signal terminal is an output terminal and the other of the first signal terminal and the second signal terminal is an input terminal.

US Pat. No. 10,340,887

BAND PASS FILTER AND FILTER MODULE

MURATA MANUFACTURING CO.,...

1. A band pass filter comprising:an LC high pass filter including a first input terminal, a first output terminal, a first path connecting the first input terminal and the first output terminal, a first elastic wave resonator and a first capacitor connected in series in the first path, and a first inductor connected between the first path and a ground potential;
an LC low pass filter including a second input terminal, a second output terminal, a second path connecting the second input terminal and the second output terminal, a second elastic wave resonator and a second capacitor connected between the second path and a ground potential, and a second inductor connected in series in the second path; wherein
the LC high pass filter and the LC low pass filter are connected in series;
the first elastic wave resonator includes a first electrode and a piezoelectric first base board in or on which the first electrode is provided;
the second elastic wave resonator includes a second electrode and a piezoelectric second base board in or on which the second electrode is provided; and
a type of the first base board and a type of the second base board are different from each other, and/or a configuration of the first electrode and a configuration of the second electrode are different from each other.

US Pat. No. 10,340,886

CERAMIC SUBSTRATE, LAYERED BODY, AND SAW DEVICE

SUMITOMO ELECTRIC INDUSTR...

1. A ceramic substrate formed of a polycrystalline ceramic and having a supporting main surface,wherein the supporting main surface has a roughness of 0.01 nm or more and 3.0 nm or less in terms of Sa, and
a number of projections and depressions with a height of 1 nm or more in a square region with 50 ?m sides on the supporting main surface is less than 5 on average, and a number of projections and depressions with a height of 2 nm or more in the square region is less than 1 on average.

US Pat. No. 10,340,883

HIGH-FREQUENCY MODULE

MURATA MANUFACTURING CO.,...

1. A high-frequency module comprising:a module substrate;
a surface acoustic wave filter disposed on a main surface of the module substrate and including a piezoelectric substrate and an electrode pattern provided on the piezoelectric substrate;
a resin member covering the surface acoustic wave filter; and
a wiring pattern connected to the electrode pattern and provided in or on the resin member; wherein
the electrode pattern and the wiring pattern are inductively coupled, capacitively coupled, or inductively coupled and capacitively coupled with each other.

US Pat. No. 10,340,882

BULK ACOUSTIC WAVE FILTER

Samsung Electro-Mechanics...

15. A bulk acoustic wave filter, comprising:a first electrode and a second electrode disposed on a substrate;
a piezoelectric layer comprising a piezoelectric material, the piezoelectric layer disposed between the first and second electrodes;
a housing comprising a passive element disposed on one surface thereof, wherein the housing is coupled to the substrate to accommodate the piezoelectric layer, the first electrode and the second electrode;
a second piezoelectric layer having one surface disposed on the second electrode;
a third electrode disposed on the other surface of the second piezoelectric layer;
a first via formed on the other surface of the first electrode;
a second via formed on one surface of the second electrode; and
third and fourth vias formed on the substrate,
wherein one surface of each of the first and third electrodes is in contact with the substrate.

US Pat. No. 10,340,881

BONDED SUBSTRATE, SURFACE ACOUSTIC WAVE ELEMENT, SURFACE ACOUSTIC WAVE DEVICE, AND METHOD OF MANUFACTURING BONDED SUBSTRATE

THE JAPAN STEEL WORKS, LT...

1. A bonded substrate comprising: a quartz substrate; and a piezoelectric substrate which is bonded on or above the quartz substrate and on which a surface acoustic wave propagates, wherein the quartz substrate and the piezoelectric substrate are covalently bonded at an interface.

US Pat. No. 10,340,880

STRUCTURES OF PLANAR TRANSFORMER AND BALANCED-TO-UNBALANCED TRANSFORMER

REALTEK SEMICONDUCTOR COR...

1. A planar transformer structure comprising:a first planar coil comprising a first ring structure, a second ring structure and a connecting section, wherein the connecting section connects the first ring structure and the second ring structure;
a second symmetric planar coil having at least two turns, wherein a range of the second symmetric planar coil partially or entirely overlaps a range of the first ring structure, and an outmost turn of the first ring structure is arranged inside an outmost turn of the second symmetric planar coil; and
a third symmetric planar coil having at least two turns, wherein a range of the third symmetric planar coil partially or entirely overlaps a range of the second ring structure, and an outmost turn of the second ring structure is arranged inside an outmost turn of the third symmetric planar coil;
wherein, a transformer is constituted by the first planar coil and the second planar coil or by the first planar coil and the third planar coil;
wherein a current entering the first ring structure flows through all metal segments of the first ring structure before leaving the first ring structure;
wherein the current flowing in the first ring structure is opposite in direction to a current flowing in the second ring structure.

US Pat. No. 10,340,877

ANTENNA MATCHING CIRCUIT, ANTENNA DEVICE, AND COMMUNICATION TERMINAL APPARATUS

MURATA MANUFACTURING CO.,...

1. An antenna matching circuit comprising:an impedance converter circuit connected to a feeder circuit; and
an impedance-conversion-ratio adjustment circuit connected between the impedance converter circuit and an antenna port; wherein
the impedance converter circuit includes a first inductance element and a second inductance element that are coupled to each other through magnetic fields, a first end of the first inductance element is connected to the feeder circuit, a first end of the second inductance element is connected to a second end of the first inductance element, and a second end of the second inductance element is connected to ground;
the impedance-conversion-ratio adjustment circuit includes a third inductance element that is series-connected between the impedance converter circuit and the antenna port, and a capacitance element that is shunt-connected between the antenna port and ground, and the impedance-conversion-ratio adjustment circuit corrects an impedance conversion ratio of the impedance converter circuit in accordance with a frequency band; and
a first end of the third inductance element is directly connected to the impedance converter circuit, and a second end of the third inductance element is directly connected to the antenna port.

US Pat. No. 10,340,876

TUNABLE AND INTEGRATED IMPEDANCE MATCHING AND FILTER CIRCUIT

pSemi Corporation, San D...

1. A combined tunable impedance matching and filtering circuit including:(a) a coupled merged inductor having at least three ports, including an input port configured to receive an input signal and having a first characteristic impedance, an output port configured to output a filtered impedance matched output signal and having a second characteristic impedance, and at least one internal port situated between the input port and the output port, wherein the at least one internal port has a corresponding characteristic impedance;
(b) a plurality of tuning circuits, each electrically connected to a corresponding one of the at least three ports of the coupled merged inductor; and
(c) at least one filter circuit, each configured as a notch filter electrically connected to at least one internal port of the coupled merged inductor and comprising circuit components distinct from the plurality of tuning circuits, configured to filter selected radio frequencies at the corresponding characteristic impedance of the at least one internal port.

US Pat. No. 10,340,875

ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. An electronic component comprising:a laminate including a plurality of insulator layers laminated in a lamination direction; and
a first LC parallel resonator, a second LC parallel resonator, and a third LC parallel resonator; wherein
the first LC parallel resonator includes a first inductor and a first capacitor;
the third LC parallel resonator includes a third inductor and a third capacitor;
the second LC parallel resonator includes a second inductor and a second capacitor coupled to each other in parallel;
the first inductor and the third inductor respectively include a first inductor conductor and a third inductor conductor that are wound when viewed in a plan view from the lamination direction;
the second capacitor includes a second capacitor conductor and a second ground conductor that face each other;
the second inductor includes a second inductor conductor that includes a first coupling portion and a second coupling portion, the first coupling portion being electrically coupled to the second capacitor conductor, the second coupling portion being electrically coupled to the second ground conductor;
a first region surrounded by the first inductor conductor and the second inductor conductor is smaller in area than a second region surrounded by the third inductor conductor and the second inductor conductor when viewed in the plan view from the lamination direction; and
a second region forming portion and a first region forming portion are electrically coupled in series in this order on a path from the first coupling portion to the second coupling portion, the second region forming portion being included in the second inductor conductor and surrounding the second region, the first region forming portion being included in the second inductor conductor and surrounding the first region.

US Pat. No. 10,340,840

OSCILLATION BRAKE FOR SOLAR TRACKING SYSTEM

SolarCity Corporation, S...

1. A solar-tracking photovoltaic array, comprising:a torque tube having a first end and a second end opposite the first end;
a plurality of photovoltaic modules coupled with and distributed along the torque tube;
a locking mechanism coupled with and configured to prevent movement of the first end of the torque tube; and
an orientation motor coupled with the second end of the torque tube,
wherein the locking mechanism releases the first end of the torque tube during actuation of the orientation motor.

US Pat. No. 10,340,833

LOAD DRIVE DEVICE

Hitachi Automotive System...

1. A load drive device comprising:a first switching element, including either a first source terminal or a first drain terminal connected to a side of power source potential and either the first drain terminal or the first source terminal connected to one end terminal of a coil load;
a second switching element including either a second drain terminal or a second source terminal connected to a side of ground potential and either the second source terminal or the second drain terminal connected to either the first drain terminal of the first switching element or the second source terminal;
a third switching element including either a third source terminal or a third drain terminal connected to the side of the power source potential and either the first drain terminal or the first source terminal connected to another terminal of the load;
a fourth switching element including either a fourth drain terminal or a fourth source terminal connected to the side of the ground potential and either the fourth source terminal or the fourth drain terminal connected to either the third drain terminal or the third source terminal of the third switching element;
a capacitor including both end terminals connected between the power source potential and the ground potential;
a voltage measurement unit configured to measure a voltage across the capacitor; and
a control unit configured to individually turn the first to fourth switching elements ON or OFF,
wherein the voltage measurement unit detects whether a value of the voltage across the capacitor is not less than a predetermined voltage value set based on withstand voltage values of the first to fourth switching elements or is less than the predetermined voltage value,
the control unit performs switching control between a first mode and a second mode in an operation mode in which the first to fourth switching elements connected to the load are turned ON or OFF, or performs, after control in either the first or second mode starts, the switching control in mode into the second mode or the first mode,
the control unit operates the first to fourth switching elements in the first mode in a case where the voltage across the capacitor is not less than the predetermined voltage value, and operates the first to fourth switching elements in the second mode in a case where the voltage across the capacitor is less than the predetermined value,
the first mode is the operation mode in which all the first to fourth switching elements are turned OFF,
the second mode turns either the second or fourth switching element ON and turns all the other first to fourth switching elements OFF so as to form a closed current path including the coil load and the ground potential,
a capacitance value of the capacitor is determined based on a difference energy value between an energy value stored in the load at time at which occurrence of an excess current in the load is detected and an energy value consumed by either the second or fourth switching element with a current flowing into either the second or fourth switching element in the second mode after the detection of the excess current, and
the voltage across the capacitor is determined to a value of the predetermined voltage value or less, the voltage across the capacitor rising with electrical energy supplied, through the load and diode elements connected in parallel to the first to fourth switching in the first operation mode, to the diodes.

US Pat. No. 10,340,807

GATE DRIVE APPARATUS FOR RESONANT CONVERTERS

Futurewei Technologies, I...

1. A device comprising:a gate drive bridge coupled between a bias voltage of a power converter and ground, wherein the gate drive bridge comprises two high-side switches and two low-side switches, and wherein a duty cycle of the two low-side switches is greater than a duty cycle of the two high-side switches; and
a transformer connected to the gate drive bridge, wherein the transformer comprises:
a primary winding connected to two legs of the gate drive bridge respectively; and
a plurality of secondary windings configured to generate gate drive signals for low side switches, high side switches and secondary switches of the power converter.

US Pat. No. 10,340,786

HIGH FREQUENCY WIRELESS POWER RECTIFIER STARTUP CIRCUIT DESIGN

Integrated Device Technol...

1. A rectifier, comprising:a first transistor and a second transistor coupled in series between a rectifier output and a ground, wherein a first AC input is coupled to a first node between the first transistor and the second transistor;
a third transistor and a fourth transistor coupled in series between the rectifier output and the ground, wherein a second AC input is coupled to a second node between the third transistor and the fourth transistor;
a first control circuit coupled between a gate of the first transistor and a gate of the fourth transistor to control operation of the first and the fourth transistors;
a first startup circuit directly connected between the gate of the first transistor and the first node, the first startup circuit controlling the gate of the first transistor in a startup time period prior to an operating period of the rectifier, wherein the first startup circuit maintains a low impedance between the gate of the first transistor and the first node during a startup time and maintains a high impedance between the gate of the first transistor and the first node during the operating period of the rectifier; and
a second startup circuit directly connected between the gate of the fourth transistor and the ground.

US Pat. No. 10,340,775

APPARATUS FOR WINDING AND TERMINATING DYNAMO ELECTRIC MACHINE CORES

1. Apparatus for winding and terminating coils wound with at least one electric wire on a core of a dynamo electric machine; the core having a longitudinal axis; the apparatus comprising:a wire dispenser; the dispenser having a tubular portion for passage of the wire and an exit from where the wire reaches the core;
a first motor for translating the dispenser with respect to the core during winding or the termination of leads;
tubular support for supporting the core;
a second motor for rotating the tubular support of the core around a rotation axis;
a pulley wheel where the wire is wound before entering the passage portion of the dispenser;
a recovery device of the wire that draws the wire returning from the pulley wheel;
characterized in that the feeding the wire comprises:
a device for applying torque in two directions on the pulley wheel as a function of the position of the dispenser in the translation and the position of the core in the rotation.

US Pat. No. 10,340,769

AUXILIARY DRIVE DEVICE

BorgWarner Inc., Auburn ...

1. An auxiliary drive device comprisingan electric motor having a rotor, which is rotatable about an axis, and a stator that is received within the rotor; and
a viscous clutch having a housing, a clutch disk and a reservoir, the housing being coupled to the rotor for common rotation about the axis, the clutch disk being received in the housing and being rotatable about the axis relative to the housing, the housing and the clutch disk forming a working chamber, the reservoir being coupled in fluid communication to the working chamber.

US Pat. No. 10,340,750

FOREIGN OBJECT DETECTION MANIPULATION METHOD

Nokia Technologies Oy, E...

1. A method, comprising:receiving a wireless power signal from a wireless energy transmitter device;
determining a power level value of the received wireless power signal;
manipulating the determined power level value to obtain a manipulated power level value; and
sending the manipulated power level value to the wireless energy transmitter device.

US Pat. No. 10,340,715

POWER CONTROL APPARATUS, POWER CONTROL METHOD, AND POWER CONTROL SYSTEM

KYOCERA Corporation, Kyo...

1. A power control apparatus that connects to a grid and is capable of controlling charging and discharging of a storage cell, the power control apparatus comprising:a controller configured to reduce a difference from a power purchase amount by controlling charging and discharging of the storage cell, the power purchase amount being established in a power purchase plan;
wherein the controller is further configured, upon acquiring a demand response request issued over a network, to make a comparison between a current amount of stored power in the storage cell and an amount of stored power necessary to comply with the demand response request, and to set a target power for power purchase from the grid on the basis of a result of the comparison,
wherein the demand response request is a request to reduce power usage at a predetermined time after the demand response request is received by the controller, and
wherein as a result of the comparison, when determining that the current amount of stored power in the storage cell does not satisfy the amount of stored power necessary to comply with the demand response request, the controller sets the target power to a first target value higher than a standard value that matches the power purchase amount at a corresponding time in the power purchase plan.

US Pat. No. 10,340,693

SYSTEMS AND METHODS FOR GENERATING ENERGY USING A HYDROGEN CYCLE

1. A system for providing electric power to a commercial military or industrial user, the system comprising:a renewable energy power generator;
a hydrogen generator electrically coupled to the renewable energy power generator;
a water source coupled to the hydrogen generator to supply water to the hydrogen generator;
a hydrogen fueled turbine generator coupled to the hydrogen generator;
a hydrogen storage system fluidly coupled to the hydrogen generator and the hydrogen fueled turbine generator; and
a control system communicatively coupled to the renewable energy power generator, the water source, the hydrogen generator and the hydrogen fueled turbine generator;
wherein the control system controls the hydrogen fueled turbine generator to produce at least a portion of the electric power when the renewable energy power generator is unable to produce the at least a portion of the electric power.

US Pat. No. 10,340,691

RACK POWER DISTRIBUTION VIA MODULAR, EXPANDABLE BUS BAR FOR MODULAR AND SCALABLE/EXPANDABLE INFORMATION HANDLING SYSTEM

Dell Products, L.P., Rou...

1. A rack-based information handling system (IHS), comprising:a rack having a modular structure that supports insertion from a front of the rack of different numbers and sizes of information technology (IT) gear to create one or more IT nodes, the rack vertically provisioned into an upper standard zone, a switch zone, and a lower standard zone, the switch zone designed with at least one switch bay and at least one power bay, each of the at least one switch bay and the at least one power bay configured to enable insertion of a fill-width chassis, the upper standard zone and the lower standard zone each divided into tiers by shelves, the shelves including full-width shelfs providing full-width IT bays for insertion of full-width IT nodes and shelves including partitions defining partial-width bays for insertion of multiple side-by-side partial-width IT nodes;
a power bay chassis having an exterior casing and configured as a full width IT node for insertion into one of the at least one power bay chassis of the switch zone, the exterior casing presenting a volumetric enclosure with opposed side panels, a top and a bottom panel, and a back and a front side, the power bay chassis being a separate physical component from other IT nodes within the rack, the power bay chassis further comprising, within the volumetric enclosure, a plurality of power supply units that electrically connects to an alternating current (AC) switch to receive AC power, a power controller, and a power distribution unit (PDU) having a positive distribution conductor and a negative distribution conductor directed toward a rear of the rack, the PDU electrically connected to the one or more PSUs to receive direct current (DC) electrical power; and
a modular busbar assembly attached to the rear of the rack, the modular busbar assembly comprising (i) a first positive and a first negative vertical busbar segment extending vertically along a rear of the rack and in direct electrical connection, respectively, to the positive distribution conductor and to the negative distribution conductor of the PDU and spanning one or more nodes inserted into the rack to provide hot pluggable electrical power to an aft-directed connection of an IT node inserted into the rack and (ii) second, separate, positive and negative vertical busbar segments modularly attached to the first positive and negative vertical busbar segments, respectively, to electrically connect with the positive and negative distribution conductor, respectively, of the PDU, the second, separate positive and negative vertical busbar segments extending vertically and spanning at least one additional node that is vertically adjacent to the one or more nodes powered by the first positive and negative busbar segments to provide electrical power to the additional adjacent nodes.

US Pat. No. 10,340,690

INTERFERENCE SUPPRESSION STAGE AND POWER SUPPLY

Robert Bosch GmbH, Stutt...

1. An interference suppression stage (12) of a power supply (2), the interference suppression stage (12) comprising:an input (14) connected to an input module (4) of the power supply (2), the input module (4) connected to an electrical supply system (6),
an output (16) connected to an output module (8) of the power supply (2), the output module (8) connected to an electrical load (10),
at least two power paths (18a-c) connected in parallel between input (14) and output (16), wherein each of the power paths (18a-c) are configured to be switched between an active state (A) and an inactive state (I),
a control unit (20) configured to switch at least one of the power paths (18a-c) to the inactive state (I) in a saving mode (S),
wherein the control unit (20) switches different power paths (18a-c) alternately in time to inactive (I) in saving mode (S),
wherein the saving mode (S) is activated when the electrical current (E) flowing through the interference suppression stage (12) is below a limit current (G).

US Pat. No. 10,340,689

SYSTEM AND METHOD FOR POWER MANAGEMENT

NXP B.V., Eindhoven (NL)...

1. A power management device, comprising:a first port configured to be coupled to a first power source;
a second port configured to be coupled to a second power source;
a switched capacitor converter;
an inductor coupled in parallel with a switch;
wherein the switched capacitor converter is coupled between the first port and one end of the inductor coupled in parallel with the switch;
wherein another end of the inductor coupled in parallel with the switch, is coupled to the second port;
a first power controller configured to regulate power transfer between the first power source and the second power source using commands sent to the first power source; and
a second power controller configured to regulate power transfer between the first power source and the second power source using commands sent to the switch.

US Pat. No. 10,340,688

MODULAR OVERVOLTAGE PROTECTION UNITS

RIPD IP ASSETS LTD, Nico...

1. A modular overvoltage protection unit comprising:a unit enclosure defining an enclosure cavity and having an integral DIN rail receiver channel;
first and second surge protection devices (SPDs) each disposed in the enclosure cavity, each of the first and second SPDs including:
a first electrode in the form of a metal housing defining a housing cavity;
a second electrode disposed within the housing cavity; and
a varistor member formed of a varistor material, wherein the varistor member is captured between and electrically connected with each of the first and second electrodes;
wherein the unit enclosure is configured to mount the overvoltage protection unit on a DIN rail such that the DIN rail is seated and secured in the DIN rail receiver channel to support the unit enclosure on the DIN rail; and
wherein the unit enclosure is DIN standard compliant.

US Pat. No. 10,340,687

ESD PROTECTION CIRCUIT AND METHOD WITH HIGH IMMUNITY TO HOT PLUG INSERTION AND OTHER TRANSIENT EVENTS

TEXAS INSTRUMENTS INCORPO...

1. An electrostatic discharge (ESD) protection circuit, comprising:a first transistor, including a first drain terminal coupled with a protected pad, a first source terminal coupled with a voltage supply node, and a first control terminal coupled to a first control node;
a trigger circuit configured to turn on the first transistor to conduct a current from the protected pad to the voltage supply node in response to a first voltage rise in the protected pad at or above a first slew rate; and
a second circuit coupled between the first control node and the voltage supply node, the second circuit configured to reduce the voltage of the first control node in response to a second voltage rise of the first control node at a second slew rate below the first slew rate, the reduced voltage of the first control node partially reducing the current flow through the first transistor, the second circuit comprising:
a low pass filter circuit to provide a rising filter output signal at a first filter node responsive to the rises in the voltage of the first control node, the low pass filter circuit including a first filter resistor connected between the first control node and the first filter node, and a first filter capacitor connected between the first filter node and the voltage supply node, a filter time constant associated with the first filter resistor and the first filter capacitor of the low pass filter circuit is between 100 ns and 2 ?s.

US Pat. No. 10,340,686

ELECTRONIC DEVICE

DENSO CORPORATION, Kariy...

1. An electronic device having a circuit network therein and conducting at least one of power reception and communication with an external device through a wire harness, the electronic device comprising:a detection circuit detecting a voltage variation caused by a noise that has a frequency component near a resonance frequency and superimposes on at least one of the wire harness and the circuit network, the resonance frequency being determined based on a characteristic impedance of the wire harness and the circuit network;
a resonance frequency shift circuit shifting the resonance frequency by changing at least one of a capacitance and an inductance of the circuit network based on a level of the voltage variation detected by the detection circuit; and
a wiring passing from a connection to the wire harness to the resonance frequency shift circuit and connected to the detection circuit, wherein
the detection circuit is connected to the wiring that is included in the circuit network and to be connected to the wire harness,
the detection circuit detects the voltage variation caused in the wiring,
the detection circuit includes a first capacitor that is charged when a magnitude of the voltage variation is equal to or more than a predetermined voltage,
the resonance frequency shift circuit operates with a charged voltage of the first capacitor,
the detection circuit further includes a determining element that is connected between the wiring and the first capacitor, and determines that the magnitude of the voltage variation is equal to or more than the predetermined voltage,
the detection circuit further includes a discharge resistor that is connected to ground, is connected in parallel with the first capacitor, and discharges the first capacitor, and
the resonance frequency shift circuit includes a maintenance circuit that shifts the resonance frequency when the level of the voltage variation detected by the detection circuit is equal to or higher than a predetermined level and maintains the shifted resonance frequency for a predetermined period regardless of the level of the voltage variation detected by the detection circuit.

US Pat. No. 10,340,684

VOLTAGE DERIVATIVE AND ZERO-SEQUENCE BROKEN CONDUCTOR DETECTION

Schweitzer Engineering La...

1. A system for detecting a broken conductor, comprising:a plurality of circuit breakers in electrical communication with a conductor, wherein each circuit breaker is configured to open and close an electrical path of the conductor;
a plurality of intelligent electronic devices in communication with the plurality of circuit breakers and the conductor, such that each circuit breaker is in communication with at least one intelligent electronic device,
wherein each intelligent electronic device is configured to obtain electrical measurements from the conductor, determine phasor data from the measurements, and transmit the phasor data; and
a central controller device in communication with the plurality of intelligent electronic devices configured to receive the phasor data from the plurality of intelligent electronic devices and use the received phasor data to detect a broken conductor condition of the conductor by comparing a rate of change of voltage from the phasor data of each of the plurality of intelligent electronic devices.

US Pat. No. 10,340,683

LOAD-DRIVING INTEGRATED CIRCUIT DEVICE

Mitsubishi Electric Corpo...

1. A load-driving integrated circuit device comprising:a calculation control circuit unit that generates a load driving command Son that is a command signal for applying a power-source voltage to an electric load;
an opening/closing device unit that is connected in series with a negative-side load wiring lead or a positive-side load wiring lead of the electric load and has a plurality of semiconductor opening/closing devices;
a monitoring control circuit unit that makes the plurality of semiconductor opening/closing devices perform opening/closing operation in response to the load driving command Son; and
an opening/closing device integrated circuit in which the opening/closing device unit and the monitoring control circuit unit are integrated on a semiconductor chip,
wherein the opening/closing device unit has a plurality of opening/closing circuit units which are equal to or more than three opening/closing circuit units of a first opening/closing circuit unit, a second opening/closing circuit unit, and a third opening/closing circuit unit, which are connected in parallel with one another,
wherein each of the plurality of opening/closing circuit units has upper and lower opening/closing devices which form a pair of upper-side opening/closing device and lower-side opening/closing device which are connected in series with each other, and a connection point potential detection circuit that generates an output voltage corresponding to the potential of the connection point between the upper-side opening/closing device and the lower-side opening/closing device,
wherein the calculation control circuit unit has an application circuit selection calculator that selects an application circuit, which is an opening/closing circuit unit for performing on/off operation of a load current corresponding to the load driving command Son, from the plurality of opening/closing circuit units; in the case where it is determined based on an output voltage of the connection point potential detection circuit that a device disconnection abnormality or a device snort-circuit abnormality has occurred in the upper-side opening/closing device or the lower-side opening/closing device, the application circuit selection calculator removes an opening/closing circuit unit, in which an abnormality has occurred, from the application circuit, and includes an auxiliary circuit, which is a normal opening/closing circuit unit which is not selected as the application circuit, in the application circuit in the case where there is the auxiliary circuit, and
wherein the monitoring control circuit unit has an opening/closing signal selection circuit that distributes opening/closing command signals corresponding to the load driving command Son into the upper and lower opening/closing devices of the application circuit selected by the application circuit selection calculator.

US Pat. No. 10,340,682

ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME

MURATA MANUFACTURING CO.,...

1. An electronic device comprising:a wiring substrate including a land electrode;
an electronic component; and
an intermediate connection layer interposed between the wiring substrate and the electronic component, the intermediate connection layer including:
a first substrate defining an opening therein;
a second substrate, the first substrate being more rigid than the second substrate; and
a first conductor part on a first principal surface of the second substrate, the first conductor part including a fuse part at a position opposite the opening;
second and third conductor parts on respective opposed principal surfaces of the first substrate, wherein
the second substrate and the first substrate are electrically connected with each other via a conductive bond material,
the electronic component and the wiring substrate are electrically connected with each other via the intermediate connection layer, and
the first, second and third conductor parts each include a respective plurality of connection electrodes electrically insulated from each other.

US Pat. No. 10,340,681

POWER MANAGEMENT SYSTEM COMPRISING STATIC PROTECTING CIRCUIT AND RELATED METHOD OF OPERATION

Samsung Electronics Co., ...

1. A power management system, comprising:a power converter, comprising:
a power stage configured to stabilize a direct current (DC) power supply voltage in response to an enable signal to generate a DC output voltage, and
a protecting circuit configured to:
detect a first state in which a switch node of the power stage is shorted to the DC power supply voltage, and in response thereto generate a protection signal indicating an abnormal state of the power stage;
detect a second state in which the switch node of the power stage is shorted to a ground voltage, and in response thereto generate the protection signal indicating the abnormal state of the power stage;
detect a third state in which an inductor in an inductor-capacitor circuit of the power stage is floated from the switch node of the power stage, and in response thereto generate a protection signal indicating the abnormal state of the power stage; and
detect a fourth state in which the DC power supply voltage is floated from the power stage, and in response thereto generate a protection signal indicating the abnormal state of the power stage; and
a main control circuit configured to generate the enable signal for the power converter based on the protection signal received from the power converter.

US Pat. No. 10,340,680

METHOD AND DEVICE FOR SHUTTING DOWN AN INSTALLATION PART EXHIBITING AN INSULATION FAULT IN AN UNGROUNDED POWER SUPPLY SYSTEM

6. A device for shutting down an installation part (6) provided with connected equipment in an ungrounded power supply system (2) in case of an insulation fault in a direct-current circuit (8) connected to the installation part (6) to be shut down, comprising an insulation monitoring device (20) for determining an insulation resistance (Riso) of the ungrounded power supply system (2), characterized in that the insulation monitoring device (20) comprises a voltage measuring device (26) for determining a displacement direct voltage (Uv) between a respective outer conductor of the ungrounded power supply system (2) and ground and an evaluating device (28) for combined evaluation of the insulation-resistance value (Riso) and the displacement direct voltage (Uv).

US Pat. No. 10,340,678

ELECTRONIC CIRCUIT BREAKER WITH PHYSICAL OPEN-CONTACT CONSTRUCTION AND FAIL-SAFE PROTECTION

21. A circuit breaker comprising:a pair of main contacts movable with respect to each other between a closed position wherein a line terminal and a load terminal are in electrical communication with each other via a main power circuit, and an open position wherein the line terminal and the load terminal are electrically isolated from each other;
a trip coil connected to at least one of said pair of main contacts, said trip coil causing said pair of main contacts to move from the closed position to the open position in response to a trip current, thereby tripping said circuit breaker;
a normally closed relay having a relay activating circuit and a switching circuit, the switching circuit defaulting to an on state, but being switchable to an off state when an activating power is supplied to the relay activating circuit, the switching circuit automatically returning to the on state when the activating power to the relay activating circuit is interrupted;
wherein an input of the switching circuit of said normally closed relay receives power from the main power circuit, downstream of said pair of main contacts, and an output of the switching circuit of said normally closed relay is electrically connected to said trip coil, such that the switching circuit of said normally closed relay provides the trip current to said trip coil when the switching circuit is in the on state, thereby tripping said circuit breaker, but ceases to provide the trip current to said trip coil when the switching circuit is in the off state, thereby allowing the line terminal and the load terminal to be in electrical communication with each other; and
a monitoring circuit receiving power from the main power circuit, upstream of said pair of main contacts, and being electrically connected to the relay activating circuit of the normally closed relay, said monitoring circuit supplying the activating power to the relay activating circuit so long as a determination is made that said circuit breaker is operating within acceptable parameters, and ceasing to supply the activating power to the relay activating circuit upon a determination being made that said circuit breaker is not operating within acceptable parameters, thereby tripping said circuit breaker.

US Pat. No. 10,340,677

FLEXIBLE ELECTRICAL CONTACT MODULE

NDI Engineering Company, ...

1. A system for conducting electricity, the system comprising a first body, a second body configured to move relative to the first body in a primary movement direction, and one or more electrical contact modules disposed between and in contact with the first body and the second body, each electrical contact module comprising:a plurality of laminations, each lamination comprising a metal sheet having a central longitudinal portion aligned on a first plane, a first plurality of fingers extending outward from the central longitudinal portion and aligned on a second plane angled relative to the first plane at a first angle, and a second plurality of fingers extending outward from the central longitudinal portion and aligned on a third plane angled relative to the first plane at an angle supplementary to the first angle, such that the lamination has an arrow shape from an end view, each pair of longitudinally adjacent fingers separated from one another by a gap; and
at least a first clamping bar and a second clamping bar parallel to the central longitudinal portions of the plurality of laminations and disposed to compressively hold the plurality of laminations together in a stack disposed between the clamping bars along a clamping axis disposed orthogonal to the primary movement direction, each lamination separated from an adjacent lamination in the stack by a shim having a thickness that defines a space between parallel fingers of the adjacent laminations.

US Pat. No. 10,340,676

ELECTRICAL DEVICE PROTECTIVE HOUSING

Titan3 Technology LLC, T...

1. A protective housing kit for an electrical device comprising:a baseplate including a first baseplate hinge component on a first baseplate side and a second baseplate hinge component on a second baseplate side;
a lid including a first lid hinge component on a first lid side and a second lid hinge component on a second lid side;
a first hinge pin with a first structural feature; and
a second hinge pin with a second structural feature distinct from the first structural feature,
wherein:
the first baseplate hinge component, the first lid hinge component, and the first hinge pin are configured to be assembled to form a first hinge that connects the baseplate and the lid;
the second baseplate hinge component, the second lid hinge component, and the second hinge pin are configured to be assembled to form a second hinge that connects the baseplate and the lid; and
the first baseplate side is adjacent and perpendicular to the second baseplate side.

US Pat. No. 10,340,674

REVERSIBLE CABLE SUPPORT BAR

1. A cable management tool, comprising: an elongated body portion having one or more sets of slots configured to be filled with cable ties, wherein each set of slots of the one or more sets of slots has at least two slots with a same shape; a first part extending from a first end of the body portion and configured to be attached to a chassis, wherein the first part includes: a first arm portion having a first length, a first U-shape slot on a first end of the first arm portion, a second U-shape slot on a second end of the first arm portion, wherein the first U-shape slot and the second U-shape slot have their openings point at opposite directions, thereby forming a first H-shape, and are configured to enable vertical movement of the first arm portion, and the first end and the second end are opposite ends of the first arm portion; a second part extending from a second end of the body portion and configured to be attached to the chassis, wherein the second part includes: a second arm portion having a second length, a third U-shape slot on a first end of the second arm portion, a fourth U-shape slot on a second end of the second arm portion, wherein the third U-shape slot and the fourth U-shape slot have their openings point at opposite directions, thereby forming a second H-shape, and are configured to enable vertical movement of the second arm portion, and the first end and the second end are opposite ends of the second arm portion, wherein the one or more sets of slots include a first set of vertical pairs of slots and a second set of horizontal pairs of slots, wherein the first set of vertical pairs of slots and the second set of horizontal pairs of slots include a same number of pairs of slots.

US Pat. No. 10,340,672

CONDUCTING WIRE END PORTION JOINING METHOD, AND CONDUCTING WIRE END PORTION JOINING STRUCTURE

TOYOTA JIDOSHA KABUSHIKI ...

1. A conducting wire end portion joining method for conductively joining together end portions of conducting wires each covered with an insulation coating,the conducting wire end portion joining method comprising:
aligning end portions of conducting wires with end portions of insulation coatings of the conducting wires while adjoining the insulation coatings of side surfaces of the end portions of two winding wires, and bringing end surfaces of the end portions of the conducting wires of the two winding wires into contact with a conductive coating material stored in an insulating cap having a property of shrinking when heated; and
shrinking the insulating cap by heating to fix the shrunken insulating cap around the insulation coatings of the end portions of the two winding wires, and joining together the end portions of the two winding wires by conductively connecting the conducting wires of the two winding wires via the hardened conductive coating material.

US Pat. No. 10,340,671

CONDUCTOR COVER APPLICATOR WITH SPOOL

Cantega Technologies Inc....

1. An applicator for applying a conductor cover to a cable, the applicator comprising:a structural element comprising a hot stick;
a spool connected to rotate relative to the structural element;
the conductor cover, which is tubular and split longitudinally to define a first longitudinal edge and a second longitudinal edge, the conductor cover being resilient to assume a tubular conformation, with the second longitudinal edge curled over the first longitudinal edge to overlap a portion of an exterior surface of the conductor cover, in a lowest energy state of the conductor cover, the spool to storing the conductor cover in a pre-application state where the conductor cover is flattened against the resiliency of the conductor cover and wrapped more than one time around the spool with the first longitudinal edge and the second longitudinal edge of the conductor cover spread open and perpendicular to a spool axis; and
a lock attached to the structural element or the spool, the lock holding the conductor cover wrapped around the spool in the pre-application state, the applicator being configured to, during use, unwind the conductor cover from the pre-application state on the spool to curl the second longitudinal edge over the first longitudinal edge into the tubular conformation around the cable.

US Pat. No. 10,340,670

LOW VOLTAGE ELECTRICAL DISTRIBUTION INSTALLATION

SCHNEIDER ELECTRIC INDUST...

1. A low voltage electrical distribution installation comprising:at least one busbar linked electrically to a power supply busbar, or to an upstream protection switchgear, and to switchgears of an electrical equipment item,
wherein, for each of at least two bars, an insulating support configured to house said bar over substantially all of its length, each insulating support comprising a clip and a runner being configured to fix the respective insulating support to another adjacent insulating support, the number of insulating supports being able to be adapted to demand, each insulating support situated at the end of a group of insulating supports, being configured to be fixed to at least one upright belonging to a device housing the switchgear, via at least one crossmember extending substantially at right angles to the longitudinal direction of said corresponding bar, said at least one crossmember being fixed to the upright(s), and to said insulating support so as to offer total accessibility to the connection surface of the bar and such that the assembly comprising the upright(s), the crossmember(s) and the insulating supports housing the bars, forms a rigid assembly,
wherein said clip provided on each insulating support is integrated with the insulating support and configured to cooperate with a runner on an adjacent insulating support, and said runner provided on each insulating support is configured to cooperate with a clip on an adjacent insulating support.

US Pat. No. 10,340,669

POWER DISTRIBUTION LOOP WITH FLOW-THROUGH JUNCTION LOCATIONS

Amazon Technologies, Inc....

1. A data center comprising:computing rooms;
electrical rooms comprising electrical equipment configured to distribute electrical power to the computing rooms; and
an electrical power distribution loop electrically coupled to a utility power source, wherein the electrical power distribution loop comprises feed-through junction locations, each junction location comprising:
a bus connected at a first end and a second end to the electrical power distribution loop;
a tap electrically coupled to the bus between the first end and the second end; and
a disconnect switch electrically coupled downstream of the tap;
wherein a particular one of the junction locations is configured to flow electrical power while a particular one of the electrical rooms is being connected to or disconnected from the particular one of the junction locations, such that electrical power flow through the electrical power distribution loop to electrical rooms electrically coupled to other ones of the junction locations is not interrupted.

US Pat. No. 10,340,668

STACKABLE MODULE

1. A stackable module with a housing provided to hold an electric/electronic component and with a clamping device for attaching to a support rail,wherein the clamping device has two latching/gripping hooks, which are displaceable in mutually opposite directions between an open position and a fastening position,
and a force deflection mechanism to adjust the latching/gripping hooks between the open position and the fastening position, that is actuable by means of an actuating element, and able to be subjected to an actuating force from an outer side,
wherein the latching/gripping hooks bound a free opening distance which, for release fastening to the support rail, is greater in the open position and smaller in the fastening position than a provided support rail extent, and
wherein the force deflection mechanism has an actuating-element-side deflection profile and a hook-side displacement part, which has a deformation portion which is deformable by a displacement force in order to generate a hook-side displacement, wherein between the deflection profile and the deformation portion, a sliding contact is able to be formed, at which the deformation portion is able to be subjected to the displacement force via the deflection profile.

US Pat. No. 10,340,667

SPARK PLUG

NGK SPARK PLUG CO., LTD.,...

1. A spark plug comprising:an insulator having an axial hole extending along an axial line from a front side to a rear side;
a center electrode disposed on the front side of the axial hole;
a metal terminal disposed on the rear side of the axial hole; and
a resistor disposed between the metal terminal and the center electrode in the axial hole so as to be electrically connected to the metal terminal and the center electrode, wherein
the resistor is in contact with an inner circumferential surface of the insulator, and,
on a cross section taken along the axial line so as to include the axial line,
in a case where
a plurality of points are plotted at predetermined intervals in a direction of the axial line so as to be present on a partial boundary line, within an arbitrary range in the direction of the axial line, of a boundary line between the insulator and the resistor, and
a regression line is drawn by a least-squares method with use of the plurality of points,
an average value of distances in a direction perpendicular to the regression line between the regression line and the partial boundary line is 0.1 to 0.3 ?m.

US Pat. No. 10,340,666

SPARK PLUG

NGK SPARK PLUG CO., LTD.,...

1. A spark plug, comprising:an insulator having an axial hole extending along an axial line;
a center electrode disposed within the axial hole;
a tubular metallic shell disposed around an outer circumference of the insulator; and
a ground electrode having a tip-joining surface and a base end that is fixed to the tubular metallic shell, the ground electrode including a noble metal tip that is joined to the tip-joining surface via a fused portion so as to face an end face of the center electrode and to protrude toward the end face, the noble metal tip having an elliptic cylindrical shape,
wherein, when the noble metal tip is projected onto a projection plane parallel to the tip-joining surface, the noble metal tip has an elliptical shape in the projection plane, and
wherein, when the ground electrode is also projected onto the projection plane, an angle of 45° or less is formed between a major axis of the elliptical shape of the noble metal tip in the projection plane and a straight line that extends in a lengthwise direction of the ground electrode and passes through a center of the noble metal tip in the projection plane.

US Pat. No. 10,340,665

SPARK PLUG HAVING AN INCREASED TIGHTENING TORQUE

Robert Bosch GmbH, Stutt...

1. A spark plug, comprising:an insulator;
a casing including a sealing surface; and
a gasket which rests against the sealing surface;
wherein the sealing surface includes a plurality of recesses, wherein a form-locked connection is present between the recesses and the gasket.

US Pat. No. 10,340,664

CORONA IGNITION DEVICE

BorgWarner Ludwigsburg Gm...

1. A corona ignition device, comprising:a central electrode;
an insulator in which the central electrode sits;
a coil connected to the central electrode;
a housing which holds the insulator and surrounds the coil;
a cover which closes the housing at an end facing away from the insulator; and
a spring arranged between the cover and the coil, wherein the spring comprises a metal plate having spring lugs.

US Pat. No. 10,340,663

QUANTUM CASCADE LASER

SHARP KABUSHIKI KAISHA, ...

1. A quantum cascade laser comprising:a semiconductor substrate; and
an active layer that is disposed on the semiconductor substrate and has a cascade structure, in which a plurality of unit layered bodies, each composed of a quantum well light emitting layer and an injection layer, are stacked such that the quantum well light emitting layers and the injection layers are alternately stacked,
wherein each of the plurality of unit layered bodies has a subband level structure having an upper laser emission level, a lower laser emission level, and a relaxation miniband that is composed of at least two energy levels which function as relaxation levels with an energy spacing smaller than the energy difference (EUL) between the upper laser emission level and the lower laser emission level,
the energy width (EMB) of the relaxation miniband is set to be smaller than the energy (ELO?EUL) obtained by subtracting the energy difference (EUL) between the upper laser emission level and the lower laser emission level from the energy (ELO) of longitudinal optical phonons (EMB light is generated due to intersubband transition of electrons from the upper laser emission level to the lower laser emission level in the quantum well light emitting layer, and
the electrons subjected to the intersubband transition are relaxed in the relaxation miniband included in the injection layer and are injected from the injection layer into a quantum well light emitting layer in the unit layered body at a subsequent stage.

US Pat. No. 10,340,662

QUANTUM CASCADE LASER

Sharp Kabushiki Kaisha, ...

1. A quantum cascade laser comprising:a first electrode;
a first contact layer that is in contact with the first electrode and is made of a first compound semiconductor;
a second electrode having a polarity opposite to that of the first electrode;
a second contact layer that is in contact with the second electrode and is made of a second compound semiconductor; and
an active layer disposed between the first contact layer and the second contact layer and including two or more active layer units, wherein
each of the active layer units includes one or more quantum well layers made of a third compound semiconductor and one or more barrier layers made of a fourth compound semiconductor, and each of the quantum well layers and each of the barrier layers are alternately stacked,
the third compound semiconductor is Alx3Iny3Ga(1-x3-y3)N (0?x3?1, 0?y3?1),
the fourth compound semiconductor is Alx4Iny4Ga(1-x4-y4)N (0?x4?1, 0?y4?1),
the fourth compound semiconductor has a band gap energy higher than that of the third compound semiconductor,
at least one of the barrier layers has a thickness of 1.8 nm or more, and
a main surface of each of the quantum well layers and a main surface of each of the barrier layers have an off-angle of ±1° with respect to a (1?100) orientation.

US Pat. No. 10,340,661

ELECTRO-OPTICAL DEVICE WITH LATERAL CURRENT INJECTION REGIONS

International Business Ma...

1. A lateral current injection electro-optical device comprising:an active region comprising a stack of III-V semiconductor gain materials stacked along a stacking direction z, the active region formed as a slab having two pairs of opposite, lateral surface portions, each extending parallel to said stacking direction z,
wherein the slab is a form factor, whereby a length of the slab is larger than a width thereof,
wherein said width, said length, and said stacking direction z are perpendicular; and
two paired elements, including:
a pair of doped layers of III-V semiconductor materials, including an n-doped layer and a p-doped layer,
wherein the p-doped layer and the n-doped layer are arranged on respective sides of the slab, contiguously with the opposite, lateral surface portions of one of said two pairs of lateral surface portions,
wherein a maximum length of each of the p-doped layer and the n-doped layer is less than a length of said opposite, lateral surface portions of said one of said two pairs, and
wherein each of the p-doped layer and the n-doped layer comprises, on a top surface portion thereof, a recess extending laterally along the slab and parallel to its length, so as for the active region and the contiguous pair of doped layers to have a rib waveguide configuration; and
a pair of lateral waveguide cores,
wherein the lateral waveguide cores are laterally butt-jointed to the opposite, lateral surface portions of the other one of said two pairs of surface portions, and
wherein the two paired elements are laterally arranged on opposite sides of the slab, the elements distinctly adjoining respective elements of the lateral surface portions of the slab such that the elements are separated from each other by the slab.

US Pat. No. 10,340,660

SEMICONDUCTOR TUNABLE LASER PACKAGE WITH TUNABLE OPTICAL FILTERS SUBASSEMBLY

NeoPhotonics Corporation,...

1. A tunable laser assembly comprising:a housing comprising a plurality of walls forming an interior space within the plurality of walls and extending from a first end to a second end along an axis;
an electrical input interface positioned at the first end of the housing and configured to receive an information-containing electrical signal;
an optical output interface positioned at the second end of the housing and configured to transmit a laser beam along the axis;
a semiconductor laser positioned in the interior space of the housing and operable to emit the laser beam along the axis, wherein the semiconductor laser is configured to a select the wavelength of the laser beam emitted thereby in response to the information-containing electrical signal received by the electrical input interface;
an optical isolator positioned exterior of the housing along the axis to receive the laser beam from the optical output interface to at least prevent light from reflecting back into the interior space of the housing; and
a piezoelectric transducer positioned exterior of the housing and coupled to the optical isolator, wherein the piezoelectric transducer is configured to provide dithering during frequency tuning of the laser beam.

US Pat. No. 10,340,659

ELECTRONICALLY PUMPED SURFACE-EMITTING PHOTONIC CRYSTAL LASER

Conary Enterprise Co., Lt...

1. An electrically pumped surface-emitting photonic crystal laser, comprising:a substrate having a top surface and a bottom surface;
a first cladding layer arranged on said top surface of the substrate;
an active layer with a quantum structure arranged on said first cladding layer;
a second cladding layer arranged on said active layer;
a contact layer arranged on said second cladding layer in a shape of mesa and including a plurality of holes to form a photonic crystal structure, said photonic crystal structure further having a first area on a top surface thereof;
an electrical currents confining structure arranged on said photonic crystal structure and on said active layer and including an opening corresponding to said first area on the photonic crystal structure, so as to confine electrical currents within the first area;
a transparent conducting layer arranged on said electrical currents confining structure and including a second area on a top surface thereof, covering said first area of the photonic crystal structure and having said second area vertically aligned with said first area;
a metal anode arranged on said transparent conducting layer with an aperture aligned with said second area of the transparent conducting layer to avoid blocking the first area; and
a metal cathode arranged under said bottom surface of the substrate;
whereby the metal anode, the transparent conducting layer, the electrical currents confining structure and the metal cathode are arranged correspondingly for electrically pumping the quantum structure, and then the photonic crystal structure surface-emits laser through the first area, the opening of the electrical currents confining structure and the second area of the transparent conducting layer to the aperture of the metal anode.

US Pat. No. 10,340,658

LASER SYSTEM FOR ATOMIC CLOCKS AND SENSORS

AOSense, Inc., Sunnyvale...

1. A system, comprising:a single laser, wherein a central optical frequency of laser light of the single laser can be tuned;
an intensity splitter, wherein the laser light is split along a first optical path and a second optical path using the intensity splitter;
a modulator disposed in the first optical path, wherein a portion of the laser light is subjected to the modulator with the modulator disposed to generate a frequency-shifted sideband from some or all of the portion of the laser light subjected to the modulator, with the frequency-shifted sideband shifted by an adjustable frequency source, resulting in an adjustable frequency offset between the frequency-shifted sideband and an unmodulated carrier propagating in the second optical path, and
a feedback-based lock controller, wherein the feedback-based lock controller locks the optical frequency of the frequency-shifted sideband to a repumping transition for atom cooling.

US Pat. No. 10,340,657

LASER DEVICE

1. A laser device, comprisinga tunable laser comprising a laser cavity and a laser control module placed outside the laser cavity,
wherein:
the tunable laser is configured to generate laser light having a center frequency,
the laser control module is configured to receive at least a portion of the laser light generated by the laser, to generate a control signal and to feed the control signal back to the laser for stabilizing the frequency, and
the laser control module comprises an interferometer comprising interferometer mirrors and a tunable interferometer length, wherein the interferometer length is tunable by an actuator arranged between the interferometer mirrors and by thermal variation.

US Pat. No. 10,340,656

SEMICONDUCTOR LASER SOURCE

1. A semiconductor laser source able to emit at least one optical signal of wavelength ?Li, said laser source comprising:a substrate made of silicon extending mainly in a plane called the “plane of the substrate”;
a structured layer formed on an upper face of the substrate made of silicon and having an upper face on the opposite side to the substrate made of silicon, said structured layer comprising:
a passive optical component chosen from a group consisting of an optical reflector and a waveguide, said passive optical component being encapsulated in silica or produced on a silica layer; and
at least one pad extending from a lower face, making direct contact with the substrate made of silicon, to an upper face flush with the upper face of the structured layer, said pad being made entirely from a material the thermal conductivity at 20° C. of which is higher than the thermal conductivity at 20° C. of silica, in order to form a thermal bridge through the structured layer; and
an optical amplifier made of III-V material configured, when supplied with power, to amplify the optical signal of wavelength ?Li, said optical amplifier being bonded directly, by direct bonding, to the upper face of the structured layer so that the optical signal amplified by the optical amplifier is reflected or guided by said passive optical component, said optical amplifier being bonded directly, by direct bonding, at least partially to the upper face of the pad in order to dissipate heat generated by the optical amplifier to the substrate made of silicon, wherein
the pad is produced from silicon nitride, and
the passive optical component is disposed directly below, in a direction perpendicular to the plane of the substrate, the optical amplifier and is narrower than the optical amplifier in a dimension parallel to the plane of the substrate.

US Pat. No. 10,340,655

OPTICAL WAVEGUIDE AS AMPLIFIER FIBRE FOR HIGH-PERFORMANCE OPERATION

1. A laser/amplifier device comprising a laser, an amplifier fiber and a pump light source, wherein the pump light source optically pumps the amplifier fiber and wherein the amplifier fiber amplifies the radiation of the laser-propagating therein, wherein the core of the amplifier fiber guiding the laser radiation, at least in sections, is doped with rare earth ions, wherein the maximum small signal gain of the amplifier fiber is up to 60 dB on account of at least one of the concentration of the rare earth ions and the distribution thereof in the light-guiding core, and wherein the mean power of the laser radiation at the output of the amplifier fiber is at least 100 W.

US Pat. No. 10,340,653

SOLID-STATE LASER FOR LIDAR SYSTEM

Luminar Technologies, Inc...

1. A lidar system comprising:a solid-state laser configured to emit pulses of light, wherein the solid-state laser comprises a passively Q-switched laser comprising a gain medium and a saturable absorber, wherein the saturable absorber is bonded to the gain medium;
a scanner configured to scan the emitted pulses of light across a field of regard;
a receiver configured to detect at least a portion of the scanned pulses of light scattered by a target located a distance from the lidar system; and
a processor configured to determine the distance from the lidar system to the target based at least in part on a round-trip time of flight for an emitted pulse of light to travel from the lidar system to the target and back to the lidar system.

US Pat. No. 10,340,652

LASER DEVICE AND METHOD FOR DRIVING LASER DEVICE

LUTRONIC CORPORATION, Go...

1. A laser apparatus, comprising:a pumping laser supply unit emitting a pumping laser having a nano-second pulse width; and
a laser output unit disposed on one side of the pumping laser supply unit and generating an output laser pumped by the pumping laser to have a nano-second pulse width corresponding to the pulse width of the pumping laser,
wherein the laser output unit comprises an output laser medium that comprises Er:YAG and the pumping laser supplied to the laser output unit has a wavelength of 630-670 nm.

US Pat. No. 10,340,651

LIDAR SYSTEM WITH OPTICAL TRIGGER

Luminar Technologies, Inc...

1. A lidar system comprising:a light source configured to emit a ranging pulse of light that is directed into a field of regard of the lidar system, wherein the light source comprises a seed laser diode configured to produce a seed pulse of light and an optical amplifier configured to amplify the seed pulse of light to produce the ranging pulse of light;
a fiber-optic splitter located within the light source, wherein the fiber-optic splitter is configured to split off a portion of the ranging pulse of light to produce a trigger pulse of light that is directed to a receiver of the lidar system;
the receiver, wherein the receiver is configured to:
detect, at a first time, at least a portion of the trigger pulse of light; and
detect, at a second time subsequent to the first time, a portion of the ranging pulse of light scattered by a target located a distance from the lidar system; and
a processor configured to determine the distance from the lidar system to the target based at least in part on the first time and the second time.

US Pat. No. 10,340,650

NEAR-FIELD ELECTRON LASER

1. A near-field electron laser producing laser light from the near-field energy of vibrating electrons, comprising a light source and a sealed container; wherein the working medium of the laser is electron; the interior of the sealed container is filled with an electron gas, the light source produces an incident light which is a parallel monochromatic light or a laser light, the average distance between electrons in the sealed container is much smaller than the wavelength of the incident light, the electron number density is much greater than the negative third power of the wavelength of the incident light, and the product of the number of electrons in the sealed container and the distance between the electrons is much greater than the wavelength of the incident light, so that the vibrating electrons are in the near-field of each other; the electric field intensity direction of the incident light and the electric moments of the vibrating electrons are in the same radial straight line and in the same direction, and there exists a radial attractive force among the vibrating electrons; the radial attractive force among the vibrating electrons is controlled by controlling the charge amount and amplitude of an accelerating charge that produces the incident light and the distance between the light source and the vibrating electrons, so that the average kinetic energy of the electrons for thermal motion is reduced to nearly zero, and cause the electrons to vibrate in the same radial straight line and in the same direction and have a constant frequency, amplitude and phase difference, and the interference effects of the radiation of various vibrating electrons are used to obtain a stronger directionality and intensity to form a laser light;the incident light is produced by a vibrating electric dipole with a radiated electric field of E(t):where Q is charge amount, a is amplitude, ? is frequency, ?0 is a vacuum dielectric constant, c is a vacuum light speed, and R is the distance from an observation point to the centre of the vibrating electric dipole.

US Pat. No. 10,340,649

C-BAND AND L BAND AMPLIFIER DESIGN WITH INCREASED POWER EFFICIENCY AND REDUCED COMPLEXITY

NEC CORPORATION, Tokyo (...

1. An improved optical transmission system for carrying C-band and L-band optical signals, the system having a C-band optical path including a C-band optical amplifier and an L-band optical path including an L-band optical amplifier, wherein the C-band optical path and the L-band optical path are substantially isolated from one another, said system including an input optical path and an optical circulator, said input optical path in optical communication with the optical circulator, the circulator in further optical communication with the C-band optical path and the L-band optical path, said system including an output optical path and a second circulator, said second optical circulator in optical communication with the C-band optical path at a point in the path after the C-band optical amplifier, said second optical circulator in optical communication with the L-band optical path at a point in the path before the L-band optical amplifier, and said optical circulator in optical communication with the output path,said system CHARACTERIZED IN THAT:the system is configured such that a pre-determined amount of C-band optical energy is applied to an input of the L-band optical amplifier;
the amount of C-band optical energy applied to the input is the L-band optical amplifier is more than 1% but less than 10% of the total C-band optical energy and is between 5 to 25 dB less than the power level of an L-band signal input to the L-band optical amplifier;
the optical circulator is configured to apply the pre-determined amount of C-band optical energy to the L-band optical path such that it is received by the L-band optical amplifier;
the optical circulator directs a portion of the C-band optical energy output from the C-band optical amplifier to an input of the L-band optical amplifier; and
no optical isolators are interposed between the circulators and the amplifiers.

US Pat. No. 10,340,648

CABLE CONNECTOR CLOCKING DEVICE AND RELATED COMPONENTS, SYSTEMS, AND METHODS

Lockheed Martin Corporati...

1. A clocking assembly for cable connectors comprising:at least one socket adapter sub-assembly comprising:
a socket portion having a first end and a second end, wherein the first end is configured to be connected to a cable connector;
an adapter portion comprising:
a generally cylindrical body portion having a first end and a second end, wherein the second end of the socket portion is connected to the first end of the cylindrical body portion; and
at least one indicium proximate to the first end of the cylindrical body portion configured to indicate a clock angle of the cable connector when the cable connector is connected to the socket portion; and
a fastener fixedly securing the socket portion to the adapter portion, the fastener extending through an opening in the cylindrical body portion of the adapter portion, the fastener comprising a spindle portion having a first non-circular cross-section and the opening in the cylindrical body portion having a second non-circular cross-section configured to prevent rotation of the fastener with respect to the adapter portion; and
an adapter holder sub-assembly comprising:
at least one clamp portion configured to receive the adapter portion of the socket adapter sub-assembly within the at least one clamp portion; and
a face portion having a plurality of indicia indicative of different clock angles, wherein:
the at least one clamp portion has an unclamped configuration, in which the at least one socket adapter sub-assembly is rotatable to align the indicium of the adapter portion with an indicium of the plurality of indicia of the face portion; and
the at least one clamp portion has a clamped configuration, in which the at least one socket adapter sub-assembly is retained with the indicium of the adapter portion aligned with an indicium of the plurality of indicia of the face portion.

US Pat. No. 10,340,647

METHOD OF CONSTRUCTING A SOLDERLESS DC CABLE

TRISIMIAN, LLC, Raleigh,...

1. A method for constructing a solderless DC cable comprising the steps:a. providing a cable operative to transmit a DC current, said cable having a conductive inner core, a core insulator wrapped about said inner core, a metal conductive shield formed about said core insulator and a shearable outer jacket;
b. providing first and second plugs, said first and second plugs being operatively functional as conventional 2.1 mm male connectors, each respective first and second plug having an outer barrel portion defining a proximal end and a distal end, said barrel portion having an external male sleeve portion extending from the distal end thereof, said barrel portion further defining a threaded axial passageway extending into the proximal side thereof, said external sleeve, barrel portion and threaded portion all being in electrical communication relative one another, each respective first and second plug further having an internal pin assembly disposed within said barrel portion of said plug whereby said internal pin assembly includes a distally extending conductive sleeve and further including a conductive pin extending proximally therefrom and into said threaded axial passageway, each respective first and second plug further having a non-conductive electrically insulated sleeve disposed between and separating said barrel portion and distal male sleeve extending therefrom from said internal pin assembly;
c. defining a first respective end of said cable provided in step a) and inserting said end within said axial passageway of a respective one of said plugs provided in step b);
d. rotating said plug upon said end of said cable such that said threads within said axial passageway shear said outer jacket of said cable such that said threads of said barrel portion electrically contact said metal conductive shield of said cable, said end of said cable being advanced within said axial passageway to a degree sufficient for said pin of said internal pin assembly to establish electric communication with said inner core of said cable;
e. defining a second respective end of said cable provided in step a) and inserting said second end within said axial passageway of said respective other of said plugs provided in step b); and
f. rotating said respective other plug upon said second end of said cable such that said threads within said axial passageway shear said outer jacket of said cable such that said threads of said barrel portion electrically contact said metal conductive shield of said cable, said second end of said cable being advanced within said axial passageway to a degree sufficient for said pin of said internal pin assembly to establish electric communication with said inner core of said cable.

US Pat. No. 10,340,645

MULTIFUNCTIONAL SOCKET

Bestore Europe Holding Gm...

1. A multifunctional socket, comprising: a main socket module and at least two functional device modules,wherein the functional device modules and the main socket module can be assembled in any manner, at least one of the functional device modules is detachably connected to the main socket module, adjacent functional device modules are detachably connected, the at least one of the functional device modules and the main socket module are electrically connected, and the adjacent functional device modules are electrically connected,
the functional device module comprises a wireless charging module, and the wireless charging module comprises a wireless charging base,
a peripheral side of the wireless charging module is provided with a slide rail, a storage member is slidably arranged on the slide rail, the storage member is provided with a storage compartment, and the wireless charging base is arranged on a bottom surface of the storage compartment.

US Pat. No. 10,340,644

ELECTRIC VEHICLE CHARGING CONNECTOR DEVICE AND A PLUG CONNECTOR AND A RECEPTACLE CONNECTOR THEREOF

CHENG UEI PRECISION INDUS...

1. An electric vehicle charging connector device and a plug connector and a receptacle connector thereof, wherein the plug connector is docked with the receptacle connector, wherein:the plug connector includes:
a first insulating body having a first outer ring base and a first inner ring base inside the first outer ring base, the first inner ring base protruding towards the first outer ring base to form a plurality of columns extending longitudinally, each two of the plurality of the columns defining a guiding groove therebetween;
a first circuit board disposed at a side of the first insulating body and having a plurality of first through holes each located corresponding to the guiding groove;
a plurality of contact terminals each inserted in the guiding groove and in each of the plurality of the first through holes of the first circuit board;
a first electrode unit disposed inside the first insulating body, and including a first conducting sleeve and a second conducting sleeve, the first conducting sleeve being positively charged, the second conducting sleeve being negatively charged; and
a first jumper unit electrically connected with the first electrode unit and including a first jumper body and a second jumper body, the first jumper body being riveted to the first conducting sleeve and the second jumper body being riveted to the second conducting sleeve;
the receptacle connector includes:
a second insulating body having a second outer ring base and an inner side of the second outer ring base defined with an outer ring groove, a retaining wall rising from a middle of the outer ring groove, the retaining wall extending laterally to form a stair surface, a plurality of slits disposed on the stair surface;
a second circuit board disposed at a side of the second insulating body and having a plurality of second through holes located corresponding to the plurality of the slits;
a plurality of docking terminals each abutting on the retaining wall and inserted in each of the plurality of the second through holes of the second circuit board through each of the plurality of the slits;
a second electrode unit disposed inside the second insulating body, and including a third conducting sleeve and a fourth conducting sleeve, the third conducting sleeve being negatively charged, the fourth conducting sleeve being positively charged; and
a second jumper unit electrically connected with the second electrode unit and including a third jumper body and a fourth jumper body, the third jumper body being riveted to the third conducting sleeve and the fourth jumper body being riveted to the fourth conducting sleeve.

US Pat. No. 10,340,643

CHARGING CONNECTOR

HORIZON CO., LTD., Nagan...

1. A charging connector comprising: a pair of power supply terminals for pinching power supply terminals of a Type-C plug connector complying with the USB connector standard from both sides, and a pair of grounding terminals for pinching grounding terminals of the plug connector from both sides; whereinthe power supply terminals and the grounding terminals are configured by fork terminals;
the power supply terminals are mutually connected through a cooling plate which is provided with a soldering terminal at opposite side of the fork terminals;
the grounding terminals are mutually connected through a cooling plate which is provided with a soldering terminal at opposite side of the fork terminals;
one of the soldering terminals is located at an upper side of a circuit board to which the charging connector is to be connected; and
the other of the soldering terminals is located at a lower side of the circuit board.

US Pat. No. 10,340,642

FUSE-EQUIPPED HERMETIC TERMINAL

SCHOTT Japan Corporation,...

1. A fuse-equipped hermetic terminal comprising:a housing provided with a hollow portion and a pair of through holes located with the hollow portion being interposed therebetween;
a conductive pin extending through the housing via the pair of through holes and the hollow portion; and
a pair of insulating sealing materials that each hermetically seal a gap between the conductive pin and a corresponding one of the pair of through holes,
wherein:
the conductive pin includes an inner pin, an outer pin, and a fuse element that bridges between the inner pin and the outer pin and that is located in the hollow portion,
center axes of the pair of through holes are offset from each other out of axial alignment, and
the inner pin and the outer pin respectively extend through the through holes on opposite sides of the hollow portion, and respectively extend outwardly from the housing on opposite sides of the housing.

US Pat. No. 10,340,641

DEVICE FOR TRANSMITTING DATA

1. A device for data transmission, said device comprising a data module for storing and playing back data, and also a plug connector housing having a cable outlet opening and a cable gland, wherein the device comprises furthermore an adaptor module that comprises at least one cable passage region and that the adaptor module comprises a cable inlet opening at a first end of this cable passage region and a cable outlet opening at a second end of this cable passage region, wherein the adaptor module may be fastened through its cable inlet opening to the cable outlet opening of the plug connector housing, and the cable gland may be fastened to the cable outlet opening of the adaptor module, with the result that the adaptor module may be fastened between the cable outlet opening and the cable gland, and further wherein the adaptor module comprises in addition to the cable outlet opening a further outlet for outputting data.

US Pat. No. 10,340,640

SYSTEM AND METHOD FOR DETERMINING THE CURRENT CONDITION OF POWER CONTACTS

SCHNEIDER ELECTRIC USA, I...

1. A system for determining a current condition of a power contact in an electrical contactor comprising:a power contact having a movable contact supported on a bridge and a fixed contact;
a first auxiliary contact having a movable contact supported on a bridge and a fixed contact;
a second auxiliary contact having a movable contact supported on a bridge and a fixed contact;
a contact carrier supporting the movable power contact bridge, the first auxiliary movable contact bridge and the second auxiliary movable contact bridge such that the movable contacts move in unison and such that the movable contacts of the first and second auxiliary contacts are spaced apart by a first fixed distance and the movable contact of the second auxiliary contact and the movable power contact are spaced apart by a second fixed distance;
a controller having a processor and a non-tangible memory, the first fixed distance, the second fixed distance, contactor characteristics and an algorithm for determining the current condition of the power contact being previously stored in the non-tangible memory, the processor receiving a binary signal from each of the power contact, the first auxiliary contact and the second auxiliary contact indicating the opening or closing of their respective movable contacts and storing each binary signal received from the power contact, the first auxiliary contact and the second auxiliary contact in the non-tangible memory; and,
wherein the algorithm, being executed by the processor, determines the current condition of the power contact based on the stored binary signals, the fixed distances and the previously stored contactor characteristics, the processor notifying a preventive maintenance system and/or a user that preventive maintenance on the contactor is required when the determined current condition of the power contact has exceeded a predetermined wear limit.

US Pat. No. 10,340,639

SHIELD SHELL AND SHIELDED CONNECTOR

YAZAKI CORPORATION, Toky...

1. A shield shell comprising:a housing accommodation portion that includes a shell fixing portion configured to be fixed to a conductive mounting target and that is configured to accommodate a housing; and
a shield member mounting portion that is formed so as to be continuous to the housing accommodation portion and that has an outer surface on which a shield member is mounted by fastening of a binding member,
wherein a fastening position aligning unit is provided on an entire circumference or at a plurality of positions of the outer surface of the shield member mounting portion;
wherein the fastening position aligning unit includes an inclined portion and a restricting portion;
wherein the inclined portion is inclined in a tapered shape from a base end side of the shield member mounting portion toward an open end side of the shield member mounting portion; and
wherein the restricting portion is continuous to a lowest portion of the inclined portion and restricts the binding member from moving toward the open end side of the shield member mounting portion when the shield member is pulled toward the open end side of the shield member mounting portion,
wherein the restricting portion intersects the inclined portion at an acute angle.

US Pat. No. 10,340,638

SHIELDED AND MULTISHIELDED COAXIAL CONNECTORS

Holland Electronics, LLC,...

1. A coaxial connector for passing signals similar to those passed by F-Type connectors, the connector comprising:a body, an electrical contact, and a metallic waveguide;
the body including a connection that incorporates the electrical contact;
the electrical contact aligned along a body centerline and electrically isolated from the body; and,
the waveguide fixed within the body and the body centerline passes through a central aperture of the waveguide;
wherein the waveguide faces the electrical contact and is configured to limit entry of stray RF signals into a body region that includes the electrical contact.

US Pat. No. 10,340,574

SPATIAL COMBINING DEVICE AND ANTENNA

Qorvo US, Inc., Greensbo...

1. A spatial power-combining device for modifying a signal, the spatial power-combining device comprising:a plurality of amplifier assemblies, wherein each amplifier assembly comprises:
an amplifier;
an output antenna structure comprising an output ground conductor and an output signal conductor that are entirely separated by air;
a transmission line connected between the amplifier and the output signal conductor; and
an output waveguide configured to combine signals received from the output antenna of each amplifier assembly.

US Pat. No. 10,340,567

MICROWAVE SWITCHING DEVICE WITH THE STATE OF THE CONNECTIONS OF THE INPUTS AND OUTPUTS BEING READ BY TELEMETRY

THALES, Courbevoie (FR)

1. A microwave switching device comprising:a switching matrix with M inputs and N outputs comprising at least one surface-mount microwave switch with ohmic contacts with at least one input and at least one output position;
a control bus for the one or more microwave switches of the switching matrix;
a remote-control bus for the M inputs;
a telemetry bus for the N outputs;
a bias tee positioned on each input of the switching matrix; and
a bias tee positioned on each output of the switching matrix.

US Pat. No. 10,340,536

MODULAR FUEL CELL STRUCTURE, CASING OF THE SAME, AND FUEL CELL SYSTEM

National Taipei Universit...

1. A modular fuel cell structure, which is adapted for injecting a first material and a second material for reaction; comprising:a casing, which has a reaction vessel recessed into a surface thereof, and has a first flow passage, a second flow passage, and a third flow passage provided therein, which all communicate with the reaction vessel, wherein the first flow passage is adapted for delivering the first material into the reaction vessel, the second flow passage is adapted for delivering the second material into the reaction vessel, and the third flow passage is adapted to exhaust the first material and the second material out from the reaction vessel after reaction;
an anode conductive sheet disposed in the reaction vessel;
an air electrode sheet disposed on a side of the anode conductive sheet opposite to the reaction vessel;
a separating membrane disposed between the anode conductive sheet and the air electrode sheet to electrically separate the anode conductive sheet and the air electrode sheet; and
a cathode conductive sheet disposed on the air electrode sheet, wherein the cathode conductive sheet is electrically connected to the air electrode sheet;
wherein the casing has a first surface, a second surface opposite to the first surface, a first end face, and a second end face opposite to the first end face; the first end face and the second end face are both connected to the first surface and the second surface, wherein the reaction vessel is formed on the first surface, and is recessed in a direction toward the second surface; one end of the first flow passage is exposed on a side of the casing near the first end face, while another end thereof communicates with a side of the reaction vessel near the second end face; one end of the second flow passage is exposed on the side of the casing near the first end face, while another end thereof communicates with another side of the reaction vessel near the first end face; one end of the third flow passage communicates with the another side of the reaction vessel near the first end face, while another end thereof is exposed on the side of the casing near the first end face;
wherein the casing further has two opposing side surfaces; a periphery of each of the side surfaces is connected to the first surface, the second surface, the first end face, and the second end face, wherein a distance between the two side surfaces gradually decreases in a direction from the first surface toward the second surface.

US Pat. No. 10,340,534

REVISED FUEL CELL CYCLE FOR IN BLOCK REFORMING FUEL CELLS

LG FUEL CELL SYSTEMS INC....

11. A solid oxide fuel cell system comprising:a solid oxide fuel cell stack comprising at least one solid oxide fuel cell, each solid oxide fuel cell comprising an anode, a cathode, and an electrolyte;
a reformer comprising cold-side channels and hot-side channels;
an anode loop for supplying fuel and reformate to the anode of each solid oxide fuel cell, said anode loop comprising:
a fuel inlet manifold in said fuel cell stack configured to supply fuel and reformate to the anode of each solid oxide fuel cell;
a fuel exhaust manifold configured to receive unused fuel from the anode of each solid oxide fuel cell;
a source of fuel;
an anode ejector configured to receive fuel from said fuel source and said fuel exhaust manifold;
the cold-side channels of said reformer configured to receive fuel from said anode ejector;
a cathode loop for supplying oxidant to the cathode of each solid oxide fuel cell, said cathode loop comprising:
an oxidant inlet manifold in said fuel cell stack configured to supply oxidant to the cathode of each solid oxide fuel cell;
an oxidant exhaust manifold in said fuel cell stack configured to receive unused oxidant from each cathode of said solid oxide fuel cells;
a source of oxidant;
a cathode ejector configured to receive oxidant from said oxidant source and said oxidant exhaust manifold and configured to supply oxidant to said oxidant inlet manifold; and
an auxiliary loop for combusting a portion of the unused fuel from said fuel exhaust manifold and a portion of the unused oxidant from said oxidant exhaust manifold, said auxiliary loop comprising:
the hot-side channels of said reformer configured to receive a portion of the unused oxidant from said oxidant exhaust manifold;
an auxiliary ejector configured to receive the oxidant from the hot-side channels of said reformer, a portion of the oxidant from said oxidant source, and a portion of the unused fuel from said fuel exhaust manifold; and
a combustor configured to receive the exhaust from said auxiliary ejector.

US Pat. No. 10,340,443

PERPENDICULAR MAGNETIC MEMORY WITH FILAMENT CONDUCTION PATH

Intel Corporation, Santa...

1. An apparatus comprising:first and second electrodes on a substrate;
a perpendicular magnetic tunnel junction (pMTJ), between the first and second electrodes, comprising a dielectric layer between a fixed layer and a free layer; and
a third electrode layer, between the pMTJ and the first electrode, including an additional dielectric layer between first and second metal layers;
wherein first metal layer includes a first metal comprising at least one of Copper (Cu), Hafnium (Hf), Titanium (Ti), Ruthenium (Ru), Aluminum, or Silver (Ag), the second metal layer includes a second metal including at least one of Tungsten (W), Hafnium (Hf), Tantalum (Ta), Platinum (Pt), Palladium (Pd) and Ti, and the additional dielectric layer includes a dielectric and the first metal.

US Pat. No. 10,340,436

THERMOELECTRIC ELEMENT, THERMOELECTRIC MODULE, AND HEAT CONVERSION APPARATUS INCLUDING THE SAME

LG INNOTEK CO., LTD., Se...

1. A thermoelectric module comprising:a first substrate;
a thermoelectric element disposed on the first substrate; and
a second substrate disposed on the thermoelectric element,
wherein the thermoelectric element comprises:
a first element portion disposed on the first substrate and having a first cross-sectional area;
a connection portion connected to the first element portion; and
a second element portion connected to the connection portion, disposed between the connection portion and the second substrate, and having a second cross-sectional area;
wherein the connection portion has a third cross-sectional area,
wherein the third cross-sectional area is smaller than at least one of the first cross-sectional area and the second cross-sectional area,
wherein the first cross-sectional area increases as the first element portion is distanced from the connection portion,
wherein the second cross-sectional area increases as the second element portion is distanced from the connection portion,
wherein the first element portion and the second element portion each is formed with two protrusions protruding toward the connection portion and a recess between the two protrusions recessing toward the corresponding first or second substrate, and
wherein the first element portion, the second element portion, and the connection portion are formed from stacked unit members and each of the stacked unit members are formed of the same material.

US Pat. No. 10,340,407

AVALANCHE PHOTODETECTOR

1. An avalanche photodetector (APD) comprising:a photo converter layer for signals to be converted into a current of free charge carriers; and
at least one avalanche amplifier for the current,
wherein the photo converter layer and the avalanche amplifier are located next to each other on the same substrate and are in direct contact with each other,
wherein the avalanche amplifier includes a contact layer and a multiplier layer,
wherein the multiplier layer is made of a semiconductor of the same conductivity type as the photo converter layer and faces the substrate while abutting the photo converter layer on one side, and
wherein a first electrode is on the contact layer of the avalanche amplifier, and the second electrode is on a bottom of the substrate.

US Pat. No. 10,340,404

MULTILAYER FILM AND PHOTOVOLTAIC MODULE

LG Chem, Ltd., Seoul (KR...

1. A photovoltaic module, comprising:a photovoltaic cell; and
a multilayer film disposed below the photovoltaic cell,
wherein the multilayer film comprises a first layer disposed below the photovoltaic cell and including a first matrix resin and first inorganic particles having a band gap energy of 3.3 eV or more; and a second layer disposed below the first layer and including a second matrix resin and second inorganic particles having a band gap energy of less than 3.3 eV,
wherein the only inorganic particles present in the first layer are the first inorganic particles, and the only inorganic particles present in the second layer are the second inorganic particles,
wherein the first layer is disposed closer to incident light than the second layer,
wherein the first layer is directly stacked on the second layer,
wherein the multilayer film has a reflectance of 20.4% or more with respect to UV rays in a wavelength range of 280 to 400 nm, and a reflectance of more than 80% with respect to visible rays in a wavelength range of 400 to 1200 nm,
wherein the first inorganic particles are barium sulfate (BaSO4) and the second inorganic particles are titanium dioxide (TiO2),
wherein the first layer includes the first inorganic particles in an amount of 10 to 200 parts by weight with respect to 100 parts by weight of the first matrix resin, and the second layer includes the second inorganic particles in an amount of 10 to 200 parts by weight with respect to 100 parts by weight of the second matrix resin, and
wherein each of the first matrix resin and the second matrix resin is a mixture consisting of a copolymer of vinylidene fluoride and chlorotrifluoroethylene, a copolymer of vinylidene fluoride and hexafluoropropylene, and an acrylic polymer of methyl methacrylate, glycidyl methacrylate and methyl methacrylic acid.

US Pat. No. 10,340,403

PHOTOVOLTAIC DEVICE

SANYO ELECTRIC CO., LTD.,...

1. A photoelectric conversion device comprising:a crystalline semiconductor substrate having a first surface and a second surface; and
a first amorphous semiconductor layer formed over the first surface of the crystalline semiconductor substrate, wherein
an interface between the crystalline semiconductor substrate and the first amorphous semiconductor layer is an oxidized interface containing oxygen;
the first amorphous semiconductor layer comprises a high-oxygen-concentration region;
the oxidized interface has an oxygen concentration higher than an oxygen concentration of the high-oxygen-concentration region; and
the high-oxygen-concentration region has an oxygen concentration profile in which the oxygen concentration shown in a logarithmic scale is reduced stepwise in two or more steps from a side near the oxidized interface along a thickness direction of the first amorphous semiconductor layer;
the oxygen concentration profile comprises a first region, a second region, a third region, and a fourth region in this order from the side near the oxidized interface along the thickness direction of the first amorphous semiconductor layer;
the first region comprising a rising portion of a first step of the two or more steps;
the third region comprises a rising portion of the second step of the two or more steps;
the first region has a first slope, shown in a logarithmic scale, of the oxygen concentration from the side near the oxidized interface along the thickness direction, a magnitude of the first slope being defined as a first gradient;
the second region has a second slope, shown in a logarithmic scale, of the oxygen concentration from the side near the oxidized interface along the thickness direction, a magnitude of the second slope being defined as a second gradient;
the third region has a third slope, shown in a logarithmic scale, of the oxygen concentration from the side near the oxidized interface along the thickness direction, a magnitude of the third slope being defined as a third gradient;
the fourth region has a fourth slope, shown in a logarithmic scale, of the oxygen concentration from the side near the oxidized interface along the thickness direction, a magnitude of the fourth slope being defined as a fourth gradient; and
the second gradient and the fourth gradient are smaller than the first gradient and the third gradient.

US Pat. No. 10,340,402

METHOD OF PREPARING METAL CHALCOGENIDE NANOPARTICLES AND METHOD OF PRODUCING LIGHT ABSORPTION LAYER THIN FILM BASED THEREON

LG CHEM, LTD., Seoul (KR...

1. A method of preparing metal chalcogenide nanoparticles, the method comprising:heat-treating at least one type of single-source precursor,
wherein the single-source precursor comprises a metal-ligand complex selected from the group consisting of a copper (Cu)-ligand complex, a tin (Sn)-ligand complex and a zinc (Zn)-ligand complex,
wherein the ligand comprises one or more selected from the following:

wherein R is a methyl group, an ethyl group or a propyl group.

US Pat. No. 10,340,401

MULTI-LAYER BACK SURFACE FIELD LAYER IN A SOLAR CELL STRUCTURE

The Boeing Company, Chic...

1. A photovoltaic (PV) cell comprising:an emitter layer comprising a first material having a first doping;
a base layer having a first side adjacent to said emitter layer and a second side, said base layer comprising the first material having a second doping that is opposite the first doping and a first bandgap between 0.7 eV and 2.0 eV; and
a back surface field (BSF) layer adjacent to said base layer, said BSF layer comprising:
a first, strained layer adjacent to said second side of said base layer and comprising a second, indium-free material made of AlGaAs having an aluminum content greater than about 50%, said first, strained layer having a second bandgap between 4.95 eV and 2.1 eV that increases relative to the aluminum content, said first, strained layer comprising a first doping concentration of the second doping achieved using carbon, wherein the first doping concentration is larger than a second doping concentration of the second doping of said base layer and wherein said first, strained layer is fully strained and has a thickness of less than 8 nm; and
a second layer adjacent to said first, strained layer and comprising a third material made of AlGaInAs and a third bandgap, wherein the use of In in said third material reduces the third bandgap to below 2.0 eV and wherein said second layer of said BSF layer is lattice-matched to said base layer.

US Pat. No. 10,340,400

PHOTOELECTRIC CONVERSION DEVICE, METHOD OF MANUFACTURING THE SAME, AND CAMERA

CANON KABUSHIKI KAISHA, ...

1. A photoelectric conversion device that includes a silicon substrate,wherein the silicon substrate includes a first portion configured to perform photoelectric conversion, and a second portion containing carbon, the second portion being arranged farther apart from a light receiving surface of the silicon substrate than the first portion,
wherein a carbon peak concentration in the second portion is 1×1018 [atoms/cm3] to 1×1020 [atoms/cm3], and
wherein an oxygen peak concentration in the second portion is 1/1000 to 1/10 of the carbon peak concentration.

US Pat. No. 10,340,399

OPTICAL DEVICE

PHOTONICS ELECTRONICS TEC...

1. An optical device comprising:a semiconductor layer which comprises Ge and has a (001) plane and a facet surface between the (001) plane and a (110) plane; and
a cap layer which comprises Si and is formed on the (001) plane and the facet surface of the semiconductor layer;
wherein a ratio of a film thickness of the cap layer at the facet surface to a film thickness of the cap layer at the (001) plane is equal to or greater than 0.4 and equal to or less than 0.77.

US Pat. No. 10,340,397

OPTICAL SENSOR DEVICE

ABLIC Inc., (JP)

6. An optical sensor device, comprising:a die pad portion;
an optical sensor element disposed on the die pad portion;
a plurality of leads formed separately around the die pad portion;
a first resin molding portion holding a periphery of the die pad portion and first peripheries of the plurality of leads excluding a portion in which a surface of each of the plurality of leads used as a wire bonding portion is exposed after integration by contact fitting molding using a first resin; and
a second resin molding portion covering an entire periphery of the first resin molding portion, at least a part of an upper surface of the optical sensor element, and second peripheries of the plurality of leads by contact fitting molding using a second resin, the second resin molding portion having one of a resin with transparency, a resin containing a filler of finely pulverized glass having a first filter function, and a resin containing a dye or a pigment having a second filter function.

US Pat. No. 10,340,396

METHOD FOR MANUFACTURING SOLAR CELL

LG ELECTRONICS INC., Seo...

1. A method for manufacturing a solar cell, the method comprising:forming a semiconductor layer on one surface of a semiconductor substrate;
forming a mask layer comprising a first layer and a second layer sequentially on the semiconductor layer;
texturing another surface of the semiconductor substrate using the mask layer as a mask;
forming a patterned mask layer by forming an opening in the mask layer through a laser patterning using a laser; and
forming a conductive region through a doping process of doping a portion of the semiconductor layer exposed through the opening with a dopant.

US Pat. No. 10,340,395

SEMICONDUCTOR VARIABLE CAPACITOR USING THRESHOLD IMPLANT REGION

QUALCOMM Incorporated, S...

18. A semiconductor variable capacitor comprising:a first non-insulative region disposed in a gate region above a first semiconductor region;
a second non-insulative region disposed above the first semiconductor region;
a threshold voltage (Vt) implant region interposed between the first non-insulative region and the first semiconductor region and disposed adjacent to the second non-insulative region; and
a control region disposed above a second semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region,
wherein the first semiconductor region is a retrograde well formed on a semiconductor substrate, and
wherein the Vt implant region is disposed directly on the first semiconductor region and has a same doping type as the first semiconductor region.

US Pat. No. 10,340,394

III-V SEMICONDUCTOR DIODE

3-5 Power Electronics Gmb...

1. A stacked III-V semiconductor diode comprising:an n+-layer with an upper side, a lower side, a dopant concentration of at least 1019 N/cm3 and a layer thickness of about 675 microns or less, wherein said n+-layer comprises a GaAs compound;
an n?-layer with an upper side and a lower side, a dopant concentration of 1012-1016 N/cm3, a layer thickness of 10-300 microns, and comprising a GaAs compound;
a p+-layer with an upper side, a lower side, a dopant concentration of 5×1018-5×1020 N/cm3, with a layer thickness greater than 2 microns and comprising a GaAs compound; and
a p-type intermediate layer with a layer thickness of 1-50 microns and a dopant concentration of 1012-1017 N/cm3 is disposed between the n?-layer and the p+-layer, and is materially bonded with an upper side and a lower side, and the lower side of the p-type intermediate layer is materially bonded with the upper side of the n?-layer, and the upper side of the p-type intermediate layer is materially bonded with the lower side of the p+-layer,
wherein the n+-layer, the n?-layer, and the p+-layer are monolithically formed,
wherein the n+-layer or the p+-layer is formed as a substrate and the lower side of the n?-layer is materially connected to the upper side of the n+-layer,
wherein the p-type intermediate layer is materially bonded with the n?-layer and with the p+-layer and is p-doped,
wherein the stacked III-V semiconductor diode has a first defect layer with a layer thickness between 0.5 microns and 40 microns,
wherein the first defect layer is arranged within the p-type intermediate layer, and
wherein the first defect layer has a first defect concentration ranging between 1×1013 N/cm3 and 5×1016 N/cm3.

US Pat. No. 10,340,393

SEMICONDUCTOR CONSTRUCTIONS, METHODS OF FORMING VERTICAL MEMORY STRINGS, AND METHODS OF FORMING VERTICALLY-STACKED STRUCTURES

Micron Technology, Inc., ...

1. A memory device, comprising:a stack of alternating electrically conductive levels and electrically insulative levels over a material comprising tungsten silicide;
electrically insulative pillars that extends through the stack and contactan upper surface of the material comprising tungsten silicide;a channel material post between a first adjacent pair of the pillars, the channel material post extending through the material comprising tungsten silicide and having a first pair of opposing sides and a second pair of opposing sides; each side of the first pair of opposing sides being spaced from a respective one of a second adjacent pair of the pillars by a corresponding intervening region of the stack; none of the stack being present between each side of the second pair of opposing sides and a respective one of the first adjacent pair of the pillars;
gate dielectric material and charge-storage material between edges of the electrically conductive levels and the channel material post.

US Pat. No. 10,340,392

SEMICONDUCTOR DEVICE INCLUDING MARK PORTION AND PRODUCTION METHOD FOR SAME

Sharp Kabushiki Kaisha, ...

1. A semiconductor device comprising: a substrate; a thin film transistor supported by the substrate; an interlayer insulating layer covering the thin film transistor; and a wire connecting portion,wherein the thin film transistor includes a gate electrode provided on the substrate, a gate insulating layer covering the gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a protection layer covering at least a channel region of the oxide semiconductor layer, and a source electrode and a drain electrode, each of which is in contact with the oxide semiconductor layer,
the wire connecting portion includes
a lower electrically-conductive portion formed out of a same electrically-conductive film as the gate electrode,
an insulating layer which is provided on the lower electrically-conductive portion and which has a contact hole through which at least a part of the lower electrically-conductive portion is exposed, and
an upper electrically-conductive portion, at least a part of which is provided inside the contact hole,
the insulating layer includes the gate insulating layer, the protection layer and the interlayer insulating layer,
at a lateral wall of the contact hole, the gate insulating layer includes an upper portion and a lower portion which is present on the substrate side of the upper portion, and when viewed in a normal direction of the substrate, a lateral surface of the lower portion juts out from a lateral surface of the upper portion, and
the upper electrically-conductive portion is in contact with the lower electrically-conductive portion and the lateral surface and an upper surface of the lower portion of the gate insulating layer inside the contact hole, and
the semiconductor device further includes
a mark portion formed out of a same electrically-conductive film as the gate electrode;
an island-shaped insulating film covering the mark portion;
an oxide semiconductor cover portion formed out of a same semiconductor film as the oxide semiconductor layer and arranged so as to at least partially overlap the mark portion with the insulating film interposed therebetween; and
an upper electrical conductor cover portion covering the oxide semiconductor cover portion, wherein
at a periphery of the insulating film, the insulating film includes another upper portion and another lower portion which is present on the substrate side of the another upper portion, a lateral surface of the another lower portion jutting out from a lateral surface of the another upper portion when viewed in the normal direction of the substrate,
the lateral surface of the another upper portion is in alignment with a lateral surface of the oxide semiconductor cover portion, and
the upper electrical conductor cover portion is arranged so as to be in contact with the lateral surface and an upper surface of the another lower portion, the lateral surface of the another upper portion, and the lateral surface and an upper surface of the oxide semiconductor cover portion.

US Pat. No. 10,340,391

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

United Microelectronics C...

1. A method for fabricating a semiconductor device, comprising:forming an oxide semiconductor layer, over a substrate;
forming a metal nitride layer over the oxide semiconductor layer;
patterning the metal nitride layer to form a source electrode and a drain electrode of a metal nitride; and
forming a metal-nitride oxidation layer on a surface of the source electrode and the drain electrode,
wherein a metal plasma is provided under a power range of 5 kw to 15 kw and flashing of only N2 by a range of 30 sccm to 50 sccm for forming the metal nitride layer having reduced oxidation, thereby facilitating reduction of thickness of the metal-nitride oxidation layer to be equal to or less than 0.2 of a thickness of the drain electrode or the source electrode.

US Pat. No. 10,340,390

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

SHARP KABUSHIKI KAISHA, ...

1. A semiconductor device comprising:a substrate, a thin-film transistor supported on the substrate, and a first insulating layer,
the thin-film transistor including a semiconductor layer, a gate electrode, a gate insulating layer arranged between the gate electrode and the semiconductor layer, a source electrode, and a drain electrode, the source electrode and the drain electrode being in contact with the semiconductor layer, wherein
one of an upper surface and a lower surface of the semiconductor layer is in contact with the gate insulating layer, the other is in contact with the first insulating layer,
the semiconductor layer has a laminated structure including a first oxide semiconductor layer and a second oxide semiconductor layer, the first oxide semiconductor layer is arranged on a gate insulating layer side of the second oxide semiconductor layer and is in contact with the second oxide semiconductor layer,
the first insulating layer contains silicon oxide,
the second oxide semiconductor layer contains In and Ga and does not contain Sn,
the first oxide semiconductor layer contains In, Sn, and Zn,
a percentage of Zn in the first oxide semiconductor layer in a depth direction does not have a maximum value in a vicinity of a surface of the first oxide semiconductor layer adjacent to the second oxide semiconductor layer,
a percentage of Sn having a metallic bonding state at an interface between the first oxide semiconductor layer and the second oxide semiconductor layer is 90% or less with respect to a total amount of Sn, and
a region where the percentage of Sn having the metallic bonding state at the interface between the first oxide semiconductor layer and the second oxide semiconductor layer is 50% or more with respect to the total amount of Sn has a thickness of less than 10 nm.

US Pat. No. 10,340,389

MULTI-GATE THIN FILM TRANSISTORS, MANUFACTURING METHODS THEREOF, ARRAY SUBSTRATES, AND DISPLAY DEVICES

BOE Technology Group Co.,...

1. A thin film transistor comprising a base substrate, an active layer, a source, a gate, and a drain, the active layer, the source, the gate, and the drain disposed on the base substrate, the active layer including an end connected to the source and another end connected to the drain,the gate including a top gate and a bottom gate, the top gate including a top gate top portion and a top gate side portion connected to the top gate top portion, the top gate top portion and the bottom gate arranged opposite to each other in a direction perpendicular to the base substrate, the top gate side portion extending from the top gate top portion towards the base substrate and not physically contacting the bottom gate,
the active layer sandwiched between the top gate top portion and the bottom gate, and the active layer including a sidewall at least partially surrounded by the top gate side portion.

US Pat. No. 10,340,387

LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND ARRAY SUBSTRATE

WUHAN CHINA STAR OPTOELEC...

1. A manufacturing method of a low temperature poly-silicon thin film transistor, comprising:providing a substrate and sequentially forming a buffer layer, a low temperature poly-silicon layer, a source contact region, a drain contact region, a gate insulator layer, a gate layer, and a dielectric layer on the substrate, wherein the source contact region and the drain contact region are disposed in a same layer as the low temperature poly-silicon layer and are respectively disposed at two opposite ends of the low temperature poly-silicon layer;
respectively forming a first contact hole and a second contact hole through the dielectric layer and the gate insulator layer by dry etching to expose the source contact region and the drain contact region respectively; wherein an etching gas used in the dry etching comprises a fluorine-containing gas and a hydrogen gas; and
forming a source electrode on the dielectric layer to contact the source contact region through the first contact hole and a drain electrode on the dielectric layer to contact the drain contact region through the second contact hole;
wherein during the dry etching, a pressure is in a range of 30-50 mtorr, a gas source power is in a range of 400-800 W, and a bias voltage is in a range of 100-200 V.

US Pat. No. 10,340,386

ELECTRONIC DEVICE INCLUDING LIGHT DETECTION DEVICE AND OPERATION METHOD THEREOF

Samsung Electronics Co., ...

1. An electronic device comprising:a housing;
a display exposed through a surface of the housing;
a light emitting unit configured to be disposed on at least a part of a rear surface of the display, and including at least one light source for outputting light of at least one wavelength band;
a light receiving unit configured to include at least one area for receiving light of the at least one wavelength band;
a light blocking element that blocks light output from the at least one light source, from entering a switch for turning on/off at least one pixel of the display;
a processor electrically connected with the display, the light emitting unit, and the light receiving unit; and
a memory electrically connected with the processor,
wherein the memory includes instructions configured to cause, when executed, the processor to output light through the at least one light source in a state where one or more pixels included in a specific area of the display, which includes an area covering the at least one light source, are turned off or displayed in a specific color.

US Pat. No. 10,340,385

METHOD TO IMPROVE FINFET DEVICE PERFORMANCE

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:providing a substrate structure comprising a PMOS region and an NMOS region, the PMOS region including a first semiconductor region, a first gate structure on the first semiconductor region, and a first epitaxial grown raised source region and a first epitaxial grown raised drain region on opposite sides of the first gate structure, the NMOS region including a second semiconductor region and a second gate structure on the second semiconductor region;
introducing a p-type dopant into the first epitaxial grown raised source region and the first epitaxial grown raised drain region;
performing a first annealing process on the substrate structure after the p-type dopant has been introduced into the first epitaxial grown raised source region and the first epitaxial grown raised drain region;
forming a second source region and a second drain region on opposite sides of the second gate structure;
introducing an n-type dopant into the second source region and the second drain region; and
performing a second annealing process on the substrate structure after the n-type dopant has been introduced into the second source region and the second drain region.

US Pat. No. 10,340,384

METHOD OF MANUFACTURING FIN FIELD-EFFECT TRANSISTOR DEVICE

Taiwan Semiconductor Manu...

1. A method comprising:forming a first fin protruding above a substrate, the first fin having a PMOS region;
forming a first gate structure over the first fin in the PMOS region;
forming a first spacer layer over the first fin and the first gate structure;
forming a second spacer layer over the first spacer layer;
performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region;
performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and
epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.

US Pat. No. 10,340,383

SEMICONDUCTOR DEVICE HAVING STRESSOR LAYER

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a fin extending along a first direction over a semiconductor substrate;
a gate structure extending in a second direction overlying the fin,
wherein the gate structure comprises:
a gate dielectric layer overlying the fin;
a gate electrode overlying the gate dielectric layer; and
insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction;
a source/drain region in the fin in a region adjacent the gate structure,
wherein the source/drain region consists essentially of Ge or SiGe and a first dopant; and
a stressor layer between the source/drain region and the semiconductor substrate,
wherein the stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a second dopant, and
a portion of the fin under the gate structure is a channel region.

US Pat. No. 10,340,382

EMBEDDED SOURCE OR DRAIN REGION OF TRANSISTOR WITH DOWNWARD TAPERED REGION UNDER FACET REGION

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:providing a semiconductor structure comprising a body structure;
forming a gate structure over the body structure;
forming a first pair of dielectric structures abutting the body structure;
removing a portion of the body structure and a portion of the first pair of dielectric structures to form downward tapered sidewalls of the first pair of dielectric structures to define a source or drain recess;
growing stressor material with a lattice constant different from that of the body structure in the source or drain recess to form a source or drain region, wherein the source or drain region comprises:
a first region formed above a first level at a top of the first pair of dielectric structures; and
a second region formed under the first level and abutting the downward tapered side walls of the first pair of dielectric structures.

US Pat. No. 10,340,381

METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE

UNITED MICROELECTRONICS C...

1. A method for fabricating a semiconductor structure, comprising:providing a substrate;
forming a dielectric layer on the substrate;
forming a gate conductive layer and two spacers disposed in the dielectric layer, wherein the two spacers are respectively disposed on both sides of the gate conductive layer;
forming a high-k layer and a work function metal layer between the gate conductive layer and the substrate;
removing parts of the gate conductive layer, parts of the high-k layer and parts of the work function metal layer;
removing parts of the two spacers, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and wherein a top surface of the high-k layer and a top surface of the work function metal layer are higher than the top surface of the two spacers and lower than the top surface of the gate conductive layer; and
forming a cap layer overlying the gate conductive layer and the two spacers, wherein parts of the cap layer is located right above the two spacers.

US Pat. No. 10,340,380

THREE-DIMENSIONAL TRANSISTOR WITH IMPROVED CHANNEL MOBILITY

GLOBALFOUNDRIES Inc., Gr...

1. A semiconductor structure, comprising:a plurality of spaced apart fins, each of said plurality of spaced apart fins comprising a semiconductor material;
a dielectric material layer positioned between each of said plurality of spaced apart fins;
a common gate structure positioned above said dielectric material layer and extending across each of said plurality of spaced apart fins;
a continuous merged semiconductor material region positioned on each of said plurality of spaced apart fins and above said dielectric material layer, wherein said continuous merged semiconductor material region is laterally spaced apart from said common gate structure and extends between and physically contacts each of said plurality of spaced apart fins, said continuous merged semiconductor material region having a first sidewall surface that faces toward said common gate structure and a second sidewall surface that is opposite of said first sidewall surface and faces away from said common gate structure, wherein said first sidewall surface of said continuous merged semiconductor material region, a first portion of opposing sidewall surfaces of an adjacent pair of said plurality of spaced apart fins, and a first portion of an upper surface of said dielectric material layer at least partially define a first space between said continuous merged semiconductor material region and said common gate structure, and wherein said second sidewall surface of said continuous merged semiconductor material region, a second portion of said opposing sidewall surfaces of said adjacent pair of said plurality of spaced apart fins, and a second portion of said upper surface of said dielectric material layer at least partially define a second space on an opposite side of said continuous merged semiconductor material region from said first space; and
a stress-inducing material positioned in said first space.

US Pat. No. 10,340,379

SEMICONDUCTOR DEVICE WITH PLURALITY OF ACTIVE BARRIER SECTIONS

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first output element;
a second output element that is provided to be spaced apart from the first output element when seen in a plan view;
a circuit unit that is provided between the first output element and the second output element when seen in a plan view;
a first element isolation section that is configured in a closed pattern enclosing the circuit unit when seen in a plan view;
a second element isolation section that is configured in a closed pattern enclosing the first element isolation section while spaced apart from the first element isolation section when seen in a plan view;
an isolation section that is connected to the first element isolation section and the second element isolation section and separates a region sandwiched between the first element isolation section and the second element isolation section into a first region and a second region;
a first barrier section that is enclosed by the first region when seen in a plan view; and
a second barrier section that is enclosed by the second region when seen in a plan view.

US Pat. No. 10,340,378

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first electrode;
a first semiconductor region provided on the first electrode and electrically connected to the first electrode, the first semiconductor region being of a first conductivity type;
a second semiconductor region provided on the first semiconductor region, the second semiconductor region being of a second conductivity type;
a third semiconductor region provided on a portion of the second semiconductor region, the third semiconductor region being of the first conductivity type;
a gate electrode provided on the first semiconductor region, the gate electrode including
a first portion, the first portion opposing, in a second direction with a gate insulating portion interposed, the second semiconductor region, a portion of the first semiconductor region, and at least a portion of the third semiconductor region, the second direction being perpendicular to a first direction, the first direction being from the first semiconductor region toward the second semiconductor region,
a second portion separated from the first portion in a third direction, the third direction being perpendicular to the first direction and the second direction, and
a third portion positioned between the first portion and the second portion,
a fourth semiconductor region including a first region and being of the second conductivity type, the first region opposing the second portion in the second direction with the gate insulating portion interposed;
an interconnect portion provided on the third portion and electrically connected to the third portion; and
a second electrode provided on the second semiconductor region, the third semiconductor region, and the first region, the second electrode being electrically connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region and electrically isolated from the interconnect portion.

US Pat. No. 10,340,377

EDGE TERMINATION FOR SUPER-JUNCTION MOSFETS

Vishay-Siliconix, San Jo...

1. A metal oxide semiconductor field effect transistor (MOSFET) comprising:a core region comprising a plurality of parallel core plates coupled to a source terminal of said super-junction MOSFET; and
a termination region surrounding said core super-junction region comprising
a plurality of termination segments configured to force breakdown into said core super-junction region and away from said termination region,
wherein all said termination segments in said termination region are electrically floating,
wherein each of said termination segments has a length dimension less than a length dimension of said core plates.

US Pat. No. 10,340,376

HETEROJUNCTION FIELD-EFFECT TRANSISTOR HAVING GERMANIUM-DOPED SOURCE AND DRAIN REGIONS

OMMIC, Limeil Brevannes ...

1. A heterojunction field-effect transistor comprising:a semiconductor structure made up of superposed layers, comprising in a stacking order on a substrate layer:
a buffer layer composed of a material having a hexagonal crystal structure of Ga(1-x-y)Al(x)In(y)N, where x and y are comprised between 0 inclusive and 1 inclusive, the sum x+y being lower than or equal to 1,
a channel layer on the buffer layer, the channel layer being composed of a material having a hexagonal crystal structure of Ga(1-z-w)Al(z)In(w)N, where z and w are comprised between 0 inclusive and 1 inclusive, the sum z+w being lower than or equal to 1, at least one of z and w being different from x or y, respectively, and
a barrier layer on the channel layer, the barrier layer being composed of a material having a hexagonal crystal structure of Ga(1-z?-w?)Al(z?)In(w?)N, where z? and w? are comprised between 0 inclusive and 1 inclusive, the sum z?+w? being lower than or equal to 1, at least one of z? and w? being different from z or w, respectively,
a layer of epitaxial material, deposited by epitaxy on a growth zone corresponding to the location of an opening formed in a dielectric masking layer, the growth material having a hexagonal crystal structure and being composed of Ga(1-x?-y?)Al(x?)In(y?)N and previously-doped with germanium, where x? and y? are comprised between 0 inclusive and 1 inclusive, the sum x?+y? being lower than or equal to 1, at a temperature sufficient for constituent atoms of the semiconductor material having the hexagonal crystal structure of Ga(1-x?-y?)Al(x?)In(y?)N doped with germanium to migrate toward the growth zone, by mass transport, and
a contact electrode on the layer of growth material and a gate electrode in a location outside of the growth zone,
wherein the material doped with germanium has a sufficiently defined crystal structure for lateral edges of the growth layer to have an inclination between 5° and 60° relative to the vertical.

US Pat. No. 10,340,375

EPITAXIAL SUBSTRATE FOR FIELD EFFECT TRANSISTOR

SUMITOMO CHEMICAL COMPANY...

1. An epitaxial substrate for a field effect transistor, said epitaxial substrate comprising:a ground layer;
a first buffer layer that (i) is disposed directly and physically above the ground layer, (ii) has a thickness from 50 angstroms to 2000 angstroms, and (iii) contains only AlN doped with Mn as a compensation impurity element at a first concentration from 1E10 cm?3 to 1E20 cm?3;
a second buffer layer that (i) is disposed directly and physically above the first buffer layer, (ii) has a thickness of 5,000 angstroms or more, and (iii) contains only AlGaN doped with Mn at a second concentration from 1E15 cm?3 to 5E20 cm?3;
an epitaxial crystal layer that (i) is disposed directly and physically above the second buffer layer and (ii) is an undoped epitaxial crystal layer containing only GaN; and
an operating layer that is disposed above the epitaxial crystal layer and comprises undoped AlGaN.

US Pat. No. 10,340,374

HIGH MOBILITY FIELD EFFECT TRANSISTORS WITH A RETROGRADED SEMICONDUCTOR SOURCE/DRAIN

Intel Corporation, Santa...

1. A monolithic high mobility field effect transistor, comprising:a gate electrode over a channel region comprising a first III-V semiconductor material of a first alloy composition; and
a pair of semiconductor source/drain regions impurity doped to a same conductivity type and interfacing the channel region, the source/drain regions comprising a compositionally graded III-V semiconductor alloy varying between:
the first alloy composition proximal to an interface of the channel region and a second alloy composition a first distance from the interface, wherein material with the second alloy composition has a charge carrier-blocking band offset from material with the first alloy composition; and
the second alloy composition and a third alloy composition at a second distance from the interface, material with the third alloy composition having a non-blocking band offset from material with the second alloy composition.

US Pat. No. 10,340,373

REVERSE CONDUCTING IGBT

University of Electronic ...

1. A reverse conducting insulated gate bipolar transistor (RC-IGBT), comprising:a P-type region;
an N-type emitter region;
a P-type body contact region;
a dielectric trench;
a collector region; and
an electrical field cutting-off region,
wherein
the P-type region is formed on a surface of a N-type high resistance semiconductor material,
the N-type emitter region and the P-type body contact region are alternately formed on a surface of the P-type region side by side along a lateral direction of the RC-IGBT,
the dielectric trench is formed in a central region of the N-typed emitter region and passes through the P-type region,
a bottom of the dielectric trench contacts the N-type high resistance semiconductor material,
in the dielectric trench are provided an insulating dielectric layer located at an inner wall of the dielectric trench and a conductive material surrounded by the insulating dielectric layer,
a gate electrode is led out from the conductive material in the dielectric trench to form a trench-gate structure,
a common terminal led out from the N-type emitter region and the P-type body contact region serves as an emitter electrode,
on a backside of the high resistance N-type semiconductor material, a collector region consists of a N-type area and a P-type area that are continuously alternately disposed along the lateral direction of the RC-IGBT,
a common terminal led out from the N-type area and the P-type area serves as a collector electrode,
an electrical field cutting-off region is provided on the top of the collector region,
there is an interval of the N-type high resistance material between the electrical field cutting-off region and the collector region in a longitudinal direction of the RC-IGBT,
the electrical field cutting-off region is formed by N-type heavily doped regions and P-type lightly doped regions that are continuously alternately disposed along the lateral direction of the RC-IGBT, and
the lateral direction and the longitudinal direction of the RC-IGBT are in the same plane and are perpendicular to each other.

US Pat. No. 10,340,372

TRANSISTOR DEVICE HAVING A PILLAR STRUCTURE

Semiconductor Components ...

1. An apparatus, comprising:a first trench disposed in a semiconductor region and including a gate electrode;
a second trench disposed in the semiconductor region;
a mesa region disposed between the first trench and the second trench;
a source region of a first conductivity type disposed in a top portion of the mesa region;
an epitaxial layer of the first conductivity type;
a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type, the second conductivity type being different than the first conductivity type; and
a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to, and in contact with the pillar, and a second portion of the source region is disposed above, and in contact with the pillar.

US Pat. No. 10,340,371

MODULATION DEVICE COMPRISING A NANODIODE

CENTRE NATIONAL DE LA REC...

1. A modulation device made on a substrate including at least one nanodiode which appears as T fitted into a U, a channel of this nanodiode being a leg of the T which penetrates into the U,characterized in that it includes at least one electrically conductive line which passes over at least one portion of this channel thereby forming a switch.

US Pat. No. 10,340,370

ASYMMETRIC GATED FIN FIELD EFFECT TRANSISTOR (FET) (FINFET) DIODES

QUALCOMM Incorporated, S...

1. An asymmetric gated fin Field Effect Transistor (FET) (finFET) diode, comprising:a substrate comprising:
a first-type well region; and
a fin disposed in a direction, the fin comprising:
a first source/drain region having a first length in the direction, wherein, within the first length, the first source/drain region comprises a first-type doped material disposed in the fin and extending in the direction from a first side to a second side of the first-type doped material;
a second source/drain region having a second length in the direction that is larger than the first length, wherein, within the second length, the second source/drain region comprises a second-type doped material disposed in the fin and extending in the direction from a first side to a second side of the second-type doped material; and
a gate region disposed between the first source/drain region and the second source/drain region having a third length in the direction that is equal to the second length plus a difference of the second length and the first length.

US Pat. No. 10,340,369

TUNNELING FIELD EFFECT TRANSISTOR

GLOBALFOUNDRIES Inc., Gr...

1. A tunneling field effect transistor device comprising a drain region, a source region and a gate region, the device comprising:a semiconductor substrate;
a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above said substrate, said body having an axis that is oriented substantially perpendicular to an upper surface of said substrate, said body having two side surfaces and an upper surface, said body extending a full length of said drain region, said gate region and said source region, wherein said first semiconductor material is part of said drain region;
a second semiconductor material positioned above at least a portion of said gate region and above said source region, wherein said second semiconductor material defines said channel region;
a third semiconductor material positioned above said second semiconductor material and above at least a portion of said gate region and above said source region, said third semiconductor material being doped with a second type of dopant material that is opposite to said first type of dopant material, wherein said third semiconductor material is part of said source region; and
a gate structure positioned above said first, second and third semiconductor materials in said gate region, wherein said gate structure includes a gate insulation layer and said third semiconductor material has an uppermost surface having a height greater than a height of an uppermost surface of said gate insulation layer.

US Pat. No. 10,340,368

FIN FORMATION IN FIN FIELD EFFECT TRANSISTORS

International Business Ma...

1. A method of forming a semiconductor device, the method comprising:forming a plurality of fins from a first material;
depositing a semiconductor layer formed from a second material over the plurality of fins;
depositing dielectric material covering the plurality of fins and the semiconductor layer, the dielectric material defining dielectric regions; and
diffusing the second material from the semiconductor layer into an entirety of each fin of the plurality of fins.

US Pat. No. 10,340,367

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:forming a spacer layer over a dummy gate, formed over a first portion of a fin structure, and a second portion of the fin structure;
forming a dielectric layer over the spacer layer;
removing the dielectric layer and the spacer layer formed over the dummy gate to expose the first portion of the fin structure;
forming a gate stack over the exposed first portion of the fin structure;
forming trenches by removing the dielectric layer formed over a remaining portion of the spacer layer and a portion of a height of the fin structure underneath the dielectric layer; and
forming source and drain contacts by filling the trenches with a metal.

US Pat. No. 10,340,366

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device including a Fin FET, the method comprising:forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, a part of the upper layer being exposed from an isolation insulating layer;
forming a dummy gate structure over a part of the fin structure, the dummy gate structure extending in a second direction crossing the first direction;
removing the dummy gate structure and forming a gate structure in a region in which the dummy gate structure is removed;
forming an interlayer dielectric layer over the fin structure and the gate structure;
forming a contact hole in the interlayer dielectric layer so that a part of the fin structure is exposed;
forming a source/drain structure on the exposed fin structure;
directly depositing a cap layer, by using a first gas and a second gas, on the source/drain structure, the cap layer covering a bottom surface and sidewalls of the contact hole;
forming a dielectric layer over the cap layer; and
forming a contact metal layer over the dielectric layer.

US Pat. No. 10,340,365

METHOD OF MANUFACTURING A THIN FILM TRANSISTOR

SHENZHEN CHINA STAR OPTOE...

1. A method of manufacturing a thin film transistor, comprising:providing a substrate;
depositing a buffer layer on the substrate and patterning the buffer layer, so as to form an active area of a thin film transistor;
sequentially depositing an insulation layer and a first metal layer on the substrate;
coating a photoresist on a gate region and a lightly doped region of the first metal layer, wherein the gate region and the lightly doped region are covered by a projection of the active area on the first metal layer;
metal etching the first metal layer excluding the gate region and the lightly doped region for exposing the insulation layer;
ashing the photoresist for exposing the lightly doped region of the first metal layer;
metal etching the first metal layer at the lightly doped region for forming a metal half tone mask;
implanting ions to the active area for forming a source region, a source lightly doped region, a channel region, a drain lightly doped region, and a drain region of the thin film transistor;
removing the photoresist;
depositing a media layer over the substrate, and forming a source through-hole and a drain through-hole on the media layer;
depositing a second metal layer over the substrate, and patterning the second metal layer, so as to form a source and a drain of the thin film transistor through the source through-hole and the drain through-hole;
depositing an organic planarization layer over the substrate, and forming a pixel electrode through-hole on the organic planarization layer; and
depositing a pixel electrode layer over the substrate, and patterning the pixel electrode layer, so as to form a corresponding pixel electrode through the pixel electrode through-hole;
wherein the step of depositing the buffer layer on the substrate and patterning the buffer layer, comprises:
depositing an amorphous silicon buffer layer on the substrate;
annealing the amorphous silicon buffer layer to form a polycrystalline silicon buffer layer; and
patterning the polycrystalline silicon buffer layer.

US Pat. No. 10,340,364

H-SHAPED VFET WITH INCREASED CURRENT DRIVABILITY

International Business Ma...

1. A method of forming a fin structure for a vertical field effect transistor (VFET), the method comprising the steps of:depositing a hardmask onto a substrate;
depositing a mandrel material onto the hardmask;
patterning the mandrel material along a first direction to form first mandrels;
forming first spacers alongside the first mandrels;
filling gaps between the first mandrels with additional mandrel material to form second mandrels in between the first mandrels;
patterning the first mandrels, the first spacers and the second mandrels along a second direction, wherein the second direction is perpendicular to the first direction;
forming second spacers, perpendicular to the first spacers, alongside the first mandrels and the second mandrels;
selectively removing the first mandrels and the second mandrels leaving behind a ladder-shaped pattern formed by the first spacers and the second spacers;
transferring the ladder-shaped pattern to the hardmask; and
transferring the ladder-shaped pattern from the hardmask to the substrate to form a first fin adjacent to a second fin, and at least one cross fin interconnecting the first fin and the second fin; and
cutting the ladder-shaped pattern in the substrate into individual fin structures, wherein cuts made during the cutting are located to form each individual fin structure comprising: a first cross fin interconnecting the first fin and the second fin at one end of the individual fin structure, and a second cross fin interconnecting the first fin and the second fin at another end of the individual fin structure in an O-shaped fin structure.

US Pat. No. 10,340,363

FABRICATION OF VERTICAL FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED BOTTOM INSULATING SPACERS

International Business Ma...

18. A semiconductor device, comprising:a vertical field effect transistor (FET) device on a semiconductor substrate, wherein the vertical FET device comprises:
a semiconductor fin formed on a recessed surface of a semiconductor substrate;
a lower source/drain region formed on the recessed surface of the semiconductor substrate in contact with a bottom portion of the semiconductor fin, wherein the lower source/drain region comprises a first type of epitaxial semiconductor material;
a self-aligned bottom insulating spacer formed on the lower source/drain region, the self-aligned bottom insulating spacer comprising an oxide layer formed from oxidation of a second type of epitaxial semiconductor material epitaxially grown on the lower source/drain region, which is different from the first type of epitaxial semiconductor material;
a gate structure formed in contact with sidewalls of the semiconductor fin;
an upper insulating spacer formed on the gate structure; and
an upper source/drain region formed on an upper portion of the semiconductor fin;
wherein the self-aligned bottom insulating spacer electrically insulates the lower source/drain region from the gate structure;
wherein the upper insulating spacer electrically insulates the upper source/drain region from the gate structure; and
wherein the first type of epitaxial semiconductor material comprises crystalline silicon germanium with a first concentration of germanium, and wherein the second type of epitaxial semiconductor material comprises crystalline silicon germanium with a second concentration of germanium that is greater than the first concentration of germanium.

US Pat. No. 10,340,362

SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS

GLOBALFOUNDRIES Inc., Gr...

1. A structure comprising:a semiconductor body having a top surface;
an epitaxial layer of semiconductor material on the semiconductor body;
a first gate structure on the semiconductor body, the first gate structure having a sidewall;
a first spacer adjacent to the sidewall of the first gate structure, the first spacer having a first section and a second section vertically between the first section and the top surface of the semiconductor body, the first section of the first spacer having a first thickness, and the second section of the first spacer having a second thickness different from the first thickness; and
a conformal layer on the first spacer and the epitaxial layer of semiconductor material,
wherein the second section of the first spacer is located between the epitaxial layer of semiconductor material and the sidewall of the first gate structure, the first spacer is composed of SiBCN having a first dielectric constant, and the conformal layer is composed of SiBCN having a second dielectric constant that is less than the first dielectric constant of the SiBCN of the first spacer.

US Pat. No. 10,340,361

FORMING OF A MOS TRANSISTOR BASED ON A TWO-DIMENSIONAL SEMICONDUCTOR MATERIAL

1. A MOS transistor manufacturing method, comprising the successive steps of:a) forming a first layer made of a conductive or semiconductor material on a surface of a support substrate;
b) forming a sacrificial gate on the upper surface of the first layer, and a second layer made of an insulating material laterally surrounding the sacrificial gate;
c) forming, on either side of the sacrificial gate, source and drain electric connection elements made of a conductive material, crossing the second layer and contacting the first layer;
d) removing the sacrificial gate and the portion of the first layer located vertically in line with the sacrificial gate;
e) depositing a third layer made of a two-dimensional semiconductor material on the sides and on the bottom of an opening formed at step d) by the removal of the sacrificial gate and of the first layer);
f) depositing a fourth layer made of an insulating material on the third layer; and
g) forming a conductive gate in the opening, on the fourth layer.

US Pat. No. 10,340,360

NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A nitride semiconductor device comprising:an electron transit layer including GaxIn1-xN (0 an electron supply layer formed on the electron transit layer and including AlaGabIncN (0?a?1, 0?b?1, 0?c?1 and a+b+c=1);
a gate insulating film formed to pass through the electron supply layer to contact the electron transit layer; and
a gate electrode facing the electron transit layer with the gate insulating film interposed therebetween,
wherein the gate insulating film includes an oxide of the electron supply layer.

US Pat. No. 10,340,359

GATE STRUCTURE WITH DUAL WIDTH ELECTRODE LAYER

GLOBALFOUNDRIES Inc., Gr...

1. A high-k dielectric metal gate (HKMG) transistor, comprising:a substrate;
an HKMG gate stack with a gate dielectric layer and a gate electrode layer positioned above said substrate, wherein said gate electrode layer has an upper portion and a lower portion;
a first liner contacting a sidewall portion of said upper portion;
a spacer contacting said first liner and a sidewall portion of said lower portion; and
raised source and drain regions adjacent said spacer, wherein a height of an uppermost surface of said spacer is greater than a height of an uppermost surface of said raised source and drain regions, and a width of said upper portion between said raised source and drain regions is smaller than a width of said lower portion between said raised source and drain regions.

US Pat. No. 10,340,356

LAMINATED ARTICLE

IDEMITSU KOSAN CO., LTD.,...

1. A laminated body comprising a substrate, an ohmic electrode layer, a metal oxide semiconductor layer, a Schottky electrode layer and a buffer electrode layer in this order, whereina reduction suppressing layer is provided between the Schottky electrode layer and the buffer electrode layer.

US Pat. No. 10,340,355

METHOD OF FORMING A DUAL METAL INTERCONNECT STRUCTURE

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming source/drain regions on opposite sides of at least one gate structure located over a channel region of a semiconductor fin;
forming a single interlevel dielectric (ILD) layer overlying the source/drain regions and the at least one gate structure;
forming source/drain contact trenches through the ILD layer, each of the source/drain contact trenches exposing at least a portion of one of the source/drain regions; and
forming a source/drain contact structure within each of the source/drain contact trenches, wherein each of the source/drain contact structures comprises a first contact conductor portion located at a bottom portion of each of the source/drain contact trenches and contacting one of the source/drain regions, and a second contact conductor portion overlying the first contact conductor portion, wherein the first contact conductor comprises a first metal and the second contact conductor portion comprises a second metal having a lower electromigration resistance and a lower electrical resistance than the first metal, and wherein each of the source/drain contact structures further comprises an elemental metal liner located on sidewalls of each of the source/drain contact trenches, a metal nitride liner located on the elemental metal liner and a bottom surface of each of the source/drain contact trenches, wherein the metal nitride liner contacts sidewalls and a bottommost surface of the first contact conductor portion, a contact liner located over the metal nitride liner and directly contacting a top surface of the first contact conductor portion, and an adhesion layer portion located on the contact liner and contacting sidewalls and a bottommost surface of the second contact conductor portion, wherein the elemental metal liner has a bottommost surface that is coplanar with a bottommost surface of the metal nitride liner.

US Pat. No. 10,340,354

MANUFACTURING METHOD OF THIN-FILM TRANSISTOR (TFT) ARRAY SUBSTRATE

BOE TECHNOLOGY GROUP CO.,...

1. A method of manufacturing a thin-film transistor (TFT) array substrate, comprising:forming a gate layer, a gate insulating layer, an oxide semiconductor layer, a source/drain electrode layer and a transparent conductive layer on a base substrate,
wherein the forming of the source/drain electrode layer and the transparent conductive layer includes:
forming a transparent conductive film and a first metallic film on the oxide semiconductor layer in sequence, to form a stack layer of the transparent conductive film and the first metallic film, in which the transparent conductive film contacts the oxide semiconductor layer;
forming source electrodes, drain electrodes and pixel electrodes by performing a single patterning process on the stack layer of the transparent conductive film and the first metallic film; and
forming a protective layer film on the first metallic film, and forming the pixel electrodes, the source electrodes, the drain electrodes, and the protective layer by performing a single patterning process on the transparent conductive film, the first metallic film, and the protective layer film;
wherein the protective layer film includes at least one of ITO IZO, IGZO, GZO, or carbon nanotube conductive films.

US Pat. No. 10,340,353

EPITAXIAL METALLIC TRANSITION METAL NITRIDE LAYERS FOR COMPOUND SEMICONDUCTOR DEVICES

The United States of Amer...

9. A semiconductor device, comprising:a substrate;
an epitaxial metal layer selected from the group consisting of TaNx, NbNx, WNx, MoNx, TMN ternary compounds, and combinations thereof; and
at least one epitaxial semiconductor layer comprising a semiconductor material selected from the group consisting of SiC or AlN;
wherein the in-plane lattice constants of the substrate, the epitaxial metal layer, and the epitaxial semiconductor layer are within 2% of one another; and
wherein the epitaxial metal layer is in direct contact with the substrate and the at least one epitaxial semiconductor layer is in direct contact with the epitaxial metal layer to form an epitaxial metal/semiconductor heterostructure, or the at least one epitaxial semiconductor layer is in direct contact with the substrate and the epitaxial metal layer is in direct contact with the at least one epitaxial semiconductor layer to form an epitaxial metal/semiconductor heterostructure.