US Pat. No. 10,395,990

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer;
a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and
a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction,
wherein the first gate structure includes a trench defined by the first gate spacer, and a high-k dielectric insulating film extending along a sidewall and a bottom surface of the trench, and
the high-k dielectric insulating film does not extend along a sidewall of the gate insulating support.

US Pat. No. 10,395,989

MULTI-LAYER WORK FUNCTION METAL GATES WITH SIMILAR GATE THICKNESS TO ACHIEVE MULTI-VT FOR VFETS

International Business Ma...

1. A structure for forming a device having multiple field effect transistors (FETs) with each FET having a different work function, the structure comprising:first, second, third, and fourth FETs formed over a semiconductor substrate;
an interfacial layer and a high-k dielectric layer formed over the first, second, third, and fourth FETs;
a first work function conducting layer formed over the high-k dielectric layer, where the first work function conducting layer is subsequently removed from the third FET;
a second work function conducting layer disposed in direct contact with portions of the first work function conducting layer, where the second work function conducting layer is subsequently removed from the second FET;
a third work function conducting layer disposed in direct contact with portions of the second work function conducting layer, where the third work function conducting layer is subsequently removed from the first FET;
a fourth work function conducting layer disposed in direct contact with portions of the third work function conducting layer;
a fifth work function conducting layer, where the fifth work function conducting layer is subsequently removed from the third and fourth FETs; and
first and second conducting layers formed over the first, second, third, and fourth FETs.

US Pat. No. 10,395,988

VERTICAL FET TRANSISTOR WITH REDUCED SOURCE/DRAIN CONTACT RESISTANCE

International Business Ma...

1. A method for reducing contact resistance and parasitic capacitance, the method comprising:forming a bottom source/drain region between a plurality of fins;
forming a bottom spacer over the bottom source/drain region;
forming high-k metal gates (HKMGs) over the bottom spacer;
forming a top spacer over the HKMGs and an interlayer dielectric (ILD) over the top spacer;
recessing the ILD to expose top sections of the plurality of fins;
depositing an epitaxial material over the top sections of the plurality of fins; and
forming a dielectric film over the epitaxial material such that air-gaps are created over the top spacer, the dielectric film recessed to expose top sections of the epitaxial material and to deposit a silicide metal liner and a conductive material thereon.

US Pat. No. 10,395,986

FULLY ALIGNED VIA EMPLOYING SELECTIVE METAL DEPOSITION

International Business Ma...

1. A method for creating a fully-aligned via (FAV) by employing selective metal deposition, the method comprising:forming metal lines within a first inter-layer dielectric (ILD) layer;
forming a second ILD layer over the first ILD layer;
forming a lithographic stack over the second ILD layer to define areas where via growth is prevented;
recessing the lithographic stack to expose a top surface of the metal lines where via growth is permitted by the lithographic stack; and
performing metal growth over the exposed top surface of the metal lines where via growth is permitted; and
removing the lithographic stack and depositing a conformal metal nitride cap in direct contact with a top surface and an entire length of sidewalls of the metal growth.

US Pat. No. 10,395,985

SELF ALIGNED CONDUCTIVE LINES WITH RELAXED OVERLAY

INTERNATIONAL BUSINESS MA...

1. A semiconductor structure, comprising:a first hardmask on an insulator layer;
a planarizing layer on the first hardmask;
a second hardmask on a portion of the planarizing layer;
a third hardmask on the planarizing layer and on the second hardmask;
sacrificial mandrels on portions of the second hardmask;
a mandrel on the third hardmask; and
an organic planarizing layer on the third hardmask, on spacer material, on the sacrificial mandrels, and on a mandrel including spacer material.

US Pat. No. 10,395,984

SELF-ALIGNED VIA INTERCONNECT STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A method, comprising:forming a wiring structure in a dielectric layer;
depositing a dielectric cap layer over the wiring structure and the dielectric layer;
etching an opening in the dielectric cap layer, exposing a surface of the wiring structure;
forming a self-aligned via interconnect structure in direct electrical contact with the metal material of the wiring structure by overfilling the opening with a metal or metal-alloy growth process to have the self-aligned via interconnect structure in direct electrical contact with the wiring structure and directly on a portion of a top surface of the dielectric cap layer adjacent to the opening, wherein the growth process is performed while the entire top surface of the dielectric cap layer is exposed, wherein a contact region between the self-aligned via interconnect structure and the portion of the top surface of the dielectric cap layer which the self-aligned via interconnect structure is formed on is devoid of a barrier material and liner material;
depositing an interlevel dielectric material over the self-aligned via interconnect structure and the top surface of the dielectric cap layer;
etching a trench within the interlevel dielectric material to expose one or more surfaces of the self-aligned via interconnect structure;
depositing a barrier material and liner material over the exposed one or more surfaces of the self-aligned via interconnect structure and on sidewalls of the trench; and
electroplating a metal or metal-alloy material on the liner material to complete formation of an upper wiring structure, in electrical contact with the self-aligned via interconnect structure.

US Pat. No. 10,395,983

METHOD OF FORMING TRENCHES

Taiwan Semiconductor Manu...

1. A method comprising:forming a first material layer over a substrate;
forming a first trench in the first material layer;
forming a second material layer along sidewalls of the first trench;
forming a second trench in the first material layer while the second material layer is disposed along the sidewalls of the first trench, wherein the second material layer has a tapered top surface after the forming of the second trench;
after the forming of the second trench, extending the first trench to expose a portion of the substrate within the first trench; and
forming a conductive feature within the first trench and the second trench such that the conductive feature covers the second material layer having the tapered top surface.

US Pat. No. 10,395,982

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate including a first region and a second region;
a lower layer structure on the substrate, the lower layer structure having a first thickness on the first region and a second thickness on the second region, the second thickness being greater than the first thickness, the lower layer structure including an electrode layer at a top and an insulating layer under the electrode layer;
an etch stop layer on the lower layer structure;
an upper layer structure on the etch stop layer, a top surface of the upper layer structure being substantially a same level on the first and second regions, the etch stop layer having an etch selectivity with respect to both the upper layer structure and the lower layer structure;
a first contact plug filling a first opening, the upper layer structure and the etch stop layer including the first opening defined therethrough on the first region, the first contact plug being in connection with the electrode layer of the lower layer structure; and
a second contact plug filling a second opening, the upper layer structure and the etch stop layer including the second opening defined therethrough on the second region, a bottom surface of the first contact plug having a first distance from a bottom surface of the etch stop layer and a bottom surface of the second contact plug having a second distance from the bottom surface of the etch stop layer, the first distance being different from the second distance.

US Pat. No. 10,395,981

SEMICONDUCTOR DEVICE INCLUDING A LEVELING DIELECTRIC FILL MATERIAL

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a dielectric fill material above and laterally adjacent to a transistor element of a semiconductor device and a circuit element, said transistor element comprising a gate electrode structure including a dielectric capping layer, said circuit element having an electrode structure covered by a further dielectric capping layer;
removing a portion of said dielectric fill material so as to expose a surface of said dielectric capping layer and a surface of said further dielectric capping layer;
removing said dielectric capping layer and said further dielectric capping layer after removing said portion of said dielectric fill material, wherein a non-removed portion of said dielectric fill material remains laterally adjacent to said transistor element and said circuit element;
masking said circuit element by a mask layer after removal of said dielectric capping layer of said gate electrode structure and said further dielectric capping layer of said electrode structure;
forming a metal semiconductor compound in a semiconductor containing electrode material of said gate electrode structure, wherein said metal semiconductor compound in said gate electrode structure is formed in the presence of said mask layer so as to prevent formation of a metal semiconductor compound in said electrode structure; and
removing a further portion of said dielectric fill material so as to expose surface areas of drain and source regions of said transistor element.

US Pat. No. 10,395,980

DUAL AIRGAP STRUCTURE

GLOBALFOUNDRIES INC., Gr...

1. A structure, comprising:a lower metal line;
a plurality of upper metal lines;
a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines; and
a second airgap between the plurality of upper metal lines,
wherein the first airgap is a bottom airgap, the bottom airgap is directly attached to a top surface of the lower metal line and situated between sidewalls of a capping material which acts as an etch stop material, and the lower metal line comprises a different material than the capping material, and
the etch stop material is directly above a top surface of a dielectric material and below a bottom surface of the upper metal lines.

US Pat. No. 10,395,979

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate;
a first lower insulating interlayer, a protection insulating layer, and a first upper insulating interlayer that are sequentially stacked on the substrate; and
a conductive pattern penetrating the first upper insulating interlayer, the protection insulating layer; and the first lower insulating interlayer,
wherein the conductive pattern comprises a line part extending in a direction parallel to an upper surface of the substrate and contact parts extending from the line part toward the substrate,
wherein the contact parts are spaced apart from each other with an insulating pattern therebetween,
wherein the insulating pattern comprises a portion of the first upper insulating interlayer, a portion of the protection insulating layer, and a portion of the first lower insulating interlayer, and
wherein at least a portion of the insulating pattern has a stepped profile.

US Pat. No. 10,395,977

SELF ALIGNED VIA AND PILLAR CUT FOR AT LEAST A SELF ALIGNED DOUBLE PITCH

INTERNATIONAL BUSINESS MA...

1. A method of forming via openings comprising:forming a first set of spacers on sidewalls of a first set of mandrels, the first set of mandrels present on a mandrel material layer for forming a second mandrel that is present overlying a hardmask layer and at least one interlevel dielectric layer;
etching the mandrel material layer using the first set of spacers as an etch mask to form a second set of mandrels, wherein etching the mandrel material layer includes removing the first set of mandrels;
forming a second set of spacers on sidewalls of the second set of mandrels;
etching the hardmask layer using the second set of spacers and the second set of mandrels to define a first pillar of hardmask material;
etching the interlevel dielectric layer using the first pillar of hardmask material and a first via etch mask to provide a first via opening;
removing the second set of mandrels; and
forming a second via opening in the interlevel dielectric layer.

US Pat. No. 10,395,975

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

DENSO CORPORATION, Kariy...

1. A semiconductor device comprising:a semiconductor substrate made of a semiconductor material including
a plurality of elements arranged at a front surface portion of the semiconductor substrate,
an insulation film arranged at a rear surface portion of the semiconductor substrate, and
a trench arranged to insulate and separate at least one of the plurality of elements by surrounding the at least one of the plurality of elements,
wherein:
the trench is arranged to penetrate both sides of the semiconductor substrate,
the trench has an inner part where a hollow space is arranged,
the trench has an inner wall surface of the semiconductor material, and the inner wall surface of the semiconductor material is exposed to the hollow space of the trench at both sides of the trench,
the trench has an upper layout with a shape from a bird's eye view that is line-symmetrical with respect to two directions orthogonal to each other as symmetrical lines, and
the at least one of the plurality of elements is surrounded and isolated by the hollow space of the trench and the insulation film and provides a separate semiconductor device that withstands insulation breakdown with other of the plurality of elements adjacent to the at least one of the plurality of elements,
wherein the trench includes two side surfaces of the trench as wall surfaces opposite to each other configured to generate an electrostatic attraction force that prevents tiling of an island constituting an element forming region based on a resulting imbalance of electrostatic attraction forces.

US Pat. No. 10,395,974

METHOD FOR FORMING A THIN SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor-on-insulator (SOI) substrate, the method comprising:epitaxially forming an etch stop layer on a sacrificial substrate;
epitaxially forming a device layer on the etch stop layer, wherein the device layer has a different crystalline lattice than the etch stop layer;
bonding the sacrificial substrate to a handle substrate, such that the device layer and the etch stop layer are between the sacrificial and handle substrates;
removing the sacrificial substrate; and
performing an etch into the etch stop layer to remove the etch stop layer, wherein the etch is performed using an etchant comprising hydrofluoric acid, hydrogen peroxide, and acetic acid, wherein the etchant further comprises a solvent within which the hydrofluoric acid, the hydrogen peroxide, and the acetic acid are dissolved, and wherein the hydrofluoric acid, the hydrogen peroxide, and the acetic acid have individual weight percentages in the etchant that are respectively about 8-10, about 5.25-15.75, and about 38.4-56.7.

US Pat. No. 10,395,973

ISOLATION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

SK hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:a substrate including a trench and a plurality of active regions are defined by the trench, wherein the trench include a first trench and a second trench is wider than the first trench;
a liner lining over inner surfaces of the first and the second trenches;
a gap-fill layer formed over the liner to fill the first and the second the trenches; and
a capping layer formed between the liner and the gap-fill layer and extending over a top surface of the gap-fill layer to form a merged overhang in the first trench.

US Pat. No. 10,395,972

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

MagnaChip Semiconductor, ...

1. A semiconductor device comprising:a substrate;
a deep well region in the substrate;
a body region in the deep well region;
a source region in the body region;
a gate electrode formed on the substrate and overlapping with the body region;
a deep trench in the substrate;
a support formed between air claps respectively formed within the deep trench provided around two adjacent semiconductor devices, the support being configured to maintain a shape of respective air gaps; and
a channel stop implantation region at a bottom of the deep trench,
wherein the deep trench is tapered in shape so that an upper end of the deep trench has a greater width than a lower end of the deep trench.

US Pat. No. 10,395,971

DAM LAMINATE ISOLATION SUBSTRATE

TEXAS INSTRUMENTS INCORPO...

1. An apparatus, comprising:a lead frame;
a dam and adhesive on portions of the lead frame; and
an integrated circuit die having a portion on the dam and another portion on the adhesive, wherein the lead frame includes two lead frames.

US Pat. No. 10,395,969

TRANSPARENT HALO FOR REDUCED PARTICLE GENERATION

Varian Semiconductor Equi...

1. An apparatus comprising:a platen for supporting a workpiece; and
a halo surrounding the platen, the halo comprising:
a first side opposite a second side, and a first end opposite a second end, wherein the first side is operable to receive an ion beam from an ion source; and
a plurality of apertures extending between the first side and the second side, wherein the plurality of apertures permit passage of a portion of the ion beam to pass therethrough, and
wherein a first group of apertures of the plurality of apertures has a first diameter, the first group of apertures positioned along a midpoint between the first and second ends, wherein a second group of apertures of the plurality of apertures has a second diameter, the second group of apertures positioned along at least one of: the first end, and the second end, and wherein the first diameter is greater than the second diameter.

US Pat. No. 10,395,968

SUBSTRATE TRANSPORT DEVICE, DETECTION POSITION CALIBRATION METHOD AND SUBSTRATE PROCESSING APPARATUS

SCREEN Holdings Co., Ltd....

10. A detection position calibration method for calibrating a position of a substrate detected by a plurality of detectors provided in a substrate transport device,the substrate transport device comprising:
a movable element;
a first driver that moves the movable element;
a holder that is configured to hold the substrate;
a second driver that moves the holder in a first direction with respect to the movable element; and
a plurality of detectors that are provided to respectively detect a plurality of portions in an outer periphery of the substrate moved by the holder, and
the detection position calibration method including the steps of:
during a detection position calibrating operation, moving the holder with respect to the movable element by the second driver and calculating deviation amounts respectively between design positions of the plurality of detectors and actual positions of the plurality of detectors based on output signals of the plurality of detectors, and
during a substrate transport operation, detecting a position of the substrate in the holder based on output signals of the plurality of detectors and the calculated deviation amounts.

US Pat. No. 10,395,967

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

17. A method of manufacturing a semiconductor device, comprising:(a) forming a circuit on a first surface of a semiconductor wafer, the semiconductor wafer having a second surface opposite to first surface;
(b) grinding the second surface of the semiconductor wafer such that a first part is thinner than a second part surrounding the first part;
(c) attaching a bonding surface of a first tape to the first surface of the semiconductor wafer;
(d) separating the first part from the second part by cutting a part of the first part with a first rotary blade in contact with the second surface of the first part, while the semiconductor wafer is held by the first tape;
(e) after (d), removing the second part;
(f) attaching a bonding surface of a second tape to the second surface side of the first part of the semiconductor wafer while the first tape remains attached to the semiconductor wafer; and
(g) after (f), peeling off the first tape from the semiconductor wafer,
wherein (d) comprises:
(d1) forming a trench by performing a cutting process at the second surface side of the first part by moving the first rotary blade to draw an arc along an outer edge of the first part of the semiconductor wafer while rotating the rotary blade; and
(d2) after (d1), performing another cutting process by moving the first rotary blade along the trench to further cut the first part in a thickness direction thereof, thereby separating the first part from the second part;
wherein the first tape includes:
a first base material, and
a first adhesive layer provided at one surface of the first base material and attached to the first surface of the semiconductor wafer,
wherein the second tape includes:
a second base material, and
a second adhesive layer provided at one surface of the second base material and attached to the second surface of the first part of the semiconductor wafer, and
wherein the first adhesive layer is thicker than the second adhesive layer, and
the method further comprises:
after (d), forming a mark for identifying a direction of the semiconductor wafer, in part of the first tape.

US Pat. No. 10,395,963

ELECTROSTATIC CHUCK

ENTEGRIS, INC., Billeric...

1. An electrostatic chuck comprising:an electrode; and
a surface layer activated by a voltage in the electrode to form an electric charge to electrostatically clamp a substrate to the electrostatic chuck, the surface layer including:
(i) a dielectric comprising a bulk resistivity greater than about 1012 ohm-cm;
(ii) a plurality of protrusions extending to a height above portions of the surface layer surrounding the protrusions to support the substrate upon the protrusions during electrostatic clamping of the substrate, the protrusions being substantially equally spaced across the surface layer as measured by a center to center distance between pairs of neighboring protrusions, the protrusions comprising a low stress material having an internal compressive film stress less than about 450 MPa and comprising an overcoating of diamond like carbon; and
(iii) a charge control surface layer coating overlying the dielectric and comprising a thickness in the range of from about 0.1 microns to about 10 microns and a surface resistivity in the range of from about 1×108 ohms/square to about 1×1011 ohms/square, the charge control surface layer comprising a surface coating layer comprising portions of the surface layer surrounding the protrusions, above which the protrusions extend.

US Pat. No. 10,395,962

SUBSTRATE ARRANGEMENT APPARATUS AND SUBSTRATE ARRANGEMENT METHOD

SCREEN Holdings Co., Ltd....

10. A substrate arrangement apparatus for disposing each of a plurality of first substrates in a first substrate group between each pair of a plurality of second substrates in a second substrate group,wherein each substrate in said first substrate group and said second substrate group is curved in a first radial direction to one side in the thickness direction with a minimum curvature, and
said each substrate is curved in a second radial direction to said one side in the thickness direction with a maximum curvature, said second radial direction being orthogonal to said first radial direction with an angle that is greater than or equal to 45 degree and less than or equal to 135 degrees,
wherein the substrate arrangement apparatus comprises
a controller for disposing each of said plurality of first substrates between each pair of said plurality of second substrates, in a state that said first radial direction of said plurality of first substrates is orthogonal to said first radial direction of said plurality of second substrates.

US Pat. No. 10,395,961

POSTURE CHANGING DEVICE

SCREEN Holdings Co., Ltd....

1. A posture changing device for changing a posture of a substrate from one of horizontal and vertical postures to the other posture, the device comprising:a vertical holder for, when a substrate is in a vertical posture, catching and holding a lower edge portion of said substrate on two sides in a circumferential direction of a bottom edge portion of said substrate, with said bottom edge portion projecting downward from said vertical holder;
a horizontal holder for, when said substrate is in a horizontal posture, supporting a lower surface of said substrate from underside on two sides in a radial direction of said substrate, said horizontal holder being disposed above and adjacent to said vertical holder in a state in which said vertical holder holds said substrate in a vertical posture;
a mounting block on which said vertical holder and said horizontal holder are mounted;
a holder rotator that rotates said mounting block about a rotational shaft pointing in a horizontal direction to switch between a vertical holding state and a horizontal holding state, said vertical holding state being a state in which said vertical holder is capable of holding said substrate in a vertical posture, and said horizontal holding state being a state in which said horizontal holder is capable of holding said substrate in a horizontal posture;
a holder shifter that shifts said horizontal holder relative to said vertical holder in a thickness direction of said substrate;
a pusher for transferring said substrate held in a vertical posture to and from said vertical holder;
a controller for, before transfer of said substrate between said vertical holder and said pusher, controlling said holder shifter on the basis of a warped state of said substrate to shift a position in said thickness direction of said horizontal holder by a shift distance from said vertical holder, said shift distance being determined on the basis of said warped state; and
a substrate alignment mechanism for rotating said substrate in a circumferential direction to change a circumferential orientation of said substrate,
wherein, when said substrate is curved in one radial direction to one side in said thickness direction with a minimum curvature, said controller controls said substrate alignment mechanism on the basis of the warped state of said substrate, before transfer of said substrate between said vertical holder and said pusher, to make said one radial direction of said substrate that is held in a vertical posture by said vertical holder, parallel to an up-down direction.

US Pat. No. 10,395,960

HIGH DENSITY STOCKER WITH INTERLOCKING NUBS

MURATA MACHINERY, LTD., ...

1. A substrate stocker system comprising:a high density storage chamber that comprises one or more high density containers or stacks of one or more substrates, each of the one or more substrates being supported on a respective carrier wherein the one or more high density containers or stacks are in a closed position;
one or more low density containers, each of the one or more low density containers being configured to store one or more substrates;
one or more opener stations, each of the one or more opener stations configured to send or receive one or more stacks or containers from the high density storage chamber and one or more substrates from the one or more low density containers, each of the one or more opener stations comprising one or more separator modules for changing one or more distances between corresponding one or more adjacent substrates in the one or more high density containers or stacks;
a load port; and
at least one robot configured to move:
one or more containers or stacks between the high density storage chamber and the one or more opener stations; and
one or more substrates between the one or more high density containers or stacks and the one or more low density containers;whereinthe one or more opener stations are located between the load port and the high density storage chamber;whereina separator module included within the one or more opener stations comprises:
a conveyor belt; and
a motor driven cogwheel; wherein
the conveyor belt comprises a plurality of interlocking nubs which interlock into corresponding notches in individual carriers; and
the conveyor belt is driven such that the plurality of interlocking nubs interlock with the carrier and move or separate the one or more carriers and substrates by one or more predefined distances.

US Pat. No. 10,395,958

METHODS FOR INSPECTION SAMPLING ON FULL PATTERNED WAFER USING MULTIPLE SCANNING ELECTRON BEAM COLUMN ARRAY

1. A method of operating a multi-column electron beam array, the method comprising:dividing a whole wafer area collectively in equally divided areas allocated to each column of the array;
assigning each of the areas as a column working space having the same dimensions and orientations;
aligning the array of column working spaces to an array of column optical axes;
wherein a field of view of each column is defined as a covered region in which critical wafer patterns can be scanned by one column to take an image;
moving the stage supporting the wafer such that each column working space is fully covered by the field of view of each column completely;
scanning and imaging all critical sites inside the working space while ignoring non-critical patterns; and
wherein a position and dimension of critical sites in different working spaces is independently determined by an algorithm that accounts for lithography conditions and critical features in the patterning database.

US Pat. No. 10,395,957

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND STORAGE MEDIUM

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus, comprising:a substrate processing unit including a plurality of processing chambers each configured to perform a process on a substrate;
a mounting unit configured to mount thereon at least one carrier, each carrier comprising substrates to be processed;
wherein the substrates of each carrier are processed in accordance with a processing recipe;
wherein each carrier possesses a first substrate number, the first substrate number indicating the number of substrates to be processed per unit time in the substrate processing unit according to the processing recipe;
a substrate transfer device provided between the mounting unit and the processing chambers, wherein the substrate transfer device comprises a transfer arm holding the substrate; and
a computer having:
a memory which stores a plurality second substrate numbers, each second substrate number indicating the number of substrates capable of being processed per unit time in the substrate processing unit for a given operating speed of the substrate transfer device; and
wherein the memory stores a mapping table that correlates each of the plurality of second substrate numbers with a respective operating speed of the substrate transfer device, and
a controller configured to:
compare a first substrate number with each of the plurality of second substrate numbers in the mapping table,
when the first substrate number is not equal to the second substrate number, select, from the mapping table, a smallest second substrate number from the plurality of second substrate numbers that is larger than the first substrate number; and
control the substrate transfer device based on the operating speed in the mapping table which corresponds to the smallest second substrate number.

US Pat. No. 10,395,955

METHOD AND SYSTEM FOR DETECTING A COOLANT LEAK IN A DRY PROCESS CHAMBER WAFER CHUCK

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:configuring a dry wafer processing chamber to process a wafer, wherein the dry wafer processing chamber comprises a wafer chuck with a flat mounting surface for mounting the wafer for processing, the wafer chuck is further configured to include a coolant loop within the wafer chuck, and the coolant loop is disposed under the wafer for transferring heat and cooling the wafer chuck by a coolant during a cooling phase of the processing;
measuring relative humidity (RH) of the dry wafer processing chamber;
detecting a change in the RH greater than a threshold value, the change being caused by a leak in the coolant; and
triggering a shutdown of the processing in response to the change.

US Pat. No. 10,395,952

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD

SCREEN Holdings Co., Ltd....

1. A substrate processing method comprising:a substrate processing step of processing a substrate held by a substrate holding unit by supplying a high-temperature processing liquid having a predetermined first temperature that is higher than a room temperature to a processing liquid distribution passage of a processing liquid distributing member and discharging the processing liquid from a discharge port communicating with the processing liquid distribution passage; and
an equilibrium temperature maintaining step of maintaining an inner wall surface of the processing liquid distributing member at a thermal equilibrium temperature which is higher than the room temperature and lower than the first temperature by heating or cooling an outer wall surface of the processing liquid distributing member from the outside to change a temperature of the processing liquid distributing member in a state where the substrate processing step is not performed.

US Pat. No. 10,395,951

METHOD OF CLEANING A SUBSTRATE AND APPARATUS FOR PERFORMING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacture, the method comprising:providing a substrate on a support;
spraying a protecting liquid on a first portion of a surface of the substrate from a first position in a first spray direction;
injecting cleaning droplets on the first portion of the surface of the substrate;
spraying the protecting liquid on a second portion of the surface of the substrate from a second position different from the first position in a second spray direction different from the first spray direction; and
injecting cleaning droplets on the second portion of the surface of the substrate,
wherein: the second portion of the surface is a different portion from the first portion of the surface,
the protecting liquid is sprayed from a protection liquid-spraying unit,
the cleaning droplets are sprayed from a cleaning droplet-injecting unit,
the protection liquid-spraying unit moves with respect to the cleaning droplet-injecting unit,
injecting the cleaning droplets comprises moving a head providing the cleaning droplets from a first edge of the substrate to a second edge of the substrate through a center portion of the substrate,
the spray directions of the protecting liquid from a nozzle switch from the first spray direction to the second spray direction when the head reaches the center portion of the substrate, and
the second spray direction is the opposite direction of the first spray direction.

US Pat. No. 10,395,950

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND RECORDING MEDIUM

Tokyo Electron Limited, ...

7. A substrate processing method comprising:accommodating a substrate having a pattern formed on a surface thereof and a liquid adhering to the surface, in a processing container;
raising a pressure within the processing container to a processing pressure higher than a critical pressure of the processing fluid by supplying a pressurized processing fluid to the processing container; and
performing a circulation process of supplying the pressurized processing fluid to the processing container and discharging the processing fluid from the processing container while keeping a pressure at which at least the processing fluid is maintained in a supercritical state, within the processing container,
wherein, in the raising the pressure, the pressurized processing fluid is supplied from a first fluid supply unit provided below the substrate until at least the pressure within the processing container reaches the critical pressure of the processing fluid,
in the performing the circulation process, the pressurized processing fluid is supplied from a second fluid supply unit provided at a side of the substrate, and
in the raising the pressure, the pressurized processing fluid is not supplied from the second fluid supply unit until at least the pressure within the processing container reaches the critical pressure of the processing fluid.

US Pat. No. 10,395,949

SUBSTRATE DRYING APPARATUS, STORAGE MEDIUM, AND SUBSTRATE DRYING METHOD

Ebara Corporation, Tokyo...

1. A substrate drying apparatus, comprising:a substrate rotating mechanism configured to rotate a substrate within a horizontal plane;
a rinse agent nozzle configured to eject a rinse agent to the substrate while moving away from a center of the substrate relative to the substrate rotated by the substrate rotating mechanism;
an IPA gas nozzle configured to spout an IPA gas to the substrate while moving away from the center of substrate relative to the substrate rotated by the substrate rotating mechanism with movement of the rinse agent nozzle;
a liquid area sensor mounted on an arm and a dried area sensor mounted on the arm, the sensors respectively configured to sense a film thickness of a liquid film on a surface of the substrate at two places around an interface of the rinse agent by moving away from the center of the substrate with movement of the rinse agent nozzle and the IPA gas nozzle while a rinse agent flow from the rinse agent nozzle and an IPA gas flow from the IPA gas nozzle are supplied to the surface; and
a control unit configured to control drying conditions comprising a rinse agent ejection amount, an arm swing speed, and a substrate rotation speed based on a sensing result of the liquid area sensor and the dried area sensor such that the interface of the rinse agent is spread on the surface of the substrate toward an outer circumference of the substrate by the rinse agent and the drying gas,
wherein the rinse agent nozzle and the IPA gas nozzle are arranged such that the landing area of the rinse agent is on the upstream side compared with the landing area of the IPA gas when viewed in the rotation direction of the substrate.

US Pat. No. 10,395,947

MANUFACTURING METHOD OF A RESIN MOLDED ARTICLE

DENSO CORPORATION, Kariy...

1. A manufacturing method of a resin molded article including:a thermosetting resin member made of thermosetting resin; and a thermoplastic resin member made of thermoplastic resin to seal a sealed surface as part of a surface of the thermosetting resin member, wherein an exposed surface as a remaining part of the surface of the thermosetting resin member is exposed from the thermoplastic resin member, the manufacturing method comprising:
completely hardening, by heating, the thermosetting resin material to form the thermosetting resin member into a shape of a cuboid by using a thermosetting resin material as a raw material of the thermosetting resin member;
removing a surface layer on a topmost surface in at least part of the sealed surface of the thermosetting resin member to form the at least part of the sealed surface as a newly formed surface containing a functional group;
adding, into a thermoplastic resin material as a raw material of the thermoplastic resin member, a functional group-containing additive containing a functional group that is to be chemically bound to the functional group on the newly formed surface, to prepare a material doped with the functional group-containing additive; and
plasticizing injection molding by injection molding the material doped with the functional group-containing additive onto the thermosetting resin member formed with the newly formed surface, and
sealing the sealed surface of the thermosetting resin member with the thermoplastic resin member while chemically binding the functional group on the newly formed surface to the functional group in the functional group-containing additive with which the thermoplastic resin material is doped, wherein
in the removing of the surface layer, the newly formed surface containing the functional group corresponds to a base for the surface layer and the newly formed surface is a roughened surface that is formed as a closed ring that extends around four sides of the cuboid of the thermosetting resin member.

US Pat. No. 10,395,946

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

1. A method for manufacturing an electronic package, comprising:forming a middle patterned conductive layer, wherein the middle patterned conductive layer has a first surface, a second surface opposite to the first surface, and a plurality of middle conductive pads;
forming a first redistribution circuitry on the first surface of the middle patterned conductive layer, wherein the first redistribution circuitry comprising a first patterned conductive layer, the first patterned conductive layer has a plurality of first conductive elements, each of the first conductive elements has a first conductive pad and a first conductive via that form a T-shaped section, and each of the first conductive vias connects the corresponding middle conductive pad and is tapering facing towards the corresponding middle conductive pad; and
forming a second redistribution circuitry on the second surface of the middle patterned conductive layer, wherein the second redistribution circuitry comprises a second patterned conductive layer, the second patterned conductive layer has a plurality of second conductive elements, each of the second conductive elements has a second conductive pad and a second conductive via that form an inversed T-shaped section, and each of the second conductive vias connects the corresponding middle conductive pad and is tapering facing towards the corresponding middle conductive pad.

US Pat. No. 10,395,945

BONDING DEVICE FOR CHIP ON FILM AND DISPLAY PANEL AND BONDING METHOD FOR THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A bonding device for a chip on film and a display panel, comprising:a bearing stage having a horizontal bearing surface for supporting at least one row of display panels, wherein one row of the at least one row of display panels has a row of first bonding regions;
a grasping unit disposed above the bearing stage and configured to grasp at least a partial area of the entire chip on film so that a row of second bonding regions of the entire chip on film is horizontally located above the one row of the display panels;
a driving unit configured to enable the grasping unit and the bearing stage to move with respect to each other such that the entire chip on film grasped by the grasping unit is horizontally moved with respect to the at least one row of display panels supported on the horizontal bearing surface of the bearing stage, so that the row of second bonding regions of the entire chip on film are aligned with the row of first bonding regions, respectively; and
a bonding unit configured to bond the row of second bonding regions which have been aligned with the row of first bonding regions respectively, to the row of first bonding regions.

US Pat. No. 10,395,944

PULSING RF POWER IN ETCH PROCESS TO ENHANCE TUNGSTEN GAPFILL PERFORMANCE

Lam Research Corporation,...

1. An apparatus comprising:a process chamber comprising a showerhead and a pedestal;
one or more gas inlets into the process chamber and associated flow-control hardware;
a radio frequency (RF) plasma generator configured to generate a capacitively coupled or inductively coupled plasma in the process chamber; and
a controller having at least one processor and a memory,
wherein the at least one processer and the memory are communicatively connected with one another,
the at least one processor is at least operatively connected with the flow-control hardware and RF plasma generator, and
the memory stores computer-executable instructions for:
causing introduction of a fluorine- and nitrogen-containing gas to the process chamber,
causing generation of a plasma in the process chamber, and
causing pulsing of the RF plasma generator between an ON state and an OFF state, wherein plasma power during the OFF state is 0 W and the plasma power during the ON state is between about 50 W and about 3000 W.

US Pat. No. 10,395,942

ETCHING DEVICE, SUBSTRATE PROCESSING APPARATUS, ETCHING METHOD AND SUBSTRATE PROCESSING METHOD

SCREEN Holdings Co., Ltd....

1. An etching device that performs etching processing using an organic solvent on a process film that is formed on a substrate and made of a Directed Self Assembly material, comprising:a pure water supplier that supplies only pure water to the process film;
an organic solvent supplier that, after the pure water is supplied to the process film by the pure water supplier, supplies the organic solvent to the process film with the pure water remaining on the process film; and
a rinse liquid supplier that, after the organic solvent is supplied by the organic solvent supplier, supplies the pure water used as a rinse liquid to the process film with the organic solvent remaining on the process film.

US Pat. No. 10,395,941

SADP METHOD WITH MANDREL UNDERCUT SPACER PORTION FOR MANDREL SPACE DIMENSION CONTROL

GLOBALFOUNDRIES INC., Gr...

16. A self-aligned double patterning (SADP) method, comprising:undercutting a mandrel over an underlying layer, forming an undercut space under opposing sides of the mandrel;
depositing a spacer material over the mandrel and into the undercut space under the opposing sides of the mandrel;
etching the spacer material, forming a pair of spacers adjacent the mandrel, each spacer including a vertical spacer portion on each side of the mandrel and an undercut spacer portion extending into the undercut space from the vertical spacer portion, the undercut spacer portions defining a sub-lithographic lateral dimension therebetween;
removing the mandrel; and
etching to form a sub-lithographic feature in at least the underlying layer using the spacers.

US Pat. No. 10,395,940

METHOD OF ETCHING MICROELECTRONIC MECHANICAL SYSTEM FEATURES IN A SILICON WAFER

The Board of Trustees of ...

1. A method of etching features in a silicon wafer, the method comprising:coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer;
removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer;
etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a target depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface;
coating the top surface and the one or more top surface features with a metallic coating; and
etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.

US Pat. No. 10,395,939

METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:disposing a hard mask on a substrate;
disposing an oxide layer and a neutral layer on the hard mask;
removing a portion of the oxide layer and the neutral layer to expose a portion of the hard mask;
forming a guiding pattern by selectively backfilling a polymeric material in the exposed portion of the hard mask;
forming a self-assembled block copolymer layer on the guiding pattern, the guiding pattern comprising the neutral layer and the polymeric material that is backfilled;
removing a portion of the block copolymer layer to form an etch template with the polymeric material that is remaining;
etching the neutral layer, the oxide layer, and the hard mask to transfer a pattern from the etch template into the neutral layer, the oxide layer, and the hard mask;
etching the substrate to transfer the pattern from the hard mask into the substrate and form a first fin and a second fin.

US Pat. No. 10,395,938

WAFER ELEMENT WITH AN ADJUSTED PRINT RESOLUTION ASSIST FEATURE

INTERNATIONAL BUSINESS MA...

1. A wafer element fabrication method, comprising:forming a single device element directly on an upper surface of a substrate such that the single device element comprises an upper device element surface and a sidewall extending exclusively vertically in a height dimension from the upper surface to the substrate;
forming an adjusted print resolution assist feature (APRAF) directly on the upper surface of the substrate such that the APRAF is smaller than the device element in at least the height dimension; and
depositing surrounding oxide material, which is different from materials of the APRAF, to surround an entirety of the APRAF and to lie directly on the upper surface of the substrate in abutment with an entirety of the sidewall of the single device element.

US Pat. No. 10,395,937

FIN PATTERNING FOR SEMICONDUCTOR DEVICES

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor device, comprising:providing a device having a substrate and a hard mask layer over the substrate;
forming a mandrel over the hard mask layer;
depositing a material layer on sidewalls of the mandrel;
implanting a dopant into the material layer;
performing an etching process on the hard mask layer using the mandrel and the material layer collectively as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and
forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask.

US Pat. No. 10,395,936

WAFER ELEMENT WITH AN ADJUSTED PRINT RESOLUTION ASSIST FEATURE

INTERNATIONAL BUSINESS MA...

1. A wafer element, comprising:a substrate comprising an upper substrate surface;
a single device element formed directly on the upper substrate surface and comprising an upper device element surface and a sidewall extending exclusively vertically in a height dimension from the upper device element surface to the upper substrate surface;
an adjusted print resolution assist feature (APRAF) formed directly on the upper substrate surface proximate to the single device element, the APRAF being:
smaller than the single device element in at least the height dimension as measured from an uppermost portion thereof to the upper substrate surface, and
tapered with a wide base at the upper substrate surface and a pointed tip at the uppermost portion; and
oxide disposed to surround an entirety of the APRAF and to lie on the upper device element surface and directly on the upper substrate surface in abutment with an entirety of the sidewall of the single device element.

US Pat. No. 10,395,935

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

Hitachi High-Technologies...

1. A plasma processing method using a plasma processing apparatus including a plasma processing chamber configured to process a sample using plasma, a radio frequency power supply configured to supply radio frequency power for generation of the plasma, a sample stage including an electrode configured to electrostatically chuck the sample, the sample stage configured to mount the sample thereon, and a DC power supply configured to apply DC voltage to the electrode, the plasma processing method comprising:shifting the DC voltage previously set, in a negative direction by a predetermined value during discharge of the plasma; and
shifting the DC voltage having been shifted in the negative direction by the predetermined value, in a positive direction by the predetermined value after the discharge of the plasma.

US Pat. No. 10,395,934

CONTROL DEVICE, SUBSTRATE PROCESSING SYSTEM, SUBSTRATE PROCESSING METHOD, AND PROGRAM

Tokyo Electron Limited, ...

1. A control device that controls an operation of a substrate processing apparatus, the control device comprising:a recipe memory configured to store film formation conditions including a first film formation condition to form a first film and a second film formation condition to form a second film;
a model memory configured to store process models including a first process model that represents an effect of the first film formation condition on a property of the first film and a second process model that represents an effect of the second film formation condition on a property of the second film; and
a controller configured to:
control the substrate processing apparatus to form a laminated film of the first film and the second film by sequentially using the first film formation condition and the second film formation condition stored in the recipe memory;
measure a value of a property of the laminated film;
determine whether or not a measured value of the property of the laminated film satisfies a target value of the property of the laminated film;
update the second film formation condition based on the measured value of the property of the laminated film, and the second process model stored in the model memory when it is determined that the measured value of the property of the laminated film does not satisfy the target value of the property of the laminated film;
determine whether or not to update the first film formation condition based on an expected value of the property of the laminated film, which is expected when forming the laminated film by the first film formation condition and the updated second film formation condition; and
when it is determined to update the first film formation condition, update the first film formation condition so that the expected value of the property of the laminated film coincides with the target value of the property of the laminated film based on the measured value of the property of the laminated film including the first film and the second film which are formed by the first film formation condition and the second film formation condition stored in the recipe memory, respectively, and the first process model stored in the model memory.

US Pat. No. 10,395,933

METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER

SHIN-ETSU HANDOTAI CO., L...

1. A method for manufacturing a semiconductor wafer comprising:slicing off a plurality of wafers from an ingot;
chamfering outer peripheral portions of the plurality of sliced wafers; and
holding the plurality of chamfered wafers by using a carrier which holds the outer peripheral portions of the wafers and performing double-side polishing to polish both surfaces of each wafer whose outer peripheral portion is held by the carrier,
wherein the method comprises performing warp direction adjustment to uniform directions of warps of the plurality of wafers in one direction after the slicing and before the chamfering,
the chamfering and the double-side polishing are performed in a state where the directions of the warps of the plurality of wafers are uniformed in one direction after the warp direction adjustment, and
in the warp direction adjustment, the directions of the warps of the plurality of wafers are determined, and some of the plurality of wafers are reversed based on a result of the determination, thus the directions of the warps of the plurality of wafers are uniformed in one direction.

US Pat. No. 10,395,932

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first electrode including a first conductive region;
a second electrode including a second conductive region, the second conductive region being separated from the first conductive region in a first direction;
a third electrode including a third conductive region, a third position of the third conductive region in the first direction being between a first position of the first conductive region in the first direction and a second position of the second conductive region in the first direction;
a first semiconductor region of Alx1Ga1-x1N (0?x1<1) separated from the first conductive region, the second conductive region, and the third conductive region in a second direction crossing the first direction;
a second semiconductor region of Alx2Ga1-x2N (0 a third semiconductor region of Alx3Ga1-x3N (0 a fourth semiconductor region of Alx4Ga1-x4N (0 a fifth semiconductor region of Alx5Ga1-x5N (0?x5

US Pat. No. 10,395,931

LDMOS TRANSISTOR, ESD DEVICE, AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A laterally diffused metal-oxide-semiconductor (LDMOS) transistor, comprising:a base substrate;
a first well area formed in the base substrate, wherein the first well area is doped with a first well ion;
a second well area formed in the base substrate, wherein
the second well area is formed on a side of the first well area, abutting directly against the first well area and doped with a second well ion, and
the second well area includes a first region adjacent to the first well area and doped with the second well ion, the first region abutting directly against the first well area;
a first ion doping region formed in the first well area and the first region, wherein the first ion doping region in the first well area is doped with first ions, the first ion doping region in the first region is doped with first ions to neutralize the second well ion in the first region, and a type of the first ions is the same as a type of the first well ion and opposite to a type of the second well ion; and
a gate structure formed on part of the first well area and part of the first region.

US Pat. No. 10,395,929

CHIP HANDLING AND ELECTRONIC COMPONENT INTEGRATION

International Business Ma...

1. A method for integrating electronic elements into an electronic package assembly, comprising:obtaining a semiconductor structure including a device wafer comprising an array of singulated electronic elements, a handle wafer, and a release layer, the device wafer being bonded to the handle wafer, and the release layer being positioned between the device wafer and the handle wafer;
aligning a carrier with the device wafer;
directing electromagnetic radiation through the handle wafer, thereby causing ablation of discrete, selected portions of the release layer beneath a targeted plurality of the singulated electronic elements;
removing portions of the release layer between the singulated electronic elements prior to causing ablation of the discrete, selected portions of the release layer beneath the targeted plurality of the singulated electronic elements;
attaching the targeted plurality of singulated electronic elements to the carrier;
aligning the targeted plurality of singulated electronic elements attached to the carrier with a plurality of targeted bonding sites of an electronic package assembly;
integrating the targeted plurality of singulated electronic elements into the electronic package assembly at the targeted bonding sites, and
detaching the targeted plurality of singulated electronic elements from the carrier.

US Pat. No. 10,395,926

MULTIPLE PATTERNING WITH MANDREL CUTS FORMED USING A BLOCK MASK

GLOBALFOUNDRIES Inc., Gr...

1. A method comprising:forming a first mandrel line over a hardmask layer;
forming a first block mask over a first portion of the first mandrel line that is linearly arranged between respective second portions of the first mandrel line; and
after forming the first block mask, removing the second portions of the first mandrel line with a first etching process to cut the first mandrel line and expose respective first portions of the hardmask layer,
wherein a second portion of the first mandrel line is covered by the first block mask during the first etching process to define a mandrel cut in the first mandrel line.

US Pat. No. 10,395,925

PATTERNING MATERIAL FILM STACK COMPRISING HARD MASK LAYER HAVING HIGH METAL CONTENT INTERFACE TO RESIST LAYER

International Business Ma...

1. A lithographic patterning method, comprising:forming a multi-layer patterning material film stack on a semiconductor substrate, wherein forming the patterning material film stack comprises forming a hard mask layer and forming a resist layer over the hard mask layer, and wherein an interface portion of the hard mask layer proximate the resist layer has a higher metal content than other portions of the hard mask layer;
exposing the multi-layer patterning material film stack to patterning radiation to form a desired pattern in the resist layer;
developing the pattern formed in the resist layer;
etching the hard mask layer in accordance with the developed pattern; and
removing remaining portions of the resist layer.

US Pat. No. 10,395,924

SEMICONDUCTOR STACK

SUMITOMO ELECTRIC INDUSTR...

1. A semiconductor stack, comprising:a substrate made of silicon carbide; and
an epi layer disposed on the substrate and made of silicon carbide,
wherein an epi principal surface of the epi layer, the epi principal surface being a principal surface opposite to the substrate, is a carbon surface having an off angle of 4° or smaller relative to a c-plane,
wherein a plurality of first recessed portions having an outer shape of a rectangular shape in a planar view is formed in the epi principal surface, and
wherein density of a second recessed portion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions, is lower than or equal to 10 cm?2 in the epi principal surface.

US Pat. No. 10,395,923

LOCALIZED ELECTRON BEAM INDUCED DEPOSITION OF SILICON CARBIDE

Lawrence Livermore Nation...

1. A method of producing a silicon-carbide film, comprising the steps of:admitting a gaseous silicon-carbide precursor into a vacuum chamber containing a substrate with a substrate surface wherein said gaseous silicon-carbide precursor absorbs to said substrate surface, and
directing an electron beam or ion beam to said substrate surface, wherein said electron beam or ion beam dissociates said gaseous silicon-carbide precursor creating non-volatile fragments that bind to said substrate surface forming a silicon-carbide film, and wherein said step of directing an electron beam or ion beam to said substrate surface comprises using a scanning electron microscope for directing an electron beam or ion beam to said substrate surface.

US Pat. No. 10,395,922

ATOMIC LAYER DEPOSITION SEALING INTEGRATION FOR NANOSHEET COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH REPLACEMENT SPACER

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device comprising:etching exposed portions of a stack of at least two semiconductor materials with an etch process, wherein the etch process includes a stage that removes one of the at least two semiconductor materials at a faster rate than a second of the at least two semiconductor materials to provide a divot region undercutting an overlying spacer, wherein the etch process removes one of the at least two semiconductor materials so that the remaining semiconductor material provides suspended source and drain semiconductor material layers; and
forming a plurality of atomic layer deposited (ALD) conformal dielectric monolayers that fills the divot region, wherein a seam is centrally positioned in the divot resulting from two portions of the conformal dielectric contacting each other in the ALD conformal dielectric layer that fills the divot region.

US Pat. No. 10,395,921

METHOD OF FORMING THIN FILM

ASM IP Holding B.V., Alm...

1. A thin film forming method for forming a thin film of a material using anatomic layer deposition (ALD) process, comprising:providing a substrate on which the thin film of the material is to be formed;
providing a target thickness T of the thin film;
determining, at a processor device, n processing conditions that respectively have predetermined film growth rates (G1, G2. . . , and Gn) different from each other, where n is 2 or a greater integer, and wherein each of the film growth rates represents a thickness of the thin film formed by growth of the material per ALD cycle in each of the processing conditions;
determining, at the processor device, a minimum value among the film growth rates G1, G2, . . . , and Gn;
repeatedly calculating, at the processor device, values of (a1×G1+a2×G2+ . . . +an×Gn) using different sets of the numbers of the ALD) cycles (a1, a2, . . . an) until a value of |T?(a1×G1+a2×G2+ . . . +an×Gn)| is less than the minimum value, wherein each of a1, a2, . . . an is an integer of 1 or greater and at least two of a1, a2, . . . an are different from each other; and
performing, after the repeatedly calculating, deposition on the substrate using the determined numbers of ALD cycles (a1, a2, . . . an) and the n processing conditions so as to form the thin film of the material.

US Pat. No. 10,395,920

ALKYL-ALKOXYSILACYCLIC COMPOUNDS

VERSUM MATERIALS US, LLC,...

1. A composition for a vapor deposition of a dielectric film comprising a silacyclic compound having the following Formula I:wherein R1 is independently selected from hydrogen, a linear or branched C1 to C10 alkyl group, a linear or branched C2 to C10 alkenyl group, a linear or branched C2 to C10 alkynyl group, a C3 to C10 cyclic alkyl group, a C3 to C10 hetero-cyclic alkyl group, a C5 to C10 aryl group, and a C3 to C10 hetero-aryl group; R2 is selected from hydrogen, a linear or branched C1 to C10 alkyl group, a linear or branched C2 to C10 alkenyl group, a linear or branched C2 to C10 alkynyl group, a C3 to C10 cyclic alkyl group, a C3 to C10 hetero-cyclic alkyl group, a C5 to C10 aryl group, and a C3 to C10 hetero-aryl group; and R3 is selected from a C3 to C10 alkyl di-radical which forms a four-membered, five-membered, or six-membered cyclic ring with the Si atom, wherein the compound is substantially free of at least one impurity selected from the group consisting of halides and water.

US Pat. No. 10,395,919

METHOD AND APPARATUS FOR FILLING A GAP

ASM IP Holding B.V., Alm...

1. A method for filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising:in a cycle, providing an anisotropic plasma comprising a noble gas to bombard a bottom area of a surface of the one or more gaps with ions thereby creating adsorption sites comprising dangling bonds for a first reactant at the bottom area;
in the cycle, after the step of providing an anisotropic plasma, introducing the first reactant to the substrate; and,
in the cycle, allowing the first reactant to react with the created adsorption sites at the bottom area of the surface relative to side walls of the surface to deposit material on the bottom surface relative to the side walls, and
repeating the cycle to fill the one or more gaps from the bottom area upwards,
wherein during introducing the first reactant, a sputtering plasma is created by providing a sputtering gas to relocate material in a top area of the surface relative to the bottom area of the surface.

US Pat. No. 10,395,918

METHOD AND SYSTEM FOR CONTROLLING PLASMA IN SEMICONDUCTOR FABRICATION

TAIWAN SEMICONDUCTOR MANU...

1. A method for controlling a plasma in semiconductor fabrication, comprising:generating the plasma by a remote plasma module;
providing a compound mixing member connected to the remote plasma module by a line, wherein the compound mixing member includes a main body having a first outer surface and a second outer surface and a first end surface and a second end surface opposing the first end surface, the first end surface and the second end surface connecting the first outer surface and the second outer surface;
directing the plasma from the remote plasma module through the line extending into the compound mixing member through a first inlet port disposed on the first end surface;
directing a first processing gas into the compound mixing member through a second inlet port on the second outer surface and directing a second processing gas into the compound mixing member through a third inlet port on the first outer surface, wherein the first processing gas is different than the second processing gas;
mixing the plasma with the first processing gas at a first point and the second processing gas at a second point in a flow path within a body of the compound mixing member, wherein a distance interposes the first point and the second point, and wherein the second point is further from the first inlet port than the first point by the distance;
prior to the mixing, acquiring a parameter data of the plasma while in the compound mixing member wherein the acquiring is performed through a window in the second outer surface;
after acquiring the parameter data, passing the mixed plasma, first processing gas, and second processing gas out of the compound mixing member through an outlet port in the second end surface;
comparing the parameter data to a preset parameter specification; and
terminating operation of the remote plasma module if the parameter data falls outside the preset parameter specification and wherein if the parameter data falls inside the preset parameter specification.

US Pat. No. 10,395,917

SI PRECURSORS FOR DEPOSITION OF SIN AT LOW TEMPERATURES

ASM IP Holding B.V., Alm...

1. A method of depositing a silicon nitride thin film on a substrate in a reaction space by plasma enhanced atomic layer deposition (PEALD), the method comprising:carrying out a plurality of deposition cycles, at least one of the deposition cycles comprising:
(a) introducing a vapor-phase silicon reactant comprising silicon, iodine and hydrogen into the reaction space;
(b) flowing a purge gas through the reaction space to remove excess silicon reactant and reaction byproducts from the reaction space with the aid of a purge gas;
(c) contacting the substrate with a nitrogen plasma; and
(d) flowing a purge gas through the reaction space to remove excess nitrogen plasma and reaction byproducts from the reaction space;
wherein the reaction space comprises a susceptor and a showerhead plate with a gap of 0.5 to 5 cm between the susceptor and the showerhead plate;
wherein the nitrogen plasma is produced by applying RF power with a density of from 0.02 W/cm2 to 2.0 W/cm2 between the susceptor and the showerhead plate to generate a plasma in a nitrogen precursor;
wherein the silicon reactant is consumed at a rate of from 0.1 mg per deposition cycle to about 50 mg per deposition cycle; and
wherein the substrate is a 300 mm wafer.

US Pat. No. 10,395,916

IN-SITU PRE-CLEAN FOR SELECTIVITY IMPROVEMENT FOR SELECTIVE DEPOSITION

APPLIED MATERIALS, INC., ...

1. A method of selectively depositing a film, the method comprising:providing a substrate having a first surface and a second surface different from the first surface;
exposing the substrate to a pre-clean plasma comprising one or more of argon or hydrogen to form a pre-cleaned substrate; and
directly depositing a metal film selectively on the first surface of the pre-cleaned substrate relative to the second surface, the metal film deposited by chemical vapor deposition.

US Pat. No. 10,395,914

EFFICIENT ION TRAPPING

MICROMASS UK LIMITED, Wi...

1. An ion trapping system comprising:a plurality of electrodes;
one or more voltage supplies connected to the electrodes, wherein the electrodes and the one or more voltage supplies are adapted and configured to provide an ion trap;
an ion entrance for receiving ions into the ion trap along an ion entrance axis, in use;
an ion ejecting system for ejecting ions from the ion trap along an ion exit axis in use, wherein the electrodes and voltage supplies are configured such that the maximum dimension over which the ion trap extends orthogonal to the entrance axis is greater than the maximum dimension over which the ion trap extends parallel to the entrance axis; and
further comprising one or more of the following:
an ion deflector arranged upstream of the ion trap, wherein the ion deflector is configured to deflect at least some of the ions travelling towards the ion trap such that ions entering the ion trap enter an ion trapping region at different locations; and/or
an ion deflector arranged upstream of, or at the entrance to, the ion trap, wherein the ion deflector is configured to deflect at least some of the ions travelling towards or into the ion trap such that ions enter the ion trap with different speeds orthogonal to the entrance axis so that the ions spread out within the ion trap in a direction orthogonal to the entrance axis.

US Pat. No. 10,395,913

MASS SPECTROMETRY PROBES AND SYSTEMS FOR IONIZING A SAMPLE TRANSPORT

Purdue Research Foundatio...

1. A system comprising:a mass spectrometry probe comprising a paper substrate in which a portion of the paper substrate is coated with an electrically conductive material that is not a sample or a solvent, in a manner that a plurality of nanoscale features protrude from the paper substrate, the plurality of nanoscale features configured to act as a plurality of electrodes and upon application of a voltage of 3 volts or less, providing a field strength high enough to cause field emission of microscale solution droplets at the plurality of nanoscale features at a voltage that does not cause fragmentation of the analyte; and
a voltage source coupled to the substrate, wherein the voltage source is configured to generate a voltage of 3 volts or less.

US Pat. No. 10,395,909

MASS SPECTROMETER

SHIMADZU CORPORATION, Ky...

1. A mass spectrometer for performing an MSn analysis, where n is any integer equal to or greater than two, by selecting an ion through a window having a predetermined mass-to-charge-ratio width from among ions originating from a sample, dissociating the selected ion as a precursor ion, and performing a mass spectrometry for product ions generated by the dissociation, the mass spectrometer comprising:a) a measurement executer for:
changing a central mass-to-charge ratio of the window;
performing an MSn analysis for a same sample for each of the changed central mass-to-charge ratio;
obtaining a plurality of MSn spectra corresponding to a plurality of windows of the changed central mass-to-charge ratio, respectively; and
extracting a signal intensity of product-ion peaks appearing at a same mass-to-charge ratio on the plurality of MSn spectra;
b) a product ion assignment determination processor for;
comparing a change in the central mass-to-charge ratio of the plurality of windows and a change in the signal intensity of the product-ion peaks appearing at the same mass-to-charge ratio; and
determining, based on a result of the comparison, an assignment of each product ion by ascertaining which of a plurality of ion species that are possibly present within the plurality of windows having respectively different values of central mass-to-charge ratio is an origin of that product ion; and
c) a spectrum reconstructor for reconstructing the MSn spectrum for one ion species based on a result of the assignment of the product ions by the product ion assignment determination processor.

US Pat. No. 10,395,908

METHOD FOR CONVERTING MASS SPECTRAL LIBRARIES INTO ACCURATE MASS SPECTRAL LIBRARIES

DH Technologies Developme...

8. A computer program product, comprising a non-transitory and tangible computer-readable storage medium whose contents include a program with instructions being executed on a processor so as to perform a method for converting product ion mass spectra to product ion mass spectra with higher mass accuracy, comprising:providing a system, wherein the system comprises one or more distinct software modules, and wherein the distinct software modules comprise an input module and an analysis module;
receiving at least one product ion mass spectrum produced by a tandem mass spectrometer using the input module;
receiving a chemical structure of a compound that corresponds to the at least one product ion mass spectrum using the input module;
assigning one or more elemental compositions to at least one peak in the at least one product ion spectrum based on the chemical structure using the analysis module by calculating one or more elemental compositions from the elements of the chemical structure that have masses within a mass tolerance of the mass of the at least one peak and assigning the one or more elemental compositions to the at least one peak;
scoring the one or more assigned elemental compositions using the analysis module;
simulating one or more fragmentations of the chemical structure to produce a plurality of substructures of the chemical structure using the analysis module;
comparing the plurality of substructures to the one or more assigned elemental compositions to find one or more matching substructures using the analysis module;
assigning the one or more matching substructures to their corresponding assigned elemental compositions using the analysis module;
scoring the one or more matching substructures using the analysis module;
combining scores of the one or more assigned elemental compositions and their corresponding one or more matching substructures to produce an overall score for each of the one or more assigned elemental compositions using the analysis module;
selecting at least one elemental composition of the one or more assigned elemental compositions that has the highest overall score using the analysis module;
and
converting the mass of the at least one peak to the mass of the selected at least one elemental composition using the analysis module, producing a product ion mass spectrum with higher mass accuracy.

US Pat. No. 10,395,907

MEMS DEVICE FOR GENERATING AN ION BEAM

1. A generator of an ion beam, comprising:an ionisation chamber provided with an inlet of a fluid to be ionised;
a source of ionising particles configured to impact the fluid in an impact zone of the ionisation chamber so as to generate ions; and
an extractor of ions generated in a direction of an outlet zone of the generator,
the extractor comprising at least two electrodes, a first electrode referred to as input electrode laterally bordering the impact zone, and at least one second electrode referred to as intermediate electrode located in the impact zone, the at least two electrodes being configured to generate a voltage gradient in the impact zone, with the voltage gradient being configured to direct the generated ions to the outlet zone of the generator.

US Pat. No. 10,395,906

MEASUREMENT ERROR CORRECTION METHOD BASED ON TEMPERATURE-DEPENDENT DISPLACEMENT IN MEASUREMENT DEVICE AND MASS SPECTROMETER USING THE SAME METHOD

SHIMADZU CORPORATION, Ky...

1. A measurement error correction method based on a temperature-dependent displacement in a measurement device, the measurement error correction method to be used in a measurement device configured to perform a predetermined measurement and acquire measurement data, for correcting an error or discrepancy in measurement data due to a thermal expansion of a specific component member included in the measurement device and having a length contributing to the measurement data, the measurement error correction method comprising:placing a reference member in a same temperature atmosphere as the component member, the reference member made of a material whose coefficient of thermal expansion is different from a coefficient of thermal expansion of the component member; and
measuring a difference in length between the component member and the reference member, with the two members individually demonstrating a thermal expansion in the same temperature atmosphere, and correcting measurement data obtained by a measurement, based on the difference in length.

US Pat. No. 10,395,904

METHOD OF REAL TIME IN-SITU CHAMBER CONDITION MONITORING USING SENSORS AND RF COMMUNICATION

Applied Materials, Inc., ...

1. A method of processing a workpiece in a chamber of a reactor having a process controller outside of the chamber and governing process parameters in the chamber, comprising:activating placement of a workpiece into the chamber so that the workpiece rests on a support;
monitoring the workpiece using plural sensors which are secured to the chamber and fixed in locations inside the chamber, each sensor having a wireless transceiver;
establishing respective independent wireless communication channels between a wireless communication hub inside the chamber and respective wireless transceivers of the plural sensors;
transmitting measurements by each respective sensor from the wireless transceiver of the respective sensor to the wireless communication hub; and
transmitting the measurements from the wireless communication hub inside the chamber to the process controller outside the chamber.

US Pat. No. 10,395,903

SELF-SUSTAINED NON-AMBIPOLAR DIRECT CURRENT (DC) PLASMA AT LOW POWER

Tokyo Electron Limited, ...

13. A method for processing a substrate comprising:exciting an electron beam source plasma in an electron beam source chamber and generating an electron beam from the electron beam source plasma;
injecting the electron beam from the electron beam source plasma and propelling the electron beam into an ion beam source chamber through a dielectric injector that couples the electron beam source chamber with the ion beam source chamber;
exciting an electron beam excited plasma in the ion beam source chamber with the injected electron beam and generating an ion beam from the electron beam excited plasma;
injecting the ion beam from the electron beam excited plasma and propelling the ion beam through the dielectric injector and into the electron beam source chamber;
applying power to the electron beam source chamber and the ion beam source chamber for simultaneously generating and propelling the respective electron beam and ion beam in opposite directions and into a respective ion beam source chamber and electron beam source chamber for generating an energy field sufficient for maintaining the electron beam;
providing a substrate in one or both of the electron beam source chamber and the ion beam source chamber and treating the substrate with one or both of the electron beam source plasma and electron beam excited plasma;
decreasing the power to the electron beam source chamber when the energy field is sufficient for maintaining the electron beam.

US Pat. No. 10,395,902

CHAMBER WITH VERTICAL SUPPORT STEM FOR SYMMETRIC CONDUCTANCE AND RF DELIVERY

Lam Research Corporation,...

1. A system for providing symmetric delivery of radio frequency (RF) power to a lower electrode within a plasma chamber, comprising:the lower electrode having a bottom side; and
an RF rod having a bowl-shaped portion and a column-shaped portion, wherein the bowl-shaped portion of the RF rod has a lower bowl side that is coupled to the column-shaped portion of the RF rod, wherein the bowl-shaped portion of the RF rod has an upper bowl side that is coupled to the bottom side of the lower electrode, wherein the upper bowl side of the RF rod has a rim that is disposed symmetrically proximate to a periphery of the bottom side of the lower electrode to symmetrically deliver the RF power to the lower electrode.

US Pat. No. 10,395,901

PLASMA IGNITION AND SUSTAINING APPARATUS

Lam Research Corporation,...

1. An apparatus for generating a plasma in a vessel, comprising,a first comb structure configured to partially encircle a circumference of the vessel used to generate the plasma, the first comb structure having a first end and a second end, such that a first separation distance is defined between the first end and the second end, the first comb structure defining a first plurality of fingers oriented perpendicular to the circumference of the vessel, and wherein the first comb structure is configured to be connected to a first end of a coil that is configured to receive an radio frequency (RF) driver signal for generating the plasma in the vessel; and
a second comb structure configured to partially encircle the circumference of the vessel, the second comb structure having a first end and a second end, such that a second separation distance is defined between the first end and the second end of the second comb structure, the second comb structure defining a second plurality of fingers oriented perpendicular to the circumference of the vessel, and wherein the second comb structure is configured to be connected to a second end of the coil;
wherein the first plurality of fingers of the first comb structure are further oriented to face the second plurality of fingers of the second comb structure;
wherein a gap is defined between ends of the first and second plurality of fingers.

US Pat. No. 10,395,900

PLASMA PROCESSING APPARATUS

Samsung Electronics Co., ...

1. A plasma processing apparatus comprising:a chamber;
a window plate disposed in an upper portion of the chamber and having a fastening hole; and
an injector configured to be disposed in the fastening hole, the injector including a first body having a plurality of distribution nozzles for distributing a process gas, and a second body having an accommodating groove to which the first body is configured to be fastened and having a plurality of injection nozzles for injecting the process gas to an interior of the chamber when the injector is disposed in the fastening hole.

US Pat. No. 10,395,899

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS

Toshiba Memory Corporatio...

1. A method of manufacturing a semiconductor device, comprising:forming a first film on a substrate;
housing the substrate provided with the first film in a chamber;
introducing a first gas into the chamber;
generating plasma discharge of the first gas in the chamber or applying radiation to the first gas in the chamber; and
introducing a second gas containing a metal component into the chamber to cause the metal component to infiltrate into the first film after the generation of the plasma discharge or the application of the radiation is started.

US Pat. No. 10,395,898

SUBSTRATE TREATING APPARATUS, SUBSTRATE TREATING METHOD, AND PLASMA GENERATING UNIT

PSK INC., Gyeonggi-Do (K...

8. A substrate treating method comprising:initiating ignition of plasma by connecting a first antenna wound on an upper portion of a chamber to a power source;
determining a state of impedance in the first antenna with a controller based on current flowing through the first antenna; and
when after the ignition of the plasma is initiated, the controller determines that a deviation value of a current flowing through the first antenna with respect to a normal state current is a preset value or less, connecting a second antenna to the first antenna in parallel.

US Pat. No. 10,395,896

METHOD AND APPARATUS FOR ION ENERGY DISTRIBUTION MANIPULATION FOR PLASMA PROCESSING CHAMBERS THAT ALLOWS ION ENERGY BOOSTING THROUGH AMPLITUDE MODULATION

APPLIED MATERIALS, INC., ...

1. An apparatus for plasma processing, comprising:a controller;
a process chamber with a symmetrical plasma source configured to process a wafer with a single monolithic top electrode, the single monolithic top electrode positioned centrally within the process chamber opposite a bottom electrode;
one or more very high frequency (VHF) sources, coupled to the single monolithic top electrode via symmetrical conductors connected to a top edge of a hollow cylinder which has a bottom edge connected to the single monolithic top electrode, to generate plasma density; and
two or more frequency generators that generate low frequencies relative to the one or more VHF sources, coupled to a bottom electrode of the process chamber, the two or more frequency generators configured to dissipate energy in a plasma sheath above the bottom electrode,
wherein the controller controls the one or more VHF sources to generate a VHF signal and the two or more frequency generators to generate two or more frequency signals, and
wherein the single monolithic top electrode is DC grounded to the process chamber such that a symmetrical low impedance current return path for the two or more frequency signals is provided by the symmetrical conductors.

US Pat. No. 10,395,895

FEEDBACK CONTROL BY RF WAVEFORM TAILORING FOR ION ENERGY DISTRIBUTION

MKS Instruments, Inc., A...

12. A method for controlling a radio frequency (RF) generator comprising:detecting spectral emissions from a load, the spectral emissions including at least one a harmonic and intermodulation distortion (IMD); and
varying a parameter of an RF output signal of a RF power source in accordance with one of the harmonic or the IMD detected in the spectral emissions, wherein the parameter is one of phase, frequency, or amplitude.

US Pat. No. 10,395,894

SYSTEMS AND METHODS FOR ACHIEVING PEAK ION ENERGY ENHANCEMENT WITH A LOW ANGULAR SPREAD

Lam Research Corporation,...

1. A method for operating a plasma chamber to increase ion energy and decrease angular spread of ions directed towards a surface of a substrate during an etch operation, comprising:receiving a pulsed signal to drive operation of the plasma chamber, wherein the pulsed signal has two states including a first state and a second state;
operating a primary radio frequency (RF) generator at a primary frequency level during the first state and maintaining the primary RF generator in an off state during the second state, wherein operating the primary RF generator is performed to generate a primary RF signal that pulses between the primary frequency level and the off state, wherein operating the primary RF generator during the first state produces an increased charge for a plasma sheath formed over the substrate, wherein the increased charge adds to a thickness of the plasma sheath;
operating a secondary RF generator at a secondary frequency level during the second state and maintaining the secondary RF generator in the off state during the first state, wherein operating the secondary RF generator is performed to generate a secondary RF signal that pulses between the off state and the secondary frequency level, wherein the secondary RF signal is in the off state while the primary RF signal has the primary frequency level and the secondary RF signal has the secondary frequency level while the primary RF signal is in the off state, wherein operating the secondary RF generator during the second state uses at least part of the increased charge of the plasma sheath produced during the first state as additive power to enhance the ion energy generated during the second state, the additive power reduces the angular spread of the ions when directed towards the surface of the substrate, wherein the primary and secondary RF generators are coupled via an impedance matching circuit to a top electrode associated with the plasma chamber; and
continuing to operate the primary and secondary RF generators in the first and second states according to the pulsed signal to enhance the etch operation over multiple cycles of the first and second states.

US Pat. No. 10,395,893

DUAL-FEED TUNABLE PLASMA SOURCE

APPLIED MATERIALS, INC., ...

1. A plasma source assembly comprising:a housing having a gas inlet and a front face defining a flow path, the gas inlet allowing a flow of gas to move along the flow path to pass through the housing and out an opening in the front face;
an RF hot electrode within the housing, the RF hot electrode having an inner peripheral end and an outer peripheral end;
only one outer RF feed connected to the RF hot electrode near the outer peripheral end; and
only one inner RF feed connected to the RF hot electrode near the inner peripheral end, the inner RF feed having a variable capacitor between the inner RF feed and electrical ground,
wherein the outer RF feed provides power to the RF hot electrode and the inner RF feed provides a return path for the power, wherein the housing and RF hot electrode are wedge-shaped with a narrower width at the inner peripheral edge than at the outer peripheral edge.

US Pat. No. 10,395,888

OPTICAL-CAVITY BASED PONDEROMOTIVE PHASE PLATE FOR TRANSMISSION ELECTRON MICROSCOPY

THE REGENTS OF THE UNIVER...

1. A system for electron beam imaging or electron beam spectroscopy comprising:a transmission electron microscope (TEM) having a back focal plane;
a plurality of mirrors forming an optical cavity, a focal spot of the optical cavity positioned at the back focal plane of the TEM, the optical cavity positioned to allow an electron beam provided by the TEM to pass through the focal spot of the optical cavity, and the optical cavity being operable to admit a laser beam;
a laser coupled to the optical cavity and operable to provide a laser beam of a specified wavelength to enter the optical cavity, the laser beam being reflected from the plurality of mirrors to provide a standing wave optical phase plate focused at the back focal plane of the TEM to cause a modulation of the electron beam; and
an image plane of the TEM positioned to receive the electron beam modulated by the standing wave optical phase plate.

US Pat. No. 10,395,886

APPARATUS OF PLURAL CHARGED-PARTICLE BEAMS

ASML Netherlands B.V., V...

1. A multi-beam apparatus for observing a surface of a sample, comprising:an electron source;
a condenser lens below said electron source;
a source-conversion unit below said condenser lens;
an objective lens below said source-conversion unit;
a deflection scanning unit below said source-conversion unit;
a sample stage below said objective lens;
a beam separator below said source-conversion unit;
a secondary projection imaging system; and
an electron detection device with a plurality of detection elements,
wherein said electron source, said condenser lens and said objective lens are aligned with a primary optical axis of said apparatus, and said sample stage sustains said sample so that said surface faces to said objective lens,
wherein said source-conversion unit comprises a beamlet-forming means with a plurality of beam-limit openings and an image-forming means with a plurality of electron optics elements,
wherein said electron source generates a primary-electron beam along said primary optical axis, and said primary-electron beam is focused by said condenser lens to become a substantially parallel beam and then incident into said source-conversion unit,
wherein a plurality of beamlets of said primary-electron beam exits from said source-conversion unit, said plurality of beamlets respectively passes through said plurality of beam-limit openings and is deflected by said plurality of electron optics elements towards said primary optical axis, and deflection angles of said plurality of beamlets are different;
wherein said plurality of beamlets is focused by said objective lens onto said surface and forms a plurality of probe spots thereon, said deflection scanning unit deflects said plurality of beamlets to scan said plurality of probe spots respectively over a plurality of scanned regions within an observed area on said surface, and currents of said plurality of probe spots are limited by said plurality of beam-limit openings,
wherein a plurality of secondary electron beams is generated by said plurality of probe spots respectively from said plurality of scanned regions and directed into said secondary projection imaging system by said beam separator, said secondary projection imaging system focuses and keeps said plurality of secondary electron beams to be detected by said plurality of detection elements respectively, and each detection element therefore provides an image signal of one corresponding scanned region,
wherein said deflection angles are individually set to reduce aberrations of said plurality of probe spots respectively.

US Pat. No. 10,395,885

CHARGED PARTICLE DEVICE, CHARGED PARTICLE IRRADIATION METHOD, AND ANALYSIS DEVICE

HITACHI, LTD., Tokyo (JP...

1. A charged particle device, comprising:a charged particle source which generates charged particles;
a sample table on which a sample is placed; and
a transport optical system which is disposed between the charged particle source and the sample table and is configured to transport the charged particles as charged particle flux toward the sample table, the transport optical system comprising
a magnetic field generating section which generates a magnetic field having a perpendicular component to a course of the charged particle flux;
an electric field generating section which generates an electric field having a perpendicular component to the course of the charged particle flux; and
a shielding section which shields at least a part of the charged particle flux passed through the magnetic field generating section and the electric field generating section; and
a separation optical system comprising the magnetic field generating section and the electric field generating section,
wherein the perpendicular component of the magnetic field has a magnetic field gradient,
wherein the perpendicular component of the electric field provides an electrostatic force in a direction opposite to a Lorentz force received by the charged particle flux,
wherein the charged particle flux emitted out from the separation optical system have deviated distribution of the charged particles having upward spins and the charged particles having downward spins, and
wherein the shielding section increases a spin polarization degree of the charged particle flux by the shielding.

US Pat. No. 10,395,883

APERTURE SIZE MODULATION TO ENHANCE EBEAM PATTERNING RESOLUTION

Intel Corporation, Santa...

1. A blanker aperture array (BAA) for an e-beam tool, the BAA comprising:a first column of openings along a first direction and having a pitch, each opening of the first column of openings having a dimension in the first direction; and
a second column of openings along the first direction and staggered from the first column of openings, the second column of openings having the pitch, and each opening of the second column of openings having the dimension in the first direction, wherein a scan direction of the BAA is along a second direction orthogonal to the first direction, and wherein the openings of the first column of openings overlap with the openings of the second column of openings by at least 5% but less than 50% of the dimension in the first direction when scanned along the second direction.

US Pat. No. 10,395,881

SYSTEMS AND METHODS FOR PROVIDING AN ION BEAM

HIL APPLIED MEDICAL, LTD....

1. A system for generating a proton beam, the system comprising:an interaction chamber configured to support an ion-generating target;
an electromagnetic radiation source configured to provide an electromagnetic radiation beam;
one or more optics components configured to direct the electromagnetic radiation beam at the ion-generating target to thereby cause a resultant proton beam;
a detector configured to measure at least one laser-target interaction property; and
at least one processor configured to:
receive a feedback signal based on the at least one laser-target interaction property measured by the detector, wherein the feedback signal is indicative of a relationship between the proton beam and the electromagnetic radiation beam; and
based on the received feedback signal, alter the proton beam by adjusting an item among at least one of the following: (A) the electromagnetic radiation source, (B) the one or more optics components, (C) at least one of a relative position and orientation of the electromagnetic radiation beam to the ion-generating target;
wherein altering the proton beam includes altering a temporal profile of the electromagnetic radiation beam based on the relationship between the proton beam and the electromagnetic radiation beam as indicated in the received feedback signal and by altering a chirp of the electromagnetic radiation beam.

US Pat. No. 10,395,878

MODULAR FUSE HOLDER AND ARRANGEMENT AND CONNECTION THEREOF

Eaton Intelligent Power L...

1. A fuse holder comprising:a holder base including:
a plurality of protrusions each having a mounting hole formed therein to provide for mounting of the holder base to an external component;
one or more mating protrusions and one or more mating slots formed on each of opposing side surfaces; and
an electrically conductive buss bar insert that is over molded in the holder base;
an input stud coupled to or formed on the holder base;
an output stud coupled to or formed on the holder base; and
a cover configured to attach to the holder base to at least partially enclose first and second fuses positioned on the input and output studs;
an input power buss bar positioned on the input stud such that the input stud extends through an opening in the input power buss bar, with the input power buss bar positioned on the first stud so as to be adjacent to the holder base and electrically coupled to the first fuse;
wherein the one or more mating protrusions and the one or more mating slots formed on each of the opposing side surfaces of the holder base comprise dovetailed protrusions and slots of a matching profile capable of receiving such a dovetailed protrusion, so as to enable a side-by-side stacking and interlocking of fuse holders with such mating protrusions and mating slots;
wherein the first and second fuses comprise first and second MRBF fuses, with the first and second MRBF fuses being positioned on the input and output studs via an opening in each of the first and second MRBF fuses; and
wherein the input power buss bar contacts the electrically conductive buss bar insert so as to be electrically coupled thereto, the electrically conductive buss bar insert transferring power from the input power buss bar to the second MRBF fuse.

US Pat. No. 10,395,877

PROTECTIVE DEVICE

Littelfuse, Inc., Chicag...

1. A protection device comprising:(i) a protection element which includes a first thermal fuse and a resistor, and in which the resistor generates heat as a result of current passing through the resistor when there are abnormalities, and the first thermal fuse is activated due to this heat and interrupts the current;
(ii) a PTC element and a second thermal fuse which are electrically connected in parallel to the first thermal fuse and which are electrically connected in series to each other; and
(iii) a current fuse which is electrically connected in series to the first thermal fuse.

US Pat. No. 10,395,875

CIRCUIT BREAKER PANEL INCLUDING REMOTELY OPERATED CIRCUIT BREAKER

EATON INTELLIGENT POWER L...

1. A circuit breaker panel comprising:a control unit structured to generate a control signal; and
a number of circuit breakers,
wherein at least one of the circuit breakers includes first and second sets of separable contacts,
wherein the at least one of the circuit breakers includes a first operating mechanism structured to open the first set of separable contacts in response to a fault condition and a second operating mechanism structured to open or close the second set of separable contacts in response to the control signal,
wherein the at least one of the circuit breakers includes a thermal-magnetic trip device including an elongated bimetal and a magnetic yoke and being structured to actuate the first operating mechanism in response to the fault condition,
wherein the at least one of the circuit breakers includes a remote operation circuit structured to receive the control signal and to control the second operating mechanism to open or close the second set of separable contacts based on said control signal,
wherein the at least one of the circuit breakers is structured to electrically connect between a line and load and includes a power supply structured to convert power from the line and to use the converted power to open or close the second set of separable contacts,
wherein the at least one of the circuit breakers includes a processor structured to determine whether one or more conditions are met in response to the at least one of the circuit breakers receiving the control signal and to control the second set of separable contacts to open or close if the one or more of the conditions are met, and
wherein the one or more conditions are based on at least one of a current between the line and the load, a voltage between the line and a neutral, and a type of the at least one of the circuit breakers.

US Pat. No. 10,395,874

AUXILIARY SWITCH

1. An auxiliary switch comprising:a housing including a first housing part and a second housing part separate from and releasably connected to the first housing part;
a printed circuit board fixedly mounted within the housing and having an electrical pad and an electrical contact connected to the electrical pad;
a terminal conductor electrically connected to the printed circuit board; and
an actuator mechanism mounted within the housing and having an electrical contactor engaged to the terminal conductor, wherein the actuator mechanism is configured to move within the housing and at least partially displace the electrical contact while maintaining engagement between the contactor and the terminal conductor.

US Pat. No. 10,395,873

CIRCUIT BREAKER, FASTENING ASSEMBLY THEREFOR, AND ASSOCIATED ASSEMBLY METHOD

EATON INTELLIGENT POWER L...

1. A fastening assembly for a circuit breaker, said circuit breaker comprising a base and a bimetal, said fastening assembly comprising:a heater element coupled to said bimetal and said base; and
a plurality of fastening members comprising a nut and a coupling member coupled to said nut, said nut being disposed between said heater element and said bimetal, said coupling member extending through said heater element and into said nut in order to minimize movement of said heater element with respect to said base,
wherein said nut comprises a stabilizing portion and a post portion extending outwardly from said stabilizing portion and away from said bimetal.

US Pat. No. 10,395,872

MOVABLE CONTACT ASSEMBLY FOR CIRCUIT BREAKER

LSIS CO., LTD., Anyang-s...

1. A movable contact assembly for a circuit breaker, comprising: a fixed contact; a connector formed to protrude from one side of a terminal connected to a load or a power source; a plurality of movable contacts pivotably installed at the connector through a connector pin and configured to be contactable to or separable from the fixed contact; a side holder pivotably installed at the connector through the connector pin; a catch pivotably installed at the connector, supported on the side holder, and configured to restrict a rebound phenomenon of the plurality of movable contacts when current limiting interruption occurs; and a pressurizing protrusion formed at a lower portion of each of the plurality of movable contacts and configured to push the catch when the current limiting interruption occurs; wherein a latch is pivotably installed at an intermediate portion of the side holder, a latch support to which the latch is contactable is formed to protrude from one side of the lower portion of each of the plurality of movable contacts, and the pressurizing protrusion is formed at a lower portion of the latch support.

US Pat. No. 10,395,871

ELECTRICAL SWITCHING APPARATUS AND METHOD OF MANUFACTURING SAME

EATON INTELLIGENT POWER L...

1. An electrical switching apparatus comprising:a housing member;
a printed circuit board assembly comprising a board having a first side and a second side facing away from the first side; and
a barrier member coupled to each of said housing member and the first side of said board, said barrier member substantially encapsulating the first side of said board,
wherein said printed circuit board assembly further comprises a hot terminal and a neutral terminal each extending from the first side of said board toward said housing member; wherein said housing member comprises a base portion and a primary wall portion extending from said base portion; and wherein said primary wall portion is disposed between said hot terminal and said neutral terminal.

US Pat. No. 10,395,870

RELAY WITH FIRST AND SECOND ELECTROMAGNETS FOR PLACING AND KEEPING A CONTACT IN A CLOSED STATE

EPCOS AG, Munich (DE)

1. A relay comprising:a first terminal;
a second terminal;
a contact which in a closed state brings about an electrical connection between the first and second terminals and which in an opened state electrically disconnects the first and second terminals;
an armature which is mechanically connected to the contact;
a first electromagnet which is configured to move the armature from a first position to a second position, thereby placing the contact in the closed state if the first electromagnet is switched on; and
a second electromagnet which is an air-gap-free holding magnet and which is configured to keep the armature in the second position and to keep the contact in the closed state if the contact is in the closed state and the second electromagnet is switched on,
wherein the armature abuts the second electromagnet in the second position without an air gap in-between, does not abut the second electromagnet in the first position, and does not abut the first electromagnet in the second position, and
wherein the first and second electromagnet are arranged displaced from each other along the direction of the movement from the first position to the second position.

US Pat. No. 10,395,869

RELAY CIRCUIT AND METHOD FOR PERFORMING SELF-TEST OF RELAY CIRCUIT

SCHNEIDER ELECTRIC INDUST...

1. A relay circuit, comprising:four relays, each relay comprising:
a first forcibly guided contact, and
a second forcibly guided contact;
wherein the four relays are arranged in a first pair and a second pair of two in series connected via the first forcibly guided contacts, and
wherein the first relay pair and second relay pair are arranged in parallel between a power supply connection and a load connection for switching a power supply to a load through the first forcibly guided contacts.

US Pat. No. 10,395,867

SELF REGULATING MECHANISM FOR STORAGE WATER HEATER

1. A self regulating mechanism for a storage water heater, comprising:a water tank to store water therein;
an electrical contactor disposed on top of the water tank, and connected with a input voltage line;
a liquid level switch directly and electrically connected to a first side of the electrical contactor in the water tank to energize the electrical contactor in response to the water in the water tank meeting a predefined threshold, such that the electrical contactor makes the circuit, and automatically interrupted the flow of electricity to the heating elements when the water in the tank fell below a preset threshold wherein the predefined threshold and preset threshold are levels of water in the water tank;
at least one heating element including an uppermost heating element and a lowermost heating element; wherein the uppermost heating element connected to a second side of the electrical contactor in the water tank, and configured to heat the water in response to receiving electricity from the electrical contactor, such that the at least one heating element is suspended in the water with an electrical wire;
at least two thermostats, and each of the at least two thermostats connected between one of the at least one heating element and the electrical contactor;
a first indicator light positioned on an exterior of a housing of the electrical contactor to provide a visual indication of whether power is going to the contactor;
a second indicator light positioned on the exterior of the housing of the electrical contactor to provide a separate visual indication of whether the tank is full of water and whether the tank is receiving electricity;
wherein the liquid level switch is operative to detect the level of water in the water tank and operate for switching of the electrical contactor based on whether the level of water in the water tank surpasses a predefined threshold defined by the uppermost heating element in the water tank;
wherein the electrical contactor is configured to selectively make and break a circuit to control the flow of electricity from the input voltage line to the thermostats and the at least one heating element, and control electricity to flow to the at least one heating element when the liquid level switch indicates that the water tank is full.

US Pat. No. 10,395,865

REMOTE-CONTROLLED SWITCH COVER ASSEMBLY

Ecolink Intelligent Techn...

1. A remote-controlled switch cover assembly for converting an existing rocker switch into a remote-controlled switch, comprising:a tilt plate pivotally mounted over the standard rocker switch, comprising a first elongated structure coupled to a second elongated structure joined at an angle to one another, the first elongated structure having a first underside proximate to a first existing rocker switch portion, and the second elongated structure having a second underside proximate to a second existing rocker switch portion;
a wiper coupled to a gear train;
the gear train coupled to a motor; and
the motor for driving the gear train in a first direction to move the wiper in a first wiper direction against the first underside of the tilt plate;
wherein the standard rocker switch is turned on when the wiper contacts the first underside, causing an end of the second elongated structure to depress the second rocker switch portion of the standard rocker switch.

US Pat. No. 10,395,864

SWITCHING DEVICE COMPRISING A RESETTING DEVICE

SCHNEIDER ELECTRIC INDUST...

1. A switching device comprising:a shell,
a switching device including an input connection terminal and an output connection terminal and adapted to switch between a closed position allowing the passage of the current between the input connection terminal and the output connection terminal and an open position preventing the passage of the current between the input connection terminal and the output connection terminal, and
a device for controlling the switching device, the control device including a grasping device movable between a first position and a second position by an operator to command the movement of the switching device between the open position and the closed position, the switching device being in the closed position when the grasping device is in the first position and being in the open position when the grasping device is in the second position,
the shell further delimiting a plurality of spaces each able to accommodate a trip including a tripping device mobile between an armed position and a tripped position, the tripping device being configured to command the movement of the switching device from its closed position to its open position when the tripping device goes from its armed position to its tripped position,
wherein the control device further includes a single resetting device configured to move each tripping device from its tripped position to its armed position when the operator moves the grasping device from the first position to the second position.

US Pat. No. 10,395,863

MAGNETIC ROTARY DIAL

DENSO International Ameri...

1. A rotary dial assembly comprising:a holder;
a dial portion rotatably coupled to the holder;
a plurality of dial magnets fixed to the dial portion;
a holder magnet on a side of the holder opposite to the dial portion; and
a pair of stoppers on a side of the holder opposite to the dial portion, the holder magnet is slidably movable between the pair of stoppers;
wherein the holder magnet is configured to attract or repel the plurality of dial magnets as the dial portion is rotated to resist rotation of the dial portion; and
wherein rotation of the dial portion and the plurality of dial magnets thereof forces the holder magnet against one of the pair of stoppers.

US Pat. No. 10,395,860

STRAIN GAUGE PROPORTIONAL PUSH BUTTON

Eaton Intelligent Power L...

1. A transmitter device comprising:a printed circuit board including one or more electrical components thereon; and
a push button comprising:
a flexible membrane;
a dome switch positioned beneath the flexible membrane and attached to the printed circuit board, the dome switch being proximate to the flexible membrane such that depression of the flexible membrane causes the dome switch to snap down and thereby form a closed circuit in the dome switch; and
a force sensor formed on or applied to the printed circuit board and positioned adjacent the dome switch, the force sensor generating an electrical output responsive to an amount of deflection of the printed circuit board caused by pressure exerted thereon by depression of the flexible membrane and the dome switch.

US Pat. No. 10,395,859

SWITCH CASE AND SWITCH

PANASONIC INTELLECTUAL PR...

1. A switch case comprising:a dome shape first metal plate; and
a resin case which holds the dome shape first metal plate; and
a second metal plate that includes a contact portion facing the dome shape first metal plate, and an intermediate portion which is electrically connected to the contact portion and is embedded in the resin case,
wherein the intermediate portion of the second metal plate includes:
a first surface,
a second surface opposing to the first surface,
a first side surface embedded in the resin case and disposed between the first surface and the second surface, and
three or more recesses formed on the second surface, aligned with each other, and disposed at different respective distances from the first side surface,
wherein the intermediate portion further includes a second side surface embedded in the resin case and disposed between the first surface and the second surface, and
wherein a line passing through the three or more recesses intersects the second side surface.

US Pat. No. 10,395,855

SWITCH

MITSUBISHI ELECTRIC CORPO...

1. A switch comprising:a first contact placed to be able to reciprocate in a first direction along an operating shaft and in a second direction opposite to the first direction;
a second contact placed on a side of the first direction with respect to the first contact to be able to reciprocate in the first direction and the second direction along the operating shaft;
a housing box to include inside a housing space housing one end of the second contact on the side of the first direction, to form an opening through which the second contact can pass, and to allow another end of the second contact opposite to the one end to be exposed to the outside of the housing space through the opening;
a surrounding portion erected in the second direction from the opening of the housing box and surrounding a side surface of the second contact;
a slide contact placed between the second contact and the surrounding portion and in contact with the second contact and the surrounding portion;
a partition to be formed integrally with a part of the second contact housed in the housing space and to partition the housing space into a first space on the side of the first direction and a second space on a side of the second direction; and
an energizing portion to energize the second contact in the first direction, wherein
the first contact, the second contact, the housing box, the surrounding portion, and the slide contact are each formed of a conductor,
the partition is formed of an insulator,
the first contact includes a first abutting portion to be able to come into contact with the side surface of the second contact, a second abutting portion formed on the side of the first direction with respect to the first abutting portion to be able to come into contact with an outer surface of the surrounding portion, and an arc generator placed on the side of the first direction with respect to the first abutting portion to generate an arc between the second contact and the arc generator,
a facing portion that faces the one end of the second contact is formed on a part of an inner wall surface forming the first space of the housing space, and
an insulating guide made of an insulator is placed in a part of the side surface of the second contact, the part coming into contact with the slide contact in a state in which the second contact is disposed on the side of the first direction by energizing force of the energizing portion.

US Pat. No. 10,395,854

ELECTRICAL SWITCHING APPARATUS, AND CROSSBAR ASSEMBLY AND SPRING CAP THEREFOR

EATON INTELLIGENT POWER L...

1. A spring cap for an electrical switching apparatus, said electrical switching apparatus comprising a housing, a stationary contact, a movable contact disposed on a moving arm, and a crossbar assembly, said crossbar assembly comprising a crossbar, a first contact spring, a second contact spring, and a spring clip, said moving arm being coupled to said crossbar, said spring cap comprising:a first segment structured to be disposed between said spring clip and said first contact spring;
a second segment structured to be disposed between said spring clip and said second contact spring; and
a connecting portion connecting the first segment to the second segment,
wherein said spring clip is disposed between said moving arm and said contact springs, and
wherein said spring cap is structured to support said spring clip and evenly distribute bias forces of said first contact spring and said second contact spring,
wherein said spring clip has a predetermined geometry; wherein the first segment and the second segment together form a contact surface having a predetermined profile; and wherein said predetermined profile is structured to cooperate with said predetermined geometry of said spring clip,
wherein said spring clip includes a plurality of bends; wherein said predetermined profile comprises a plurality of angled surfaces; and wherein each of said angled surfaces is structured to engage said spring clip between a corresponding pair of said bends, and
wherein said plurality of angled surfaces includes a first ramped portion disposed at a first angle and a second ramped portion disposed at a second angle different from the first angle.

US Pat. No. 10,395,853

ELECTRODE AND PROCESS FOR PREPARING THE ELECTRODE AND DEVICES THEREOF

1. A process for preparation of an electrode, wherein the process step comprises:a) immersing a substrate in brewed green tea for a period of time in the range of 1-24 hours to obtain a modified substrate;
b) immersing the modified substrate as obtained from step (a) in an ammonical AgNO3 solution for a period of time in the range of 10 minutes-8 hours to obtain silver nanoparticle coated substrate;
c) keeping the silver nanoparticle coated substrate as obtained from step (b) in a metal plating solution of the pH ranging between 7-10 for a period of time in the range of 8-24 hours to obtain a metal coated substrate; and
d) polymerizing a monomer on the metal coated substrate as obtained from step (c) by soaking in electrically conducting solution for a period of time in the range of 5-30 minutes to obtain an electrode.

US Pat. No. 10,395,851

METHOD FOR PREPARING AQUEOUS MNO2 INK AND CAPACITIVE ENERGY STORAGE DEVICES COMPRISING MNO2

The Hong Kong Polytechnic...

1. A symmetric supercapacitor device comprising MnO2 coated electrodes and a solid state ionic liquid as electrolyte,wherein the MnO2 is an aqueous MnO2 obtained by:
providing highly crystalline carbon particles (HCCPs) with average diameters less than 800 nm;
mixing KMnO4 solution with the HCCPs at 30-60° C. for at least 8 hours; and
increasing the temperature of the resultant suspension to 60-90° C. for 30-60 minutes, followed by cooling and filtration.

US Pat. No. 10,395,850

QUANTUM DIPOLE BATTERY

1. An electric energy storage device comprising:a first conductor layer in a multilayer structure, both surfaces of which comprising first ionic or dipole material layer adjacent to the entire conductor surface thereof and being insulated electrically;
a second conductor layer in the multilayer structure, both surfaces of which comprising a second ionic or dipole material layer adjacent to the entire conductor surface thereof and being insulated electrically, wherein a bilayer hetero-structure is comprised of the first and second conductor layers and the ionic material layer sandwiched therebetween them, wherein a thickness of the conductor layers and the interval between them are nanometer scale to form a quantum dipole system of excitons and ions, so that interaction between excitonic dipoles and ionic dipoles occur in the bilayer structure, wherein the multilayer structure is comprised of the millions of ionic or dipole material layers and conductor layers of nanometer thickness, both conductor surfaces of which being coated with ionic or dipole materials across entire surface thereof and being insulated electrically, wherein the multilayer is consisted of the millions of the bilayers;
a plastic sheet less than a millimeter thickness is inserted between the two electrodes in order to block direct electric current between the two electrodes;
a quantum dot existing on the surface of the nano-thickness conductor layer is effectively formed when the surface is stretched by press, so that an electronic charge can be easily localized in the dot and the polaron interaction is more effective, wherein thickness of the conductor layers and the interval between the conductor layers are nanometer scale to form a quantum dipole system of excitons and ions, so that interaction between excitonic dipoles and ionic dipoles occur in the bilayer structure;
a positive electrode attached to only the first conductor layer of the multilayer structure; and
a negative electrode attached to only the last conductor layer of the multilayer structure,
wherein every conductor layer in the multilayer structure is disconnected, insulated and isolated from an electric current, and each conductor layer is not a current collector, but an excitonic dipole collector,
wherein neither electronic nor ionic current is allowed in the multilayer structure except for the electrodes which are attached to a copper (conductor) sheet, because the current in the multilayer structure destroys the dipoles,
wherein the first conductor layer is stacked on top of the second conductor layer with a nanometer-scale interval and the ionic or dipole material layer is sandwiched therebetween so as to form the bilayer structure,
wherein the first and second conductor layers form the bilayers configured to store electrical energy in the bilayer in a form of binding energy,
wherein the electrical energy is stored in the bilayer by applying a DC voltage in the direction perpendicular to the layer plane sheet to the positive and negative electrodes,
wherein the stored electrical energy is discharged and output to the electrodes by using an external AC field in a predetermined frequency range as a guiding wave with trigger power,
wherein a conductor layer is adopted because low excitation energy of a valence electron is required for jumping to conduction band, and the nanometer thickness of a conductor layer is adopted because the reciprocal of the length of the layer period in the vertical direction shall be large for a polaron formation at the interface of a conductor layer and ionic layer,
wherein the length of the layer period in the multilayer is in the range of nanometer scale to have a quantum dipole interaction in the bilayer,
wherein the length of the layer period in the multilayer structure is in the range of nanometer scale for an electrical energy storage device, so that the spatial period of the layers in the vertical direction is directly related to a polaron formation in the bilayers, and the thickness of layers as well,
wherein a linear chain of dipoles is introduced and formed in the vertical direction to the layers, and the optical vibration is governed to be tuned by the acoustical vibration and the frequencies of the vibrations as well,
wherein the layer thickness and interval between the layers are in the range of nanometer scale for formation of quantum dipole system and exciton,
wherein the layer thickness and interval in multilayer structure are in the range of nanometer scale in order to have a polaron interaction effective, and a polaron formation at the interface between a conductor layer and ionic layer is important in a storing an electrical energy in the bilayer, because the excitonic and ionic dipole structure has been transformed into the excitonic bipolaron which leads to the formation of the stable anti-ferroelectric structure in the bilayer,
wherein when an external field is applied, an polarization of ions and an excitation of valence electrons to conduction band create an collective dipoles in the multilayer system through a propagation of a dipole field (pseudo spin wave) from the electrodes to the empty states,
wherein the interaction energy between an excitonic dipole and an ionic dipole depends upon the directions and positions of the dipoles in the bilayer, which is a quasi one dimensional interaction in the vertical direction to the layers,
wherein in a nanometer scale, a charge polarization in quantum hetero-structure is a quantum dipole,
wherein the states of electronic and ionic dipoles are described in the eigenstates of two-level system, which represents a transition,
wherein the interaction terms of excitonic dipole and ionic dipole describe a propagation of pseudo spin waves across the layers in the direction vertical to the layer sheet,
wherein the pseudo spin waves propagate crossing the layers by an applied power, and as the pseudo spin waves propagate in the vertical direction, the dipoles spread all over the multilayer structure as the power continues to be provided by an external field,
wherein a mechanism for a charging process is induced by a polaron interaction, and by a polaron interaction and Coulomb force, the dipoles keep transforming into the anti-ferroelectric nanostructures in charge,
wherein a polaron interaction is so strong that the excitons in the conductor layer have been broken into the electrons and the holes to form the positive polarons and the negative polarons in the bilayer,
wherein the positive polarons on one conductor layer and the negative polarons on the other conductor are combined together to form the excitonic bipolarons in the bilayer, and
wherein the mechanism for a storing energy in the multilayer structure is a transformation process of from the dipole system into an anti-ferroelectric nanostructure created by applied power in the bilayers,
wherein the ionic or dipole material layers comprise an ionic or dipole materials selected from the group consisting of MgSO4, LiPF6, LiClO4, LiN(CF3SO2)2, LiBF4, LiCF3SO3, LiSbF6, Li4Ti5O12, ionic polymers, and ionic minerals or any kind of ionic mineral materials and dipole materials, wherein the ionic or dipole material is MgSO4.

US Pat. No. 10,395,849

ELECTRODE PLATE USING GERMANIUM FILM, MANUFACTURING METHOD THEREOF, AND ENERGY STORAGE DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing an electrode plate, comprising:forming a germanium film on a metal substrate, wherein the germanium film consists of germanium;
carrying out a topology treatment on the germanium film by using a functionalization element, to obtain the germanium film having a topological semiconductor characteristic;
wherein the functionalization element comprises at least one selected from the group consisting of fluorine, chlorine, bromine, or iodine;
carrying out the topology treatment on the germanium film using the functionalization element to obtain the germanium film having the topological semiconductor characteristic comprises:
carrying out a halogenation treatment on the germanium film by using fluorine, chlorine, bromine, or iodine, to obtain a germanium halide film, and
wherein the germanium film having the topological semiconductor characteristic is integrally formed as a whole in a single film.

US Pat. No. 10,395,847

PHOTOELECTRIC CONVERSION ELEMENT

FUJIKURA LTD., Tokyo (JP...

1. A photoelectric conversion element, comprising:a first substrate;
a conductive layer provided on one surface of the first substrate, the conductive layer including a first conductive layer which includes at least one first conductive portion, and a second conductive layer which is provided on the outside of the first conductive layer, and includes at least one second conductive portion;
wherein the photoelectric conversion element has at least one photoelectric conversion cell,
wherein the photoelectric conversion cell includes,
the first conductive portion,
a second substrate facing the first conductive portion, and
a ring-shaped sealing portion joining the first substrate and the second substrate,
the first conductive layer and the second conductive layer are separated from each other via a first groove,
the photoelectric conversion element includes an insulating layer,
the insulating layer is provided to overlap with the sealing portion between the sealing portion of the at least one photoelectric conversion cell and the first substrate,
an outer circumferential edge of the insulating layer is provided on the outside from the sealing portion to surround the entire sealing portion of the at least one photoelectric conversion cell, in a plan view showing the one surface of the first substrate,
a portion of the first conductive layer protrudes outward from the sealing portion,
the insulating layer covers and hides the portion of the first conductive layer, which protrudes outward from the sealing portion, the portion of the first conductive layer is located on the inside of the outer circumferential edge of the insulating layer and on the outside of the sealing portion, the first groove is partially or entirely located on an outer side of the sealing portion, the insulating layer enters the first groove located on the outer side of the sealing portion and covers a part of the second conductive layer, and
the rest of the second conductive layer is exposed from the insulating layer.

US Pat. No. 10,395,845

FLEXIBLE TI—IN—ZN—O TRANSPARENT ELECTRODE FOR DYE-SENSITIZED SOLAR CELL, AND METAL-INSERTED THREE-LAYER TRANSPARENT ELECTRODE WITH HIGH CONDUCTIVITY USING SAME AND MANUFACTURING METHOD THEREFOR

KOREA INSTITUTE OF INDUST...

1. A flexible Ti—In—Zn—O transparent electrode for a dye-sensitized solar cell, comprising:a flexible transparent substrate; and
a Ti—In—Zn—O thin-film on the flexible transparent substrate, the Ti—In—Zn—O thin-film having an amorphous structure and comprises 4 to 34 at % of Ti, 9 to 17 at % of Zn, and 56 to 79 at % of In, and O varies with the process conditions.

US Pat. No. 10,395,844

CAPACITOR COMPONENT

MURATA MANUFACTURING CO.,...

1. A capacitor component comprising:a plurality of multilayer ceramic capacitors; and
an interposer board on which the plurality of multilayer ceramic capacitors are mounted; wherein
the interposer board includes:
at least four lands that are electrically connected to respective external electrodes of the corresponding plurality of multilayer ceramic capacitors;
an input terminal; and
an output terminal;
each of the at least four lands is electrically connected to one of the input terminal and the output terminal;
the at least four lands are provided on a front surface of the interposer board;
each of the input terminal and the output terminal is provided on a back surface of the interposer board opposite to the front surface;
the input terminal extends from the back surface to a first side surface of the interposer board; and
the output terminal extends from the back surface to a second side surface opposite to the first side surface.

US Pat. No. 10,395,843

ELECTRICAL CONNECTION CONTACT FOR A CERAMIC COMPONENT, A CERAMIC COMPONENT, AND A COMPONENT ARRANGEMENT

1. A component,comprising a main body having ceramic layers and electrode layers and
comprising an electrical connection contact,
the electrical connection contact comprising a first layer comprising a first material and a second layer comprising a second material arranged thereon, wherein the first material has a high electrical conductivity and the second material has a low coefficient of thermal expansion,
wherein the electrical conductivity of the first material is at least 40 m/? mm2 and the coefficient of thermal expansion of the second material is at most 5 ppm/K, wherein a relation of the thickness of the second layer to the thickness of the first layer is 1:1 up to 5:1,
wherein the electrical connection contact is secured on the main body by a contact material, wherein the contact material is a sintering material, and
wherein the thermal coefficient of the second material is at most 2.5 ppm/K and the thermal coefficient of the connection contact as a whole is between 5 and 7 ppm/K.

US Pat. No. 10,395,842

THIN FILM CAPACITOR AND MANUFACTURING METHOD THEREOF

SAMSUNG ELECTRO-MECHANICS...

1. A thin film capacitor comprising:a capacitor body formed by alternately stacking first and second electrode layers and a dielectric layer on a substrate, and having the second electrode layer disposed in an uppermost portion thereof; and
a stress alleviation layer formed on the uppermost second electrode layer,
wherein the stress alleviation layer is formed of a material having a coefficient of thermal expansion higher than those of the substrate and the dielectric layer,
wherein the dielectric layer is composed of a material having a coefficient of thermal expansion higher than that of the substrate, and
wherein the substrate includes SiO2/Si.

US Pat. No. 10,395,840

MULTILAYER CERAMIC ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic electronic component comprising:a ceramic body including dielectric layers and first and second internal electrodes alternately laminated in a stacking direction with the dielectric layers disposed therebetween, the first and second internal electrodes respectively being exposed to first and second external surfaces of the ceramic body in a length direction perpendicular to the stacking direction;
first and second external electrodes disposed on the first and second external surfaces of the ceramic body to be electrically connected to the first and second internal electrodes, respectively, the first and second external electrodes each including first and second base electrode layers having at least a portion in contact with first and second external surfaces of the ceramic body, respectively, and first and second plating layers covering the first and second base electrode layers, respectively; and
a water repellent layer including a first portion covering external surfaces of the first and second plating layers and a second portion covering at least one surface of the ceramic body,
wherein the water repellent layer further includes a third portion covering gaps between the ceramic body and the first and second plating layers, and
wherein arcsin (Pa/Pc), which is an angle of an inclined surface of the third portion with respect to the at least one surface of the ceramic body covered by the second portion, is 30 degrees or more and 60 degrees or less, where a minimum distance from a corner edge, at which the first and second plating layers and the at least one surface of the ceramic body intersect, to the inclined surface of the third portion is denoted by “Pa”, and a minimum distance from the corner edge to an intersection portion between the inclined surface of the third portion and the second portion covering the at least one surface of the ceramic body is denoted by “Pc”.

US Pat. No. 10,395,839

MULTILAYER CERAMIC ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic electronic component comprising:a ceramic body including dielectric layers and first and second internal electrodes alternately laminated with the dielectric layers disposed therebetween, the first and second internal electrodes being exposed to first and second external surfaces of the ceramic body, respectively;
first and second external electrodes disposed on the first and second external surfaces of the ceramic body to be electrically connected to the first and second internal electrodes, respectively, the first and second external electrodes each including first and second base electrode layers having at least a portion in contact with first and second external surfaces of the ceramic body, respectively, and first and second plating layers covering the first and second base electrode layers, respectively; and
a water repellent layer including a first portion covering external surfaces of the first and second plating layers and a second portion covering at least one surface of the ceramic body,
wherein the water repellent layer further includes a third portion covering a gap between the ceramic body and the first and second plating layers, the third portion having a thickness greater than that of the second portion covering the at least one surface of the ceramic body.

US Pat. No. 10,395,838

MULTILAYER CERAMIC ELECTRONIC COMPONENT INCLUDING AN ORGANIC LAYER

MURATA MANUFACTURING CO.,...

1. A multilayer ceramic electronic component comprising:a laminated body including a plurality of dielectric layers that are laminated and a plurality of internal electrodes that are laminated, and further including a first principal surface and a second principal surface opposed to each other in a laminating direction, a first side surface and a second side surface opposed to each other in a width direction perpendicular or substantially perpendicular to the laminating direction, and a first end surface and a second end surface opposed to each other in a length direction perpendicular or substantially perpendicular to the laminating direction and the width direction;
a first external electrode connected to the plurality of internal electrodes, and disposed on the first end surface, with an end extending onto the first principal surface, the second principal surface, the first side surface, and the second side surface;
a second external electrode connected to the plurality of internal electrodes, and disposed on the second end surface, with an end extending onto the first principal surface, the second principal surface, the first side surface, and the second side surface; wherein
the first external electrode includes a first base electrode layer including a conductive metal and a glass component, a first organic layer including an organic silicon compound, covering the first base electrode layer, and a first plating layer disposed on the first organic layer;
the second external electrode includes a second base electrode layer including a conductive metal and a glass component, a second organic layer including an organic silicon compound, covering the second base electrode layer, and a second plating layer disposed on the second organic layer;
the first organic layer covers from the first base electrode layer to a surface of the laminated body, and the second organic layer covers from the second base electrode layer to a surface of the laminated body;
a leading end of the first plating layer is in contact with the first organic layer, and a leading end of the second plating layer is in contact with the second organic layer;
a relational expression of A>B is satisfied by an atomic concentration ratio B of Si to Cu in the first organic layer disposed on the first base electrode layer located on the first end surface, an atomic concentration ratio A of Si to Cu in the first organic layer disposed on the first base electrode layer located on the first principal surface and the second principal surface, and an atomic concentration ratio A of Si to Cu in the first organic layer located directly on the first principal surface and the second principal surface; and
a relational expression of A>B is satisfied by an atomic concentration ratio B of Si to Cu in the second organic layer disposed on the second base electrode layer located on the second end surface, an atomic concentration ratio A of Si to Cu in the second organic layer disposed on the second base electrode layer located on the first principal surface and the second principal surface, and an atomic concentration ratio A of Si to Cu in the second organic layer located directly on the first principal surface and the second principal surface.

US Pat. No. 10,395,837

MULTILAYER CERAMIC CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic capacitor, comprising:a body in which a plurality of dielectric layers are stacked;
first and second external electrodes disposed on one surface of the body and spaced apart from each other;
a plurality of first and second internal electrodes opposing each other, the dielectric layers being interposed therebetween;
a first conductive via directly connecting the plurality of first internal electrodes to the first external electrode;
a second conductive via directly connecting the plurality of second internal electrodes to the second external electrode;
a third conductive via connected to only a first internal electrode most adjacent the first external electrode among the plurality of first internal electrodes;
a fourth conductive via connected to only the second internal electrode most adjacent the second external electrode among the plurality of second internal electrodes; and
a shielding layer covering at least a portion of an external surface of the body.

US Pat. No. 10,395,836

MULTILAYER CERAMIC ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. A multilayer ceramic electronic component comprising:a laminated body including:
a plurality of dielectric layers and a plurality of internal electrode layers laminated in a laminating direction; and
a first side surface and a second side surface opposite to each other in the laminating direction, a first principal surface and a second principal surface opposite to each other in a height direction perpendicular or substantially perpendicular to the laminating direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular or substantially perpendicular to the laminating direction and the height direction;
a first external electrode extending in the laminating direction on a central portion of the second principal surface in the length direction, over the second principal surface to respective portions of the first side surface and second side surfaces;
a pair of second external electrodes including:
one second external electrode extending in the laminating direction on one end of the second principal surface in the length direction; and
another second external electrode extending in the laminating direction on the other end of the second principal surface in the length direction; and
a pair of insulating coating portions including:
one insulating coating portion extending in the laminating direction between the one second external electrode and the first external electrode on the second principal surface; and
another insulating coating portion extending in the laminating direction between the another second external electrode and the first external electrode on the second principal surface; wherein
the plurality of internal electrode layers include:
a plurality of first internal electrode layers connected to the first external electrode; and
a plurality of second internal electrode layers connected to each of the pair of second external electrodes;
the one second external electrode extends from the second principal surface to a portion of at least one of the first side surface and the second side surface, and to a portion of the first end surface;
the another second external electrode extends from the second principal surface to a portion of at least one of the first side surface and the second side surface, and to a portion of the second end surface;
the pair of insulating coating portions each extends from the second principal surface to a portion of the at least one of the first side surface and the second side surface;
as viewed from at least one direction in the laminating direction, an end of the pair of insulating coating portions, which is located closest to the first principal surface, is located closer to the first principal surface than an end of the first external electrode and pair of second external electrodes, which is located closest to the first principal surface; and
as viewed from at least one direction in the laminating direction, a distance in the height direction is about 20 ?m or more between an end of the pair of insulating coating portions, which is located closest to the first principal surface, and an end of the first external electrode and pair of second external electrodes, which is located closest to the first principal surface.

US Pat. No. 10,395,835

MULTILAYER CERAMIC ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. A multilayer ceramic electronic component comprising:a laminated body including:
multiple dielectric layers and multiple internal electrode layers laminated in a laminating direction; and
a first side surface and a second side surface opposite to each other in the laminating direction, a first principal surface and a second principal surface opposite to each other in a height direction perpendicular or substantially perpendicular to the laminating direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular or substantially perpendicular to the laminating direction and the height direction;
a first external electrode extending in the laminating direction on a central portion of the second principal surface in the length direction, from the second principal surface to respective portions of the first side surface and second side surfaces; and
a pair of second external electrodes including:
one second external electrode extending in the laminating direction on one end of the second principal surface in the length direction; and
the other second external electrode extending in the laminating direction on the other end of the second principal surface in the length direction; and
a pair of insulating coating portions including:
one insulating coating portion extending in the laminating direction between the one second external electrode and the first external electrode on the second principal surface; and
the other insulating coating portion extending in the laminating direction between the other second external electrode and the first external electrode on the second principal surface; wherein
the multiple internal electrode layers include:
multiple first internal electrode layers connected to the first external electrode; and
multiple second internal electrode layers connected to each of the pair of second external electrodes;
the one second external electrode extends from the second principal surface to a portion of at least one of the first side surface and the second side surface, and to a portion of the first end surface;
the other second external electrode extends from the second principal surface to a portion of at least one of the first side surface and the second side surface, and to a portion of the second end surface;
the pair of insulating coating portions each extends from the second principal surface to a portion of the at least one of the first side surface and the second side surface;
as viewed from at least one direction in the laminating direction, an end of the first external electrode and the pair of second external electrodes, which is located closest to the first principal surface, is located closer to the first principal surface than an end of the pair of insulating coating portions, which is located closest to the first principal surface; and
as viewed from at least one direction in the laminating direction, a distance in the height direction is about 20 ?m or more between an end of the pair of insulating coating portions, which is located closest to the first principal surface, and an end of the first external electrode and pair of second external electrodes, which is located closest to the first principal surface.

US Pat. No. 10,395,834

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a ceramic body including a plurality of dielectric layers stacked to be disposed perpendicularly to a mounting surface of the ceramic body, and first and second internal electrodes alternately disposed, with respective dielectric layers interposed therebetween, the first and second internal electrodes being exposed to the mounting surface of the ceramic body and the first and second internal electrodes being exposed respectively to first and second end surfaces of the ceramic body, the first and second end surfaces opposing each other;
first and second external electrodes disposed to be connected to the first and second internal electrodes respectively, at least a portion of the first external electrode being disposed on the first end surface and at least a portion of the second external electrode being disposed on the second end surface; and
an insulating layer disposed on the mounting surface of the ceramic body and covering portions of the first and second internal electrodes exposed to the mounting surface but not in contact with the first and second external electrodes, the insulating layer being formed of a material different from that of the plurality of dielectric layers,
wherein a portion of each of the first and second external electrodes contacting the insulating layer at the mounting surface has a three layer structure and each of the three layers contacts the mounting surface laterally adjacent to each other,
the first and second internal electrodes are not exposed to a surface of the ceramic body opposing the mounting surface and connecting the first and second end surfaces, and
wherein the insulating layer extends from the mounting surface of the ceramic body to portions of the end surfaces of the ceramic body in a length direction and to portions of side surfaces of the ceramic body in a width direction.

US Pat. No. 10,395,833

METHOD FOR MANUFACTURING A LAMINATED CERAMIC ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. A method for manufacturing a laminated ceramic electronic component including:a ceramic element assembly including a plurality of laminated ceramic layers and including first and second end surfaces opposed to each other, first and second side surfaces which connect the first and second end surfaces and are opposed to each other, and third and fourth side surfaces which connect the first and second end surfaces and are opposed to each other;
a plurality of inner electrodes provided within the ceramic element assembly and extended to the first and second side surfaces; and
a strip-shaped side-surface outer electrode located on the first and second side surfaces of the ceramic element assembly and connected to the inner electrodes extended to the first and second side surfaces, the method comprising:
a step of forming the side-surface outer electrode, the step including:
a first application step of applying a first conductive paste to portions of the first and second side surfaces of the ceramic element assembly into a strip shape such that the conductive paste extends from one end side to another end side of the first and second side surfaces in a lamination direction; and
a second application step of applying a second conductive paste to regions covering portions of outermost inner electrodes located at an outermost side portion among the inner electrodes, which portions are exposed in the first and second side surfaces of the ceramic element assembly, without applying the second conductive paste to a center portion of the strip shape of the first conductive paste in the lamination direction.

US Pat. No. 10,395,832

ELECTRONIC COMPONENT AND COMPONENT-EMBEDDED SUBSTRATE

FUJITSU LIMITED, Kawasak...

1. A method of manufacturing a component-embedded substrate, the method comprising:forming a through hole in a core substrate the electronic component including
a top metal plate electrode directly coupled to an upper surface of the electronic component, and
a bottom metal plate electrode directly coupled to a lower surface of the electronic component;
placing an electronic component in the through hole; and
forming a first insulating layer on an upper surface of the core substrate;
forming a first wiring layer on the first insulating layer;
forming a first via in the first insulating layer that couples the first wiring layer and the top metal plate electrode;
forming a second insulating layer on a lower surface of the core substrate;
forming a second wiring layer on the second insulating layer; and
forming a second via in the second insulating layer that couples the second wiring layer and the bottom metal plate electrode,
wherein the electronic component includes a component body into which elements are built and a metal plate electrode made of a metal plate that is joined to the component body by conductive paste so as to be electrically coupled to the elements, and the metal plate electrode exceeds in size a surface of the component body onto which the conductive paste is deposited, such that edge parts of the top metal plate electrode protrude laterally from the electronic component, and a length and a width of the top metal plate electrode as seen looking from above are at least 1.5 times more than a length and a width of the electronic component as seen looking from above.

US Pat. No. 10,395,831

ELECTRONIC COMPONENT WITH METAL TERMINALS AND ELECTRONIC COMPONENT MOUNTING CIRCUIT BOARD

TAIYO YUDEN CO., LTD., T...

1. An electronic component with metal terminals, comprising:an electronic component having a pair of external electrodes, and
a pair of metal terminals each having, integrally, a plate-like supporting part for supporting the electronic component, and a plate-like connecting part made to be connected to a circuit board, where the supporting parts of the metal terminals are joined to the external electrodes of the electronic component, respectively, in a manner that ends of the connecting parts face each other,
wherein the connecting part of each metal terminal has a planar connecting face facing away from the electronic component and configured to face a conductor pad of the circuit board, wherein at least one projecting part is provided on the connecting face and projects from the connecting face away from the electronic component in a manner forming a space between the conductor pad and the connecting face, into which space molten solder flows when the connecting face is connected to the conductor pad.

US Pat. No. 10,395,830

MULTI-LAYER CERAMIC ELECTRONIC COMPONENT

TAIYO YUDEN CO., LTD., T...

1. A multi-layer ceramic electronic component, comprising:a ceramic body including
a first main surface,
a second main surface,
a first side surface and a second side surface each connecting the first main surface to the second main surface in a first axial direction,
a first end surface and a second end surface connected to each other by each of the first main surface and the second main surface in a second axial direction orthogonal to the first axial direction, the first end surface and the second end surface each connecting the first main surface to the second main surface in the first axial direction, and each connecting the first side surface to the second side surface in a third axial direction perpendicular to both the first axial direction and the second axial direction,
a first internal electrode that is drawn to the first end surface, and
a second internal electrode that faces the first internal electrode and is drawn to the second end surface,
a length of the ceramic body measured in the third axial direction being longer than both a length of the ceramic body measured in the first axial direction and a length of the ceramic body measured in the second axial direction, and
the length of the ceramic body measured in the first axial direction being 80 ?m or less;
a first external electrode that covers the first end surface, a first portion of the first main surface and a first portion of the second main surface, and extends in the third axial direction from the first side surface to the second side surface; and
a second external electrode that covers the second end surface, a second portion of the first main surface and a second portion of the second main surface, and extends in the third axial direction from the first side surface to the second side surface.

US Pat. No. 10,395,828

CAPACITOR

KYOCERA Corporation, Kyo...

1. A capacitor comprising:a plurality of dielectric layers that are each formed from a dielectric porcelain, wherein the dielectric porcelain contains barium titanate and a rare earth element;
a plurality of internal electrode layers;
a capacitor body that includes alternating layers of the plurality of dielectric layers and the plurality of internal electrode layers; and
an external electrode that is electrically coupled to the plurality of internal electrode layers and provided on an end surface of the capacitor body, wherein the end surface of the capacitor body is orthogonal to a direction of the alternating layers; wherein
the dielectric porcelain contains the crystal particles that have a low concentration region and a high concentration that is inward from the low concentration region, wherein the low concentration region is 10 nm to 60 nm inward from a surface of the crystal particles and the low concentration region contains a concentration of the rare earth element that is lower than a concentration of the rare earth element in the high concentration region.

US Pat. No. 10,395,827

ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. An electronic component comprising:a laminated body including a first end surface and a second end surface positioned opposite to each other in a length direction, a first side surface and a second side surface positioned opposite to each other in a width direction perpendicular or substantially perpendicular to the length direction, and a first principal surface and a second principal surface positioned opposite to each other in a height direction perpendicular or substantially perpendicular to the length direction and to the width direction;
a first external electrode provided on the first end surface; and
a second external electrode provided on the second end surface; wherein
the first external electrode includes a first fired electrode layer provided on the first end surface and a first resin layer provided on the first fired electrode layer;
the second external electrode includes a second fired electrode layer provided on the second end surface and a second resin layer provided on the second fired electrode layer;
each of the first fired electrode layer and the second fired electrode layer is provided on the laminated body and includes a region including voids and glass;
an outermost surface of each of the first fired electrode layer and the second fired electrode layer is smooth or substantially smooth;
each of the first resin layer and the second resin layer includes metal particles; and
a surface layer of each of the first resin layer and the second resin layer includes a portion of the metal particles exposed in a ratio of about 72.6% or more and about 90.9% or less.

US Pat. No. 10,395,826

METHOD OF SUPPORTING A CAPACITOR, CAPACITOR ASSEMBLY AND SUBSEA ADJUSTABLE SPEED DRIVE COMPRISING THE ASSEMBLY

SIEMENS AKTIENGESELLSCHAF...

1. A method for supporting a capacitor, the method comprising:applying a pressure on a first side of the capacitor, parallel to a first electrode of the capacitor in a first direction of a normal of the first electrode;
applying a pressure on a second side of the capacitor, parallel to a second electrode of the capacitor in a second direction of a normal of the second electrode, wherein the first direction is opposite to the second direction;
applying a voltage between the first electrode of the capacitor and the second electrode of the capacitor, to charge the capacitor at a start pressure of non-conductive fluid surrounding the capacitor; and
subsequently pressurizing the non-conductive fluid surrounding the capacitor to a target pressure, the target pressure being above an atmospheric air pressure.

US Pat. No. 10,395,825

MULTILAYER CERAMIC CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic capacitor comprising:a body including a dielectric layer and first and second internal electrodes alternately disposed with the dielectric layer interposed therebetween; and
first and second external electrodes disposed on at least one surface of the body and respectively connected to the first and second internal electrodes,
wherein the first internal electrode includes a first main portion and a first lead out portion connecting the first main portion and the first external electrode,
the second internal electrode includes a second main portion and a second lead out portion connecting the second main portion and the second external electrode, and
the second main portion has a greater area than the first main portion and includes a corner portion defining an open space to compensate for a capacitance formed by an area in which the first lead out portion and the second main portion overlap each other.

US Pat. No. 10,395,824

METHOD OF MANUFACTURING WINDING-TYPE COIL COMPONENT

Murata Manufacturing Co.,...

1. A method of manufacturing a winding-type coil component which includes:a core member having a columnar winding core portion and a pair of flange portions which are formed on both ends of the winding core portion;
a pair of external electrodes formed on one flange portion and the other flange portion of the pair of flange portions; and
a winding wound on the winding core portion,
wherein the external electrodes are formed on regions of the one flange portion and the other flange portion near an object on which the winding-type coil component is to be mounted such that a height of the external electrodes is gradually increased in an inclined manner from opposedly facing surfaces of the one flange portion and the other flange portion to surfaces of the one flange portion and the other flange portion on a side opposite to the opposedly facing surfaces, wherein
the method comprises:
(a) a holding step of holding the core member by a first holding jig having a holding force for holding a plurality of the core members in a posture where an axis of the winding core portion has a predetermined angle with respect to a holding surface which is a main surface of the first holding jig on a side where the core member is held, and a region of the one flange portion where the external electrode is to be formed projects more from the holding surface of the first holding jig than the other flange portion,
(b) a first electrode applying step of, by performing the step (a), applying an electrode material for forming the external electrode to the region of the one flange portion where the external electrode is to be formed by bringing the region of the one flange portion into contact with the electrode material, the region of the one flange portion where the external electrode is to be formed and which is projecting from the holding surface;
(c) a rotating step of, after performing the step (b), bringing a rotating jig for rotating the core member into contact with the core member held by the first holding jig, and rotating the core member by moving the rotating jig relative to the first holding jig in a direction along a main surface of the first holding jig such that a region of the other flange portion where the external electrode is to be formed opposedly faces the first holding jig;
(d) a transferring step of, after performing the step (c), transferring the core member held by the first holding jig to a second holding jig which is positioned such that the second holding jig faces the first holding jig and which has a holding force for holding the core member, and
holding the core member by the second holding jig in a posture where the axis of the winding core portion has a predetermined angle with respect to a holding surface which is a main surface of the second holding jig on a side where the core member is held, and a region of the other flange portion where the external electrode is to be formed projects more from the holding surface of the second holding jig than the one flange portion, and
(e) a second electrode applying step of, by performing the step (d), applying an electrode material for forming the external electrode to the region of the other flange portion where the external electrode is to be formed by bringing the region of the other flange portion into contact with the electrode material, the region of the other flange portion where the external electrode is to be formed and which is projecting from the holding surface of the second holding jig.

US Pat. No. 10,395,822

RARE-EARTH MAGNET, METHOD OF MANUFACTURING RARE-EARTH MAGNET, AND ROTATOR

TDK CORPORATION, Tokyo (...

1. An R—Fe—B-based rare-earth magnet comprising a crystal particle group containing a rare-earth element R, the magnet comprising:a center part; and
a surface part surrounding the center part and including crystal particles of the crystal particle group, an alloy containing R, Cu, Co, Al, and Fe being present in an R-rich phase included at a grain-boundary triple junction of the crystal particles, wherein:
the rare-earth magnet contains Ni;
the total of Cu, Co, and Al contents in the R-rich phase is at least 13 at %;
the alloy containing R, Cu, Co, Al, and Fe is present only in the surface part of the rare-earth magnet and is present only in a region of the magnet whose depth is 400 ?m or less from an outer surface of the magnet;
in a direction perpendicular to the outer surface of the magnet, a thickness of the center part is greater than a thickness of the surface part;
the thickness of the surface part in the perpendicular direction is at least 100 ?m and 400 ?m or less;
a gradient of a concentration distribution based on unit weight of the rare-earth magnet of the Cu is 0.01 to 5 wt %/mm, a gradient of a concentration distribution based on unit weight of the rare-earth magnet of the Co is 0.01 to 5 wt %/mm, a gradient a concentration distribution based on unit weight of the rare-earth magnet of the Al is 0.01 to 5 wt %/mm, and a gradient of a concentration distribution based on unit weight of the rare-earth magnet of the Ni is 0.001 to 0.1 wt %/mm;
each of the gradients is in the direction perpendicular to the outer surface of the rare-earth magnet and directed from the outer surface to an inside of the magnet such that concentrations of the Cu, Co, Al, and Ni are highest at the outer surface; and
each value of the gradients is an average concentration gradient from a position where a depth from the outer surface of the rare-earth magnet is 20 ?m to a position at ¼ of a thickness of the rare-earth magnet.

US Pat. No. 10,395,821

ROTARY TYPE MAGNETIC COUPLING DEVICE

TDK CORPORATION, Tokyo (...

1. A rotary type magnetic coupling device used for a rotator, the rotary type magnetic coupling device comprising first and second coils magnetically coupled to each other,wherein each of the first and second coils is a loop-shaped having an opening surrounding a rotary axis of the rotator,
wherein each of the first and second coils includes:
first and second wiring parts extending in a peripheral direction of the rotator;
a third wiring part bent in the rotary axis direction from one end of the first wiring part or one end of the second wiring part; and
a fourth wiring part bent in the rotary axis direction from other end of the first wiring part or other end of the second wiring part, and
wherein at least one of the first and second coils is configured such that the third wiring part and the fourth wiring part match or overlap each other when viewed in a radial direction substantially orthogonal to the rotary axis.

US Pat. No. 10,395,820

COMMON MODE CHOKE COIL

TAIYO YUDEN CO., LTD., T...

1. A common mode choke coil comprising:a first coil conductor provided on a first coil forming surface in a first insulator and wound around a coil axis;
a second coil conductor provided on a second coil forming surface in the first insulator and wound around the coil axis; and
a third coil conductor provided on a third coil forming surface in the first insulator and wound around the coil axis,
wherein the common mode choke coil is divided into a first region and a second region in plan view as seen from an axial direction along the coil axis, the first region extending in a circumferential direction around the coil axis, the second region adjoining both ends of the first region in the circumferential direction and extending in the circumferential direction,
in the first region, each of the first coil conductor, the second coil conductor, and the third coil conductor extends parallel with the other coil conductors, and
in the second region, each of the first coil conductor, the second coil conductor, and the third coil conductor crosses at least one of the other coil conductors in plan view as seen from the axial direction, and crosses none of the other coil conductors as seen in a section cut along a plane including the coil axis.

US Pat. No. 10,395,818

NOISE FILTER AND NOISE REDUCTION UNIT

YAZAKI CORPORATION, Toky...

1. A noise filter comprising:a plurality of conductors each having a winding portion; and
a ring-shaped core made from a magnetic material and being inserted through the winding portions, wherein
the ring-shaped core includes a core main body having a pair of extension portions connected to each other at one end; and a link core attached to the core main body at another end to connect the pair of extension portions,
at least one of the pair of extension portions of the core main body has a straight shape,
the plurality of conductors being arranged in a row to allow the extension portion having the straight shape to be inserted through the winding portion of each of the plurality of conductors, and
the link core includes: a fitting plate portion fitted between respective end portions of the pair of extension portions of the core main body; and a positioning plate portion contacting the pair of extension portions when the fitting plate portion is fitted between the end portions of the pair of extension portions.

US Pat. No. 10,395,817

COIL COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A coil component comprising:a body part containing a magnetic material;
a coil part disposed in the body part; and
an electrode part disposed on the body part,
wherein the coil part includes:
a support member;
a coil disposed on a surface of the support member in a planar coil pattern and having a terminal exposed to at least one outer surface of the body part; and
a conductive via connected to the terminal of the coil and disposed adjacent to at least one end portion of the support member to thereby be exposed to the at least one outer surface of the body part to which the terminal is exposed,
wherein the support member is not exposed to any outer surface of the body part.

US Pat. No. 10,395,815

MAGNETIC DEVICE

Delta Electronics, Inc., ...

1. A magnetic device comprising: a housing having at least one side plate and a bottom plate, the side plate standing on the bottom plate and forming a space with the bottom plate; a bobbin at least partially located in the space, the bobbin having a cylinder; at least one coil wound around the cylinder; and a first magnetic core and a second magnetic core, each of the first and second magnetic cores comprising:a center column located in the cylinder; a side column located on an outer side of the coil being opposite to the bottom plate, such that the coil is located between the side column and the bottom plate; and a connecting portion connecting the center column and the side column, wherein the first magnetic core and the second magnetic core are arranged on two sides of the bobbin, respectively, and the side column of the first magnetic core and the side column of the second magnetic core form an outer side surface at a side away from the bobbin; a metal clip provided at the outer side surfaces for tightening the first magnetic core and the second magnetic core so that the first and second magnetic cores fit together; wherein accommodating grooves for holding the metal clip are provided in the side columns, the metal clip is arranged in the accommodating grooves of the side columns, and a fixing glue is provided between the metal clip and the accommodating grooves of the side columns; and a top cover is configured to cover the housing and arranged on the opposite side to the bottom plate, the outer side surfaces of the side columns form an assembly surface together with the metal clip, and another fixing glue is provided between the top cover and the assembly surface, the assembly surface and the top cover are glued and fixed by the another fixing glue.

US Pat. No. 10,395,814

COIL ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A coil electronic component comprising:a plurality of stacked coil layers, each of the coil layers including coil patterns including anisotropic plating layers;
conductive vias connecting the coil patterns formed on different coil layers to each other;
external electrodes electrically connected to the plurality of coil layers;
first insulating layers covering the coil patterns;
second insulating layers covering at least side surfaces of the first insulating layers; and
third insulating layers,
wherein an upper surface of the third insulating layer is in contact with a lower surface of the second insulating layer, and an upper surface of the second insulating layer is covered by the first insulating layer.

US Pat. No. 10,395,813

MAGNETIC CORE AND PROCESS FOR PRODUCING SAME

NTN CORPORATION, Osaka (...

1. A magnetic core produced by compression molding iron-based soft magnetic powder having a resin film comprising an epoxy resin formed on surfaces of particles of said iron-based soft magnetic powder and thereafter thermally hardening said epoxy resin in said resin films,wherein a radial crushing strength of said magnetic core is 90 to 150 MPa,
wherein said iron-based soft magnetic powder passes through a number 100 mesh Tyler sieve, but does not pass through a number 325-mesh Tyler sieve and
wherein said resin film before compression molding is an uncured epoxy resin film formed by dry mixing said iron-based soft magnetic powder and said epoxy resin containing a latent curing agent at a temperature not less than a softening temperature of said epoxy resin containing said latent curing agent and less than a thermal curing starting temperature of said epoxy-resin containing said latent curing agent;
said latent curing agent is dicyandiamide;
said softening temperature of said epoxy resin containing said latent curing agent is 100 to 120° C.;
said iron-based soft magnetic powder having said resin films formed on said surfaces of said particles of said iron-based soft magnetic powder is compression molded by using a die to produce a compression molded body; and
said compression molded body having said epoxy resin film formed on said surfaces of said particles of said magnetic powder is thermally hardened at a temperature not less than said thermal curing starting temperature of said epoxy resin containing said latent curing agent.

US Pat. No. 10,395,812

ADJUSTABLE INDUCTOR

The United States of Amer...

1. A high voltage standoff adjustable inductor, comprising:a conductive plate having a first side, a second side, and an aperture extending through both said first side and said second side, said aperture having a threaded portion;
a wire coil mounted on said first side of said conductive plate, wherein said wire coil has a plurality of windings; and
a non-ferromagnetic core having a first portion and a second portion, wherein each of said first portion and said second portion are configured with a plurality of grooves for threading engagement with said plurality of windings of said wire coil, said threading engagement attaching said non-ferromagnetic core to said plurality of windings of said wire coil, wherein the ratio of the diameter of said first portion and the diameter of said second portion is about a 1.5:1 ratio.

US Pat. No. 10,395,810

INDUCTOR

Shinko Electric Industrie...

1. An inductor comprising:a stacked body that includes a plurality of structural bodies that are stacked, wherein each of the plurality of structural bodies includes a wiring and an insulation layer formed on the wiring, and the wirings of the plurality of structural bodies that are adjacent in a stacking direction of the stacked body are connected in series to form a helical coil;
a first through hole that extends through the stacked body in the stacking direction; and
a plurality of first discrete insulation films that are spaced apart from each other and cover entire surfaces of the wirings of the plurality of structural bodies that are exposed from a surface of the stacked body,
wherein the stacked body includes:
a first wiring;
a first insulation layer stacked on an upper surface of the first wiring and including a second through hole partially covering the upper surface of the first wiring;
a first adhesive layer stacked on an upper surface of the first insulation layer and including a third through hole that is in communication with the second through hole;
a second wiring stacked on an upper surface of the first adhesive layer and including a fourth through hole that is in communication with the third through hole;
a second insulation layer stacked on an upper surface of the second wiring and including a fifth through hole that is in communication with the fourth through hole; and
a first through electrode, wherein the second through hole, the third through hole, the fourth through hole, and the fifth through hole are filled with the first through electrode, wherein
the first through electrode connects the first wiring and the second wiring in series, and
the fifth through hole has a larger planar shape than the fourth through hole.

US Pat. No. 10,395,808

DECOUPLING INDUCTOR ASSEMBLY, RADIO FREQUENCY RECEIVING COIL AND MAGNETIC RESONANCE IMAGING APPARATUS

Siemens Aktiengesellschaf...

1. A decoupling inductor assembly connectable to two adjacent coil units, the decoupling inductor assembly comprising:a first inductor comprising a first solenoid and a first port pair located at two ends of the first solenoid; and
a second inductor comprising a second solenoid and a second port pair located at two ends of the second solenoid,
wherein the first solenoid and the second solenoid are wound partially or completely overlapped, and
wherein the first port pair comprises at least one pair of first parallel connection interfaces, and the second port pair comprises at least one pair of second parallel connection interfaces.

US Pat. No. 10,395,806

GRAIN-ORIENTED ELECTRICAL STEEL SHEET AND METHOD OF MANUFACTURING THE SAME

JFE Steel Corporation, T...

1. A grain-oriented electrical steel sheet, linear strain having been applied thereto by irradiation with a high-energy beam, the linear strain extending in a direction that intersects a rolling direction of the steel sheet, whereinan area ratio of an irradiation mark within an irradiation region of the high-energy beam is 2% or more and 20% or less, an area ratio of a protrusion with a height of 1.5 ?m or more within a surrounding portion of the irradiation mark is 60% or less, and an area ratio of an exposed portion of steel substrate in the irradiation mark is 90% or less.

US Pat. No. 10,395,804

ISOLATING SEMICONDUCTING SINGLE-WALLED NANOTUBES OR METALLIC SINGLE-WALLED NANOTUBES AND APPROACHES THEREFOR

The Board of Trustees of ...

11. A method comprising:adding a supramolecular polymer to a single-walled carbon nanotube (SWNT) mixture, the SWNT mixture including SWNTs of a first electrical type and SWNTs of a second electrical type, wherein adding the supramolecular polymer to the SWNT mixture forms a mixture of non-dispersed SWNTs of the first electrical type and non-dispersed supramolecular polymer, and a dispersed complex including the SWNTs of the second electrical type and the supramolecular polymer;
removing the non-dispersed SWNTs of the first electrical type from the dispersed complex;
adding a bond disrupting agent to the dispersed complex, the bond disrupting agent configured to disassemble the supramolecular polymer and release the SWNTs of the second electrical type from the supramolecular polymer; and
isolating the SWNTs of the second electrical type from the disassembled supramolecular polymer and the bond disrupting agent.

US Pat. No. 10,395,802

WIRE HARNESS MANUFACTURING METHOD

YAZAKI CORPORATION, Toky...

1. A wire harness manufacturing method comprising:a conduction path inserting step of inserting one or a plurality of conduction paths from one end of a resin-made tubular exterior member to the other end thereof; and
an exterior member working step of performing post-working on one or a plurality of parts of the exterior member, after the conduction path inserting step,
wherein the exterior member working step includes forming a convex-shaped part which projects into an interior of the exterior member with projecting walls extending toward the one or plurality of conduction paths when viewed from an inner surface side of the exterior member by performing the post-working using a heated mold pressed against an outer surface side of the exterior member, and
wherein the convex-shaped part is a vibration suppressing part to reduce a play rate of the one or plurality of conduction paths in the exterior member and suppress a vibration of the one or a plurality of conduction paths.

US Pat. No. 10,395,800

METHOD OF MANUFACTURING AN ELECTRICAL CABLE USING 3-D PRINTING

RAYTHEON COMPANY, Waltha...

1. A method of manufacturing an electrical cable, the method comprising:performing ether sintering to form connecting pins on the electrical cable;
ink printing conductive wirings to connect the pins, wherein at least a portion of the ink printed conductive wirings is configured to convey data;
ink printing a shielding atop the ink printed conductive wirings; and
performing a three-dimensional (3D) printing to form a mechanical protection device that protects the ink printed conductive wirings.

US Pat. No. 10,395,799

METHODS AND SYSTEMS FOR FABRICATING HIGH QUALITY SUPERCONDUCTING TAPES

1. A method for fabricating a superconductor film, the method comprising:heating a superconductor substrate tape through ohmic heating with a first roller and a second roller;
delivering the heated superconductor substrate tape to a groove in a housing via the first roller and the second roller, wherein the groove is in fluid communication with a chamber positioned between two parallel channels, wherein the groove traverses the housing and is accessible at a first end and a second end of the housing, wherein the first roller is positioned exterior to the housing and guides the heated superconductor substrate tape to the groove at the first end of the housing, and wherein the second roller is positioned exterior to the housing and guides the heated superconductor substrate tape out of the second end of the housing via the groove; and
flowing at least one superconductor precursor in a gas phase through the chamber such that the at least one precursor thermally decomposes upon contact with the heated superconductor substrate tape thereby forming the superconductor film.

US Pat. No. 10,395,797

SELF-SUPPORTING ELECTRIC POWER CABLE AND BUOY ARRANGEMENT

1. A self-supporting electric power cable having a length defining a longitudinal direction and comprising an outer jacket portion and a core portion, whereinthe outer jacket portion extends along the longitudinal direction and encloses the core portion, wherein
the core portion includes at least one insulated conductor and at least one supporting cord, wherein
the at least one insulated conductor includes a number of individual wires, and wherein
the at least one supporting cord includes fibres, preferably selected from synthetic fibres, mineral fibres or a combination thereof,whereinthe number of individual wires, individually or arranged in bundles, are arranged in a first lay direction, wherein
the at least one insulated conductor, and the at least one supporting cord are arranged in a second lay direction, the second lay direction being opposite to the first lay direction, and wherein
the at least one supporting cord is arranged as a separate unit in a cross sectional sector of the self-supporting electric power cable.

US Pat. No. 10,395,796

FLAT CABLE AND WATERPROOF CABLE

AUTONETWORKS TECHNOLOGIES...

1. A flat cable comprising:a plurality of cores each including one insulated wire and/or a plurality of insulated wires that are twisted together, the cores being lined up in a cable width direction, which is orthogonal to a longitudinal direction of the insulated wires;
a sheath that collectively covers the plurality of cores; and
a space that is surrounded by an outer surface of one of the plurality of cores, an outer surface of another one of the plurality of cores that is adjacent to the one of the plurality of cores, and an inner surface of the sheath, wherein the sheath includes:
a pair of sheath sends respectively located along outer surfaces of cores of the plurality of cores that are disposed at opposite ends;
a coupler that couples the pair of sheath ends; and
a reinforcement that is formed integrally with the coupler, and is provided outward of a portion of the coupler that covers the space.

US Pat. No. 10,395,795

DATA TRANSMISSION CABLE

ALLTOP ELECTRONICS (SUZHO...

1. A data transmission cable, comprising:a first wire and a second wire adjacent to each other, each of the first wire and the second wire having a central conductor and a cover layer enclosing the conductor, and the conductor of the first wire has an outer diameter same as the conductor of the second wire;
wherein the ratio of the center distance between the first wire and the second wire to the outer diameter of the conductor is in the range of 1.7 to 2.35, the first wire and the second wire are served as a differential pair, and the cover layer is set to make the differential impedance between the first wire and the second wire be controlled in 78 to 107 Ohm when the ratio of the center distance between the first wire and the second wire to the outer diameter of the conductor is in the range of 1.7 to 2.35.

US Pat. No. 10,395,793

CONDUCTIVE MEMBER, TERMINAL-EQUIPPED CONDUCTIVE MEMBER, AND METHOD OF MANUFACTURING CONDUCTIVE MEMBER

SUMITOMO WIRING SYSTEMS, ...

1. A conductive member configured by a plurality of coated metal wires provided with a plurality of metal strands and with an electrically conductive sheath covering a circumference of each of the plurality of metal strands, the conductive member comprising:a welded portion, in which at least a portion in an extension direction of the plurality of coated metal wires is welded,
wherein the welded portion includes an outer layer that is formed on an outer circumference side by welding the plurality of coated metal wires together, and an inner layer,
the outer layer including an outermost circumference side having a majority of the coated metal wires welded together, and an inner side having at least a portion of the plurality of coated metal wires capable of untwining due to crimping a terminal, and
the inner layer provided at the inner side of the outer layer, the inner layer containing a plurality of the coated metal wires not welded together and capable of untwining due to crimping a terminal.

US Pat. No. 10,395,790

TRANSPARENT CONDUCTOR AND ELECTRONIC DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A transparent conductor comprising:a compound comprising a Group 5 transition metal and boron, wherein the compound has a layered structure,
the compound is represented by the following Chemical Formula 1:
MxBy  Chemical Formula 1wherein, in Chemical Formula 1,M is vanadium, niobium, tantalum, or a combination thereof,
B is boron, and
x and y are stoichiometric ratios of M and B,
the compound comprises V2B3, Nb2B3, Ta2B3, V3B4, Nb3B4, Ta3B4, VB, NbB, TaB, V5B6, Nb5B6, Ta5B6, or a combination thereof,
wherein the compound is in a form of a plurality of exfoliated nanosheets having a thickness of less than or equal to about 10 nanometers,
wherein the nanosheets contact one another and provide an electrical connection,
wherein the layered structure comprises a plurality of unit crystal layers,
wherein each unit crystal layer comprises an upper layer and a lower layer, each consisting of the Group 5 transition metal and boron disposed between the upper layer and the lower layer, and
wherein the unit crystal layers have an interlayer bonding force of less than 0.25 electron volts per Angstrom.

US Pat. No. 10,395,783

STEAM GENERATOR FOR NUCLEAR STEAM SUPPLY SYSTEM

SMR, LLC

1. A nuclear steam supply system with natural gravity-driven coolant circulation, the system comprising:a vertically-oriented reactor vessel comprising an elongated cylindrical shell forming an internal cavity configured for containing primary coolant and a nuclear reactor fuel core;
a vertically-oriented steam generating vessel comprising a top, a bottom, an elongated cylindrical shell extending between the top and bottom defining an internal cavity, a top tubesheet, and a bottom tubesheet;
a vertical riser pipe extending vertically between the top and bottom tubesheets, the riser pipe fluidly connected to the reactor vessel;
a plurality of heat transfer tubes extending vertically between the top and bottom tubesheets; and
a flange-less 90 degree primary coolant fluid coupling forming a flow conduit for exchanging primary coolant between the steam generating vessel and reactor vessel;
the fluid coupling comprising a reactor vessel outer inlet nozzle and a reactor vessel inner outlet nozzle inside the outer inlet nozzle and arranged concentrically thereto;
the inner outlet nozzle having an inlet end directly coupled to the reactor vessel, and an outlet end directly coupled to the riser pipe in the steam generating vessel;
the outer inlet nozzle external to the steam generating vessel and having an inlet end directly coupled to a bottom outlet nozzle of the steam generating vessel, and an outlet end directly coupled to the shell of the reactor vessel;
the outer inlet nozzle comprising a vertically-extending upper eccentric cone section defining the inlet end of the outer inlet nozzle which is directly coupled to the bottom outlet nozzle of the steam generating vessel, and an adjoining horizontally-extending stub pipe section defining the outlet end of the outer inlet nozzle which is directly coupled to the shell of the reactor vessel;
wherein the eccentric cone section comprises a vertically straight inner wall and a straight opposing inclined outer wall obliquely angled to the inner wall;
wherein a closed primary coolant loop is formed in which primary coolant flows from the reactor vessel through the eccentric cone into the steam generator vessel and returns from the steam generating vessel to the reactor vessel through the eccentric cone.

US Pat. No. 10,395,750

SYSTEM AND METHOD FOR POST-PACKAGE REPAIR ACROSS DRAM BANKS AND BANK GROUPS

Dell Products, LP, Round...

1. A dynamic random access memory (DRAM) device, comprising:a plurality of bank groups of first storage cells, each bank group arranged as a plurality of banks, each bank arranged as a plurality of rows, and each row including a plurality of dynamic storage cells; and
a post-package repair (PPR) storage array arranged as a plurality of entries, each entry being associated with a PPR row, each PPR row including a plurality of dynamic storage cells, wherein the DRAM device is configured to map a first row failure from a first row in a first bank group to a first entry of the PPR storage array, to store first row data associated with the first row in a first PPR row associated with the first entry, to map a second row failure from a second row in a second bank group to a second entry of the PPR storage array, and to store second row data associated with the second row in a second PPR row associated with the second entry.

US Pat. No. 10,395,738

OPERATIONS ON MEMORY CELLS

Micron Technology, Inc., ...

1. A method, comprising:applying a plurality of signal pulses across a memory cell until the memory cell reaches a desired state, wherein the memory cell is coupled to a first signal line and a second signal line, and wherein each signal pulse of the plurality of signal pulses causes the memory cell to move toward the desired state by causing the memory cell to snap back; and
turning off current to the second signal line in response to each time the memory cell snaps back.

US Pat. No. 10,395,730

NON-VOLATILE MEMORY DEVICE WITH VARIABLE READOUT REFERENCE

Sony Semiconductor Soluti...

1. A non-volatile memory device comprising:a plurality of bit lines;
a plurality of word lines;
a memory cell array having a plurality of memory cells respectively including a non-volatile storage element and a two-terminal selective element, one of the memory cells being disposed at respective ones of a plurality of crossing sections of the plurality of bit lines and the plurality of word lines;
a reference voltage generator circuit configured to generate a readout reference voltage serving as a reference for discrimination of data values stored on the memory cells;
a readout circuit configured to read the data values stored on the memory cells by detecting values of readout voltages from the memory cells relative to the readout reference voltage in a state where a predetermined current-limited readout current is applied to respective two-terminal selective elements via the corresponding bit lines; and
an address compensation circuit configured to change the readout reference voltage in accordance with a placement position of a memory cell to be read of the memory cells in the readout circuit.

US Pat. No. 10,395,728

DEMARCATION VOLTAGE DETERMINATION VIA WRITE AND READ TEMPERATURE STAMPS

INTEL CORPORATION, Santa...

1. An apparatus for use with a bitcell array of non-volatile storage elements and a temperature sensor, comprising:a memory controller configured to control memory read and memory write operations directed to the bitcell array of non-volatile storage elements, wherein the temperature sensor is configured to provide temperature values indicative of temperatures of memory read and write operations, and wherein the memory controller includes:
data stamp logic configured to, in response to a memory write operation for writing data on a storage element in the bitcell array of non-volatile storage elements, store a temperature value provided by the temperature sensor as a stored temperature value to indicate a temperature of the write operation on the storage element; and
voltage demarcation logic configured to, in response to receiving a request to perform a read operation to read the data written by the write operation on the storage element, determine a demarcation voltage to apply for performing the read operation on the storage element, as a function of the stored temperature value at which the write operation occurred on the storage element.

US Pat. No. 10,395,727

NONVOLATILE METHOD DEVICE AND SENSING METHOD OF THE SAME

Samsung Electronics Co., ...

1. A sensing method of a nonvolatile memory device comprising multiple multi-level cells, the sensing method comprising:precharging, during a first precharge interval, a bit line of a selected memory cell and a sense-out node connected to the bit line to a bit line precharge voltage and a first sense-out precharge voltage, respectively;
identifying a first state of the selected memory cell, by developing the sense-out node during a first develop time and sensing a first voltage level of the sense-out node at a first sensing point;
precharging the sense-out node to a second sense-out precharge voltage during a second precharge interval; and
identifying a second state of the selected memory cell, by developing the sense-out node during a second develop time different from the first develop time and sensing a second voltage level of the sense-out node at a second sensing point,
wherein the second state is a program state adjacent to the first state.

US Pat. No. 10,395,726

FUSE ARRAY AND MEMORY DEVICE

WINBOND ELECTRONICS CORP....

1. A fuse array, comprising:a plurality of fuses, generating a plurality of data signals; and
a plurality of first D flip-flops, respectively coupled to a corresponding fuse of the fuses to receive the data signals generated by the corresponding fuse, receiving a clock signal from a clock generator and transmitting the clock signal and the data signals to a plurality of second D flip-flops of a plurality of memory cells, wherein the first D flip-flops are connected in series and the second D flip-flops are connected in series.

US Pat. No. 10,395,725

SEMICONDUCTOR DEVICE INCLUDING MEMORY CELLS

Semiconductor Energy Labo...

1. A semiconductor device comprising:an encoder comprising:
first to m-th memory cells (m is an integer of 2 or more), wherein an i-th memory cell (i is an integer greater than or equal to 1 and less than or equal to m) comprises a capacitor and a first transistor;
first to m-th lines, wherein an i-th line is electrically connected to a first terminal of the capacitor of the i-th memory cell; and
a circuit electrically connected to the first to m-th memory cells through a wiring,
wherein the i-th memory cell is configured to retain an i-th retained data to a node where a second terminal of the capacitor and a gate of the first transistor are electrically connected,
wherein the i-th line is supplied with an i-th supplied data, and
wherein the circuit is configured to output data depending on summation of products of the i-th retained data and the i-th supplied data.

US Pat. No. 10,395,723

MEMORY SYSTEM THAT DIFFERENTIATES VOLTAGES APPLIED TO WORD LINES

Toshiba Memory Corporatio...

1. A memory system comprising:a semiconductor memory chip including a substrate and word lines stacked in a thickness direction above the substrate, each of the word lines connecting a plurality of memory cells, the word lines including a first word line connecting first memory cells and a second word line above the first word line connecting second memory cells that are above the first memory cells, wherein a size of each of the first memory cells is different from a size of each of the second memory cells; and
a controller configured to:
determine an offset value with respect to each of a plurality of word line groups, each of the word line groups including a plurality of the word lines, and
with respect to each of the word line groups, set a voltage to be applied to a word line in the word line group during at least one of write and erase operations, based on the offset value corresponding to the word line group and a base parameter value, wherein
during the write operation, the semiconductor memory chip applies as the voltage a plurality of write voltages, one of the write voltages having a voltage level that is incremented by a step voltage from a bias voltage and others of the write voltages having a voltage level that is incremented by the step voltage from another write voltage, and
the base parameter value corresponds to a base value of the step voltage, and the offset value corresponds to an offset value of the step voltage.

US Pat. No. 10,395,719

MEMORY DEVICE DRIVING MATCHING LINES ACCORDING TO PRIORITY

SAMSUNG ELECTRONICS CO., ...

1. A memory device comprising:a storage circuit configured to store first data and to compare the first data and second data;
a first driving circuit configured to selectively drive a matching line to a first logic state only or not drive the matching line depending on a comparison result of the first data and the second data by the storage circuit; and
a second driving circuit configured to drive the matching line to a second logic state regardless of the comparison result.

US Pat. No. 10,395,706

SEMICONDUCTOR DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and
a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein
the first memory section comprises a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and
the second memory section comprises a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other,
wherein the second memory cells are higher from the substrate than each of the capacitors.

US Pat. No. 10,395,694

LOW PERMEABILITY ELECTRICAL FEED-THROUGH

Western Digital Technolog...

1. An electrical feed-through configured to interface between a hermetically-sealed environment and an external environment, the feed-through comprising:a first conductor layer (L1) comprising an L1 through-hole;
a first insulator layer (I1) over said L1 and comprising an I1 through-hole coaxial with said L1 through-hole;
a second conductor layer (L2) over a first portion of said I1 and coplanar with a second portion of said I1 and comprising an L2 through-hole coaxial with said I1 through-hole, wherein said L2 partially overlaps with said L1;
a second insulator layer (I2) over said L2 and said second portion of said I1 and comprising an I2 through-hole coaxial with said L2 through-hole; and
a third conductor layer (L3) over said I2 and comprising an L3 through-hole coaxial with said I2 through-hole,
wherein said L1 and said L3 are electrically connected by way of an electrically conductive annulus positioned through each of said L1, I1, L2, I2 and L3 through-holes.

US Pat. No. 10,395,682

ACHIEVING FINE MOTION BETWEEN MODULES IN A MAGNETIC HEAD

International Business Ma...

1. An apparatus comprising:a first module and a second module each having an array of transducers oriented orthogonal to an intended direction of tape travel thereacross, wherein the first module is movable relative to the second module;
a first actuator configured to exert a force on one of the modules for causing a relative movement of the first module with respect to the second module for aligning the transducers of the first module with the transducers of the second module in a direction of tape travel thereacross; and
a second actuator,
wherein the second actuator is coupled to a second end of the first module and at least a portion of the second module, the second end of the first module being opposite a first end of the first module along a longitudinal axis of the first module,
wherein the second actuator is positioned entirely between the second end of the first module and the portion of the second module,
wherein longitudinal axes of the arrays of the first and second modules are not pivotable from orthogonal to the intended direction of tape travel thereacross.

US Pat. No. 10,395,680

LEADING EDGE THERMAL SENSOR FOR A HEAT-ASSISTED MAGNETIC RECORDING HEAD

Seagate Technology LLC, ...

1. An apparatus, comprising:a slider comprising an air bearing surface (ABS);
a near-field transducer (NFT) at or near the ABS;
an optical waveguide configured to couple light from a laser source to the NFT comprising a first side facing the NFT and a second opposing side facing away from the NFT, and further comprising an upper cladding layer, a lower cladding layer disposed proximate the second side, and a core disposed between the first and second cladding layers; and
a thermal sensor disposed at a leading edge of the NFT within the lower cladding layer, the thermal sensor comprising an ABS section situated at or proximate the ABS and a distal section extending away from the ABS, the thermal sensor configured to detect changes in output optical power of the laser source and contact between the slider and a magnetic recording medium.

US Pat. No. 10,395,678

METHOD AND SYSTEM FOR DETERMINING SLIDER-DISK CONTACT IN A MAGNETIC RECORDING DISK DRIVE WITH DUAL FLY-HEIGHT ACTUATORS

Western Digital Technolog...

1. A method for determining slider-disk contact in a magnetic recording disk drive having a rotatable magnetic recording disk, a slider maintained over the surface of the rotating disk, a first thermal fly-height control (TFC1) heater and a first contact sensor on the slider, and a second thermal fly-height control (TFC2) heater and a second contact sensor on the slider, the first and second contact sensors being electrically connected to provide a combined output signal, the method comprising:applying power to the TFC1 heater;
applying power to the TFC2 heater;
dithering the TFC1 heater power at a first frequency;
dithering the TFC2 heater power at a second frequency different from said first frequency;
sensing the combined output signal;
analyzing the combined output signal to detect a first signal at said first frequency and a second signal at said second frequency;
comparing the first and second detected signals; and
determining from said compared detected signals the TFC1 and TFC2 heater power values corresponding to slider-disk contact.

US Pat. No. 10,395,673

IN-FIELD LASER CALIBRATION FOR HEAT-ASSISTED MAGNETIC RECORDING HEAD USING TEMPERATURE COMPENSATION EQUATION

Seagate Technology LLC, ...

1. A method, comprising:generating, for a heat-assisted magnetic recording (HAMR) disk drive, a temperature compensation equation that characterizes total currents supplied to a laser diode of the disk drive across a range of operating temperatures of the disk drive, the total currents representative of currents for recording data to or erasing data from a magnetic recording medium;
storing the temperature compensation equation in the disk drive;
updating the temperature compensation equation using a subsequent total current associated with an operating temperature at the time of the updating; and
adjusting, using the updated temperature compensation equation, the total current supplied to the laser diode for a subsequent write operation in response to an operating temperature at the time of the subsequent write operation.

US Pat. No. 10,395,672

METHODS AND SYSTEMS FOR MANAGING ADAPTATION DATA

ELWHA LLC, Bellevue, WA ...

1. A personal device comprising:circuitry configured for obtaining adaptation data that is correlated to at least one aspect of speech of a particular party;
circuitry configured for detecting using a microphone speech of at least one speech-facilitated interaction involving the particular party and a target device;
circuitry configured for determining that recognition by the target device of one or more words spoken by the particular party during the at least one speech-facilitated interaction has taken longer than a duration; and
circuitry configured for updating the target device with at least some of the adaptation data prior to completion of the at least one speech-facilitated interaction based at least partly on recognition of the one or more words by the target device taking longer than the duration,
wherein the at least some of the adaptation data is configured to be applied by the target device to improve one or more speech recognition capabilities with respect to the at least one speech-facilitated interaction.

US Pat. No. 10,395,671

DYNAMICALLY PROVIDING TO A PERSON FEEDBACK PERTAINING TO UTTERANCES SPOKEN OR SUNG BY THE PERSON

INTERNATIONAL BUSINESS MA...

1. A method, comprising:receiving, in real time, from a mobile communication device, utterances spoken or sung by a first person, wherein the mobile communication device detects the utterances spoken or sung by the first person when the utterances are spoken or sung;
determining that a location of the mobile communication device is in an area designated as a quiet zone;
generating, using a processor, a key indicator that indicates at least one characteristic of the detected utterances spoken or sung by the first person;
based, at least in part, on the key indicator, determining that the first person is speaking or singing too loudly in the area designated as the quiet zone; and
responsive to determining that the first person is speaking or singing too loudly in the area designated as the quiet zone, communicating to the mobile communication device feedback indicating that the first person is speaking or singing too loudly in the area designated as the quiet zone, wherein the mobile communication device is configured to present the feedback to the first person or a second person.

US Pat. No. 10,395,668

SYSTEM AND A METHOD FOR DETERMINING AN INTERFERENCE OR DISTRACTION

1. A method of determining an interference value, the method comprising:providing a sound signal;
providing an interferer signal;
establishing a pair of a first portion of the sound signal and a second portion of the interferer signal, the first and second portions having a particular time duration;
determining a single value of a first sound energy of the first portion;
determining a single value of a second sound energy of the second portion;
determining a single value of a third sound energy of a combination of the first and second portions; and
determining the interference value based on one single value of the single values of the first, second and third sound energies,
wherein the establishing, the determining the first sound energy, the determining the second sound energy, the determining the third sound energy, and the determining the interference value are performed within a period of time that is less than the particular time duration.

US Pat. No. 10,395,664

ADAPTIVE QUANTIZATION

Dolby Laboratories Licens...

1. A method of processing audio data, the method comprising:receiving audio data comprising a plurality of audio objects, the audio objects including audio signals and associated audio object metadata;
determining an importance metric for each of the audio objects, the importance metric being based, at least in part, on an energy metric;
determining a global importance metric for all of the audio objects, the global importance metric being based, at least in part, on a total energy value calculated by summing the energy metric of each of the audio objects;
determining an estimated quantization bit depth and a quantization error for each of the audio objects;
calculating a total noise metric for all of the audio objects, the total noise metric being based, at least in part, on a total quantization error corresponding with the estimated quantization bit depth;
calculating a total signal-to-noise ratio corresponding with the total noise metric and the total energy value; and
determining a final quantization bit depth for each of the audio objects by determining whether the total signal-to-noise ratio is less than or equal to a signal-to-noise ratio threshold; and
if it is determined that the total signal-to-noise ratio exceeds the signal-to-noise ratio threshold, performing the following steps iteratively until it is determined that the total signal-to-noise ratio is less than or equal to the signal-to-noise ratio threshold:
identifying an audio object corresponding with a greatest quantization error;
increasing a bit depth for quantizing the audio object corresponding with the greatest quantization error;
recalculating the total noise metric; and
recalculating the total signal-to-noise ratio,
the method further comprising quantizing the audio signals corresponding to each of the audio objects according to the final quantization bit depths.

US Pat. No. 10,395,663

SIGNAL ENCODING METHOD AND APPARATUS, AND SIGNAL DECODING METHOD AND APPARATUS

SAMSUNG ELECTRONICS CO., ...

1. A spectrum encoding method for an input signal including at least one of a speech signal and an audio signal in an encoding device comprising:selecting an encoding method of a band of the input signal based on bit allocation information of the band;
if the selected encoding method of the band is a zero-encoding method, encoding spectral components in the band to zero;
if the selected encoding method is not a zero-encoding method, encoding a magnitude of the spectral components in the band by using one of uniform scalar quantization (USQ) and trellis coded quantization (TCQ) based on an average number of bits allocated to the spectral components of the band; and
transmitting a bitstream including a result of the encoding, for reconstruction of the input signal.

US Pat. No. 10,395,660

APPARATUS AND METHOD FOR MULTICHANNEL DIRECT-AMBIENT DECOMPOSTION FOR AUDIO SIGNAL PROCESSING

Fraunhofer-Gesellschaft z...

1. An apparatus for generating one or more audio output channel signals depending on two or more audio input channel signals, wherein each of the two or more audio input channel signals comprises direct signal portions and ambient signal portions, wherein the apparatus comprises:a filter determination unit configured to calculate a filter by estimating first power spectral density information and by estimating second power spectral density information, wherein the filter depends on the first power spectral density information and on the second power spectral density information, wherein the filter determination unit is configured to calculate the filter by estimating the first power spectral density information, by estimating the second power spectral density information, and by determining trade-off information depending on at least one of the two or more audio input channel signals, and
a signal processor configured to determine the one or more audio output channel signals by applying the filter on the two or more audio input channel signals, wherein the one or more audio output channel signals depend on the filter,
wherein the first power spectral density information indicates power spectral density information on the two or more audio input channel signals, and the second power spectral density information indicates power spectral density information on the ambient signal portions of the two or more audio input channel signals, or
wherein the first power spectral density information indicates the power spectral density information on the two or more audio input channel signals, and the second power spectral density information indicates power spectral density information on the direct signal portions of the two or more audio input channel signals, or
wherein the first power spectral density information indicates the power spectral density information on the direct signal portions of the two or more audio input channel signals, and the second power spectral density information indicates the power spectral density information on the ambient signal portions of the two or more audio input channel signals.

US Pat. No. 10,395,658

PRE-PROCESSING PARTIAL INPUTS FOR ACCELERATING AUTOMATIC DIALOG RESPONSE

International Business Ma...

1. An apparatus comprising:a memory; and
a processor coupled to the memory and configured to:
receive a speech input from a user;
process a first portion of the input via more than one service module, including at least a speech-to-text service module, while continuing to receive more of the input to determine a first speculative result, wherein processing the first portion of the input comprises executing at least one service module coupled to a corresponding speculation buffer;
process a second portion of the input via the more than one service module, including at least the speech-to-text service module, to determine a second speculative result, wherein processing the second portion of the input comprises executing the at least one service module coupled to the corresponding speculation buffer, wherein the second portion of the input includes the first portion of the input as well as more of the input not included in the first portion of the input;
process the input via the more than one service module, including at least the speech-to-text service module, to determine a final output, wherein processing the input comprises executing the at least one service module coupled to the corresponding speculation buffer, wherein the final output is the first speculative result when the second speculative result and the first speculative result are the same, and wherein the final output is the second speculative result when the second speculative result and the first speculative result are not the same; and
output the final output to the user.

US Pat. No. 10,395,656

METHOD AND DEVICE FOR PROCESSING SPEECH INSTRUCTION

BAIDU ONLINE NETWORK TECH...

1. A method for processing a speech instruction, comprising:recognizing a speech instruction, so as to generate text information corresponding to the speech instruction;
performing semantic analysis on the text information, so as to obtain a semantic analysis result of the text information;
determining whether a corresponding operation is executable based on the semantic analysis result of the text information;
if it is determined that the corresponding operation is not executable based on the semantic analysis result of the text information, determining whether the text information belongs to instruction text data;
if it is determined that the text information belongs to the instruction text data, correcting the text information, so as to obtain corrected text information;
performing semantic analysis on the corrected text information, and executing the corresponding operation according to a semantic analysis result of the corrected text information;
wherein correcting the text information so as to obtain corrected text information comprises:
correcting the text information based on an instruction text correcting rule, so as to obtain the corrected text information;
wherein correcting the text information based on an instruction text correcting rule so as to obtain the corrected text information comprises:
locating an erroneous instruction keyword in the text information according to an instruction text matching rule;
rewriting the erroneous instruction keyword according to high frequency error information, so as to obtain the corrected text information.

US Pat. No. 10,395,653

VOICE DIALOG DEVICE AND VOICE DIALOG METHOD

TOYOTA JIDOSHA KABUSHIKI ...

1. A voice dialog device, comprising:a sight line detection unit configured to detect a sight line of a user;
a state determination unit configured to determine a state of the user;
a voice processing unit configured to obtain voice pronounced by the user and a result of recognizing the voice;
a dialog determination unit configured to determine whether or not the voice dialog device has a dialog with the user; and
an answer generation unit configured to generate an answer, based on a result of recognizing the voice,
wherein the dialog determination unit determines whether or not the user has started the dialog, based on both the sight line of the user and the obtained voice by:
when the determined state of the user is driving a vehicle, the detected sight line of the user is in a vehicle forward direction, and a start keyword has been detected from the voice, the dialog determination unit determines that the user has started a dialog,
when the determined state of the user is driving a vehicle and either the detected sight line of the user is not in the vehicle forward direction or the start keyword has not been detected from the voice, the dialog determination unit determines that the user has not started a dialog,
when the determined state of the user is not driving a vehicle, the detected sight line of the user is in a direction toward the voice dialogue device, and a start keyword has been detected from the voice, the dialog determination unit determines that the user has started a dialog, and
when the determined state of the user is not driving a vehicle and either the detected sight line of the user is not in the direction toward the voice dialogue device or the start keyword has not been detected from the voice, the dialog determination unit determines that the user has not started a dialog.

US Pat. No. 10,395,619

PROFILE ADJUSTMENT SYSTEM, PROFILE ADJUSTMENT DEVICE, AND PROFILE ADJUSTMENT METHOD

Seiko Epson Corporation, ...

1. A profile adjustment system configured to adjust, based on a parameter displayed in a display unit, a profile specifying a correspondence relationship between an input coordinate value of an input color space and an output coordinate value of an output color space, comprising:an adjustment coordinate reception unit configured to display, in the display unit, an input field of a coordinate of an adjustment point disposed on the color space and to receive a coordinate configuration of the adjustment point;
an adjustment influence range reception unit configured to display, in the display unit, an input field of an adjustment influence range of the adjustment point disposed on the color space and to receive a configuration of an adjustment influence range of the adjustment point;
a linking configuration reception unit configured to display, in the display unit, an input field of a linking configuration between each of at least two or more of the adjustment points configured in the adjustment coordinate reception unit and the adjustment influence range reception unit and to receive a linking configuration between each of the adjustment points as needed;
a linking configuration display processing unit configured to display, in the display unit, a linking configuration condition configured in the linking configuration reception unit;
an adjustment coordinate configuration unit configured to configure a coordinate of a new adjustment point between each of the adjustment points configured in the linking configuration reception unit;
an adjustment influence range configuration unit configured to configure an adjustment influence range for the new adjustment point configured in the adjustment coordinate configuration unit;
a whole adjustment influence range display processing unit configured to display, in the display unit, a whole adjustment influence range including the adjustment influence range reception unit, the linking configuration reception unit, the adjustment coordinate configuration unit, and the adjustment influence range configuration unit; and
a profile adjustment unit configured to adjust the profile based on all adjustment points configured in the adjustment coordinate reception unit and an adjustment point added by the adjustment coordinate configuration unit.

US Pat. No. 10,395,616

DISPLAY DEVICE WITH CLOCK SIGNAL MODIFICATION DURING VERTICAL BLANKING PERIOD

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a display panel comprising a pixel which is connected to a gate line and a data line;
a gate driver configured to generate a gate signal that swings between a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal; and
a gate controller configured to generate a clock signal that has a plurality of first pulses having a first high level, and a low level, during an active period of a frame cycle and that has a plurality of second pulses having a second high level and the low level during a vertical blanking period of the frame cycle following the active period, and to provide the gate driver with the clock signal,
wherein the second high level is lower than the first high level.

US Pat. No. 10,395,612

DRIVER CIRCUIT

INNOLUX CORPORATION, Mia...

9. A driver circuit, comprising:an output circuit comprising a pull-up transistor, and the pull-up transistor comprising a silicon semiconductor layer; and
a control circuit coupled to the output circuit, the control circuit comprising a first transistor, and the first transistor comprising an oxide semiconductor layer;
wherein the pull-up transistor has a first control node, and the pull-up transistor is coupled to a first clock signal and a gate line;
wherein the output circuit further comprises an auxiliary transistor coupled to the pull-up transistor and a low voltage, and the auxiliary transistor has a second control node;
wherein the control circuit further comprises a second transistor, a third transistor, and a fourth transistor;
wherein the first transistor is coupled to the first control node;
wherein the second transistor is coupled to the first control node, the low voltage, and the second control node;
wherein the third transistor is coupled to a high voltage and the second control node;
wherein the fourth transistor is coupled to the second control node and the low voltage;
wherein at least one of the second transistor, the third transistor and the fourth transistor comprises an oxide semiconductor layer;
wherein the control circuit further comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor;
wherein the pull-up transistor is further coupled to the first transistor,
wherein the auxiliary transistor is further coupled to the third transistor, the second transistor, the fourth transistor, the fifth transistor and the sixth transistor;
wherein the first transistor is coupled to the high voltage;
wherein the third transistor is coupled to the high voltage, the eighth transistor and the tenth transistor;
wherein the fourth transistor is coupled to the low voltage, the first control node, the first transistor, the second transistor, the seventh transistor and the ninth transistor;
wherein the sixth transistor is coupled to the low voltage, the fifth transistor and a first control signal line;
wherein the seventh transistor is coupled to a first input signal line, a second control signal line and the eighth transistor;
wherein the ninth transistor is coupled to a second input signal, a third control signal and the tenth transistor, the eighth transistor being coupled to a fourth control signal; and
wherein the tenth transistor is coupled to a fifth control signal;
wherein each of the pull-up transistor, the auxiliary transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor has a first end, a second end and a third end.

US Pat. No. 10,395,609

SEMICONDUCTOR DEVICE, DISPLAY PANEL, DISPLAY DEVICE, INPUT/OUTPUT DEVICE, AND DATA PROCESSING DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first D/A converter circuit; and
an amplifier electrically connected to the first D/A converter circuit, the amplifier comprising:
a first transconductance amplifier electrically connected to a first terminal, a second terminal, a first node, and a second node;
a current/voltage converter circuit between the first node and a third node, and between the second node and the third node;
a switch between the third node and the second terminal; and
an offset adjustment circuit electrically connected to the first node, the second node, and the third node,
wherein the first transconductance amplifier is configured to supply a first current to the first node and the second node on the basis of a voltage between the first terminal and the second terminal,
wherein the offset adjustment circuit is configured to supply a correction current to the first node and the second node, and
wherein the current/voltage converter circuit is configured to supply a first voltage to the third node on the basis of the first current and the correction current.

US Pat. No. 10,395,602

DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A display device, comprising:a display panel including data lines;
a data driver configured to output a data voltage to be supplied to the data lines through a source line; and
a multiplexer configured to distribute the data voltage received from the source line to the data lines in response to an enable signal received through an enable signal line, the multiplexer including a plurality of switching elements each including a drain electrode connected to the source line, a source electrode connected to the data line, and a gate electrode supplied with the enable signal,
wherein the enable signal is transferred from the enable signal line to the gate electrode of each switching element via an enable signal pattern, and
wherein the enable signal pattern is disposed on a metal layer different from the drain electrode, the source electrode, and the gate electrode of each switching element,
wherein the display panel has a curved or circular outer boundary,
wherein the data driver is disposed in an upper half of the display panel along an outside of the display panel,
wherein the display panel comprises another multiplexer,
wherein one multiplexer corresponds to one source line, and
wherein the multiplexers are disposed between the display panel and the data driver in a step shape along the outside of the display panel.

US Pat. No. 10,395,599

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device, comprising:a display panel divided into a first area including a plurality of first area pixel rows and a second area including a plurality of second area pixel rows, the number of pixels of each of the second area pixel rows being less than the number of pixels of each of the first area pixel rows;
a scan driver configured to provide a plurality of scan signals to the first area pixel rows and the second area pixel rows based on a width of an active period of a clock signal, the scan signals being output having substantially the same width of active periods to each other;
a data driver configured to provide a plurality of data signals to the display panel via a plurality of data lines; and
a timing controller configured to adjust the width of the active period of the clock signal within a frame period based on locations of the first area and the second area.