US Pat. No. 10,484,599

SIMULATING DEPTH OF FIELD

Microsoft Technology Lice...

1. A computer-implemented method comprising:determining an optimal scan distance of a camera from a subject in a physical environment for a scan of the subject by the camera;
iteratively updating a blur level to correspond to a proximity of the camera to the determined optimal scan distance as the proximity changes during the scan; and
for each update to the blur level from the iteratively updating, generating, on a user device associated with the scan, an image comprising a three-dimensional (3D) model of the physical environment depicted at the updated blur level, the 3D model produced from the scan, the generating comprising:
blending a first texture with a second texture based on determining that a value of the blur level is greater than a first value corresponding to the first blur texture and a second value corresponding to the second blur texture, and
performing the blurring of the 3D model with the blended first texture and second texture for the image.

US Pat. No. 10,484,587

VEHICLE CAMERA WITH CONNECTOR SYSTEM FOR HIGH SPEED TRANSMISSION

MAGNA ELECTRONICS INC., ...

1. A camera for a vision system of a vehicle, said camera comprising:a front housing portion comprising a lens;
a circuit board having circuitry established thereat, wherein said circuitry is associated with an imager of said camera;
a plastic rear housing portion having a connector for electrically connecting to a connector end of a wire harness of the vehicle when said camera is disposed at the vehicle;
wherein said rear housing portion comprises internal wall structure establishing internal wall surfaces of said rear housing portion;
wherein said connector of said rear housing portion comprises a multi-pin connector having terminals that electrically connect to circuitry at said circuit board; and
an electrically conductive metallic shield element disposed within said rear housing portion and corresponding with said internal wall surfaces of said rear housing portion.

US Pat. No. 10,484,554

PROCESSING APPARATUS, IMAGE FORMING APPARATUS, AND NON-TRANSITORY COMPUTER READABLE MEDIUM FOR PRESENTING A CUSTOMIZATION SCREEN

FUJI XEROX CO., LTD., To...

1. A processing apparatus comprising:a function-screen processing unit that arranges setting-item elements in order, the setting-item elements being display elements corresponding to respective setting items to be displayed, the setting items being a portion of a group of setting items corresponding to a function provided to a user, and that performs processing for presenting, to the user, a function screen on which a customization element that is a display element for receiving a request for a customization operation is arranged; and
a customization-screen processing unit that performs, in a case where the user has performed an operation to request the customization operation on the customization element within the presented function screen, processing for presenting, to the user, a customization screen through which, for each of the setting items in the group of setting items corresponding to the function, specification of whether the setting item is to be displayed is received.

US Pat. No. 10,484,548

OPERATION DISPLAY SYSTEM, OPERATION DISPLAY APPARATUS, AND OPERATION DISPLAY PROGRAM

KONICA MINOLTA, INC., To...

1. An operation display system comprising:a plurality of operation display apparatuses each including a touch panel; and
a hardware processor configured to:
acquire load references of the respective touch panels of the plurality of operation display apparatuses, the load references serving as a reference of pressing force by which the respective corresponding touch panels receive an operation,
compare the acquired load references of a first operation display apparatus and a second operation display apparatus among the plurality of operation display apparatuses, with each other, and
in a case in which it is determined based on a result of the comparison that there is a difference between the load references, control a degree of a change in pressing force for pressing the touch panel of the second operation display apparatus as compared to the pressing force for pressing the touch panel of the first operation display apparatus, to be indicated in an output notification, the first operation display apparatus being an operation display apparatus operated by a user most recently among the plurality of operation display apparatuses and the second operation display apparatus being an operation display apparatus to be subsequently operated among the plurality of operation display apparatuses.

US Pat. No. 10,484,536

METHODS AND APPARATUS TO ASSOCIATE VOICE MESSAGES WITH MISSED CALLS

BlackBerry Limited, Wate...

1. A method comprising:loading into memory of a mobile device a call log item;
determining whether or not the call log item relates to a missed call; and
in response to determining that the call log item relates to a missed call:
obtaining a caller identity and a call log item time stamp from the call log item, the call log item time stamp comprising a time at which the mobile device obtains a missed call indication;
locating an incoming voice message associated with the call log item based on a timing constraint being met that includes an evaluation of the call log item time stamp from the call log item, a message duration of an outgoing message, a message duration of the incoming voice message, and a latency time including time required to create a visual voicemail message from the incoming voice message, wherein the latency time is learned from prior message processing and a comparison between the time at which the mobile device obtained the missed call indication and a time when the visual voicemail message is received; and
adding the call log item to the call log upon locating the incoming voice message based on the timing constraint.

US Pat. No. 10,484,530

SENSOR BASED COMPONENT ACTIVATION

Google LLC, Mountain Vie...

1. A computer-implemented method of mode determination, the method comprising:receiving, by a computing system comprising one or more computing devices, object detection data based in part on one or more sensor outputs from a plurality of sensors that detect one or more portions of a user of the computing system;
receiving, by the computing system, motion data based in part on one or more sensor outputs from the plurality of sensors, wherein the motion data describes a motion of the computing system relative to the user of the computing system;
determining, by the computing system, based in part on the object detection data, a state of the one or more portions of the user of the computing system comprising one or more spatial relations of the one or more portions of the user of the computing system with respect to the computing system;
determining, by the computing system, based in part on the object detection data and the motion data, when the state of the one or more portions of the user relative to the computing system matches one or more falsing profiles associated with a state of the one or more portions of the user relative to the computing system that does not activate the one or more components, wherein the satisfying the one or more operational criteria comprises the state of the one or more portions of the user relative to the computing system not matching any of the one or more falsing profiles; and
responsive to the state of the one or more portions of the user of the computing system satisfying one or more operational criteria, activating, by the computing system, an input mode of a plurality of input modes associated with activating one or more components of the computing system, the one or more components comprising one or more microphone components, one or more camera components, or one or more text input components, wherein the one or more components are associated with performing one or more operations comprising detection of one or more inputs.

US Pat. No. 10,484,515

IMPLEMENTING LOGICAL METADATA PROXY SERVERS IN LOGICAL NETWORKS

NICIRA, INC., Palo Alto,...

1. A method for enabling a metadata proxy server to provide metadata proxy services for a plurality of logical networks, the method comprising:at a managed forwarding element (MFE) that executes on a same host computer as the metadata proxy server,
receiving a first packet sent from a first data compute node (DCN) of a first logical network requesting metadata for the first DCN, said first packet comprising a particular layer four destination port number;
receiving a second packet sent from a second DCN of a second logical network requesting metadata for the second DCN, said second packet comprising the same particular layer four destination port number;
replacing (i) the particular destination port number in the first packet with a first port number that corresponds to a first port of the metadata proxy server that is associated with the first logical network and (ii) the particular destination port number in the second packet with a second different port number that corresponds to a second port of the metadata proxy server that is associated with the second logical network; and
forwarding the first and second packets with their replaced port numbers to the metadata proxy server on the host computer for the metadata proxy server to provide metadata for the first DCN through the first port number and provide metadata for the second DCN through the second port number.

US Pat. No. 10,484,514

METHOD FOR DISPATCHING NETWORK FRAMES AMONG PROCESSING RESOURCES

KALRAY, Orsay (FR)

1. A method of processing data frames arriving on a network interface, the method comprising the following steps implemented in the network interface:storing a set of subframe and session parameter positions for a frame, including positions of a subframe parameter and of a set of session parameters;
storing an expected value for the subframe parameter;
receiving a current frame in fixed size words;
when a current word of the current frame overlaps a position among the stored parameter positions, storing the current word in a respective register of an extracted parameter register bank;
configuring an index mask for cancelling all data of the extracted parameter register bank except data at the positions of the set of session parameters;
calculating an index from the index mask;
comparing data received at the position of the subframe parameter to the expected value; and
if the comparison is equal, routing the current frame to a processing resource associated with the index.

US Pat. No. 10,484,505

SYSTEM AND METHOD FOR ZERO-FOOTPRINT SCREEN CAPTURE

ZOOM International a.s., ...

1. A system for zero-footprint screen capture for contact centers, comprising:a screen capture server comprising a processor, a memory, and a plurality of software programming instructions stored in the memory and operating on the processor which cause the screen capture server to:
receive screen capture data from a screen capture software application; and
store the screen capture data; and
a screen capture software application comprising a plurality of programming instructions configured to be downloaded to an agent workstation, wherein the screen capture software application, when operating on the agent workstation, causes the agent workstation to:
detect a connection of an incoming phone call to an agent workstation;
start capturing images of a screen of the agent workstation;
detect a disconnection of the incoming phone call to the agent workstation; and
stop capturing images of the screen of the agent workstation; and
a web server comprising a processor, a memory, and a plurality of programming instructions stored in the memory and operating on the processor which cause the web server to;
receive login information for an agent via a web browser on the agent workstation;
download an applet to the agent workstation for authentication;
associate, using the applet, an agent identification with workstation;
receive captured screens of the agent workstation from the screen capture software application;
transmit captured screens to screen capture server.

US Pat. No. 10,484,502

SYSTEM AND METHOD FOR IMPROVING EFFICIENCY OF A REMOTE COMPUTING DEVICE

Click Therapeutics, Inc.,...

1. A method, comprising:identifying, by a server including one or more processors, a profile associated with an application executing on a remote computing device;
transmitting, by the server, at a first time in accordance with a delivery model, a first request for application activity update, the first request including instructions to provide a trigger on the remote computing device, the remote computing device configured to provide a plurality of actions to be performed via the remote computing device responsive to detecting an activation of the trigger;
receiving, by the server, from the remote computing device and responsive to the activation of the trigger on the remote computing device, a response including content relating to a selected action of the plurality of actions performed via the remote computing device;
determining, by the server, based on the content relating to the selected action included in the response from the remote computing device, a delay from the first time corresponding to a second time at which to transmit a second request for application activity update;
updating, by the server, the profile to include an entry corresponding to the first request for application activity update and the response, the entry identifying a first timestamp at which the first request for application activity update was transmitted, a second timestamp at which the response was received, and a type of response; and
transmitting, by the server, at the second time in accordance with the delivery model, the second request for application activity update to the remote computing device.

US Pat. No. 10,484,500

UPDATING A PROFILE

INTERNATIONAL BUSINESS MA...

1. A method for updating a profile with a computer comprising a server and having a network interface for communicating with a computer network and programmed to perform the method, the method comprising:with the computer and network interface, monitoring electronic communications between a target user and a number of other users occurring on the computer network in real-time;
with an extracting circuit of the computer, extracting communicated information available about the target user and the number of other users from the electronic communications;
with the computer and network interface, accessing at least one social network available on the computer network to obtain information from a profile of the target user on each social network;
based on an analysis of the communicated information available about the target user and the number of other users, with an identifying circuit of the computer, identifying relevant information from the communicated information that replaces older information already in the profile of the target user and so is relevant for updating the profile of the target user on a particular social network, the profile comprising a visual display of personal data associated with the target user for presentation to other users of the social network;
with the computer, accessing metadata associate with the social network using the network interface, and determining from the metadata associated with the social network whether the social network is designated for personal use or business use; and,
when a type of the relevant information, as between personal or business information, matches the designated use of the social network, with the computer, updating the profile of the target user on that social network with the relevant information, including updating the older information already in the profile of the target user on that social network using the relevant information derived from the analysis; and
with the computer, continually updating the profile of the target user with relevant information extracted from further electronic communications so that information in the profile of the target user remains current for other users of the social network.

US Pat. No. 10,484,495

SYSTEM AND METHOD FOR NOTIFICATION MANAGEMENT

Amazon Technologies, Inc....

1. A device comprising:a memory storing computer-executable instructions; and
at least one processor in communication with the memory, the at least one processor executes the computer-executable instructions to:
receive preference data that designates preferred distribution of a notification associated with a merchant account, the preferred distribution indicates one or more of:
a preferred user device to send the notification,
a period of time to send the notification,
a security protocol to protect information included in the notification, or a priority hierarchy for sending the notification;
receive heartbeat data indicative of a user device connected to a network and identification information that associates the user device to the merchant account;
receive merchant data indicative of activity information associated with the merchant account;
generate the notification based on the merchant data;
based on the preference data and receipt of the heartbeat data, send the notification corresponding to the activity information to the user device; and
receive confirmation data indicative of presentation of the notification by the user device.

US Pat. No. 10,484,493

METHOD AND APPARATUS FOR COMMUNICATING MESSAGES

1. A sending device, comprising:a processing system including a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
receiving user input including a first message and identification information associated with a recipient user that is intended to receive the first message, wherein the first message comprises a text message;
obtaining activity information and presence information associated with the recipient user;
determining a first attention span of the recipient user according to the activity information;
detecting network traffic for a communication network communicatively coupled to the sending device;
generating a second message by adjusting the first message according to the first attention span and the network traffic, wherein the second message comprises a video message;
selecting a receiving device from among a group of devices according to the presence information; and
transmitting the second message to a server hosting a social network website, wherein the second message is accessed, via the social network website, by the receiving device to enable the receiving device to generate a third message by adjusting the second message according to a second attention span and significance of content in one of the first message and the second message determined by the receiving device for the recipient user, wherein the adjusting of the second message to generate the third message comprises removing content from the second message and adding content from the first message, wherein the third message is presentable by the receiving device, wherein the third message comprises an audio message.

US Pat. No. 10,484,476

DISTRIBUTED DATA MANAGEMENT SYSTEMS FOR EMBEDDED CONTROLLERS

Siemens Aktiengesellschaf...

1. A system for managing data in an industrial production environment, the system comprising:a distributed database system stored on a plurality of embedded controller devices, wherein each respective embedded controller device comprises:
a distributed database instance configured to store data collected from the industrial production environment by the respective embedded controller device, and
a database management application configured to facilitate distributed queries and transactions on the plurality of embedded controller devices; and
a sharding key definition providing a mapping between data stored in the distributed database system and the plurality of embedded controller devices.

US Pat. No. 10,484,470

PEAK CYCLICAL WORKLOAD-BASED STORAGE MANAGEMENT IN A MULTI-TIER STORAGE ENVIRONMENT

International Business Ma...

1. A method for managing data, the method comprising:collecting workload information for a device for a present time period and one or more previous time periods;
determining a maximum workload parameter for the present time period and the one or more previous time periods;
determining a maximum workload threshold that corresponds to the maximum workload parameter;
computing a difference between the maximum workload threshold and the maximum workload parameter in response to a determination that the maximum workload parameter is less than the maximum workload threshold;
determining an amount of workload to move to the device based on the difference; and
preventing movement of additional workload to the device over the present time period in response to a determination that the maximum workload parameter is at least as great as the maximum workload threshold.

US Pat. No. 10,484,464

CONNECTION CONTROL DEVICE, CONNECTION CONTROL SYSTEM, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

KABUSHIKI KAISHA TOSHIBA,...

9. A non-transitory computer readable medium having a program stored therein which, when executed, causes a computer to execute processing comprising:transmitting an acquiring request of state information to a plurality of relay servers including a temporary server and a normal server via a network and receiving the state information transmitted from the relay servers, wherein the temporary server has a scheduled stop time point and a scheduled start time point set therein and stops running at the scheduled stop time point and restarts the running at the scheduled start time point and the normal server continues running without stopping, the plurality of relay servers being configured to connect between control devices and communication devices controlled by the control devices;
receiving a connection destination determination request transmitted from a first of the communication devices, which is not yet connected to any relay server, via the network;
selecting a relay server to be connected by the first communication device from among the plurality of relay servers based on the state information; and
transmitting address information of the relay server selected, to the first communication device via the network, the address information being required for the first communication device to connect to the selected relay server,
wherein the selecting includes determining whether a time period until the scheduled stop time point of the temporary server is reached is longer than a predetermined length of time period, and when the time period is longer than the predetermined length of time period, selecting a relay server so that load is equally distributed between the temporary server and the normal server.

US Pat. No. 10,484,460

ACCESS SERVICES IN HYBRID CLOUD COMPUTING SYSTEMS

Microsoft Technology Lice...

1. A method of facilitating operations between a public cloud computing system interconnected with a private cloud computing system via a computer network, the method comprising:exposing, at the public cloud computing system, one or more applications deployable in the private cloud computing system to an access service of the public cloud computing system, the access service being configured to respond to one or more requests from a connection service of the private cloud computing system without having direct access to resources in the private cloud computing system;
receiving, from the connection service of the private cloud computing system, a request for a list of at least one of the one or more applications that are deployable in the private cloud computing system; and
in response to the received request,
transmitting, via the computer network, from the access service of the public cloud computing system to the connection service of the private cloud computing system, the list of at least one of the one or more applications deployable in the private cloud computing system selectively identified by the access service based on a service subscription of the connection service at the public cloud computing system; and
transmitting, from the public cloud computing system to the private cloud computing system, one or more artifacts of at least one application in the list to be deployed in the private cloud computing system.

US Pat. No. 10,484,442

JUST-IN-TIME DISTRIBUTED VIDEO CACHE

Performance and Privacy I...

1. A computer-implemented method for streaming video, the method comprising:receiving a request to optimize an original source file from a client computing device, the request including a key specifying parameters to optimize the original source file;
identifying, based on the key, a first portion of an optimized version of the original source file in a local cache of a video optimizer;
generating a query, based on the key, to a database maintaining a plurality of reference keys corresponding to a plurality of optimized versions of source files stored on a plurality of other video optimizers, each reference key specifying parameters of an optimized version of a source file;
receiving, from the database, a response indicating whether the key matches a reference key;
receiving from the database, in response to a reference key matching the key, the address of another video optimizer storing a segment of the requested optimized version of the original source file;
stitching the first portion of the optimized version of the original source file with the segment of the optimized version of the original source file stored on the other video optimizer; and
streaming the stitched optimized version of the original source file for playback on the client computing device.

US Pat. No. 10,484,428

METHODS AND SYSTEMS FOR SECURING VPN CLOUD SERVERS

LGS Innovations LLC, Her...

1. A computer-implemented method for enhancing security on a network comprising:sending, from a virtual private network (VPN) service provider, a request to a cloud provider to create a server on a cloud independent of an enterprise selection of the cloud server;
receiving a notification from the cloud provider that the requested server is available on the cloud;
embedding the server with a VPN service;
sending, from the VPN service provider, a credential of the embedded server to the enterprise on the network;
reviewing, via a graphical user interface (GUI) of the VPN service provider, a list of servers created by the cloud provider;
determining, via the GUI of the VPN service provider, which users in the enterprise to match with the generated servers;
evaluating on a portal on the GUI of the VPN service provider, progress of server generation by the cloud provider and one or more additional cloud providers; and
ranking efficiency of the cloud provider and the one or more additional cloud providers based on the evaluating step.

US Pat. No. 10,484,420

RETRIEVING NETWORK PACKETS CORRESPONDING TO DETECTED ABNORMAL APPLICATION ACTIVITY

International Business Ma...

1. A computer-implemented method for preventing abnormal application activity associated with a software application running on a data processing system, the computer-implemented method comprising:retrieving, by the data processing system, packets from a packet buffer in response to detecting the abnormal application activity using packet location information corresponding to information associated with the detected abnormal application activity running on the data processing system, wherein the packet location information is used to map a relationship between a received packet and the software application associated with the detected abnormal activity causing security violation;
analyzing, by the data processing system, the packets to identify content of the packets causing the abnormal application activity; and
blocking, by the data processing system, network packets containing the content causing the abnormal application activity in the data processing system.

US Pat. No. 10,484,413

SYSTEM AND A METHOD FOR DETECTING ANOMALOUS ACTIVITIES IN A BLOCKCHAIN NETWORK

COGNIZANT TECHNOLOGY SOLU...

1. A method for detecting anomalous activities in a distributed and decentralized network, performed by an anomaly detection engine interfacing with one or more transaction databases and one or more terminal devices, the anomaly detection engine executing instructions stored in a memory via a processor, said method comprising:generating, by the anomaly detection engine, a data set representative of identified users and associated transactional behavior, wherein users are identified from anonymous users transacting in the distributed and decentralized network using a first set of rules;
generating, by the anomaly detection engine, a datatype by processing the data set using a second set of rules, wherein the datatype is representative of transactional behavior of the users with other users;
generating, by the anomaly detection engine, one or more first level data clusters based on the data set and one or more transactional attributes by employing one or more clustering techniques, wherein each data cluster is representative of data associated with users having similar transactional behaviour;
generating, by the anomaly detection engine, anomaly detection values based on the first level data clusters, the datatype and one or more behavioral parameters derived from the first level data clusters by employing an anomaly detection technique;
classifying users, by the anomaly detection engine, into one or more second level data clusters based on the generated anomaly detection values using a third set of rules, wherein the second level data clusters are representative of data associated with users having similar transactional behavior;
classifying users, by the anomaly detection engine, into one or more new data clusters based on the generated anomaly detection values using a third set of rules, wherein the new data clusters are representative of data associated with users having similar transactional behavior;
determining, by the anomaly detection engine, if the classification of users into the new data clusters is same as the classification of users into the second level data clusters, wherein the classification of users is identified as optimum classification if the classification remains the same; and
identifying one or more users with high anomaly detection value from the users classified in the new data cluster classification determined as optimum classification, wherein the one or more users with high anomaly detection values are identified as anomalous users.

US Pat. No. 10,484,410

ANOMALY DETECTION FOR MICRO-SERVICE COMMUNICATIONS

Cisco Technology, Inc., ...

1. A method comprising:at a computing device:
obtaining a plurality of micro-service communication records that are each associated with traffic sent between pairs of executables that are related to a micro-services application, wherein each of the micro-service communication records includes a time series entry and an associated trace sequence identifier;
determining, from the plurality of micro-service communication records, one or more typical communication patterns for the executables related to the micro-services application;
obtaining one or more micro-service communication records that are associated with traffic sent between pairs of the executables related to the micro-services application, wherein the one or more micro-service communication records each include a time series entry and an associated trace sequence identifier, wherein the one or more micro-service communication records are different from the plurality of micro-service communication records, and wherein each of the one or more micro-service communication records is generated during a first time period; and
analyzing the one or more micro-service communication records relative to the one or more typical communication patterns to detect possible anomalous communication patterns associated with the micro-services application during the first time period.

US Pat. No. 10,484,398

THREAT INTELLIGENCE ON A DATA EXCHANGE LAYER

McAfee, LLC, Santa Clara...

1. A threat intelligence apparatus adapted for use on a data exchange layer (DXL), comprising:a network interface;
a DXL client engine comprising a DXL application programming interface (API) operable for communicatively coupling the apparatus to a DXL via a DXL broker, wherein the DXL is a messaging bus configured to provide endpoint-to-endpoint communication, brokered by a DXL broker, between loosely-coupled dissimilar DXL endpoints, including the threat intelligence apparatus, on a one-to-many publish-subscribe fabric on which a plurality of private DXL topics are to be established between the dissimilar DXL endpoints; and
one or more logic elements comprising a threat intelligence engine operable for:
aggregating reputation data for a network object via a plurality of DXL messages;
computing a composite reputation for the network object;
receiving from a DXL endpoint a DXL request message, via a private topic of the plurality of private topics, for a reputation for the network object; and
providing the composite reputation via a DXL message through the DXL broker and the one-to-many publish-subscribe fabric.

US Pat. No. 10,484,397

AUTOMATIC ELECTRONIC MAIL (EMAIL) ENCRYPTION BY EMAIL SERVERS

Fortinet, Inc., Sunnyval...

1. A method comprising:receiving, by an electronic mail (email) server associated with a private network, from a client device coupled with the private network, a first email message originated by a local sender using the client device and directed to a remote recipient, wherein the local sender is a first user of a plurality of users associated with the private network and wherein the remote recipient is not a user associated with the private network;
querying, by the email server, one or more key servers for a public key of the remote recipient;
when the public key of the remote recipient is returned by the one or more key servers, then using the public key of the remote recipient by the email server to encrypt the first email message;
when the public key of the remote recipient does not exist, then foregoing encryption of the first email message;
querying, by the email server, the one or more key servers for a public key of the local sender;
when the public key of the local sender does not exist on the one or more key servers, then automatically generating, by the email server, a temporary key pair for the local sender on the fly and without requiring intervention on the part of the local sender, wherein the temporary key pair for the local sender includes the public key of the local sender and a private key of the local sender; and
transmitting, by the email server, both the email message and the public key of the local sender to the remote recipient.

US Pat. No. 10,484,380

UNTRUSTED NETWORK DEVICE IDENTIFICATION AND REMOVAL FOR ACCESS CONTROL AND INFORMATION SECURITY

Bank of America Corporati...

1. An information security system comprising:a switch configured to provide network connectivity for one or more endpoint devices to a network;
a network authentication server operably coupled to the switch and configured to:
determine an endpoint device is failing authentication in response to the endpoint device connecting to a port on the switch;
receive a device identifier for the endpoint device from the switch; and
send the device identifier for the endpoint device to a threat management server in response to the endpoint device failing authentication; and
the threat management server operably coupled to the switch and the network authentication server comprising:
a memory configured to store:
a device log file comprising:
a first set of device identifiers for endpoint devices that have failed authentication with the network authentication server; and
a second set of device identifiers for endpoint devices that have previously passed authentication with the network authentication server; and
a threat management engine implemented by a processor configured to:
identify the endpoint device for removal in response to receiving the device identifier, comprising:
comparing the device identifier to the second set of device identifiers for endpoint devices that have previously passed authentication with the network authentication server;
determining the device identifier is present in the second set of device identifiers;
determining a number of times that the endpoint device has failed authentication in response to determining that the device identifier is present in the second set of device identifiers; and
determining that the number of times the endpoint device has failed authentication exceeds a first threshold value within a first time period; and
block the endpoint device from accessing the network via the port on the switch in response to identifying the endpoint device for removal.

US Pat. No. 10,484,372

AUTOMATIC REPLACEMENT OF PASSWORDS WITH SECURE CLAIMS

Amazon Technologies, Inc....

1. A computer system, comprising:a network interface configured to transmit data over a network;
a biometric sensor configured to acquire biometric data of a user;
a secure storage element configured to store data including the biometric data acquired by the biometric sensor;
an input device;
one or more hardware processors operatively coupled to the network interface, the biometric sensor, the secure storage element, and the input device; and
memory operatively coupled to the one or more hardware processors, the memory storing an operating system and an application program that includes instructions executable by the one or more hardware processors that, as a result of execution by the one or more hardware processors, cause the one or more hardware processors to:
establish a secure session between the computer system and a server using a user credential;
responsive to receiving a selection via the input device for authentication using the biometric data, configure the application program for authentication using the biometric data, and generate an asymmetric cryptographic key pair;
store a first key of the cryptographic key pair in the secure storage element via the operating system, without storing the user credential in the secure storage element, wherein access to the first key is secured by the biometric data;
transmit a second key of the cryptographic key pair to the server via the network for storage in association with a user account associated with the user;
responsive to receiving a request to perform an action that requires the application program to authenticate an identity of the user of the computing system with the server, activate a presentation device associated with the computer system so as to prompt the user to input new biometric data using the biometric sensor;
responsive to the operating system authenticating the identity of the user using the new biometric data, retrieve the first key via the operating system from the secure storage element;
encrypt an authentication data object using the first key to form an encrypted data object;
transmit the encrypted data object to the server to enable the server to authorize the action that required authentication in lieu of the user credential, based on decrypting the encrypted data object using the stored second key; and
as a result of authorization by the server responsive to the decrypting of the encrypted data object using the stored second key, proceed to conduct the action requested.

US Pat. No. 10,484,371

DEVICE CONTROLLER SECURITY SYSTEM

Seagate Technology LLC, ...

1. A method comprising:accumulating at least one behavior parameter of a controller of a data storage device with an authentication module of the controller during data access operation of the controller;
generating a unique signature of the controller with the authentication module of the controller based on the at least one behavior parameter;
connecting a first host device to the controller;
providing a first signature to the controller from the first host device;
rejecting a first data access command from the first host in response to the first signature not matching the unique signature;
connecting a second host device to the controller;
providing a second signature to the controller from the second host device;
verifying the second signature matches the unique signature responsive to an initialization command from the second host device to confirm the second host device is trusted; and
transferring data between the second host device and the non-volatile memory with the controller in response to the controller issuing a second data access command.

US Pat. No. 10,484,359

DEVICE-LEVEL AUTHENTICATION WITH UNIQUE DEVICE IDENTIFIERS

Confia Systems, Inc., Mo...

1. A method comprising:transmitting, by a client device, a manufacturer security certificate to a provisioning server device, wherein the manufacturer security certificate is associated with a manufacturer of the client device;
establishing, between the client device and the provisioning server device, a secure connection, wherein the secure connection is established based on the manufacturer security certificate;
receiving, by the client device over the secure connection, a server security certificate, wherein the server security certificate identifies secure communication parameters of a pre-validated server device, wherein the pre-validated server device is not the provisioning server device;
obtaining, by the client device, a unique client device identifier, wherein the unique client device identifier is configured to support secure access to the pre-validated server device; and
based on the unique client device identifier, accessing, by the client device, protected information available to the pre-validated server device, wherein accessing the protected information occurs without the client device transmitting security credentials that identify a user of the client device to the pre-validated server device, wherein the client device stores a plurality of unique tokens, each token limited to use once per an epoch defined by a pre-established number of seconds, and wherein accessing the protected information comprises transmitting a message to establish a second secure connection with the pre-validated server device, wherein the message contains a particular token, from the plurality of unique tokens, that has not been used in a current epoch.

US Pat. No. 10,484,346

ESTABLISHMENT OF CONSORTIUM BLOCKCHAIN NETWORK

Microsoft Technology Lice...

1. An apparatus for a blockchain system, comprising:a device including at least one memory adapted to store run-time data for the device, and at least one processor that is adapted to execute processor-executable code that, in response to execution, enables the device to perform actions, including:
storing pre-determined code of a pre-determined type of blockchain protocol code in a trusted execution environment (TEE) of a first validation node;
storing, in the first validation node: a first pre-determined membership list of a consortium, wherein the first pre-determined membership list includes a prospective member associated with the first validation node and a first authorization associated with the pre-determined type of blockchain protocol code;
receiving, from a plurality of prospective members of the consortium: a plurality of membership lists, and a plurality of authorizations from the plurality of prospective members of the consortium, wherein the plurality of authorizations are indications associated with the pre-determined type of blockchain protocol code;
making a determination as to whether the plurality of membership lists from the plurality of prospective members of the consortium match the first pre-determined membership list and the plurality of authorizations that are indications associated with the pre-determined type of blockchain protocol code match the first authorization;
upon determining that the plurality of membership lists from the plurality of prospective members of the consortium match the first pre-determined membership list and that the plurality of authorizations that are indications associated with the pre-determined type of blockchain protocol code match the first authorization, verifying, via TEE attestation, that validation nodes associated with prospective members of the consortium store the pre-determined type of blockchain protocol code that matches the first authorization; and
upon the TEE attestation being successful, bootstrapping a consortium network such that the prospective members become members of the consortium network.

US Pat. No. 10,484,335

SECURE REMOTE COMPUTER NETWORK

Connectify, Inc., Philad...

1. A computer communications network system, comprising:(a) at least one VPN server computer in a hub mode in communication connectivity with an external network;
(b) at least one VPN client computer in a client mode in communication connectivity with an external network;
(c) a directory service in communication connectivity with an external network, the directory service enabling open protocol real-time messaging; and
(d) a management database for recording real time statistics related to the computer communications network system, the real time statistics including (i) cost, (ii) performance, and (iii) expected reliability of each of a plurality of potential connections between the at least one VPN server computer in a hub mode and the at least one VPN client computer in a client mode,
wherein said at least one VPN server computer in a hub mode initiates a connection with said directory service to be registered and made available for said at least one VPN client computer in a client mode to dynamically communicate via the open protocol real-time messaging with said at least one VPN server computer in a hub mode through an external network.

US Pat. No. 10,484,316

SYSTEM AND METHOD FOR CREATING AND SHARING MEDIA PLAYLISTS

S Wave Pty Ltd, Hawthorn...

1. A system for facilitating the creation of playlists of media files includinga database configured to store a plurality of playlists therein, each playlist including one or more media files, and each playlist and media file being identifiable by one or more identifiers;
a search engine being operatively configured to search and locate
one or more media files of a selected play list, wherein the selected play list can be selected from a list including playlists and media files identified based on the one or more identifiers,
one or more playlists including a selected media file, wherein the selected media file can be selected from a list of media files and play lists identified based on the one or more identifiers; and
a display module for generating display data to display search results of the search engine, wherein the display module is configured to generate display data for displaying
a first list of playlists and media files in response to receiving one or more identifiers,
a second list of playlists in response to a selected media file from the first list, wherein the selected media file forms part of each playlist in the second list, and
a third list of media files in response to a selected playlist from the second list,
wherein the selected play list includes the third list of media files
or for displaying
a first list of playlists and media files in response to receiving one or more identifiers,
a second list of media files in response to a selected playlist from the first list, wherein the selected playlist includes the second list of media files, and
a third list of playlists in response to a selected media file from the second list, wherein the selected media file forms part of each playlist in the second list.

US Pat. No. 10,484,312

METHOD AND DEVICE FOR COMMUNICATION IN A COMMUNICATIONS NETWORK

Telefonaktiebolaget LM Er...

10. A user equipment for communicating with a base station in a communications network, the user equipment being configured to communicate with the base station according to a selectable of at least two user equipment categories, the user equipment comprising:a selecting unit configured to:
select one of the at least two user equipment categories when information indicating the one of the at least two user equipment categories is received from the base station;
a determining unit configured to determine a soft buffer size of a soft buffer comprised in the user equipment according to the selected user equipment category;
a communicating unit configured to communicate with the base station according to the selected user equipment category and applying the determined soft buffer size; and
wherein the determining unit is further configured to determine that the soft buffer size is based on a transmission mode, and wherein the user equipment is configured with the transmission mode for a downlink communication from the base station to the user equipment.

US Pat. No. 10,484,292

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, INFORMATION PROCESSING SYSTEM, AND STORAGE MEDIUM WITH CONTROL PROGRAM STORED THEREON

NINTENDO CO., LTD., Kyot...

1. An information processing apparatus comprising:radio circuitry configured to wirelessly transmit and receive a packet through synchronous communication to and from another apparatus; and
a processor configured to:
determine whether the packet transmitted from the radio circuitry has been received by the another apparatus, and
select, when reception of a previously transmitted packet by the another apparatus is not confirmed, between retransmission processing for retransmitting the previously transmitted packet and non-retransmission processing for transmitting another packet instead of the previously transmitted packet, the selection depending on a content of the previously transmitted packet, wherein:
the packet transmitted from the radio circuitry contains first sequence information having a value varied in accordance with prescribed rules each time the packet is transmitted or received, and second sequence information having a value incremented each time data is transmitted, wherein the second sequence information is longer in data length than the first sequence information,
the processor is configured to determine whether the packet transmitted from the radio circuitry has been received by the another apparatus based on the first sequence information, and
the first sequence information having the value that has been varied in accordance with the prescribed rules is provided to a packet to be transmitted in the retransmission processing and/or the non-retransmission processing.

US Pat. No. 10,484,288

NETWORK FLOW CONTROL

Level 3 Communications, L...

1. A method of optimizing network traffic flow for a content delivery network (CDN), comprising:assigning a first network flow parameter for a first application requesting content from the CDN from one or more user devices in communication with the CDN, the first network flow parameter establishing one or more quality of service criteria for a transmission of the requested content associated with providing content to the first application;
receiving a request for content at a content server of the CDN from a requesting device, the request received from the first application executing on the requesting device and comprising a host name associated with the first application;
applying the first network flow parameter for transmitting the requested content to the requesting device in response to the host name associated with the first application;
transmitting, at a first rate, the requested content to the requesting device with the first network flow parameters applied to the transmission of the requested content associated with providing content to the first application;
receiving an indication that the requested content may be transmitted to the application at a second rate that is higher than the first rate;
altering the first network flow parameter to deliver the requested content at a third rate that is between the first rate and the second rate; and
altering, after a period of time, the first network flow parameter to deliver the requested content at the second rate.

US Pat. No. 10,484,275

MULTILAYERED DISTRIBUTED ROUTER ARCHITECTURE

1. A system comprising:a control plane subsystem; and
a plurality of data plane subsystems configured to forward data packets, the plurality of data plane subsystems including a first data plane subsystem and a second data plane subsystem;
wherein the control plane subsystem comprises a processor and a memory storing instructions that, when executed by the processor, cause the processor to perform operations comprising:
receiving an instruction;
determining an action based upon the instruction;
communicating, using a control channel, the action to be performed to the first data plane subsystem and the second data plane subsystem;
wherein the first data plane subsystem is a software data plane subsystem that comprises a processor and a memory storing instructions that, when executed by the processor, cause the processor to perform processing corresponding to the action; and
wherein the second data plane subsystem is a hardware data plane subsystem comprising forwarding hardware and is configured to perform processing corresponding to the action.

US Pat. No. 10,484,245

SELECTIVE INACTIVATION OF CONTROL RULES PARAMETERS

Telefonaktiebolaget LM Er...

1. A method for modifying a control rule for a service or application in a Policy and Charging Control, PCC, architecture, the method executed by a control server and comprising the steps of:determining a first control rule for a service or application, both hereinafter indistinctly referred to as the service, wherein the first control rule comprises a plurality of parameters to be used for enforcement of the first control rule for the service;
submitting the first control rule to an enforcing device;
upon determining that a particular parameter, amongst the plurality of parameters, is no longer applicable for the first control rule, determining a modified control rule that includes a removal indicator indicating the particular parameter to be removed for the first control rule previously submitted; and
submitting the modified control rule to the enforcing device.

US Pat. No. 10,484,242

DYNAMIC CLOUD STACK CONFIGURATION

Bank of America Corporati...

1. A dynamic cloud stack configuration system comprising:a cloud network comprising a plurality of cloud components;
a cloud stack server communicatively coupled to the cloud network, the cloud stack server comprising:
an interface operable to receive a cloud stack request from a user device, wherein the cloud stack request identifies user preferences associated with an operation of a cloud stack; and
a memory operable to store a plurality of historic cloud stack configurations, wherein each of the plurality of historic cloud stack configurations is associated with one or more functionality parameters;
a cloud stack configuration engine implemented by a processor operably coupled to the memory and the interface, and configured to:
identify one or more cloud components associated with the user preferences, wherein identifying the one or more cloud components comprises comparing the user preferences with features of the one or more cloud components;
determine the one or more cloud components are compatible with each other;
determine a cloud stack configuration that incorporates the one or more cloud components in response to determining that the one or more cloud components are compatible with each other;
determine whether the cloud stack configuration is an optimal cloud stack configuration by analyzing the historic cloud stack configurations;
in response to determining that the cloud stack configuration is an optimal cloud stack configuration, construct the cloud stack configuration by including the one or more cloud components that are determined to be compatible with each other and that meet the user preferences, and by excluding any cloud components that are determined to be incompatible with a remainder of the cloud stack configuration; and
implement the cloud stack configuration at the user device.

US Pat. No. 10,484,229

PAM RECEPTION CIRCUIT AND RECEPTION APPARATUS

FUJITSU LIMITED, Kawasak...

1. A PAM reception circuit comprising:a first comparison circuit that outputs a first bit value in two-bit values based on a result of a comparison between a reception signal of pulse amplitude modulation 4 in which the two-bit values are associated with four potential levels divided by three threshold values by gray codes and a first threshold value which is a center of the three threshold values;
an absolute value circuit that outputs an absolute value of a difference between the reception signal and the first threshold value or a negative value obtained by inverting a sign of the absolute value from a positive sign to a negative sign; and
a second comparison circuit that outputs a second bit value in the two-bit values based on a result of a comparison between a second threshold value which is larger than the first threshold value in the three threshold values and the absolute value or a result of a comparison between a third threshold value which is smaller than the first threshold value in the three threshold values and the negative value.

US Pat. No. 10,484,221

METHOD AND APPARATUS FOR GENERATING/TRANSMITTING A FRAME FOR WIRELESS COMMUNICATION, AND SYNCHRONIZATION ESTIMATION METHOD FOR WIRELESS COMMUNICATION

ELECTRONICS AND TELECOMMU...

1. A method of generating a frame for communication, the method comprising:generating, by a processor, a modified sequence using a base sequence, the modified sequence corresponding to a complex conjugate of the base sequence, each of the base sequence and the modified sequence including a plurality of elements;
allocating, by the processor, the plurality of elements of the base sequence and the plurality of elements of the modified sequence into a first time period of the frame; and
allocating, by the processor, information for automatic gain control or signal detection into a second time period of the frame,
wherein the plurality of elements of the base sequence and the plurality of elements of the modified sequence are allocated into a frequency domain in the first time period,
wherein the second time period is located before the first time period in the frame, and
wherein the base sequence and the modified sequence include a plurality of symbols mapping complex coordinates.

US Pat. No. 10,484,190

MANAGING CHANNELS IN AN OPEN DATA ECOSYSTEM

SATORI WORLDWIDE, LLC, P...

1. A method, comprising:providing one or more graphical user interfaces to a first user of an open data ecosystem, wherein:
the open data ecosystem comprises a plurality of public channels and a plurality of private channels; and
users of the open data ecosystem are able to receive messages on each of the plurality of public channels;
receiving first user input indicating channel configuration information from the first user via the one or more graphical user interfaces; and
configuring, by a computer processing device, one or more channels of the plurality of public channels or the plurality of private channels based on the channel configuration information received from the first user via the one or more graphical user interfaces.

US Pat. No. 10,484,186

CASCADING MULTIVARIATE QUADRATIC IDENTIFICATION SCHEMES FOR CHAIN OF TRUST

Intel Corporation, Santa...

1. A system comprising:at least one hardware processor to execute instructions;
at least one non-transitory storage medium including instructions that when executed by the processor enable the system to generate a respective public/private key pair for each component of a plurality of components of a computing environment using a multivariate quadratic function F, determine a first commitment value and a second commitment value for a first component of the plurality of components in the first component using a public key of a respective public/private key pair for a previous component, including to determine at least one of the first and second commitment values for the first component using a polar function G, wherein the polar function G is a polar form of the multivariate quadratic function F, provide the first commitment value, the second commitment value and the public key of the respective public/private key pair for the previous component to a verifier in response to a challenge from the verifier, and add the first component to a chain of trust for the computing environment if the first commitment value is equal to a first expected commitment value and the second commitment value is equal to a second expected commitment value.

US Pat. No. 10,484,179

DATA CONSISTENCY IN AN ENCRYPTED REPLICATION ENVIRONMENT

EMC IP Holding Company LL...

1. A computer-executable method for testing data consistency in a replicated data storage environment, wherein the replicated data storage environment includes data storage systems at a production site and a target site, wherein the target site is located within a cloud storage provider and each of the data storage systems includes one or more processors and memory, the computer-executable method comprising: receiving a request for a data consistency check of encrypted data stored at the second data storage system at the target site; retrieving replicated signatures from the second data storage system at the target site, wherein the replicated signatures are based on encrypted data stored at the second data storage system, wherein the encrypted data is data that was encrypted with a production encryption key maintained only at the production site; retrieving production signatures from a first data storage system from the production site, wherein retrieving production signatures comprises: encrypting data from the first data storage system at the production site using the production encryption key maintained only at the production site; and creating the production signatures based on the encrypted data from the production site; and determining data consistency based on an analysis of the replicated signatures and the production signatures, wherein, to accurately verify consistency between the replicated signatures and the production signatures, the production encryption key maintained only at the production site is used for to encrypt both the encrypted data from the first data storage system and the encrypted data stored at the second data storage system.

US Pat. No. 10,484,174

PROTECTING AN ENCRYPTION KEY FOR DATA STORED IN A STORAGE SYSTEM THAT INCLUDES A PLURALITY OF STORAGE DEVICES

Pure Storage, Inc., Moun...

1. A method of protecting an encryption key for data stored in a storage system that includes a plurality of storage devices, the method comprising:reading, from a majority of each of the storage devices, a portion of an apartment key, wherein the portion of the apartment key is stored in an unlocked portion of the majority of each of the storage devices, and wherein a main portion of the majority of each of the storage devices is locked;
reconstructing the apartment key using portions of the apartment key read from the majority of each of the storage devices;
unlocking the main portion of the majority of each of the storage devices by utilizing the apartment key;
reading, from a main portion of a majority of one of the storage devices, a third-party resource access key;
requesting, from third-party resource utilizing the third-party resource access key, the encryption key for data stored on the storage devices;
receiving, from the third-party resource, the encryption key for data stored on the storage devices; and
decrypting the data stored on the storage devices by utilizing the encryption key.

US Pat. No. 10,484,166

RECEIVER

DENSO CORPORATION, Kariy...

1. A receiver comprising:an A/D converter that performs an analog digital conversion to an input signal;
an equalizer that equalizes an output of the A/D converter, eliminates an inter-code interference and obtains a data output;
a timing recovery part that generates a recovery clock by using the data output of the equalizer;
a detector that detects a timing when the input signal varies from a non-signal state and has reached a predetermined threshold; and
an initial phase setting part that sets as an initial phase of the recovery clock from the timing recovery part, a timing when a predetermined time has elapsed after the timing detected by the detector, wherein:
the timing recovery part includes a phase lock loop that outputs a reference clock and a divider that divides the reference clock of the phase lock loop; and
when the recovery clock is generated, the phase lock loop outputs the reference clock, with the initial phase of the recovery clock set by the initial phase setting part as a start, the divider starts to divide the frequency of the reference clock, generates dual-phase clocks and generates the recovery clock corresponding to the dual-phase clocks, and wherein
the detector includes a comparator arranged in parallel with the A/D converter;
the detector detects the timing that has reached the threshold by the comparator and obtains a output signal; and
the initial phase setting part includes a delay circuit that delays outputs the output signal to the timing recovery part with a delay of the output signal of the comparator for a predetermined time, and obtains the initial phase of the recovery clock.

US Pat. No. 10,484,163

MEASURE AND IMPROVE CLOCK SYNCHRONIZATION USING COMBINATION OF TRANSPARENT AND BOUNDARY CLOCKS

CISCO TECHNOLOGY, INC., ...

1. A network time synchronization management system comprising:a computing device in communication with a communication network comprising a slave node coupled to a working master node through at least one boundary node, the computing device comprising at least one non-transitory computer readable medium comprising instructions stored thereon that when executed are effective to cause at least one processor to:
receive a request to synchronize the slave node with the working master node;
establish a first communication session between the boundary node and the slave node, the first communication session configured to measure a first timing delay from the boundary node to the slave node;
establish a second communication session between the working master node and the slave node through the boundary node, the second communication session configured to measure a second timing delay from the working master node to the slave node;
adjust a timing delay correction factor according to the first timing delay and the second timing delay; and
synchronize the slave node with the working master node according to the adjusted timing delay correction factor;
wherein the first and second communications sessions are different from each other.

US Pat. No. 10,484,148

METHOD AND DEVICE FOR TRANSMITTING AND RECEIVING MULTIMEDIA DATA

Samsung Electronics Co., ...

1. A method of receiving multimedia data in a hybrid network system, the method comprising:receiving, by a transceiver, multimedia data from a broadcast server;
identifying lost data in the multimedia data;
determining, by at least one processor, whether reconstruction of the lost data is possible through an application layer forward error correction (AL-FEC) based on the lost data;
when the reconstruction of the multimedia data is not possible through the AL-FEC while receiving the multimedia data from the broadcast server, requesting, by the at least one processor to a broadband server, an automatic repeat request (ARQ) for a retransmission of the lost data in the multimedia data through an intermediate node of a network in the hybrid network system while receiving the multimedia data from the broadcast server;
receiving, by the transceiver from the broadband server, retransmitted data corresponding to the lost data that is retransmitted based on the ARQ; and
reconstructing the lost data based on the retransmitted data.

US Pat. No. 10,484,130

METHOD AND DEVICE FOR PARALLEL POLAR CODE ENCODING/DECODING

Huawei Technologies Co., ...

1. A method for polar code encoding, the method comprising:transmitting at least a first segment of information bits over a first set of sub-channels; and
transmitting at least a second segment of information bits and a masked parity bit over a second set of sub-channels, wherein a value of the masked parity bit is equal to a bitwise combination of a first parity bit computed from the first segment of information bits and a second parity bit computed from the second segment of information bits, the second set of sub-channels being different than the first set of sub-channels.

US Pat. No. 10,484,126

CSI REPORT FOR MTC OPERATION

Telefonaktiebolaget LM Er...

1. A method in a wireless device of reporting a narrowband channel quality indicator (CQI), the method comprising:receiving, in a wireless network comprising a carrier bandwidth of a first number of physical resource blocks (PRBs), a physical channel comprising a plurality of narrowband PRB sets, each narrowband PRB set of the plurality of narrowband PRB sets comprising a bandwidth of a second number of PRBs, wherein the bandwidth of the second number of PRBs is less than the bandwidth of the first number of PRBs, and wherein each narrowband PRB set of the plurality of narrowband PRB sets comprises different time and frequency resources than the other narrowband PRB sets of the plurality of narrowband PRB sets and receiving the physical channel comprises receiving the physical channel via frequency hopping between the plurality of narrowband PRB sets;
determining a CQI that indicates a modulation and code rate of the physical channel that may be used to transmit the physical channel with a transport block error probability not exceeding 0.1 when the physical channel is transmitted in the plurality of narrowband PRB sets in a subframe and at least part of the transport block is transmitted in the subframe; and
transmitting a report to a network node, the report comprising the determined CQI for frequency hopping between the plurality of narrowband PRB sets and wherein the report is formatted according to one of a long term evolution (LTE) transmission mode 1, 2 and 6 reporting format.

US Pat. No. 10,484,117

POLARIZATION FILTER SYSTEMS AND METHODS

LATTICE SEMICONDUCTOR COR...

1. A device comprising:a first transceiver module of a wireless communication system configured to faun one or more linearly polarized communication links with a second transceiver module of the wireless communication system; and
a dual channel polarization filter structure positioned between the first and second transceiver modules and configured to filter the one or more linearly polarized communication links to produce corresponding one or more filtered linearly polarized communication links;
wherein the dual channel polarization filter structure comprises first and second filter channels each formed from three structural layers including at least one metalized layer disposed between the remaining two structural layers, and wherein each filter channel comprises an array of filter elements each comprising at least one metamaterial absorber arrangement.

US Pat. No. 10,484,108

TRANSMITTER IMAGE CALIBRATION USING PHASE SHIFT ESTIMATION

Futurewei Technologies, I...

1. An apparatus, comprising:a transmitter in-phase/quadrature mismatch correction circuit configured to receive an in-phase/quadrature signal and transmitter correction coefficients and generate a corrected in-phase/quadrature signal based on the transmitter correction coefficients to reduce an amount of in-phase/quadrature mismatch in the received in-phase/quadrature signal;
a transmission circuit configured to receive the corrected in-phase/quadrature signal and to generate therefrom a transmission signal;
a measurement receiver circuit configured to receive the transmission signal and to generate therefrom a measured in-phase/quadrature signal;
a measurement receiver in-phase/quadrature mismatch correction circuit configured to receive the measured in-phase/quadrature signal and receiver correction coefficients and generate a corrected measured in-phase/quadrature signal based on the receiver correction coefficients to reduce an amount of in-phase/quadrature mismatch in the measured in-phase/quadrature signal; and
an in-phase/quadrature mismatch estimation circuit configured to receive the corrected measured in-phase/quadrature signal, estimate a phase in the corrected measured in-phase/quadrature signal and generate the transmitter correction coefficients and receiver correction coefficients from the estimated phase.

US Pat. No. 10,484,060

METHOD AND DEVICE FOR TRANSMITTING AND RECEIVING CHANNEL STATE INFORMATION IN MOBILE COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method for transmitting channel state information by a user equipment (UE) in a mobile communication system, the method comprising:receiving, from a base station, a higher layer signaling message comprising information indicating a reporting mode for the channel state information and information related to a codebook subset configuration indicating subsampling a master codebook for use in reporting the channel state information;
determining whether to apply codebook subsampling to the master codebook based on the codebook subset configuration and the reporting mode, wherein the master codebook is defined as a set of precoding matrices shared by the UE and the base station;
upon determining to apply the codebook subsampling to the master codebook, generating a subsampled codebook by subsampling the master codebook and generating the channel state information comprising a first precoding matrix indicator (PMI) indicating a precoding matrix selected from the subsampled codebook;
when a plurality of feedback components are permitted to be simultaneously transmitted, further generating the channel state information further comprising a second PMI generated by assuming a particular codebook subset configuration which does not require subsampling and neglecting the codebook subset configuration made by the higher layer signaling; and
transmitting the channel state information to the base station.

US Pat. No. 10,484,052

METHOD AND DEVICE FOR TRANSMITTING ELECTRICAL POWER AND/OR SIGNALS BETWEEN A WALL AND A LEAF PIVOTABLE RELATIVE THERETO

1. A device for transmitting at least one of electrical power and signals between a wall and a leaf which is mounted so as to pivot on the wall, the device comprising:a transmission device which comprises,
a device for detecting a magnetic field strength in surroundings of the transmission device, the device for detecting a magnetic field strength comprising a magnetic field sensor which is designed as at least one of a reed switch and a Hall sensor,
a coil arrangement arranged on a side of the wall, and
a coil arrangement arranged on a side of the leaf;
a coil arrangement comprising a coil housing and a coil winding; and
an electrical circuit arrangement comprising a board,
wherein,
the magnetic field sensor is arranged on the board,
the board is arranged on an outer side of the coil housing,
the board comprises a transmission and/or receiving unit of an opto-electronic signal transmission device, and
the opto-electronic signal transmission device is provided as a part of a control loop for controlling power which is applied to the coil winding on the side of the wall which based on a power requirement of the side of the leaf.

US Pat. No. 10,484,046

SYSTEMS AND METHODS FOR A TWISTED PAIR TRANSCEIVER WITH CORRELATION DETECTION

Marvell International Ltd...

1. A method for transmitting data on an Ethernet link between a first device compatible with a first Ethernet transmission protocol and a second device compatible with a second Ethernet transmission protocol, the method comprising:selecting a third baud rate to be a common factor of both a first baud rate specified in the first Ethernet transmission protocol and a second baud rate specified in the second Ethernet transmission protocol;
receiving, at the first device and from the second device, one or more encoded data symbols at the third baud rate;
determining a clock division factor based on the first baud rate and the third baud rate;
sampling, at the first device, the one or more encoded data symbols using a divided clock signal based on the clock division factor; and
generating, from the sampling, a number of samples representing at least one data symbol, wherein the number equals a result of the first baud rate divided by the common factor.

US Pat. No. 10,484,040

APPARATUS AND METHOD FOR CANCELLING SELF-INTERFERENCE SIGNAL IN COMMUNICATION SYSTEM SUPPORTING FULL-DUPLEX SCHEME

Samsung Electronics Co., ...

1. A method for cancelling a self-interference (SI) signal in a communication system supporting a full-duplex scheme, the method comprising:estimating an SI channel;
performing a pre-filtering operation on a transmission signal based on the estimated SI channel;
generating copied-SI signals based on the estimated SI channel and the pre-filtered transmission signal; and
cancelling an SI signal based on the copied-SI signals,
wherein the pre-filtering operation includes an operation for decreasing a number of SI signals, and
wherein the performing of the pre-filtering operation on the transmission signal based on the estimated SI channel comprises:
acquiring a pre-filter which is time reverse for the estimated SI channel and is a complex conjugate, and
filtering the transmission signal based on the acquired pre-filter.

US Pat. No. 10,484,008

MEMORY SYSTEM WITH ON-THE-FLY ERROR DETECTION AND TERMINATION AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A decoding method, comprising:calculating cyclic redundancy check (CRC) parity bits for data on-the-fly while the data is decoded using low-density parity-check (LDPC) decoding, the calculating of CRC parity bits being performed at each of a plurality of iterations of the LDPC decoding before the LDPC decoding is complete;
updating the calculated CRC parity bits to generate CRC parity bits after each iteration of the LDPC decoding;
comparing the generated CRC parity bits with CRC bits included in the data to determine whether the generated CRC parity bits match the CRC bits in the data; and
terminating the LDPC decoding when the comparing indicates that the generated CRC parity bits match the CRC bits in the data.

US Pat. No. 10,484,000

ANALOG-TO-DIGITAL CONVERTERS

IMEC vzw, Leuven (BE)

1. A successive approximation register (SAR) analog-to-digital architecture comprising:at least one digital-to-analog converter (DAC) configured so as to receive an analog input signal and at least one digital code and generate an output signal therefrom;
at least one comparator configured so as to receive the output signal from the at least one DAC at a first input, and provide a bit output based at least in part on a comparison between at least one reference signal and the output signal received from the at least one DAC; and
a logic circuit configured so as to provide a first digital code to the at least one DAC and subsequent digital codes in response to the bit output from a preceding comparison step, control the operation of the at least one comparator, receive the bit output from the at least one comparator, and generate an output signal;
wherein the at least one DAC comprises a first DAC and a second DAC, the first and second DACs arranged in parallel and configured so as to receive the analog input signal and digital code, the first and second DACs together with the at least one comparator forming respective first and second paths, the first path being configured for deriving odd bits in the digital code and the second path being configured for deriving even bits in the digital code;
and wherein the first DAC is further configured so as to perform feedback steps for derived bits of the digital code while the at least one comparator performs comparison steps for even bits of the digital code, and the second DAC is further configured so as to perform feedback steps for derived bits of the digital code while the at least one comparator performs comparison steps for odd bits of the digital code.

US Pat. No. 10,483,990

FREQUENCY COMPENSATOR, ELECTRONIC DEVICE AND FREQUENCY COMPENSATION METHOD

BOE TECHNOLOGY GROUP CO.,...

1. A frequency compensator, comprising:a control circuit configured to generate a frequency control word according to an initial frequency and a target frequency; and
a frequency compensation circuit is configured to:
receive an input signal of the initial frequency; and
generate and output an output signal of a compensated frequency according to the frequency control word and the input signal of the initial frequency,
wherein the control circuit comprises:
an input sub-circuit configured to obtain the initial frequency, the target frequency, and a frequency multiplication parameter;
a calculation sub-circuit configured to generate the frequency control word according to the initial frequency, the target frequency, and the frequency multiplication parameter; and
an output sub-circuit configured to output the frequency control word to the frequency compensation circuit.

US Pat. No. 10,483,984

TEMPERATURE COMPENSATED OSCILLATION CONTROLLER AND TEMPERATURE COMPENSATED CRYSTAL OSCILLATOR INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A temperature compensated oscillation controller comprising:a temperature compensation circuit configured to provide a reference voltage through a first terminal and to receive an input voltage including temperature information through a second terminal; and
an oscillation circuit configured to he connected to an external crystal resonator through third and fourth terminals and to output a clock signal in response to an oscillation signal from the external crystal resonator,
wherein the temperature compensation circuit is configured to perform a voltage controlled oscillator-based sensing operation to convert the input voltage into a temperature code and to adjust a frequency of the clock signal using the temperature code, and
wherein the temperature compensation circuit comprises:
a bandgap reference configured to generate the reference voltage;
a temperature sensing circuit configured to receive the input voltage and to generate the temperature code in response to the receives input voltage;
a control logic circuit configured to output a control signal using the temperature code; and
a capacitor bank configured to adjust a capacitance of each of the third and fourth terminals in response to the control signal.

US Pat. No. 10,483,976

CIRCUITS TO INTERPRET PIN INPUTS

TEXAS INSTRUMENTS INCORPO...

1. An apparatus comprising:a pin;
an input buffer coupled to the pin;
a first current mirror coupled to the input buffer, the first current mirror comprising three transistors, each of the three transistors in the first current mirror coupling to a different one of three legs of the apparatus;
a second current mirror coupled to the input buffer, the second current mirror comprising three transistors, each of the three transistors in the second current mirror coupling to a different one of the three legs of the apparatus;
multiple level shifters positioned in a common leg of the three legs;
a voltage divider circuit coupled to the multiple level shifters;
a first output buffer coupled to the input buffer and the first current mirror; and
a second output buffer coupled to the input buffer and the second current mirror.

US Pat. No. 10,483,961

CHARGE INJECTOR WITH INTEGRATED LEVEL SHIFTER FOR LOCALIZED MITIGATION OF SUPPLY VOLTAGE DROOP

Intel Corporation, Santa...

1. An apparatus comprising:a first power supply rail to provide a first power supply voltage;
a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage;
a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first power supply voltage, wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication, wherein the first circuitry comprises a level-shifter with an asymmetric input pair circuitry, and wherein the asymmetric input pair circuitry is to turn on the first circuitry faster than turning the first circuitry off; and
a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.

US Pat. No. 10,483,956

PHASE INTERPOLATOR, TIMING GENERATOR, AND SEMICONDUCTOR INTEGRATED CIRCUIT

ROHM CO., LTD., Ukyo-Ku,...

1. A semiconductor integrated circuit comprising:a set signal generator structured to generate a set signal; and
a reset signal generator structured to generate a reset signal,
wherein at least one from among the set signal generator and the reset signal generator comprises a timing generator, the timing generator comprising N (N?2) stages,
wherein an i-th (1?i?N?1) stage comprises a first phase interpolator and a second phase interpolator,
wherein an output node of the first phase interpolator in the i-th (1?i?N?1) stage is coupled to a first input node of each of the first phase interpolator and the second interpolator in the (i+1)-th stage,
wherein an output node of the second phase interpolator in the i-th stage is coupled to a second input node of each of the first phase interpolator and the second interpolator in the (i+1)-th stage,
wherein the first phase interpolator and the second phase interpolator are each arranged such that a first signal is received via the first input node and such that a second signal is received via the second input node, and structured to generate an output signal having an edge at a timing that corresponds to control data,
and wherein the first phase interpolator and the second phase interpolator each comprise a phase interpolator, the phase interpolator comprising:
a first input node coupled to receive a first signal that transits from a first level to a second level;
a second input node coupled to receive a second signal that transits from the first level to the second level with a delay with respect to the first signal;
a first line coupled to receive a first voltage;
a second line coupled to receive a second voltage;
an intermediate line;
a capacitor having one end coupled to the intermediate line;
an initializing circuit structured to initialize a voltage across the capacitor during a period in which the first signal and the second signal are both set to the first level;
a plurality of circuit units that correspond to a plurality of bits of an input code, and coupled in parallel between the intermediate line and the second line; and
an output circuit structured to generate an output signal having a level that changes when the voltage across the capacitor crosses a predetermined threshold value,
wherein each circuit unit comprises:
a resistor and a first path arranged in series between the intermediate line and the second line; and
a second path arranged in parallel with the first path,
wherein the first path is structured such that, when the first signal is set to the second level and the corresponding bit of the input code is set to a first value, the first path is turned on,
wherein the second path is structured such that, when the second signal is set to the second level and the corresponding bit of the input code is set to a second value, the second path is turned on,
and wherein the semiconductor integrated circuit is structured to output a pulse signal that transits to a first level according to an output signal of the set signal generator, and that transits to a second level according to an output signal of the reset signal generator.

US Pat. No. 10,483,955

FEEDBACK SYSTEM AND METHOD OF OPERATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A lock signal generation circuit, comprising:an input signal control circuit configured to receive an input signal and two reference signals and output state signals and a code signal for controlling a level of the input signal, the state signals representing a result of comparison of the input signal with the two reference signals, wherein the state signals include an up/down signal and an ambiguous signal;
a pre-lock signal generator configured to receive the up/down signal, and to output a pre-lock signal to determine a time at which the level of the input signal is to be fixed in response to the up/down signal, wherein the up/down signal represents whether the input signal has a higher or lower level than the two reference signals; and
a signal-processing circuit configured to receive the pre-lock signal and the ambiguous signal, and to output a lock signal to fix the level of the input signal using the ambiguous signal and the pre-lock signal, wherein the ambiguous signal is outputted when the level of the input signal is in between levels of the two reference signals.

US Pat. No. 10,483,951

TECHNIQUES FOR DETECTING AND CORRECTING ERRORS ON A RING OSCILLATOR

Altera Corporation, San ...

1. A circuit comprising:a ring oscillator circuit comprising inverting logic circuits coupled in a loop, wherein the inverting logic circuits comprise first, second, and third output nodes;
a first error detection circuit comprising a first register circuit, wherein a first input of the first register circuit is coupled to the first output node, and wherein a second input of the first register circuit is coupled to the third output node; and
a second error detection circuit comprising a second register circuit, wherein a first input of the second register circuit is coupled to the second output node, and wherein a second input of the second register circuit is coupled to the third output node,
wherein the first or second error detection circuit resets a signal that has passed through the inverting logic circuits in response to detecting an error event in the signal from one of the first, second, or third output nodes.

US Pat. No. 10,483,940

HIGH-PERFORMANCE CONVERSION BETWEEN SINGLE-ENDED AND DIFFERENTIAL/COMMON-MODE SIGNALS

Maxlinear Israel LTD, (I...

10. A Radio Frequency Integrated Circuit (RFIC), comprising:a semiconductor substrate; and
a signal conversion unit, which is fabricated on the semiconductor substrate the signal conversion unit comprising:
a first splitter configured to convert a radio frequency (RF) input signal into a first output signal and a second output signal, wherein the first output signal is out of phase with the second output signal, and wherein the first splitter is configured to convert a first input signal and a second input signal into an RF output signal;
a second splitter configured to convert a local oscillator (LO) input signal into a third output signal and a fourth output signal, wherein the third output signal is in phase with the fourth output signal, and wherein the second splitter is configured to convert a third input signal and a fourth input signal into an LO output signal;
a first passive circuit coupled to the first splitter and configured to add a first delay to the first output signal and the second output signal to produce a delayed first output signal at a first output port and a delayed second output signal at a second output port, wherein the first delay is configured according to a frequency band comprising the LO input signal; and
a second passive circuit coupled to the second splitter and configured to add a second delay to the third output signal and the fourth output signal to produce a delayed third output signal together with the delayed first output signal at the first output port and a delayed fourth output signal together with the delayed second output signal at the second output port, wherein the second delay is configured according to a frequency band comprising the RF input signal.

US Pat. No. 10,483,906

PHOTOVOLTAIC SOLAR CONVERSION

Orenko Limited, Cambridg...

1. A photovoltaic solar conversion apparatus comprising:a plurality of photovoltaic chips arranged to convert sunlight into electrical energy;
a plurality of coupling devices operable to secure a plurality of optical fibers in a configuration with a light transmission end-face arranged to couple sunlight transported by the optical fibers onto photosensitive surfaces of the photovoltaic chips;
a carrier which supports the photovoltaic chips, with each of the coupling devices being arranged to couple sunlight transported by a respective one or more of the optical fibers to a corresponding photovoltaic chip; and
a rack having a horizontally disposed rack mounting, wherein the coupling devices are fixedly mounted on the rack with respect to the rack mounting, and the carrier is movably mounted in alignment with the coupling devices with respect to the rack mounting for ease of replacement.

US Pat. No. 10,483,902

SYSTEM AND METHOD FOR REDUCING CURRENT HARMONIC DISTORTION IN A MOTOR CONTROLLER

Rockwell Automation Techn...

1. A system for reducing current harmonic distortion in a motor controller, wherein the motor controller is operative to control operation of a multi-phase motor, the system comprising:at least two inputs, each input configured to receive a feedback signal corresponding to a current present in one phase of the motor;
a reference frame transformer operative to convert the feedback signals from the at least two inputs to a first synchronous current feedback signal and a second synchronous current feedback signal, wherein the first synchronous current feedback signal is at a fundamental frequency and the second synchronous current feedback signal is at a harmonic frequency;
a first current regulator configured to receive a current reference signal and the first synchronous current feedback signal as inputs and to generate a first regulator output signal corresponding to desired operation of the motor at the fundamental frequency; and
a second current regulator configured to receive the second synchronous current feedback signal as an input and to generate a second regulator output signal at the harmonic frequency, wherein the motor controller is operative to sum the first regulator output signal and the second regulator output signal to generate a modified current regulator output signal.

US Pat. No. 10,483,896

METHOD FOR RELIABLE CONTROL OF HIGH ROTOR POLE SWITCHED RELUCTANCE MACHINE

Software Motor Company, ...

1. A sensorless reliable control system for a high rotor pole switched reluctance machine (HRSRM) utilizing a hybrid combination of self-inductance and mutual inductance values, the reliable control system comprising:a stator phase energizing module to excite at least one of a plurality of stator phases each having a winding, wherein each of the windings of the rest of the plurality of stator phases is in an open circuit state;
a first current and time measuring module to measure a first current value through the at least one energized stator phase and time taken by the first current value to reach a first peak value of current;
a self-inductance determining module to determine a self-inductance value for the at least one energized stator phase;
a first storage module to store the self-inductance value and the first current value for each of the plurality of stator phases;
a second current and time measuring module to measure a second current value through an adjacent un-energized stator phase and time taken by the adjacent un-energized stator phase to reach a second peak value of current, wherein the winding of the adjacent un-energized stator phase is in an open circuit state;
a mutual-inductance determining module to determine a mutual inductance value between the at least one energized stator phase and the adjacent un-energized stator phase;
a second storage module to store the mutual inductance value and the second current value for each of the plurality of stator phases;
a rotor position estimation module to estimate a rotor position utilizing the hybrid combination of the stored self-inductance and mutual inductance values; and
a control module to control the HRSRM based on the estimated rotor position;
whereby the system determines a highly accurate angular position of the rotor from the hybrid combination of self-inductance and mutual inductance values and controls the HRSRM and thus eliminates the need for shaft position sensors.

US Pat. No. 10,483,891

DOUBLE STATOR PERMANENT MAGNET MACHINE WITH MAGNETIC FLUX REGULATION

HAMILTON SUNDSTRAND CORPO...

1. A permanent magnet (PM) dynamoelectric machine with directly controllable PM flux control comprising:a drive shaft;
a PM rotor assembly with multiple PMs arranged annularly around an outer periphery of the PM rotor assembly;
a first stator assembly comprising a ferromagnetic stator yoke, a first plurality ferromagnetic stator teeth mounted to the stator core with distal ends proximate the outer axial periphery of the rotor assembly separated by a first air gap and a first plurality of stator coils mounted between the stator teeth of the first plurality of stator teeth; and
a second stator assembly comprising a second ferromagnetic stator yoke, a second plurality of ferromagnetic stator teeth mounted to the stator core with distal ends proximate an inner periphery of the rotor assembly separated by a second air gap and at least one control coil, the at least one control coil wrapped about a saturable region of each the second plurality of stator teeth;
wherein each saturable region of the second plurality of stator teeth is operable as a magnetic diverter to divert air gap magnetic flux (?g) generated by the multiple PMs across the second air gap through the distal ends of the second plurality of stator teeth.

US Pat. No. 10,483,885

METHODS AND APPARATUS FOR ROTATION DETECTION OF A BRUSHED DC MOTOR

SEMICONDUCTOR COMPONENTS ...

1. A detection circuit connected to a brushed DC motor, comprising:a differential amplifier configured to detect a current of the brushed DC motor and generate an analog signal that is proportional to the current;
an analog-to-digital converter (ADC) connected to the differential amplifier and configured to convert the analog signal to a first digital signal; and
a digital circuit connected to the ADC and comprising:
a difference circuit configured to:
receive the first digital signal; and
compute a second digital signal, wherein the second digital signal is the difference of the first digital signal and a previous first digital signal;
an absolute value circuit connected to the difference circuit and configured to compute an absolute value of the second digital signal; and
a comparator circuit connected to the absolute value circuit and configured to:
compare the computed absolute value with a predetermined threshold value; and
generate a comparator output according to the comparison.

US Pat. No. 10,483,872

POWER SUPPLY SYSTEM AND ENERGY STORAGE SYSTEM

GENERAL ELECTRIC COMPANY,...

1. A power supply system, comprising:an auxiliary power supply output terminal for providing an auxiliary power supply;
a first energy storage device;
a first converter comprising a first switch and a second switch which are series-connected, wherein the first converter is coupled to the first energy storage device;
a first transformer that transforms a high voltage from the first energy storage device into a low voltage output from the auxiliary power supply output terminal and comprising a primary winding and a secondary winding, wherein the primary winding of the first transformer is connected between the first energy storage device and a connecting point of the first and the second switches, and a first terminal of the secondary winding of the first transformer is connected to the auxiliary power supply output terminal via a first diode and an opposite terminal thereof is grounded; and
a first capacitor, wherein one terminal of the first capacitor is connected to a negative electrode of the first diode and the other terminal thereof is grounded.

US Pat. No. 10,483,858

SYSTEM AND METHOD FOR STARTING UP A HIGH DENSITY ISOLATED DC-TO-DC POWER CONVERTER

ABB SCHWEIZ AG, Baden (C...

1. A DC-to-DC power converter comprising:a transformer comprising a primary side and a secondary side;
a primary circuit electrically coupled to the primary side of the transformer, the primary circuit comprising (i) at least one gate driver, (ii) a bias voltage generator, and (iii) a primary microcontroller electrically coupled to the bias voltage generator and configured to receive a first bias voltage supplied by the bias voltage generator, the primary microcontroller configured to provide a first energizing signal to the at least one gate driver in response to the first bias voltage; and
a secondary circuit electrically coupled to the secondary side of the transformer, the secondary circuit comprising a secondary microcontroller communicatively coupled to the primary microcontroller, the secondary microcontroller configured to receive a second bias voltage caused by the first energizing signal, the secondary microcontroller further configured to provide, in response to the second bias voltage, a second energizing signal to the at least one gate driver in response to the second bias voltage, the secondary microcontroller further configured to provide, in response to the second bias voltage, an instruction to the primary microcontroller that causes the primary microcontroller to relinquish control of the primary circuit to the secondary microcontroller.

US Pat. No. 10,483,853

DC-DC CONVERTER

TOYOTA JIDOSHA KABUSHIKI ...

1. A DC-DC converter, comprising:a high potential input wiring connected to a positive electrode of a direct current source;
a high potential output wiring;
a low potential wiring connected to a negative electrode of the direct current source;
a first lower FET of n-channel type, a source of the first lower FET being connected to the low potential wiring;
a first upper FET of n-channel type, a source of the first upper FET being connected to a drain of the first lower FET, and a drain of the first upper FET being connected to the high potential output wiring;
a second lower FET of n-channel type, a source of the second lower FET being connected to the low potential wiring;
a second upper FET of n-channel type, a source of the second upper FET being connected to a drain of the second lower FET, and a drain of the second upper FET being connected to the high potential output wiring;
a first diode, an anode of the first diode being connected to the source of the first upper FET, and a cathode of the first diode being connected to the drain of the first upper FET;
a second diode, an anode of the second diode being connected to the source of the second upper FET, and a cathode of the second diode being connected to the drain of the second upper FET;
a main reactor comprising a first terminal and a second terminal, the first terminal being connected to the high potential input wiring;
a first sub-reactor, one end of the first sub-reactor being connected to the second terminal of the main reactor, and other end of the first sub-reactor being connected to the drain of the first lower FET;
a second sub-reactor, one end of the second sub-reactor being connected to the second terminal of the main reactor, and other end of the second sub-reactor being connected to the drain of the second lower FET; and
a gate controller connected to a gate of the first lower FET, a gate of the first upper FET, a gate of the second lower FET, and a gate of the second upper FET, wherein
the gate controller is configured to perform a first operation and a second operation based on a variable current flowing through the main reactor,
the gate controller is configured to perform the first operation during a zero-cross mode in which the variable current decreases to zero, and to perform the second operation during a non-zero-cross mode in which the variable current does not decrease to zero,
in the first operation, the gate controller controls the first lower FET, the first upper FET, the second lower FET, and the second upper FET so as to satisfy following conditions:
a first state, a second state, a third state, and a fourth state repeatedly appear in this order, the first state being a state in which the first lower FET is on, the second state being a state in which the first lower FET and the second lower FET are off, the third state being a state in which the second lower FET is on, and the fourth state being a state in which the first lower FET and the second lower FET are off; and
the first upper FET and the second upper FET are not turned on,
in the second operation, the gate controller controls the first lower FET, the first upper FET, the second lower FET, and the second upper FET so as to satisfy following conditions:
a fifth state, a sixth state, a seventh state, and an eighth state repeatedly appear in this order, the fifth state being a state in which the first lower FET is on and the second lower FET is off, the sixth state being a state in which the first lower FET and the second lower FET are off, the seventh state being a state in which the first lower FET is off and the second lower FET is on, and the eighth state being a state in which the first lower FET and the second lower FET are off; and
the first upper FET is turned on in at least a part of a period of the sixth state, and the second upper FET is turned on in at least a part of a period of the eighth state.

US Pat. No. 10,483,852

CONTROL METHOD FOR CONTROLLING A POWER CONVERTER CIRCUIT AND RESPECTIVE POWER CONVERTER CIRCUIT

1. A control method for controlling a power converter circuit, the method comprising the steps of:providing said power converter circuit comprising at least one inductive element storing an output energy, a charging switch for charging the inductive element, a releasing switch for releasing the stored output energy from the inductive element and for charging the inductive element with a compensation energy and an output capacitor saving the released output energy, wherein the compensation energy is used to achieve a minimized voltage switching condition when switching on the charging switch; and
adjusting a turn on time of the releasing switch by a closed-loop control of a compensation control variable measured in the power converter circuit or of a characteristic value derived from this compensation control variable, wherein the compensation control variable is derived on basis of a differential voltage detected across an auxiliary winding in the power converter circuit.

US Pat. No. 10,483,831

PERMANENT MAGNET APPLYING MOTOR

PHOENIX INVENT, INC., (K...

1. A permanent magnet applying motor comprising:a first rotating plate and a second rotating plate having through-holes formed at central portions of the first rotating plate and the second rotating plate, the first rotating plate and the second rotating plate having a plurality of insertion grooves formed at the ends of the first rotating plate and the second rotating plate;
a rotary shaft passing through a central portion of the first rotating plate and a central portion of the second rotating plate;
a plurality of rotors arranged between the first rotating plate and the second rotating plate at regular intervals with respect to the rotary shaft and each including a permanent magnet and a penetration shaft passing through the permanent magnet;
a plurality of planetary gears connected in pairs to the plurality of rotors, respectively;
a center gear connected to one end of the rotary shaft and engaged with all the plurality of planetary gears;
a rotating plate support including a first support and a second support connected to opposite ends of the rotary shaft, respectively;
a stator support including a third support which has a first stator formed in the third support and includes a permanent magnet as a component and a fourth support which has a second stator which is the same as the first stator, the third support and the fourth support being spaced apart from each other with respect to the rotary shaft;
one or more deadlock point detecting sensors provided on one side of the rotating plate support; and
one or more electromagnet portions provided on one side of the stator support.

US Pat. No. 10,483,826

THERMODYNAMIC SYSTEM FOR STORING/PRODUCING ELECTRICAL ENERGY

BOREALES ENERGY, (FR)

1. A system for producing and storing electrical energy, comprising a thermally insulated chamber containing a first closed circuitry in which circulates a first working fluid, a hot source through which a first leg of the first circuitry passes for a heat exchange between the first working fluid and the hot source, a cold source through which a second leg of the first circuitry passes for a heat exchange between the first working fluid and the cold source, the hot and cold sources being thermally insulated from each other, the first circuitry further comprising third and fourth legs connecting in series the first and second legs, the third leg comprising a first member for circulating the first working fluid in liquid phase and the fourth leg comprising a second member for circulating the first working fluid in gas phase, wherein the hot source is composed of a pure water ice slurry always at 0° C., the cold source is composed of an ice slurry with a temperature lower than or equal to ?40° C. and the system for producing/storing electrical energy further comprises a second circuitry for circulating a second working fluid between the hot source and a constant temperature system outside the thermally insulated chamber, the constant temperature system being selected from the group comprising ambient air, a water reserve, a water stream, a water course, a waterway, wherein the second working fluid is circulated between said constant temperature system and the hot source by an auxiliary expansion valve and an auxiliary compressor, and is caused to exchange heat with the constant temperature system and the hot source; and,wherein the system further comprises an intermediate temperature source at an intermediate temperature between the temperature of the hot source and the temperature of the cold source, and comprises an intermediate fluid circuitry carrying an intermediate working fluid, said intermediate fluid circuitry passing through and exchanging heat with the hot source, the cold source, and the intermediate temperature source, the intermediate temperature source being connected to the intermediate fluid circuitry in parallel to the hot source, by a first sub-leg equipped with a first compressor and a second sub-leg equipped with an first expansion valve, and the intermediate temperature source being connected to the intermediate fluid circuitry in parallel to the cold source, by a third sub-leg equipped with a second compressor and a fourth sub-leg equipped with an second expansion valve.

US Pat. No. 10,483,811

STATOR HAVING ADAPTED TOOTH GEOMETRY WITH TEETH HAVING CIRCUMFERENTIAL PROJECTIONS

1. A stator of an electric motor, having teeth distributed in a circumferential direction and extending in a radial direction, and grooves respectively provided between the teeth, wherein respectively adjacent teeth each form a groove opening at the radial outer edge sections of said teeth, and the radial outer edge sections of the teeth each have a projection extending into the groove opening in the circumferential direction and each forming a free contact surface directed radially inward, wherein a contact surface width in the circumferential direction corresponds to a projection width (b) in the circumferential direction, anda ratio b/a of the projection width (b) in the circumferential direction to a groove opening width (a) in the circumferential direction is in a range of 0.1-0.15 and a ratio b/c of the projection width (b) in the circumferential direction to a projection thickness (c) in the radial direction is in a range of 0.5-1.0,
wherein, in an axial top view, each respective projection has a rectangular cross section,
wherein the grooves have an insulating overmold made of plastic, which covers at least one inner wall surface of the grooves and the radially inward directed free contact surface of the projection.

US Pat. No. 10,483,802

PEAK VOLTAGE DETECTION IN A DIFFERENTIALLY DRIVEN WIRELESS RESONANT TRANSMITTER

Texas Instruments Incorpo...

1. A wireless power circuit comprising:(a) a series resonant circuit including a primary capacitor and an inductor coupled in series, the primary capacitor having first and second terminals and the inductor having first and second terminals, a first terminal of the inductor being coupled to a second terminal of the primary capacitor;
(b) a first half-bridge circuit having a terminal coupled to the first terminal of the capacitor;
(c) a second half-bridge circuit having a terminal coupled to the second terminal of the inductor;
(d) a summing circuit having a first summing terminal coupled to the first terminal of the inductor, a second summing terminal coupled to the second terminal of the inductor, and a center node terminal; and
(e) a peek-to-peek voltage detector having an input coupled to the center node terminal of the summing circuit and having a voltage detector output.

US Pat. No. 10,483,800

PORTABLE DEVICE, CHARGING DEVICE FOR SAME, AND CHARGING SYSTEM FOR PORTABLE DEVICE

NITTO DENKO CORPORATION, ...

1. A portable device, comprising:an outer wall member exposed to outside; and
a power-receiving module at least partially arranged along a surface shape of the outer wall member, which receives power supplied by means of a resonance phenomenon, the power-receiving module including a power-receiving resonance coil having an outer circumferential side and an inner circumferential side opposite the outer circumferential side;
an electronic device disposed in a magnetic field space formed by the resonance phenomenon and having a magnetic field strength weaker than that in nearby portions, the magnetic field space being located within a space defined by the power-receiving resonance coil on the inner circumferential side of the power-receiving resonance coil; and
a magnetic member disposed between the electronic device and the power-receiving resonance coil and covering an inner circumferential surface of the power-receiving resonance coil, the magnetic member configured to reduce a magnetic field generated on the inner circumferential side of the power-receiving resonance coil.

US Pat. No. 10,483,784

WEARABLE, ACTIVITY-TRACKING SEX TOY, AND A METHOD FOR ITS USE

1. A method for tracking sexual movements, the method comprising:detecting, by at least one motion sensor incorporated in a sex toy, at least one motion of the sex toy;
calculating, by a processor coupled to a wireless communicator incorporated in the sex toy, at least one body movement of a user of the sex toy, based on the at least one motion of the sex toy;
determining, by the wireless communicator, a connection state to at least one computing device;
storing, by the processor, in a memory incorporated in the sex toy, the at least one body movement, based on the detected connection state.

US Pat. No. 10,483,783

SYSTEM AND METHOD FOR IDENTIFYING A WIRELESSLY CHARGING BATTERY

MOTOROLA SOLUTIONS, INC.,...

8. A system for selecting a battery pack of a plurality of battery packs being wirelessly charged, the system comprising:a wireless charger including
a power supply,
a plurality of charging coils, each charging coil coupled to the power supply and configured to wirelessly charge the battery pack of the plurality of battery packs using power received via the power supply, and
a wireless communication circuit forming a communication link with each battery pack; and
an optimal battery selection device
having battery information related to the plurality of battery packs including information received from the plurality of battery packs via the wireless communication circuit the battery information including a battery type and a charge level for each battery pack of the plurality of battery packs, and
configured to:
detect a battery pack request indicating a request to select a replacement battery pack from the plurality of battery packs being wirelessly charged,
determine a compatible battery pack type based on the request,
identify compatible battery packs of the plurality of battery packs based on the battery types of the plurality of battery packs and the compatible battery pack type,
identify one of the compatible battery packs as an optimal replacement battery pack by comparing the charge levels of the compatible battery packs,
and
provide a human recognizable notification indicative of the optimal replacement battery pack.

US Pat. No. 10,483,781

ELECTRICALLY HEATED AEROSOL-GENERATING SYSTEM

PHILIP MORRIS PRODUCTS S....

1. A method of controlling an electrical system, the electrical system comprising a primary charging device comprising a first rechargeable power supply, and a portable device comprising a second rechargeable power supply, the method comprising:monitoring an ambient temperature adjacent the primary charging device;
determining a charging current, for charging the first rechargeable power supply of the primary charging device, in dependence on the ambient temperature; and
charging the first rechargeable power supply of the primary charging device at the determined charging current,
wherein:
when the ambient temperature is within a first predetermined temperature range, the charging current is less than about 0.1 C,
when the ambient temperature is within a second predetermined temperature range, the charging current is greater than about 0.1 C, and
when the ambient temperature is above a predetermined temperature, preventing the charging of the first rechargeable power supply.

US Pat. No. 10,483,775

PRIVACY CHARGING STATION FOR ELECTRONIC DEVICES

1. A charging station, comprising:a container configured to house at least one electrical device within an internal space within said container;
at least one electrical outlet disposed within said container, said at least one electrical outlet configured to provide power to the at least one electrical device; and
a noise generator located within said internal space within said container, wherein the noise generator is configured to supply masking noise while the at least one electrical device is resident within said internal space.

US Pat. No. 10,483,762

POWER TRANSMISSION NETWORK

GENERAL ELECTRIC TECHNOLO...

1. A power transmission network comprising:an AC electrical network connected to a point of common coupling, the AC electrical network having a voltage, the point of common coupling being connectable to a further electrical device; and
a processing circuit comprising a phase locked loop, the processing circuit configured to receive and process a voltage of the point of common coupling to determine a phase difference between the voltages of the AC electrical network and the point of common coupling during an exchange of power between the AC electrical network and the point of common coupling, the phase locked loop comprising:
a phase detector,
a loop filter, an output of the loop filter being configured to provide a phase difference signal corresponding to the phase difference;
a first voltage controlled oscillator; and
a second voltage controlled oscillator configured to lock the phases of the voltages of the AC electrical network and the point of common coupling prior to the exchange of power between the AC electrical network and the point of common coupling;
wherein the phase locked loop is configured to switch between the first voltage controlled oscillator and second voltage controlled oscillator.

US Pat. No. 10,483,759

INTEGRATED MULTI-MODE LARGE-SCALE ELECTRIC POWER SUPPORT SYSTEM FOR AN ELECTRICAL GRID

ALENCON ACQUISITION CO., ...

1. An integrated multi-mode, large-scale electric power support system for providing an on demand electrical power from a renewable energy source comprising a renewable solar energy source or a renewable wind energy source and at least one stored energy source to an electrical grid or an on demand reactive power delivery to or absorption from the electrical grid, the integrated multi-mode, large-scale electric power support system comprising:a multi-mode controller for controlling a selection of each one of a plurality of system configurations for the integrated multi-mode, large-scale electric power support system responsive to a system mode request from the electrical grid;
a photovoltaic power station or a wind farm having a DC power capacity of supplying a minimum of 2,500 kW from a plurality of solar renewable energy string circuits or a plurality of wind renewable energy turbine power electronic blocks connected to a renewable energy DC power bus as a supply of a renewable energy DC current, each of the plurality of solar renewable energy string circuits comprising a plurality of photovoltaic modules and each of the plurality of wind renewable energy turbine power electronic blocks comprising a wind turbine and a wind turbine controller connected to an optimizer input of a renewable energy power optimizer, and an optimizer output of the renewable energy power optimizer connected to the renewable energy DC power bus, the optimizer output having a galvanic isolation with the optimizer input;
a plurality of system power modules, each of the plurality of system power modules comprising:
an at least one system stored energy DC power module, each of the at least one system stored energy DC power modules comprising:
an at least one stored energy DC power source selectively connectable to a power module DC BUS by a stored DC power source switching device controlled by the multi-mode controller for alternatively charging of the at least one stored energy DC power source or a supply of a stored energy DC current from the at least one stored energy DC power source dependent upon the selection of each one of the plurality of system configurations;
a current controller module having a controller input connected across the power module DC BUS and a controller output connected across the power module DC BUS;
a renewable energy switching device for selectively connecting the renewable energy DC power bus to the power module DC BUS dependent upon the selection of each one of the plurality of system configurations;
an inverter/charge module comprising an AC three phase solid state inverter with an inverter gating control circuit for each one of a plurality of solid state switching devices in the AC three phase solid state inverter, the AC three phase solid state inverter having an inverter/charge DC input alternatively connectable to the power module DC BUS in an inverter polarity or a charge circuit reversed polarity dependent upon the selection of each one of the plurality of system configurations, and an inverter/charge AC three phase output producing a three phase AC output currents in each one of a plurality of AC three phase solid state inverters in the plurality of system power modules; and
an inverter or charge circuit switching device for selectively connecting the controller output to the inverter polarity or the charge circuit reversed polarity dependent upon the selection of each one of the plurality of system configurations; and
a phase shifting transformation network having a transformation multi-phase output connected to the inverter/charge AC three phase output in each of the plurality of system power modules and a transformation multi-phase input connected to the electrical grid having a three phase grid voltage;
whereby the inverter/charge AC three phase output of the AC three phase solid state inverter in each one of the plurality of system power supply modules operates synchronously with the three phase grid voltage when: at least either the supply of the renewable energy DC current or the supply of the stored energy DC current is processed by the current controller module for a grid delivery of the supply of the renewable or the stored energy DC current; or a reactive power is absorbed from the electrical grid or supplied to the electrical grid, and a commutation of the plurality of solid state switching devices in each one of the plurality of AC three phase solid state inverters is sequenced to produce the three phase AC output currents from each one of the plurality of AC three phase solid state inverters and the phase shifting transformation network for phase shifting the three phase AC output currents from all of the plurality of AC three phase solid state inverters to produce a three phase AC grid-injected currents with waveforms having a decreased total harmonic distortion as the number of the plurality of AC three phase solid state inverters is increased.

US Pat. No. 10,483,742

CABLE/LEAD INSERTION UNIT

Eaton Intelligent Power L...

1. A cable/lead insertion unit for inserting and passing through at least one lead into and through a wall opening of a housing wall, comprising:an insertion sleeve for insertion into the wall opening,
a bearing flange protruding radially outwards from the insertion sleeve,
a clamp part configured to be screwed onto the insertion sleeve in the direction of the bearing flange, and
a locking plate including a safety dog insertable into a locking opening in the housing wall,
wherein the insertion sleeve includes a fastening portion situated opposite the clamp part,
wherein the fastening portion comprises a single partially circumferential thread turn, by which a clamping element can be brought into engagement for pressing the bearing flange onto a rim of the wall opening,
wherein the locking plate is configured to be fitted onto the insertion sleeve between the clamping element and the housing wall.

US Pat. No. 10,483,733

JOINT STRIP

1. A device for bridging a gap between a first rigid object and a second rigid object, the device comprising:a. a center trunk having an upper section and a lower section, the lower section comprising a first tapered terminal end, the upper section comprising a second tapered terminal end, the center trunk having a first tapered side and a second tapered side, the first and second tapered sides being on opposing sides of the center trunk and extend linearly upwardly and outwardly from the first tapered terminal end to the second tapered terminal end such that the center trunk has a tapered profile;
b. a recess shaped and positioned to receive at least a portion of opposing sides of the first rigid object, the recess defined at least in part by a first upper flange that extends directly from the second tapered terminal end of the center trunk, the first tapered side of the center trunk, and a lower flange that extends upwardly directly from the first tapered terminal end of the lower section of the center trunk to a tip of the lower flange, and wherein the device has a rest configuration prior to both receipt of the first rigid object in the recess and placement of the device in the gap at which the first upper flange and the lower flange each extend directly from the center trunk at a generally converging angle towards the other of the first upper flange and the lower flange; and
c. a second upper flange directly extending from the second tapered terminal end of the center trunk,
wherein the first tapered terminal end includes a trailing protrusion that extends, at least when the device is at the rest position, a distance outwardly and downwardly from the center trunk to create a resistance against the second rigid object when the opposing sides of the first rigid object are located within the recess and the center trunk is moved up or down within the gap such that the device is capable of installation after the first rigid object and the second rigid object are coupled together, the trailing protrusion and the lower flange extending from opposing sides of the center trunk at the first terminal end,
wherein the device has a first width between a top surface of the device above the second tapered terminal end of the center trunk and a bottom surface at the first tapered terminal end of the center trunk that is greater than a second width of the device between a top surface of the first upper flange and an outer surface of the lower flange at the tip of the lower flange.

US Pat. No. 10,483,732

MULTILAYER CONTAINMENT AND PROTECTION TUBE FOR CONDUITS, CABLES AND THE LIKE

TUBIGOMMA DEREGIBUS S.R.L...

1. A multilayer containment and protection tube for conduits, cables and the like, comprisingan inner layer made of polytetrafluoroethylene PTFE, which is electrically at least antistatic, with a smooth internal surface, which forms a duct for supporting conduits or cables,
one or more intermediate layers of electrically at least antistatic reinforcement,
an outer layer made of electrically at least antistatic polymeric material, and
a covering and finishing layer, which is electrically at least antistatic, wherein said covering and finishing layer is made of thermoplastic material, wherein said thermoplastic material of said covering and finishing layer is ultrahigh molecular weight polyethylene UHMWPE, and wherein said covering and finishing layer has a substantially smooth and glossy external surface.

US Pat. No. 10,483,718

ULTRA-LOW NOISE, HIGHLY STABLE SINGLE-MODE OPERATION, HIGH POWER, BRAGG GRATING BASED SEMICONDUCTOR LASER

Morton Photonics, Inc., ...

1. A laser comprising:a semiconductor gain chip to generate light; and
a waveguide external cavity having a first end and a second end and including an integrated Bragg grating to reflect at least a portion of the light
wherein a first end of the gain chip has a high reflectivity facet forming a first end of a laser cavity; a second end of the gain chip has a low reflectivity facet, allowing light generated from the gain chip to be coupled to the first end of the waveguide external cavity,
wherein the physical length of the Bragg grating is greater than 20 mm and occupies at least 75% of the physical length of the waveguide external cavity.

US Pat. No. 10,483,716

PHOTONIC DEVICE COMPRISING A LASER OPTICALLY CONNECTED TO A SILICON WAVE GUIDE AND METHOD OF FABRICATING SUCH A PHOTONIC DEVICE

1. Photonic device comprising:a support,
an intermediate layer in contact with the support and comprising at least one dielectric material and a first and second excess thickness of silicon, the first and second excess thicknesses of silicon being separated from each other by a space,
a first silicon layer in contact with the intermediate layer opposite the support, the first silicon layer comprising at least part of the thickness of a waveguide, and first to fifth waveguide sections distinct from the waveguide, the first to the fifth waveguide sections succeeding each other and being optically connected to the waveguide by at least either the first or the fifth waveguide section, the second, the fourth and the third waveguide sections facing the first and second excess thicknesses and the space, respectively,
a first dielectric layer covering the first silicon layer opposite the intermediate layer,
a gain structure comprising at least one gain medium capable of emitting light, the gain structure having a central portion facing the space and a first and a second end facing the first and the second excess thicknesses, thus the central portion of the gain structure with the space and the third waveguide section forms a hybrid laser waveguide, the second and the fourth waveguide sections, the first and the second excess thicknesses of silicon and the first and the second ends of the gain structure forming a first and a second optical transition zone of an optical mode between the hybrid laser waveguide and the first and fifth waveguide sections respectively,
a feedback structure to form an oscillating cavity comprising at least part of the gain medium so as to form a laser optically connected to the waveguide by at least either the first or the fifth waveguide section.

US Pat. No. 10,483,710

MULTILAYER ELECTRODE ASSEMBLY

AUROMA TECHNOLOGIES, CO.,...

1. A multilayer electrode assembly comprising:a first dielectric material having an exterior surface and an interior surface, wherein the first dielectric material is shaped so as to form a channel defined by the interior surface; and
a layered structure comprising:
a first metal layer disposed adjacent to a first portion of the exterior surface of the first dielectric material; and
a second metal layer disposed adjacent to a second portion of the exterior surface of the first dielectric material, wherein the first metal layer is disposed in a first spaced relationship with the second metal layer in the layered structure;
wherein an electric field is generated in the channel of the first dielectric material when a voltage is applied to the multilayer electrode assembly by a drive electrode.

US Pat. No. 10,483,708

ENDOSCOPE HAVING A ROTATABLE ELECTRIC CONNECTING ELEMENT

SCHOLLY FIBEROPTIC GMBH, ...

1. An endoscope (1) comprising:two functional units (2a, 2b) which are rotatable in relation to each other about a common axis of rotation (8);
an electric connecting element (3) by which the two functional units (2a, 2b) are electrically connected or connectable to one another, the connecting element (3) includes a flexible portion (4) that is placed into a winding (7),
the connecting element (3) has a first rigid portion (5) and a second rigid portion (6), and the flexible portion (4) is a central flexible portion (4) that connects the first rigid portion (5) and the second rigid portion (6) to each other, and
at least one of the first rigid portion (5) or the second rigid portion (6) protrudes over the central flexible portion (4) in a direction of the axis of rotation (8), and the first rigid portion (5) and the second rigid portion (6) overlap only in a region of the central flexible portion (4).

US Pat. No. 10,483,704

CABLE WITH MULTIPLE ELECTRICAL CONNECTORS

Kurt Solland, Goodyear, ...

1. A cable for connecting various devices, the cable comprising:a first connector and a second connector, a cord connecting the first connector to the second connector;
the first connector including a body and a plug head;
the body having a first end connected to the cord and an opposite second end;
the body being u-shaped and including a first prong and a second prong;
the first prong including a first set of electrical contacts and the second prong including a second set of electrical contacts;
the plug head including a plug head and a first plug and a second plug;
the first plug being secured to the plug head and the second plug being secured to the plug head, the first plug being located on an opposite side of the plug head from the second plug;
the plug head having a third set of electrical contacts electrically connected to the first plug and a fourth set of electrical contacts electrically connected to the second plug;
the plug head being rotatably secured between the first prong and the second prong of the body;
wherein, in a first position, the first set of electrical contacts and the second set of electrical contacts align with and electrically connect to the third set of electrical contacts; and
wherein, in a second position, the first set of electrical contacts and the second set of electrical contacts align with and electrically connect to the fourth set of electrical contacts.

US Pat. No. 10,483,678

VEHICLE ELECTRICAL CONNECTOR

Ford Global Technologies,...

1. An electrical connector, comprising:a base member disposed on an exterior portion of a vehicle;
a port disposed within a surface of the base member;
a wireless transceiver disposed within the vehicle; and
a controller configured to selectively activate the port based on an authentication of an electronic device, wherein the controller activates the port when the electronic device is authenticated within the vehicle and further wherein the controller is associated with the wireless transceiver and is configured to store information about one or more authenticated electronic devices.

US Pat. No. 10,483,649

METHODS AND APPARATUS FOR ENHANCED RADIATION CHARACTERISTICS FROM ANTENNAS AND RELATED COMPONENTS

Fractal Antenna Systems, ...

1. An aperture engine array comprising:one or more aperture engine panels, wherein each aperture engine panel includes
an antenna layer configured to receive and/or transmit radiofrequency energy (RF) over a range of frequencies, wherein the antenna layer is substantially lacunar so as to allow incident radiation to pass through to an adjacent layer;
a solar cell layer including a panel of solar cells configured to absorb incident radiation and provide power, wherein the solar cell layer is operative as a power source for the transmission and/or reception of RF energy; and
a backplane layer, at least a portion of which contains a surface reflective to RF energy.

US Pat. No. 10,483,644

EIGHT-FREQUENCY BAND ANTENNA

TAOGLAS GROUP HOLDINGS LI...

1. An eight-frequency band antenna, comprising:a carrier comprising a front face, a top face, a back face and a bottom face, the carrier having a plurality of blind holes defined on the front face and forming a recess into the carrier and at least one rib between two adjacent blind holes; a high-frequency segment arranged on the front face, the top face, the back face, and the bottom face of the carrier comprising a straight shaped radiator, a winding radiator, a double-t shaped radiator, a first L-shaped radiator with a long side parallel to the winding radiator along two faces of the carrier, and a second L-shaped radiator; and a low-frequency segment adjacent the high-frequency segment arranged on the front face, the top face, the back face and the bottom face of the carrier; and
a printed circuit board comprising a top side, a left slanting side, a slanting bottom side, and a right long side, a recessed side, and a right short side, with a first face and a second face, the first face having a first ground metal face, a micro strip and an open area with two fixed ends, the micro strip having a front section and a rear section, wherein the front section extends into the first ground metal face such that a gap is defined between the micro strip and the first ground metal faces and comprises a through hole.

US Pat. No. 10,483,643

SMALL ANTENNA AND CALCULATION APPARATUS

DENSO CORPORATION, Kariy...

1. A small antenna comprising:a first element that includes a pair of conductors provided by a wire, one end portion of each of the pair of conductors being a power feeding point; and
a second element that is arranged to face the first element with sandwiching a dielectric body, and includes a conductor provided by a wire, wherein:
a part of the wire of each of the first element and the second element has an inductance shape with three or more bending structures or an inductance shape with a spiral structure;
a first resonance mode, in which a current direction of current flowing through the first element is same as a current direction of current flowing through the second element, has a first resonant frequency (Fa0);
a second resonance mode, in which the current direction of current flowing through the first element is opposite to the current direction of current flowing through the second element, has a second resonant frequency (Fb0); and
a length from each power feeding point to the inductance shape is determined to hold the first resonant frequency of the first resonance mode within a range from a frequency slightly higher than the second resonant frequency of the second resonance mode to a high anti-resonant frequency of the second resonance mode, or a range from a frequency slightly lower than the second resonant frequency of the second resonance mode to a low anti-resonant frequency of the resonance mode.

US Pat. No. 10,483,638

ANTENNA REFLECTOR INTERCHANGE MECHANISM

MACDONALD, DETTWILER AND ...

1. An interchange mechanism for deploying at least one reflector for reconfiguration of an antenna, said interchange mechanism comprising:a rotary actuator having a fixed section for mounting on a structure of the antenna, and a mobile section rotating relative to the fixed section about a rotation axis;
at least one carrier for supporting the at least one reflector, the at least one carrier freely rotatably mounting on the fixed section for rotation about the rotation axis between a first angular position and a second angular position; and
an arm mounted on the mobile section and carrying a carrier engaging mechanism successively and releasably engaging the at least one carrier and displacing the at least one carrier from the first angular position to the second angular position when the arm and the mobile section rotate in a first direction;wherein the carrier engaging mechanism is a latching mechanism successively latching to the at least one carrier at the first angular position and unlatching from the at least one carrier at the second angular position.

US Pat. No. 10,483,623

ANTENNA DEVICE AND ELECTRONIC APPARATUS

Murata Manufacturing Co.,...

1. An antenna device comprising:a planar metallic member; and
an antenna coil that is wound into a loop or a spiral,
wherein the metallic member has an opening whose entire periphery is surrounded by a metal,
wherein the antenna coil is disposed on a side of one principal surface of the metallic member such that both of an inner region and an outer region of the antenna coil overlap the opening in a plan view that is in a direction perpendicular to a plane defined by the side of the one principal surface of the metallic member, and
wherein a magnetic sheet is provided on a side of the antenna coil that is opposite to the metallic member.

US Pat. No. 10,483,622

ANTENNA STRUCTURE AND WIRELESS COMMUNICATION DEVICE USING SAME

Chiun Mai Communication S...

1. An antenna structure comprising:a metal housing, the metal housing comprising a front frame, a backboard, and a side frame, the side frame being positioned between the front frame and the backboard; wherein the side frame defines a slot, the front frame defines a groove, the groove is positioned between two ends of the slot, communicates with the slot, and extends to cut across the front frame, a first portion of the front frame positioned at a first side of the groove forms a first branch; a second portion of the front frame extending from a second side of the groove to one end of the slot forms a second branch;
a switching circuit; and
a first feed source;
wherein the first feed source is electrically connected to the first branch and the second branch, and the first branch is grounded through the switching circuit;
wherein the first feed source is further electrically connected to the first branch and the second branch through a connecting portion, the side frame comprises an end portion, a first side portion, and a second side portion, the first side portion and the second side portion are respectively connected to two ends of the end portion; the connecting portion comprises a first connecting section, a second connecting section, a third connecting section, and a fourth connecting section; one end of the first connecting section is electrically connected to the first feed source and another end of the first connecting section extends along a direction parallel to the end portion towards the first side portion; one end of the second connecting section is perpendicularly connected to the end of the first connecting section away from the first feed source and another end of the second connecting section extends along a direction parallel to the first side portion towards the end portion until the second connecting section connects to the portion of the first branch adjacent to the groove; one end of the third connecting section is connected to a junction of the first connecting section and the first feed source and another end of the third connecting section extends along a direction parallel to the second connecting section away from the end portion; one end of the fourth connecting section is perpendicularly connected to the end of the third connecting section away from the first feed source and another end of the fourth connecting section extends along a direction parallel to the first connecting section towards the second side portion until the fourth connecting section connects to the second branch.

US Pat. No. 10,483,613

TELESCOPIC ANTENNA MAST

Maverick Inc., Fremont, ...

1. An antenna system, comprisinga base section;
a plurality of movable antenna sections adapted to fit inside of the base section, each movable antenna section including an outside section and an inside section, wherein the outside section has a plurality of threaded section locks penetrating through threads on the inside and outside sections to extend at least 0.5 inch beyond the inside section to prevent the inside section from collapsing into the outside section in an extended mode; and
a lock pin centrally positioned between the section locks to receive an actuator to extend the antenna section.

US Pat. No. 10,483,605

BATTERY COOLING SYSTEM FOR VEHICLE

Hyundai Motor Company, S...

1. A battery cooling system for a vehicle, comprising:a battery module supplying drive energy to the vehicle;
a liquid supply unit supplying liquid to the battery module; and
an injection unit configured such that a first side thereof is connected to the liquid supply unit to be supplied with liquid from the liquid supply unit and a second side thereof is adjacent to the battery module to supply the liquid supplied from the liquid supply unit to an outer surface of the battery module, thereby cooling the battery module by using latent heat of evaporation of the liquid,
wherein a vehicle body is provided with an induction tube configured to collect liquid outside the vehicle and supply the same to the liquid supply unit, such that the liquid supply unit is constantly filled with liquid to cool the battery module without the liquid being separately supplied to the liquid supply unit.

US Pat. No. 10,483,587

SULFIDE SOLID ELECTROLYTE

IDEMITSU KOSAN CO., LTD.,...

1. A sulfide solid electrolyte, comprising lithium, phosphorus, sulfur, and two or more of elements X selected from the group consisting of halogen elements,wherein the sulfide solid electrolyte comprises an argyrodite-type crystal structure, and
wherein a molar ratio of the sulfur to the phosphorus, b (S/P), and a molar ratio of the elements X to the phosphorus, c (X/P), satisfy formula (1):
0.23

US Pat. No. 10,483,586

ALL-SOLID-STATE BATTERY USING SODIUM ION INTERCALATION CATHODE WITH LI/NA EXCHANGING LAYER

TOYOTA MOTOR EUROPE, Bru...

1. An all-solid-state battery comprising the following elements in order:a positive electrode active material layer (5) comprising a sodium-containing cathode material;
a solid electrolyte layer (4) comprising a sulfide-based sodium-containing solid electrolyte material;
a sulfide-based mixture layer (3);
a solid electrolyte layer (2) comprising a sulfide-based lithium-containing solid electrolyte material;
a negative electrode active material layer (1) comprising a lithium-containing anode material,
wherein the mixture layer (3) comprises a physical mixture of a sulfide-based sodium-containing solid electrolyte material and a sulfide-based lithium-containing solid electrolyte material.

US Pat. No. 10,483,573

FUEL CELL UNIT FOR USE IN AGGREGATING MULTIPLE FUEL CELLS IN PARALLEL

LG FUEL CELL SYSTEMS INC....

1. A fuel cell unit configured to connect to a positive load rail and a negative load rail, suitable for being one of a number of fuel cells connected in parallel to the positive load rail and the negative load rail, the fuel cell unit comprising a fuel cell, having a fuel cell output voltage presented between a positive fuel cell output terminal and a negative fuel cell output terminal, and a regulating voltage converter having a DC converter output voltage presented across a positive converter output terminal and a negative converter output terminal and an input configured to be driven;the regulating voltage converter being arranged so that the input is driven by the fuel cell output voltage in series with the converter output voltage; and
the converter output voltage combines with the fuel cell output voltage such that the voltage across the fuel cell and the regulating voltage converter is the same as the voltage across the positive load rail and negative load rail.

US Pat. No. 10,483,565

FUEL CELL DEVICE, AUTOMOBILE WITH A FUEL CELL DEVICE AND METHOD FOR OPERATING A FUEL CELL DEVICE

HYUNDAI MOTOR COMPANY, S...

1. A fuel cell device for an automobile comprising:a first pipe, wherein the first pipe connects a gas tank to a fuel cell, the gas tank configured to store liquefied gas;
a second pipe having an open end and connected to the fuel cell; and
a pressure regulator,
wherein the fuel cell is arranged to be driven by evaporated liquefied gas from the gas tank, and wherein the pressure regulator is arranged to control the evaporation of the liquefied gas, and
wherein, at a parking mode or an idle mode, the pressure regulator is configured to supply the evaporated liquefied gas from the gas tank to the fuel cell when a pressure of the evaporated liquefied gas in the gas tank is higher than or equal to a predetermined pressure value, and not to supply the evaporated liquefied gas from the gas tank to the fuel cell when the pressure of the evaporated liquefied gas in the gas tank is lower than the predetermined pressure value.

US Pat. No. 10,483,556

FUEL CELL ELECTRODE AND FUEL CELL USING THE SAME

Tsinghua University, Bei...

1. A fuel cell electrode, comprising:a porous metal structure; and
a carbon nanotube structure comprising a plurality of carbon nanotubes, the carbon nanotube structure is fixed on a surface of the porous metal structure, wherein the porous metal structure and the carbon nanotube structure are shrunk together to form a plurality of wrinkled parts.

US Pat. No. 10,483,545

BINDER FOR BATTERY ELECTRODES, AND ELECTRODE AND BATTERY USING SAME

OSAKA SODA CO., LTD., Os...

1. A battery electrode binder comprising a polymer comprising:(I) structural units derived from a hydroxyl group-containing (meth)acrylate monomer (A) represented by the general formula,

wherein R1 is hydrogen or a linear or branched alkyl group having 1 to 4 carbon atoms, R2 and R3 each is hydrogen or a linear or branched alkyl group having 1 to 4 carbon atoms, and n is an integer of 1 to 30,
(II) structural units derived from a polyfunctional (meth) acrylate monomer (B), and
(III) structural units derived from a reactive surface active agent (C) which is at least one selected from a reactive anionic surface active agent, a reactive nonionic surface active agent, a reactive cationic surface active agent and a reactive amphoteric surface active agent,
wherein the reactive nonionic surface active agent is at least one selected from polyoxyalkylene alkenyl ether, polyoxyethylene alkyl propenylphenyl ether and ?-hydro-?-(1-alkoxymethyl-2-(2-propenyloxy)ethoxy)-poly(oxy-1,2-ethanediyl), and
the monomers used in the polymer do not have a carbon-carbon double bond including an aromatic carbon-carbon double bond and a carbon-carbon triple bond, other than ethylenically unsaturated double bonds contained in the (meth)acrylic group.

US Pat. No. 10,483,541

METHOD OF PRODUCING NICKEL-COBALT COMPOSITE HYDROXIDE AND METHOD OF PRODUCING POSITIVE ELECTRODE ACTIVE MATERIAL FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY

NICHIA CORPORATION, Anan...

1. A method of producing a nickel-cobalt composite hydroxide, comprising:preparing a first solution containing nickel ions and cobalt ions;
preparing a second solution containing tungsten ions and having a pH of 10 or more;
preparing a third solution containing a complex ion-forming factor;
preparing a liquid medium having a pH in a range of 10 to 13.5;
supplying a portion of the first solution to the liquid medium to obtain a seed solution;
supplying the first solution, the second solution, and the third solution separately and simultaneously to the seed solution to obtain a reacted solution, the reacted solution having a pH in a range of 10 to 13.5; and
obtaining the nickel-cobalt composite hydroxide containing nickel, cobalt, and tungsten from the reacted solution.

US Pat. No. 10,483,527

CATHODE MATERIAL FOR RECHARGEABLE MAGNESIUM BATTERY AND METHOD FOR PREPARING THE SAME

KOREA INSTITUTE OF SCIENC...

1. A cathode material for a rechargeable magnesium battery, represented by the following Chemical Formula 1:Ag2SxSe1-x  [Chemical Formula 1]
wherein x is a real number and satisfies 0

US Pat. No. 10,483,526

POSITIVE ELECTRODE ACTIVE MATERIAL, NONAQUEOUS ELECTROLYTE BATTERY, AND BATTERY PACK

KABUSHIKI KAISHA TOSHIBA,...

1. A nonaqueous electrolyte battery comprising:a positive electrode comprising a positive electrode active material;
a negative electrode; and
a nonaqueous electrolyte,
wherein the positive electrode active material comprises positive electrode active material primary particles which have an olivine structure, are represented by LiMn1?x?yFexMyPO4 where 0?x?0.5, 0?y?0.2 where M is at least one element selected from the group consisting of Mg, Ni, Co, Sn, and Nb, and satisfy Formula (1) below:
? wherein the positive electrode active material primary particles comprise a surface portion, ? is a ratio of Fe in LiMn1???yFe?MyPO4 which is a composition of the surface portion of the positive electrode active material primary particles, and ? is a ratio of Fe in LiMn1???yFe?MyPO4 which is a composition of a central portion of the positive electrode active material primary particles,
wherein the composition of the surface portion of the positive electrode active material primary particles is a composition of a portion having a thickness of 1 to 10 nm from a surface of a cross section of the positive electrode active material primary particle, and the composition of the central portion of the positive electrode active material primary particles is a composition of a peripheral portion within a range of 1 to 10 nm from a center of gravity of the cross section of the same positive electrode active material primary particle,
wherein an average diameter of the positive electrode active material primary particles is from 0.01 to 1 ?m,
and wherein the negative electrode comprises a negative electrode active material comprising at least one oxide selected from the group consisting of titanium dioxide having a monoclinic system structure and a niobium titanium oxide.

US Pat. No. 10,483,510

POLARIZED BATTERY TRAY FOR A VEHICLE

Shape Corp., Grand Haven...

1. A battery tray for a vehicle, said battery tray comprising:a first tray component having a first panel portion and elongated reinforcement members integrally coupled at opposing edges of the first panel portion and extending in parallel alignment with each other;
a second tray component having a second panel portion and a plurality of cross members integrally extending across the second panel portion;
wherein the second panel portion is disposed at an upper surface of the first panel portion with the plurality of cross members extending between the elongated reinforcement members so as to provide a battery containment area between the plurality of cross members; and
wherein opposing ends of the plurality of cross members directly engage inside surfaces of the elongated reinforcement members to provide the battery containment area with an interior peripheral surface.

US Pat. No. 10,483,509

ENERGY STORAGE APPARATUS, MOVING BODY, AND ENERGY STORAGE SYSTEM

BLUE ENERGY CO., LTD., K...

1. An energy storage apparatus comprising:an energy storage device including a surface having a first end face from which an external terminal protrudes and a second end face on an opposite side from the first end face; and
a retaining member that includes paired end portions disposed on opposite sides of the energy storage device in a second direction orthogonal to a first direction in which the external terminal protrudes and a coupling portion for coupling the paired end portions and that retains the energy storage device,
wherein the coupling portion includes
a main body portion facing the energy storage device in a third direction orthogonal to the first direction and the second direction,
a first extending portion extending along the first end face from the main body portion, and
an end extending portion extending along the end portion from the main body portion,
a drain portion is provided to a position of the energy storage apparatus near the second end face, and
the main body portion, the first extending portion, and the end extending portion are continuously connected to each other to thereby form first end corner portions of the coupling portion;
the energy storage apparatus further comprising an insulating member for covering at least a face of the coupling portion facing the energy storage device,
wherein the coupling portion has a second extending portion extending along the second end face from the main body portion,
the insulating member has a convex part positioned astride the main body portion and the second extending portion between each of the end portions and the energy storage device adjacent to the end portion, and
the drain portion is disposed on an outer side of the convex portion in the second direction.

US Pat. No. 10,483,508

WIRING MODULE

AUTONETWORKS TECHNOLOGIES...

1. A wiring module to be attached to a power storage element group in which a plurality of power storage elements having positive and negative electrode terminals are aligned in a first direction, the wiring module configured to be attached from a second direction orthogonal to the first direction, comprising:connection members to be connected to the electrode terminals; and
a plurality of holding units that are coupled in the first direction and hold the connection members,
wherein the holding units are each provided with:
a locking portion that locks and couples a holding unit adjacent to the holding unit, and
a locked portion that is locked to the locking portion of a holding unit adjacent to the holding unit, and
a plurality of at least one of the locking portions and the locked portions are provided in alignment in the first direction in the holding unit and are configured such that an interval between the adjacent holding units can be changed in a stepwise manner, wherein the locking portion of the holding unit is configured to lock with the locked portion of an adjacent holding unit at a first set interval of a plurality of set intervals so that a distance taken in the first direction between the holding unit and the adjacent holding unit is kept constant and maintained at a predetermined length that corresponds to the first set interval.

US Pat. No. 10,483,506

BATTERY PACK

1. A battery pack, comprising:a housing of a plastic material, the housing including a mechanical interface for mechanically coupling the battery pack to a corresponding mechanical interface of a power tool in a first direction,
the housing mechanical interface including a rail, a groove and a sliding surface, the housing rail and the housing sliding surface being opposed to each other on opposing sides of the housing groove,
the housing mechanical interface configured to receive a power tool rail in the housing groove between the housing rail and the housing sliding surface, and
a bracket partially encased within the housing plastic material, the bracket comprising a first portion positioned within the housing mechanical interface rail, the first portion including a wear surface positioned at a lower surface of the housing mechanical interface rail and exposed to the housing mechanical interface groove.

US Pat. No. 10,483,501

SECONDARY BATTERY

Samsung SDI Co., Ltd., Y...

1. A secondary battery, comprising:an electrode assembly including a first electrode plate, a second electrode plate, and a separator between the first electrode plate and the second electrode plate;
a can housing the electrode assembly, the can having a long axis and a short axis, and an opening at a side thereof through which the electrode assembly is inserted; and
a cap plate that seals the opening of the can,
wherein the can includes:
a first side surface and a second side surface that face each other and extend in a first direction of the short axis of the can, the first side surface and the second side surface each having a first thickness in a second direction of the long axis of the can,
a third side surface and a fourth side surface that face each other and extend along the second direction of the long axis of the can, the third side surface and the fourth side surface each having a second thickness, the first thickness being greater than the second thickness in the first direction, and
a bottom surface that is located opposite the opening of the can and contacts the first through fourth side surfaces, the bottom surface having a third thickness in a third direction perpendicular to the first direction and the second direction, the first direction, the second direction, and the third direction being orthogonal to each other, wherein the third thickness of the bottom surface is greater than either of the first thickness and the second thickness, wherein:
the can further includes a second connection part where the bottom surface is connected to the first side surface and the second side surface, and a third connection part where the bottom surface is connected to the third side surface and the fourth side surface, and
a thickness of the second connection part and a thickness of the third connection part increase or decrease in a continuous manner in the third direction, and wherein:
the thickness of the second connection part and the thickness of the third connection part are straightly tapered in an inner side of the can along the short and long axes, respectively, in the third direction.

US Pat. No. 10,483,495

ORGANIC LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...

1. A lighting device, comprising:a first substrate; and
an organic light emitting diode on a first surface of the first substrate, the organic light emitting diode including a first electrode, an organic light emitting layer, and a second electrode, the organic light emitting diode being divided into a plurality of pixels, each of the pixels having a respective light emitting region,
wherein the first electrode is made of a transparent conductive material having a resistance value within a range of 2,800? to 5,500? in each pixel, and has light scattering particles dispersed therein.

US Pat. No. 10,483,494

ENCAPSULATION STRUCTURE FOR TRANSPARENT FLEXIBLE ORGANIC ELECTRONIC DEVICE

KOREA ADVANCED INSTITUTE ...

1. An encapsulation structure for a transparent flexible organic electronic device, the encapsulation structure comprising:a flexible substrate;
at least one hybrid unit structure provided on at least one surface of the flexible substrate and comprising a zinc oxide thin film, an aluminum oxide thin film, and a magnesium oxide thin film stacked on one another,
wherein, in the at least one hybrid unit structure, the zinc oxide thin film, the aluminum oxide thin film, and the magnesium oxide thin film individually have pinholes, and have a pinhole decoupling structure in which the pinholes of adjacent thin films among the zinc oxide thin film, the aluminum oxide thin film, and the magnesium oxide thin film are misaligned.

US Pat. No. 10,483,489

INTEGRATED CIRCULAR POLARIZER AND PERMEATION BARRIER FOR FLEXIBLE OLEDS

Universal Display Corpora...

1. An optical system for an organic light emitting device, the optical system comprising:a first layer comprising a birefringent material;
a polarizer layer; and
a transparent first permeation barrier disposed between the first layer and the polarizer layer, wherein the first permeation barrier has a permeation not greater than 10?4 g/cm/day.

US Pat. No. 10,483,463

MEMORY CELLS, MEMORY ARRAYS, AND METHODS OF FORMING MEMORY CELLS AND ARRAYS

Micron Technology, Inc., ...

1. A method of forming a memory array, comprising:forming heater structures over an array of electrical nodes; the heater structures being in one-to-one correspondence with the electrical nodes; the array of electrical nodes having rows extending along a first direction and having columns extending along a second direction substantially orthogonal to the first direction;
forming confined phase change material structures over the heater structures and in one-to-one correspondence with the heater structures, having lateral peripheries of a phase change material, the array having x-direction axes extending through the confined phase change material structures along the first direction and y-direction axes extending through the confined phase change material structures along the second direction;
forming bitlines across the confined phase change material structures, with the bitlines extending along the second direction;
forming conductive material caps between and contacting the bitlines and the confined phase change material structures, the confined phase change material structures and conductive material caps being spaced from one another along the x-direction axes by first insulative material regions comprising a first oxide-containing material having a first pair of opposing vertical sidewalls sandwiched between first nitride-containing materials that extend vertically along an entirety of the first pair of opposing vertical sidewalls, the confined phase change material structures and conductive material caps further being spaced from one another along the y-direction axes by second insulative material regions comprising a second oxide-containing material having a second pair of opposing vertically extending sidewalls sandwiched between second nitride-containing materials that extend vertically along an entirety of the second pair of opposing vertically extending sidewalls; and
the lateral peripheries of the confined phase change material structures, the conductive material caps and the heater structures being entirely laterally surrounded by the first and second nitride-containing materials.

US Pat. No. 10,483,459

MAGNETIC MEMORY

KABUSHIKI KAISHA TOSHIBA,...

1. A magnetic memory comprising:a first terminal and a second terminal;
a first conductive layer including a first region, a second region, and a third region that are arranged along a first direction, the second region being disposed between the first region and the third region, and the first region being electrically connected to the first terminal;
a second conductive layer including a fourth region, a fifth region, and a sixth region that are arranged along the first direction, the fifth region being disposed between the fourth region and the sixth region, and the sixth region being electrically connected to the second terminal;
a third conductive layer electrically connected to the third region and the fourth region;
a first magnetoresistance device disposed to correspond to the second region, including a first magnetic layer that is separate from the second region along a second direction intersecting the first direction, a second magnetic layer disposed between the second region and the first magnetic layer and electrically connected to the second region, a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer, and a third terminal electrically connected to the first magnetic layer;
a second magnetoresistance device disposed to correspond to the fifth region, including a third magnetic layer that is separate from the fifth region along the second direction, a fourth magnetic layer disposed between the fifth region and the third magnetic layer and electrically connected to the fifth region, a second nonmagnetic layer disposed between the third magnetic layer and the fourth magnetic layer, and a fourth terminal electrically connected to the third magnetic layer; and
a first circuit configured to flow a current between the first terminal and the second terminal through the first conductive layer, the third conductive layer, and the second conductive layer in a write operation,
a direction from the first region to the third region differing from a direction from the fourth region to the sixth region, and a direction from the second magnetic layer to the fourth magnetic layer intersecting a plane including the first direction and the second direction.

US Pat. No. 10,483,458

MAGNETORESISTIVE EFFECT DEVICE

TDK CORPORATION, Tokyo (...

1. A magnetoresistive effect device comprising:a first magnetoresistive effect element and a second magnetoresistive effect element each including a magnetization fixed layer, a spacer layer, and a magnetization free layer in which a magnetization direction is changeable;
a first port via which a high-frequency signal is input;
a second port via which a high-frequency signal is output;
a signal line; and
a direct-current input terminal, wherein
the first port and the second port are connected to each other via the signal line to form a connection of the first port and the second port,
the first port, the first magnetoresistive effect element and the second magnetoresistive effect element are connected in series to form a series connection with the first magnetoresistive effect element connected to the first port via the signal line and with the second magnetoresistive effect element connected to the first magnetoresistive effect element, such that the first magnetoresistive effect element is between the first port and the second magnetoresistive effect element in the series connection of the first port, the first magnetoresistive effect element and the second magnetoresistive effect element,
the series connection of the first port, the first magnetoresistive effect element and the second magnetoresistive effect element is in parallel to the connection of the first port and the second port, and
the direct-current input terminal is connected to the signal line.

US Pat. No. 10,483,450

INTERNAL ELECTRIC CONVERTER

1. A cell comprising:a first substrate with a first substrate first side and a first substrate second side, wherein the first substrate is electrically insulating and thermally conductive;
a first electrical contact with a first electrical contact first side and a first electrical contact second side, wherein the first electrical contact first side is connected to the first substrate second side;
a first n-type semiconductor layer with a first n-type dopant concentration and a first n-type semiconductor layer first side and a first n-type semiconductor layer second side, wherein the first n-type semiconductor layer first side is connected to the first electrical contact second side;
a second n-type semiconductor layer with a second n-type dopant concentration and a second n-type semiconductor layer first side and a second n-type semiconductor layer second side, wherein the second n-type dopant concentration is higher than the first n-type dopant concentration and the second n-type semiconductor layer first side is electrically and directly physically connected to the first n-type semiconductor layer second side;
a first p-type semiconductor layer with a first p-type dopant concentration and a first p-type semiconductor layer first side and a first p-type semiconductor layer second side, wherein the first p-type semiconductor layer first side is connected to the second n-type semiconductor layer second side;
a second p-type semiconductor layer with a second p-type dopant concentration and a second p-type semiconductor layer first side and a second p-type semiconductor layer second side, wherein the first p-type dopant concentration is higher than the second p-type dopant concentration and the second p-type semiconductor layer first side is electrically and directly physically connected to the first p-type semiconductor layer second side;
a second electrical contact with a second electrical contact first side and a second electrical contact second side, wherein the second electrical contact first side is connected to the second p-type semiconductor layer second side;
a second substrate with a second substrate first side and a second substrate second side, wherein the second substrate is electrically insulating and thermally conductive and the second substrate first side is connected to the second electrical contact second side.

US Pat. No. 10,483,439

OPTOELECTRONIC DEVICE WITH SILICON SLICE COVER ARRANGED DOWNSTREAM OF A CONVERSION ELEMENT

OSRAM Opto Semiconductors...

1. An optoelectronic device, comprising:a radiation-emitting semiconductor chip, wherein the emitted radiation is infrared radiation having a wavelength of <1100 nm;
a conversion element comprising a quantum dot converter material suitable for converting at least part of the emitted radiation into converted radiation, wherein the converted radiation from the quantum dot converter material is infrared radiation having a wavelength of >1200 nm; and
a cover which is substantially transmissive for the converted radiation and which is arranged downstream of the conversion element in a main emission direction,
wherein the conversion element is arranged on an inner side of the cover facing the semiconductor chip,
wherein the cover comprises silicon or is a silicon slice comprising an absorption edge, which lies at around 1100 nm, and
wherein the cover effectively suppresses the emitted radiation.

US Pat. No. 10,483,435

SEMICONDUCTOR LIGHT EMITTING DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor light emitting device, comprising:a semiconductor substrate comprising a first surface and a second surface, the second surface facing an opposite side from the first surface;
a first metal layer formed on the first surface;
a second metal layer formed on the first metal layer, the second metal layer containing Au;
an insulating layer formed above the second metal layer;
an epitaxial growth layer formed on the insulating layer;
a semiconductor layer formed on the epitaxial growth layer so that a portion of the epitaxial growth layer is exposed, the semiconductor layer containing Ga; and
a first electrode layer formed above the semiconductor layer, wherein
the epitaxial growth layer exposed from the semiconductor layer comprises an uneven portion.

US Pat. No. 10,483,433

ULTRAVIOLET LIGHT EMITTING DEVICES

SAMSUNG ELECTRONICS CO., ...

1. An ultraviolet light emitting device comprising:a substrate provided with an edge pattern at an upper surface thereof at side edges of the substrate, the edge pattern having a concave or convex shape with respect to the upper surface of the substrate;
a semiconductor laminate disposed on the substrate and on the edge pattern and including first and second conductivity-type AlGaN semiconductor layers and an active layer disposed between the first and second conductivity-type AlGaN semiconductor layers and having an AlGaN semiconductor;
a plurality of uneven portions extending from the edge pattern along side surfaces of the semiconductor laminate in a stacking direction of the semiconductor laminate;
first and second electrodes connected to the first and second conductivity-type AlGaN semiconductor layers, respectively; and
a plurality of even portions between the plurality of uneven portions, the plurality of even portions comprising flat side surfaces, and the plurality of uneven portions comprising cleavages in the flat side surfaces,
wherein the plurality of uneven portions are a plurality of gaps in the semiconductor laminate that start at the edge pattern along the side surfaces of the semiconductor laminate.

US Pat. No. 10,483,425

OPTICAL SEMICONDUCTOR COMPONENT PACKAGE AND OPTICAL SEMICONDUCTOR DEVICE

Kyocera Corporation, Kyo...

1. An optical semiconductor component package, comprising:a plate-like base having a first surface including a mount area in which an optical semiconductor component is mountable;
a frame located on the first surface and surrounding the mount area;
a plate-like lid bonded to the frame and covering the mount area; and
a light absorbing member located on a second surface of the lid facing the mount area, the light absorbing member having a plurality of recesses on a surface thereof.

US Pat. No. 10,483,420

CELL MODULE

Raygen Resources PTY LTD,...

1. A photovoltaic cell assembly that is suitable for use in a dense array concentrated photovoltaic cell module, the assembly including a substrate, a plurality of photovoltaic cells mounted on the substrate, each cell having an exposed surface for acceptance of solar radiation, the cells being arranged in a dense array covering more than 95% of the assembly with active cell area that includes at least one string of cells which are electrically connected together and form a series electrical circuit, and each string including a plurality of straight lengths of cells that form rows, with an end cell of one row of cells being electrically connected to a cell at the beginning of a successive row of cells, and a by-pass diode associated with each cell to allow the cell to be by-passed in the electrical circuit in the event that the cell fails or has low illumination, the diodes being positioned in the shadows of the cells, and the diodes providing direct pathways for heat and electricity from the cells to the substrate, and the substrate being a multiple layer substrate including an electrical insulation material layer, a top metalized layer and a bottom metalized layer respectively on opposite top and bottom faces of the electrical insulation material layer, the top metalized layer comprising a plurality of mounting pads in each row on which the cells are secured, with at least 90% of each cell being maintained in thermal contact with the substrate via the mounting pads, each cell being mounted on one of the mounting pads, each mounting pad including a section that extends under a neighboring cell in the electrical circuit, the by-pass diode for the cell being positioned beneath and in the shadow of the neighboring cell and mounted on a section of the mounting pad that extends under the neighboring cell, the diode being electrically and thermally connected to the substrate via the section of the mounting pad, and the diode being electrically and thermally connected to the neighboring cell.

US Pat. No. 10,483,404

THIN FILM TRANSISTOR WITH MULTIPLE OXIDE SEMICONDUCTOR LAYERS

Semiconductor Energy Labo...

2. A semiconductor device comprising:a first oxide semiconductor layer comprising indium and gallium;
a second oxide semiconductor layer comprising indium and gallium over the first oxide semiconductor layer;
a third oxide semiconductor layer comprising indium and gallium over the second oxide semiconductor layer;
a first insulating layer over the third oxide semiconductor layer;
a gate electrode over the first insulating layer, and
a second insulating layer in contact with a side surface of the gate electrode,
wherein a content of the gallium in the first oxide semiconductor layer is higher than a content of the indium in the first oxide semiconductor layer,
wherein a content of the indium in the second oxide semiconductor layer is higher than a content of the gallium in the second oxide semiconductor layer,
wherein a content of the gallium in the third oxide semiconductor layer is higher than a content of the indium in the third oxide semiconductor layer,
wherein a proportion of the indium to the gallium in the first oxide semiconductor layer is lower than a proportion of the indium to the gallium in the third oxide semiconductor layer, and
wherein the second oxide semiconductor layer comprises a region which is not overlapped with the gate electrode and the second insulating layer and comprises at least one of nitrogen, argon, and aluminum.

US Pat. No. 10,483,403

SEMICONDUCTOR DEVICE, POWER DIODE, AND RECTIFIER

Semiconductor Energy Labo...

1. A semiconductor device comprising:a gate electrode;
a gate insulating layer over the gate electrode;
an oxide semiconductor layer over the gate insulating layer;
a first layer comprising indium and zinc over and in contact with the oxide semiconductor layer; and
a second layer over and in contact with the first layer,
wherein an end portion of the first layer protrudes from an end portion of the second layer in a channel length direction,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc, and
wherein at least a part of the oxide semiconductor layer has c-axis alignment.

US Pat. No. 10,483,398

SEMICONDUCTOR DEVICE WITH GATE STACK

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a gate stack over a semiconductor substrate, wherein the gate stack has a work function layer and a metal filling, and tops of the work function layer and the metal filling are at different height levels;
a protection element over the gate stack, wherein a top and a bottom of the protection element have different widths;
a spacer over a side surface of the protection element and a sidewall of the gate stack;
a conductive feature over the semiconductor substrate; and
a conductive contact electrically connected to the conductive feature.

US Pat. No. 10,483,397

FIN FIELD EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A fin field effect transistor, comprising:a semiconductor substrate having a fin structure between two trenches, wherein each of the two trenches has a top portion and a bottom portion, the top portion of each of the two trenches is closer to a top portion of the fin structure than the bottom portion of each of the two trenches;
shallow trench isolations respectively formed in the bottom portions of the two trenches, wherein the top portion of the fin structure is tapered and above the shallow trench isolations;
a gate electrode over the fin structure and the shallow trench isolations, wherein the gate electrode is perpendicular to the fin structure;
a gate dielectric layer along sidewalls of the fin structure; and
a source/drain doped region formed in the fin structure,
wherein each of the shallow trench isolations has a rounded and convex top corner, a rounded and convex bottom corner and a straight side edge,
wherein the rounded and convex top corner of each of the shallow trench isolations is close to and separated from the fin structure,
wherein the rounded and convex bottom corner of each of the shallow trench isolations is in contact with the bottom portion of each of the two trenches,
wherein the rounded and convex top corner of each of the shallow trench isolations is directly connected the straight side edge of each of the shallow trench isolations, and the shallow trench isolations are in contact with the fin structure,
wherein the gate dielectric layer has a convex top surface and a concave bottom surface, and an entirety of the gate dielectric layer is disposed at a level between a top surface of the fin structure and the rounded and convex top corner of each of the shallow trench isolations.

US Pat. No. 10,483,394

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a Fin FET device including:
a first fin structure disposed over a substrate;
an isolation insulating layer disposed over the substrate; and
a first source/drain stressor layer made of semiconductor material and disposed over the first fin structure, wherein:
an upper surface of the isolation insulating layer has a valley portion and a peak portion disposed between the valley portion and the first fin structure, and
a height Ha of an interface between the first fin structure and the first source/drain stressor layer measured from the substrate is greater than a height Hb of the valley portion measured from the substrate, and is less than a height Hc of the peak portion measured from the substrate.

US Pat. No. 10,483,393

METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES

STMicroelectronics, Inc.,...

1. A device, comprising:a substrate having a first portion and a second portion extending away from the first portion, the second portion having a first length in a first direction and a first width in a second direction orthogonal to the first direction;
a microfabricated structure on the substrate, the microfabricated structure having a fin including:
the second portion of the substrate;
a strain-inducing layer on the second portion of the substrate, the strain-inducing layer having a second length in the first direction and a second width in the second direction, the first length approximately equal to the second length and the first width approximately equal to the second width; and
a semiconductor layer on the strain-inducing layer.

US Pat. No. 10,483,390

INSULATED GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

FUJI ELECTRIC CO., LTD., ...

1. An insulated gate semiconductor device, comprising:a drift layer of a first conductivity type made of a semiconductor material having a wider bandgap than silicon, a top surface of the semiconductor material having an off-angle;
a base region of a second conductivity type made of said semiconductor material, disposed above the drift layer;
a first high-impurity region of the first conductivity type, embedded in a top of the base region and having a higher impurity density than the drift layer, wherein a trench is provided penetrating the first high-impurity region and the base region;
a gate insulating film disposed on side surfaces and a bottom surface of the trench;
an embedded gate electrode embedded inside the trench, with the gate insulating film being interposed between the trench and the embedded gate electrode;
a second high-impurity region of the first conductivity type made of said semiconductor material, disposed on a bottom surface side of the drift layer;
a gate bottom protection region of the second conductivity type, embedded in the drift layer at a bottom of the trench; and
a base bottom embedded region of the second conductivity type, embedded in the drift layer below the base region separately from the gate bottom protection region, and having a higher impurity density than the base region,
wherein a cross-section of the base bottom embedded region has a trapezoid-shaped portion on at least a bottom side of the base bottom embedded region, an upper base and a lower base of the trapezoid are parallel, and a virtual straight line that connects a midpoint of the upper base and a midpoint of the lower base is tilted from a line normal to the top surface of the drift layer towards a direction of the off-angle by a prescribed tilt angle, and
wherein a bottom surface of the base bottom embedded region is deeper than a bottom surface of the gate bottom protection region.

US Pat. No. 10,483,384

TRANSISTOR DEVICE WITH HIGH CURRENT ROBUSTNESS

Infineon Technologies AG,...

1. A transistor device, comprising:a first emitter region of a first doping type, a second emitter region of a second doping type, a body region of the second doping type, a drift region of the first doping type, a field-stop region of the first doping type, and at least one boost structure; and
a gate electrode dielectrically insulated from the body region by a gate dielectric,
wherein the body region is arranged between the first emitter region and the drift region, the field-stop region is arranged between the drift region and the boost structure, and the boost structure is arranged between the field-stop region and the second emitter region,
wherein the at least one boost structure comprises a base region of the first doping type and at least one auxiliary emitter region of the second doping type separated from the second emitter region by the base region,
wherein an overall dopant dose in the drift region and the field-stop region in a current flow direction of the transistor device is higher than a breakthrough charge of a semiconductor material of the drift region and the field-stop region.

US Pat. No. 10,483,376

METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE

UNISANTIS ELECTRONICS SIN...

1. A method for producing a semiconductor device, the method comprising:depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate;
forming a first hole for forming a gate electrode in the second insulating film;
filling the first hole with a first metal to form the gate electrode;
forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole;
performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film;
forming a gate insulating film on a side surface of the second hole; and
epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.

US Pat. No. 10,483,375

FIN CUT ETCH PROCESS FOR VERTICAL TRANSISTOR DEVICES

International Business Ma...

1. A method for fabricating a semiconductor device including a vertical transistor, comprising:forming a fin structure from a substrate, the fin structure including a fin;
forming a bottom source/drain region on the substrate adjacent to the fin;
etching a longitudinal end portion of the fin to create a gap exposing the substrate;
forming a gate and a top source/drain region; and
forming a contact wrapping around a horizontal portion and a vertical portion of the bottom source/drain region in a region including a location where the longitudinal end portion of the fin was removed by the etching.

US Pat. No. 10,483,364

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A method for manufacturing a semiconductor structure, the method comprising:forming a dielectric layer on at least one gate structure and at least one source drain structure;
forming an opening in the dielectric layer to expose the source drain structure;
forming a protection layer on at least one sidewall of the opening;
forming a conductive plug in the opening, wherein the conductive plug is electrically connected to the source drain structure;
etching back the dielectric layer to expose a sidewall of the protection layer after the forming the conductive plug; and
removing the protection layer after the forming the conductive plug.

US Pat. No. 10,483,357

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate having a drift region of a first conductivity type;
a cathode region formed on a lower surface of the semiconductor substrate;
a diode portion having the cathode region formed on the lower surface of the semiconductor substrate;
a first dummy trench portion provided from an upper surface of the semiconductor substrate to the drift region, including one part provided inside the diode portion and the other part provided outside the diode portion, and provided extending in series from inside the diode portion to outside the diode portion in a predetermined extending direction on the upper surface of the semiconductor substrate; and
a first lead-out portion provided on the upper surface of the semiconductor substrate, and electrically connected to the first dummy trench portion outside the diode portion.

US Pat. No. 10,483,350

SEMICONDUCTOR DEVICE

HOSEI UNIVERSITY, Tokyo ...

1. A semiconductor device, comprising:a semiconductor member having a mesa structure in which a second semiconductor layer having one of a p-type conductivity type and an n-type conductivity type is laminated on a first semiconductor layer having the other one of the p-type conductivity type and the n-type conductivity type, so that the second semiconductor layer is exposed on an upper surface of the mesa structure, a pn junction interface is exposed on a side surface of the mesa structure, and the first semiconductor layer is exposed on an outside upper surface of the mesa structure;
an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure;
a first electrode electrically connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and
a second electrode electrically connected to the first semiconductor layer on a lower surface of the first semiconductor layer,
wherein the insulating film is formed including a first insulating layer and a second insulating layer,
the first insulating layer is disposed so as to cover a corner portion where the side surface of the mesa structure and the outside upper surface of the mesa structure are connected to each other,
the second insulating layer is disposed so as to cover the pn junction interface exposed on the side surface of the mesa structure, or disposed so as to cover an area directly under an electrode end in a state of constituting an entire thickness of the insulating film directly under the electrode end of the first electrode,
a relative dielectric constant of the second insulating layer is equal to or larger than a relative dielectric constant of the semiconductor member, and
the relative dielectric constant of the first insulating layer is smaller than the relative dielectric constant of the second insulating layer, and
wherein the first insulating layer is in direct contact with the corner portion,
the second insulating layer is in direct contact with the pn junction interface, or in direct contact with the semiconductor member at an area directly under the electrode end of the first electrode, and
the second insulating layer is not in contact with the corner portion.

US Pat. No. 10,483,348

SEMICONDUCTOR DEVICE

SOCIONEXT, INC., Kanagaw...

1. A semiconductor device comprising:a substrate;
a first transistor which includes a first impurity region of a first conductivity type formed in the substrate, and which includes a second impurity region of the first conductivity type formed in the substrate;
a first guard ring of a second conductivity type different from the first conductivity type, formed in the substrate, the first guard ring surrounding the first transistor in a plan view;
a first wiring formed on the first guard ring and electrically connected to the first guard ring; and
a ground wiring formed on the first wiring, the ground wiring being electrically connected to the first wiring and the second impurity region,
wherein
the first transistor includes a first part and a second part which are respectively arranged in a first direction in a plan view,
the first part of the first transistor is separated with a first distance from the first guard ring in a second direction which is perpendicular to the first direction in a plan view,
the second part of the first transistor is separated with a second distance from the first guard ring in the second direction in a plan view,
the second distance is shorter than the first distance,
the first part is separated from the ground wiring in a plan view, and
the second part is overlapped with the ground wiring in a plan view.

US Pat. No. 10,483,347

SEMICONDUCTOR DEVICE, STARTER CIRCUIT, AND SWITCHED-MODE POWER-SUPPLY CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate of a first conductivity type;
a drift layer of a second conductivity type provided on the semiconductor substrate;
a drain region of the second conductivity type in contact with the drift layer to be provided on the semiconductor substrate at a center of the drift layer;
a gate region of the first conductivity type provided on the semiconductor substrate in an outer side of the drift layer, the gate region including U-shaped first and second concave patterns in a planar pattern, each of which having entrances of the U-shapes located with equal distances from the drain region, the bottoms of the U-shapes protruding toward an outer side of the planar pattern;
source regions of the second conductivity type provided in an inner side of the first concave patterns, each of the source regions contacts with the drift layer and the gate region; and
surge-current guiding-regions of the second conductivity type provided in an inner side of the second concave patterns, each of the surge-current guiding-regions contacts with the drift layer and the gate region.

US Pat. No. 10,483,339

ORGANIC LIGHT-EMITTING DEVICE INCLUDING A BRIDGE ELECTRODE

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting device comprising:a substrate comprising a pixel area;
an oxide semiconductor layer disposed in the pixel area, wherein the oxide semiconductor layer comprises a channel region, a source region and a drain region, and wherein the channel region is disposed between the source region and the drain region;
a gate insulating layer disposed on the oxide semiconductor layer;
a gate electrode disposed on the gate insulating layer;
a conductive layer disposed between the substrate and the oxide semiconductor layer, wherein a first portion of the conductive layer is electrically connected to one of the source region and the drain region via a bridge electrode, wherein the bridge electrode is in contact with the one of the source region and the drain region and a second portion of the conductive layer, and wherein the first portion of the conductive layer overlaps the channel region;
a first insulation film covering the gate electrode and the bridge electrode; and
an organic light-emitting diode comprising a pixel electrode disposed on the first insulation film in the pixel area, an emissive layer disposed on the pixel electrode, and an opposite electrode disposed on the emissive layer,
wherein at least a portion of the oxide semiconductor layer overlaps the organic light-emitting diode.

US Pat. No. 10,483,335

ORGANIC LIGHT EMITTING DISPLAY DEVICE HAVING PIXEL DEFINING LAYER

LG Display Co., Ltd., Se...

1. An organic light emitting display device, comprising:a first electrode in an emission area of a subpixel;
a pixel defining layer surrounding the first electrode in a non-emissive area of the subpixel;
a light emitting layer on the first electrode;
a second electrode on the light emitting layer;
a first encapsulation layer on the second electrode; and
a color filter on the first encapsulation layer in the subpixel,
wherein the pixel defining layer includes:
a first pixel defining layer;
a second pixel defining layer on the first pixel defining layer, a width of the second pixel defining layer at any height thereof is wider than a width of the first pixel defining layer at any height thereof;
a first metal layer on the second pixel defining layer; and
a third pixel defining layer on the first metal layer;
wherein a thickness of the third pixel defining layer is thicker than a thickness of each of the first pixel defining layer, the second pixel defining layer, and the first metal layer.

US Pat. No. 10,483,324

3D VERTICAL MEMORY ARRAY CELL STRUCTURES AND PROCESSES

1. A method for forming a vertical memory structure, comprising:forming a layer stack comprising word line layers separated by insulator layers;
forming an opening through the layer stack to expose internal surfaces of the word line layers;
depositing a selector material directly on the internal surfaces of the word line layers, wherein the depositing forms segments of the selector material, and wherein each segment is deposited on a corresponding internal surface of a respective word line layer;
depositing a memory material directly on the selector material; and
depositing bit line material directly on the memory material.

US Pat. No. 10,483,322

MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A memory device, comprising:a plurality of transistors;
a first inter-layer dielectric layer over the transistors;
a plurality of first conductive features embedded in the first inter-layer dielectric layer;
a plurality of memory structures respectively over the first conductive features, wherein each of the memory structures has a top electrode, a bottom electrode coupled electrically to a respective one of the first conductive features, and a resistive material layer sandwiched between the top and bottom electrodes;
a filler in between the memory structures; and
a second inter-layer dielectric layer over the filler and the memory structures, the second inter-layer dielectric layer and the filler forming an interface, the interface extending from one of the memory structures to another of the memory structures, wherein the second inter-layer dielectric layer has a first portion over the filler and the memory structures and a second portion around the first portion, and a top surface of the first portion of the second inter-layer dielectric layer is higher than a top surface of the second portion of the second inter-layer dielectric layer.

US Pat. No. 10,483,297

ENERGY HARVESTING DEVICES AND METHOD OF FABRICATION THEREOF

Baupil Photonoics, Inc., ...

1. A thermal energy harvester, comprising:a substrate;
a buffer layer;
a first electrode;
a second electrode;
an absorption layer electrically connected between the first and second electrodes comprising,
a first material;
a second material of a different type that the first material; and
a third material of a different type than the second material;wherein at least one of the first material, the second material, and the third materials are selected from the group consisting of InSb, InAs, GaSb, and PbTe, or a combination thereof, wherein when GaSb is selected, at least one of the first material, the second material, or the third material is selected from the group consisting of InSb, GaAs, InP, GaN, AlN, InAs, and PbTe, or a combination thereof, wherein the first, the second, and the third materials are in a p-n or pin junction with each other in the absorption layer comprises two or more p-n or p-i-n junctions comprising three-dimensional-structures, wherein the two or more p-n or pin junctions are in series increasing the open circuit voltage, and wherein the two or more p-n or p-i-n junctions comprising cutoff wavelength between 2 ?m to 40 ?m.

US Pat. No. 10,483,294

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. An array substrate, comprising a gate electrode layer, an active layer, and a source-drain electrode layer that are disposed on a substrate,wherein the substrate comprises a storage capacitance region thereon, in the storage capacitance region, projections of the gate electrode layer and the active layer on the substrate are at least partially overlapped, and projections of the active layer and the source-drain electrode layer on the substrate are at least partially overlapped,
wherein the array substrate further comprises a gate insulation layer between the gate electrode layer and the active layer and an etch-stopper layer between the active layer and the source-drain electrode layer,
wherein the etch-stopper layer is an insulating layer, and
wherein, in the storage capacitance region, the gate electrode layer and the active layer are spatially separated by the gate insulation layer so as to form a capacitor between them, and the active layer and the source-drain electrode layer are spatially separated by the etch-stopper layer so as to form another capacitor between them,
wherein the gate electrode layer comprises a portion in the storage capacitance region, the gate insulation layer comprises a portion in the storage capacitance region, the active layer comprises a portion in the storage capacitance region, the etch-stopper layer comprises a portion in the storage capacitance region, and the source-drain electrode layer comprises a portion in the storage capacitance region,
wherein the substrate further comprises a thin film transistor region, and a thickness of the gate insulation layer formed in the storage capacitance region is smaller than a thickness of the gate insulation layer formed in the thin film transistor region,
wherein the gate electrode layer at a contact hole in the gate insulation layer is in contact with the source-drain electrode layer.

US Pat. No. 10,483,288

LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE USING THE SAME

Semiconductor Energy Labo...

1. A light-emitting device comprising:a substrate;
an oxide semiconductor over the substrate, the oxide semiconductor comprising indium, zinc, and gallium;
a gate electrode over the oxide semiconductor;
a first insulating film over the gate electrode, the first insulating film comprising an inorganic insulating material;
a source electrode and a drain electrode over the first insulating film, the source electrode and the drain electrode each comprising a region in contact with the oxide semiconductor;
a color filter over the first insulating film;
a light-emitting element over the color filter, the light-emitting element electrically connected to one of the source electrode and the drain electrode; and
an organic resin over the light-emitting element,
wherein the color filter is positioned between the first insulating film and the light-emitting element,
wherein the color filter comprises a region overlapping with the light-emitting element,
wherein the color filter does not overlap with the oxide semiconductor and the gate electrode,
wherein the light-emitting element comprises:
a first electrode;
a second electrode over the first electrode;
a charge generation layer between the first electrode and the second electrode;
a first light-emitting layer between the first electrode and the charge generation layer;
a second light-emitting layer between the charge generation layer and the second electrode; and
a third light-emitting layer between the charge generation layer and the second electrode,
wherein the first light-emitting layer comprises a blue-emissive fluorescent substance,
wherein the second light-emitting layer comprises a first phosphorescent substance,
wherein the first phosphorescent substance is a red-emissive phosphorescent substance,
wherein the third light-emitting layer comprises a second phosphorescent substance and overlaps with the second light-emitting layer, and
wherein the first electrode is positioned over the one of the source electrode and the drain electrode.

US Pat. No. 10,483,287

DOUBLE GATE, FLEXIBLE THIN-FILM TRANSISTOR (TFT) COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (MOS) (CMOS) CIRCUITS AND RELATED FABRICATION METHODS

QUALCOMM Incorporated, S...

1. A complementary metal-oxide semiconductor (CMOS) circuit, comprising:a flexible substrate;
at least one P-type Field-Effect Transistor (FET) (PFET) formed on a first surface of the flexible substrate, each of the at least one PFET comprising:
a first gate disposed on the first surface of the flexible substrate;
a P-type thin-film semiconductor structure disposed over the first gate in a first axis direction, the P-type thin-film semiconductor structure comprising a first source/drain region, a second source/drain region, and a first channel region between the first and second source/drain regions; and
a second gate disposed over the P-type thin-film semiconductor structure in the first axis direction opposite to the first gate;
at least one N-type FET (NFET) formed on the first surface of the flexible substrate, each of the at least one NFET comprising:
a third gate disposed on the first surface of the flexible substrate;
an N-type thin-film semiconductor structure disposed over the third gate in the first axis direction, the N-type thin-film semiconductor structure comprising a third source/drain region, a fourth source/drain region, and a second channel region between the third and fourth source/drain regions; and
a fourth gate disposed over the N-type thin-film semiconductor structure in the first axis direction opposite to the third gate; and
at least one metal contact electrically coupling the second source/drain region of the at least one PFET and the third source/drain region of the at least one NFET.

US Pat. No. 10,483,286

ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY, THIN FILM TRANSISTOR, AND MANUFACTURING METHOD OF ARRAY SUBSTRATE

Mitsubishi Electric Corpo...

1. An array substrate comprising a first thin film transistor and a second thin film transistor on a substrate, whereinthe first thin film transistor includes
a first gate electrode provided on the substrate,
a gate insulating film provided covering the first gate electrode,
a first oxide semiconductor layer and a second oxide semiconductor layer provided on the gate insulating film while overlapping the first gate electrode in plan view, with a first separation portion separating the first oxide semiconductor layer and the second oxide semiconductor layer from each other,
a first source electrode and a first drain electrode provided extending from above the first oxide semiconductor layer and above the second oxide semiconductor layer, respectively, onto the gate insulating film while overlapping the first oxide semiconductor layer or the second oxide semiconductor layer in plan view, with a second separation portion, greater than the first separation portion, separating the first source electrode and the first drain electrode from each other, and
an amorphous silicon layer provided extending on the first separation portion on the gate insulating film, the second separation portion, a part of the first source electrode, and a part of the first drain electrode, and
the second thin film transistor includes
a second gate electrode provided on the substrate,
the gate insulating film provided covering the second gate electrode,
a third oxide semiconductor layer provided on the gate insulating film while overlapping the second gate electrode in plan view, and
a second source electrode and a second drain electrode provided extending from above the third oxide semiconductor layer onto the gate insulating film while overlapping the third oxide semiconductor layer in plan view, with a third separation portion separating the second source electrode and the second drain electrode from each other.

US Pat. No. 10,483,284

LOGIC SEMICONDUCTOR DEVICE

Korea University Research...

1. A semiconductor device comprising:a plurality of stacked transistors,
wherein:
each of the transistors comprises:
a semiconductor column including a first conductive region of a first conductivity type, a second conductive region of a second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region;
a gate electrode disposed to cover the intrinsic region; and
a gate insulating layer disposed between the gate electrode and the intrinsic region;
wherein not all of the plurality of stacked transistors have a same first conductivity type, and
wherein:
the plurality of stacked transistors include a first transistor disposed at a lower portion and a second transistor disposed above the first transistor,
the first conductivity type of the first transistor is n-type, and
the first conductivity type of the second transistor is p-type.

US Pat. No. 10,483,281

SEMICONDUCTOR MEMORY DEVICE

SK hynix Inc., Gyeonggi-...

1. A method of manufacturing a semiconductor memory device comprising:forming bit lines on a substrate, wherein the substrate includes a cell array region, a word line contact region and a page buffer region;
wherein the page buffer region is coupled to the cell array region through bit lines,
wherein the bit lines include a first bit line and a second bit line, and
wherein the second bit line has a curved structure toward the word line contact region and a curvedness of the second bit line is greater than a curvedness of the first bit line.

US Pat. No. 10,483,277

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:a substrate;
a plurality of interconnect portions, at least one portion of the plurality of interconnect portions being provided inside the substrate, each of the plurality of interconnect portions extending in a first direction along a surface of the substrate, the plurality of interconnect portions being arranged along a second direction, the second direction crossing the first direction and being along the surface of the substrate, the plurality of interconnect portions having a line-and-space arrangement arranged along the second direction;
a conductive layer provided on the plurality of interconnect portions;
a stacked body provided on the conductive layer, the stacked body including a plurality of electrode layers stacked to be separated from each other, each of the plurality of electrode layers extending in the second direction; and
a plurality of columnar portions provided inside the stacked body, each of the plurality of columnar portions including a semiconductor portion and a charge storage film, the semiconductor portion extending in a stacking direction of the plurality of electrode layers, the charge storage film being provided between the semiconductor portion and the stacked body,
the plurality of electrode layers being disposed continuously over two or more of the plurality of interconnect portions arranged along the second direction,
one interconnect portion of the plurality of interconnect portions overlapping two or more sets of the plurality of electrode layers when viewed from the stacking direction, the two or more sets of the plurality of electrode layers extending in the second direction respectively and being separated in the first direction from each other.

US Pat. No. 10,483,276

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, comprising the steps of:forming, over a first surface of a semiconductor substrate located in a region where a first transistor is to be formed, a first gate insulating film having a first oxide film, a first nitride film placed over the first oxide film, and a second oxide film placed over the first nitride film; and
forming a second gate insulating film over the first surface located in a region where a second transistor is to be formed,
wherein the second oxide film includes a first layer and a second layer placed over the first layer,
wherein the first gate insulating film formation step includes a step of forming a second nitride film placed over the first layer, and
wherein the second layer is formed by oxidation of at least a portion of the second nitride film,
wherein the second gate insulating film is formed by thermal oxidation,
wherein the method further comprises forming, over the first surface located in a region where a third transistor is to be formed, a third gate insulating film thinner than the second gate insulating film,
wherein the portion of the second nitride film remains at the time of formation of the second gate insulating film,
wherein the second nitride film oxidized at the time of formation of the second gate insulating film is removed by etching prior to the third gate insulating film formation step, and
wherein the portion of the second nitride film which has remained at the time of formation of the second gate insulating film is oxidized into the second layer at the time of formation of the third gate insulating film.

US Pat. No. 10,483,270

INTEGRATED ASSEMBLIES AND METHODS OF FORMING INTEGRATED ASSEMBLIES

Micron Technology, Inc., ...

1. An integrated assembly, comprising:a first channel structure extending substantially vertically;
a second channel structure extending substantially vertically; each of the first and the second semiconductor channel structures having a first doped channel region interfacing a second doped channel region at a boundary region, the first doped channel regions being differently doped relative to the second doped channel regions; and
a gating structure extending between the first channel structure and the second channel structure and having a first gating region extending along the first channel structure, a second gating region extending along the second channel structure, and an interconnecting region extending laterally between the first and second gating regions, the interconnecting region being vertically narrower than first and second the gating regions.

US Pat. No. 10,483,267

EIGHT-TRANSISTOR STATIC RANDOM-ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A Static Random Access Memory (SRAM) cell, comprising:a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and
a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each other, gate electrodes of the read pull-down transistor, the second pull-down transistor, and the second pull-up transistors being electrically connected to each other,
wherein a first doping concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doping concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.

US Pat. No. 10,483,263

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A manufacturing method for a semiconductor device, comprising:providing a substrate structure, wherein the substrate structure comprises:
a semiconductor substrate;
a single fin protruding from the semiconductor substrate, wherein trenches are formed on sides of the fin;
a pad insulator layer for padding the trenches;
a first insulator layer separately formed from the pad insulator layer and partially filling the trenches, wherein the single fin protrudes from the first insulator layer; and
a second insulator layer covering the single fin;
forming a plurality of pseudo gate structures on the second insulator layer, wherein each pseudo gate structure wraps a part of the single fin, wherein each pseudo gate structure comprises a pseudo gate located on the second insulator layer, wherein the plurality of pseudo gate structures comprises at least a first pseudo gate structure, a second pseudo gate structure, and a third pseudo gate structure that are spaced from each other, and wherein the second pseudo gate structure and the third pseudo gate structure are located at two opposite edge corners of the single fin and the first pseudo gate structure is a only pseudo gate structure disposed between the second pseudo gate structure and the third pseudo gate structure, and a first part of each of the second pseudo gate structure and the third pseudo gate is on and in direct contact with the first insulator layer and a second part of each of the second pseudo gate structure and the third pseudo gate structure is on and in direct contact with the second insulator layer;
forming, above the first insulator layer and the second insulator layer, spacers at two sides of each of the second pseudo gate structure and the third pseudo gate structure, where a bottom face of one of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the first insulator layer whereas a bottom face of another of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the second insulator layer;
etching, after forming the spacers, the second insulator layer and at least a part of the single fin that are not covered by the spacers and the pseudo gates, to form recesses in the single fin; and
forming at least one source or drain in the recesses.

US Pat. No. 10,483,261

INTEGRATED CIRCUIT HAVING CHEMICALLY MODIFIED SPACER SURFACE

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit (IC), comprising:sidewall spacers having a second dielectric material on a first dielectric material, wherein the second dielectric material comprises carbon and silicon and the first dielectric material comprises silicon and another element besides carbon, and wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material,
wherein the transition region has a composition that includes silicon, carbon and the another element besides carbon, and
wherein at a widest point of the sidewall spacers, the transition region is thicker than the second dielectric material.

US Pat. No. 10,483,256

OPTOELECTRONIC SEMICONDUCTOR DEVICE AND APPARATUS WITH AN OPTOELECTRONIC SEMICONDUCTOR DEVICE

OSRAM OPTO SEMICONDUCTORS...

1. An optoelectronic semiconductor device comprising:an emission region comprising a semiconductor layer sequence with a first semiconductor layer, a second semiconductor layer and, arranged between the first semiconductor layer and the second semiconductor layer, an active region configured to generate radiation;
a protection diode region; and
a contact for external electrical contacting of the optoelectronic semiconductor device,
wherein the contact comprises a first contact region electrically conductively connected to the emission region,
wherein the contact comprises a second contact region located at a distance from the first contact region and electrically conductively connected to the protection diode region,
wherein the second contact region is not directly electrically connected to the emission region,
wherein the first contact region and the second contact region are externally electrically contactable by a common end of a single connecting lead,
wherein the single connecting lead is a wire bond connection,
wherein the semiconductor layer sequence is arranged on a carrier,
wherein the first semiconductor layer is electrically conductively connected in the emission region to a first connection layer, and
wherein the first connection layer extends in places between the carrier and the emission region.

US Pat. No. 10,483,253

DISPLAY WITH EMBEDDED PIXEL DRIVER CHIPS

Apple Inc., Cupertino, C...

1. A display panel comprising:an array of pixel driver chips embedded front side up in an insulator layer;
a front side redistribution layer (RDL) spanning across and in electrical connection with front sides of the array of pixel driver chips; and
an array of light emitting diodes (LEDs) bonded to the front side RDL, the array of LEDs arranged in an array of pixels, wherein each pixel driver chip is to switch and drive a plurality of LEDs in the array of LEDs for a plurality of pixels;
wherein each pixel driver chip has a minimum x-y dimension that that is larger than a maximum pitch in the x-y dimension between adjacent LEDs of the array of LEDs, and each pixel driver chip is characterized by pixel driver chip area in x-y dimensions that is directly underneath an entire LED area in the x-y dimensions for each of a corresponding plurality of LEDs of the array of LEDs.

US Pat. No. 10,483,245

LIGHT BAR, EDGE-TYPE BACKLIGHT MODULE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A light bar, comprising: a circuit board and an integrated light emitting body arranged on the circuit board,wherein the integrated light emitting body comprises a package and a plurality of light sources, and the package is configured to package the plurality of light sources,
wherein a light emitting surface of the integrated light emitting body is perpendicular to a surface of the circuit board on which the integrated light emitting body is mounted, a distance between the light emitting surface and an edge of the surface of the circuit beard on which the integrated light emitting body is mounted, close to the light emitting surface and parallel to the light emitting surface is W1, and 0.3 mm?W1?1.0 mm.

US Pat. No. 10,483,244

POWER SEMICONDUCTOR MODULE

ABB Schweiz AG, Baden (C...

1. A power semiconductor module comprising:a first main electrode, a second main electrode, and a control terminal, controllable power semiconductor components arranged between the first main electrode and the second main electrode, wherein each controllable power semiconductor component has a first electrode, a second electrode and a control electrode, and the first electrode of each controllable power semiconductor component is electrically connected to the first main electrode, the second electrode of each controllable power semiconductor component is electrically connected to the second main electrode, and the control electrode of each controllable power semiconductor component is electrically connected to the control terminal, wherein the controllable power semiconductor components are arranged in a plurality of ring arrangements, and
an electrically conductive contact element arranged between the second main electrode of the power semiconductor module and each controllable power semiconductor component, said contact element connecting the second main electrode to the second electrode of the power semiconductor component, wherein the contact element and the power semiconductor component define a current carrying direction that is at least approximately at right angles with respect to the first main electrode,
wherein each ring arrangement of the plurality of ring arrangements has the respective controllable power semiconductor components arranged at least approximately along a first circular line as well as a control conductor track which is arranged on the first main electrode and runs at least approximately along a second circular line, the second circular line of the respective ring arrangement runs concentrically and outside relative to the first circular line of the respective ring arrangement, wherein all of the controllable power semiconductor components are arranged in the plurality of ring arrangements,
wherein the control electrode of each controllable power semiconductor component of the respective ring to the control conductor track of the respective ring arrangement, and the control conductor track of the respective ring arrangement is connected via a further electrical connection to the control terminal, and
wherein the further electrical connection runs at least substantially parallel to the current carrying direction.

US Pat. No. 10,483,234

CHIP PACKAGES AND METHODS OF MANUFACTURE THEREOF

Taiwan Semiconductor Manu...

1. A chip package comprising:a plurality of first chips laterally adjacent to each other, each of the plurality of first chips having a plurality of first contact pads on a first surface thereof;
first redistribution layers (RDLs) at the first surfaces of the first chips, wherein the first RDLs are separate from each other, wherein each of the first RDLs contacts the first surface of a respective first chip and is laterally conterminous with the respective first chip;
a second chip attached to the first surfaces of the plurality of first chips, the second chip having a plurality of second contact pads on a first surface thereof, wherein the first surface of the second chip faces away from the plurality of first chips, wherein a first portion of the second chip is disposed within lateral extents of a third chip of the plurality of first chips, and a second portion of the second chip is disposed within lateral extents of a fourth chip of the plurality of first chips;
an adhesive layer between the second chip and the plurality of first chips, the adhesive layer being attached to and contacting a second surface of the second chip opposing the first surface of the second chip, the adhesive layer having a same width as the second chip, a first portion of the adhesive layer being attached to the third chip of the plurality of first chips, and a second portion of the adhesive layer being attached to the fourth chip of the plurality of first chips;
a second RDL coupled to the plurality of second contact pads of the second chip, wherein the second chip is between the second RDL and the plurality of first chips;
a plurality of first conductive pillars laterally separated from the second chip, the plurality of first conductive pillars extending from the second RDL to corresponding ones of a first group of the plurality of first contact pads, the first group disposed outside a width of the second chip; and
a molding compound around the plurality of first chips, the second chip, and the plurality of first conductive pillars.

US Pat. No. 10,483,233

SPLIT BALL GRID ARRAY PAD FOR MULTI-CHIP MODULES

International Business Ma...

1. A multi-chip module, comprising:a substrate containing multiple wiring layers, each wiring layer having multiple wires, first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, wherein the first section is connected by a first wire of the multiple wires to a pad of a first group of the first pads, wherein the non-contiguous second section is connected by a second wire of the multiple wires to a pad of a second group of the first pads, and wherein another pad of the second pads is a conventional pad having a contiguous top surface and a contiguous bottom surface;
a first solder ball in direct physical contact with the contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height in a first direction, and wherein the first direction is perpendicular to the contiguous bottom surface of the conventional pad; and
a second solder ball in direct physical contact with the first section and the non-contiguous second section of the split pad, wherein the second solder ball has a second height in the first direction, and wherein the second height is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging,
wherein a first active component is attached to the first group of the first pads and a second active component is attached to the second group of the first pads.

US Pat. No. 10,483,231

BONDING METHOD OF FIXING AN OBJECT TO A ROUGH SURFACE

Tsinghua University, Bei...

1. A bonding method comprising:placing a sheet structure on a substrate surface of a substrate, wherein a surface roughness of the substrate surface is larger than 1.0 micrometer; the sheet structure comprises a first surface and a second surface opposite to the first surface, the first surface is in direct contact with the substrate surface, and a surface roughness of the second surface is less than or equal to 1.0 micrometer;
laying a carbon nanotube structure on the second surface, wherein the carbon nanotube structure comprises a first portion, a second portion, and a third portion, the first portion and the second portion are connected together by the third portion, the first portion and the second portion extend out of the second surface and are in direct contact with the substrate surface, the third portion is in direct contact with the sheet structure; the carbon nanotube structure comprises a super-aligned carbon nanotube film, the super-aligned carbon nanotube film comprises a plurality of carbon nanotubes, the plurality of carbon nanotubes extends substantially along a same direction, and an extending direction of the plurality of carbon nanotubes is substantially parallel to the second surface;
adding an organic solvent to the first portion and the second portion, to fix the sheet structure on the substrate surface only by the carbon nanotube structure;
laying an object on and in direct contact with the third portion, wherein the carbon nanotube structure is located between the sheet structure and the object, and a surface of the object being in direct contact with the third portion has a surface roughness less than or equal to 1.0 micrometer; and
applying a pressure to the object to make the object bonded to the substrate surface and forming a structure comprising the substrate, the sheet structure, the carbon nanotube structure and the object.

US Pat. No. 10,483,209

IMPEDANCE CONTROLLED ELECTRICAL INTERCONNECTION EMPLOYING META-MATERIALS

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a plurality of layers to be secured to provide electrical interconnection between a plurality of first bond pads of a first device and a plurality of second bond pads of a second device, wherein the plurality of layers includes:
a first conductor layer arranged to extend continuously along a portion of a length of the first device and the second device, such that the first conductor layer physically contacts the plurality of first bond pads of the first device and the plurality of second bond pads of the second device when secured;
a second conductor layer disposed over the first conductor layer, wherein the second conductor layer includes a plurality of electrically independent conductors arranged to span a length that is about the portion of the length of the first device and the second device when secured; and
a third conductor layer disposed over the second conductor layer, such that the second conductor layer is disposed between the first conductor layer and the third conductor layer, wherein the third conductor layer is arranged to extend continuously along the portion of the length of the first device and the second device when secured.

US Pat. No. 10,483,208

INTERCONNECTION STRUCTURE, FABRICATING METHOD THEREOF, AND SEMICONDUCTOR DEVICE USING THE SAME

Taiwan Semiconductor Manu...

1. A device comprising:a multi-gate transistor, the multi-gate transistor including an epitaxial source/drain region;
a dielectric layer overlying the epitaxial source/drain region;
a contact extending through an opening in the dielectric layer and electrically contacting the epitaxial source/drain region, the contact including:
a silicide layer contacting the epitaxial source/drain region, wherein a Si concentration of the silicide is varied along a height of the silicide;
a barrier layer contacting the silicide layer;
a metal layer contacting the barrier layer and contacting sidewalls of the opening in the dielectric layer, wherein the silicide layer is a silicide of the epitaxial source/drain region and the metal layer; and
a conductor contacting the barrier layer, wherein the barrier layer extends between and separates the conductor and the silicide layer.

US Pat. No. 10,483,207

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a first semiconductor region of a first conductivity type;
a stacked body provided on the first semiconductor region, the stacked body including a plurality of electrode layers stacked with an insulating body interposed, the stacked body including a first stacked portion and a second stacked portion, the plurality of electrode layers of the second stacked portion including a plurality of terrace portions arranged in a staircase configuration with a level difference in a first direction;
a first columnar portion extending through the first stacked portion in a stacking direction of the stacked body and including a first semiconductor body contacting the first semiconductor region;
an insulating layer provided on the plurality of terrace portions;
a plurality of contact portions extending through the insulating layer in the stacking direction and contacting the plurality of terrace portions;
a second columnar portion extending through the insulating layer and through the second stacked portion in the stacking direction, and including a second semiconductor body contacting the first semiconductor region; and
a first insulating portion dividing the first semiconductor region in the first direction, the first insulating portion provided under a boundary portion between the first stacked portion and the second stacked portion.

US Pat. No. 10,483,206

DEVICE COMPRISING NANOSTRUCTURES AND METHOD OF MANUFACTURING THEREOF

Waqas Khalid, Berkeley, ...

1. A method for manufacturing of a device comprising a first substrate comprising a plurality of sets of nanostructures arranged on said first substrate, wherein each of said sets of nanostructures is individually electrically addressable, said method comprising the steps of:providing a substrate having a first face, said substrate having an insulating layer comprising an insulating material arranged on said first face of said substrate forming an interface between said insulating layer and said substrate;
providing a plurality of stacks on said first substrate, said stacks being spaced apart from each other, wherein each stack comprises a first conductive layer comprising a first conductive material and a second conductive layer comprising a second conductive material different from said first material, said second conductive layer being arranged on said first conductive layer for catalyzing nanostructure growth; heating said first substrate having said plurality of stacks arranged thereon in a reducing atmosphere to enable formation of nanostructures on said second conductive material;
heating said first substrate having said plurality of stacks arranged thereon in an atmosphere such that nanostructures are formed on said second layer; wherein said insulating material and said first conductive material are selected such that during said heating steps, said first conductive material interacts with said insulating material to form an electrically conductive portion within said insulating layer below each of said stacks, wherein said electrically conductive portion comprises a mixture of said first conductive material and said insulating material and/or reaction adducts thereof.

US Pat. No. 10,483,197

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a first connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package, the first connection member including an insulating member and a first redistribution layer embedded in the insulating member and having exposed regions in the second surface;
a semiconductor chip having an active surface having connection electrodes disposed thereon, and an inactive surface opposing the active surface in the stacking direction and disposed on the first connection member, the inactive surface facing the second surface of the first connection member;
an encapsulant disposed on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region positioned in the vicinity of the semiconductor chip;
a second redistribution layer including connection vias penetrating through the first region of the encapsulant and connected to the connection electrodes, through-vias penetrating through the second region of the encapsulant and connected to the exposed regions of the first redistribution layer, and a wiring pattern disposed on the encapsulant and having an integrated structure with the connection vias and the through-vias; and
a second connection member having a third surface disposed on the encapsulant and a fourth surface opposing the third surface in the stacking direction, the second connection member including a third redistribution layer connected to the second redistribution layer,
wherein an area of a surface of at least one of the through-vias adjacent to the first connection member is smaller than an area of a surface of the at least one of the through-vias adjacent to the second connection member.

US Pat. No. 10,483,193

ELECTRICAL CONNECTIVITY FOR CIRCUIT APPLICATIONS

Infineon Technologies Ame...

1. A method comprising:aligning a face of a chip substrate with respect to an electrically conductive surface of a host substrate, the chip substrate fabricated to include first switch circuits and second switch circuits, a sequence of nodes of the second switch circuits disposed on the face of the chip substrate alongside and substantially parallel to a sequence of nodes of the first switch circuits; and
coupling the sequence of nodes of the first switch circuits and the sequence of nodes of the second switch circuits to an electrically conductive surface of the host substrate.

US Pat. No. 10,483,191

BOTTOM PACKAGE EXPOSED DIE MEMS PRESSURE SENSOR INTEGRATED CIRCUIT PACKAGE DESIGN

STMICROELECTRONICS, INC.,...

1. A package containing a MEMS sensor circuit, comprising:a lead frame having an open region in a middle of the lead frame and a first surface exposed to an ambient atmosphere;
a monolithic MEMS semiconductor die being laterally adjacent to the lead frame, the monolithic MEMS semiconductor die having an exposed outer surface thereof exposed to the ambient atmosphere, the exposed outer surface having a plurality of apertures, the plurality of apertures exposing an internal chamber of the monolithic MEMS semiconductor die to the ambient atmosphere;
a second semiconductor die attached to the monolithic MEMS semiconductor die;
a first plurality of bonding wires connected between the lead frame and the second semiconductor die;
a second plurality of bonding wires connected at least between one of the lead frame and the monolithic MEMS semiconductor die or the monolithic MEMS semiconductor die and the second semiconductor die; and
a molding compound partially covering the monolithic MEMS semiconductor die and the lead frame and encapsulating the second semiconductor die and the plurality of bonding wires, a first surface of the molding compound being flush with the exposed outer surface of the monolithic MEMS semiconductor die and also with the first surface of the lead frame, the exposed outer surface of the monolithic MEMS semiconductor die being a semiconductor material, and an opening of the apertures being flush with the first surface of the molding compound.

US Pat. No. 10,483,183

SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor element;
a temperature detecting element provided at a central part of a surface of the semiconductor element; and
a heat conductor jointed to the surface of the semiconductor element via a jointing element,
wherein
the jointing element comprises a central part positioned over the temperature detecting element, and a peripheral part positioned on a periphery of the central part of the jointing element, and
the heat conductor comprises a metal part being in contact with the central part of the jointing element, and a graphite part being in contact with the peripheral part of the jointing element.

US Pat. No. 10,483,179

SEMICONDUCTOR DEVICE WITH SEALING PORTION TO SUPPRESS CONNECTION CORROSION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor element having a first pad formed of AlSiCu or AlCu;
a frame member having a second pad;
a connection member that contains at least one of copper and silver and connects the first pad and the second pad; and
a sealing portion that is formed of resin composition containing no sulfur in excess of 100 ppm as measured by extraction from the sealing portion by ion chromatographic analysis under an extraction condition that the temperature is 150° C. and the duration of time is 100 hours, the sealing portion sealing the semiconductor element, the frame member, and the connection member,
wherein arithmetic mean roughness of an upper surface of the first pad is equal to or greater than 0.02 ?m.