US Pat. No. 10,191,899

SYSTEM AND METHOD FOR UNDERSTANDING TEXT USING A TRANSLATION OF THE TEXT

Comigo Ltd., Yarkona (IL...

1. A method for automatically determining content of a text associated with video media content and for generating an output based on the content, the method comprising:a) obtaining, by a processor associated with a media playing device or with a set top box feeding said media playing device, a first segment of text in a first language, said first segment of text being part of subtitles in said first language of video media content played by said media playing device, said subtitles in said first language being generated prior to initiating playing of said video media content by said media playing device;
b) obtaining, by said processor, a second segment of text in a second language, said second segment of text being part of subtitles in said second language of said video media content played by said media playing device, said second segment of text being a translation of said first segment of text, said subtitles in said second language being generated prior to initiating playing of said video media content by said media playing device;
c) using said processor, automatically determining content of said first segment of text, in accordance with a predefined analysis rule, said automatically determining of said content of said first segment of text being done while said media playing device is playing said video media content, said rule including:
i) initially automatically analyzing said first segment of text without using said second segment of text, thereby attempting to unambiguously determine said content of said first segment of text;
ii) in response to determining, during said analyzing of said first segment of text, that said first segment of text contains no ambiguous words which have multiple meanings in said first language, automatically and unambiguously determining said content of said first segment of text;
iii) in response to identifying, during said analyzing of said first segment of text, one or more ambiguous words in said first segment of text which have multiple meanings in said first language, for at least one identified ambiguous word having multiple meanings in said first language:
A) automatically identifying a corresponding word of said second language that appears in said second segment of text and is a translation of said identified ambiguous word;
B) automatically determining whether said corresponding word has an unambiguous meaning in said second language; and
C) in response to determining that said corresponding word has an unambiguous meaning in said second language, automatically assigning said unambiguous meaning of said corresponding word to said identified ambiguous word, and automatically and unambiguously determining said content of said first segment of text based on said assigned unambiguous meaning;
d) generating a recommendation based on said determined content of said first segment of text, said recommendation being for content associated with said video media content or with said first segment of text; and
e) outputting, by said processor, said recommendation.

US Pat. No. 10,191,898

REPRESENTATION OF PEOPLE IN A SPREADSHEET

Microsoft Technology Lice...

1. A computer system, comprising:at least one processing unit; and
at least one memory storing computer-readable instructions that when executed by the at least one processing unit cause the computer system to perform a method for representing a person within a spreadsheet, the method comprising:
determining that a spreadsheet operation involves a person object, wherein the person object comprises a plurality of fields including at least a name and a contact action, wherein the spreadsheet operation treats the person object in a same manner as one or more native spreadsheet objects of the spreadsheet, and wherein the person object is acted upon in a same manner as the one or more native spreadsheet objects; and
in response to determining that the spreadsheet operation involves the person object, configuring a view of the spreadsheet based on a person represented by the person object, wherein configuring the view comprises filtering or sorting the one or more native spreadsheet objects based on the person represented by the person object.

US Pat. No. 10,191,897

DATA FLOW VIEW FOR A SPREADSHEET

Workday, Inc., Pleasanto...

1. A system for a data flow view for a spreadsheet, comprising:an input interface to receive a first spreadsheet and an indication of a spreadsheet cell of interest being located on the first spreadsheet; and
a processor to:
determine a first set of spreadsheet cells that the spreadsheet cell of interest depends on, comprising to:
determine whether a first cell of the spreadsheet cell of interest depends on a second cell of a second spreadsheet, the first spreadsheet being different from the second spreadsheet; and
in response to a determination that the first cell of the spreadsheet cell of interest depends on a second cell of second spreadsheet, add the second cell to the first set of spreadsheet cells;
determine a second set of spreadsheet cells that depends on the spreadsheet cell of interest, comprising to:
determine whether a third cell of third spreadsheet depends on the first cell of the spreadsheet cell of interest, the third spreadsheet being different from the first spreadsheet; and
in response to a determination that the third cell of third spreadsheet depends on the first cell of the spreadsheet cell of interest, add the third cell to the second set of spreadsheet cells;
determine whether a fourth cell of the first set of spreadsheet cells matches a fifth cell of the second set of spreadsheet cells;
in response to a determination that the fourth cell matches the fifth cell, omit including the fourth cell in the first set of spreadsheet cells or the fifth cell in the second set of spreadsheet cells;
provide a spreadsheet cell data flow view for the spreadsheet cell of interest based at least in part on the first set of spreadsheet cells and the second set of spreadsheet cells, comprising to:
determine a new first set of spreadsheet cells that a new spreadsheet cell of interest depends on, wherein a first arrow indicates that the new spreadsheet cell of interest depends on a spreadsheet cell of the new first set of spreadsheet cells; and
determine a new second set of spreadsheet cells that depends on the new spreadsheet cell of interest, wherein a second arrow indicates that a spreadsheet cell of the new second set of spreadsheet cells depends on the new spreadsheet cell of interest; and
in response to a determination that an indication of a new spreadsheet cell of interest is received:
provide a spreadsheet cell data flow view for the new spreadsheet cell of interest.

US Pat. No. 10,191,896

POPULATING USER DATA

SKYPE, Dublin (IE)

1. A computer system for receiving user data comprising:a user terminal having a processor arranged to execute a data receiving application, wherein the data receiving application provides at least one street address field for a transaction, and wherein the user terminal is configured to:
receive user input to commence the transaction; and
issue, responsive to the user input, a notification that a street address for the transaction is required; and
a geographical location device in communication with a location network and arranged to receive the notification, and to identify a geographical location of the user terminal using information from the location network, the geographical location device operable to provide location data from which street address data of a user address is derived and supplied to the data receiving application to automatically communicate the street address data to the data receiving application for populating to the street address field for the transaction.

US Pat. No. 10,191,895

ADAPTIVE MODIFICATION OF CONTENT PRESENTED IN ELECTRONIC FORMS

Adobe Systems Incorporate...

1. A method for adaptively modifying interactive content provided over a network via electronic forms, wherein the method includes one or more processing devices performing operations comprising:transmitting, via a data network and to a first plurality of clients, a first plurality of messages that provide electronic access to a first version of an electronic form, wherein the first version of the electronic form includes first form content with a field configured for receiving narrative content;
receiving, via the first version of the electronic form and from the first plurality of clients, first responsive client communications;
dynamically generating a second version of the electronic form that omits or replaces the first form content associated with a first data category and maintains a second form content associated with a second data category, wherein dynamically generating the second version of the electronic form comprises:
(i) determining that fewer than a threshold number of the first responsive client communications includes data for the field configured for receiving narrative content,
(ii) responsive to determining that fewer than the threshold number of the first responsive client communications includes the data for the field configured for receiving narrative content, determining that the second version of the electronic form includes a field restricted to receiving a discrete value from a specified set of values, wherein the field configured for receiving narrative content and the field restricted to receiving the discrete value from the specified set of values are used for obtaining data in a common data category, and
(iii) selecting the second version of the electronic form based on the second version of the electronic form having the field restricted to receiving the discrete value from the specified set of values rather than the field configured for receiving narrative content; and
transmitting, via the data network and to a second plurality of clients, a second plurality of messages that provide electronic access to the second version of the electronic form.

US Pat. No. 10,191,894

MOBILE DATA AND HANDWRITING SCREEN CAPTURE AND FORWARDING

Microsoft Technology Lice...

1. A computing system comprising:a first memory storing computer-executable instructions configured to control the computing system to:
receive, from a device including a display and a second memory, a screen shot of current display content of the second memory with annotation data related to the current display content appended to the screen shot by the device; and
store in a data store the screen shot with the appended annotation data; and
a processor configured to execute the computer-executable instructions stored in the first memory.

US Pat. No. 10,191,891

INTERACTIVE PREVIEW TEASERS IN COMMUNICATIONS

Microsoft Technology Lice...

1. A computing device to provide rich visualization of embedded objects, attachments, and links within emails through teasers, the computing device comprising:a memory configured to store instructions; and
one or more processors coupled to the memory, the one or more processors configured to execute, in conjunction with the instructions stored in the memory, a communication application, wherein the one or more processors are configured to:
provide a conversation to be displayed on a conversation user interface, the conversation comprising a plurality of email messages;
detect an embedded object within an email message of the plurality of email messages;
analyze the embedded object to determine one or more teaser components, each of the one or more teaser components including a portion of textual or graphical content included in the embedded object;
conducting a search of an external source for additional information associated with the embedded object based on content included in at least one of the one or more teaser components;
construct a teaser including at least one of the one or more teaser components and the additional information; and
provide the teaser to be displayed within a body of the email message or on a dedicated portion of the conversation user interface without requiring a user to open the email message in a separate user interface.

US Pat. No. 10,191,890

PERSISTENT VIEWPORTS

Microsoft Technology Lice...

1. A method, comprising acts of:identifying an element-of-interest in content of a virtual document, the element-of-interest in a viewport of the virtual document presented on a passive user system;
receiving an update to the content of the virtual document from an active user system;
determining that the update will change the position of the element-of-interest in the viewport on the passive user system and cause the position of the viewport to be adjusted in order for the element-of-interest to be persisted within the viewport;
causing, based on determining that the update will change the position of the element-of-interest in the viewport on the passive user system and cause the position of the viewport to be adjusted in order for the element-of-interest to be persisted within the viewport, an update notification to be displayed by the passive user system, the update notification providing an option to delay incorporation of the update into the virtual document presented on the passive user system;
receiving a selection in response to the update notification; and
causing, in response to receiving the selection, the passive user system to delay input of the update and queue the update for entry into the virtual document presented on the passive user system.

US Pat. No. 10,191,889

SYSTEMS, APPARATUSES AND METHODS FOR GENERATING A USER INTERFACE BY PERFORMING COMPUTER VISION AND OPTICAL CHARACTER RECOGNITION ON A GRAPHICAL REPRESENTATION

Board of Regents, The Uni...

1. A method for at least partially automating the generation of a user interface for a mobile application, the method comprising:performing computer vision processing on an original graphical representation of a proposed user interface, identifying atomic elements within the original graphical representation, and generating a view hierarchy image having one bounding box for each atomic element;
performing optical character recognition on the original graphical representation, identifying words and lines of text within the original graphical representation, and generating a first word image comprising one bounding box per word and a second word image comprising one bounding box per line;
merging the view hierarchy image and the first word image, removing words that conflict with the bounding boxes of the view hierarchy image, and generating a modified first word image;
merging words from the modified first word image and lines from the second word image into text blocks, grouping words that belong together, splitting words that do not belong together, and generating a third word image comprising one bounding box per valid word;
merging the original graphical representation with the third word image and generating a modified graphical representation comprising text boxes and images;
merging the modified graphical representation with the view hierarchy image and generating a modified view hierarchy image that comprises the text boxes and unknown vision boxes;
traversing a vision box hierarchy of the modified view hierarchy image and generating an OS-specific view hierarchy image that comprises image views, text views, and container views;
determining if there are repeated items in the OS-specific view hierarchy image, creating a list view for any repeated items in the OS-specific view hierarchy image, and generating a modified OS-specific view hierarchy image comprising list view items; and
using at least the modified graphical representation and the modified OS-specific view hierarchy image as an input and generating an OS-specific project directory that comprises OS-specific source code and resource files, wherein the OS-specific project directory is capable of being compiled to produce an OS-specific functional executable application having a graphical user interface that emulates the original graphical representation.

US Pat. No. 10,191,887

CONTEXT AFFINITY IN A REMOTE SCRIPTING ENVIRONMENT

Microsoft Technology Lice...

1. A computer-implemented method for providing context affinity in a remote scripting environment by creating a plurality of runspaces, each of the plurality of runspaces associated with a connection between a local computer and a remote computer, wherein each of the plurality of runspaces is associated with a global context object, the method comprising:initiating, on the local computer that transmits remote session commands, a remote scripting component;
creating, by the remote scripting component, a connection between the local computer and the remote computer, wherein said creating the connection creates a particular run space of the plurality of runspaces;
initiating, by the remote scripting component, a global context object associated with the connection, wherein the global context object includes a variable providing a context to execute one or more remote session commands via the particular runspace;
determining, by the remote scripting component at the local computer, that a connection pool is available from a dictionary stored on the local computer, wherein the connection pool is associated with the plurality of runspaces;
based at least partly on a determination that the connection pool is available, determining, by the remote scripting component that the connection between the local computer and the remote computer is available in the connection pool;
based at least partly on a determination that the connection between the local computer and the remote computer is available in the connection pool:
sending, by the remote scripting component from the local computer to the remote computer via the connection, a first remote session command to be executed by the remote computer in the particular runspace;
sending, by the remote scripting component from the local computer to the remote computer via the connection, the global context object;
receiving, by the remote scripting component at the local computer, result data based at least partly on execution of the first remote session command within the particular runspace based on the variable included in the global context object providing the context for the particular runspace;
updating, by the remote scripting component based at least in part on the result data, the global context object at the local computer to generate an updated global context object; and
sending, by the remote scripting component from the local computer to the remote computer, the updated global context object with a second remote session command to be executed by the remote computer in the particular runspace;
wherein the second remote session command is executed within the particular runspace using the updated global context object as updated after execution of the first remote session command;
wherein the global context object creates a context affinity between the first remote session command executed by the remote computer and the second remote session command executed by the remote computer;
wherein creating a context affinity between the first remote session command and the second remote session command executed by the remote computer includes using both the connection and the global context object when executing the first remote session command and the second remote session command; and
wherein each of the plurality of runspaces maintains a global context object and wherein the global context object of a runspace allows two or more commands to be executed within the runspace when the two or more commands do not share a common context by defining a new shared context for executing the two or more commands.

US Pat. No. 10,191,886

GESTURE CONTROLLED CALCULATOR

1. A gesture controlled calculator comprising:a) a touch screen input device and output device;
b) a microprocessor; and
c) a permanent memory comprising computer code to cause said microprocessor to carry out the steps of:
i) receive from a user through a virtual keyboard presented in said touch screen a multiplication problem, said multiplication problem comprising a multiplicand and a multiplier wherein said multiplicand and multiplier each comprise one or more digits and wherein each of said digits is associated with a place value;
ii) upon receipt of said multiplication problem, display on said touch screen:
(1) a work plan area comprising:
(a) said multiplication problem; and
(b) a planning arrow touch target;
(2) a multiplication machine area; and
(3) a totals tracker area;
iii) upon receipt of at least a touch gesture from said user in said planning arrow, carry out the steps of:
(1) separate said multiplication problem into one or more easy multiplication problems wherein each of said easy multiplication problems comprises:
(a) one of said digits of said multiplier with said digit's place value preserved; and
(b) said multiplicand;
(2) display each of said easy multiplication problems in said work plan area; and
(3) display a horizontal selection arrow touch target next to each of said easy multiplication problems;
iv) upon receipt of at least a touch gesture from said user in one of said selection arrow touch targets associated with one of said easy multiplication problems, carry out the steps of:
(1) move said selected easy multiplication problem into said times machine area;
(2) display in a header of said times machine area a very easy multiplication problem associated with said selected easy multiplication problem, said very easy multiplication problem comprising:
(a) the multiplier digit of said selected easy multiplication problem without its place value preserved; and
(b) said multiplicand;
(3) display below said header a stack of said multiplicands wherein:
(a) the number of said multiplicands in said stack is equal to said multiplier digit of said selected easy multiplication problem; and
(b) the digits of said multiplicands in said stack are aligned in columns;
(4) display around each digit of said multiplicands in said stack a virtual digit card;
(5) display an equals bar below said stack of said multiplicands;
(6) display said selected easy multiplication problem at the bottom of said multiplication machine in a problem statement box; and
v) upon receipt of at least a touch gesture from said user in one of said digit cards in one of said columns of digit cards, carry out the steps of:
(1) move all of said digit cards in said selected column of digit cards below the equals bar;
(2) overlap said digits cards in said selected column of digit cards to form a single digit card in a solution position below said equals bar;
(3) display the sum of said digit cards in said selected column of digit cards in said single digit card below said equals bar;
(4) when said sum of said digit cards in said solution position is a two digit number comprising a tens digit and a ones digit, carry out the steps of:
(a) upon receipt of at least a touch gesture by said user in said digit card in said solution position, carry out the steps of:
(i) display a digit card above the next left most column of said digit cards and display said tens digit therein; and
(ii) display said ones digit in said digit card in said solution position;
(5) when all of said digit cards in said stack of multiplicands have been moved below said equals bar and the sums thereof are displayed in digit cards in solution positions below said equals bar, carry out the steps of:
(a) display the solution to said selected easy multiplication problem next so said easy multiplication problem displayed in said solution box;
(b) display a horizontal transport arrow touch target next to said solution to said selected easy multiplication problem; and
(6) upon receipt of at least a touch gesture in said transport arrow, carry out the steps of:
(a) move said solution to said selected easy multiplication problem to an appropriate row in said totals tracker area; and
(b) upon the movement of the solutions of all of said easy multiplication problems to said totals tracker area, carry out the steps of:
(i) present virtual digit cards around each digit of said solutions to said easy multiplication problems displayed in said totals tracker area such that said digits of said solutions to said easy multiplication problems are in columns in said totals tracker area;
(ii) upon receiving at least a touch gesture in one of said digit cards in one of said columns in said totals tracker area, carry out the steps of:
1) move all of said digit cards in said selected column in said totals tracker area below an equals bar in said totals tracker area;
2) overlap said digit cards from said selected column in said totals tracker area to form a single digit card in a solution area in said totals tracker area;
3) display within said digit card in said solution area of said totals tracker area the sum of said digit cards in said selected column in said totals tracker area;
4) when said sum of said digit cards in said selected column in said totals tracker area is a two digit number comprising a tens digit and a ones digit, carry out the steps of:
a) display said tens digit of said two digit number in said digit card in said solution area of said totals tracker area in a digit card above the top row of the next left column of said digit cards in said totals tracker area; and
b) display said ones digit of said two digit number in said digit card in said solution area of said totals tracker area; and
(iii) when all of said digit cards in said totals tracker area have been moved below said equals bar in said totals tracker area, display the solution to said multiplication problem in said solution area of said totals tracker area.

US Pat. No. 10,191,884

MANAGING A MULTI-LANE SERIAL LINK

Hewlett Packard Enterpris...

1. A method for managing a multi-lane serial link, comprising:establishing a serial link between a number of integrated circuits across a first number of lanes, in which the first number of lanes comprises a subset of a number of available lanes on the serial link;
selecting to change a transmission state of a second number of lanes, in which the second number of lanes comprises a subset of the available lanes;
changing the transmission state of the second number of lanes while transmitting data on a number of remaining lanes; and
after receiving an indication that the transmission state of the second number of lanes has been changed, synchronizing the first number of lanes and the second number of lanes.

US Pat. No. 10,191,882

METHOD AND SYSTEM FOR AGGREGATION-FRIENDLY ADDRESS ASSIGNMENT TO PCIE DEVICES

Futurewei Technologies, I...

1. A peripheral component interconnect express (PCI-e) system comprising:a processor operable to perform a method of assigning addresses to nodes of a topology tree of the PCI-e system, comprising:
(a) assigning addresses to the PCI-e topology tree, said (a) comprising:
traversing, at a level and in a breadth direction, down-link couplings to an interconnection of the PCI-e system;
ascertaining, at the level, which of the down-link couplings are connected to nodes, and incrementing an update counter based on detection of an additional depth level; and
assigning contiguous addresses, at the level, to nodes of ascertained down-link couplings that have nodes;
(b) propagating the level of the PCI-e topology tree, said (b) comprising:
traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e system;
ascertaining, at the level, which of the down-link couplings are coupled to other interconnections in the depth direction; and
consecutively proceeding, in the depth direction, to a next level of down-link coupling of a next interconnection; and
(c) repeating alternately (a) and (b) until the nodes are assigned addresses, wherein, if there are no down-link couplings at the level, proceeding up to a previous level based on the update counter to ascertain additional down-link couplings.

US Pat. No. 10,191,881

MODIFICATIONS TO A STREAM PROCESSING TOPOLOGY DURING PROCESSING OF A DATA STREAM

Hewlett Packard Enterpris...

1. A method comprising:receiving a first topology that communicatively couples a plurality of processing elements via a first arrangement of interconnections to perform an operation on a stream of data;
defining a second topology that communicatively couples the plurality of processing elements via a second arrangement of interconnections that is different from the first arrangement of interconnections to perform the operation on the stream of data, wherein the second topology assigns the plurality of processing elements a first set of operations;
providing the second topology to a stream processing manager;
modifying the second topology during processing of the stream of data by assigning a second set of operations to the plurality of processing elements that is different from the first set of operations; and
processing the stream of data according to the modified second topology without providing the modified second topology to the stream processing manager.

US Pat. No. 10,191,877

ARCHITECTURE FOR SOFTWARE DEFINED INTERCONNECT SWITCH

Intel Corporation, Santa...

21. A system comprising:a plurality of hosts, wherein each host comprises a respective processor device;
a plurality of devices; and
a switch comprising a control host, wherein the plurality of hosts are connected to respective upstream ports of the switch, the plurality of devices are connected to respective downstream ports of the switch, and the control host comprises:
a dedicated processor device;
memory; and
software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide one or more enhanced routing capabilities,
wherein the enhanced routing capabilities comprise:
a simple assignment capability to dynamically assign one or more of the devices to respective hosts of the switch; and
a virtual assignment capability to define virtual partitions of resources provided by the devices and assign each partition to a respective one of the hosts.

US Pat. No. 10,191,875

TECHNIQUES OF PROVIDING SERIAL PORT IN NON-LEGACY SYSTEM VIA EMBEDDED-SYSTEM DEVICE

AMERICAN MEGATRENDS, INC....

1. A method of operating an embedded-system device, comprising:receiving first command or data through a first serial port of the embedded-system device;
exposing a second serial port to a host of the embedded-system device such that the host has control over the second serial port and receiving second command or data from the host for outputting at the second serial port;
redirecting the first command or data to the second serial port when the embedded-system device is in a first mode; and
allowing the second command or data to be output at the second serial port when the embedded-system device is in a second mode;
wherein the redirecting the first command or data includes, in the first mode:
constructing third command or data based on the first command or data; and
sending the third command or data to the second serial port for outputting.

US Pat. No. 10,191,874

METHOD AND APPARATUS FOR PROVIDING USB POWER DELIVERY NEGOTIATED THROUGH A DEDICATED TRANSMISSION CHANNEL

MICROCHIP TECHNOLOGY INCO...

1. A USB interface to provide power delivery negotiated through a dedicated transmission channel, the USB interface comprising:a transmitter circuit including a digital-to-analog converter having an output coupled with an input of a transmission filter;
a receiver circuit including an analog-to-digital converter having an input coupled with an output of a receiving filter; and
a switching circuit configured in a first operating mode of the USB interface to connect an output of the transmission filter and an input of the receiving filter to a first connection node of the dedicated transmission channel.

US Pat. No. 10,191,873

METHOD AND APPARATUS FOR POWER REDUCTION FOR DATA MOVEMENT

Advanced Micro Devices, I...

1. A method in a device, of transferring data including:determining by a controller a first difference between a first transferred data segment and a first data segment to be transferred of a plurality of data segments to be transferred;
determining by the controller a second difference between the first transferred data segment and a second data segment to be transferred of the plurality of data segments to be transferred, the second data segment being separate from the first data segment;
determining by the controller an ordered second data segment based on the first difference and the second difference to re-create an order of the ordered second data segment relative to the first data segment, the ordered second data segment being the data segment to be transferred having the smallest difference relative to the first transferred data segment; and
transmitting by the transmitter the ordered second data segment as the next data segment of the plurality of data segments to be transferred that is transferred after transfer of the first data segment.

US Pat. No. 10,191,872

SEMICONDUCTOR DEVICE AND CONTROL METHOD OF SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a CPU section configured to execute a plurality of software modules; and
a hardware IP configured to perform processing based on operation requests transmitted by the CPU section,
wherein the hardware IP includes
a first storage unit including a plurality of control receiving units configured to receive the operation requests transmitted by respective ones of the software modules,
a calculation unit configured to perform processing based on the operation requests transmitted from the control receiving units to generate response information, and
an arbitration unit configured to control information transmission between the control receiving units and the calculation unit such that the calculation unit receives only one of the operation requests at a time from any one of the control receiving units, and
wherein, while forming a first information transmission path between the calculation unit and one of the control receiving units, the arbitration unit transmits the operation request output from the one of the control receiving units to the calculation unit and transmits the response information generated based on the transmitted operation request from the calculation unit to the one of the control receiving units.

US Pat. No. 10,191,871

SAFE DOUBLE BUFFERING USING DMA SAFE LINKED LISTS

Infineon Technologies AG,...

1. A Direct Memory Access (DMA) controller, comprising:a set of transaction control registers configured to receive a sequence of transaction control sets which are arranged in a linked list and which collectively describe a data transfer by which the DMA controller is to move data, wherein the data transfer is to move the data from a peripheral and alternatingly to a first memory buffer and a second memory buffer, the first and second memory buffers being arranged in parallel with one another at an interface of the peripheral; and
wherein the DMA controller is configured to transfer a first portion of the data from the peripheral to the first memory buffer according to a first transaction control set in the sequence, and is configured to subsequently transfer a second portion of the data from the peripheral to the second memory buffer according to a second transaction control set in the sequence; and
an integrity checker configured to determine an actual error detection code based on the first and/or second portions of the data or an address actually processed by the DMA controller during execution of the first and/or second transaction control sets, the integrity checker being further configured to selectively flag an error based on whether the actual error detection code is the same as an expected error detection code contained in a third transaction control set in the sequence.

US Pat. No. 10,191,867

MULTIPROCESSOR SYSTEM HAVING POSTED TRANSACTION BUS INTERFACE THAT GENERATES POSTED TRANSACTION BUS COMMANDS

Netronome Systems, Inc., ...

1. An integrated circuit comprising a plurality of rectangular islands disposed in a two-dimensional array, wherein the rectangular islands are intercoupled by a posted transaction bus, wherein one of the rectangular islands comprises:a first processor;
a second processor that executes the same instruction set that the first processor executes; and
an interface means for receiving addresses from the first processor via a first bus and for receiving addresses from the second processor via a second bus and for interfacing to the posted transaction bus, wherein neither the first bus nor the second bus is a posted transaction bus, wherein an address received by the interface means via the first bus is an address in shared address space shared by the first and second processors, wherein the interface means generates a posted transaction bus read command from the address received via the first bus and causes a posted transaction bus read transaction to occur using the generated posted transaction bus read command such that read data is obtained from the posted transaction bus and is then stored into a shared memory in the interface means at a memory location indicated by the first processor.

US Pat. No. 10,191,866

MEMORY CONTROLLER FOR SELECTIVE RANK OR SUBRANK ACCESS

1. A memory controller integrated circuit, comprising:transaction queue circuitry to implement transaction queues;
a register to store a selective one of a first mode select value and a second mode select value;
command path circuitry to receive memory access commands from the transaction queues and to transmit the memory access commands to first and second memory devices over a common command path connection; and
data exchange circuitry to exchange data with the first and second memory devices via respective first and second data paths; wherein based on the first mode select value the command path circuitry is to drive the common command path connection responsive to a single one of the transaction queues, and the data exchange circuitry is to responsively exchange data via both of the respective first and second data paths in association with each memory access command from the single one of the transaction queues; and
wherein based on the second mode select value
the command path circuitry is to is to drive the common command path connection to time-multiplex first and second memory access commands from respective transaction queues, and
the data exchange circuitry is to concurrently exchange first data in association with the first memory access command via the first data path and second data in association with the second memory access command via the second data path.

US Pat. No. 10,191,865

CONSOLIDATING WRITE TRANSACTIONS FOR A NETWORK DEVICE

Amazon Technologies, Inc....

1. A network device comprising:a network interface operable to send and receive a packet;
a bus interface operable to send and receive bus traffic on a bus; and
processing logic coupled to the bus interface and the network interface, wherein the processing logic is operable to:
store information associated with the packet in a queue;
mask interrupts for the network device;
send an interrupt to a host processor to notify the host processor of completion of packet processing;
receive, by the bus interface, a Memory-Mapped Input/Output (MMIO) write transaction that includes an update for a pointer associated with a completion queue and an interrupt unmasking value;
update the pointer associated with the completion queue; and unmask the interrupts for the network device based on the MMIO write transaction.

US Pat. No. 10,191,864

STANDARDIZED INTERFACE FOR STORAGE USING AN INPUT/OUTPUT (I/O) ADAPTER DEVICE

Amazon Technologies, Inc....

1. An Input/Output (I/O) adapter device comprising:a storage device interface configured to communicate with a first storage device and a second storage device communicatively coupled to the I/O adapter device;
a host interface configured to communicate with a host device communicatively coupled to the I/O adapter device, wherein the host device is configured to run an operating system and wherein the operating system executes a standardized storage frontend driver to communicate with the I/O adapter device through the host interface and using a standardized interface implemented in the operating system; and
a processing core communicatively coupled to the storage device interface and to the host interface, wherein the processing core is configured to execute a plurality of computer-executable instructions to execute:
a first emulated storage backend driver to communicate with the standardized storage frontend driver through the host interface using the standardized interface, and to communicate with the first storage device, to provide the standardized storage frontend driver with access to the first storage device; and
a second emulated storage backend driver to communicate with the standardized storage frontend driver through the host interface using the standardized interface, and to communicate with the second storage device, to provide the standardized storage frontend driver with access to the second storage device.

US Pat. No. 10,191,859

MEMORY ACCESS PROTECTION APPARATUS AND METHODS FOR MEMORY MAPPED ACCESS BETWEEN INDEPENDENTLY OPERABLE PROCESSORS

Apple Inc., Cupertino, C...

1. A method for providing access to a shared memory resource, comprising:during a boot process of a second processor:
generating, by a first processor, a first window register value associated with the shared memory resource;
transmitting the first window register value from the first processor to a window register of the second processor, the first window register value defining a first extent of address space within the shared memory resource that is directly accessible by the second processor; and
wherein the first extent of address space is mapped to a memory map of the second processor during the boot process.

US Pat. No. 10,191,858

VIRTUAL MACHINE MEMORY LOCK-DOWN

1. A method of memory lock-down, the method comprising:storing, by a guest virtual machine, a secure datum at a location within a memory range;
responsive to storing the secure datum, sending, by the guest virtual machine, a request to disable access to the memory range;
receiving, by a hypervisor from the guest virtual machine, the request to disable access to the memory range;
disabling, by the hypervisor, access to the memory range;
detecting, by the hypervisor, a prohibited access attempt, wherein the prohibited access attempt is an access attempt to the memory range;
responsive to detecting the prohibited access attempt, stopping, by the hypervisor, the guest virtual machine;
receiving, by the hypervisor, a request to reboot the guest virtual machine;
rebooting, by the hypervisor, the guest virtual machine; and
responsive to rebooting the guest virtual machine, enabling, by the hypervisor, access to the memory range.

US Pat. No. 10,191,853

APPARATUS AND METHOD FOR MAINTAINING ADDRESS TRANSLATION DATA WITHIN AN ADDRESS TRANSLATION CACHE

ARM Limited, Cambridge (...

1. An apparatus comprising:an address translation cache having at least one entry, each entry to store address translation data used when converting a virtual address into a corresponding physical address of a memory system;
control circuitry to perform an allocation process to determine the address translation data to be stored in each entry;
the control circuitry arranged when performing the allocation process for a selected entry in the address translation cache:
to perform a page table walk process using a virtual address in order to obtain from a page table a plurality of descriptors including a descriptor identified using the virtual address;
to determine whether predetermined criteria are met by said plurality of descriptors, said predetermined criteria comprising page alignment criteria and attribute match criteria, each descriptor comprising physical address data and attribute data identifying a plurality of attributes, and the attribute match criteria allowing the plurality of descriptors to have different values for a first subset of the attributes when determining that the attribute match criteria is met;
when said predetermined criteria are met, to generate coalesced address translation data from said plurality of adjacent descriptors and to store said coalesced address translation data in said selected entry; and
in absence of said predetermined criteria being met, to generate address translation data from the descriptor identified using the virtual address and to store that address translation data in said selected entry.

US Pat. No. 10,191,852

METHODS AND APPARATUS FOR LOCKING AT LEAST A PORTION OF A SHARED MEMORY RESOURCE

Apple Inc., Cupertino, C...

1. A method for locking a shared memory, comprising:attempting to lock at least a portion of the shared memory by a first processor;
verifying whether a second processor has locked the at least the portion of the shared memory;
responsive to determining that the at least the portion of the shared memory is successfully locked based on the verifying whether the second processor has locked the at least the portion of the shared memory, executing a critical section, the critical section comprising one or more computer instructions accessible only to the first processor; and
otherwise, responsive to determining, based on the verifying whether the second processor has locked the at least the portion of the shared memory, that the at least the portion of the shared memory is not successfully locked, attempting to lock the at least the portion of the shared memory at a later time.

US Pat. No. 10,191,851

METHOD FOR DISTRIBUTED TRANSACTION PROCESSING IN FLASH MEMORY

TSINGHUA UNIVERSITY, Bei...

1. A method for distributed transaction processing in a flash memory, comprising the following steps:S1. performing two-phase commit on a transaction and removing a state log record of a two-phase commit protocol, wherein the function and information stored in the state log record of the two-phase commit protocol is internalized as an operation on flash memory metadata in a transaction interface, thereby removing the step of creating and updating the state transaction log file for the two-phase commit; wherein final commit of a coordinator is used as a distributed transaction end identifier;
S2. in a process of performing the transaction, storing a temporary data object as a shadow version,
using a shadow mapping table to store an address of the shadow version or the state of a page in the transaction processing, wherein the shadow mapping table is a memory structure that records the address of the shadow version in the first phase of the two-phase commit and records the state of the page participating in the transaction in the second phase of the two-phase commit,
using page metadata to record transaction information wherein the page metadata is an out-of-band (OOB) area of a flash memory page,
using a transaction metadata page to record a transaction state wherein the transaction metadata page stored in a transaction state table is used to determine whether the transaction is committed or aborted: the shadow mapping table records commit identifier, and the transaction metadata page records transaction commit, and
using the transaction state table to record an address of the transaction metadata page, wherein the transaction state table is a persistently stored mapping table, and before the transaction metadata page is written, the transaction state table stores a mapping from a transaction identification (ID) to the address of the transaction metadata page; and
S3. when the coordinator or a participant fails, scanning a part of the storage, reading the flash memory metadata, and recovering a FTL mapping table, the shadow mapping table, and the transaction state table to determine the state of the transaction in the two-phase commit with the state log record of the two phase commit protocol removed;
wherein the step S2 further comprises: when the transaction is written, the shadow mapping table stores a location of new data; and
the page metadata records logic page number, the transaction ID, and the quantity of transaction pages, and when the transaction is committed, the location of the new data is updated to the FTL mapping table and changed to a user readable state; the shadow mapping table records a commit identifier, and the transaction metadata page records transaction commit; if the transaction is aborted, the shadow mapping table records an abort identifier, and the transaction metadata page records transaction abort, and the new data is set as invalid;
if a flash memory block is used completely and all transactions on the flash memory block are completed, the flash memory block is marked as a CHECKED block; if there is an uncompleted transaction, the flash memory block is marked as a WAIT block; if the flash memory block is partially used, the flash memory block is marked as an UPDATE block; if the flash memory block is not used, the flash memory block is marked as a FREE block; and the first page of the block is used to differentiate a block state;
when a failure occurs in the two-phase commit process, the FTL mapping table, the shadow mapping table, and the transaction state table are recovered to determine the transaction state, and the WAIT block and the UPDATE block are scanned,
wherein the step S3, when the coordinator or a participant fails, scanning a part of the storage, reading the flash memory metadata, and recovering the FTL mapping table, the shadow mapping table, and the transaction state table to determine the state of the transaction in the two-phase commit, comprises the following steps:
step (1): scanning and finding all UPDATE blocks and WAIT blocks,
step (2): scanning the UPDATE blocks, recovering the FTL mapping table, the shadowing mapping table, and the transaction state table, and determining a transaction state on these blocks: a mapping (Logic Page Number (LPN), transaction ID, (TxID)) is written in page metadata and the transaction metadata page is located before all transaction data ages; and pages on the UPDATE blocks are scanned in sequence; and
step (3): scanning the WAIT block, and reading the transaction identification from the page metadata.

US Pat. No. 10,191,847

PREFETCH PERFORMANCE

International Business Ma...

1. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processor to cause the processor to:receive at least a first request in a plurality of requests to pre-fetch data from a stream in a plurality of streams;
assign a confidence level to the at least the first request based on an amount of confirmations observed in the stream, wherein the at least the first request is in a confident state if the confidence level exceeds a specified phase threshold and wherein the at least the first request is in a non-confident state if the confidence level does not exceed the specified phase threshold;
prioritize requests to prefetch data in the plurality of requests having a higher confidence level than the confidence level of the first request to pre-fetch data;deprioritize requests to prefetch data in the plurality of requests that are associated with respective streams with a low prefetch utilization ratio; anddetermine whether to drop the at least the first request based on the confidence level, based upon a prefetch utilization ratio of the stream, and based upon a memory resource utilization threshold.

US Pat. No. 10,191,846

CACHE MEMORY FOR PARTICULAR DATA

TOSHIBA MEMORY CORPORATIO...

1. A cache unit comprising:a first memory configured to temporarily hold data and an address of the data;
a second memory configured to temporarily hold an address of a particular data set in advance, the particular data being not held by the first memory; and
a controller configured to, when an instruction to load first data is made for a first specified address, search for a storage destination of the first specified address, output the data of the first specified address if the storage destination is the first memory, and output the particular data if the storage destination is the second memory, and configured to, when an instruction to store a specified data at a second specified address is made, judge whether the specified data is the particular data or not, store the second specified address and the specified data into the first memory if the specified data is not the particular data, and store the second specified address into the second memory if the specified data is the particular data.

US Pat. No. 10,191,845

PREFETCH PERFORMANCE

International Business Ma...

1. A method, comprising:receiving at least a first request in a plurality of requests to pre-fetch data from a stream in a plurality of streams;
assigning a confidence level to the at least the first request based on an amount of confirmations observed in the stream, wherein the at least the first request is in a confident state if the confidence level exceeds a specified phase threshold and wherein the at least the first request is in a non-confident state if the confidence level does not exceed the specified phase threshold;
prioritizing requests to prefetch data in the plurality of requests having a higher confidence level than the confidence level of the first request to pre-fetch data;deprioritizing requests to prefetch data in the plurality of requests that are associated with respective streams with a low prefetch utilization ratio; anddetermining whether to drop the at least the first request based on the confidence level, based upon a prefetch utilization ratio of the stream, and based upon a memory resource utilization threshold.

US Pat. No. 10,191,844

AUTOMATIC GARBAGE COLLECTION THRASHING MONITORING

Cisco Technology, Inc., ...

1. A method for monitoring a garbage collection process in a business transaction over a computer network, comprising:monitoring, by an agent on a server, the garbage collection process to identify a source of a garbage thrashing in the garbage collection process, the garbage collection process executed in association with one or more business transaction applications executing on the server;
determining, by the agent, a memory usage associated with the garbage collection process;
collecting, by the agent, a plurality of data objects handled by the garbage collection process;
graphing, by the agent, the plurality of data objects handled by the garbage collection process into a memory usage versus time graph, wherein the graph is divided into garbage collection time intervals;
determining, by the agent, a memory usage associated with each of the collected data objects handled by the garbage collection process during each of the garbage collection time intervals based on the graph of the plurality of data objects handled by the garbage collection process;
comparing, by the agent, graphically the memory usage of each of the collected data objects to the memory usage of the garbage collection process by comparing one or more stack traces obtained at a time of creation of the collected data objects to identify one or more commonalities regarding the creation of the collected data objects to identify the source of the garbage trashing;
identifying, by the agent, a suspicious sub-set of the collected data objects that most closely resemble the memory usage of the garbage collection process, wherein the suspicious sub-set of the collected data objects is the source of the garbage thrashing in the garbage collection process; and
reporting, by the agent, the sub-set of identified data objects as the source of the garbage thrashing in the garbage collection process.

US Pat. No. 10,191,843

UNALIGNED DATA COALESCING

Micron Technology, Inc., ...

1. A method for unaligned data coalescing, comprising:receiving a first write command associated with an unaligned portion of data; and
coalescing, using a coalescing tree, the unaligned portion of data with data associated with another write command, wherein a logical address of the unaligned portion of data and a logical address of the data associated with the another write command correspond to a particular logical page.

US Pat. No. 10,191,836

SOFTWARE WATCHPOINTS APPARATUS FOR VARIABLES STORED IN REGISTERS

NXP USA, Inc., Austin, T...

1. A method for debugging a compiled computer program comprising one or more variables, the method comprising:generating variable location information for a first variable stored in a CPU register using debug information and runtime disassembly information for the compiled computer program, wherein the first variable comprises a global variable;
generating a search pattern for the first variable based on the variable location information, wherein
the search pattern comprises an address range for the first variable, and
said generating the search pattern comprises creating a regular expression for the first variable;
searching the runtime disassembly information for the search pattern to identify a first program address for the first variable, wherein said searching the runtime disassembly information comprises
searching the runtime disassembly information between the address range to identify the first program address as a machine address for a change of flow pattern that matches the regular expression, and
returning the first program address with a marker flag being set; and
setting a software program watchpoint for the first variable at the first program address.

US Pat. No. 10,191,835

MULTI-THREADED DEBUGGER SUPPORT

International Business Ma...

1. A method for managing debugging requests associated with a multi-threaded application, the method comprising:receiving, by a control program, a first memory buffer including a Transmission Control Protocol (TCP) request from a debugger, responsive to a first request from a set of debugging requests being input by a user via a graphical user interface, wherein the first memory buffer is associated with a thread of a process that has been designated for debugging, wherein the first memory buffer is separate and distinct from the thread, and wherein the TCP request instructs the control program to perform at least one action on the thread;
generating a bracket for the thread, based on analysis of the first memory buffer, wherein the bracket comprises a set of control registers and an address range associated with execution of the thread;
determining whether the action associated with the TCP request to be performed on the thread is one of an execute type action and a service type action;
responsive to determining the execute type action:
waking up the thread associated with the bracket;
placing the thread on a list for execution of the action; and
executing the thread, while performing the execute type action on the thread, until said thread falls into the address range specified by the bracket, wherein the execute type action manipulates the thread:
responsive to determining the service type action:
setting up a Program Control Block (PCB) for the thread; and
performing the service type action on the thread;
generating, by the control program, debugging event information comprising results associated with one of the execute type action and the service type action, wherein the debugging event information is at least based on the manipulated thread;
inserting the debugging information into the memory buffer associated with a TCP reply of the thread;
determining whether a reply flag associated with the memory buffer is ready to be sent out;
responsive to determining that the reply flag is ready:
passing the memory buffer to the debugger in accordance with the TCP reply; and responsive to determining that the reply flag is not ready;
checking a communication socket for determining whether a further user request has been made from the debugger:
if the further request has not been made:
sleeping the debugger for a period of time, while performing a subsequent check of the reply flag; and
if the further request has been made:
retrieving a user thread associated with the further user request:
modifying a new memory buffer to process the user thread; and
processing the user thread in accordance with the TCP request.

US Pat. No. 10,191,832

MULTI-LANGUAGE PLAYBACK FRAMEWORK

Microsoft Technology Lice...

1. One or more computer-readable storage media storing computer-executable instructions, which when executed by a computer, cause the computer to perform operations, the operations comprising:receiving a language-neutral script comprising a plurality of recorded actions to perform on respective user interface elements of a software product supporting multiple languages;
receiving a language file mapping properties of the respective user interface elements of the language-neutral script to properties of user interface elements in a target language among the multiple languages supported by the software product; and
executing the language-neutral script on a playback engine interfacing with a build of the software product in the target language, wherein executing the language-neutral script on the playback engine comprises:
identifying, among the plurality of recorded actions of the language-neutral script, a given recorded action corresponding to a recorded user interface element of the language-neutral script, the recorded user interface element comprising a plurality of properties, wherein each property of the plurality of properties is a different property type;
finding an under-test user interface element of the build of the software product in the target language equivalent to the recorded user interface element of the language-neutral script by performing an ordered search for the properties of the recorded user interface element within the language file, the ordered search evaluating the properties of the recorded user interface element in a predefined order that prioritizes the different property types relative to each other; and
performing the given recorded action of the language-neutral script on the matching under-test user interface element of the build of the software product in the target language.

US Pat. No. 10,191,827

METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR UTILIZING LOOPBACK OPERATIONS TO IDENTIFY A FAULTY SUBSYSTEM LAYER IN A MULTILAYERED SYSTEM

SANDISK TECHNOLOGIES LLC,...

1. A method for utilizing loopback operations to identify a faulty subsystem layer in a multilayered system, the method comprising:executing a plurality of loopback operations using a respective plurality of loopback points positioned among subsystem layers of a multilayered system, wherein:
the plurality of loopback operations incrementally test loopback points in the plurality of loopback points; and
each loopback operation tests loopback points that have been previously tested during previously executed loopback operations;
detecting a failed loopback operation among the plurality of loopback operations; and
identifying a faulty subsystem layer among the subsystem layers by comparing the failed loopback operation against a previously conducted successful loopback operation corresponding to a preceding subsystem layer that is adjacent to the faulty subsystem layer within the multilayered system.

US Pat. No. 10,191,825

SYSTEM AND METHOD FOR TESTING A DEVICE USING A LIGHT WEIGHT DEVICE VALIDATION PROTOCOL

WIPRO LIMITED, Bangalore...

1. A method for testing a device, the method comprising:accessing, via a testing engine, a test script corresponding to a test case for testing the device, wherein the test script comprises a set of mutually independent primitive executables;
packetizing, via the testing engine, one or more of the set of primitive executables based on a light weight device validation (LWDV) protocol, wherein the LWDV protocol is configured to represent a message as a series of data fields, wherein the data fields comprise a SYNC byte field, a start byte field, a payload length field, a session identification field, a message identification field, a sequence identification field, a test case identification field, a core data field, and a checksum field, and wherein the message identification field comprises a more bit field; and
transmitting, via the testing engine, the one or more primitive executables to the device for execution, wherein transmitting the one or more primitive executables comprises:
determining an availability of each of one or more resources in the device via the LWDV protocol; and
transmitting the one or more primitive executables to the device based on the availability.

US Pat. No. 10,191,821

COOPERATIVE DATA RECOVERY IN A STORAGE STACK

Dell Products, LP, Round...

1. A computer-implemented method of recovering data in response to a failed input/output request, the method comprising:in a memory storage stack having layers, including a lowest layer, at least one intermediate layer, and a highest layer, in a hierarchical order, wherein each layer has associated storage memory and one or more associated processor and wherein each intermediate layer has a first single layer immediately lower in hierarchical order and a second single layer immediately above in hierarchical order:
seeking data in hierarchical order from the highest layer to the lowest layer in the storage stack and responsive to a failed input/output (I/O) request for data, from a higher layer of the memory storage stack to a lower layer of the memory storage stack in the hierarchical order, generating, at the lower layer, a first help response and sending the first help response from the lower layer to the higher layer to recover the data;
at the higher layer, determining whether a recovery mechanism can fulfill the I/O request and, if not, generating a second help response and sending the second help response to a next higher layer of the memory storage stack in the hierarchical order;
at the next higher layer, determining whether a recovery mechanism can fulfill the I/O request and, if not, generating a third help response and sending the third help response to an even next higher layer of the memory storage stack in the hierarchical order;
in response to determining a recovery mechanism can fulfill the I/O request, obtaining the data using the recovery mechanism and providing the data to the higher layer in response to the I/O request; and
upon the help response reaching the highest layer of the memory storage stack, generating an error at the highest layer.

US Pat. No. 10,191,819

DATABASE PROTECTION USING BLOCK-LEVEL MAPPING

Commvault Systems, Inc., ...

1. A data storage system for protecting database files, the system comprising:one or more primary storage devices that store a plurality of application-level blocks associated with a database, and one or more secondary storage devices that store a secondary copy of the database with a plurality of storage blocks, the plurality of storage blocks having a first granularity that is larger than a second granularity of the application-specific blocks;
an index stored in memory that maps the plurality of storage blocks with corresponding application-level blocks, wherein each of the plurality of storage blocks in the secondary copy spans a plurality of the application-level blocks;
in response to instructions to retrieve one or more requested application-level blocks associated with of a database file from the secondary copy, one or more secondary storage controller computers comprising computer hardware are configured to:
access the index that provides a mapping between the plurality of requested application-level blocks and corresponding plurality of storage blocks;
retrieve the corresponding plurality of storage blocks from the secondary copy; and
a data agent executing on one or more computer processors and configured to divide the corresponding plurality of storage blocks retrieved from the secondary copy into the one or more requested application-level blocks; and
a database application executing on one or more computer processors, the database application in communication with the data agent, the database application configured to receive the requested application-level blocks from the data agent.

US Pat. No. 10,191,816

CLIENT-SIDE REPOSITORY IN A NETWORKED DEDUPLICATED STORAGE SYSTEM

Commvault Systems, Inc., ...

1. A method for restoring data to a client system from one or more secondary storage devices, the method comprising:performing with a media agent executing in or more computer processors, a secondary copy operation that copies a plurality of data blocks associated with one or more primary storage devices in a client system to one or more secondary storage devices located remotely from the one or more primary storage devices;
copying at least a portion of the data blocks and a first copy of hash signatures associated with the portion of the data blocks to a client-side repository comprising at least computer memory, wherein the client-side repository is different than the one or more secondary storage devices;
populating an index in communication with the media agent with a second copy of the hash signatures associated with the plurality of the data blocks stored in the one or more secondary storage devices;
receiving a request to restore data to the client system;
querying the client-side repository with the second copy of the hash signature from the index to determine whether the first copy of the hash signature is stored in the client-side repository;
if the querying the client-side repository with the second copy of the hash signature indicates that client-side repository is populated with the first hash signature, accessing the at least one data block associated with the restore data from the client-side repository;
if the querying the client-side repository with the second copy of the hash signature indicates that the client-side repository is not populated with the first hash signature, accessing the at least one data block associated with the restore data from the one or more secondary storage devices; and
monitoring the usage of the client-side repository and the one or more secondary storage devices and pruning the data in the client-side repository based at least in part on the percentage of data restored from the client-side repository.

US Pat. No. 10,191,814

RESTORING DATA IN A HIERARCHICAL STORAGE MANAGEMENT SYSTEM

International Business Ma...

1. A method for storing data in a hierarchical storage management (HSM) system, the method comprising:receiving, by a first controller, a request to migrate a data item to a first storage tier managed by the first controller, wherein (i) the request associates the data item with at least an initial object ID that is an object ID of a first version of the data item and (ii) the data item is associated with a HSM status parameter value that indicates that the data item is in a resident state, and, in response:
generating, by the first controller, a new object ID;
identifying, by the first controller, a first record in a data structure that includes a plurality of records based, at least in part, on the initial object ID being identical to an object ID of the first record and to a parent object ID of the first record;
replacing, by the first controller, the object ID of the first record with the new object ID;
creating, by the first controller, a new record in the data structure, wherein the new record is associated with the data item;
setting, by the first controller, an object ID field of the new record and a parent object ID field of the new record to the initial object ID; and
storing, by the first controller, the data item to the first storage tier.

US Pat. No. 10,191,813

DATA REPLICATION SNAPSHOTS FOR PERSISTENT STORAGE USING OPERATION NUMBERS

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:maintaining a master copy and a slave copy of a data volume, the master copy including data for a plurality of operations having respective sequential operation numbers, the data for the plurality of the operations being replicated to the slave copy;
generating a snapshot of the master copy, the snapshot being assigned a next operation number in an operation number sequence, the snapshot comprising snapshot data;
writing the snapshot data, as well as the operation number and metadata for the snapshot, to persistent storage; and
while writing the snapshot data to the persistent storage, processing subsequent input/output (I/O) operations by the master copy.

US Pat. No. 10,191,811

DUAL BOOT COMPUTER SYSTEM

QUANTA COMPUTER INC., Ta...

1. A computer system, comprising:a processor;
a complex programmable logic device (CPLD);
a locally protected primary boot;
a locally modifiable secondary boot, wherein the CPLD is connected to the processor, and configured to control the processor with regard to selecting either the locally protected primary boot or the locally modifiable secondary boot, wherein the locally protected primary boot and the locally modifiable boot are individually partitioned, and the way the locally protected primary boot being partitioned is different from the way the locally modifiable boot being partitioned;
a computer-readable memory storing instructions which, when executed by the processor, causes the processor to perform operations comprising:
commencing a first boot sequence for the computer system with the primary boot;
restarting the computer system and commencing, in response to the restarting, a second boot sequence with the locally modifiable secondary boot;
if the second boot sequence with the secondary boot is successful, storing a copy of the secondary boot in a partition of the primary boot as one of a ONIE u-boot code, a u-boot environment, or a kernel code; and
if the second boot sequence with the secondary boot fails, restarting the computer system and re-commencing a third boot sequence with the primary boot.

US Pat. No. 10,191,810

MOBILE TERMINAL AND RELATED REPAIR METHOD

MEDIATEK SINGAPORE PTE. L...

1. A repair method for a mobile terminal, comprising:obtaining a current storage integrity information of a system partition of the mobile terminal;
matching the current storage integrity information and an original storage integrity information; and
connecting to a server, and obtaining an original system partition document from the server, and repairing the system partition according to the original system partition document when the matching fails,
wherein the step of connecting to the server, and obtaining original system partition document from the server, and repairing the system partition according to the original system partition document when the matching fails further comprising:
checking whether a logic block address of a storage device of the mobile terminal is damaged;
if the logic block address is not damaged, finding abnormal document of the system partition, and repairing the abnormal document according to the original system partition document; and
if the logic block address is damaged, connecting to the server, acquiring the original system partition document from the server, and repairing all document of the system partition according to the original system partition document.

US Pat. No. 10,191,809

CONVERTING A DATA CHUNK INTO A RING ALGEBRAIC STRUCTURE FOR FAST ERASURE CODING

International Business Ma...

1. A method comprising:at a storage manager of a storage system:
arranging a first data chunk into a ring structure;
tagging the first data chunk by appending extra data to the ring structure;
performing erasure coding on the first data chunk utilizing only exclusive or (XOR) operations and the ring structure, wherein erasure coded encoded data resulting from the erasure coding is written to a persistent storage device; and
maintaining an index pointer that references a portion of the ring structure;
wherein the ring structure allows for multiplication of data included in the first data chunk to be implemented by rotation of the data utilizing the index pointer, thereby increasing efficiency of the storage system as the multiplication is simplified to an adjustment of the index pointer.

US Pat. No. 10,191,807

MEMORY SYSTEMS AND OPERATION METHOD THEREOF

SK hynix Inc., Icheon-si...

14. A memory system, comprising:a memory controller including a first-type error correction circuit suitable for generating a first error correction code using a first write data which is a portion of a write data form a host, and a second-type error correction circuit suitable for generating a second error correction code using a second write data which is a remaining portion of the write data, wherein error correction algorithms used by the first-type error correction circuit and the second-type error correction circuit are different from each other; and
a memory module including a plurality of first memory devices suitable for storing the first write data and the first error correction code, and one or more second memory device suitable for storing the second write data and the second error correction code.

US Pat. No. 10,191,804

UPDATING RELIABILITY DATA

Micron Technology, Inc., ...

1. An apparatus, comprising:a memory device;
a reliability circuit coupled to the memory device and configured to receive hard data from the memory device and to determine reliability data assigned thereto, the reliability data comprising a first reliability data value in response to the hard data comprising a first value or comprising a second reliability data value in response to the hard data comprising a second value;
an error correction circuit coupled to the reliability circuit and configured to receive the hard data and the reliability data from the reliability circuit, wherein the error correction circuit is further configured to:
iteratively compute parity data for the hard data; and
increment or decrement the reliability data once per L-number of layers of parity data, wherein one iteration includes a plurality of layers of parity data.

US Pat. No. 10,191,803

REWRITING FLASH MEMORIES BY MESSAGE PASSING

California Institute of T...

1. A data storage device comprising:a host interface configured to receive a binary representation of a message m;
a non-volatile memory device;
a memory device interface coupled to the non-volatile memory device; and
a controller configured to:
receive the message m for storing the message m into n cells of the non-volatile memory device;
read a current state s of the n cells of the non-volatile memory device in which a previously received message has been stored;
determine a vector x based on the message m and the current state s of the n cells, wherein the vector x represents the message m and can be written into the n cells over the current state s of the n cells without erasing the n cells; and
if the vector x cannot be determined,
provide a FAIL indication; and
implement an error handling routine;
otherwise,
provide the vector x to the memory device interface for storing the vector x into the n cells of the non-volatile memory device without erasing the n cells.

US Pat. No. 10,191,802

EXTRACT-TRANSFORM-LOAD DIAGNOSTICS

Oracle International Corp...

1. A method for diagnosing extract-transform-load (ETL) errors in a cloud-based data integration system, comprising:initiating, by a computer system, a first process of an extract-transform-load process within the cloud-based data integration system, the first process comprising extracting data from a cloud-based application;
receiving, by the computer system, a first data set associated with the first process;
initiating, by the computer system, a second process of the extract-transform-load process within the cloud-based data integration system, the second process comprising caching the extracted data into a first schema, and the first schema being associated with the cloud-based application;
receiving, by the computer system, a second data set associated with the second process;
initiating, by the computer system, a third process of the extract-transform-load process within the cloud-based data integration system, the third process comprising loading the extracted data from a first schema to a second schema, the second schema being associated with a cloud-based data warehouse, and the first process, the second process, and the third process being distinct processes performed at different times during the extract-transform-load process;
receiving, by the computer system, a third data set associated with the third process;
determining, by the computer system, a first error and a second error in the extract-transform-load process based at least in part on the first data set, the second data set, or the third data set;
determining, by the computer system, a first characteristic associated with the first error, the first characteristic indicating at least that the first error is correctable;
determining, by the computer system, a second characteristic associated with the second error, the second characteristic indicating at least that the second error is fault tolerant;
rejecting, by the computer system, based at least in part on the first characteristic, at least a portion of data associated with the first error; and
transforming, by the computer system, based at least in part on the second characteristic, at least a portion of data associated with the second error.

US Pat. No. 10,191,801

ERROR CORRECTION CODE MANAGEMENT OF WRITE-ONCE MEMORY CODES

TEXAS INSTRUMENTS INCORPO...

1. An electronic device comprising:a write-once memory (WOM) device; and
a memory controller that includes:
a host interface to receive a data word including a first symbol and a second symbol, each of the first and second symbols having at least two bits;
a WOM controller to encode the first symbol and the second symbol and outputs a WOM-encoded word that includes a first WOM code corresponding to the first symbol and a second WOM code corresponding to the second symbol, wherein each of the first and second WOM codes include at least three bits with at least two of the at least three bits having the same logic value;
an error correction code (ECC) controller to encode the WOM-encoded word and output an ECC-encoded word that includes the first and second WOM codes and a first set of ECC bits corresponding to a first write operation; and
a memory device interface to write the ECC-encoded word to a first address of the WOM device as part of the first write operation.

US Pat. No. 10,191,800

METRIC PAYLOAD INGESTION AND REPLAY

Cisco Technology, Inc., ...

1. A method for metric payloads ingestion and playback, the method including:receiving, by a collector executing on a server, time series of metric payloads for a plurality of performance metrics indicating performance of a node or machine, wherein the collector is communicatively connected to a coordinator that provides collectors with information on a plurality of aggregators including assignments of the performance metrics to each aggregator;
storing, by a database executing on the server, the received time series of metric payloads in a payload tracking table of a database, wherein the storing includes:
storing the received time series of metric payloads in different layers and partitioned regions of the payload tracking table, wherein the layers represent time ranges corresponding to time points when the time series of metric payloads are received, and wherein the partitioned regions are assigned to received certain ones of the received time series of metric payloads; and
replaying the stored time series of metric payloads from a select one or more of the partitioned region or layer or both.

US Pat. No. 10,191,799

BER MODEL EVALUATION

SanDisk Technologies LLC,...

1. A storage system comprising:a memory; and
a controller configured to:
read a data set from a target storage location of the memory;
measure a first parameter and a second parameter of the data set to obtain a first actual value of the first parameter and a second actual value of the second parameter;
apply the first actual value or the second actual value to a model; and
based on the application, identify a deviation level of the target storage location relative to the model.

US Pat. No. 10,191,797

ELECTRONIC SYSTEM GENERATING MULTI-PHASE CLOCKS AND TRAINING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. An electronic system comprising:a memory controller configured to generate a plurality of controller clocks having different phases from one another based on a reference clock signal, and to transmit a first clock and a second clock having phase difference from each other between the plurality of controller clocks, the phase difference between the first clock and the second clock is 90 or 270 degrees; and
a memory configured to generate a plurality of internal clocks having different phases from one another by receiving the first clock and the second clock, and selectively output a plurality of odd-ordered data or a plurality of even-ordered data among a plurality of data in synchronization with the plurality of internal clocks,
wherein the memory comprises:
a clock receiver configured to generate a first differential clock and a second differential clock in response to the first and second clocks;
a duty cycle correction portion configured to correct duty ratios of the first differential clock and the second differential clock;
a clock division portion configured to output the first and second groups of clocks by dividing an output of the duty cycle correction portion; and
a data input/output portion configured to transmit the plurality of the odd-ordered data or the plurality of the even-ordered data to the memory controller in response to the first group of clocks and an even-odd flag signal.

US Pat. No. 10,191,796

SYSTEM AND METHOD FOR STATISTICAL APPLICATION-AGNOSTIC FAULT DETECTION IN ENVIRONMENTS WITH DATA TREND

Open Invention Network, L...

1. A system, comprising:one or more memory locations configured to store one or more applications and one or more statistical models, wherein each of said one or more application is comprised of one or more processes and threads;
one or more Central Processing Units operatively connected to said one or more memory locations, configured to execute said one or more applications on a host with a host operating system, and configured to generate one or more statistical events for said one or more executing applications and said host operating system; and
a fault detector configured to create one or more statistical models for the execution of said one or more applications, each comprising: one or more of calculating one or more distributions for said one or more statistical events, de-trending the data for said one or more statistical events, transforming the data for said statistical events, and detecting faults in the execution of said one or more applications by detecting significant deviation of recent statistical events from said one or more distributions.

US Pat. No. 10,191,795

METHOD AND SYSTEM FOR TIMEOUT MONITORING

Infineon Technologies AG,...

1. A method for timeout monitoring of commands comprising:assigning, by a first microcontroller, each one of the commands to a corresponding one of a plurality of timeout timers in a FIFO manner when corresponding commands are to be transmitted by the first microcontroller over a high speed serial link (HSSL) to a second microcontroller within a same system;
for a first type of command, transmitting over the HSSL, by the first microcontroller, a subsequent command only after receiving a command acknowledge or a timeout to a previously transmitted command; and
for a second type of command, transmitting over the HSSL, by the first microcontroller, a subsequent command before a command acknowledge or a timeout to a previously transmitted command has been received.

US Pat. No. 10,191,792

APPLICATION ABNORMALITY DETECTION

International Business Ma...

1. A method of operating a computer system comprising:collecting, from the computer system, data indicative of variations in throughput and response time over a period of time;
calculating processing power of the computer system over the period of time;
recording a maximal power;
calculating a standard deviation of the response time (RT-StdDev);
recording the standard deviation of the response time corresponding to a time of the maximal power (RT-StdDevMaxPower); and
generating a notification that the computer system is in a bottleneck state using a comparison of a current processing power to the maximal power and a comparison of the RT-StdDev to the RT-StdDevMaxPower.

US Pat. No. 10,191,791

ENHANCED ADDRESS SPACE LAYOUT RANDOMIZATION

Intel Corporation, Santa...

1. An enhanced address space layout randomization apparatus comprising:a linear address space comprising a metadata data structure;
metadata logic to generate a metadata value; and
enhanced address space layout randomization (ASLR) logic to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address,
the address pointer corresponding to an apparent address in an enhanced address space, a size of the enhanced address space greater than a size of the linear address space.

US Pat. No. 10,191,790

DATA STORAGE DEVICE AND ERROR RECOVERY METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A data storage device comprising:a nonvolatile memory device including a memory block having a plurality of memory regions; and
a controller suitable for searching a first memory region for which error correction is passed, by scanning the plurality of memory regions in a reverse order of a write sequence for the memory block, determining a target memory region in the memory block based on data stored in the first memory region, and performing a recovery operation for the target memory region,
wherein, when it is determined that transaction-begin data is stored in the first memory region, the controller determines a memory region which is indicated by the transaction-begin data, as the target memory region.

US Pat. No. 10,191,788

PROGRAMMABLE DEVICE, HEIRARCHICAL PARALLEL MACHINES, AND METHODS FOR PROVIDING STATE INFORMATION

Micron Technology, Inc., ...

1. A method of providing state information from a parallel machine to another device, wherein the parallel machine includes a plurality of programmable elements, wherein each of the programmable elements is configured to have a corresponding state, comprising:determining state information, wherein the state information comprises the state of each of the programmable elements in the parallel machine;
compressing the state information, wherein compressing the state information comprises aggregating final states in a finite state machine implemented on the parallel machine; and
providing the compressed state information to the other device.

US Pat. No. 10,191,786

APPLICATION PROGRAM INTERFACE MASHUP GENERATION

FUJITSU LIMITED, Kawasak...

1. A method of generating application program interface (API) mashups, the method comprising:grouping, via at least one processor, a plurality of APIs into a plurality of sub-clusters based on at least one keyword for each API of the plurality of APIs;
identifying, via the at least one processor, at least one keyword combination for the plurality of sub-clusters based on real-world data and two or more keywords for the plurality of sub-clusters;
determining, via the at least one processor, one or more possible API mashups including two or more APIs of the plurality of APIs for the at least one keyword combination;
determining, via the at least one processor, a similarity score for each possible API mashup of the one or more possible API mashups; and
identifying, via the at least one processor, at least one API mashup from the one or more possible API mashups based on the similarity score for each possible API mashups of the one or more possible API mashups.

US Pat. No. 10,191,784

ADAPTIVE QUEUED LOCKING FOR CONTROL OF SPECULATIVE EXECUTION

Intel Corporation, Santa...

1. An apparatus, comprising:a queue controller to control removal of threads from a queue, the queue to contain threads that are waiting to be permitted to speculatively execute in a critical section of a multi-threaded program;
a first thread associated with a head node of the queue, the queue controller to control the removal of threads from the queue in response to operations performed by the first thread, and when a number of threads executing in the critical section reaches a quota, the first thread to retry speculatively executing in the critical section and to remain associated with the head node of the queue to prevent a second thread corresponding to a second node of the queue from retrying speculatively executing in the critical section; and
an adjuster to change a number of threads permitted to speculatively execute based on a rate of threads currently speculatively executing transactions in the critical section, the adjuster is implemented via a logic circuit.

US Pat. No. 10,191,783

UDP MULTICAST OVER ENTERPRISE SERVICE BUS

Red Hat, Inc., Raleigh, ...

1. A method comprising:receiving application data from an event listener comprising a transport component and a web component by a processing device of an infrastructure service system, wherein the infrastructure service system comprises a first enterprise service bus (ESB) associated with an enterprise messaging system, wherein the application data comprises business rules to be shared between a first application in communication with the first ESB and a second application in communication with a second ESB associated with the enterprise messaging system;
forming, using the application data, a message by the processing device; and
transmitting, by the processing device, via the first ESB, the message via User Datagram Protocol (UDP) multicast over a public channel to a multicast address associated with a plurality of receivers associated with the second ESB, wherein the second ESB is subscribed to the multicast address.

US Pat. No. 10,191,782

SYSTEM TO SCHEDULE AND PERFORM AUTOMATED SOFTWARE TASKS DURING UNATTENDED SYSTEM TIME USING PREDICTED KNOWLEDGE OF INDIVIDUAL USER BEHAVIOR

Dell Products, LP, Round...

1. A method, comprising:determining, by an information handling system, a future predicted system time that an unattended task is to be executed on the information handling system, the future predicted system time based at least in part on first usage parameters for a user of the information handling system, the first usage parameters indicating first periods of usage activity and second periods of inactivity associated with the information handling system recorded during a first duration, and the first usage parameters indicating critical system parameters relevant to the present state of the information handling system;
ensuring, by the information handling system, that system resources of the information handling system are available for the unattended task to be able to complete;
in response to an arrival of the future predicted system time, executing, by the information handling system, the unattended task;
incrementing, by the information handling system, a count of wake events in response to the executing of the unattended task at the arrival of the future predicted system time;
comparing, by the information handling system, the count of the wake events to a threshold value, the threshold value based on the first periods of usage activity and the second periods of inactivity; and
recording, by the information handling system, the future predicted system time as a wake event of the wake events in response to the count of the wake events being less than the threshold value.

US Pat. No. 10,191,779

APPLICATION EXECUTION CONTROLLER AND APPLICATION EXECUTION METHOD

FUJITSU LIMITED, Kawasak...

1. An application execution controller, configured to instruct an execution of an application in a computing environment having available to allocate to executing applications: one or both of different amounts of computing resources in a plurality of computing resource categories and different types of computing resources in a plurality of computing resource categories; the controller comprising a memory and a processor coupled to the memory, the processor being configured:to collect available resource information detailing configurations of computing resources available to execute the application, wherein the configurations each include an indication of respective an amount and type of computing resources available in each category among the plurality of computing resource categories;
to collect application execution scalability information including, in respect of computing resources in at least one of the categories among the plurality of computing resource categories, an indication of how the one of or both of different amounts and types of computing resources in the respective computing resource category correlate with execution rate of a first portion of the application, the application execution scalability information being specific to an execution mode for the first portion of the application;
to collect performance target information including an indication of one or more performance targets for the execution of the application;
to perform a selection of a configuration from among the configurations detailed in the available resource information which, based on the application execution scalability information will come closest out of the configurations to meeting, the one or more performance targets; and
to instruct the computing environment to execute the first portion of the application using the selected configuration; wherein
for a change in an execution mode during the execution of the application caused by progressing from the first portion of the application to a forthcoming second portion:
the processor is configured to collect an updated version of the application execution scalability information, specific to the changed execution mode for the forthcoming second portion of the execution of the application, and to use the updated version to update a currently held version of the application execution scalability information; and
using the updated version of the application execution scalability information, the processor is configured to perform an updated selection of configuration from among the configurations detailed in the available resource information which, based on the updated application execution scalability information will come closest out of the configurations to meeting the one or more performance targets specified in the performance target information; wherein
the application execution scalability information is provided as a scalability matrix, the scalability matrix including an entry for each pair of factors from among factors comprising each category from among the plurality of computing resource categories and execution rate, the entry representing an effect of a proportional change along a linear scale representing usage of respective different amounts and types of a first factor from a pair of factors on the respective amount and type required of a second factor from the pair of factors, in terms of a proportional change along a linear scale representing the respective different amounts and types of the second factor, and
the processor is configured to instruct the computing environment to perform the execution of the forthcoming second portion of the application using the updated selection of configuration.

US Pat. No. 10,191,776

INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, INFORMATION PROCESSING PROGRAM, AND STORAGE MEDIUM

FUJIFILM CORPORATION, To...

1. An information processing system comprising:a control device that transfers data that is a processing target and a control command describing processing content for the data;
a plurality of processing devices that are provided outside the control device and perform processing according to the control command on the data in a case where the control command is transferred from the control device; and
a planning device that determines a division size of the data such that a difference between a transfer time to transfer divided data obtained by dividing the data from the control device to each of the plurality of processing devices and a processing time to process the divided data in the processing device falls within a predetermined range, on the basis of an amount of the data, the transfer time, and the processing time,
wherein the control device sequentially transfers the divided data obtained by dividing the data according to the division size determined by the planning device to any one of the plurality of processing devices,
each of the plurality of processing devices performs processing according to the corresponding control command on the previously transferred divided data in parallel with the transfer of the divided data from the control device to the processing device in a case where the control command is transferred from the control device,
the transfer time and the processing time are determined in advance for each of the plurality of processing devices, and
the planning device determines the division size for each of the plurality of processing devices, calculates a processing completion time from start of transfer of the divided data from the control device to each of the plurality of processing devices to end of transfer of all pieces of data obtained by processing the divided data from each of the plurality of processing devices to the control device on the basis of the determined division size, and determines a processing device having a shortest processing completion time to be a transfer destination of the divided data of the control device.

US Pat. No. 10,191,773

METHODS, SYSTEMS, AND DEVICES FOR ADAPTIVE DATA RESOURCE ASSIGNMENT AND PLACEMENT IN DISTRIBUTED DATA STORAGE SYSTEMS

Open Invention Network LL...

1. A distributed data storage system for automatic constraint-based data resource arrangement, the data storage system comprising:a plurality of data storage components communicatively coupled to each other, each of said data storage components comprising at least one data resource selected from a data storage media for storing client-related digital information, a data processor for processing said client-related digital information, and a network communications interface for communicating said client-related digital information; and
a constraint engine comprising a constraint processor and a constraint database, said constraint database receiving and storing changeable digital constraint parameters indicative of permissible operational constraints on said data storage system, and said constraint processor automatically determining permissible data resource assignment arrangements in accordance with said changeable digital constraint parameters so to assign at least some of said data resources for use with said client-related digital information in compliance with said permissible operational constraints on said data storage system;
wherein, in response to an operational change to said data storage system, at least some said data resource are automatically reassigned from a current permissible data resource assignment arrangement to an alternate permissible data resource assignment arrangement and wherein a reassignment is selected when a number of reassignment steps is less than a designated reassignment threshold and thereby determined to comply with a designated set of said changeable digital constraint parameters.

US Pat. No. 10,191,770

MAINTENANCE TASKS BASED ON DEVICE ROLE

Microsoft Technology Lice...

1. A computer system comprising:one or more processors; and
one or more computer-readable media having stored thereon instructions that are executable by the one or more processors to configure the computer system to update a computing device, including instructions that are executable to configure the computer system to perform at least the following:
identify a defined computing system role for the computing device, wherein the defined computing system role defines a specific predefined purpose of the computing device;
based on the defined computing system role for the computing device, identify a schedule correlated to the defined computing system role, wherein the schedule comprises predetermined time periods, the predetermined time periods defining at least one of when computing devices having the defined computing system role should he active, when computing devices having the defined computing system role should be idle, or when computing devices having the defined computing system role should have maintenance tasks performed;
based on the predetermined time periods in the schedule, identify one or more times for performing maintenance tasks for the defined computing system role, and thus for the computing device such that the times for performing maintenance on the computing device are directly correlated to and based on the defined computing role for the computing device; and
perform one or more maintenance tasks on the computing device, at the one or more times identified for maintenance for the defined computing system role according to the identified schedule; and
wherein the performing one or more maintenance tasks on the computing device comprises performing updates, including at least one of application updates, operating system updates, application store updates, or security updates.

US Pat. No. 10,191,767

SEAMLES SDN-SUPPORTED RAN-APP MIGRATION

NEC CORPORATION, Tokyo (...

1. A method for performing centralized radio access network (CRAN) process migration in a CRAN, wherein the CRAN comprises a number of remote radio access points and a centralized processing center including a number of physical compute hosts that perform at least part of a radio access network (RAN) functionality, wherein the method comprising:executing a CRAN process on a first of the physical compute hosts and starting a new instance of the CRAN process on a second of the physical compute hosts,
duplicating traffic destined to the CRAN process to both instances of the CRAN process,
during a first time interval, processing the traffic on the first and the second physical compute host in parallel and suppressing the output of the second physical compute host, and
when the second physical compute host reaches a same state with respect to the CRAN process as the first physical compute host, forwarding duplicate outputs from both instances to higher layers.

US Pat. No. 10,191,766

AUTHORING AND RUNNING TASK-BASED FLOWS WITHIN A COMPUTING SYSTEM

Microsoft Technology Lice...

1. A computing system, comprising:a processor; and
memory storing instructions executable by the processor, wherein the instructions, when executed, configure the computing system to provide:
an application component configured to:
run a parent application; and
navigate a user through a plurality of parent application pages, each parent application page having user interface (UI) controls;
launch point detector logic configured to detect a launch point indicator that is indicative of a launch point corresponding to a task associated with an application object in the parent application;
flow identifier logic configured to identify a sub-application to be launched based on the launch point indicator; and
a sub-application runtime system configured to:
launch the identified sub-application having a sub-application page configured to perform the task, the sub-application page having a set of UI controls comprising a subset of the UI controls on a parent application page;
receive an indication of user input through the sub-application page; and
provide data associated with the user input to the application object in the parent application.

US Pat. No. 10,191,765

TRANSACTION COMMIT OPERATIONS WITH THREAD DECOUPLING AND GROUPING OF I/O REQUESTS

SAP SE, Walldorf (DE)

1. One or more tangible computer-readable media storing computer-executable instructions for causing a server programmed thereby to perform a method at a master node of a database system, the method comprising:for each of multiple database transactions, receiving from one or more database clients one or more operations to manipulate data stored in the database system;
receiving one or more requests to commit the multiple database transactions to disk; and
performing operations to commit the multiple transactions to disk, including:
with a first thread at the master node:
writing a first prepare log to disk at the master node for a first transaction of the multiple transactions;
defining a first job to direct a slave node of the database system to write a first prepare commit log to disk, the first prepare commit log being for at least a portion of the one or more operations of the first transaction;
enqueuing the first job in a queue maintained by the master node, the queue comprising a data structure, physically stored in memory, configured to store a plurality of jobs, the enqueuing comprising storing the job in the data structure; and
after enqueuing the first job, releasing the first thread;
with a second thread at the master node, which may be the first thread after having been released after enqueuing the first job:
writing a second prepare log to disk at the master node for a second transaction of the multiple transaction;
defining a second job to direct the slave node to write a second prepare commit log to disk, the second prepare commit log being for at least a portion of the one or more operations of the second transaction;
enqueuing the second job in the queue; and
after enqueuing the second job, releasing the second thread;
with a third thread at the master node:
dequeuing the first and second jobs from the queue, the dequeuing comprising removing the first and second jobs from the data structure;
grouping the first and second jobs in a single request to be sent to the slave node; and
sending the request to perform the first and second jobs to the slave node, the slave node processing the first and second jobs after receiving the request, writing the first and second prepare commit logs, and sending an acknowledgement to the master node that the first and second prepare commit logs were written;
receiving the acknowledgement from the slave node;
committing the first and second transactions at the master node;
writing a commit log for the first transaction at the master node;
writing a commit log for the second transaction at the master node; and
sending commit acknowledgements to the one or more database clients for the first and second transactions.

US Pat. No. 10,191,764

AGENT-BASED END-TO-END TRANSACTION ANALYSIS

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method for agent-based transaction analysis comprising:building an instrumented binary code of a software application for a transaction;
configuring an analysis agent for the software application;
starting the software application in an application process environment with the instrumented binary code;
attaching the analysis agent to the instrumented binary code of the software application;
extracting by the analysis agent the metadata from the software application wherein the metadata includes data transmitted as a part of the transaction;
sending the metadata to a central analysis server in an environment separate from the application process environment; and
building by the central analysis server an end-to-end description of the transaction from the metadata.

US Pat. No. 10,191,763

ARCHITECTURE OF NETWORKS WITH MIDDLEBOXES

NICIRA, INC., Palo Alto,...

1. A system for implementing a logical network to communicatively connect a plurality of end machines, the logical network comprising (i) a set of logical forwarding elements collectively implemented by a set of managed forwarding elements and (ii) at least two logical middleboxes, the system comprising:a plurality of host computers on each of which (i) a managed forwarding element executes to implement the set of logical forwarding elements and (ii) a middlebox element executes to implement a first logical middlebox of the logical network, wherein the middlebox elements collectively implement the first logical middlebox and each store state information for the first logical middlebox but do not communicate the state information with the other middlebox elements; and
a set of separate physical middleboxes for implementing a second logical middlebox of the logical network, wherein the second logical middlebox performs an operation that requires state information relating to packets between several different sets of end machines connected by the logical network and the set of separate physical middleboxes share the state information for the second logical middlebox with each other;
wherein the middlebox elements and the set of separate physical middleboxes perform middlebox services on packets between the end machines of the logical network.

US Pat. No. 10,191,760

PROXY RESPONSE PROGRAM, PROXY RESPONSE DEVICE AND PROXY RESPONSE METHOD

Fujitsu Limited, Kawasak...

10. A method for a proxy response by a computer, the method comprising:requesting suspension or pausing of a virtual machine when an idle state of the virtual machine is detected;
changing, when the virtual machine is suspended or paused, settings information of a communication control device that controls communication between a terminal device and the virtual machine, so as to transfer access from the terminal device to the virtual machine that is to be suspended or paused, to the computer;
sending, when the access to the virtual machine that is suspended or paused is transferred, a response to the terminal device on the basis of communication response settings information relating to a communication response to the terminal device by the virtual machine that is suspended or paused; and
requesting resumption of the virtual machine that is suspended or paused in response to the transfer of the access.

US Pat. No. 10,191,759

APPARATUS AND METHOD FOR SCHEDULING GRAPHICS PROCESSING UNIT WORKLOADS FROM VIRTUAL MACHINES

Intel Corporation, Santa...

1. A system comprising:a graphics processing unit (GPU) comprising multiple GPU engines;
a microcontroller in the GPU; and
a storage medium having stored thereon instructions which, when executed, implement a virtual machine manager (VMM) to instantiate a virtualization driver interface (vdriver interface) that is adapted to
(a) communicate with the GPU via the microcontroller,
(b) enable multiple virtual machines (VMs) to communicate with the GPU,
(c) store, to memory that is accessible to the microcontroller, a first GPU state for a first VM among the multiple VMs, and
(d) store, to the memory that is accessible to the microcontroller, a second GPU state for a second VM among the multiple VMs;
wherein each VM, when instantiated, is associated with a unique Peripheral Component Interconnect (PCI) device function number and comprises a paravirtualized GPU driver (pdriver) to enable that VM to communicate with the GPU via the vdriver interface, at least in part by enabling that VM to send GPU state for that VM to the vdriver interface of the VMM, for subsequent utilization by the microcontroller in the GPU;
wherein the microcontroller is adapted to
(a) obtain the first GPU state for the first VM, after the vdriver interface of the VMM has received the first GPU state from the pdriver of the first VM and stored the first GPU state to the memory,
(b) obtain the second GPU state for the second VM, after the vdriver interface of the VMM has received the second GPU state from the pdriver of the second VM and stored the second GPU state to the memory,
(c) assign a first schedule slot for the first VM to access a first GPU engine among the multiple GPU engines,
(d) assign a second schedule slot for the second VM to access a second GPU engine among the multiple GPU engines, and
(e) in preparation for transitioning execution from the first VM to a third VM among the multiple VMs, saving the first GPU state for the first VM and restoring a third GPU state for the third VM;
wherein the GPU is adapted to grant exclusive access to the first GPU engine for the first VM when the first VM accesses the first GPU engine; and
wherein, when the first GPU engine executes a memory access instruction provided by the first VM, the first GPU engine is adapted to use the PCI device function number associated with the first VM to execute the memory access instruction.

US Pat. No. 10,191,754

VIRTUAL MACHINE DEVICE HAVING KEY DRIVEN OBFUSCATION AND METHOD

KONINKLIJKE PHILIPS N.V.,...

1. A device comprising:a memory to store multiple operation routines, wherein each operation routine is configured to perform a particular instruction;
at least one processor configured to:
receive an encoded instruction, the encoded instruction being obtained by encoding a plain instruction with a code encoding;
look-up a corresponding operation routine of the multiple operation routines based on the encoded instruction using a look-up table in the memory, the corresponding operation routine being configured to perform the plain instruction corresponding to the encoded instruction; and
receive input data encoded with a first encoding;
perform the corresponding operation routine based on the input data encoded with the first encoding to produce an output; and
encode the output with a second internal encoding.

US Pat. No. 10,191,753

GENERATING VERIFICATION METADATA AND VERIFYING A RUNTIME TYPE BASED ON VERIFICATION METADATA

Oracle International Corp...

1. A non-transitory computer readable medium comprising instructions which, when executed by one or more hardware processors, causes performance of operations comprising:receiving a request to verify a first runtime type, loaded based on a first runtime type reference, wherein the first runtime type includes a statement associated with a second runtime type reference and a third runtime type reference;
responsive to receiving the request to verify the first runtime type:
identifying verification metadata associated with the first runtime type reference for verifying the first runtime type;
determining that the verification metadata comprises a stored assignable relationship between the second runtime type reference and the third runtime type reference;
determining whether an actual assignable relationship between a second runtime type, loaded based on the second runtime type reference, and a third runtime type, loaded based on the third runtime type reference, adheres to the stored assignable relationship between the second runtime type reference and the third runtime type reference; and
responsive at least to determining that the actual assignable relationship adheres to the stored assignable relationship, determining that the first runtime type is verified based on the verification metadata.

US Pat. No. 10,191,751

INFORMATION PROCESSING DEVICE FOR GENERATING APPLICATION PROGRAMMING INTERFACE INFORMATION

FUJITSU LIMITED, Kawasak...

1. An information processing device comprising:a memory; and
a processor coupled to the memory and the processor configured to:
execute an application software,
execute a specific process for coordinating a software module described in a first language with a software module described in a second language that is different from the first language, and
perform loading of a device driver for using a peripheral device, the device driver including a first software module described in the first language and a second software module described in the second language, the first software module being a software module in which a first plurality of interfaces are defined, the second software module being a software module in which a second plurality of interfaces are defined, in response to the loading, generate interface information for associating the first plurality of interfaces with the second plurality of interfaces respectively,
wherein for using the peripheral device,
the application software is configured to make a first access to a first interface selected from the first plurality of first interfaces,
the first software module is configured to make a second access to the specific process based on the first access,
the specific process is configured to make, on the basis of the second access and the generated interface information, a third access to a second interface selected from the second plurality of interfaces, the second interface being associated with the selected first interface, and
the second software module is configured to make a fourth access to the peripheral device based on the third access.

US Pat. No. 10,191,749

SCATTER REDUCTION INSTRUCTION

Intel Corporation, Santa...

5. A processor comprising:a register array comprising a first element that stores a first register value that identifies a first memory location, a second element that stores a second register value that identifies a second memory location, and a third element that stores a third register value that identifies a third memory location;
a decoder circuit to:
receive a single instruction multiple data (SIMD) instruction from an application, the SIMD instruction identifying the register array and an array of input values comprising at least a first input value, a second input value, and a third input value; and
decode the SIMD instruction; and
a processor core to:
perform an operation on the first input value and the first register value to obtain a first operation value, and wherein the first register value is stored at a first location of the register array;
perform the operation on the second input value and the second register value to obtain a second operation value, and wherein the second register value is stored at a second register array location of the register array; and
perform the operation the third input value and the third register value, and wherein the second register value is stored at a third location of the register array,
wherein the operation on the first, second, and third input values are performed in parallel;
associate the first operation value with the first location;
associate the second operation value with the second location;
associate a third operation value with the third location;
determine that the first register value and the second register value are the same value, wherein the third register value is different than the first register value and the second register value;
perform a horizontal add operation on the first operation value and the second operation value to obtain a result value;
write the result value to the second memory location, wherein the second memory location and the first memory location are the same when the first register value and the second register value are the same; and
write the third operation value to the third memory location.

US Pat. No. 10,191,748

INSTRUCTION AND LOGIC FOR IN-ORDER HANDLING IN AN OUT-OF-ORDER PROCESSOR

Intel IP Corporation, Sa...

1. A processor comprising:a core comprising an out-of-order pipeline including a decode logic, an issue logic to issue decoded instructions, and at least one execution logic to execute issued instructions of a program, wherein the at least one execution logic is to execute at least some instructions of the program out-of-order, the decode logic to decode a first in-order memory instruction of the program and provide the decoded first in-order memory instruction to the issue logic, the issue logic to order the first in-order memory instruction ahead of a second in-order memory instruction of the program, the first in-order memory instruction comprising a user-level instruction of an instruction set architecture to specify in-order execution of the first in-order memory instruction, wherein the issue logic is to issue the first in-order memory instruction to the at least one execution logic with a higher priority than the second in-order memory instruction by association of a priority indicator with the first in-order memory instruction.

US Pat. No. 10,191,747

LOCKING OPERAND VALUES FOR GROUPS OF INSTRUCTIONS EXECUTED ATOMICALLY

Microsoft Technology Lice...

1. A method comprising:fetching a first group of instructions, configured to execute by a processor, including a group header for the first group of instructions, wherein the group header includes a field including locking information for at least a first operand and a second operand for processing by the first group of instructions;
storing a value of the first operand in a first operand buffer of the processor and storing a value of the second operand in a second operand buffer of the processor;
detecting completion of execution of the first group of instructions by counting:
(1) register writes associated with the first group of instructions or (2) stores associated with the first group of instructions;
based on the locking information, locking a value of the first operand in the first operand buffer of the processor such that the first operand is not cleared from the first operand buffer of the processor in response to the completion of the execution of the first group of instructions even when a second group of instructions, for execution by the processor after the completion of the execution of the first group of instructions, is a new group of instructions comprising different instructions from the first group of instructions; and
based on the locking information, in response to the completion of the execution of the first group of instructions, clearing the value of the second operand from the second operand buffer of the processor.

US Pat. No. 10,191,746

ACCELERATED CODE OPTIMIZER FOR A MULTIENGINE MICROPROCESSOR

INTEL CORPORATION, Santa...

1. A method for accelerating code optimization in a microprocessor, comprising:fetching an incoming macro instruction sequence using an instruction fetch component;
transferring the incoming macro instruction sequence to a decoding component for decoding into a microinstruction sequence;
performing optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups, wherein performing the optimization processing includes checking for true dependencies, output dependencies, and anti-dependencies in the microinstruction sequence to determine which microinstructions of the microinstruction sequence are grouped into a same dependent code group of the plurality of dependent code groups;
outputting the plurality of dependent code groups to a plurality of engines of the microprocessor for execution in parallel; and
storing a copy of the optimized microinstruction sequence into a sequence cache for subsequent use upon a subsequent hit on the optimized microinstruction sequence.

US Pat. No. 10,191,745

OPTIMIZED CALL-RETURN AND BINARY TRANSLATION

Intel Corporation, Santa...

1. A processor, comprising:a region formation engine to perform aggressive region formation of a region of code for translation from a guest instruction set architecture code to a translated instruction set architecture code,
wherein the aggressive region formation comprises forming the region of code across a boundary of a return (RET) instruction; and
a binary translator to:
translate the region of code; and
prevent a side entry into the translated region of code at a translated return target (RET_TGT?) included in the translated region of code, wherein the RET_TGT? is translated from a return target (RET_TGT) in the guest instruction set architecture code, and
wherein the side entry is prevented based on an indication mapped to an instruction pointer of the RET_TGT.

US Pat. No. 10,191,743

VERSATILE PACKED DATA COMPARISON PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

Intel Corporation, Santa...

1. A processor comprising:a decode unit to decode a versatile packed data compare instruction, the versatile packed data compare instruction to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, each data element of the second source packed data operand to correspond to a data element of the first source packed data operand in a same relative position, and to indicate a source comparison operation indication operand that is to include at least four comparison operation indicators each operable to versatilely indicate a potentially different comparison operation for a different corresponding pair of corresponding data elements from the first and second source packed data operands, wherein the source comparison operation indication operand comprises a packed data operand that is to include at least four data elements that are each to include a different corresponding one of the comparison operation indicators, and wherein each comparison operation indicator is to be specified in a least significant byte of the corresponding data element; and
an execution unit coupled with the decode unit, the execution unit, in response to the versatile packed data compare instruction, to store a result in a destination storage location to be indicated by the versatile packed data compare instruction, the result to include at least four result indicators that are each to correspond to a different one of the at least four comparison operation indicators, each result indicator to indicate a result of a comparison operation, which is to be indicated by the corresponding comparison operation indicator, which is to have been performed on the corresponding pair of data elements from the first and second source packed data operands.

US Pat. No. 10,191,742

MECHANISM FOR SAVING AND RETRIEVING MICRO-ARCHITECTURE CONTEXT

Intel Corporation, Santa...

1. An apparatus comprising:an execution unit within a processor to execute a code block having been compiled to have a reserved space appended to one end, the reserved space including a metadata block associated with the code block, and a switch code sign signifying an end of the code block and a beginning of the reserved space, wherein the code block and the reserved space appended to its end occupy a contiguous region of memory and boundaries of the code block are defined by conditional instructions;
power management hardware coupled to the execution unit, wherein the power management hardware is to:
monitor a first execution of the code block;
store a micro-architectural context of the processor in the associated metadata block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters;
read the associated metadata block upon a second execution of the code block; and
tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block; and
wherein the metadata block associated with the code block stores the performance data collected from executing the associated code block on two different processor cores that have different performances, and wherein the power management hardware is to determine which one of the two different processor cores is to execute the associated code block based on the performance data.

US Pat. No. 10,191,741

SYSTEM AND METHOD FOR MITIGATING THE IMPACT OF BRANCH MISPREDICTION WHEN EXITING SPIN LOOPS

Oracle International Corp...

1. A method, comprising:performing by a computer:
determining that a sequence of program instructions comprises a conditional branch type instruction that includes a hint or parameter that indicates that a particular branch path should be predicted;
performing dynamic branch prediction of the conditional branch instruction;
in response to said determining, predicting that the path taken following the conditional branch type instruction will be the particular branch path indicated by the hint or parameter included in the conditional branch type instruction, wherein the prediction of the particular branch path according to the hint or parameter overrides an outcome of the dynamic branch prediction;
if the particular branch path is correctly predicted, continuing on the predicted branch path; and
if the particular branch path is incorrectly predicted, incurring a misprediction stall.

US Pat. No. 10,191,740

DEINTERLEAVE STRIDED DATA ELEMENTS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

Intel Corporation, Santa...

1. A processor comprising:a plurality of packed data registers;
a decode unit to decode an instruction, the instruction to indicate a source operand, to indicate a stride, to indicate at least one set of strided data element positions out of all sets of strided data element positions for the indicated stride, and to indicate at least one destination packed data register of the plurality of packed data registers; and
an execution unit coupled with the plurality of packed data registers, and coupled with the decode unit, the execution unit, in response to the instruction, for each of the indicated at least one set of strided data element positions, to store a corresponding result packed data operand, in a corresponding destination packed data register of the plurality of packed data registers, each result packed data operand to include a plurality of data elements, which are to be from the corresponding indicated set of strided data element positions of the source operand, in which strided data element positions of the set are to be separated from one another by integer multiples of the indicated stride.

US Pat. No. 10,191,735

LANGUAGE-INDEPENDENT PROGRAM COMPOSITION USING CONTAINERS

1. An apparatus comprising:a memory;
at least one hardware processor, coupled to said memory, and,
a non-transitory computer readable medium comprising computer executable instructions which when loaded into said memory configure said at least one hardware processor to:
obtain:
an action sequence comprising a plurality of actions; and
a corresponding input dictionary;
instantiate a first container running a first image for a first one of said actions implemented in a first programming language;
execute said first image for said first one of said actions on said input dictionary to obtain a first action result;
update said input dictionary with said first action result to obtain an updated input dictionary;
instantiate a second container running a second image for a second one of said actions implemented in a second programming language different than said first programming language;
execute said second image for said second one of said actions on said updated input dictionary to obtain a second action result; and
update said updated input dictionary with said second action result to obtain a further updated input dictionary;
wherein said input dictionary, said updated input dictionary, and said further updated input dictionary are independent of said first and second programming languages.

US Pat. No. 10,191,733

SOFTWARE CHANGE PROCESS ORCHESTRATION IN A RUNTIME ENVIRONMENT

SAP SE, Walldorf (DE)

1. A method comprising:defining, by a computer system, a set of software change processes across different platforms and environments;
mapping, by the computer system, each software change process to at least one tool for performing each software change process to generate a software change process map comprising a list of software change processes and at least one corresponding tool for performing each software change process;
receiving, at the computer system, an indication to initiate a software change process orchestration;
identifying, by the computer system, a first software change process and a second software change process to be performed for the software change process orchestration in response to receiving the indication;
accessing, by the computer system, the software change process map comprising the list of change processes mapped to at least one corresponding tool for performing each change process to identify at least one first corresponding tool for the first software change process and at least one second corresponding tool for the second software change process;
creating, by the computer system, a composed process by combining the first software change process to be performed for the software change process orchestration and the at least one first corresponding tool for performing the first software change process, and the second software change process and the at least one second corresponding tool for performing the second software change process;
triggering, by the computer system, execution of the at least one first corresponding tool for performing the first software change process and the at least one second corresponding tool performing the second software change process of the composed process, using a uniform software logistic protocol that manages calls to tools across different platforms and environments, the software logistic protocol comprising a uniform process interface that starts and monitors a software change process;
monitoring, by the computer system, status of an execution of the at least one first corresponding tool and the at least one second corresponding tool during the first software change process and the second software change process of the composed process; and
presenting, by the computer system, the status of the execution of the at least one first corresponding tool and the at least one second corresponding tool during the software first change process and the second software change process of the composed process on a uniform user interface that is process independent.

US Pat. No. 10,191,732

SYSTEMS AND METHODS FOR PREVENTING SERVICE DISRUPTION DURING SOFTWARE UPDATES

Citrix Systems, Inc., Fo...

1. A method for preventing service disruptions in a computing system, comprising:receiving, at a cloud-based computing system, a plurality of messages for initiating software updates requiring system reboots by a plurality of remote computing machines, where each said message is sent by a respective one of the remote computing machines to itself through a hosted maintenance service; and
performing operations by the cloud-based computing system to schedule maintenance operations across the plurality of remote computing machines for a performance of the system reboots in a one-machine-at-a-time manner, where the operations comprise
sequencing the plurality of messages across the remote computing machines so as to ensure that an operational state of only one remote computing machine of the plurality of remote computing machines is transitioned from an online state to an offline state at any given time; and
making the plurality of messages available to the remote computing machines in accordance with the sequencing.

US Pat. No. 10,191,731

SAFE AND AGILE ROLLOUTS IN A NETWORK-ACCESSIBLE SERVER INFRASTRUCTURE USING SLICES

Microsoft Technology Lice...

1. A method of rolling out updates to a network-accessible server infrastructure which operates a plurality of instances of a supporting service, the supporting service comprised by a plurality of service portions, the instances of the supporting service each including the plurality of service portions, the method comprising:receiving an indication of a partition of the instances of the supporting service into a plurality of slices, each instance of the supporting service partitioned to include one or more slices of the plurality of slices, each slice of an instance of the supporting service including one or more of the service portions of the instance of the supporting service; and
deploying a software update to the plurality of instances of the supporting service by
applying the software update to the plurality of slices in a sequence such that the software update is applied to a same slice in parallel across the instances of the supporting service containing that same slice before being applied to a next slice and
waiting a wait time after each applying of the software update to a slice of the plurality of slices before applying the software domain to a next slice of the plurality of slices in the sequence.

US Pat. No. 10,191,729

SYSTEM AND METHODOLOGY FOR UPDATING INDIVIDUALIZED SYSTEM DATA TO FACILITATE REPAIR AND/OR REPLACEMENT SERVICE PROVISION

Lenovo Enterprise Solutio...

1. A system, comprising:a storage device hosting a file system and implementing an operating system, the file system storing first individualized system data identifying a computer hardware component;
a replacement computer hardware component comprising an embedded storage module storing second individualized system data identifying the replacement computer hardware component;
wherein the embedded storage module is configured to implement a routine stored thereon using a processor or a controller of the system;
wherein the routine is configured to overwrite the first individualized system data with the second individualized system data in response to determining a mismatch between the first individualized system data and the second individualized system data;
wherein the storage device is physically separate from the computer hardware component and the replacement computer hardware component;
wherein the embedded storage module is configured to automatically implement the routine during a boot process of the system using a target disk mode function of the boot process;
wherein the embedded storage module is further configured to automatically implement the routine as part of a startup process of the operating system;
wherein the first individualized system data and the second individualized system data each comprise vital product data (VPD) corresponding to the computer hardware component; and
wherein the VPD comprises:
a manufacturer name corresponding to the replacement computer hardware component;
a location corresponding to the replacement computer hardware component, wherein the location includes a city name, a state, and a country name;
a serial number corresponding to the replacement computer hardware component, wherein the serial number is an uninterrupted string of alphanumeric characters excluding special characters and spaces;
a component type corresponding to the replacement computer hardware component, wherein the component type comprises a model name;
a universally unique identifier (UUID) corresponding to the replacement computer hardware component, wherein the UUID is a 128-bit value selected from the group consisting of: a MAC address: a DCE security value, a MD5 hash, and a SHA-1 hash; and
asset tag information corresponding to the replacement computer hardware component, wherein the asset tag information is a string encoded as a barcode on a physical tag applied to the replacement computer hardware component.

US Pat. No. 10,191,724

COMPILER-BASED INSTRUCTION SCOREBOARDING

INTEL CORPORATION, Santa...

1. An apparatus comprising:a processor to:
remove one or more unnecessary dependence edges from a data dependency graph which represents one or dependencies between instructions for execution on a processing device;
partition the data dependency graph into a plurality of sub-graphs based on dependence characteristics of the instructions for execution;
determine a live range for each of the plurality of sub-graphs; and
assign a scoreboard entry to each of the plurality of sub-graphs, wherein sub-graphs which have interfering live ranges are assigned different scoreboard indices which identify an execution order for operations in the plurality of sub-graphs.

US Pat. No. 10,191,696

IMAGE FORMING SYSTEM INCLUDING A FIRST IMAGE FORMING APPARATUS AND A SECOND IMAGE FORMING APPARATUS CONNECTED ON A DOWNSTREAM SIDE OF THE FIRST IMAGE FORMING APPARATUS

KONICA MINOLTA, INC., Ch...

1. An image forming system comprising: a first image forming apparatus; and a second image forming apparatus connected on a downstream side of the first image forming apparatus in a paper conveying direction,wherein the first image forming apparatus includes:
a first expander that expands a first image having image expansion time per page including a first time; and
a first image former that forms the first image expanded by the first expander, onto a first face of paper, and
the second image forming apparatus includes:
a second expander that expands a second image having image expansion time per page including a second time longer than the first time; and
a second image former that forms the second image expanded by the second expander, onto the first face on which the first image has been formed.

US Pat. No. 10,191,695

IMAGE FORMING APPARATUS CAPABLE OF MAKING BOOKLET, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM STORING CONTROL PROGRAM THEREFOR

CANON KABUSHIKI KAISHA, ...

5. A control method for an image forming apparatus comprising a reader configured to read an original having a plurality of pages, a storage device configured to store data, a display device configured to display information, and an image forming device configured to form images on a sheet, the control method comprising the steps of:obtaining an opening direction of the original read by the reader, based on a user instruction, the original being for a booklet to which a saddle stitch bookbinding is applied;
storing, in the storage device, print data of a plurality of images generated based on the plurality of pages of the original read by the reader and the opening direction of the original, the plurality of images being printable by the image forming device;
receiving a selection of images to be printed, from among the plurality of images, based on a user instruction;
displaying a plurality of opening directions on the display device as a setting screen about bookbinding print of the selected images, with the stored opening direction initially selected among the displayed plurality of opening directions;
receiving a selection of an opening direction based on a user instruction from among the displayed plurality of opening directions;
determining a print layout based on the received selection of the opening direction; and
causing, in a case where the saddle stitch bookbinding is applied, the image forming device to form the selected images according to the determined print layout.

US Pat. No. 10,191,682

PROVIDING EFFICIENT LOSSLESS COMPRESSION FOR SMALL DATA BLOCKS IN PROCESSOR-BASED SYSTEMS

QUALCOMM Incorporated, S...

1. A compressed memory controller (CMC), comprising:a mask table providing a plurality of masks and an associated plurality of prefixes;
a pattern identification circuit configured to:
receive a plurality of input words;
for each mask of the plurality of masks of the mask table:
apply the mask to each unassigned input word of the plurality of input words to generate a corresponding plurality of patterns;
determine whether a most frequently occurring pattern exists among the plurality of patterns; and
responsive to determining that a most frequently occurring pattern exists among the plurality of patterns:
output the most frequently occurring pattern and an uncompressed data portion of each unassigned input word to an output generation circuit in association with a prefix of the plurality of prefixes associated with the mask; and
assign the prefix associated with the mask to each unassigned input word corresponding to the most frequently occurring pattern; and
output a plurality of assigned prefixes assigned to the plurality of input words to the output generation circuit;
the output generation circuit configured to generate a compressed output block comprising:
the plurality of assigned prefixes assigned to the plurality of input words;
one or more most frequently occurring patterns, each associated with one of the plurality of assigned prefixes; and
one or more uncompressed data portions of a corresponding one or more input words of the plurality of input words.

US Pat. No. 10,191,680

MEMORY ACCESS CONTROL

Hewlett Packard Enterpris...

1. A method performed on a computing device, comprising:receiving a request to execute an instruction specified to access a first unit of memory identified by a target address, wherein the instruction is associated with a second unit of memory associated with a source address;
identifying a sensitivity value of the target address, wherein identifying the sensitivity value comprises extracting bits from the target address;
identifying a trust value of the source address, wherein identifying the trust value comprises extracting bits from the source address; and
determining whether the request to execute the instruction is trusted to access the first memory unit based on the sensitivity value of the target address and the trust value of the source address.

US Pat. No. 10,191,664

MEMORY SYSTEM

SK Hynix Inc., Gyeonggi-...

1. A memory system comprising:a first memory device including a first memory and a first memory controller configured to control the first memory to store data;
a second memory device including a second memory and a second memory controller configured to control the second memory to store data; and
a processor is configured to execute an operating system (OS) and an application to access a data storage memory through the first and second memory devices,
wherein the first and second memories are separated from the processor,
wherein the second memory controller transfers a signal between the processor and the second memory device based on at least one of values of a handshaking information field included in the signal,
wherein the first memory includes a plurality of first high-capacity memory cores configured to work as cache memories for the second memory,
wherein the first memory device further includes a first memory management logic operatively and commonly coupled with the plurality of first high-capacity memory cores, and configured to support high-speed data communication between the processor and the plurality of first high-capacity memory cores,
wherein the second memory includes a plurality of second high-capacity memory cores configured to work as system memories,
wherein the second memory device further includes a second memory management logic operatively and commonly coupled with the plurality of second high-capacity memory cores, and configured to support data communication between the processor and the plurality of second high-capacity memory cores,
wherein the second memory management logic includes a buffer configured to buffer write data, based on which the plurality of second memory cores are updated,
wherein the second memory controller firstly buffers the write data in the buffer, and then the second memory management logic independently updates the plurality of second memory cores based on the buffered write data, and
wherein the at least one of values of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

US Pat. No. 10,191,658

LIFECYCLE FOR OFFLINE DATA

SAP SE, Walldorf (DE)

10. The system of claim 9, the operations further comprising, in response to determining that a trigger associated with performing a memory management process has occurred based on the set of memory management rules:identifying, by the memory management process and from the set of memory management rules, a threshold age of particular offline data instances corresponding to a deletion action;
comparing, by the memory management process, the identified threshold age to a current age for each of the set of offline data instances based on their respective creation timestamp or the most recent time of access; and
deleting, by the memory management process and from the set of memory management rules, at least a subset of the set of offline data instances wherein the age of a particular offline data instance meets or exceeds the identified threshold age of the particular offline data instances.

US Pat. No. 10,191,650

ACTIONABLE CONTENT DISPLAYED ON A TOUCH SCREEN

MICROSOFT TECHNOLOGY LICE...

1. A computer-implemented method comprising:displaying media on a touchscreen display, the media including a photograph;
detecting a user gesture performed on the touchscreen display;
determining text selected by the user gesture;
determining a user intent based at least partly on the text selected by the user gesture;
determining a context associated with the text selected by the user gesture based on the user intent, the context including additional text captured in the media, wherein the additional text is associated with the text selected by the user gesture; and
automatically performing one or more follow-up actions based at least partly on the text selected by the user gesture and based at least partly on the context.

US Pat. No. 10,191,584

REDUCING CONNECTIONS FROM A SENSING MODULE

Synaptics Incorporated, ...

1. An input device, comprising:a first glass layer;
a plurality of transmitter electrodes disposed on the first glass layer and configured for capacitance sensing;
a second glass layer;
a plurality of receiver electrodes disposed on the second glass layer and configured for capacitance sensing; and
a multiplexer disposed on the first glass layer and coupled to a plurality of sources and a sensing channel,
wherein the multiplexer selectively couples one of the plurality of sources to the sensing channel based on at least a control signal, and
wherein the plurality of sources comprises the plurality of transmitter electrodes and the plurality of receiver electrodes.

US Pat. No. 10,191,580

DISPLAY DEVICE AND METHOD OF DRIVING THE SAME IN TWO MODES

Samsung Display Co., Ltd....

1. A display device, comprising:a display panel comprising a first display substrate and a second display substrate facing the first display substrate;
scan line groups, each scan line group comprising a first scan line sub-group, a second scan line sub-group connected to the first scan line sub-group, and a third scan line sub-group disposed between the first scan line sub-group and the second scan line sub-group;
source line groups, each source line group comprising a first source line sub-group, a second source line sub-group connected to the first source line sub-group, and a third source line sub-group disposed between the first source line sub-group and the second source line sub-group;
a first driver configured to provide first scan signals to the scan line groups in a first mode and to provide second scan signals to the scan line groups in a second mode, a magnetic field being induced by a current path formed by the first scan line sub-group and the second scan line sub-group;
a second driver configured to provide first sensing signals corresponding to a variation in a capacitance from the source line groups in the first mode, and to provide second sensing signals according to a resonant frequency associated with an input device, the second sensing signals being provided from the source line groups in the second mode; and
a touch sensor configured to receive the first sensing signals and the second sensing signals and to determine coordinate information of an input position based on the first sensing signals and the second sensing signals.

US Pat. No. 10,191,575

IN-CELL TOUCH TYPE LIQUID CRYSTAL DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. A liquid crystal display device comprising:a substrate including first and second touch blocks adjacent to each other, the first and second touch blocks including first and second sub-pixels, respectively;
a first electrode in each of the first and second sub-pixels;
a second electrode in each of the first and second touch blocks, wherein the second electrode of the first touch block and the second electrode of the second touch block are separated from each other;
first and second data lines disposed at side portions of the first and second sub-pixels, respectively; and
wherein the first and second sub-pixels face in the same direction, and are disposed between the first and second touch blocks,
wherein the first and second sub-pixels are disposed between the first and second data lines, and a field blocking line is disposed between the first and second sub-pixels.

US Pat. No. 10,191,569

OPERATING TOOL, INPUT DEVICE, AND ELECTRONIC DEVICE

MITSUBISHI ELECTRIC CORPO...

1. An operating tool comprising:a holder to be fixed onto a detection surface of a touch panel;
a movable member movably supported by the holder;
a movable contact point that is provided on the movable member, and that moves, while making contact with the detection surface of the touch panel, as the movable member moves; and
a plurality of holder contact points that are provided on the holder, and that are to be in contact with the detection surface of the touch panel in a positional relationship of the plurality of holder contact points, the positional relationship corresponding to a function of the operating tool, wherein
the touch panel is a capacitance-type touch panel,
the movable member, the movable contact point, and the plurality of holder contact points are formed of electrically-conductive members,
the holder is formed of an electrically non-conductive member, and
the plurality of holder contact points are electrically connected to the movable member.

US Pat. No. 10,191,553

USER INTERACTION WITH INFORMATION HANDLING SYSTEMS USING PHYSICAL OBJECTS

Dell Products, L.P., Rou...

1. A method for user interaction with information handling systems, the method comprising:acquiring image data associated with an information handling system;
identifying a plurality of physical objects from the image data including a first physical object used by a user;
identifying that the first physical object corresponds to a virtual input device from a set of virtual input devices accessible to the information handling system;
identifying a virtual input device category of the virtual input device from a set of virtual input device categories of the set of virtual input devices;
updating tracking information for the virtual input device corresponding to the first physical object, wherein the tracking information is based on a motion of the first physical object;
assigning the virtual input device as an active virtual input device associated with user input to the information handling system;
determining a gesture from a motion of the virtual input device performed by the user corresponding to the tracking information based on the virtual input device category;
identifying a user input command associated with the virtual input device based on the gesture from a set of user input commands accessible to the information handling system and the virtual input device category; and
executing the user input command on the information handling system based on the virtual input device category, wherein the set of virtual input device categories comprise a pointer category, a stylus category, and a dial category.

US Pat. No. 10,191,548

OPERATION APPARATUS

FUJITSU TEN LIMITED, Kob...

1. An operation apparatus that is operable in a plurality of operation modes, the operation apparatus comprising:a touch sensor that generates an output based on an operation performed to the touch sensor by an operator;
a transducer attached to the touch sensor and configured to vibrate the touch sensor so as to give a touch feeling to the operator contacting the touch sensor; and
a controller configured to (i) determine a content of the operation performed to the touch sensor by the operator based on the output of the touch sensor and (ii) select one of the plurality of operation modes based on the determined content of the operation performed to the touch sensor by the operator, wherein
the controller causes the transducer to vibrate the touch sensor with different patterns of vibration so as to give different touch feelings to the operator contacting the touch sensor depending on the determined content of the operation performed to the touch sensor by the operator, the patterns of vibration resulting in a slippery touch feeling, a click touch feeling or a rough touch feeling depending on the operation mode, and
when an adjustment operation is performed after the operation mode is started, a predetermined touch feeling selected from the different touch feelings is given to the operator each time when an operation amount reaches a predetermined amount, the adjustment operation including an operation of drawing a circle or a line, the predetermined amount including an operation distance and a direction of the operation of drawing the cirlci or the line.

US Pat. No. 10,191,543

WEARABLE DEVICE TOUCH DETECTION

Microsoft Technology Lice...

1. A wearable device comprising:at least one pressure sensor on an inner surface of the wearable device, the at least one pressure sensor being configured to detect pressure imparted on the inner surface of the wearable device by a user wearing the wearable device;
at least one other sensor configured to detect movement of the wearable device; and
at least one processor or hardware logic circuit configured to:
based at least on the pressure imparted on the inner surface of the wearable device being detected by the at least one pressure sensor, detect that the user is touching a surface other than the inner surface of the wearable device; and
activate the at least one other sensor responsive to detecting that the user is touching the surface other than the inner surface of the wearable device.

US Pat. No. 10,191,541

AUGMENTING VIRTUAL REALITY CONTENT WITH REAL WORLD CONTENT

Sony Interactive Entertai...

1. A method for changing a virtual reality scene displayed in a head mounted display (HMD), comprising:obtaining sensor data from sensors on the HMD, the sensors including inertial sensors;
processing the sensor data for determining that a criteria is met to transition from the virtual reality scene to an augmented virtual reality scene to be presented by the HMD, the criteria corresponding to predetermined indicators that are suggestive of disorientation of a user when wearing the HMD and being presented the virtual reality scene, the augmented virtual reality scene being a modified version of the virtual reality scene;
overlaying, based on said determining that the criteria is met, at least part of a real world object from a real world view into the virtual reality scene for the augmented virtual reality scene, the real world view being captured by one or more cameras of the HMD;
determining that the criteria is still met after said overlaying and continuing to sequentially overlay additional real world objects as long as the criteria is still met.

US Pat. No. 10,191,539

USER AWARE ODOMETRY CORRECTION TECHNOLOGY

Intel Corporation, Santa...

1. A system comprising:a display;
a camera;
wireless interface circuitry;
a battery;
a housing including a wearable form factor;
one or more drift detectors to generate one or more first signals;
a perception monitor to generate one or more second signals;
one or more processors;
memory; and
one or more storage devices to store instructions, which when executed by at least one of the one or more processors, cause the system to:
detect a pose drift condition with respect to the display based on at least one of the one or more first signals;
detect a reduced perception state with respect to a wearer of the display based on at least one of the one or more second signals; and
trigger a correction of the pose drift condition during the reduced perception state that is to include a selection of a pre-assigned value based on a perception tolerance in the reduced perception state and an application of the pre-assigned value to the display.

US Pat. No. 10,191,538

ELECTRONIC DEVICE DISPLAYS AN IMAGE OF AN OBSTRUCTED TARGET

1. A method executed in a computer system in which two wearable electronic devices (WEDs) capture information while at a geographical location to display a three-dimensional (3D) image of a person that is obstructed from view to one of the two WEDs, the method comprising:capturing, with a first WED at the geographical location, an image of the person;
capturing, with a second WED at the geographical location, an object that blocks the person from being visible with the second WED;
determining, based on the image of the person captured with the first WED and the object captured with the second WED, a location where the person would be visible to the second WED if the person were not blocked by the object; and
displaying, with a display of the second WED at the geographical location, the 3D image of the person over the object at the location where the person would be visible to the second WED if the person were not blocked by the object.

US Pat. No. 10,191,537

SMART WEARABLE DEVICES AND METHODS FOR CUSTOMIZED HAPTIC FEEDBACK

SONY CORPORATION, Tokyo ...

1. A wearable sensor apparatus, comprising:(a) a processor;
(b) a plurality of sensors operably coupled to the processor, said sensors comprising at least one biological sensor configured to measure an internal physical condition of a wearer and at least one non-biological sensor configured to measure an external condition of a wearer;
(c) at least one haptic output coupled to the processor;
(d) a communications module operably coupled to the processor, the module having a transmitter and a receiver: and
(e) programming in a non-transitory computer readable medium and executable on the processor for performing steps comprising:
(i) designating a haptic output for possible sensor results of each sensor;
(ii) acquiring sensor data from at least one sensor worn by a user;
(iii) processing the acquired sensor data with possible sensor results;
(iv) initiating the designated haptic output for matching sensor data;
(v) communicating acquired sensor data to a remote computer;
(vi) executing program commands received from the remote computer;
(vii) identifying at least one possible sensor result from a sensor;
(viii) designating a recipient of a communication regarding the sensor result; and
(ix) sending the communication to the recipient over the communications module when the acquired sensor data and the possible sensor results match.

US Pat. No. 10,191,536

METHOD OF OPERATING A CONTROL SYSTEM AND CONTROL SYSTEM THEREFORE

KONINKLIJKE PHILIPS N.V.,...

1. A method of operating a control system for controlling a device, the control system comprising a motion capture equipment, and a controller for providing control signals for controlling one or more device functions of the device, the method comprising the steps of:capturing, by the motion capture equipment, motion picture images of a space and providing the motion picture images to the controller;
performing a pattern recognition analysis on one or more of the motion picture images for distinguishing input from known and unknown users,
analyzing, by the controller, the motion picture images for detecting user input from a user in the space, comprising:
monitoring one or more gesture zones in said motion picture images, each gesture zone being associated with one respective device function of said one or more device functions,
determining the gesture zone wherein the gesture is detected for establishing the selected device function to control,
detecting by the controller a gesture performed by the user; and
providing, by the controller in response to said detecting of the gesture, a control signal to the device for controlling a selected device function of said one or more device functions.

US Pat. No. 10,191,535

REDUCED ENERGY CONSUMPTION IN A COMPUTER SYSTEM THROUGH SOFTWARE AND HARDWARE COORDINATED CONTROL OF MULTIPLE POWER SUPPLIES

Apple Inc., Cupertino, C...

1. A computing system, comprising:a standby power supply electrically coupled to a sensor, wherein the sensor is configured to produce a sensor signal based on an output from the standby power supply during a standby mode of the computing system; and
a controller electrically coupled to the sensor, wherein the controller is configured to:
receive the sensor signal from the sensor,
when the sensor signal indicates that the output has reached or exceeded an output threshold, enable a main power supply to provide power to an external load removably attached to the computing system, and
determine whether the external, removably attached load is a memory device and provide an enable signal to the main power supply when the memory device has a capacity that is equal to or greater than a memory threshold.

US Pat. No. 10,191,534

STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS

TEXAS INSTRUMENTS INCORPO...

1. A cache memory system, comprising:a cache memory including a tag memory array and a data memory array, wherein the data memory array includes a plurality of cache lines and being divided into a plurality of cache ways, wherein the cache memory is configured to access data in a plurality of addressable locations of the data memory array in response to cache access requests, each cache access request including a request address;
a plurality of pipeline stages, each pipeline stage receiving a respective request address corresponding to one of the cache access requests;
a plurality of buffers, each buffer receiving a respective request address corresponding to one of the cache access requests;
a plurality of decoders, each decoder receiving bits from a set field of a request address received at a respective one of either the pipeline stages or the buffers, and configured to decode the received bits of the set field to output a set of decoded output signals;
a plurality of logic gates to receive the sets of decoded output signals from each of the plurality of decoders, each logic gate outputting a respective power enable signal; and
a memory nap controller to track in-flight cache accesses and to control a desired power state of at least a first group of a plurality of contiguous cache lines of the data memory array, the first group of the plurality of contiguous cache lines being organized as a first power group, wherein the first power group is controllable to be in one of a first desired power state or a second desired power state in response to a first power group enable signal output by the memory nap controller, wherein the first power group receives a first voltage in the first desired power state and a second voltage in the second desired power state, the first voltage being greater than the second voltage, and wherein the first power group enable signal is generated based on a plurality of the power enable signals output by the plurality of logic gates, the plurality of the power enable signals upon which the first power group enable signal is generated including at least a subset of all of the power enable signals.

US Pat. No. 10,191,532

CONFIGURING POWER MANAGEMENT FUNCTIONALITY IN A PROCESSOR

Intel Corporation, Santa...

1. A system comprising:a plurality of processors;
a processor interconnect to communicatively couple two or more of the plurality of processors;
a system memory comprising a dynamic random access memory communicatively coupled to one or more of the plurality of processors over a memory interconnect;
at least one of the plurality of processors comprising:
a plurality of cores formed on a single semiconductor die, a core of the plurality of cores to execute one or more threads;
the core of the plurality of cores comprising a fetch unit to fetch instructions from an instruction cache, a decode unit to decode the instructions and a plurality of execution units to perform out-of-order execution of the instructions;
one or more control registers to store a first indication that two or more cores of the plurality of cores are to operate at independent performance states comprising active power states in which the two or more cores are to operate at different frequencies and a second indication that a first set of cores are to operate at a common performance state comprising an active power state in which the first set of cores are to operate at a common frequency;
a plurality of voltage regulators formed on the single semiconductor die, a voltage regulator of the plurality of voltage regulators associated with one of the plurality of cores;
a power controller formed on the single semiconductor die, the power controller to control the plurality of voltage regulators to provide a voltage and/or frequency to a first core of the plurality of cores independently of a voltage and/or frequency to one or more other cores and to determine whether to update the voltage and/or frequency of the first core based on a workload of the first core, thermal constraints, and activity counters; and
at least one additional voltage regulator formed on the single semiconductor die and associated with processor circuitry external to the plurality of cores, the at least one additional voltage regulator to allow the processor circuitry external to the plurality of cores to operate at a different voltage and/or frequency than one or more cores of the plurality of cores.

US Pat. No. 10,191,531

HYBRID CONVERTER SYSTEM

GENERAL ELECTRIC COMPANY,...

1. A voltage converter, comprising:a first set of silicon (Si)-based power devices coupled to a first direct current (DC) voltage source;
a second set of Si-based power devices coupled to a second DC voltage source;
a first set of silicon-carbide (SiC)-based power devices coupled to the first set of Si-based power devices and to the second set of Si-based power devices, wherein each SiC-based power device of the first set of SiC-based power devices is configured to switch at a higher frequency as compared to each Si-based power device of the first and second sets of the Si-based power electronic devices;wherein Si-based power devices in the voltage converter are twice that of SiC-based power devices in the voltage converter;wherein the voltage converter further comprises:a capacitor coupled to across the first set of SiC-based power devices;
wherein the first set of SiC-based power devices is connected across a first output terminal of the first set of Si-based power devices and a second output terminal of the second set of Si-based power devices; and
wherein the first and second output terminals of the first and second sets of Si-based power devices are obtained at interconnection points of Si-based power devices in the first and second sets respectively.

US Pat. No. 10,191,530

SELF-CONTAINED METHOD AND DEVICE FOR MANAGING A FIRST ELECTRONIC APPARATUS

Orange, Paris (FR)

1. A method for managing a multimedia providing apparatus, the multimedia providing apparatus comprising a functional device that in operation provides multimedia data to a multimedia production apparatus for use by the multimedia reproduction apparatus and a management device, wherein the multimedia providing apparatus and the multimedia reproduction apparatus are locally connected, the method, carried out by the management device, comprising:transmitting, from the management device of the multimedia providing apparatus to the multimedia reproduction apparatus, a request for the status of the multimedia reproduction apparatus;
receiving, at the management device of the multimedia providing apparatus from the multimedia reproduction apparatus in response to the request, data indicating the activity status of the multimedia reproduction apparatus; and
changing, by the management device, the activity state of the functional device of the multimedia providing apparatus based on the activity status indicated by the received data.

US Pat. No. 10,191,529

REAL-TIME DATA MANAGEMENT FOR A POWER GRID

ACCENTURE GLOBAL SERVICES...

1. A method for data transfer in a power grid, the method comprising:monitoring, by a processor, a data transfer rate at which power grid data is communicated to data consumer instances via a communication bus, the communication bus configured to exchange the power grid data between data producers and the data consumer instances, the power grid data comprising data related to the power grid received from a plurality of different equipment operable as the data producers within the power grid;
identifying, by the processor, sub-processes of a data consumer instance that process power grid data only in parallel and sub-processes of the data consumer instance that process power grid data only in serial, wherein the sub-processes of the data consumer instance that process the power grid data only in parallel comprise parallelizable threads and the sub-process of the data consumer instance that process the power grid data only in serial comprise non-parallelizable threads;
determining, by the processor, an estimated parallel processing time of the sub-processes of the data consumer instance that process power grid data only in parallel and an estimated serial processing time of the sub-processes of the data consumer instance that process power grid data only in serial; and
controlling, by the processor, the data transfer rate based the estimated parallel processing time and the estimated serial processing time.

US Pat. No. 10,191,528

SENSOR FOR DETECTING PRESENCE OF MATERIAL

Apple Inc., Cupertino, C...

1. A device comprising:one or more sensors configured to detect a material covering the device; and
logic coupled to the one or more sensors, the logic configured to:
detect one or more characteristics of the material covering the device, wherein the material has a first characteristic if the material is covering a first portion of the device from a first direction, and has a second characteristic if the material is covering the first portion of the device from a second direction different from the first direction, and
change an operating state of the device based on the detected one or more characteristics, wherein changing the operating state comprises:
in accordance with the material having the first characteristic, the device entering a first operating state, and
in accordance with the material having the second characteristic, the device entering a second operating state different from the first operating state.

US Pat. No. 10,191,527

BROWN-OUT DETECTOR

ARM Limited, Cambridge (...

1. An integrated circuit, comprising:a first stage having first transistors and resistors arranged to receive an input voltage and provide a first voltage that is substantially independent of temperature while remaining related to the input voltage;
a second stage configured to provide a single-ended to differential up-converter circuit and having second transistors arranged to receive the input voltage and receive the first voltage from the first stage and up-convert the first voltage as the input voltage lowers, wherein the second stage is configured to provide a second voltage corresponding to a differential voltage of the input voltage and the first voltage; and
a third stage having third transistors arranged to receive the second voltage and provide a high-gain output voltage corresponding to an error signal.

US Pat. No. 10,191,525

MODULES STORING POWER CONFIGURATION PARAMETERS

HEWLETT PACKARD ENTERPRIS...

1. A method comprising:detecting a presence of a module in a socket;
based on detecting the presence of the module, supplying power to a memory of the module while restricting power to an integrated circuit of the module;
reading information stored in the memory of the module that specifies a power-on sequence for the integrated circuit of the module; and
applying power to the integrated circuit of the module according to the power-on sequence specified in the information when an alignment of the module with the socket is confirmed.

US Pat. No. 10,191,524

LOW-POWER TYPE-C RECEIVER WITH HIGH IDLE NOISE AND DC-LEVEL REJECTION

Cypress Semiconductor Cor...

1. A device comprising:a receiver circuit coupled to a Configuration Channel (CC) line of a Universal Serial Bus (USB) Type-C subsystem, wherein the receiver circuit is configured to:
receive valid BMC-encoded data from an incoming signal on the CC line when the incoming signal has more than 250 mV of direct current (DC) offset with respect to a local ground; and
operate in the presence of a VBUS charging current that is specified in a USB-PD specification.

US Pat. No. 10,191,523

SYSTEMS AND METHODS FOR MANAGEMENT OF EXHAUST TEMPERATURE IN AN INFORMATION HANDLING SYSTEM

Dell Products L.P., Roun...

1. An information handling system comprising:at least one information handling resource, including a first and a second information handling resource;
heat-rejecting media thermally coupled to the at least one information handling resource for transferring heat generated to an exterior of an enclosure housing the at least one information handling resource, wherein the heat-rejecting media is proximate to an exhaust of the enclosure such that the heat-rejecting media is subject to physical contact with a user of the information handling system via the exhaust while the information handling system is operational and while the enclosure is closed;
a temperature sensor for sensing an ambient temperature associated with the at least one information handling resource; and
a thermal management driver comprising a program of instructions embodied in non-transitory computer-readable media and executable by a processor, the thermal management driver configured to:
based on a first power consumed by the first information handling resource, a second power consumed by the second information handling resource, and thermal resistances associated with the heat-rejecting media, calculate an exhaust temperature and a second exhaust temperature of the heat-rejecting media proximate to, respectively, the exhaust of the enclosure and a second exhaust of the enclosure; and
based on a determination that at least one of the exhaust temperature and the second exhaust temperature is greater than a maximum temperature that is safe for human contact, control at least one of an operating frequency of the at least one information handling resource and a flow rate of fluid proximate to the heat-rejecting media to lower the at least one of the exhaust temperature and the second exhaust temperature to a new exhaust temperature that is below the maximum temperature that is safe for human contact.

US Pat. No. 10,191,508

PERIPHERAL MODULE AND CIRCUIT ARRANGEMENT FOR A DIGITAL INPUT OF THE PERIPHERAL MODULE

Siemens Aktiengesellschaf...

1. A circuit arrangement for a digital input of an electronic peripheral module, comprising:an inlet connection forming a digital input;
a ground connection;
a semiconductor switching device arranged between the inlet connection and the ground connection, said semiconductor switching device limiting an input current;
a reference voltage source connected to a control input of the semiconductor switching device to control the semiconductor switching device; and
a regulator configured to regulate the reference voltage source depending on an input voltage at the inlet connection such that, for a first voltage value, the semiconductor switching device adjusts the input current for the input voltage to a first input current and, for a second voltage value, adjusts the first input current for the input voltage to a second input current;
wherein the first voltage value is greater than the second voltage value and the first input current is less than the second input current on account of the regulator;
wherein the semiconductor switching device comprises a first transistor with a collector, an emitter and a base, the base being connected to the control input, and the regulator including a second transistor with a collector, an emitter and a base, the base of the second transistor being connected to the collector of the first transistor via a voltage divider and the collector of the second transistor being connected to the control input; and
wherein the electronic peripheral module includes a means for level detection which is connected to the inlet connection.

US Pat. No. 10,191,472

NUMERICAL CONTROLLER PROVIDED WITH PROGRAM PRE-READING FUNCTION

FANUC Corporation, Minam...

1. A numerical controller which executes a plurality of numerical control (“NC”) programs at a same time in parallel by successively pre-reading blocks of the plurality of NC programs from a memory or from a storage device connected via a network so that the generation of an alarm or an immediate axes stop due to the pre-reading failing to be performed in time becomes less liable to occur, the numerical controller comprising:non-transitory computer readable memory;
one or more hardware processors coupled to the non-transitory memory and configured to read instructions from the non-transitory memory to cause the numerical controller to perform operations comprising:
storing execution times of the respective blocks in the plurality of NC programs;
reading out, when one block in an NC program among the plurality of NC programs is pre-read, the execution time of the pre-read block, and calculates a sum total of the execution time of the pre-read block and the execution times of other blocks in the NC program which have been pre-read;
extracting, from the plurality of NC programs, one NC program having the smallest sum total of the execution times calculated; and
subsequently performing pre-reading of one block of the NC program which is extracted and has the smallest sum total of the execution times among those of the plurality of NC programs.

US Pat. No. 10,191,271

IMAGE PICKUP SYSTEM

OLYMPUS CORPORATION, Tok...

1. An image pickup system comprising:a light source apparatus configured to sequentially emit lights with a plurality of mutually different wavelength bands as illumination light for illuminating an object;
an objective optical system configured to form an image of light from the object illuminated by the illumination light;
an image pickup device provided with an image pickup surface formed by two-dimensionally arranging a plurality of pixels for receiving the light formed by the objective optical system and photoelectrically converting the received light to generate electric signals;
a judging portion configured to perform a judgment process for judging: the object is observed in which of a distant view and a near view; and
an image pickup control portion configured to perform control for setting a reading mode of the image pickup device to either a single pixel reading mode which is a mode for sequentially reading the electric signals generated by the respective pixels arranged on the image pickup surface one by one, or a pixel addition reading mode which is a mode for, with electric signals generated by one pixel group constituted by a plurality of pixels arranged mutually adjoining one another on the image pickup surface as electric signals corresponding to one pixel, sequentially reading the electric signals corresponding to one pixel, according to a judgment result obtained by the judgment process of the judging portion; wherein
the light source apparatus is configured to be able to sequentially emit light of a red wavelength band, light of a green wavelength band and light of a blue wavelength band as the illumination light; and
the image pickup control portion performs control for setting the reading mode of the image pickup device to the single pixel reading mode when a judgment result that the object is observed in the distant view is obtained, and it is detected that the light of the blue wavelength band is emitted from the light source apparatus as the illumination light; and performs control for setting the reading mode of the image pickup device to the pixel addition reading mode when the judgment result that the object is observed in the distant view is obtained, and it is detected that the light of the red wavelength band is emitted from the light source apparatus as the illumination light.

US Pat. No. 10,191,246

ZOOM LENS AND IMAGING APPARATUS

FUJIFILM Corporation, To...

1. A zoom lens consisting of, in order from an object side:a first lens group that has a positive refractive power;
a second lens group that has a negative refractive power;
a third lens group that has a positive refractive power;
a fourth lens group that has a negative refractive power; and
a fifth lens group that has a positive refractive power,
wherein all intervals between the lens groups adjacent to each other change during zooming,
wherein an aperture diaphragm is disposed between a surface of the second lens group closest to an image side and a surface of the fourth lens group closest to the object side,
wherein the first lens group and the fifth lens group each consist of two or less lenses,
wherein a lens of the second lens group closest to the object side is a meniscus lens which has a negative refractive power and of which an object side surface has a convex shape,
wherein a lens of the fourth lens group closest to the image side is a meniscus lens which has a negative refractive power and of which an image side surface has a convex shape, and
wherein the following conditional expression (3) is satisfied,
?0.35 where f4 is a focal length of the fourth lens group, and
f1 is a focal length of the first lens group.

US Pat. No. 10,191,243

EXPANDABLE MIRRORS

FORD GLOBAL TECHNOLOGIES,...

5. A mirror implementable in a vehicle, comprising:a first pane having a first reflective surface;
a second pane having a second reflective surface;
a third pane having a third reflective surface,
a mechanism connected with each of the first and second panes, wherein the mechanism is configured, when actuated, to expand a viewing area of the mirror from a first size to a second size larger than the first size, the expanded viewing area comprising the first and second reflective surfaces; and
a positioning motor configured to integrally position the first pane and the second pane as a whole for adjusting an orientation of the viewing area of the mirror,
wherein the mechanism comprises a plurality of guiding rails connecting the first, second and third panes, and wherein the mechanism is configured to expand the viewing area of the mirror by sliding the second and third panes along the plurality of guiding rails to expose each of the first, second and third reflective surfaces such that the viewing area of the mirror comprises the first, second and third reflective surfaces.

US Pat. No. 10,191,219

OPTICAL SELECTOR ARRANGEMENT

BAE Systems plc, London ...

1. An optical selector arrangement, comprising:a first set of optical ports, having a first number of optical ports, the first number being greater than or equal to 2;
a second set of optical ports for communicating with the first set of optical ports, the second set of optical ports having a second number of optical ports, the second number being greater than the first number;
a selector interface comprising the second set of optical ports; and
a selector arranged to selectively optically couple the first set of optical ports to a subset of the second set of optical ports of the selector interface corresponding to the first number of optical ports, the selector being rotatable relative to the selector interface to facilitate the selection by optically aligning the first set of optical ports to the subset of the second set of optical ports of the selector interface, the selector being configured to be continuously relatively rotatable over multiple rotations, so as to selectively optically couple the first set of optical ports to a different subset of the second set of optical ports of the selector interface.

US Pat. No. 10,191,150

HIGH PRECISION RADAR TO TRACK AERIAL TARGETS

1. High Precision Radar To Track Aerial Targets, installed on the ground, in a container or in a vehicle, which determines the following parameters of the target, namely, azimuth angle (?a), elevation angle (?e), range, speed and flying direction and transmits them to another system said radar comprising an array of two collinear antennas with narrow beam in elevation wherein electromagnetic wave energy radiated from said antennas is spread over a 120-degrees beam width in azimuth installed on a platform and rotating around a vertical axis at a rotational frequency of, at least, 50 rpm, wherein the precise azimuth angle of the target (?a) is determined through correlation of the signal detected by the said antennas and a +1/?1 step function, wherein an adder is configured to sum the signals of target localizers gaining 3 dB wherein a correlator is configured to correlate an output lobe of the adder and the +1/?1 function, wherein a zero localizer is configured to search for a transition of said correlated signal through zero.

US Pat. No. 10,191,138

RFID-BASED SYSTEMS FOR MONITORING LARGE AREAS

AVERY DENNISON RETAIL INF...

1. A system for locating RFID tags in an area, comprising:a platform;
an RFID reader head associated with the platform;
at least one support extending between the platform and an anchor position within an area, with a separate anchor position being associated with each support; and
at least one support adjustment device, with a separate support adjustment device being associated with each support, wherein each support adjustment device is operable to adjust the length of the associated support between the platform and the anchor position associated with said support, thereby varying the location of the RFID reader head in the area.

US Pat. No. 10,191,016

METHOD AND SYSTEM FOR PASSIVE DETECTION, LOCALIZATION AND CHARACTERIZATION OF MECHANICAL WAVE SOURCES USING ULTRASONIC GUIDED WAVES

1. A method of estimating and storing for subsequent, non-contemporaneous use, one or more spatial channel impulse responses corresponding to one or more spatial points of interest on a structure when the structure is in a known state comprising:collecting first data at one or more spatial points of interest on the structure using a movable transducer, used only in this step, wherein collecting first data includes individually exciting at least one fixed transducer on the structure with a known excitation function and recording measurements at the one or more spatial points of interest with the movable transducer;
computing one or more spatial channel impulse response estimates for each of the one or more spatial points of interest based on the collected first data; and
storing said spatial channel impulse response estimates for subsequent, non-contemporaneous use after the structure has transitioned to an unknown state.

US Pat. No. 10,191,015

OBJECT INFORMATION ACQUIRING APPARATUS AND LASER APPARATUS

CANON KABUSHIKI KAISHA, ...

1. An object information acquiring apparatus comprising:irradiation means configured to irradiate an object with a laser beam;
a shutter unit having a shutter disposed on a light path of the laser beam from the irradiation means to the object, configured to restrict an output of the laser beam from the irradiation means to the object;
control means configured to control an irradiation of the laser beam by the irradiation means and an operation of the shutter unit;
a probe configured to receive an acoustic wave generated from the object irradiated with the laser beam; and
construction means configured to generate, using the acoustic wave, characteristic information relating to the object,
wherein the irradiation means is configured to generate the laser beam at a plurality of wavelengths and to irradiate the laser beam with a wavelength selected from among the plurality of wavelengths, and
wherein the control means performs, while the wavelength of the laser beam is switched, a control of closing the shutter and a control of stopping or suppressing the generation of the laser beam by the irradiation means.

US Pat. No. 10,191,014

SYSTEM AND METHOD FOR NONDESTRUCTIVE EVALUATION OF A TEST OBJECT

The Boeing Company, Chic...

1. A system for nondestructive evaluation of a test object, the system comprising:a platform;
an electromagnetic acoustic transducer (EMAT) mounted on the platform and positioned to generate a magnetic field in the test object to create acoustic vibrations that travel along a surface of the test object;
an infrared detector mounted on the platform and positioned to record thermal images of a plurality of test areas on the surface of the test object to detect flaws in the surface of the test object within the plurality of test areas as at least one of the platform and the test object move relative to each other;
a velocity interferometer system for any reflector (VISAR) mounted on the platform and oriented to detect a presence of one of the vibrations in the test object caused by the EMAT in one of the plurality of test areas aligned with the infrared detector; and
a controller connected to the EMAT, the VISAR, and the infrared detector, wherein the controller actuates the EMAT to create the vibrations in the test object the VISCAR, and the infrared detector, wherein the connection synchronizes the creation of the vibrations by the EMAT with the recording of the thermal images of the plurality of test areas by the infrared detector, wherein the controller receives signals from the VISAR indicating the presence of the vibrations in the one of the plurality of test areas aligned with the infrared detector, and the infrared detector is triggered to record each of the thermal images of the one of the plurality of test areas aligned with the infrared detector in response to the VISCAR detecting the one of the vibrations in the one of the plurality of test areas, wherein the controller receives a signal from the infrared detector indicative of the thermal images of the surface of the test object, and the controller records locations of the flaws appearing on the thermal images of the plurality of test areas, wherein the controller receives and records as at least one of the platform and the test object move relative to each other.

US Pat. No. 10,191,009

ELECTROCHEMICAL DETERMINATION OF HEAVY METALS

UNIVERSITY OF LOUISVILLE ...

1. A method of analyzing dissolved metals in a sample solution, the sample solution being contained in a cell having a fixed and known volume, the method comprising:initiating a first reduction reaction in the sample solution which contains two or more dissolved metals by applying a first deposition potential for an interval of time representing a first deposition pulse, wherein the first reduction reaction results in non-exhaustive deposition of one or more of the dissolved metals upon an electrode, wherein the one or more dissolved metals deposited during the first reduction reaction comprise one or more interferents;
initiating a first oxidation reaction by applying a stripping potential for an interval of time, representing a first stripping pulse, that is sufficient to strip the one or more interferents from the electrode that were deposited during the first reduction reaction, and measuring electrical current generated during the first stripping pulse;
after the first oxidation reaction, initiating a second reduction reaction by applying a deposition potential for an interval of time, representing a second deposition pulse, that results in exhaustive deposition of the one or more interferents upon the electrode;
initiating a second oxidation reaction by applying a stripping potential for an interval of time, representing a second stripping pulse, that is sufficient to strip all the one or more interferents from the electrode that were deposited during the second reduction reaction, and measuring electrical current generated during the second stripping pulse;
after the second oxidation reaction, initiating a third reduction reaction in the sample solution by applying a second deposition potential different from the first deposition potential for an interval of time representing a third deposition pulse, wherein the third reduction reaction results in non-exhaustive deposition of the one or more dissolved metals comprising the one or more interferents and at least one analyte upon the electrode;
initiating a third oxidation reaction by applying a stripping potential for an interval of time, representing a third stripping pulse, that is sufficient to strip the one or more interferents and the at least one analyte from the electrode that were deposited during the third reduction reaction, and measuring electrical current generated during the third stripping pulse;
after the third oxidation reaction, initiating a fourth reduction reaction by applying a deposition potential different from the first deposition potential, for an interval of time that results in exhaustive deposition of the one or more interferents and the at least one analyte upon the electrode;
initiating a fourth oxidation reaction by applying a stripping potential for an interval of time, representing a fourth stripping pulse, that is sufficient to strip the one or more interferents and the at least one analyte from the electrode that were deposited during the fourth reduction reaction, and measuring electrical current generated during the fourth stripping pulse; and
calculating a concentration of the at least one analyte in the sample solution based on a quantitative difference between the absolute charge associated with stripping the one or more interferents from the electrode, subtracted from the absolute charge associated with stripping the one or more interferents and the at least one analyte from the electrode.

US Pat. No. 10,191,007

SULFUR OXIDES DETECTION SYSTEM

TOYOTA JIDOSHA KABUSHIKI ...

1. A sulfur oxides detection system comprising:a device part arranged in an exhaust passage of an internal combustion engine and comprising a first electrochemical cell having a first solid electrolyte layer having oxide ion conductivity, a first electrode arranged on one surface of the first solid electrolyte layer so as to be exposed to gas to be measured, and a second electrode arranged on an other surface of the first solid electrolyte layer so as to be exposed to the atmospheric air, and a diffusion regulating layer to regulate diffusion of the gas to be measured;
a power supply to supply voltage across the first electrode and the second electrode;
a detector to detect a first current correlation parameter correlated with a current flowing between the first electrode and the second electrode; and
an electronic control part to control the power supply and to acquire the first current correlation parameter from the detector, wherein
the electronic control part is to control the power supply so that a first voltage which is a decomposition start voltage of water and sulfur oxides or greater is to be applied across the first electrode and the second electrode and to calculate a concentration of sulfur oxides in the gas to be measured based on the first current correlation parameter detected by the detector if the first voltage is applied across the first electrode and the second electrode and
the electronic control part is to judge whether a concentration of water in the gas to be measured is stable and does not calculate the concentration of sulfur oxides in the gas to be measured if the electronic control part judges that the concentration of water in the gas to be measured is not stable.

US Pat. No. 10,191,005

ULTRA-COMPACT, PASSIVE, VARACTOR-BASED WIRELESS SENSOR USING QUANTUM CAPACITANCE EFFECT IN GRAPHENE

Regents of the University...

1. A sensor comprising:a graphene quantum capacitance varactor comprising:
an insulator layer;
a dielectric layer;
a gate electrode between the insulator layer and the dielectric layer;
a graphene layer on the dielectric layer, wherein capacitance of the graphene layer changes in response to a sensed electrical charge collected proximate to the graphene layer upon exposure to a sample, and wherein the graphene layer comprises an exposed surface opposite the dielectric layer; and
at least one contact electrode on the graphene layer and making electrical contact with the graphene layer.

US Pat. No. 10,190,998

METHOD AND DEVICE FOR EVALUATING AND PREDICTING A SHALE OIL ENRICHMENT AREAS OF FAULT LACUSTRINE BASINS

1. A method for evaluating and predicting a shale oil enrichment area of a fault lacustrine basin, wherein the method comprising:Step 1, obtaining analytical test material for a key core well in a fine-grained facies region of the shale oil enrichment area of the fault lacustrine basin, and obtaining key data of the target stratum logging interpretation based on the analytical test material, wherein the key data of the target stratum logging interpretation includes a dolomite-to-formation ratio, dolomite thickness, a lithology profile, a total organic carbon (TOC) average value, and effective source rock thickness;
Step 2, determining a source-reservoir configuration relationship according to a longitudinal superposition relationship of different types of rock in the lithology profile, and establishing a single-well lithofacies mode in conjunction with the dolomite-to-formation ratio and the TOC average value;
Step 3, in the single-well lithofacies mode, forming a dolomite-to-formation ratio contour map, a TOC contour map and a source-reservoir configuration relationship plane distribution map respectively by using the dolomite-to-formation ratio, the TOC average value and the source-reservoir configuration relationship, and superposing the dolomite-to-formation ratio contour map, the TOC contour map and the source-reservoir configuration relationship plane distribution map to form a lithofacies plane distribution map; and
Step 4: on the basis of the lithofacies plane distribution map, superposing a vitrinite reflectance contour map and a dolomite thickness contour map formed through the dolomite thickness to obtain a corresponding evaluation and prediction map of the shale oil enrichment area of the fault lacustrine basin.

US Pat. No. 10,190,988

METHODS OF LASER WELDING DISPOSABLE DIAGNOSTIC TEST ELEMENTS

Roche Diabetes Care, Inc....

17. A disposable diagnostic test element for analyzing a body fluid sample having or suspected of having an analyte of interest, the test element comprising:a stacked or layered arrangement of a base layer, a cover layer, and optionally an intermediate layer, wherein one of the layers is made of an absorbing material configured to absorb radiation from a laser beam and at least one other of the layers is made of a transparent material configured to transmit radiation from the laser beam, wherein the absorbing and transparent materials are fused together in a weld area by laser welding seams, wherein at least one of the layers includes a coating in the form of a chemistry layer adapted to react with the analyte of interest when conducting a test, and wherein the coating covers the weld area and contains one or more components that absorb and/or scatter the radiation from the laser beam at least in part.

US Pat. No. 10,190,987

METHOD FOR INLINE MEASUREMENT ON SIMULATED MOVING BED UNITS OR HYBRID UNITS FOR SEPARATION BY SIMULATED MOVING BED AND CRYSTALLIZATION, AND APPLICATION TO THE CONTROL AND REGULATION OF SAID UNITS

IFP Energies Nouvelles, ...

1. A method for measuring concentrations of species present at at least one point during a separation process operating as a simulated moving bed (SMB) reactor, or a hybrid separation operating as a simulated moving bed (SMB) separation and a further crystallization, said method employing:an immersion probe placed at a point of the reactor or at a point located on a stream entering or leaving said reactor (termed the measurement point),
a thermocouple placed at a distance between an immersed end of the probe and the thermocouple which is at most 30 cm from the measurement point,
a sampling point downstream of the measurement point for analysis by a reference analytical technique during a calibration step,in a manner such as to provide, a Raman spectrum and a temperature simultaneously for each measurement point, said method comprising:a) calibration by inline acquisition of Raman spectra for different mixtures covering a range of concentrations of the species which are to be measured and under temperature and pressure conditions which are representative of an industrial unit and sampling, simultaneously in situ at the sampling point, of moving mixture for analysis by a reference technique, enabling one or more mathematical model(s) to be constructed per constituent as a function of its content;
b) analysis by inline signal processing of the Raman spectrum obtained at each measurement point by means of a chemometric mathematical method employing the or said models constructed during the calibration for each constituent, taking into account the temperature (Tspl) at the measurement point under consideration as well as the range of concentrations Cj of the species present at said measurement point, in order to obtain the concentration Ci of each species present, in which, for each of a) and b), the acquisition of each Raman spectrum is carried out by:
sending a monochromatic signal through a first optical fibre connected to the immersion probe, originating from a laser source with a wavelength of 785 nm plus or minus 1 nm,
retrieving, through a second optical fibre also connected to the immersion probe, a signal corresponding to the Raman effect termed the Raman signal, which is sent to a spectrometer,
retrieving the Raman spectrum of the signal under consideration at the output from the spectrometer.

US Pat. No. 10,190,982

INFORMATION PROCESSING DEVICE, IMAGE ACQUISITION SYSTEM, INFORMATION PROCESSING METHOD, IMAGE INFORMATION ACQUISITION METHOD, AND PROGRAM

SONY CORPORATION, Tokyo ...

6. An image acquisition system, comprising:an imaging unit configured to generate a plurality of pieces of image data for fluorescence generated from a measurement subject by radiation of an excitation light towards the measurement subject and imaging the fluorescence of the measurement subject while a position of the measurement subject is changed in a thickness direction; and
an arithmetic processing unit configured to generate a plurality of fluorescence images corresponding to respective thickness positions by controlling the imaging unit and perform data processing on each of the plurality of pieces of image data generated by the imaging unit,
wherein the imaging unit includes:
a light source optical system configured to guide the excitation light for excitation of the measurement subject with at least two photons to generate fluorescence toward the measurement subject,
an image guide fiber which is formed by bundling a plurality of multimode optical fiber element wires and is configured to transmit the excitation light incident on one end to the measurement subject from the light source optical system and transmit an image of the measurement subject formed on an other end using the fluorescence generated from the measurement subject to the one end, and
an imaging optical system configured to scan the image of the measurement subject transmitted to the one end of the image guide fiber at a scanning pitch that is narrower than a size of a core of each of the plurality of multimode optical fiber element wires to perform imaging such that at least a part of an optical fiber element wire-corresponding area which corresponds to each of the plurality of multimode optical fiber element wires is included in a plurality of images, and generate the plurality of pieces of image data of the measurement subject, and
the arithmetic processing unit includes:
a selection unit configured to select, for each of a plurality of pixels constituting the optical fiber element wire-corresponding area, a pixel value that has maximum luminance among the plurality of pieces of image data as a representative pixel value of a pixel,
a captured image re-constructing unit configured to re-construct a captured image of the measurement subject using the selected representative pixel value and generate a fluorescence image,
a representative luminance value specifying unit configured to, when luminance values constituting the plurality of fluorescence images captured while the position of the measurement subject in the thickness direction is changed are sequentially rearranged from a highest luminance value based on the plurality of fluorescence images corresponding to respective thickness positions, extract a luminance value ranked at a predetermined position from the highest luminance value and set the extracted luminance value as a representative luminance value of the fluorescence image at a thickness position to be noted, and
a surface position specifying unit configured to use the representative luminance value for each of the plurality of fluorescence images and set the thickness position corresponding to the fluorescence image that gives a maximum representative luminance value as a position corresponding to a surface of the measurement subject.

US Pat. No. 10,190,979

METROLOGY IMAGING TARGETS HAVING REFLECTION-SYMMETRIC PAIRS OF REFLECTION-ASYMMETRIC STRUCTURES

KLA-Tencor Corporation, ...

1. A metrology target comprising:at least one reflection-symmetric pair of structures, wherein the at least one reflection-symmetric pair includes a first reflection-asymmetric structure and at least an additional reflection-asymmetric structure, wherein at least one of the first reflection-asymmetric structure or the at least an additional reflection-asymmetric structure includes a series of periodically spaced target elements, wherein at least some of the periodically spaced target elements are reflection-asymmetric.

US Pat. No. 10,190,975

LEAKED GAS DETECTION DEVICE AND LEAKED GAS DETECTION METHOD

KONICA MINOLTA, INC., To...

1. A leaked gas detection device comprising:an infrared image acquisitor that acquires an infrared image of a target area;
a hardware processor that extracts a gas cloud image area of a gas cloud formed with a leaked gas on the basis of the infrared image of the target area acquired in the infrared image acquisitor; and
a gas cloud temperature acquisitor that acquires a gas temperature of the gas cloud,
the hardware processor obtaining a concentration-thickness product of the gas cloud, and obtaining a reliability degree that is an index representing the degree of reliability with respect to the concentration-thickness product of the gas cloud obtained in the hardware processor on the basis of a background temperature in the gas cloud image area extracted in the hardware processor and the gas temperature acquired in the gas cloud temperature acquisitor.

US Pat. No. 10,190,974

OPTICAL GAS SENSOR COMPRISING AN LED EMITTER FOR THE EMISSION OF LIGHT OF A NARROW BANDWIDTH

1. An optical gas sensor for quantitatively measuring the concentration of one or more gases, the optical gas sensor comprising:a radiation source for emitting light waves;
a cuvette for holding a gas to be measured; and
a detector for measuring light intensities, wherein:
the radiation source comprises a first emitter and a second emitter, the first emitter being configured to emit light waves of a first wavelength and the second emitter is configured to emit light waves of a second wavelength, the second wavelength being different from the first wavelength, and the detector comprising at least one optical filter, the radiation source being configured to emit the light waves of the at least one first wavelength and of the second wavelength simultaneously as well as separately from one another;
the cuvette comprising a mirror arrangement with a plane mirror and a concave mirror arranged opposite the plane mirror, wherein an optical axis of the concave mirror is arranged essentially at right angles to the plane mirror, wherein the plane mirror has a first aperture and a second aperture, wherein the first aperture has at least two emitters;
the emitter is configured to emit a spectrum, the full width at half maximum of which is a maximum 50% of the effective wavelength; and
the detector being configured to receive the first and second wavelengths and to separately quantitatively detect an intensity of the emitted light waves of the first wavelength and of the second wavelength.

US Pat. No. 10,190,972

DEVICE FOR MANAGING PULSES IN PUMP-PROBE SPECTROSCOPY

ECOLE POLYTECHNIQUE, Pal...

1. A device for managing light pulses for measuring a reaction of a sample exposed to a first light pulse called a “pump” pulse, the measurement being performed by analysis of a signal emitted by the sample subjected to a second light pulse, called a “probe” pulse, temporally shifted with respect to the “pump” pulse by a determined time interval, the device comprising:two ultrashort pulsed oscillators of different pulse frequencies, stable over a determined period ?t, said oscillators being characterized by their relative phase which allows to foresee the delay between all the pulses produced by the two oscillators,
two optical detectors beamed to detecting the pulses of two light beams emitted by two ultrashort pulsed oscillators respectively, the first beam being called the “pump” beam and the second beam being called the “probe” beam, in the direction of said sample; the detectors being connected to
a computer configured to accumulate during said determined period ?t measurements of the relative phase and determine, based on these measurements, the value of the time delays between subsequent pump and probe pulses, with a precision improving with the square root of the number of measurements, hence in the picosecond or sub-picosecond domain,
an acquisition system connected to the computer and configured to receive from the computer the time delay values and to acquire signals emitted by the sample in order to analyze its reaction to the pairs of pulses for determined values of time delay.

US Pat. No. 10,190,968

CORROSION RATE MEASUREMENT WITH MULTIVARIABLE SENSOR

ROSEMOUNT INC., Shakopee...

1. A corrosion measurement system, comprising:a corrosion sensor having a corrosion sensor output related to corrosion due to exposure to a process fluid;
a process variable sensor having a process variable output related to a process variable of the process fluid wherein the process variable changes a rate at which components exposed to the process fluid corrode; and
measurement circuitry coupled to the corrosion sensor and the process variable sensor having an output related to corrosion of components exposed to the process fluid based upon the corrosion sensor output and the process variable output wherein the measurement circuitry identifies periods of reduced corrosion rate and uses reduced power during the periods of reduced corrosion rate.

US Pat. No. 10,190,966

METAL-PIPE USE SUPPORT SYSTEM

1. A metal-pipe use support system comprising:a reading unit configured to read identification data for a plurality of metal pipes,
a metal pipe information reception unit configured to receive, from the reading unit, the identification data for each of the plurality of metal pipes;
a use condition reception unit configured to receive an environment value indicative of an environment at each of positions in a space in which the metal pipes are to be placed as use condition data about a condition under which a metal pipe is to be used;
a pipe-specific data acquisition unit configured to access a data recording unit storing pipe-specific data indicative of a property of each metal pipe and corresponding identification data in an associated manner and to acquire the pipe-specific data associated with the identification data received by the metal pipe information reception unit, the pipe-specific data including a performance value indicative of a performance of each of the metal pipes;
a pipe determination unit configured to assign, by a processor, to each of the positions in the space in which the metal pipes are to be placed, a metal pipe having a performance value suitable for the environment value of that position based on a comparison between the environment value for each of the positions in the space in which the metal pipes are to be placed indicated by the use-condition data and the performance value indicative of the performance of each of the metal pipes included in the pipe-specific data to determine an arrangement of the plurality of metal pipes; and
an output unit configured to output information relating to the metal pipe determined by the pipe determination unit.

US Pat. No. 10,190,964

GENERATING A FLUID STREAM IN A MICROFLUIDIC DEVICE

XY, LLC, Navasota, TX (U...

1. A method of operating a flow cytometer, comprising:providing a variable volume container having a flexible wall;
establishing an amount of fluid in said variable volume container;
exerting an amount of pressure with an amount of a gas on an exterior surface of said flexible wall of said variable volume container, wherein said flexible wall comprises at least two flexible layers, a first flexible layer compatible with said amount of gas and a second flexible layer compatible with said amount of fluid;
collecting said amount of gas between said first flexible layer and said second flexible layer;
providing a conduit between said variable volume container and a flow path of said flow cytometer;
generating a fluid stream of said amount of fluid in said flow path of said flow cytometer by exerting said amount of pressure with said amount of gas on said exterior surface of said flexible wall of said variable volume container;
generating a fluid pressure of said fluid stream of said amount of fluid inside of said flow cytometer within the range of about 25 psi and about 50 psi;
regulating said fluid stream within said flow path of said flow cytometer having said fluid pressure within the range of about 25 psi and about 50 psi for analysis of a plurality of particles entrained within said fluid stream;
intermittently entraining one of said plurality of particles in said fluid stream in said flow path of said flow cytometer; and
analyzing said plurality of particles entrained within said fluid stream.

US Pat. No. 10,190,962

FLOW CYTOMETRY SYSTEMS AND METHODS FOR BLOCKING DIFFRACTION PATTERNS

Abbott Laboratories, Abb...

1. A flow cytometer system for blocking a diffraction pattern, the system comprising:an intermediate angle scatter (IAS) light detector; and
a mask disposed across a portion of the IAS light detector and covering at least a central portion of the IAS light detector so as to block a diffraction pattern created by:
(1) a flat beam profile irradiating the liquid sample while allowing all IAS signals to be detected by the IAS light detector; or
(2) a mismatched index of refraction between a sheath fluid and a liquid sample when the liquid sample is irradiated while allowing all IAS signals emitted from the liquid sample to be detected by the IAS light detector.

US Pat. No. 10,190,961

SAMPLE ANALYZER AND SAMPLE ANALYZING METHOD THEREOF

Shenzhen Mindray Bio-Medi...

1. A sample analyzer, comprising:a sample collection device for collecting a sample quantitatively, wherein the sample comprises cell particles;
a reagent supplement device for providing a reagent, wherein the reagent is able to react with the cell particles;
a sample reaction device for receiving the sample from the sample collection device and the reagent from the reagent supplement device, wherein the reagent reacts with the cell particles to generate an analyte;
an analyte delivery device for delivering the analyte for optical measurement; and
an optical measurement device for measuring a light signal generated from the analyte to generate light signal information, wherein the optical measurement device comprises:
a fluid chamber comprising an illumination zone, wherein the analyte from the analyte delivery device flows through the illumination zone to form a sample stream;
a light source for illuminating the illumination zone to generate the light signal from the sample stream; and
a light detector for detecting the light signal and transforming the light signal into the light signal information, wherein the light detector comprises at least one silicon photomultiplier, wherein a light sensing area of the silicon photomultiplier is smaller than a threshold value, a distortion of a pulse amplitude of an electrical signal is triggered when the light sensing area of the silicon photomultiplier exceeds the threshold value, and the electrical signal is generated according to an amount of a dark pulse count overlapping on a single one of the cell particles.

US Pat. No. 10,190,960

MICRO-LENS SYSTEMS FOR PARTICLE PROCESSING SYSTEMS

1. A particle processing system comprising:a detection region including a micro-lens array; and
a particle processing region configured to be removably and optically coupled to the detection region, wherein the particle processing region includes at least one microfluidic channel;
wherein the micro-lens array includes at least one micro-lens system having a plurality of free-space optical elements disposed along a central axis, the micro-lens system positioned relative to the at least one microfluidic channel so as to collect light from an angle of less than 180 degrees from the at least one microfluidic channel, and
wherein at least one optical element collects and collimates a fluorescence signal.

US Pat. No. 10,190,959

SORTING FLOW CYTOMETER

Beckman Coulter, Inc., B...

1. A sorting flow cytometer comprising:a fluid nozzle configured to receive a fluid input and generate a fluid stream along a fluid path;
a laser configured to generate a laser beam and positioned to direct the laser beam at the fluid stream;
acquisition electronics including a sensor analyzer arranged and configured to detect light from the laser after the laser beam has intersected the fluid stream;
a computing device in data communication with the acquisition electronics;
a computer readable data storage device storing data instructions that, when executed by the computing device, cause the computing device to perform the following steps:
identify segments of the fluid stream, including a first segment and a second segment that are directly adjacent to each other;
generate preliminary sort decisions that assign preliminary charges to segments of the fluid stream including a first preliminary sort decision that assigns a first preliminary charge to the first segment and a second preliminary sort decision that assigns a second preliminary charge to the second segment;
evaluate the first preliminary sort decision and the second preliminary sort decision;
generate final sort decisions that include a modification to the first preliminary sort decision or the second preliminary sort decision to assign a neutral charge for at least one of the first segment or the second segment; and
generate a sort control signal according to the final sort decisions;
sort control electronics in data communication with the computing device, configured to receive the sort control signal from the computing device and selectively apply charges to the segments of the fluid stream prior to a drop break off point; and
deflection plates arranged adjacent to the fluid path to sort drops formed from the segments of the fluid stream into a plurality of containers.

US Pat. No. 10,190,954

PRE-STRAINED COMPOSITE TEST COUPONS

THE BOEING COMPANY, Chic...

1. A method comprising:inserting a test coupon of a composite material having a plurality of layers into a testing device that has a first element to secure the test coupon and a second element to secure the test coupon, wherein the plurality of layers of the test coupon are arranged in a cross-ply layup including:
inner ply layers having first fibers and a first matrix material associated with the first fibers, the first fibers oriented in a first direction; and
outer ply layers having second fibers and a second matrix material associated with the second fibers, the outer ply layers including outermost ply layers and the second fibers oriented in a second direction that is different than the first direction;
performing a first loading operation on the test coupon, wherein the first loading operation includes applying a first tensile load oriented in the first direction, the first tensile load corresponding to a threshold load that is less than a failure load of the first fibers;
removing the first tensile load after the first tensile load causes cracking along the second direction and between the second fibers of each of the outermost ply layers;
after removing the first tensile load, performing a second loading operation on the test coupon, wherein the second loading operation includes increasing tensile loading of the test coupon to the failure load of the first fibers;
receiving, from the testing device, strain values of the test coupon during tensile loading of the test coupon; and
determining one or more modulus values associated with a first contribution corresponding to the inner ply layers based on the strain values and based on a nominal thickness of a ply area associated with the inner ply layers, the first contribution independent of a second contribution of the outer ply layers.

US Pat. No. 10,190,953

TOMOGRAPHY SAMPLE PREPARATION SYSTEMS AND METHODS WITH IMPROVED SPEED, AUTOMATION, AND RELIABILITY

1. A method for creating a tomography sample from a sample substrate, comprising:(a) identifying a target area and underlying target volume of a substrate containing a region of interest;
(b) creating a mill pattern based on the target area and a desired sample pillar height and width;
(c) milling a crater asymmetrically positioned around the identified target area to form a sample pillar containing a target volume using a focused ion beam (FIB), (i) the crater large enough to allow a single FIB cut at a desired angle from vertical with respect to the sample pillar orientation to pass within the crater and cut the sample pillar free from the substrate, (ii) the crater having a first depth on a cutting side of the sample pillar of at least the desired sample pillar height and a second, larger, depth opposite the cutting side, the second depth large enough to accommodate the opposite end of the single FIB cut to leave the sample pillar detached after the single FIB cut, (iii) the crater having a first gap between the sample pillar and a crater edge on the cutting side and a second gap, substantially smaller than the first gap, opposite the cutting side;
(d) attaching a probe tip of a probe to the sample pillar;
(e) cutting the sample pillar free with the single FIB cut at the desired angle; and
(f) using the probe to move the sample pillar to a sample holder.

US Pat. No. 10,190,950

SEMI-AUTOMATED SAMPLING SYSTEM FOR ASEPTIC SAMPLING

GENERAL ELECTRIC COMPANY,...

1. A semi-automated sampling assembly configured for aseptic sampling at one or more instances from a sample source having a biological inoculum, the semi-automated sampling assembly comprising:a sampling conduit comprising a first port and a second port, wherein the first port of the sampling conduit is configured to be coupled to the sample source, wherein the second port of the sampling conduit is configured to be coupled to a purging fluid source;
a recovery conduit comprising a first port and a second port, wherein the first port of the recovery conduit is configured to be coupled to the sample source, wherein the second port of the recovery conduit is coupled to the sampling conduit at a junction;
a sampling loop comprising a portion of a tubing of the semi-automated sampling assembly disposed between the first port of the sampling conduit, the junction, and the first port of the recovery conduit, and wherein the biological inoculum is circulated in the sampling loop and returned to the sample source via the recovery conduit prior to a sampling instance;
one or more sampling kits coupled to the sampling conduit; and
a motorized pump coupled to the sampling conduit, wherein the motorized pump is configured to draw the purging fluid source, or a sample, or both, in the sampling conduit.

US Pat. No. 10,190,949

METHOD AND APPARATUS FOR A CONE PENETRATION TEST WITH WHIPSTOCK-ENABLED SOIL SAMPLING

1. An apparatus for taking soil samples from subsurface soil strata, comprising:an elongated tubular whipstock cell having a proximal end and a distal end;
a through-opening along a portion of the whipstock cell comprising a pre-formed window;
a whipstock residing within the whipstock cell, the whipstock having a face angled towards the pre-formed window;
at least one push rod connected to the proximal end of the whipstock cell, the push rod representing a tubular body;
an elongated sampling rod dimensioned to be slidably moved through an inner diameter of the at least one push rod en route to the whipstock cell;
a mechanical soil sampler configured to extend through the pre-formed window; and
a bent sub having a proximal end and a distal end, wherein the proximal end is connected to a distal end of the sampling rod, and the distal end is connected to the soil sampler, and wherein the bent sub is configured to deflect off of the whipstock face when urged through the pre-formed window.

US Pat. No. 10,190,947

VISUAL CREEP INSPECTION OF ROTATING COMPONENTS

GENERAL ELECTRIC COMPANY,...

1. A system comprising:a component with an external surface and an axis of rotation, wherein the external surface has a circumference and a plurality of three dimensional reference marks forming a reference pattern along the circumference;
an optical data capture device that transmits a data signal based on the plurality of three dimensional reference marks;
a rotational index encoder that generates position data related to the plurality of three dimensional reference marks as the component rotates around the axis of rotation; and
a data analysis system that processes the data signal transmitted from the optical data capture device and the position data generated by the rotational index encoder to calculate a deviation in spacing of the reference pattern along the circumference and determine a strain measurement.

US Pat. No. 10,190,942

DIAGNOSIS OF DRIVE SHAFT DISC COUPLINGS

SIKORSKY AIRCRAFT CORPORA...

1. A method applied to one or more components of a drive shaft of an aircraft, the method comprising:obtaining data based on samples of a vibration signal;
processing, by at least one processor, the data to obtain a qualitative and quantitative assessment of a health of the one or more components based on an application of the data to at least one model, wherein processing the data further comprises segmenting the vibration signal into a plurality of segments representative of a revolution of the drive shaft based on a nominal speed of the drive shaft as part of processing the data, resampling the vibration signal segments from constant time based sampling to constant angular based sampling, and averaging the resampled segments as part of processing the data; and
outputting the assessment.

US Pat. No. 10,190,941

SILICON OPTICAL CIRCUIT FOR FLAW DETECTION IN AN OPTICAL CIRCUIT ELEMENT

NIPPON TELEGRAPH AND TELE...

1. A silicon optical circuit having a function of detecting a flaw occurred on an optical circuit element formed on a substrate, the optical circuit comprising:an optical waveguide arranged along at least a part of a contour of a target circuit having a predetermined function by the optical circuit element and arranged proximate at a distance that does not cause optical coupling with the target circuit; and
optical path conversion means disposed at both ends of the optical waveguide.

US Pat. No. 10,190,939

METHOD AND APPARATUS FOR PERFORMING INTERRELATION PROFILE ANALYSIS

AFL Telecommunications LL...

1. A method of analyzing polarization-maintaining (PM) optical fibers, comprising:illuminating a side of each of a first and second PM optical fiber using light having a focus point intersecting each of the first and second PM optical fibers;
physically rotating each of the first and second PM optical fiber and measuring light intensity of the light transmitted through each of the first and second PM optical fiber to obtain an image profile of each of the first and second PM optical fiber;
mathematically shifting the image profile of each of the first and second PM optical fiber at incremental rotation angles;
expanding the image profile of each of the first and second PM optical fiber at each rotational angle into a Fourier series profile, using the following equations to expand the image profile of each of the first and second PM optical fiber at each rotational angle into the Fourier series profile:

determining points of symmetry of each of the first and second PM optical fiber based on the Fourier series profiles; and
aligning the first and second PM optical fibers based on the points of symmetry.

US Pat. No. 10,190,938

SEMI-FLEXIBLE PROOF-MASS

MURATA MANUFACTURING CO.,...

1. A microelectromechanical device, comprising:a substantially planar semi-flexible proof-mass comprising at least one primary part and at least one secondary part, and at least one stiff spring coupling the at least one primary part to the at least one secondary part of the semi-flexible proof-mass, the at least one stiff spring substantially causing the at least one primary part and the at least one secondary part to move as a single, rigid entity when the device is in a normal operation range;
at least one main spring coupled to the at least one secondary part, the main spring coupling the semi-flexible proof-mass to a fixed suspension structure; and
at least one first stopper structure configured to stop the at least one primary part,
wherein the semi-flexible proof-mass is configured to deform through deflection of the at least one stiff spring, when the device is subjected to a shock that impacts the device with a force that is beyond the normal operation range of the device, the shock causing a motion of the semi-flexible proof-mass at least in a direction along an axis of movement, and
wherein the at least one stiff spring further causes a restoring force causing the at least one secondary part of the semi-flexible proof-mass to be driven into a restoring motion in a direction opposite to the motion along the axis of movement caused by the shock, wherein momentum of the at least one secondary part in the restoring motion further causes the at least one primary part to dislodge from the at least one first stopper structure.

US Pat. No. 10,190,936

MOBILE BRIDGE APPARATUS

BAE Systems plc, London ...

1. A mobile bridge apparatus, comprising:a plurality of mobile bridge modules each configured to form a portion of a bridge and to be in connection with one another; and
a plurality of sensors, each of the sensors being located at different locations on at least one of the mobile bridge modules and configured to sense a deformation of each respective mobile bridge module.

US Pat. No. 10,190,934

SYSTEMS AND METHODS FOR ENGINE-OFF NATURAL VACUUM LEAK TESTING WITH FUEL ENABLEMENT COMPENSATION

Ford Global Technologies,...

1. A method for an evaporative emissions system, comprising:adjusting a threshold for an evaporative emissions leak test entry condition that comprises an engine heat rejection inference for an engine run time duration, based on at least a fuel level;
responsive to the engine heat rejection inference being greater than the adjusted threshold, adjusting one or more pressure thresholds for an evaporative emissions leak test based on the engine heat rejection inference; and
indicating degradation of the evaporative emissions system based on the adjusted one or more pressure thresholds.

US Pat. No. 10,190,929

PRESSURE SENSOR DEVICE AND PRESSURE SENSOR DEVICE MANUFACTURING METHOD

FUJI ELECTRIC CO., LTD., ...

1. A pressure sensor cell, comprising:a semiconductor pressure sensor chip having a pressure receiving portion and for converting pressure into an electric signal;
a base member having a through hole that penetrates a first surface of the base member and a second surface of the base member, the semiconductor pressure sensor chip being joined to the second surface so that the pressure receiving portion is aligned with the through hole;
a metal material;
a pressure introduction unit formed of metal and having a through hole that penetrates a first surface of the pressure introduction unit and a second surface of the pressure introduction unit, the second surface of the pressure introduction unit being joined across the metal material to the first surface of the base member so that the through hole of the pressure introduction unit connects with the through hole of the base member, the pressure introduction unit having
a stepped portion protruding outward in an end portion of the pressure introduction unit on an opened end side in which the through hole of the pressure introduction unit is opened, and
a protruding portion protruding from the stepped portion to a base member side, a wall thickness of the protruding portion being smaller than a height of the stepped portion; and
a resin case having a signal terminal that extracts the electric signal from the semiconductor pressure sensor chip, the protruding portion being integrated with the resin case so that a surface of the stepped portion on a side, that is opposite to the opened end side, is in contact with the resin case;
wherein the through hole of the pressure introduction unit is wider than the through hole of the base member.

US Pat. No. 10,190,926

FIBER BRAGG GATING (FBG) SENSOR

AGENCY FOR SCIENCE, TECHN...

1. A fiber Bragg grating (FBG) sensor structure comprising:a plurality of optical fiber portions, each one of the plurality of optical fiber portions having at least one FBG formed therein and a loose tube, wherein the at least one FBG is disposed within the loose tube, and wherein the loose tube is spaced approximately 2 cm apart from each of one or two neighboring loose tubes; and
a sleeve structure capable of transferring vibrations, strain, or the vibrations and strain along a length thereof, wherein each of the plurality of optical fiber portions is coupled to the sleeve structure such that the wavelength of the each of the plurality of optical fiber portions is variable under the transferred vibrations, strain, or the vibrations and strain,
and
wherein the plurality of optical fiber portions are split from one another by one or more single mode fibers.

US Pat. No. 10,190,925

LOW COST OVERMOLDED LEADFRAME FORCE SENSOR WITH MULTIPLE MOUNTING POSITIONS

Honeywell International I...

1. A force sensor comprising:a leadframe comprising a plurality of electrically conductive leads;
a sense die coupled to the leadframe, wherein the sense die is electrically coupled to the plurality of leads;
an encapsulant disposed over at least a portion of the leadframe and the sense die, wherein the plurality of leads extends from the encapsulant;
wherein the encapsulant is in contact with the leadframe and the sense die;
a first actuation element disposed in contact with a first side of the sense die, wherein the first actuation element comprises a mechanical coupling element configured to mechanically couple an external force with the sense die; and
a second actuation element disposed in contact with a second side of the sense die, wherein the second side is opposite to the first side, and wherein the second actuation element comprises a gel.

US Pat. No. 10,190,924

PRESSURE-SENSING DEVICE AND PRESSURE-SENSING TOUCH PANEL

MURATA MANUFACTURING CO.,...

1. A pressure-sensing device comprisinga pressed component that has a contact surface to which pressure is applied by contact from a presser;
a polymeric piezoelectric element that is disposed at an opposite side from the contact surface of the pressed component and that has a piezoelectric constant d14 of 1 pC/N or more, as measured at 25° C. using a stress-charge method;
a curable resin layer that comprises at least one selected from the group consisting of cold-setting resins, thermosetting resins and actinic radiation-curable resins, and that is in contact with at least part of a surface of a side facing the pressed component of the polymeric piezoelectric element or at least part of a surface of an opposite side facing the pressed component of the polymeric piezoelectric element; and
an electrode that is in contact with at least part of a surface of the polymeric piezoelectric element or of a surface of the curable resin layer.

US Pat. No. 10,190,923

STRAIN SENSING ELEMENT, PRESSURE SENSOR, MICROPHONE, BLOOD PRESSURE SENSOR, AND TOUCH PANEL

Kabushiki Kaisha Toshiba,...

1. A strain sensing element provided on a deformable substrate, comprising:a first magnetic layer;
a second magnetic layer including Fe1-yBy (0 an intermediate layer provided between the first magnetic layer and the second magnetic layer,
wherein a first part of the Fe1-yBy (0

US Pat. No. 10,190,922

METHOD AND APPARATUS FOR CALIBRATING A SENSOR

INTEL CORPORATION, Santa...

1. An apparatus comprising:a first transistor with a gate terminal coupled to a first node and a current source;
a second transistor with a gate terminal coupled to a second node and ground;
a first resistor coupled to the first and second nodes;
a second resistor coupled to the first node and a reference voltage supply;
a diode coupled to the second node;
a third resistor coupled to the second node and the voltage reference supply; and
a switch coupled to the third resistor and the voltage reference supply, and wherein a temperature is sensed by subtracting a first current from the first resistor with a second current from the third resistor at the first node when the switch is on.

US Pat. No. 10,190,921

INTERNAL TEMPERATURE MEASUREMENT DEVICE

OMRON Corporation, Kyoto...

1. An internal temperature measurement device, comprising:a base portion, one surface of which is to be brought into contact with a surface of a measuring object when an internal temperature of the measuring object is measured;
a MEMS chip arranged on another surface of the base portion, and including: a substrate portion including a first thin film portion and a second thin film portion that are hollow on the base portion side; a first thermopile configured to measure a first temperature difference between a predetermined region and another region of the first thin film portion; and a second thermopile configured to measure a second temperature difference between a predetermined region and another region of the second thin film portion; and
a calculation unit configured to calculate an internal temperature of the measuring object by using the first temperature difference measured by the first thermopile and the second temperature difference measured by the second thermopile,
wherein the MEMS chip is configured such that a first heat flux which passes through the predetermined region of the first thin film portion from the measuring object in contact with the one surface of the base portion, and which is determined on the basis of the first temperature difference, and a second heat flux which passes through the predetermined region of the second thin film portion from the measuring object in contact with the one surface of the base portion, and which is determined on the basis of the second temperature difference, are different from each other, and in order to reduce the first heat flux, a thin film portion that is hollow on the base portion side is provided on at least one of both sides of the first thin film portion of the substrate portion in a direction where the first thin film portion and the second thin film portion are arranged.

US Pat. No. 10,190,919

DIFFERENTIAL THERMISTOR CIRCUIT

Fairchild Semiconductor C...

1. A circuit comprising:a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance;
a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance;
a temperature information circuit configured to:
receive a first voltage from the first terminal of the temperature-sensitive resistance;
receive a second voltage from the second terminal of the temperature-sensitive resistance; and
provide temperature information based on the first voltage and the second voltage, the temperature information circuit including:
a first comparison circuit configured to determine a difference between the first voltage and the second voltage; and
a second comparison circuit configured to compare an output of the first comparison circuit to a reference.

US Pat. No. 10,190,918

CIRCUIT APPARATUS, ELECTRONIC APPARATUS, AND MOVING OBJECT

Seiko Epson Corporation, ...

1. A circuit apparatus comprising:a voltage output circuit that outputs a first output voltage when a first current of first temperature characteristics flows in a resistance element, and a second output voltage when a second current of second temperature characteristics different from the first temperature characteristics flows in the resistance element, wherein the voltage output circuit includes
a first transistor configured to selectively provide the first current to the resistance element in a first period such that the voltage output circuit outputs the first output voltage in the first period, and
a second transistor configured to selectively provide the second current to the resistance element in a second period such that the voltage output circuit outputs the second output voltage in the second period;
an A/D conversion circuit that outputs a first digital value by performing A/D conversion on the first output voltage, and outputs a second digital value by performing A/D conversion on the second output voltage; and
a processing unit that obtains temperature data by digital calculation processing based on the first digital value and the second digital value.

US Pat. No. 10,190,917

SURFACE TEMPERATURE PROBE

ABB SCHWEIZ AG, Baden (C...

1. A surface temperature probe assembly, comprising:a surface temperature probe having a first geometric contact surface configured to determine a temperature in a vessel, the vessel having a second geometric contact surface, the first geometric contact surface contacting the second geometric contact surface in a punctiform and/or linear manner and being variably spaced apart from the second contact surface at least in part; and
a metal adapter, provided between the first geometric contact surface and the second geometric contact surface,
wherein a side of the metal adapter facing the vessel has a polygonal surface structure, and
wherein a side of the metal adapter facing the surface temperature probe includes a sack-shaped recess.

US Pat. No. 10,190,914

MOTION DETECTION FOR A/V RECORDING AND COMMUNICATION DEVICES

Amazon Technologies, Inc....

1. A method for an audio/video (A/V) recording and communication device, including a motion sensor, the method comprising:gathering, by the motion sensor, information within a field of view of the A/V recording and communication device and generating an output signal;
sampling the output signal from the motion sensor during a first sampling interval;
calculating a first magnitude of the output signal during the first sampling interval;
sampling the output signal from the motion sensor during a second sampling interval;
calculating a second magnitude of the output signal during the second sampling interval;
calculating a difference between the first magnitude and the second magnitude;
comparing the difference between the first magnitude and the second magnitude to a threshold value; and
upon determining that the difference between the first magnitude and the second magnitude is greater than the threshold value, refraining from generating an alert signal.