US Pat. No. 10,796,824

OPTICAL SIGNAL TRANSFERRING APPARATUS, ELECTRONIC APPARATUS, SOURCE DEVICE, AND METHODS OF OPERATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. An optical signal transferring apparatus comprising:a signal transfer unit comprising one or more optical signal lines and one or more power lines;
a first connector which is arranged on a first end of the signal transfer unit, configured to convert an optical signal to and from an electrical signal, and connectable to an electronic apparatus to transfer the electrical signal to and from the electronic apparatus; and
a second connector which is arranged on a second end of the signal transfer unit, configured to convert an optical signal to and from an electrical signal, and connectable to a source device to transfer the electrical signal to and from the source device,
wherein,
in response to a power-on input to turn on the electronic apparatus, at least one optical signal line of the one or more optical signal lines is configured to transfer an optical signal from the first connector connected to an electronic apparatus to the second connector connected to a source device, and
in response to a detection of the transferred optical signal by the source device, at least one power line of the one or more power lines is configured to supply power from the second connector connected to the source device to the first connector connected to the electronic apparatus, and at least one optical signal line of the one or more optical signal lines is configured to transfer data from the second connector connected to the source device to the first connector connected to the electronic apparatus.

US Pat. No. 10,796,823

COMMUNICATIONS CABLE WITH IMPROVED ISOLATION BETWEEN WIRE-PAIRS AND METAL FOIL TAPE

Panduit Corp., Tinley Pa...

1. A communications cable, comprising:a jacket;
a cable core comprising a plurality of twisted pairs of conductors;
a metal foil tape disposed between the cable core and the jacket, the metal foil tape comprising:
a discontinuous metal layer;
a polymer layer bonded to the metal layer; and
a plurality of solid dimples formed by deforming portions of the metal foil tape, the solid dimples forming air gaps between the polymer layer and the cable core, the air gaps lowering an overall dielectric constant between the metal layer and the cable core.

US Pat. No. 10,796,822

METHOD FOR MAKING A GAS BLOCKING CABLE

1. A method for making a gas blocking cable comprising the steps of:a) cabling a plurality of conductors so that a first set of interstitial areas are formed there between;
b) applying a conductor filling material to the first set of interstitial areas between the plurality of conductors so that the first set of interstitial areas are filled, where the conductor filling material is inert, non-flammable and able to withstand a temperature up to at least approximately 200° C.;
c) applying an insulation material so as to circumferentially surround the plurality of conductors and conductor filling material so that a first wire is formed;
d) repeating steps a) through c) so that a second wire is formed;
e) cabling the first and second wires so that a second set of interstitial areas are formed there between;
f) pumping a first part of a wire filling material and a second part of a wire filling material;
g) mixing the first part of the wire filling material and the second part of the wire filling material together in a mixing nozzle, thereby creating the wire filling material;
h) applying, with an application device, the wire filling material to the second set of interstitial areas between the first and second wires so that the second set of interstitial areas are filled by passing the first and second wires through a pressure chamber with the wire filling material to apply the wire filling material to the first and second wires, where the wire filling material is inert, non-flammable and able to withstand a temperature up to at least approximately 200° C.;
i) applying a shield material so as to circumferentially surround the first and second wires and the wire filling material;
j) applying a jacket material over the applied shield material, wherein the jacket material is extruded and circumferentially surrounds the shield material with a jacket filling material positioned within a third set of interstitial areas between the shield material and the jacket material, where the jacket filling material is inert, non-flammable and able to withstand a temperature up to at least approximately 200° C.; and
k) braiding a fiberglass material over the applied jacket material,
wherein the gas blocking cable blocks a passage of a high pressure gas or a high pressure fluid through the first set of interstitial areas, the second set of interstitial areas, and the third set of interstitial areas to prevent the passage of the high pressure gas or the high pressure fluid.

US Pat. No. 10,796,821

METHOD OF MANUFACTURING POLYGONAL SHAPED AL ALLOY WIRE

1. A method for manufacturing a high conductive Al alloy wire without conducting an annealing process, the method comprising:providing an Al alloy rod comprising 0.01 parts by weight to 0.08 parts by weight of Fe, Fe:Si=2 to 3:1 of Si and the balance Al and inevitable impurities, based on 100 parts by weight of an entire A1350 alloy;
conform-extruding the Al alloy rod by passing through a dies of a conform extruder having a polygonal shaped structure to form a polygonal shaped Al alloy wire;
cooling the extruded Al alloy wire to room temperature; and
winding the cooled Al alloy wire using a winder.

US Pat. No. 10,796,820

MAGNET WIRE WITH CORONA RESISTANT POLYIMIDE INSULATION

Essex Group LLC, Atlanta...

1. A magnet wire comprising:a conductor; and
at least one layer of polymeric enamel insulation formed around the conductor, the polymeric enamel insulation comprising a filler dispersed in polyimide and an additive comprising an amine moiety reacted with a formaldehyde material,
wherein the filler comprises between 20 percent and 80 percent by weight of silica oxide and between 20 and 80 percent by weight of titanium oxide,
wherein the polymeric enamel insulation has a thermal index of 260° C. or greater.

US Pat. No. 10,796,819

WIRE HARNESS

YAZAKI CORPORATION, Toky...

1. A wire harness comprising:a first round electric wire; and
a flat electric wire,
wherein the first round electric wire includes a round conductor made of a predetermined metal and having a round cross-sectional shape and a first coating portion,
wherein the flat electric wire includes a first flat conductor having a flat cross-sectional shape and a second coating portion,
wherein the first round electric wire and the flat electric wire are arranged in parallel,
wherein the round conductor has a diameter equal to or less than a predetermined reference value, and
wherein the first flat conductor has a thickness equal to or less than the reference value and a width which ensures the flat cross-sectional area of the first flat conductor is greater than an area of a circle having a diameter equal to the reference value.

US Pat. No. 10,796,818

HEATING ELEMENT

LG CHEM., LTD., Seoul (K...

1. A heating element comprising:an adhesive film; and
a conductive heating pattern provided on the adhesive film,
wherein the adhesive film has an adhesive strength decrement of 30% or greater by an external stimulus based on adhesive strength before the external stimulus,
wherein the adhesive film is formed from a composition comprising 100 parts by weight of the adhesive resin, 0.1 to 20 parts by weight of an initiator, 0.1 to 40 parts by weight of a crosslinking agent, and 5 to 200 parts by weight of an ultraviolet curable compound,
wherein the ultraviolet curable compound is included in a side chain of the adhesive resin by substituting 5 to 90 mol % of a crosslinking functional group of the adhesive resin,
wherein the adhesive resin is a (meth)acrylate-based resin with an average molecular weight of 400,000 g/mol to 2,000,000 g/mol, and
wherein the adhesive film has a thickness of greater than or equal to 5 ?m and less than 100 ?m.

US Pat. No. 10,796,817

ALUMINUM PATTERN AND METHOD FOR MANUFACTURING SAME

LG CHEM, LTD., Seoul (KR...

1. A method for manufacturing a conductive film for transparent electrodes, the conductive film comprising an aluminum pattern, wherein the method comprises, in this order:forming the aluminum pattern on a substrate;
forming a resist layer on the aluminum pattern; and
forming aluminum oxide on at least a portion of side surfaces of the aluminum pattern not covered by the resist layer by immersing the aluminum pattern in water,
wherein a pitch of the aluminum pattern before being immersed in water is from 50 ?m to 500 ?m,
wherein the aluminum pattern has an initial line width of 10 ?m or less, and
wherein a transmittance of the aluminum pattern is 80% to 100%.

US Pat. No. 10,796,816

RESIN COMPOSITION, INORGANIC FILLER, DIRECT-CURRENT POWER CABLE, AND METHOD OF MANUFACTURING DIRECT-CURRENT POWER CABLE

SUMITOMO ELECTRIC INDUSTR...

1. A resin composition forming an insulation layer, comprising:a base resin containing polyolefin, and
an inorganic filler;
wherein a surface of the inorganic filler comprises:
a hydrophobic silyl group represented by the following formula (1), and
an aminosilyl group having an amino group,
wherein a molar fraction of the aminosilyl groups with respect to all of the silyl groups bonded to the surface of the inorganic filler is 2% or more and 90% or less:

wherein R1a, R1b, and R1c represent any one of a C1 to C20 alkyl group, a C2 to C20 alkenyl group, or a C6 to C12 aryl group optionally substituted with a C1 to C3 alkyl group,
provided that R1a, R1b, and R1c may be the same, or two or more of them may be different.

US Pat. No. 10,796,815

INSULATING MATERIAL AND WIRING MEMBER

KYOCERA Corporation, Kyo...

1. An insulating material, comprising:a composite resin material comprising an organic resin and minute particles containing a metal element, wherein
the organic resin comprises a resin material comprising a polyester as a main backbone thereof and having an alkoxy group,
the polyester includes at least one of polycarbonate and polyarylate,
the alkoxy group and the main backbone of the resin material are bound together by ester binding,
the minute particles have an average particle size of greater than or equal to 0.5 nm but less than or equal to 50 nm, and
the metal element is contained in the composite resin material in an amount of greater than or equal to 0.05% by mass but less than or equal to 5.0% by mass.

US Pat. No. 10,796,814

INSULATED WINDING WIRE WITH CONFORMAL COATINGS

Essex Group LLC, Atlanta...

1. An insulated winding wire comprising:a conductor; and
insulation formed around the conductor, the insulation comprising:
a first layer comprising a first parylene material; and
a second layer comprising a second parylene material different from the first parylene material.

US Pat. No. 10,796,812

COATING LIQUID FOR FORMING CONDUCTIVE LAYER, METHOD FOR PRODUCING CONDUCTIVE LAYER, AND CONDUCTIVE LAYER

SUMITOMO ELECTRIC INDUSTR...

1. A coating liquid for forming a conductive layer, the coating liquid comprising fine metal particles, a dispersant, chloride ions, and a dispersion medium,wherein the fine metal particles contain copper or a copper alloy as a main component,
the dispersant is a polyethyleneimine-polyethylene oxide graft copolymer,
a polyethyleneimine moiety in the graft copolymer has a weight-average molecular weight of 300 or more and 1,000 or less,
a molar ratio of polyethylene oxide chains to nitrogen atoms in the polyethyleneimine moiety is 10 or more and 50 or less,
the graft copolymer has a weight-average molecular weight of 3,000 or more and 54,000 or less, and
a content of chloride ions is 0.2 g/L or more and 10.0 g/L or less,
wherein an electrical conductivity of the coating liquid for forming the conductive layer is 100 ?S/cm or more and 800 ?S/cm or less.

US Pat. No. 10,796,811

ALUMINUM ALLOY WIRE, ALUMINUM ALLOY STRAND WIRE, COVERED ELECTRICAL WIRE, AND TERMINAL-EQUIPPED ELECTRICAL WIRE

Sumitomo Electric Industr...

1. An aluminum alloy wire composed of an aluminum alloy, whereinthe aluminum alloy contains more than or equal to 0.03 mass % and less than or equal to 1.5 mass % of Mg, more than or equal to 0.02 mass % and less than or equal to 2.0 mass % of Si, and a remainder of Al and an inevitable impurity, Mg/Si being more than or equal to 0.5 and less than or equal to 3.5 in mass ratio, and
the aluminum alloy wire has a dynamic friction coefficient of less than or equal to 0.8, wherein one or more of the following conditions are satisfied: a tensile strength is more than or equal to 150 MPa; a 0.2% proof stress is more than or equal to 90 MPa; a breaking elongation is more than or equal to 5%; and an electrical conductivity is more than or equal to 40% IACS.

US Pat. No. 10,796,810

PROCESS OF GENERATING GERMANIUM

Curium US LLC, St. Louis...

1. A process for generating a radioisotope, the process comprising:bombarding a target body including a starting material, wherein the bombardment of the starting material produces a radioisotope within the target body;
allowing the bombarded target body to decay;
stripping the bombarded target body with an acidic mixture to create a stripped solution, wherein the acidic mixture includes 3 M to 6 M hydrochloric acid (HCl) and 6 M to 15 M nitric acid (HNO3);
extracting the radioisotope from the stripped solution using a non-polar solvent to remove the acidic mixture and create a non-polar solvent fraction including the radioisotope;
washing the non-polar solvent fraction including the radioisotope; and,
extracting the radioisotope from the non-polar solvent fraction using water.

US Pat. No. 10,796,809

SYSTEM FOR REMOVING FOREIGN OBJECTS FROM NUCLEAR REACTOR VESSEL

Sichuan Xingzhi Zhihui In...

1. A system with function of bending and elongation for discharging foreign matters from nuclear reactor vessel, comprising an operating rod capable of extending into the nuclear reactor vessel, wherein the operating rod comprises:a suction pipe;
a bendable rod section connected to an upper end of the suction pipe;
an expandable rod section connected to an upper end of the bendable rod section;
a suction opening disposed at a lower end of the suction pipe;
an electric valve disposed at a connection of an upper end of the suction opening and the suction pipe;
a filter mesh disposed in the suction pipe and above the electric valve;
a suction pump disposed in the suction pipe and above the filter mesh;
a touch switch disposed on the filter mesh, wherein the touch switch is in operative connection with the electric valve and wherein a foreign matter impact force to the filter mesh triggers the touch switch to close which causes the electric valve to close which prevents escape of foreign matter from the system; and
a drainage pipe; wherein a water inlet of the suction pump is connected to the suction opening, a water outlet of the suction pump is connected to an outside space of the suction pipe though the drainage pipe, and the electric valve is controlled by the touch switch.

US Pat. No. 10,796,808

CONTAINMENT SEAL

NUSCALE POWER, LLC, Corv...

1. A nuclear reactor containment seal for use sealing an opening of a containment vessel, comprising:a lower body having an opening positionable to align with the opening of the containment vessel;
an upper body including a through-hole, with the through-hole of the upper body and the opening of the lower body configured to receive a cable or tube to extend therethrough, the upper body having a bottom tubular section configured to insert at least partially down into the opening in the lower body, and a middle section that extends up and radially out from the bottom section and forms a bottom surface that seats onto a top surface of the lower body, the middle section having a threaded side surface; and
a nut retained by the lower body and configured to threadably engage the threaded side surface of the upper body to hold the upper body down against the lower body, forming a sealed connection between the upper body and the lower body.

US Pat. No. 10,796,807

NUCLEAR REACTOR FUEL ROD AND FUEL ASSEMBLY HAVING BUNDLED SAME

HITACHI, LTD., Tokyo (JP...

1. A nuclear reactor fuel rod for light-water reactor, comprising:a fuel cladding tube; and
an end plug, the end plug having an insertion straight body portion and a butting surface, the insertion straight body portion being inserted into the fuel cladding tube, the butting surface butts with an end surface of the fuel cladding tube,
wherein both of the fuel cladding tube and the end plug are composed of a silicon carbide material,
a bonding portion between the fuel cladding tube and the end plug is formed by brazing and/or by diffusion bonding with a predetermined metal bonding material interposed, the predetermined metal bonding material having a solidus temperature of 1200° C. or higher,
an outer surface of the bonding portion, and a portion of an outer surface of the fuel cladding tube and the end plug, which is adjacent to the outer surface of the bonding portion are covered by bonding-portion coating formed of a predetermined coating metal, and
the predetermined metal bonding material and the predetermined coating metal have an average linear expansion coefficient which is less than 10 ppm/K.

US Pat. No. 10,796,806

FIRST WALL CONDITIONING IN A FUSION REACTOR VESSEL

Tokamak Energy Ltd., Oxf...

3. A fusion reactor vessel sputtering assembly comprising:a support arm configured for insertion into the reactor vessel via a port, arm comprising:
an RF electrode operably coupled to an RF power supply and configured to generate a plasma when power is supplied to the RF electrode from the power supply;
a crucible supporting a material, the crucible operatively coupled to the RF electrode, such that the plasma generated by the RF electrode sputters the material; and
one or more filaments operably coupled to one or more further power supplies, wherein the one or more filaments are configured to provide electrons to the plasma,
wherein the support arm places the RF electrode, the crucible, and the one or more filaments within an interior of the reactor vessel.

US Pat. No. 10,796,805

ASSESSMENT OF A PULMONARY CONDITION BY SPEECH ANALYSIS

CORDIO MEDICAL LTD., Or-...

1. Apparatus, comprising:a network interface; and
a processor, configured:
to receive, via the network interface, a signal representing speech of a subject who suffers from a pulmonary condition related to accumulation of excess fluid,
to identify, by performing a spectral analysis of the signal, one or more spectral properties of the speech,
to assess, in response to the properties, a status of the pulmonary condition by identifying a change in an amount of the fluid present in an anatomical portion of the subject selected from the group of anatomical portions consisting of: parenchyma of lungs of the subject, and a pleural cavity of the subject, and
to generate, in response thereto, an output indicative of the status of the pulmonary condition.

US Pat. No. 10,796,804

SYSTEMS AND METHODS FOR TRANSITIONING PATIENT CARE FROM SIGNAL-BASED MONITORING TO RISK-BASED MONITORING

Etiometry, Inc., Boston,...

8. A computer-implemented method for risk-based monitoring of a patient, comprising:providing a computer having a display device and a computer accessible memory;
providing a plurality of physiological sensors including at least a heart rate sensor and an SpO2 sensor, the plurality of sensors physically attached to the critical care patient;
acquiring, with the computer from at least the physiological sensors coupled to the patient, data associated with a plurality of internal state variables each describing a parameter physiologically relevant to one of a treatment and a condition of the patient, wherein some of the data associated with the plurality of the internal state variables is intermittent or aperiodic;
storing, in the computer accessible memory, the acquired data associated with the plurality of the internal state variables;
generating, by the computer, predicted probability density functions for the plurality of the internal state variables at time step tk;
generating, by the computer, predicted probability density functions for the plurality of the internal state variables at previous time step tk?1, by evolving backwards from the predicted probability density functions at time step tk to the time step tk?1;
generating, by the computer using Bayes theorem, posterior probability density functions for the internal state variables at the previous time step tk?1;
determining, based on the generated posterior probability density functions for the internal state variables for the time step tk?1, a set of possible states at the previous time step tk?1 of a hidden internal state variable;
generating, based on the set of possible states at the previous time step of tk?1 of the hidden internal state variable, probabilities of possible patient states, wherein the possible patient states cannot be directly measured; and
causing the display, on a display device, of a plurality of graphical indicators, each of the plurality of graphical indicators corresponding to one possible patient state of the set of possible patient states, each of the plurality of graphical indicators graphically identifying the probability that the patient is in a corresponding patient state at a given point in a range of time, the plurality of graphical indicators configured to indicate a hazard level; and
causing the display, on the display device, of a timeline controller configured to allow a user to dynamically select a plurality of points in time over the range of time, the graphical indicators changing dynamically in response to a specification by the user of one of the plurality of points in time to display the evolution of the one possible patient state of the set of possible patient states over the range of time.

US Pat. No. 10,796,803

METHOD FOR INTEGRATING AND PROVIDING COLLECTED DATA FROM MULTIPLE DEVICES AND ELECTRONIC DEVICE FOR IMPLEMENTING SAME

Samsung Electronics Co., ...

1. An electronic device comprising:a housing;
a display exposed through a part of the housing;
a first motion sensor disposed within the housing and configured to detect movement of the housing;
a wireless communication circuit disposed within the housing;
a processor disposed within the housing and electrically connected to the display, the first motion sensor, and the wireless communication circuit; and
a memory electrically connected to the processor, wherein the memory stores instructions that, when executed by the processor, cause the processor to:
establish, using the wireless communication circuit, a wireless communication channel with an external electronic device that includes a second motion sensor;
obtain first data regarding the movement of the housing by using the first motion sensor for a first time period;
receive second data regarding a movement of the external electronic device obtained by the second motion sensor of the external electronic device for the first time period through the wireless communication channel;
identify a first user activity type indicated by the first data;
identify a second user activity type indicated by the second data;
determine the first user activity type indicated by the first data is different from the second user activity type indicated by the second data;
based on the determination that the first user activity type is different from the second user activity type, select one of the first user activity type or the second user activity type based on a designated priority; and
based on the selection, recognize an activity performed by a user for the first time period as the selected user activity type.

US Pat. No. 10,796,802

COMPUTER DECISION SUPPORT FOR DETERMINING SURGERY CANDIDACY IN STAGE FOUR CHRONIC KIDNEY DISEASE

Cerner Innovations, Inc.,...

1. A method for placing a vascular access device, the method comprising:measuring one or more physiologic variables used to establish a current estimated glomerular filtration rate (eGFR) for the patient;
computing the current eGFR for the patient from the one or more physiologic variables;
receiving a plurality of previously determined eGFRs for the patient corresponding to a plurality of time-stamped data points;
determining if a future eGFR value for the patient at a future time interval is outside of predetermined limits by:
determining an eGFR slope value from the current eGFR and the plurality of previously determined eGFRs,
computing a first logistic regression forecast eGFR value using the current eGFR, the plurality of previously determined eGFRs, and the eGFR slope value,
minimizing an objective function using one or more evolutionary algorithms to compute a second logistic regression forecast eGFR value using the current eGFR, the plurality of previously determined eGFRs, and the eGFR slope value,
combining at least the first logistic regression forecast eGFR value and the second logistic regression forecast eGFR value to compute a composite regression forecast eGFR value, and
determining if at least one of the first logistic regression forecast eGFR value, the second logistic regression forecast eGFR value, and the composite regression forecast eGFR value is outside of the predetermined limits; and
upon determining that at least one of the first logistic regression forecast eGFR value, the second logistic regression forecast eGFR value, and the composite regression forecast eGFR value is outside of the predetermined limits, initiating an action corresponding to treatment of the patient that includes placement of a device that facilitates vascular access.

US Pat. No. 10,796,801

METHOD AND SYSTEM FOR ASSESSING, QUANTIFYING, CODING AND COMMUNIICATING PATIENT'S HEALTH AND PERIOPERATIVE RISK

1. A multi-dimensional system that quantitatively organizes otherwise non-quantified and independently quantified information with respect to a patient's medical issues by utilizing commonly scaled numeric rankings comprising:a computer station comprising:
a graphical user interface for inputting patient information to a database;
a conversion dictionary providing a uniform numeric vocabulary for assessment of text and measurements pertaining to a patient's health status with a common scale associated with a patient's medical condition across multiple variables, the conversion dictionary providing for conversion of patient information input via the graphical user interface to provide common numeric coding and scoring across myriad conditions and bodily systems; and
a processor which calculates health assessments based upon a template and uniform scaling in accordance with the conversion dictionary, activity status for each condition and severity of a patient's condition at a level of an encompassing bodily system and at a target level;
the processor further co-populates information entered for one disorder or body system throughout multiple database fields for various other disorders or body systems by linking the one disorder or body system to various other disorders or body systems so as to integrate clinical, investigative, quality improvement research and administrative functions with common data entry, coding and scoring, the co-populated information being exported for communication, diagnostic and treatment algorithms, quality assurance and quality improvement databases based on identical terminology common terminology based on universal language or common significance based upon text and/or code+score as mediated by the conversion dictionary;
the processor presenting an output to the graphical user interface for providing information relating to health of the patient, which is viewable by the user via the graphical user interface, and includes a score for the physical condition of the patient, a score for the degree of expected surgical risk and invasiveness or a score for other vital assessments of perioperative complexity;
wherein, when graded assessment of the health of the patient is indicated, the output includes one-time or uniformly scaled assessments regarding conditions, targets, systems and/or regions within and among patients presented at the time patient information is input to the database to succinctly and universally capture and organize vital features of patient morbidities and/or laboratory values and physiologic indices.

US Pat. No. 10,796,799

METHODS FOR THE PREDICTION OF A PERSONALIZED ESA-DOSE IN THE TREATMENT OF ANEMIA

ALBERT-LUDWIGS-UNIVERSITA...

1. A method for determining a dosage of an Erythropoiesis Stimulating Agent (ESA) that is sufficient for treating anemia in a patient, the method comprising the steps of:a) Calculating a degradation of hemoglobin per time for the patient from a hemoglobin concentration of the patient from at least two separate time points;
b) Determining in vitro a present hemoglobin concentration of the patient from a concentration of hemoglobin from a recent blood sample obtained from the patient;
c) Calculating an ESA dosage based on the degradation of hemoglobin per time and the present hemoglobin concentration to treat anemia in the patient;
d) Administering the ESA dosage to the patient to thereby treat anemia in the patient;
e) Monitoring the clearance of said ESA dosage from a serum in said patient;
f) Calculating from the clearance of said ESA dosage in said patient the number of initial ESA binding sites present in said patient using a non-linear dynamic pharmacokinetic (PK) ESA-EPO-R pathway model; and
g) Adjusting the ESA dosage administered to the patient in accordance with the number of ESA binding sites.

US Pat. No. 10,796,798

SYSTEM AND METHOD OF A VIRTUAL SAND TRAY

Virtual Sandtray, LLC, F...

1. A computer-implemented method for studying an internal state of a patient, comprising:generating a virtual environment comprising a background skybox and a texture-mapped wireframe base layer that graphically represents a sand tray comprising a base layer;
providing one or more texture-mapped wireframe object models to be placed in the virtual environment, wherein or more object models in a first group are associated with a positive-orientation, one or more object models in a second group are associated with a negative-orientation, one or more object models in a third group are associated with one or more emotional states;
providing one or more tools to manipulate the virtual environment and the one or more object models by altering animations, behaviors, and interactions between one or more object models and the virtual environment, wherein at least some manipulations of the virtual environment are classified as constructive behaviors and at least some manipulations of the virtual environment are classified as destructive behaviors;
recording, in a computer database, an order of the placement of one or more selected object models in the virtual environment, an amount of time associated with selecting a particular object model of the one or more selected object models, and an association of the one or more selected object models, wherein the association comprises one or more of the positive-orientation, the negative-orientation, and the one or more emotional states;
recording, in the computer database, the classification of the manipulations of the virtual environment;
analyzing, with an analyzer coupled with the computer database, the recorded association of the one or more object models and the recorded classification of the manipulation of the virtual environment;
automatically correlating, by use of analyzer-performed pattern recognition of the recorded order of the placement of one or more selected object models and the recorded classification of the manipulations of the virtual environment, an internal state of a patient to with the recorded association of the one or more selected object models and the recorded classification of the manipulation of the virtual environment; and
generating, with the analyzer, an analysis comprising a summary of the one or more selected object models and the correlated internal state of the patient.

US Pat. No. 10,796,797

SENSOR NETWORK FOR BREAST PUMPING MOTHERS

Moxxly, LLC, Wilmington,...

1. A breast pump sensor network, comprising: a plurality of emitters disposed within a bodily fluid capture system, which emit beams of electromagnetic radiation into the bodily fluid capture system, a plurality of detectors disposed within the bodily fluid capture system, wherein an emitter of the plurality of emitters is disposed adjacent to a corresponding detector of the plurality of detectors, so as to form a plurality of emitter and detector pairs, wherein bodily fluid is carried to a reservoir by a spout disposed in a flange and droplets of bodily fluid are output from the reservoir, the droplets being released from the reservoir at a known volumetric measurement, wherein the reservoir is disposed above the detector, below the flange, and above a valve within the bodily fluid capture system, wherein the reservoir allows the bodily fluid to pool in the reservoir and allows the droplets of the known volumetric measurement to fall from the reservoir, to be detected by during the fall, and fall into the valve which closes and opens based on vacuum pressure applied to the valve by vacuum suction, and a processor counting the detected droplets, and further comprising a lens configured to control reflections of the emitted electromagnetic radiation to direct reflections into the detector.

US Pat. No. 10,796,796

FAULT DIAGNOSIS APPARATUS, FAULT DIAGNOSIS METHOD, AND FAULT DIAGNOSIS PROGRAM

FUJIFILM Corporation, To...

1. A fault diagnosis apparatus comprising:an acquisition unit that acquires, for each of a plurality of devices, installation environment information including a plurality of items about an installation environment in which each of the plurality of devices is installed;
a classification unit that classifies the plurality of devices into a plurality of groups on the basis of the installation environment information;
an extraction unit that extracts an item in the installation environment information representing a feature of a group to which a device in which a fault has occurred among the plurality of devices belongs, the feature being different from a feature of other groups; and
a display control unit that performs control to cause a display unit to display an extraction result obtained by the extraction unit.

US Pat. No. 10,796,795

VIRTUAL WAITING ROOM FOR MEDICAL APPOINTMENTS

1. A system comprising:(a) a first user device corresponding to a medical professional, wherein the first user device comprises a wireless transceiver;
(b) a location sensor located within a first examination room, wherein the location sensor is configured to form a connection with the wireless transceiver of the first user device via wireless data packets, wherein the connection between the location sensor and the first user device indicates a presence of the medical professional in the first examination room;
(c) an appointment database configured to store scheduling information,
wherein the scheduling information includes a plurality of scheduled appointments with a plurality of patients on a particular day, the plurality of patients including a first patient, wherein the plurality of scheduled appointments includes a first appointment for the first patient,
wherein Health Insurance Portability and Accountability Act (HIPAA) information is cryptographically separated from the scheduling information, wherein HIPAA information is protected from inadvertent or unauthorized access by a network firewall, wherein HIPAA information is encrypted for storage and transmission using a first mechanism distinct from a second mechanisms used to store and transmit the scheduling information; and
(d) a schedule management hub comprising:
(i) a user device interface configured to receive a first time from the first user device, wherein the first time is associated with the connection between the location sensor and the first user device and indicates when the medical professional begins the first appointment with the first patient,
(ii) a medical schedule processor configured to:
receive the scheduling information from the appointment database,
compare the first time with the scheduling information to determine whether future appointments will be delayed, and
determine modified appointment times for one or more appointments of the plurality of scheduled appointments following the first appointment based on determined delays, and
(iii) a notification interface configured to transmit data to a medical scheduling management application on a second user device, wherein the data includes a current appointment status of the medical professional and predicted delays and modified appointment times for each of the plurality of scheduled appointments, wherein the current appointment status includes whether a current appointment of the plurality of scheduled appointments is delayed and an amount of delay for the current appointment, wherein the predicted delays and modified appointment times are updated periodically, and wherein the data is displayed at the second user device via the medical scheduling management application and is viewable by one or more patients of the plurality of patients.

US Pat. No. 10,796,794

DELETION OF MEDICAL IMAGES IN CLOUD-BASED STORAGE

Konica Minolta Healthcare...

1. A method for controlling automatic deletion of medical images in a universal viewer system that shares the medical images between a cloud server and a plurality of healthcare facilities connected to the cloud server, the method comprising:receiving, by the cloud server and from a user at one of the healthcare facilities, an automatic deletion request that comprises a target deletion period and a deletion start time;
determining, by the cloud server and after the deletion start time has elapsed, a target medical image based on the target deletion period;
retrieving, by the cloud server, authority information of the user;
retrieving, by the cloud server, an access history of the target medical image;
determining, by the cloud server, whether the target medical image is accessed by a plurality of users based on the access history;
determining, by the cloud server and in response to determining that the target medical image is accessed by a plurality of users, whether the authority information is lower than, matches, or higher than a pre-configured specified authority level;
upon determining that the authority information is lower than the pre-configured specified authority level, further determining, by the cloud server, that the target medical image should not be deleted and terminating the automatic deletion request without deleting the target medical image, or upon determining that the authority information matches or is higher than a pre-configured specified authority level, further determining, by the cloud server, that the target medical image can be deleted;
storing in a memory, by the cloud server, a result of the automatic deletion request; and
causing, by the cloud server, the result of the automatic deletion request to be displayed on a display of at least one of the healthcare facilities.

US Pat. No. 10,796,793

AGGREGATION OF ARTIFICIAL INTELLIGENCE (AI) ENGINES

VARIAN MEDICAL SYSTEMS IN...

1. A method for a computer system to generate an aggregated artificial intelligence (AI) engine for radiotherapy treatment planning, wherein the method comprises:obtaining multiple AI engines associated with respective multiple treatment planners, wherein the multiple AI engines are trained to perform a particular treatment planning step, and each of the multiple AI engines is trained to emulate one of the multiple treatment planners performing the particular treatment planning step;
generating multiple sets of output data using the multiple AI engines associated with the respective multiple treatment planners;
comparing the multiple AI engines associated with the respective multiple treatment planners based on the multiple sets of output data; and
based on the comparison, aggregating at least some of the multiple AI engines to generate the aggregated AI engine for performing the particular treatment planning step.

US Pat. No. 10,796,792

EXTRACORPOREAL BLOOD TREATMENT MACHINE

Gambo Lundia AB, Lund (S...

1. A machine for extracorporeal blood treatment comprising:a machine body;
at least one blood pump actuator supported by the machine body;
a disposable extracorporeal blood circuit configured to be coupled with the blood pump actuator;
at least one touch screen user interface including at least one touch screen;
at least one memory containing at least
a first image comprising a first pictograph, the first pictograph including a representation of at least a portion of the machine body and the disposable extracorporeal blood circuit in a first configuration, wherein the first image illustrates in graphical form how to perform a first procedural step to prepare the machine for use, and
a second image comprising a second pictograph, the second pictograph including a representation of at least a portion of the machine body and the disposable extracorporeal blood circuit in a second configuration, wherein the second image illustrates in graphical form how to perform a second procedural step to prepare the machine for use; and
at least one control unit programmed to execute the following steps
detect a selection of said first image,
display said first image on the touch screen,
detect execution of said first procedural step,
generate and issue a first user feedback to indicate to an operator the execution of the first procedural step,
detect a selection of said second image,
display said second image on the touch screen,
detect execution of said second procedural step, and
generate and issue a second user feedback to indicate to the operator the execution of the second procedural step.

US Pat. No. 10,796,791

RECORDING DOSE DATA FROM DRUG INJECTION DEVICES USING OPTICAL CHARACTER RECOGNITION (OCR)

Sanofi-Aventis Deutschlan...

1. A method of recording a medicament dose using a data collection device, comprising:capturing, by a video camera of the data collection device, a video showing a medicament dose indicator of an injector pen;
determining a position of at least one of one or more characters in an image in said video;
identifying the at least one character using optical character recognition software;
determining a medicament dose indicated by the medicament dose indicator based on a result of said identifying using said optical character recognition software; and
determining whether more than one delivery of medicament is recorded in said video, wherein the injector pen comprises a movable component for selecting said medicament dose to be dispensed.

US Pat. No. 10,796,790

MEDICATION COMPLIANCE PLATFORMS, SYSTEMS, AND DEVICES

Longevity Health Corp., ...

1. A smart medicament container cap comprising:(a) a housing comprising a bottle engagement coupling configured to engage with a medicine bottle, a medicine bottle sleeve, or both;
(b) a security input connected to the housing and configured to receive a security data;
(c) an actuator connected to the housing;
(d) a compression plate connected to the actuator and engaged with the housing by a slideable coupling; and
(e) a digital processing device connected to the housing, wherein the digital processing device is configured to receive the security data from a security input and to command the actuator in response to at least the security data;
wherein the bottle engagement coupling, the actuator, and the compression plate are configured to temporarily prevent access to contents within the medicine bottle, the medicine bottle sleeve, or both.

US Pat. No. 10,796,789

METHOD AND APPARATUS FOR INITIATING A MEDICINE CONTROL ACTION

1. A method for initiating a medicine control action, the method comprising:transmitting, by a processor deployed in a communication network, a first control signal to cause an endpoint device to disable at least one functionality of the endpoint device, wherein the first control signal is transmitted in accordance with a pill consumption schedule of a user of the endpoint device;
receiving, by the processor from the endpoint device, at least one picture, the at least one picture comprising an image of one or more pills and an image of a respective prescription bottle of each one of the one or more pills;
receiving, by the processor from the endpoint device, food information of a food item;
determining, by the processor, the medicine control action is required in response to the receiving the at least one picture and the receiving the food information, wherein the determining comprises:
identifying the one or more pills in the at least one picture via a medication database; and
comparing the food information to information in a food database to identify a negative interaction between the food item and the one or more pills;
establishing, by the processor, a data connection with the endpoint device in response to the determining;
initiating, by the processor, the medicine control action over the data connection to the endpoint device, wherein the medicine control action comprises a warning message sent to the endpoint device indicating that the food item has the negative interaction with the one or more pills; and
transmitting, by the processor, a second control signal to cause the endpoint device to enable the at least one functionality of the endpoint device.

US Pat. No. 10,796,788

STRUCTURAL DETERMINATION OF CARBOHYDRATES USING SPECIAL PROCEDURE AND DATABASE OF MASS SPECTRA

Academia Sinica, Taipei ...

1. A method for constructing a set of database, comprising steps of:separating anomeric configurations of a saccharide, and
measuring and storing one or a plurality of sequential mass spectra of the separated anomeric configurations of the saccharide.

US Pat. No. 10,796,782

SYSTEM, METHOD AND APPARATUS TO ENHANCE PRIVACY AND ENABLE BROAD SHARING OF BIOINFORMATIC DATA

1. A system for selectively designating segments of bioinformatics data of a genome in an electronic document comprising:(a) at least one computer configured to receive from a party wishing to designate segments of bioinformatics data, selected directives of a set of selectable access control directives, wherein said bioinformatics data is metadata concerning variants identified within the sub-bands of the chromosomes, and said designated segments are metadata indicating, for each of said chromosomal sub-bands, the name of the gene located within said single chromosomal sub-band wherein a variant is identified;
(b) receive a command from the person to whom said bioinformatics data pertains or said person's designated representative designating said segments of said electronic document so as to identify at least one portion of said bioinformatics data to be subject to access control;
(c) present a set of selectable access control directives defining conditions for access to said at least one portion of said metadata;
(d) receive selected directives of said set of selectable access control directives; and
(e) impose access control of said at least one portion of said metadata in accordance with said conditions in response to receiving said selective access control directives.

US Pat. No. 10,796,780

SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A shift register unit, comprising an input circuit, a first pull-down circuit, a second pull-down circuit, and an output circuit;wherein the input circuit is coupled to a pull-up node, an input signal terminal, a first level signal terminal, a reset signal terminal and a second level signal terminal, and is configured to charge the pull-up node;
the output circuit is coupled to the pull-up node, a first clock signal terminal and an output terminal, and is configured to output a signal inputted by the first clock signal terminal to the output terminal under control of a level of the pull-up node;
the first pull-down circuit is coupled to the pull-up node, a first level power signal terminal and a third level signal terminal; and
the second pull-down circuit is coupled to the first clock signal terminal, a second clock signal terminal, the first level power signal terminal and the output terminal;
wherein in a first state, the first pull-down circuit is configured to pull down the level of the pull-up node, and the second pull-down circuit is configured to pull down a level of the output terminal;
the second pull-down circuit comprises a second transistor and a third transistor;
a gate electrode of the second transistor is coupled to the first clock signal terminal, a first electrode of the second transistor is coupled to a second electrode of the third transistor, and a second electrode of the second transistor is coupled to the output terminal; and
a gate electrode of the third transistor is coupled to the second clock signal terminal, and a first electrode of the third transistor is coupled to the first level power signal terminal.

US Pat. No. 10,796,779

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a first memory cell which is capable of being set to any one of at least eight threshold voltages;
a first bit line electrically connected to the first memory cell;
a sense amplifier connected to the first bit line, wherein the sense amplifier has at least four data latch circuits;
an extra data latch circuit electrically connected to the sense amplifier through a bus; and
a controller configured to control a write operation that includes a programming operation for changing the threshold voltage of the first memory cell and a verification operation for verifying the threshold voltage of the first memory cell, wherein the controller is configured to cause, in the programming operation, the extra data latch circuit and at least one of the four data latch circuits to be accessed, and
wherein the controller is configured to cause, in the verification operation, the four data latch circuits, but not the extra latch circuit, to be accessed.

US Pat. No. 10,796,778

APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN 3D NON-VOLATILE MEMORY OPERATIONS

Micron Technology, Inc., ...

1. An apparatus comprising:a memory cell string including memory cells coupled between a first select transistor and a second select transistor, and a body associated with the memory cells and the first and second select transistors, the memory cells and the first and second transistors located in different levels of the apparatus;
a control gate associated with a memory cell of the memory cells of the memory cell string;
a first select gate associated with the first select transistor;
a second select gate associated with the second select transistor;
a data line coupled to the body of memory cell string;
a source coupled to the body of memory cell string; and
a memory control unit including hardware circuitry, the memory control unit configured to:
apply a ground potential to the first and second select gates during at least a portion of an operation performed on the memory cell;
apply a first voltage having a first value to the control gate in a first stage of the operation, the first value being a positive value;
apply a second voltage having a second value to the control gate in at least a portion of a second stage of the operation, the second value being less than the first value; and
while the ground potential is applied to the first and second select gates in the second stage, perform at least one of,
apply a third voltage having a positive value to the data line, and
apply a fourth voltage having a positive value to the source.

US Pat. No. 10,796,777

METHOD FOR PROGRAMMING IN NON-VOLATILE MEMORY DEVICE BY APPLYING MULTIPLE BITLINE BIAS VOLTAGES

Yangtze Memory Technologi...

1. A method for programming in a non-volatile memory device, comprising:applying at least one programming pulse to a non-volatile memory cell of the non-volatile memory device during each of previous programming loops;
applying at least one programming pulse to the non-volatile memory cell during a current programming loop; and
providing a bitline bias voltage of the non-volatile memory cell according to a result of comparing a threshold voltage of the non-volatile memory cell in at least one of the previous programming loops with a low verify level and/or a high verify level of a target data state of the non-volatile memory cell and a result of comparing a threshold voltage of the non-volatile memory cell in the current programming loop with the low verify level and/or the high verify level of the target data state of the non-volatile memory cell.

US Pat. No. 10,796,776

NONVOLATILE MEMORY AND MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A nonvolatile memory comprising:a memory cell array including a plurality of memory cells, each of the plurality of memory cells being configured to store data in accordance with a threshold voltage thereof; and
a control circuit configured to execute a first refresh process upon receiving a first command set,
wherein:
the first refresh process includes reprogramming at least one second memory cell among a plurality of first memory cells to which data has been programmed; and
in executing the first refresh process, the control circuit is configured to:
select the second memory cell from the plurality of first memory cells by verifying that a threshold voltage of the second memory cell is a voltage obtained by shifting a first voltage by a first correction amount in a case where the second memory cell has been programmed using the first voltage; and
select the second memory cell from the plurality of first memory cells by verifying that the threshold voltage of the second memory cell is a voltage obtained by shifting a second voltage by a second correction amount in a case where the second memory cell has been programmed using the second voltage.

US Pat. No. 10,796,775

SEMICONDUCTOR DEVICE INCLUDING MEMORY CELLS STORING MULTI-BIT DATA AND OPERATING METHOD OF THE SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...

1. A method for operating a semiconductor device, the method comprising:sorting program states of a memory cell that stores multi-bit data into a plurality of groups;
applying different bias voltages to selected bit lines corresponding to a selected group among the plurality of groups;
applying a bias voltage among the different bias voltages to unselected bit lines corresponding to an unselected group among the groups;
applying a first program voltage to a selected word line corresponding to the selected group; and
verifying whether each of selected memory cells corresponding to the selected word line is programmed to a respective target program state.

US Pat. No. 10,796,774

METHOD AND APPARATUS FOR REFRESHING FLASH MEMORY DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A method of refreshing a flash memory device having memory blocks including a first memory block and a second memory block, the method comprising:recording a first number of erase operations performed on the first memory block, and a second number of erase operations performed on the second memory block;
detecting a first bit error rate of the first memory block, and a second bit error rate of the second memory block;
setting a first refresh cycle for the first memory block based on the first number of erase operations and the first bit error rate;
setting a second refresh cycle for the second memory block based on the second number of erase operations and the second bit error rate, the second refresh cycle being different from the first refresh cycle;
determining that a storage time length of data stored in a page of the first memory block has reached the first refresh cycle;
refreshing the first memory block according to the first refresh cycle; and
refreshing the second memory block according to the second refresh cycle.

US Pat. No. 10,796,773

MEMORY DEVICES INCLUDING VOLTAGE GENERATION SYSTEMS

Micron Technolgy, Inc., ...

1. A memory device comprising:a memory array comprising a plurality of planes;
a plurality of voltage generation systems, each voltage generation system of the plurality of voltage generation systems electrically coupled to a corresponding plane of the plurality of planes;
a controller configured to turn on each voltage generation system of the plurality of voltage generation systems in response to a first command to access a first plane of the plurality of planes; and
a detector configured to detect a discharge level of the plurality of voltage generation systems.

US Pat. No. 10,796,772

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A method for operating a semiconductor memory device, the method comprising:receiving a read command;
performing a sensing operation on a plurality of memory cells, using a set of reference currents;
determining whether a read operation has succeeded, as a result of the sensing operation; and
changing the set of reference currents, based on the determined result;
wherein the changing of the set of reference currents, based on the determined result, includes:
when the read operation fails, determining whether the number of is times that the read operation has failed has reached a predetermined critical value;
when the number of times that the read operation has failed has not reached the critical value, changing the set of reference currents; and
performing the sensing operation on the plurality of memory cells, 20 using the changed set of reference currents.

US Pat. No. 10,796,771

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a first group including a plurality of memory cells;
a second group including a plurality of memory cells; and
a control circuit configured to successively apply a first voltage and a second voltage which is higher than the first voltage to a first memory cell in the first group or the second group, and to apply a third voltage to the first memory cell after applying the second voltage,
wherein
when the first memory cell is included in the first group, the control circuit applies the third voltage to the first memory cell a first time earlier with respect to a time when the second voltage is applied than when the first memory cell is included in the second group, and
each of the first group and the second group corresponds to a data erase unit or a unit larger than the data erase unit.

US Pat. No. 10,796,770

SENSING CIRCUIT OF MEMORY DEVICE AND ASSOCIATED SENSING METHOD

MACRONIX INTERNATIONAL CO...

1. A sensing circuit of a memory device, comprising:a cell, coupled to a first node, wherein the cell is a NAND cell or a NOR cell;
a first transistor;
a compensation source capable of providing a compensating current to the first node during a read cycle; and
a sensing module coupled to the first node, comprising:
a second transistor, wherein a first source/drain terminal of the second transistor is coupled to a second node, a second source/drain terminal of the second transistor is coupled to a ground terminal, and a gate terminal of the second transistor is coupled to a third node;
a third transistor, wherein a first source/drain terminal of the third transistor is coupled to the first node, a second source/drain terminal of the third transistor is coupled to the third node, and a gate terminal of the third transistor receives a second control signal;
wherein the cell is capable of generating a cell current during the read cycle, and the sensing module determines that the cell is in a first storing state or a second storing state in response to a relationship between the compensating current and the cell current.

US Pat. No. 10,796,769

MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME

SK hynix Inc., Gyeonggi-...

1. A memory device, comprising:page buffers arranged in a first direction and a second direction perpendicular to the first direction;
a first storage group and a second storage group arranged adjacent to the page buffers in the second direction;
a switch circuit arranged between the first storage group and the second storage group and selectively coupling the first storage group and the second storage group to data lines in response to a first signal and a second signal;
first storage latches that are coupled to the switch circuit through first cache lines; and
second storage latches that are coupled to the switch circuit through second cache lines,
wherein the switch circuit couples the first cache lines and the data lines to each other when the first signal is enabled, and couples the second cache lines and the data lines to each other when the second signal is enabled.

US Pat. No. 10,796,768

SEMICONDUCTOR MEMORY DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor memory device comprising:a first memory area for storing data; and
a second memory area for storing information related to the data,
wherein initial threshold voltages of memory cells arranged in the second memory area is higher than initial threshold voltages of memory cells arranged in the first memory area.

US Pat. No. 10,796,767

MEMORY DEVICE AND OPERATING METHOD THEREOF

Samsung Electronics Co., ...

1. A memory device, comprising:a cell array including a first cell string and a second cell string respectively connected to a first bit line and a second bit line; and
a page buffer circuit configured to apply an erase voltage greater than 0 v to the first bit line and to place the second bit line in a floating state at a same time the erase voltage is applied to the first bit line by the page buffer circuit, when an erase operation is performed on memory cells of the first and second cell strings.

US Pat. No. 10,796,766

NONVOLATILE MEMORY DEVICE AND A METHOD OF PROGRAMMING THE NONVOLATILE MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A method of programming a non-volatile memory device including a first memory block and a second memory block, the method comprising:performing a first program operation on a first memory cell in the first memory block and connected to a first word line of a first level with respect to a substrate;
after the performing of the first program operation on the first memory cell, performing the first program operation on a second memory cell in the second memory block and connected to a second word line of the first level;
after the performing of the first program operation on the second memory cell, performing the first program operation on a third memory cell in the first memory block and connected to a third word line of a second level vertically adjacent to the first level;
after the performing of the first program operation on the third memory cell, performing the first program operation on a fourth memory cell in the second memory block and connected to a fourth word line of the second level;
after the performing of the first program operation on the fourth memory cell, performing a second program operation on the first memory cell; and
after the performing of the second program operation on the first memory cell, performing the second program operation on the second memory cell.

US Pat. No. 10,796,765

OPERATIONS ON MEMORY CELLS

Micron Technology, Inc., ...

1. A method, comprising:programming a memory cell coupled to a first signal line and a second signal line from a first data state to a second data state by:
applying a plurality of voltage differential pulses across the memory cell to cause a plurality of snap backs of the memory cell from a high-impedance state to a low-impedance state,
wherein each respective voltage differential pulse causes a respective snap back of the memory cell from the high-impedance state to the low-impedance state that incrementally changes a data state of the memory cell from the first data state towards the second data state.

US Pat. No. 10,796,764

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a memory cell capable of storing three-bit data including first bit data, second bit data, and third bit data, using one of eight threshold voltage states; and
a control circuit configured to perform a three-bit write operation to write the three-bit data on the memory cell, the three-bit write operation including a first write operation to write the first bit data in accordance with a first command set, a second write operation to write the second bit data in accordance with a second command set subsequent to the first command set, and a third write operation to write the third bit data in accordance with a third command set subsequent to the second command set,
the first command set including a first pre command, the first bit data, and a first post command,
the second command set including a second pre command, the second bit data, and a second post command, and
the third command set including a third pre command, the third bit data, and a third post command that is different from each of the first post command and the second post command, wherein
the first write operation includes programming of the memory cell to one of two threshold voltage states corresponding to the first bit data,
the second write operation includes programming of the memory cell to one of four threshold voltage states corresponding to the first bit data and the second bit data,
the third write operation includes programming of the memory cell to one of the eight threshold voltage states corresponding to the first bit data, the second bit data, and the third bit data,
based on the first write operation, the eight threshold voltage states are divided in two groups in which one of the two groups has first, second, third, and fourth target threshold voltages that are different from each other, and correspond to the first bit data, and
the control circuit starts the first write operation, in accordance with the first command set, before receiving the second command set entirely, to program the memory cell to one of the eight target threshold voltages which is the lowest target threshold voltage in one of the two groups.

US Pat. No. 10,796,763

METHOD FOR PROGRAMMING A SPLIT-GATE MEMORY CELL AND CORRESPONDING MEMORY DEVICE

STMicroelectronics (Rouss...

1. A method for programming a split-gate memory cell which comprises a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate, the method comprising:applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor; and
transitioning the third voltage during the programming duration between a first value and a second value greater than the first value.

US Pat. No. 10,796,762

SOLID STATE DRIVE ARCHITECTURES

THSTYME BERMUDA LIMITED, ...

1. A solid state drive (SSD) comprising:Dynamic Random Access Memory (DRAM) logical flash which stores files in the same way as NAND flash and responds to flash commands, wherein the DRAM logical flash comprises:
DRAM memory; and
a DRAM controller to manage data transfers into and out of the DRAM memory;
flash memory;
a master SSD controller; and
an interface to connect the SSD to a host having a Central Processing Unit (CPU) such that the CPU exclusively reads data from, and writes to, the DRAM logical flash, the DRAM logical flash providing principal data storage during operation of the CPU;
the SSD controller to independently determine when to transfer the data from the DRAM logical flash to the flash memory, wherein not all data written to the DRAM logical flash during operation of the CPU is eventually transferred to the flash memory
wherein the master SSD controller organizes data in the DRAM using a File Access Table (FAT) or New Technology File System (NTFS) in a same way that data is organized in the Flash memory;
wherein the master SSD controller updates logical records in the DRAM for data stored in the DRAM; and
wherein a majority of memory commands are handled by the master SSD controller using DRAM so as to reduce a number of writes to the Flash memory, the master controller is configured to independently determine when data should be transferred between the DRAM and the flash memory to reduce a number of write/erase cycles for the flash memory, the CPU not having direct access to the flash memory, the master SSD controller is configured to determine when to move data to or from the DRAM based on factors including lack of use of the data;
wherein when the FAT or NTFS table is requested from the SSD, the request is serviced from the DRAM which stores the FAT or NTFS table until power-down of the SSD.

US Pat. No. 10,796,761

TAILORING CURRENT MAGNITUDE AND DURATION DURING A PROGRAMMING PULSE FOR A MEMORY DEVICE

Intel Corporation, Santa...

1. A memory device, comprising:an array of memory cells; and
a memory controller comprising logic to:
receive a request to program a memory cell within the array of memory cells;
select a current magnitude and duration for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells; and
initiate the programming set pulse at the selected magnitude and duration.

US Pat. No. 10,796,760

DEVICES AND METHODS FOR WRITING TO A MEMORY CELL OF A MEMORY

Taiwan Semiconductor Manu...

1. A device for writing to a memory, comprising a current mirror circuit including a first transistor and a second transistor, a source current circuit, and a voltage-generating circuit; wherein:the first transistor has a gate terminal and a source/drain terminal that are both coupled to a memory cell of the memory through a source line of the memory;
the second transistor has a gate terminal coupled to the first transistor's gate terminal;
the second transistor has a source/drain terminal coupled to the current source circuit via a node;
the voltage-generating circuit is selectively coupled to the current mirror circuit based on a write detect voltage at the node; and
the voltage-generating circuit is configured to apply a write voltage to the memory through the current mirror circuit.

US Pat. No. 10,796,759

METHOD AND APPARATUS FOR READING RRAM CELL

Taiwan Semiconductor Manu...

1. A method of operating a resistive random access memory (RRAM) array, comprising:applying a word-line voltage to a selected word-line during a read operation;
applying a non-zero voltage to a selected bit-line during the read operation; and
applying a first voltage to a selected source-line during the read operation that is smaller than a second voltage applied to an unselected source-line during the read operation.

US Pat. No. 10,796,758

NON-VOLATILE MEMORY DEVICE WITH SWITCHABLE READING MODE AND RELATED READING METHOD

STMICROELECTRONICS S.R.L....

1. A memory device, comprising:a first sector and a second sector of an array of memory cells, wherein each of the first sector and the second sector is associated with a respective selector and a respective phase-change element configured to have a first value of resistance or a second value of resistance associated to corresponding logic data, wherein the first sector comprises:
a first top memory cell and a second top memory cell each coupled to a top wordline and, respectively, to a first top local bitline and a second top local bitline; and
a first top main bitline and a second top main bitline coupled, respectively, to the first top local bitline and the second top local bitline; and
wherein the second sector comprises:
a first bottom memory cell and a second bottom memory cell each coupled to a bottom wordline and, respectively, to a first bottom local bitline and a second bottom local bitline; and
a first bottom main bitline and a second bottom main bitline coupled, respectively, to the first bottom local bitline and the second bottom local bitline;
the memory device further comprising:
a controller and a reading circuit arranged between the first sector and the second sectors, the reading circuit comprising a top reading stage comprising a first top input node and a second top input node, and a bottom reading stage comprising a first bottom input node and a second bottom input node;
a top circuitry configured to be controlled so as to charge the first top input node and the second top input node and couple the first top input node and the second top input node respectively to the first top memory cell and the second top memory cell, respectively through the first top local bitline and the first top main bitline, and through the second top local bitline and the second top main bitline;
a bottom circuitry configured to be controlled so as to charge the first bottom input node and the second bottom input node and couple the first bottom input node and the second bottom input node respectively to the first bottom memory cell and the second bottom memory cell, respectively through the first bottom local bitline and the first bottom main bitline, and through the second bottom local bitline and the second bottom main bitline; and
a reference generator configured to be driven by the controller so as to couple to the first top input node or the second top input node to the first bottom input node or the second bottom input node.

US Pat. No. 10,796,757

SEMICONDUCTOR STORAGE DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device, comprising:a first plurality of interconnections in a first layer;
a second plurality of interconnections in a second layer;
a first plurality of memory cells connected between the first and second pluralities of interconnections and including:
a first memory cell with a first variable resistance element connected to a first interconnection in the first plurality and a first nonlinear element, the first nonlinear element being connected to a second interconnection in the second plurality;
a dummy memory cell with a second variable resistance element connected to the first interconnection and a second nonlinear element, the second nonlinear element being connected to a third interconnection in the second plurality; and
a controller configured to:
apply a first voltage of a first polarity to the first interconnection and a second voltage of a second polarity opposite the first polarity to the second interconnection at a first time point during a reading or writing operation on the plurality of memory cells,
apply a third voltage at a second time point after the first time point during the reading or writing operation to the first interconnection, the third voltage having a magnitude smaller than a magnitude of the first voltage, and
apply a fourth voltage to the third interconnection at the second time point during the reading or writing operation, the fourth voltage having a magnitude that is larger than the magnitude of the third voltage but smaller than the magnitude of the first voltage.

US Pat. No. 10,796,756

PERMUTATION CODING FOR IMPROVED MEMORY CELL OPERATIONS

Micron Technology, Inc., ...

1. An apparatus, comprising:an array of memory cells each programmable to a plurality of states;
a controller coupled to the array and configured to determine an encoded data pattern stored by a number of groups of memory cells, wherein each of the number of groups comprises:
a set of memory cells programmed to one of a plurality of different collective state permutations each corresponding to a permutation in which the cells of the set are each programmed to a different one of the plurality of states to which they are programmable, wherein the controller is configured to determine the encoded data pattern by, for each of the number of groups, determining the one of the plurality of different collective state permutations to which the respective set is programmed by direct comparison of threshold voltages of the cells of the set, and wherein the controller is further configured to determine relationships between voltages corresponding to the set of memory cells to perform the direct comparison.

US Pat. No. 10,796,755

PERMUTATION CODING FOR IMPROVED MEMORY CELL OPERATIONS

Micron Technology, Inc., ...

1. An apparatus, comprising:an array of memory cells each programmable to a plurality of states;
a controller coupled to the array and configured to determine an encoded data pattern stored by a number of groups of memory cells, wherein each of the number of groups comprises:
a set of memory cells programmed to one of a plurality of different collective state permutations each corresponding to a permutation in which the cells of the set are each programmed to a different one of the plurality of states to which they are programmable,
wherein the controller is configured to determine the encoded data pattern by, for each of the number of groups, determining the one of the plurality of different collective state permutations to which the respective set is programmed by direct comparison of threshold voltages of the cells of the set, and
wherein the set of memory cells of each of the number of groups comprises three cells each programmable to three distinct states.

US Pat. No. 10,796,754

SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM INCLUDING SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER

Toshiba Memory Corporatio...

1. A semiconductor storage device comprising:a plurality of memory cells, each of the plurality of memory cells being capable of storing data of n bits (n is an integer equal to or larger than 3);
a word line which is connected to the plurality of memory cells; and
a control circuitry including a latch circuitry, wherein the control circuitry is configured to:
in response to a first read request, perform a first read operation of reading first data out of the plurality of memory cells with a first voltage applied to the word line; and
in response to a second read request,
perform a second read operation of reading second data out of the plurality of memory cells with a second voltage within a first voltage range and a third voltage within a second voltage range applied to the word line, the first voltage range smaller than the first voltage, the second voltage range larger than the first voltage,
perform a first logical operation of logically processing the first data and the second data,
store third data generated by the first logical operation in the latch circuitry, and
output the third data stored in the latch circuitry.

US Pat. No. 10,796,753

METHOD AND SYSTEM TO DETERMINE QUICK PASS WRITE OPERATION IN INCREMENT STEP PULSE PROGRAMMING OPERATION

MACRONIX INTERNATIONAL CO...

1. A method for determining a quick pass write operation in an increment step pulse programming operation, the increment step pulse programming operation being applied to a plurality of memory cells of a memory cell array first, the quick pass write operation starting to adopt a quick pass write operation after a gate voltage reaches a pre-program-verify voltage less than a program-verify voltage, wherein a voltage difference value between the pre-program-verify voltage and the program-verify voltage is provided, the quick pass write operation is simultaneously applying a bit line voltage during the increment step pulse programming operation, and the method for determining the quick pass write operation comprises:according to a plurality of the bit line voltages varying in a first range and a plurality of the voltage difference values varying in a second range, estimating a shrinkage quantity of threshold voltage distribution width at the bit line voltage and the voltage difference value, so as to obtain a shrinkage-quantity topographic contour;
according to the bit line voltages and the voltage difference values, estimating a program shot number as needed to achieve the program-verify voltage by applying the increment step pulse programming operation, so as to obtain a program-shot-number topographic contour; and
after the shrinkage-quantity topographic contour and the program-shot-number topographic contour are overlapped, determining an operation region formed from an application range of the bit line voltage and an application range of the voltage difference value.

US Pat. No. 10,796,752

STATIC RANDOM ACCESS MEMORY CELL AND OPERATING METHOD THEREOF CAPABLE OF REDUCING LEAKAGE CURRENT

UNITED MICROELECTRONICS C...

8. A static random access memory (SRAM) cell comprising:first and second cross-coupled inverters, the first inverter having a first latch node and the second inverter having a second latch node;
a first write transistor coupled in series with a first wordline transistor between the first latch node of the first inverter and a first bitline; and
a first read transistor having a first terminal directly coupled to the first bitline, a second terminal coupled to a reference terminal, and a control terminal coupled to the second latch node of the second inverter.

US Pat. No. 10,796,751

STATE CHANGE DETECTION FOR TWO-TERMINAL MEMORY

CROSSBAR, INC., Santa Cl...

1. A memory device, comprising:a plurality of two-terminal memory cells, each coupled to a wordline, wherein a cell of the plurality of two-terminal memory cells comprises a first terminal coupled to the wordline and a second terminal coupled to a bitline; and
a detection circuit that, during application of an electrical stimulus configured to cause a change in state to the cell from a first defined state representing a first binary value to a second defined state representing a second binary value, detects the cell transitioning from the first defined state to the second defined state concurrent with the application of the electrical stimulus, wherein the detection circuit in part comprises:
a shared node electrically coupled to:
a cell current line that is connected to the bitline or to the wordline of the cell of the plurality of two-terminal memory cells, wherein a cell current Ic flowing through the cell is configured also to flow to the shared node by way of the cell current line,
a reference line having a reference current Ir generated by a reference current source that flows to the shared node from the reference line, and
a detect line that provides a detection current Id that flows to the shared node from a reference voltage on the detect line, and
a measurement node that has a first value that changes in response to a change in a second value of Id corresponding to the cell transitioning from the first defined state to the second defined state.

US Pat. No. 10,796,750

SEQUENTIAL READ MODE STATIC RANDOM ACCESS MEMORY (SRAM)

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the plurality of word lines active throughout the consecutive read operations,wherein the sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from the plurality of word lines in the array,
the sequential mode read controller comprises a set reset (SR) latch which receives a burst enable signal and an inverse set amplifier set signal and outputs a SR output signal to a multiplexer, and
the multiplexer receives the SR output signal and the burst enable signal and outputs a mux output signal to enable a path selector.

US Pat. No. 10,796,749

MEMORY DEVICE HAVING VARIABLE IMPEDANCE MEMORY CELLS AND TIME-TO-TRANSITION SENSING OF DATA STORED THEREIN

1. A circuit device comprising:a first transistor having a first electrode coupled to a first supply voltage, a control electrode coupled to an input signal, and a second electrode;
a second transistor having a first electrode coupled to the second electrode of the first transistor, a control electrode coupled to a control signal, and a second electrode coupled to a signal node, wherein an assertion of the control electrode of the second transistor causes a voltage on the signal node;
a delay element having:
an input coupled to the signal node, and
an output, wherein the delay element is configured to:
in response to an assertion of the control electrode of the second transistor, effect a voltage transition at a variable rate corresponding to a voltage of the input signal, and
determine a value of the input signal based upon a time-to-transition measurement of the output.

US Pat. No. 10,796,748

METHOD AND CIRCUIT DEVICE INCORPORATING TIME-TO-TRANSITION SIGNAL NODE SENSING

1. A memory device comprising:a memory cell having an impedance that varies in accordance with a respective data value stored therein;
a first signal line of the memory cell coupled to a time-to-discharge circuit; and the time-to discharge circuit configured to read the respective data value stored within the memory cell by:
measuring, at a first time, a first voltage value of a second signal line coupled to the first signal line;
measuring, at a second time, a second voltage value of the second signal line; and
determining the respective data value based on a difference between the first and second voltage values.

US Pat. No. 10,796,747

SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a soft repair control circuit configured to generate an enable signal, in response to a soft repair control signal, wherein the enable signal is enabled when first and second internal addresses counted in a refresh operation have the same combination as first and second failure addresses; and
a core circuit comprising first, second, third, and fourth regions each including a plurality of word lines which are activated based on a combination of the first, the second, third and fourth internal addresses, wherein the core circuit is configured to repair, in response to the enable signal, a word line in which a failure has occurred and which is included in a region selected among the first, second, third, and fourth regions by the third and fourth internal addresses.

US Pat. No. 10,796,746

FREQUENCY SYNTHESIS FOR MEMORY INPUT-OUTPUT OPERATIONS

Micron Technology, Inc., ...

1. A method of operating a memory device, the method comprising:receiving, at a mode register coupled to a memory channel, a training frequency used to synthesize a clock signal;
receiving at the memory channel a command to enter a training mode; and
receiving, by the memory channel, a training pattern associated with the training mode used to match a phase of the synthesized clock signal.

US Pat. No. 10,796,745

TEMPERATURE INFORMED MEMORY REFRESH

Micron Technology, Inc., ...

1. A memory system comprising:a memory component; and
a processing device, communicatively coupled to the memory component when in operation, the processing device performing operations comprising:
sorting, based on temperature data, a memory component element above other memory component elements in the memory component, the temperature data comprising a write temperature counter that is updated in response to a memory component write performed on the memory component element under an extreme temperature outside of a defined temperature window, the sorting comprising generating, based on at least the write temperature counter, a sort-value that is compared against one or more sort-values calculated for the other memory component elements; and
performing a refresh on the memory component element in response to the sorting.

US Pat. No. 10,796,744

CROSS-POINT MEMORY CELLS, NON-VOLATILE MEMORY ARRAYS, METHODS OF READING A MEMORY CELL, METHODS OF PROGRAMMING A MEMORY CELL, METHODS OF WRITING TO AND READING FROM A MEMORY CELL, AND COMPUTER SYSTEMS

Micron Technology, Inc., ...

1. A memory array comprising:a plurality of memory cells individually comprising a first electrode and a second electrode;
a plurality of bit lines coupled with the first electrodes of respective ones of the memory cells;
a plurality of word lines coupled with the second electrodes of respective ones of the memory cells; and
wherein the memory cells further individually comprise:
semiconductive material comprising a plurality of mobile dopants;
wherein the first and second electrodes of the individual memory cell are adjacent to the semiconductive material;
wherein the semiconductive material is configured to permit the mobile dopants to move to different locations within the semiconductive material to provide the individual memory cell with different capacitances corresponding to different programmed states of the individual memory cell at different moments in time; and
wherein the semiconductive material is configured to permit at least some of the mobile dopants to move from locations adjacent to one of the first and second electrodes of the individual memory cell when the individual memory cell is in one of the programmed states to locations which are spaced from the one of the first and second electrodes of the individual memory cell to provide the individual memory cell in another of the programmed states, wherein the individual memory cell has an increased capacitance in the another programmed state compared with the one programmed state.

US Pat. No. 10,796,743

DYNAMIC ADJUSTMENT OF MEMORY CELL DIGIT LINE CAPACITANCE

Micron Technology, Inc.

1. A method, comprising:coupling a first digit line of a first memory cell with a second digit line of a second memory cell;
applying a voltage to a plate line of the first memory cell during a period of time that the first digit line and the second digit line are coupled; and
isolating the first digit line from the second digit line based at least in part on applying the voltage to the plate line of the first memory cell.

US Pat. No. 10,796,742

CHARGE SHARING BETWEEN MEMORY CELL PLATES

Micron Technology, Inc., ...

1. A method, comprising:coupling a first memory cell with a second memory cell and a power supply for a period of time; and
transferring charge to the first memory cell from the second memory cell and the power supply during a portion of the period of time the first memory cell is coupled with the second memory cell and the power supply.

US Pat. No. 10,796,741

NON-VOLATILE MEMORY WITH A SELECT GATE REGULATOR CIRCUIT

NXP USA, Inc., Austin, T...

1. A memory comprising:a memory array of resistive memory cells, each resistive memory cell of the array including a select transistor and resistive memory element for storing a value;
a row decoder, the row decoder providing a plurality of word lines, wherein each select transistor of a resistive memory cell of the of the memory array is coupled to a word line of the plurality;
a word line regulator for providing a write word line voltage for an asserted word line during a write operation, wherein the word line regulator includes:
write replica circuit, the write replica circuit being a replica of a write path of the memory for writing a value to a memory cell in the write path from a low resistance value to a high resistance value of the resistive memory element of the memory cell;
a reference current path including a reference current source;
a regulator circuit including a first input coupled to a first node of the write replica circuit, a second input coupled to a second node of the reference current path, and an output to provide the write word line voltage;
wherein the word line regulator regulates the write word line voltage at a value during a write operation to a memory cell being written from a low resistance value to a high resistance value such that the select transistor of the memory cell is used as a source follower to regulate a first node of a resistive element of the memory cell being written wherein the first node is at a higher write voltage than a second node of the resistive element during the write operation, wherein the first node is located in a write path between the select transistor and the second node of the resistive element of the memory cell.

US Pat. No. 10,796,740

METHOD FOR GENERATING COMMAND PULSES AND SEMICONDUCTOR DEVICE CONFIGURED TO PERFORM THE METHOD

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a first command pulse generation circuit configured to generate a first command pulse from an internal command address based on a first blocking signal; and
a second command pulse generation circuit configured to generate a second command pulse from the internal command address based on a second blocking signal;
a first blocking signal generation circuit configured to generate the second blocking signal based on a first latched command address and the first blocking signal that is outputted from a second blocking signal generation circuit,
wherein the first blocking signal or the second blocking signal is activated when the first command pulse and the second command pulse are generated from a command inputted during a period of at least N number of cycles of a clock, and
wherein N is an integer.

US Pat. No. 10,796,738

PRIORITY BASED BACKUP IN NONVOLATILE LOGIC ARRAYS

TEXAS INSTRUMENTS INCORPO...

1. A computing device comprising:a non-volatile logic element array;
a volatile storage element configured to store data associated with a machine state of the computing device, wherein the volatile storage element includes:
a flip-flop having a first data input, a second data input, a clock input, and an output;
a master latch having an input and an output, the input of the master latch coupled to the first data input of the flip-flop; and
a slave latch having a first input, a second input, a third input, and a fourth input, the first input coupled to the output of the master latch, the second input coupled to the second data input of the flip-flop, the third input coupled to the clock input of the flip-flop, and a fourth input coupled to an inverse of the clock input of the flip-flop;
a controller coupled to the non-volatile logic element array and volatile storage element, the controller configured to:
identify a portion of data on the volatile storage element for use in a test mode; and
store the identified portion of data in the non-volatile logic element array.

US Pat. No. 10,796,737

SEMICONDUCTOR APPARATUS CAPABLE OF SYNCHRONIZING COMMAND SIGNAL AND CLOCK SIGNAL, AND OPERATION METHOD THEREOF

SK hynix Inc., Icheon-si...

1. A semiconductor apparatus comprising:a clock path configured to generate a delay clock signal by delaying a clock signal;
a command path configured to generate an output command signal from one of a command signal and the clock signal, based on a monitoring signal;
a delay monitoring circuit configured to generate a delay control signal and a latency control signal based on a phase difference between the delay clock signal and the output command signal, when the monitoring signal is enabled; and
an output control circuit configured to generate an output enable signal by synchronizing the output command signal with the delay clock signal, based on the latency control signal.

US Pat. No. 10,796,736

BANK TO BANK DATA TRANSFER

Micron Technology, Inc., ...

1. An apparatus, comprising:a bank-to-bank transfer (BBT) bus coupled to a plurality of banks of memory cells; and
a controller coupled to the BBT bus and configured to:
determine a shortest transfer time for transfer of data between the plurality of banks; and
control transfer of data between the plurality of banks based on the determination.

US Pat. No. 10,796,735

READ TRACKING SCHEME FOR A MEMORY DEVICE

QUALCOMM Incorporated, S...

1. A memory device, comprising:memory bit cells coupled to a read bit line;
a first sense amplifier having a first input coupled to the read bit line, a first output, a second input, and a second output, wherein the first sense amplifier is configured to
pre-charge the read bit line when the first sense amplifier is enabled by a sense enable signal, and
output a data voltage at the first output of the first sense amplifier based on a voltage of the read bit line;
a latch amplifier having a first input coupled to the first output of the first sense amplifier, a second input coupled to the second output of the first sense amplifier, an enable input, and an output;
one or more dummy bit cells coupled to a dummy bit line;
a second sense amplifier having a first input coupled to the dummy bit line, and an output;
a trigger circuit having an input coupled to the output of the second sense amplifier, and an output coupled to the enable input of the latch amplifier;
a sense enable circuit coupled to an enable input of the first sense amplifier, wherein the sense enable circuit is configured to output the sense enable signal to the enable input of the first sense amplifier when one of the memory bit cells is selected during a read operation; and
a reference resistor coupled between the second input of the first sense amplifier and a ground, wherein the first sense amplifier is configured to output a reference voltage at the second output based on the reference resistor.

US Pat. No. 10,796,734

APPARATUSES INCLUDING TEMPERATURE-BASED THRESHOLD VOLTAGE COMPENSATED SENSE AMPLIFIERS AND METHODS FOR COMPENSATING SAME

Micron Technology, Inc., ...

1. An apparatus, comprising:a switch configured to couple a plurality of inputs that are each associated with a compensation code to a plurality of outputs that are each associated with a temperature selectable compensation code, wherein the switch is operable responsive to control signaling from the apparatus;
a first multiplexer coupled to the plurality of outputs of the switch to receive the temperature selectable compensation codes and configured to select a compensation code responsive to a temperature range signal indicating an operating temperature of the apparatus; and
a sense amplifier control circuit coupled to the first multiplexer and at least one sense amplifier and configured to provide a compensation pulse to the sense amplifier responsive to the selected compensation code to cause the sense amplifier to perform a voltage compensation during a width of the compensation pulse.

US Pat. No. 10,796,733

APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

Micron Technology, Inc., ...

1. A system, comprising:a host configured to generate instructions; and
a memory device comprising an array of memory cells coupled to sensing circuitry comprising a first latch and a second latch, wherein the memory device is configured to:
receive an instruction from the host; and
execute the instruction to perform at least one of a NAND operation or an AND operation using data values stored in the array as inputs by controlling the sensing circuitry without transferring the data values externally from the memory device.

US Pat. No. 10,796,732

SEMICONDUCTOR STORAGE DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device comprising:a first word line electrically connected to a first memory cell;
a second word line electrically connected to a second memory cell; and
a voltage generation circuit configured to supply a first voltage to a first line electrically connected to the first word line and to supply a second voltage to a second line electrically connected to the second word line,
wherein the voltage generation circuit includes
a first regulator configured to output the first voltage to the first line and output a first signal according to the first voltage,
a second regulator configured to output the second voltage to the second line and output a second signal according to the second voltage, and
a switch circuit configured to open or close an electrically conductive path between the first line and the second line, based on at least one of the first signal and the second signal.

US Pat. No. 10,796,731

PROVIDING POWER AVAILABILITY INFORMATION TO MEMORY

Micron Technology, Inc., ...

1. A method, comprising:receiving, from a host at a memory device, first signaling that indicates through a configuration register of the memory device that the host will keep power active at the memory device to support a present operating condition of the memory device; and
operating the memory device in the present operating condition for an amount of time that is based at least in part on second signaling from the host that indicates the memory device will cease to receive power, wherein the amount of time is an unlimited amount of time, a first amount of time that is less than the unlimited amount of time, a second amount of time that is less than the first amount of time, or a third amount of time that is less than the second amount of time.

US Pat. No. 10,796,730

SEMICONDUCTOR MEMORY DEVICE AND WORD-LINE ACTIVATION METHOD

Elite Semiconductor Memor...

1. A semiconductor memory device, comprising:a memory bank of an open bit-line architecture, being divided into a plurality of memory blocks in a bit-line direction, wherein each of the memory blocks comprises a plurality of word lines, a plurality of bit lines and a plurality of memory cells which are grouped into a plurality of memory sections including two edge memory sections and at least one non-edge memory section; and
a word-line decoder coupled with the memory bank and configured to:
generate a plurality of word-line enabling signals based on a plurality of address signals; and
activate one of the word lines for each of the two edge memory sections of one of the memory blocks and one of the word lines for one of the at least one non-edge memory section of each of the other memory blocks concurrently in an active mode according to the word-line enabling signals.

US Pat. No. 10,796,729

DYNAMIC ALLOCATION OF A CAPACITIVE COMPONENT IN A MEMORY DEVICE

Micron Technology, Inc., ...

1. A method, comprising:transferring, by a voltage rail isolated from a capacitive component, a voltage to an array of memory cells;
identifying an operating condition associated with the voltage rail;
coupling the capacitive component with the voltage rail based at least in part on identifying the operating condition, the capacitive component for maintaining the voltage on the voltage rail for at least a portion of an access operation of the array of memory cells; and
transferring, by the voltage rail coupled with the capacitive component, the voltage to the array of memory cells.

US Pat. No. 10,796,728

WIRING WITH EXTERNAL TERMINAL

Micron Technology, Inc., ...

8. An apparatus comprising:a clock transmission circuit including a signal wire, the signal wire including:
a first portion extending in a first direction and having a first end and a second end, and further having a first impedance from the first end to the second end; and
a second portion extending in the first direction apart from the first portion and having a first end and a second end, and further having a second impedance from the first end to the second end that is lower than the first impedance,
wherein the signal wire is configured to receive a signal at the first ends of the first and second portions, and
wherein the second end of the first portion is coupled to the second end of the second portion.

US Pat. No. 10,796,727

USING SOLID STATE DEPOSITION IN THE MANUFACTURE OF DATA STORAGE DEVICES, AND RELATED DEVICES AND COMPONENTS THEREOF

Seagate Technology LLC, ...

1. A method of joining a first data storage device component and a second data storage device component, wherein the method comprises:a) providing the first data storage device component, wherein the first data storage device component comprises a first metallic substrate;
b) providing the second data storage device component, wherein the second data storage device component comprises a second metallic substrate;
c) applying at least one solid-state, metallic deposition layer over at least a portion of one or more surfaces of the first metallic substrate and/or at least a portion of one or more surfaces of the second metallic substrate;
d) aligning at least a portion of the first metallic substrate and at least a portion of the second metallic substrate along a joint line, wherein at least a portion of the at least one solid-state, metallic deposition layer is along at least a portion of the joint line; and
e) welding the first metallic substrate to the second metallic substrate along the joint line.

US Pat. No. 10,796,726

VIDEO RECORDING METHOD AND APPARATUS FOR MOBILE TERMINAL

TENCENT TECHNOLOGY (SHENZ...

1. A video recording method of a mobile terminal, the method comprising:obtaining a target video that is played online;
controlling to display a video recording page in which the target video is played, the video recording page comprising a record key;
receiving, via the video recording page that is displayed, a recording instruction for recording the target video, the recording instruction produced by pressing the record key
in response to the recording instruction being received:
controlling to display, on the video recording page, a first prompt prompting the pressing of the record key for more than a predetermined period of time; and
entering a recording mode to record the target video to obtain a first video clip corresponding to video data of the target video; and
generating a recorded video of the target video, based on the first video clip.

US Pat. No. 10,796,725

DEVICE, SYSTEM AND METHOD FOR DETERMINING INCIDENT OBJECTS IN SECONDARY VIDEO

MOTOROLA SOLUTIONS, INC.,...

1. A method comprising:playing, using a controller of an electronic device, at a display screen, a primary video from a primary video source located at a primary location;
determining, using the controller, an incident type associated with the primary video;
determining, using the controller, one or more incident objects associated with the incident type;
detecting, using the controller, a particular incident object, of the one or more incident objects, in a secondary video from a secondary video source located at a secondary location within a threshold distance of the primary location, the particular incident object appearing in the secondary video within a threshold time period from a current playback time of the primary video;
determining, using the controller, a relative direction of a location of the particular incident object from the primary location;
controlling, using the controller, the display screen to render a particular visual indicator of the particular incident object over or adjacent the primary video at a position indicative of the relative direction; and
while playing the primary video at the display screen, one or more of:
tracking movement of the particular incident object in the secondary video as a function of time of the secondary video synchronized with the playing of the primary video; and modifying the position of the particular visual indicator in the primary video with the movement of the particular incident object in the secondary video; and
determining, at a time synchronized with the playing of the primary video, that the particular incident object no longer appears in the secondary video; and responsively removing the particular visual indicator from over or adjacent the primary video.

US Pat. No. 10,796,724

MAGNETIC RECORDING MEDIUM

Sony Corporation, Tokyo ...

1. A magnetic recording medium comprising:an average thickness tT satisfies tT?5.5 ?m, and
a dimensional change amount ?w in a width direction of the magnetic recording medium with respect to a tension change in a longitudinal direction of the magnetic recording medium satisfies 700 ppm/N??w.

US Pat. No. 10,796,723

SPATIALIZED RENDERING OF REAL-TIME VIDEO DATA TO 3D SPACE

Immersive Licensing, Inc....

1. A video processing system comprising:a video capture device that receives a video fill and a video key, the video capture device combining the video fill and video key into a video texture;
a model mapper that selects a first three dimensional (3D) model from a plurality of 3D models for mapping into a 360 degree video space;
a compositor that places the video texture over an instance of the first 3D model to generate a first group;
a virtual reality workspace editor that, responsive to an instruction, orients the first group by azimuth and elevation into the 360 degree video space and places the first group at a relative depth in the 360 degree video space; and
an output that transmits an output signal including the first group mapped into the 360 degree video space.

US Pat. No. 10,796,722

METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DISTRIBUTED VIDEO EDITING

Open Text SA ULC, Halifa...

1. A system of distributed non-linear video editing, comprising:a processor; and
a non-transitory computer readable medium storing instructions translatable by the processor for:
receiving a video;
obtaining a plurality of frames of the video, the plurality of frames corresponding to moving image data over time;
generating, for each frame in the plurality of frames, a textured frame representation for that frame and sequencing the textured frame representations generated for the plurality of frames to create a sequence of textured frame representations representing to the plurality of frames;
storing the sequence of textured frame representations as a texture strip, the texture strip comprising the sequence of textured frame representations corresponding to the plurality of frames of the video formatted as a single still image;
sending the texture strip to a client device;
receiving an edit command from the client device, the edit command associated with a selected frame identified by a location expressed relative to the texture strip;
applying the edit command based on the selected frame to generate an edited video; and
sending a representation of the edited video to the client device.

US Pat. No. 10,796,721

ADVANCED AIR BEARING SLIDER

Seagate Technology LLC, ...

1. An apparatus comprising a transducing head mounted to a slider, the slider suspended above a magnetic data storage medium, the slider having a variable depth region continuously contacting a central rail wall from a first wall to a trailing edge wall, the variable depth region comprising a floor region and a curvilinear region, the floor region defined by a linear surface, the curvilinear region defined by a first continuously curvilinear surface contacting a second continuously curvilinear surface, the first continuously curvilinear surface having a first variable depth continuously extending to greater than a uniform depth from an air bearing surface, the second continuously curvilinear surface having a second variable depth continuously extending to less than the uniform depth.

US Pat. No. 10,796,720

DISC DEVICE

PANASONIC INTELLECTUAL PR...

1. A disc device comprising:a disc tray which stores a plurality of stacked discs;
a tray carrier which transports the disc tray; and
a disc selector which supplies one disc of the plurality of discs stacked on the disc tray to a drive unit,
wherein the disc selector includes
a disc selector spindle that supports the plurality of discs,
a disc press on which an upper surface of an uppermost disc of the plurality of discs supported by the disc selector spindle abuts,
a displacement amount detection mechanism that detects a displacement amount of the disc press displaced according to thicknesses of the plurality of supported discs, and
a thickness detection unit that detects a thickness of each of the plurality of discs based on the detected displacement amount of the disc press.

US Pat. No. 10,796,719

HEAT-ASSISTED MAGNETIC RECORDING (HAMR) MEDIUM WITH MULTILAYERED OVERCOAT

Western Digital Technolog...

1. A heat-assisted magnetic recording medium comprising:a substrate;
a heat-sink layer on the substrate;
a magnetic recording layer comprising a substantially chemically-ordered alloy selected from a FePt alloy and a CoPt alloy on the heat-sink layer;
a multilayered non-magnetic overcoat comprising an interface layer selected from DLC, an oxide and a nitride on the recording layer, a heat-dissipation layer on and in contact with the interface layer, and a diamond-like carbon (DLC) layer on and in contact with the heat-dissipation layer, the heat-dissipation layer consisting essentially of one or more metals and their alloys and having an in-plane thermal conductivity greater than the in-plane thermal conductivity of DLC, and
wherein the interface layer has thermal conductivity less than the thermal conductivity of the heat-dissipation layer.

US Pat. No. 10,796,718

MAGNETIC RECORDING APPARATUS HAVING CIRCUITS WITH DIFFERING TUNNEL VALVE SENSORS AND ABOUT THE SAME RESISTANCE

International Business Ma...

1. An apparatus, comprising:a first circuit electrically coupled to a first read transducer and a first parallel circuit, the first read transducer having a tunnel valve structure having a resistance; and
a second circuit electrically coupled to a second read transducer having a tunnel valve structure,
wherein an area of a tunnel barrier portion of the second read transducer along a plane of deposition thereof is larger than an area of a tunnel barrier portion of the first read transducer along a plane of deposition thereof,
wherein a resistance of the second circuit is different than a resistance of the first circuit.

US Pat. No. 10,796,717

PERPENDICULAR MAGNETIC RECORDING WRITE HEAD WITH HEATER AND HEAT SINK FOR PROVIDING TEMPERATURE GRADIENT ACROSS THE MAIN POLE

Western Digital Technolog...

1. A perpendicular magnetic recording write head for magnetizing regions of a magnetic recording layer comprising:a substrate;
a main pole of ferromagnetic material on the substrate and having a pole tip, the pole tip having an end for facing the recording layer;
heat sink material between the substrate and the main pole;
a layer of electrically conductive heater material having a first portion overlaying the main pole and a second portion in contact with the pole tip; and
a layer of electrically insulating material between the first portion of heater material and the main pole.

US Pat. No. 10,796,716

USER PRESENCE DETECTION

AMAZON TECHNOLOGIES, INC....

1. A computer-implemented method, comprising:determining first data corresponding to audio detected by at least one microphone of a first device;
processing the first data with a wakeword detection component;
determining, using the wakeword detection component, that the first data does not include a representation of a wakeword;
processing the first data with a presence detection component;
determining, using the presence detection component, that the first data indicates an occurrence of human footsteps in a vicinity of the first device; and
performing at least one action based at least in part on determining that the first data indicates the occurrence of human footsteps in the vicinity of the first device.

US Pat. No. 10,796,715

SPEECH ANALYSIS ALGORITHMIC SYSTEM AND METHOD FOR OBJECTIVE EVALUATION AND/OR DISEASE DETECTION

ARIZONA BOARD OF REGENTS ...

1. A method for evaluating speech in a system involving processor circuitry, the method comprising:selecting, by the processor circuitry, a subset of two or more laboratory-implemented features of a plurality of laboratory-implemented features from a data matrix that includes (i) the plurality of laboratory-implemented features, wherein said plurality of laboratory-implemented features is extracted from a plurality of patient speech samples, and (ii) a plurality of subjective expert ratings corresponding to the plurality of patient speech samples and involving evaluations on a multi-point scale for a plurality of perceptual dimensions including two or more of nasality, prosody, articulatory precision, vocal quality, and severity; wherein the subset of two or more laboratory-implemented features is useful for predicting the plurality of perceptual dimensions; and wherein the plurality of laboratory-implemented features comprises an envelope modulation spectrum, a long-term average spectrum, spatio-temporal features, and dysphonia features; and
utilizing, by the processor circuitry, the subset of two or more laboratory-implemented features to generate and/or update a predictive software model configured to receive at least one additional patient speech sample and to perform at least one of the following items (a) or (b): (a) generating an objective evaluation of the plurality of perceptual dimensions utilizing the at least one additional patient speech sample; or (b) evaluating at least one of disease onset, disease progression, or disease treatment efficacy for a condition involving dysarthria as a symptom, utilizing the at least one additional patient speech sample.

US Pat. No. 10,796,714

METHOD AND SYSTEM FOR DIAGNOSING CORONARY ARTERY DISEASE (CAD) USING A VOICE SIGNAL

VOCALIS HEALTH LTD., Tel...

1. A computer-implemented method for diagnosing a patient, comprising:a. receiving voice signal data indicative of speech from the patient;
b. segmenting the voice signal data into frames of 32 ms with a frame shift of 10 ms;
c. computing Mel Frequency Cepstral Coefficients (MFCC);
d. applying various statistical feature extraction operators upon the MFCC time series and;
e. determining an existence of at least one coronary artery disease symptom associated with the patient;
wherein an existence of at least one coronary artery disease symptom associated with the patient is determined based at least in part upon the ratio of intensity between at least two frequency bands found in the Cepstral representation and/or its statistical properties.

US Pat. No. 10,796,713

IDENTIFICATION OF NOISE SIGNAL FOR VOICE DENOISING DEVICE

Alibaba Group Holding Lim...

1. A computer-implemented method for voice denoising, the method being executed by one or more processors and comprising:performing, by the one or more processors, a mathematical transform on each frame signal in an audio signal segment comprising a plurality of frame signals to generate a plurality of power spectra, each power spectrum of the plurality of power spectra corresponding to a respective frame signal;
determining, by the one or more processors, a plurality of power value variances, each power value variance of the plurality of power value variances corresponding to the respective frame signal by classifying power values of each frame signal at various frequencies into a first power value variance corresponding to a first frequency interval and a second power value variance corresponding to a second frequency interval;
generating, by the one or more processors, a ranking of the plurality of frame signals in the audio signal segment according to magnitudes of the plurality of power value variances by determining for each frame signal of the plurality of frame signals:
whether a first condition is satisfied, the first condition comprising the first power value variance being greater than a first threshold,
whether a second condition is satisfied, the second condition comprising the second power value variance being greater than a second threshold,
whether a third condition is satisfied, the third condition comprising a difference between the second power value variance at the respective frame signal and the second power value variance at a subsequent frame signal being greater than a third threshold, and
whether a fourth condition is satisfied, the fourth condition comprising a difference between the second power value variance and the first power value variance is greater than a fourth threshold;
in response to determining that at least one of the first condition, the second condition, the third condition and the fourth condition fails to be satisfied, identifying, by the one or more processors, a noise signal in the respective frame signal of the plurality of frame signals based on the ranking of the plurality of frame signals in the audio signal segment; and
removing, by the one or more processors, the noise signal from the respective frame signal of the plurality of frame signals from the audio signal segment.

US Pat. No. 10,796,712

METHOD AND APPARATUS FOR DETECTING A VOICE ACTIVITY IN AN INPUT AUDIO SIGNAL

HUAWEI TECHNOLOGIES CO., ...

1. An audio signal encoding method used by a signal processing apparatus comprising a processor and a memory, the method comprising:obtaining a frame of an audio signal, wherein the frame comprises a plurality of sub-bands;
determining a long term signal to noise ratio of the audio signal;
calculating a sub-band specific parameter (sbsp) of each sub-band using an adaptive function, wherein the sbsp of the ith sub-band sbsp(i) is calculated as follows:
sbsp(i)=(f(snr(i))+?)?
where i is a sub-band index of the ith sub-band, snr(i) is a signal to noise ratio of the ith sub-band, (f(snr(i))+?)? is the adaptive function, ? is determined based on the sub-band index i and the long term signal to noise ratio of the audio signal, and ? is a configurable variable;
obtaining a modified segmental signal to noise ratio (mssnr) by summing up the calculated sbsp of each sub-band;
comparing the mssnr with a threshold value (thr) to provide a voice activity detection decision (VADD), wherein the VADD is used to indicate that a voice activity is present or absent in the frame of the audio signal; and
encoding the audio signal based on the VADD.

US Pat. No. 10,796,711

SYSTEM AND METHOD FOR DYNAMIC OPTICAL MICROPHONE

HONDA MOTOR CO., LTD., T...

1. A system for receiving a voice signal, comprising:an acoustic microphone;
a laser microphone;
a depth sensor;
a camera; and
a processor communicatively coupled to the acoustic microphone, laser microphone, depth sensor, camera, and a memory storing computer executable instructions, wherein the processor:
determines, a direction to a human speaker;
directs a laser beam emitted from the laser microphone at a voice box of the human speaker;
determines a distance to the human speaker using the depth sensor;
adjusts an intensity of the laser beam emitted from the laser microphone based on the distance to the human speaker determined by the depth sensor;
receives optical feedback from the laser beam striking the human speaker; and
isolates a voice signal through the optical feedback from the laser microphone from background noise in an audio signal received by the acoustic microphone.

US Pat. No. 10,796,710

NOISE ELIMINATION DEVICE, NOISE ELIMINATION METHOD, AND NOISE ELIMINATION PROGRAM

JVCKENWOOD Corporation, ...

1. A noise elimination device comprising:a first converter configured to convert an input signal input from a microphone into digital data to generate input digital data;
a second converter configured to convert an internal noise signal into digital data; and
a signal processing unit configured to
use, as reference data, digital data corresponding to an output signal output to a speaker and digital data having been converted by the second converter, and
eliminate a component corresponding to the reference data from the input digital data.

US Pat. No. 10,796,709

ACOUSTIC ECHO CANCELLATION BYPASS

Microsoft Technology Lice...

1. A computing device comprising:a sound processing device configured to output sound output frames via a sound output device and capture sound input frames via a sound input device;
a processor configured to:
render a stream of sound output frames based on at least sound output data received from a remote computing device over a computer network;
provide reference frames for each of the sound output frames to a reference frame buffer of an acoustic echo cancellation module;
provide the stream of sound output frames to the sound processing device for output via the sound output device;
receive a stream of sound input frames from the sound processing device;
process the stream of sound input frames via the acoustic echo cancellation module by performing acoustic echo cancellation on each sound input frame using a corresponding reference frame from the reference frame buffer selected based on an estimated echo path delay;
send the processed stream of sound input frames to the remote computing device over the computer network;
detect a stall in a sound rendering process performed by the computing device that provides reference frames for rendered sound output frames to the reference frame buffer; and
responsive to detecting the stall in the sound rendering process, suppress the acoustic echo cancellation module and send the stream of sound input frames to the remote computing device without being processed by the acoustic echo cancellation module.

US Pat. No. 10,796,708

METHOD FOR ELIMINATING SOUND AND ELECTRONIC DEVICE PERFORMING THE SAME

UNLIMITER MFA CO., LTD., ...

4. An electronic device, which is capable of connecting with a sound playback device, comprising:a microphone, used for receiving a first input sound to acquire a first input sound signal;
a microcontroller, electrically connected with the microphone, comprising:
a control module, used for recording the first input sound signal, and for controlling the first input sound signal to be transmitted to the sound playback device; the microphone being further used for receiving a second input sound from the sound playback device to acquire a second input sound signal after the first input sound signal is transmitted, wherein the second input sound is generated by the sound playback device according to the first input sound signal;
a calculation module, used for determining a difference in generation times between the first input sound signal and the second input sound signal by recording passed time from receiving the first input sound signal to acquiring the second input sound signal; and
a filter module, used for filtering the second input sound signal according to the difference in generation times and the first input sound signal.

US Pat. No. 10,796,707

METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING OF THE OBJECT-BASED AUDIO CONTENTS

ELECTRONICS AND TELECOMMU...

1. A method of transmitting object-based audio contents comprising:identifying a plurality of elementary stream related to an object;
packetizing the plurality of elementary stream using a PID (packet identification);
generating an object-based audio contents including the packetized elementary stream,
wherein the object-based audio contents include common information related to the object,
wherein the common information includes at least one of a length of packet and a type of the elementary streams related to the elementary streams,
wherein the object-based audio contents include 3D information of the object represented in a 3D coordinate axis (X, Y, and Z), and a volume of the object.

US Pat. No. 10,796,706

METHODS AND APPARATUS FOR RECONSTRUCTING AUDIO SIGNALS WITH DECORRELATION AND DIFFERENTIALLY CODED PARAMETERS

Dolby Laboratories Licens...

1. A method performed in an audio decoder for reconstructing N audio channels from an audio signal having M audio channels, the method comprising:receiving a bitstream containing the M audio channels and a set of spatial parameters, wherein the set of spatial parameters includes an amplitude parameter and a correlation parameter, wherein the correlation parameter is differentially encoded across frequency;decoding the M encoded audio channels;decoding the M encoded audio channels, wherein each audio channel is divided into a plurality of frequency bands, and each frequency band includes one or more spectral components;
extracting the set of spatial parameters from the bitstream;
applying a differential decoding process across frequency to the differentially encoded correlation parameter to obtain a differentially decoded correlation parameter
analyzing the M audio channels to detect a location of a transient, wherein the location of the transient is detected based on a filtering operation;
decorrelating the M audio channels to obtain a decorrelated version of the M audio channels, wherein a first decorrelation technique is applied to a first subset of the plurality of frequency bands of each audio channel and a second decorrelation technique is applied to a second subset of the plurality of frequency bands of each audio channel;
deriving N audio channels from the M audio channels, the decorrelated version of the M audio channels, and the set of spatial parameters, wherein N is two or more, M is one or more, and M is less than N; and
synthesizing, by an audio reproduction device, the N audio channels as an output audio signal,
wherein both the analyzing and the decorrelating are performed in a frequency domain, the first decorrelation technique represents a first mode of operation of a decorrelator, the second decorrelation technique represents a second mode of operation of the decorrelator, and the audio decoder is implemented at least in part in hardware.

US Pat. No. 10,796,705

CODING AND DECODING OF SPECTRAL PEAK POSITIONS

Telefonaktiebolaget LM Er...

1. A method for coding of spectral peak positions of an audio signal segment, the method comprising:performing, using a coder circuit, operations comprising:
determining which one out of two lossless spectral peak position coding schemes that requires the least number of bits to code the spectral peak positions of the audio signal segment, wherein the determining is based on a maximum distance dmax between two spectral peaks in the audio signal segment and/or on comparing the number of bits required for the respective scheme after coding of the audio signal segment using the two schemes, wherein a first one of the two lossless spectral peak position coding schemes is more efficient than a second one of the two lossless spectral peak position coding schemes for periodic or semi-periodic spectral peak position distributions; and wherein the second one of the two lossless spectral peak position coding schemes is more efficient than the first one of the two lossless spectral peak position coding schemes for sparse spectral peak position distributions and comprises:
dividing a bit vector representing the spectral peak positions into consecutive equal size bit groups with each non-zero bit representing presence of a spectral peak and each zero bit indicating absence of a spectral peak;
OR-ing the bits in each bit group to form a group bit vector;
compressing non-zero bit groups by exploiting constraints in the minimum allowed distance between two consecutive spectral peaks; and
providing the group bit vector and the compressed non-zero bit groups as an output of the second one of the two spectral peak position coding schemes;
selecting the spectral peak position coding scheme that requires the least number of bits to code the spectral peak positions of the audio signal segment; and
communicating an indication of the selected spectral peak position coding scheme to a radio transmitter circuit to transmit the indication of the selected spectral peak position coding scheme toward a decoder to enable the decoder to decode coded spectral peak positions of the audio signal segment based on the indication of the selected spectral peak position coding scheme.

US Pat. No. 10,796,703

AUDIO ENCODER WITH SELECTABLE L/R OR M/S CODING

Dolby International AB, ...

1. An encoder system configured for encoding a stereo signal having a left channel and a right channel to a bitstream signal, the encoder system comprising one or more processing elements configured for:generating a downmix signal and a residual signal based on the stereo signal, wherein the downmix signal is a mid (M) signal and the residual signal is a side (S) signal;
determining one or more stereo parameters describing a perceptual stereo image of the stereo signal;
perceptual encoding downstream of the generating, wherein the perceptual encoding is configured for selecting in a time variant manner either:
a left/right perceptual encoding scheme or
a mid/side perceptual encoding scheme; and
deactivating the determining when left/right perceptual encoding codes the stereo signal more efficiently than mid/side perceptual encoding;
wherein the bitstream signal includes information indicating the selected encoding scheme.

US Pat. No. 10,796,702

METHOD AND SYSTEM FOR CONTROLLING HOME ASSISTANT DEVICES

MIDEA GROUP CO., LTD., F...

1. A method of controlling a home assistant device, comprising:at a computing system having one or more processors and memory:
receiving an audio input;
performing speaker recognition on the audio input;
in accordance with a determination from performing speaker recognition that the audio input includes a voice input from a first user that is authorized to control the home assistant device:
performing, using speech recognition, speech-to-text conversion on the audio input to obtain a textual string;
searching for a predefined trigger word for activating the home assistant device in the textual string;
selecting, from a plurality of task domains of the home assistant device, one or more first task domains that the first user is authorized to control, to perform intent deduction on the textual string; and
forgoing using one or more second task domains among the plurality of task domains that the first user is not authorized to control to process the textual string; and
in accordance with a determination from performing speaker recognition that the audio input includes a voice input from the home assistant device:
forgoing performance of speech-to-text conversion on the audio input; and
forgoing search for the predefined trigger word, so that the home assistant device avoids being triggered by the home assistant device's own speech or a speech output of a neighboring home assistant device,
wherein the speaker recognition uses less resources than the speech recognition.

US Pat. No. 10,796,701

OPERATOR ASSESSMENT SYSTEM

SHARP KABUSHIKI KAISHA, ...

1. A presumable operator determining system which determines a presumable operator who is presumably an operator who has operated an electrical apparatus provided in a house, comprising:a storage section storing therein unique information of respective communication terminal devices such that the unique information are respectively associated with users who operate the electrical apparatus, the communication terminal devices being respectively carried by the users and brought along by the users when the users go out; and
a presumable operator determining section configured to, in a case where the electrical apparatus is operated, (i) conduct a search, with use of a communication section included in the electrical apparatus, for a communication terminal device which is determinable as presumably being present in the house among the communication terminal devices whose unique information are stored in the storage section and (ii) determine a presumable operator who is presumably an operator who has operated the electrical apparatus from among a user(s) associated with at least one terminal device detected through the search.

US Pat. No. 10,796,700

ARTIFICIAL INTELLIGENCE-BASED CROSS-LANGUAGE SPEECH TRANSCRIPTION METHOD AND APPARATUS, DEVICE AND READABLE MEDIUM USING FBANK40 ACOUSTIC FEATURE FORMAT

BAIDU ONLINE NETWORK TECH...

1. An artificial intelligence-based cross-language speech transcription method, wherein the method comprises:pre-processing to-be-transcribed speech data to obtain multiple acoustic features in Fbank40 format, the to-be-transcribed speech data being represented in a first language; and
predicting a corresponding translation text after transcription of the speech data according to the multiple acoustic features and a pre-trained cross-language transcription model; wherein the translation text is represented in a second language which is different from the first language,
wherein before predicting a corresponding translation text after transcription of the speech data according to the multiple acoustic features and the pre-trained cross-language transcription model, the method further comprises:
collecting, from a network, tens of thousands of items of training speech data represented in the first language and real translation texts transcribed from said tens of thousands of items of training speech data and represented in the second language; and
training, in a manner of deep learning, the cross-language transcription model by using said items of training speech data and corresponding real translation texts.

US Pat. No. 10,796,699

METHOD, APPARATUS, AND COMPUTING DEVICE FOR REVISION OF SPEECH RECOGNITION RESULTS

Guangzhou Shenma Mobile I...

1. An information input method, comprising:receiving a voice input of a user;
sending the received voice input to a server;
displaying an animation having a continuous refresh rate while the server determines, based on a speech recognition model, recognition results on the received voice input;
acquiring, from the server, a list of the recognition results;
in response to the list of the recognition results being acquired, hiding the animation and replacing the animation with a display of the list of the recognition results;
providing an interface to revise a recognition result in the list of the acquired recognition results, the providing the interface comprising:
in response to the user single clicking, double clicking, or hovering over an editing mode logo for the recognition result, sliding, for a duration distinct from the continuous refresh rate of the animation, the interface from a bottom of a screen of a display device in an accelerating and subsequently decelerating manner; and
in response to revising the recognition result, feeding the revised recognition result to the server to train the speech recognition model.

US Pat. No. 10,796,698

HANDS-FREE MULTI-SITE WEB NAVIGATION AND CONSUMPTION

Microsoft Technology Lice...

1. A method operating on a computing device that is associated with a user, the computing device having a user interface (UI), the method comprising:configuring the UI to enable the user to select multiple websites for inclusion in a group, and to provide a name for the group of user-selected websites;
placing the multiple user-selected websites within the group and associating the user-provided name to the group;
monitoring utilization of the user-selected websites by the user;
listening for a voice input from the user using the user-provided name to open the group of user-selected websites within a browser;
in response to the voice input including the user-provided name for the group, filtering user-selected websites in the group based on the monitored utilization of the user-selected websites, such that certain websites of the user-selected websites within the group are identified for opening within the browser and other user-selected websites within the group are restricted from being opened within the browser; and
opening the identified ones of the user-selected websites in the group based on the filtering so that the opened websites are simultaneously executing, wherein the identified websites are opened in respective individual tabs within the browserin which the filtering is performed to minimize resource utilization on the computing device by restricting opening of particular ones of the websites in the group, the resources including one or more of battery power, network bandwidth, processing cycles, or memory utilization.

US Pat. No. 10,796,697

ASSOCIATING MEETINGS WITH PROJECTS USING CHARACTERISTIC KEYWORDS

MICROSOFT TECHNOLOGY LICE...

1. A computer-implemented system comprising:one or more sensors configured to provide sensor data from at least one user device; one or more processors; and
one or more computer storage media storing computer-useable instructions that, when executed by the one or more processors, implement a method comprising:
evaluating a similarity between a conversation between two or more users and a set of keywords characterizing at least one project associated with a user of the two or more users, the conversation captured by the sensor data;
based on the similarity, activating a listening mode on a user device associated with the user;
generating contextual information associated with the conversation from portions of the sensor data provided by the activated listening mode;
assigning a meeting corresponding to the conversation to a project associated with the user based on the contextual information; and
personalizing content to the user based on the assignment of the meeting to the project.

US Pat. No. 10,796,696

TAILORING AN INTERACTIVE DIALOG APPLICATION BASED ON CREATOR PROVIDED CONTENT

GOOGLE LLC, Mountain Vie...

1. A method implemented by one or more processors, comprising:receiving, via one or more network interfaces:
an indication of a dynamic interactive dialog application,
structured content for executing a tailored version of the dynamic interactive dialog application, wherein the structured content comprises a spreadsheet, and
additional content for executing the tailored version of the dynamic interactive dialog application, wherein the additional content is content that is in addition to the structured content and that is not included in the structured content,
wherein the indication, the structured content, and the additional content are transmitted in one or more data packets generated by a client device of a user in response to interaction with the client device by the user;
storing the structured content in one or more databases based on the indication and based on columns and rows of the spreadsheet;
storing the additional content in one or more of the databases based on the indication;
processing the additional content and the structured content, to automatically select a plurality of output response characteristics for the tailored version of the interactive dialog application, wherein the structured content does not explicitly indicate the output response characteristics;
subsequent to receiving the indication, storing the structured content and the additional content, and automatically selecting the plurality of output response characteristics:
receiving natural language input provided via an assistant interface of the client device or an additional client device of an additional user;
determining that the natural language input corresponds to the tailored version of the interactive dialog application; and
in response to determining that the natural language input corresponds to the tailored version of the interactive dialog application:
executing the tailored version of the interactive dialog application, wherein executing the tailored version of the interactive dialog application comprises generating one or more instances of output for presentation via the assistant interface, each of the one or more instances of output being for a corresponding dialog turn during execution of the interactive dialog application and being generated based on the structured content and based on one or more of the plurality of output response characteristics.

US Pat. No. 10,796,695

MULTIMEDIA DEVICE FOR PROCESSING VOICE COMMAND

LG ELECTRONICS INC., Seo...

1. A multimedia device capable of processing a recognized speech-based command, the device comprising:a memory to store at least one application therein;
an application manager for executing any application among the at least one application stored in the memory; and
a controller configured to receive a speech-based data from an outside,
wherein the controller is configured:
to capture video data from a currently-executed application in response to the received speech-based data;
to control a network interface module to transmit to a server the captured video data, the received speech-based data, and additional information about the currently-executed application; and
to control the network interface module to receive a feedback result value associated with the speech-based data from the server,
wherein the feedback result value varies for the same speech-based data based on the captured video data and the additional information about the currently-executed application.

US Pat. No. 10,796,694

OPTIMUM CONTROL METHOD BASED ON MULTI-MODE COMMAND OF OPERATION-VOICE, AND ELECTRONIC DEVICE TO WHICH SAME IS APPLIED

VTOUCH CO., LTD., Seoul ...

1. An optimum control method based on a gesture-speech multi-mode command, the method controlling an electronic device having a gesture recognition device and a speech recognition device, and comprising the steps of:receiving gesture information of a user through the gesture recognition device;
detecting a first body coordinate point and a second body coordinate point of the user from the gesture information;
detecting a connection vector extending from the first body coordinate point to the second body coordinate point, and a motion vector of the second body coordinate point; and
generating a speech trigger to enable recognition of a speech of the user, when a characteristic value of the motion vector satisfies a predetermined threshold condition,
wherein after the speech trigger is generated, an area in which a voice command of the user is to be executed is determined according to a field of command formed by the second body coordinate point of the user, and
wherein the field of command includes a spatial area formed by extension lines between the first body coordinate point of the user and points that the second body coordinate point of the user forms in a vertical or horizontal direction, with respect to a direction faced by the first body coordinate point.

US Pat. No. 10,796,693

MODIFYING INPUT BASED ON DETERMINED CHARACTERISTICS

Lenovo (Singapore) Pte. L...

1. A method, comprising:receiving, at a digital assistant device, input from a user comprising at least one user command for performing an action at the digital assistant device;
identifying the user providing the input;
determining a characteristic to modify the command, wherein the characteristic is related to the at least one user command and is identified from at least one factor external to the digital assistant device, wherein the determining comprises determining the characteristics from a specific user pattern of the user related to the at least one factor, the specific user pattern being identified from historical data that identifies characteristics selected by the user upon previous provisions of the command when at least one external factor was similar to the at least one factor, wherein the determination of the characteristic is made independent of the received input wherein the determining is based at least in part upon a predetermined radius of the device;
implementing a preference of the identified user with respect to performance of the command, wherein the preference is based upon both the identified user, the specific user pattern, and the determined characteristic and wherein preferences of a user with respect to performance of the command are different with different determined characteristics, wherein the preference is not identified within the at least one user command and is determined from the characteristic; and
performing, by the digital assistant device, a modified action, wherein the modified action comprises the action modified based on the implemented preference.

US Pat. No. 10,796,692

ASSISTIVE LISTENING DEVICE AND HUMAN-COMPUTER INTERFACE USING SHORT-TIME TARGET CANCELLATION FOR IMPROVED SPEECH INTELLIGIBILITY

1. An assistive listening device for use in the presence of stationary interfering sound sources and/or non-stationary interfering sound sources, comprisingan array of microphones arranged into a set of microphone pairs positioned about an axis with respective distinct intra-pair microphone spacings, each microphone of the array of microphones generating a respective audio input signal;
a pair of ear-worn loudspeakers; and
audio circuitry configured to compute a set of time-varying filters, for real-time speech intelligibility enhancement, using causal and memoryless frame-by-frame processing, comprising (1) applying a short-time frequency transform to each of the respective audio input signals, thereby converting the respective time domain signals into respective frequency-domain signals for every short-time analysis frame, (2) calculating a pairwise noise estimate by first subtracting the respective frequency-domain signals from a microphone pair and thereafter taking the magnitude of the difference, (3) calculating a pairwise mixture estimate by first taking the magnitudes of the respective frequency domain signals from a microphone pair, and thereafter adding the respective magnitudes and (4) calculating a pairwise ratio mask from the pairwise noise estimate and the pairwise mixture estimate for each of the respective microphone pairs, wherein the calculation of the pairwise ratio mask includes the aforementioned frequency-domain subtraction of signals, (5) calculating a global ratio mask, which is an effective time-varying filter with a vector of frequency channel weights for every short-time analysis frame, from the set of pairwise ratio masks, with the frequency channels from each pairwise ratio mask chosen according to the frequency range(s) for which the distinct intra-pair microphone spacing provides a positive absolute phase difference; wherein when using only one pair of microphones, the singular pairwise ratio mask and the global ratio mask are equivalent, and (6) applying the global ratio mask, or a post-processed variant thereof, and inverse short-time frequency transforms, to selected ones of the frequency-domain signals, or to the frequency-domain output of a beamformer, thereby suppressing both the stationary and the non-stationary interfering sound sources in real-time and generating an audio output signal for driving the loudspeakers.

US Pat. No. 10,796,691

USER INTERFACE FOR CONTENT AND MEDIA MANAGEMENT AND DISTRIBUTION SYSTEMS

Sinclair Broadcast Group,...

1. A method for providing a user interface for use with a computer in publishing content, the method comprising:providing, via the user interface, multiple selectable items associated with different properties;
providing, via the user interface, multiple controls configured to modify a presentation of content, wherein selection of one of the multiple selectable items causes the computer to provide, to a user of the user interface, a preview of the presentation of the content as it will be published on one of the different properties associated with the selected item; wherein the different properties comprise web pages associated with different brands, and wherein each of the web pages has a structure defined by a property template linked to one or more of the different properties;
configuring the user interface to store a copy of each property of the different properties, the property template, and a determined differentiation between the each property and its linked property template;
automatically discovering tags on the presentation of the content via semantic analysis, interpretation, and cataloging of the tags as they are discovered; and
automatically generating, without user intervention, tags based on one or more relationships within one or more packages such that the presentation of the content has topical tagging.

US Pat. No. 10,796,690

DIGITAL MEDIA ENVIRONMENT FOR CONVERSATIONAL IMAGE EDITING AND ENHANCEMENT

Adobe Inc., San Jose, CA...

1. In a digital media interactive communication environment, a method implemented by at least one computing device, the method comprising:generating, by the at least one computing device, an aesthetic attribute score indicative of quality of a digital image;
determining, by the at least one computing device, a subset of a plurality of canonical intentions based at least in part on the aesthetic attribute score;
receiving, by the at least one computing device, an input utterance from a user;
mapping, by the at least one computing device, the input utterance to a canonical intention from the subset of canonical intentions using natural language understanding;
generating, by the at least one computing device, a suggestion to edit the digital image based on the mapped canonical intention; and
displaying, by the at least one computing device, the generated suggestion in a user interface.

US Pat. No. 10,796,689

VOICE PROCESSING METHODS AND ELECTRONIC DEVICES

LENOVO (BEIJING) CO., LTD...

1. A method for voice processing comprising:acquiring, by a processor, sound information from a user;
extracting, by the processor, speech information from the sound information;
recognizing, by the processor, semantic information of the speech information by determining whether the speech information contains a private keyword;
obtaining, by the processor, context information that indicates a current scenario, the context information including a mood of the user, whether there is a person other than the user present that has a relevant authority to obtain response information, and a status of another device;
determining, by the processor based on the semantic information and the context information indicating the presence of a person other than the user having the relevant authority to obtain the response information relative to or irrelative to the private keyword, the response information configured to respond to the sound information of the user, the response information including voice response information, including:
determining, by the processor based on the semantic information and the context information, sound quality characteristics of the voice response information, the sound quality characteristics including gender and age of a sound that is suitable for presenting the voice response information to the user; and
controlling, by the processor, to present the response information to the user using the sound having the determined sound quality characteristics.

US Pat. No. 10,796,688

ELECTRONIC APPARATUS FOR PERFORMING PRE-PROCESSING BASED ON A SPEECH RECOGNITION RESULT, SPEECH RECOGNITION METHOD THEREOF, AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM

SAMSUNG ELECTRONICS CO., ...

1. An electronic apparatus, comprising:an audio input unit configured to receive sound sources from different positions and provide a plurality of voice signals;
a pre-processor configured to process the plurality of voice signals based on a pre-processing method; and
a voice recognition unit configured to perform voice recognition using the plurality of voice signals processed by the pre-processor, and based on a predetermined trigger being identified as a result of the voice recognition, provide trigger information,
wherein the pre-processor is configured to, based on the trigger information being received from the voice recognition unit, change the pre-processing method and process the plurality of voice signals using the changed pre-processing method, and
wherein the changing the pre-processing method comprises:
increasing a first weight value for identifying the plurality of voice signals as a voice interval before the trigger information is received, and
increasing a second weight value for identifying the plurality of voice signals as a voiceless interval after the trigger information is received.

US Pat. No. 10,796,687

VOICE-ACTIVATED SELECTIVE MEMORY FOR VOICE-CAPTURING DEVICES

Amazon Technologies, Inc....

1. A system, comprising:one or more computing devices implementing one or more services in a service provider environment; and
one or more voice-capturing devices, wherein the one or more voice-capturing devices are communicatively coupled to the one or more services via a network; and
wherein the one or more services are executable by the one or more computing devices to:
receive a first voice input from the one or more voice-capturing devices via the network, wherein the first voice input comprises one or more utterances from a user of the one or more voice-capturing devices;
store a representation of the first voice input that was received from the one or more voice capturing devices via the network, in the service provider environment, wherein the representation of the first voice input comprises at least one or more of audio data, transcription data, or artifacts of the first voice input, and wherein the representation of the first voice input is tagged with a tag;
receive a second voice input from the one or more voice-capturing devices via the network;
determine, using analysis of the second voice input, that the second voice input represents a command to delete the first voice input from the service provider environment; and
based on the determination that the second voice input represents a command to delete the first voice input from the service provider environment, delete from the service provider environment the representation of the first voice input that was received from the one or more voice-capturing devices via the network, wherein the representation of the first voice input is deleted by application of one or more rules at the service provider environment based on contents of the tag.

US Pat. No. 10,796,686

SYSTEMS AND METHODS FOR NEURAL TEXT-TO-SPEECH USING CONVOLUTIONAL SEQUENCE LEARNING

Baidu USA LLC, Sunnyvale...

1. A text-to-speech system comprising:one or more processors; and
a non-transitory computer-readable medium or media comprising one or more sequences of instructions which, when executed by at least one of the one or more processors, causes steps to be performed comprising:
converting textual features of input text into attention key representations and attention value representations using an encoder comprising:
an embedding model, which converts an input text into text embedding representations,
a series of one or more convolution blocks that receive projections of the text embedding representations and process them through the series of one or more convolution blocks to extract time-dependent text information from the input text;
a projection layer that generates projections of the extracted time-dependent text information, which are used to form attention key representations; and
a value representation calculator which computes attention value representations from the attention key representations and the text embeddings representations; and
autoregressively generating low-dimensional audio representations of the input text using an attention-based decoder comprising:
a prenet block that receives input data representing audio frames and comprises one or more fully-connected layers to preprocess the input data;
a series of one or more decoder blocks, each decoder block comprising a convolution block and an attention block, in which a convolution block generates a query and the attention block computes a context representation as a weighted average of at least a portion of the attention value representations and attention weights computed using the query from the convolution block and at least a portion of the attention key representations; and
a postnet block comprising a fully-connected layer, which receives an output from the series of one or more decoder blocks and outputs a next set of low-dimensional audio representations.

US Pat. No. 10,796,685

METHOD AND DEVICE FOR IMAGE RECOGNITION

BEIJING BAIDU NETCOM SCIE...

1. A method for recognizing an image applied to a user terminal comprising:acquiring a to-be-recognized image containing a to-be-recognized object;
sending the to-be-recognized image from the user terminal to a server, and receiving identification information of a target object corresponding to the to-be-recognized object returned by the server, obtained by recognizing the to-be-recognized image using a convolutional neural network model, and a confidence parameter returned by the server, the confidence parameter representing a probability of the to-be-recognized object being the target object; and
in response to the confidence parameter returned by the server being smaller than the confidence threshold, sending the to-be-recognized image from the user terminal to a third-party platform providing question answering services and associated with the server, acquiring manually labeled information associated with the to-be-recognized image from the third-party platform, and determining the manually labeled information as the recognition result, wherein the manually labeled information includes information released by a registered user of the third-party platform.

US Pat. No. 10,796,684

CHROMA DETECTION AMONG MUSIC, SPEECH, AND NOISE

DIALPAD, INC., San Franc...

1. A computer-implemented method, comprising:receiving, by a computing device, audio data describing an audio signal;
determining, by the computing device, a set of frames of the audio signal using the audio data;
identifying, by the computing device, one or more potential music events based on a spectral analysis of the set of frames, the spectral analysis comprising determining a quantity of octaves having a given chroma value with a maximum energy; and
determining, by the computing device, one or more music states of the audio signal based on the one or more potential music events.

US Pat. No. 10,796,683

ACTIVE NOISE CONTROL MICROPHONE ARRAY

Invictus Medical, Inc., ...

1. A noise cancellation apparatus comprising:a plurality of reference input sensors arranged around a perimeter of a spatial zone, wherein the plurality of reference input sensors generate a plurality of reference input signals in response to one or more noise sound waves generated by one or more noise sources;
a localizing microphone array comprising a plurality of localizing microphones;
a selection mechanism coupled to the localizing microphone array and to the plurality of reference input sensors, wherein the selection mechanism is configured to select a reference control signal based on sound localization information from the localizing microphone array, and wherein the selection mechanism is further configured to select the reference control signal from the plurality of reference input signals based on a first criteria, wherein the first criteria is selected from the group consisting of sound pressure level, amplitude, frequency, periodicity, and direction;
a control element in communication with the selection mechanism;
an error input sensor proximate to the spatial zone within the perimeter, wherein the error input sensor is in communication with the control element; and
an output control transducer in communication with the control element, wherein the control element is configured to execute an adaptive noise control algorithm in response to the reference control signal received from the selection mechanism and the error signal received from the error input sensor, and wherein the adaptive noise control algorithm generates an output control signal for the output control transducer to generate a control sound wave configured to destructively interfere with the one or more noise sound waves when the one or more noise sound waves enter the spatial zone.

US Pat. No. 10,796,681

ACTIVE NOISE CONTROL FOR A HELMET

Harman Becker Automotive ...

1. An automatic noise control system comprising:a helmet with a rigid shell configured to spatially divide a shell interior from a shell ambiance;
at least one loudspeaker disposed in the shell interior;
an active noise control processor configured to generate in connection with the at least one loudspeaker, anti-sound in the shell interior based on at least one input signal, the anti-sound configured to attenuate sound occurring in the shell interior through destructive superposition;
at least one sensor configured to provide the at least one input signal, the at least one sensor being at least one of an internal acoustic sensor, a non-acoustic sensor and an external acoustic sensor; wherein:
the internal acoustic sensor is disposed in a vicinity of the at least one loudspeaker in the shell interior;
the non-acoustic sensor is mechanically or acoustically coupled to the shell; and
the external acoustic sensor is mechanically or acoustically coupled to the shell; and
an audio sound processor configured to receive or transmit audio signals via a data bus, wherein the audio signals are used for music or speech playback in the shell interior of the helmet.

US Pat. No. 10,796,680

SOUND ABSORBER WITH STAIR-STEPPING STRUCTURE

The Hong Kong University ...

1. A sound absorber, comprising:a plurality of unit absorbers arranged in a first direction, each unit absorber comprising a plurality of absorber elements comprising first to nth absorber elements arranged in the first direction, each of the first to nth absorber elements having a different thickness; and
a plurality of respectively disposed between the first to nth absorber elements in each unit absorber of the plurality of unit absorbers,
wherein the thickness of the first to nth absorber elements in each unit absorber of the plurality of unit absorbers is the same as that of the first to nth absorber elements, respectively, in each other unit absorber of the plurality of unit absorbers, such that the plurality of unit absorbers extends in a periodic manner in the first direction, and
wherein each wall of the plurality of walls comprises an acoustically reflective material.

US Pat. No. 10,796,679

AUTOMATED WIND CHIME

1. An automated wind chime comprising:a housing and a wobble arm;
wherein the housing is suspended from a clapper of a wind chime;
wherein a motor within the housing rotates the wobble arm when energized;
wherein the wobble arm is unbalanced such that rotation of the wobble arm causes the housing to sway in an erratic pattern;
wherein moving the housing in the erratic pattern causes the clapper to strike a plurality of percussion targets within the wind chime thus producing chime music even in the absence of wind.

US Pat. No. 10,796,678

KEYBOARD APPARATUS

YAMAHA CORPORATION, Hama...

1. A keyboard apparatus comprising:a key configured to rotate;
a member fixed to the key such that a positional relationship between the member and the key does not change when the key rotates;
a frame arranged below the key;
a key-side supporting section connected to the member fixed to the key and extending more downward than the member; and
a flexible section supported by the key-side supporting section, having flexibility in at least an up-and-down direction, and configured to rotate the key with respect to the frame,
wherein the flexible section has a longitudinal direction and has an outer edge including a curved line in a cross section perpendicular to the longitudinal direction.

US Pat. No. 10,796,677

ELECTRONIC MUSICAL INSTRUMENT AND AUTOMATIC POWER-OFF METHOD

YAMAHA CORPORATION, Hama...

1. An electronic musical instrument comprising:a condition determiner that determines whether an OFF condition for turning off a power supply is satisfied in an automatic power-OFF mode;
a noise gate that is opened when a level of an input audio signal exceeds a threshold value and is closed when the level of the input audio signal continues being equal to or lower than the threshold value for a first predetermined period of time; and
a controller that turns off the power supply on the condition that the condition determiner determines that the OFF condition is satisfied in the automatic power-OFF mode, wherein
the controller does not turn off the power supply when the noise gate is in an open state, even in the case where the OFF condition is satisfied.

US Pat. No. 10,796,676

PROGRAMMABLE ELECTRONIC HARMONICA HAVING BIFURCATED AIR CHANNELS

Lee Oskar Levitin, Evere...

1. An instrument for manipulating a variable control signal by embouchure, comprising:a mouthpiece;
a bifurcated air channel dividing airflow through the mouthpiece into first and second flow paths within the bifurcated air channel;
a first substrate suspended within the first flow path and having a first means for transducing air pressure into a first electronic signal;
a second substrate suspended within the second flow path and having a second means for transducing air pressure into a second electronic signal; and
detection circuitry configured to receive the first electronic signal and the second electronic signal and to generate a difference signal analogous to flow rate difference between the airflow through the first flow path and the airflow through the second flow path in response to airflow blown or airflow drawn through the bifurcated air channel.

US Pat. No. 10,796,675

PIANO FOOTED SHEET MUSIC HOLDER

1. A piano sheet music holder comprising:a shelf for holding sheet music;
at least one arm coupled to the shelf,
wherein the arm is formed to rest upon a fall board of the piano when the fall board is open,
wherein the arm is formed so that it extends beneath a piano lid, and
wherein the arm is coupled to a foot; and
a foot,
wherein the foot is formed to extend beneath a built-in sheet music holder of the piano, and
wherein the foot presses upward against the built-in sheet music holder.

US Pat. No. 10,796,674

DRUMHEAD TUNING RIM SYSTEM AND METHOD OF USE

Bedson Drum Co., Edmonds...

1. A drumhead tuning rim system comprising at least one drumhead tuning rim apparatus for securing and tuning a drumhead on a drum shell of a drum, the drumhead tuning rim apparatus comprising:a plurality of low friction housing assemblies configured to be shiftably mounted on the drum shell;
a plurality of low friction lug assemblies configured to be installed spaced about the drum shell;
a rim configured for seating over the drumhead on the drum shell and for selectively removably engaging the low friction housing assemblies so as to secure the rim on the drum shell over the drumhead;
a cable tension dial assembly configured for operably engaging the rim so as to increase or decrease tension on the rim and thus the drumhead; and
a tensioning cable configured for alternately passing about the low friction housing and lug assemblies substantially about the drum shell and for operably engaging the cable tension dial assembly at at least one end so as to selectively raise or lower the overall pitch of the drumhead, whereby operating the cable tension dial assembly to tighten the tensioning cable shifts the low friction housing assemblies toward the low friction lug assemblies and thereby pulls the rim toward the drum shell so as to increase tension on the drumhead, and operating the cable tension dial assembly to loosen the tensioning cable allows the low friction housing assemblies to shift away from the low friction lug assemblies and thereby the rim to shift away from the drum shell so as to decrease tension on the drumhead, further such operation of the cable tension dial assembly allowing the rim to be sufficiently unloaded so as to be selectively disengaged from the low friction housing assemblies and removed from the drum to facilitate removing and replacing the drumhead without any disassembly of the low friction housing assemblies, the low friction lug assemblies, the cable tension dial assembly, and the interconnected tensioning cable.

US Pat. No. 10,796,673

MOUTHPIECE PATCH FOR MUSICAL INSTRUMENT

1. A mouthpiece patch for a mouthpiece of a musical instrument comprising:a substantially planar body comprising a polymer, the body including:
a posterior end,
an anterior end,
lateral side walls,
an upper surface,
a lower surface, and
a recessed region extending in a widthwise direction and configured to receive the teeth of a user, wherein the recessed region is curved to substantially match a profile of the user's teeth.

US Pat. No. 10,796,672

KEYBOARD APPARATUS

YAMAHA CORPORATION, Hama...

1. A keyboard apparatus, comprising:a plurality of keys each rotatable with a predetermined stroke;
a support assembly which includes a support with a first side rotatably arranged with a support rail and a jack with the first side rotatably supported by the support, and rotates with depression of any of the plurality of keys;
a hammer unit which is operated by an action of the jack;
a shank rail which rotatably supports the hammer unit;
a regulating portion which extends from the shank rail and makes contact with the support assembly; and
a jack stopper which makes contact with the jack which rotates with the depression of any of the plurality of keys,
wherein the jack stopper is placed on a rotation path of the jack and protrudes from the shank rail which does not rotate with the depression of any of the plurality of keys, and
wherein the shank rail, the regulating portion, and the jack stopper are arranged on a same side with respect to the jack.

US Pat. No. 10,796,671

KEYBOARD APPARATUS

YAMAHA CORPORATION, Hama...

1. A keyboard apparatus comprising:a key;
a guide regulating a direction in which the key moves, the guide being arranged on a frame at three or more locations not lined in a straight line when seen along a scale direction of the key, and the guide slidably making contact with the key from both sides in the scale direction; and
a connecting portion connecting the key to the frame at the back side of the key from the guide, the connecting portion including a rod-like flexible member.

US Pat. No. 10,796,670

METHOD AND DEVICE FOR REDUCING BANDWIDTH CONSUMPTION, DISPLAY CONTROLLER, AND STORAGE MEDIUM

SANECHIPS TECHNOLOGY CO.,...

8. A device for reducing bandwidth consumption of a display controller, comprising a judgment module, a data reading module and a transparent region determination module, whereinthe judgment module is configured to judge whether image data of a current User Interface (UI) frame to be displayed is the same as image data of a previous UI frame;
the data reading module is configured to read image data in a nontransparent region except a transparent region of the previous UI frame; and
the transparent region determination module is configured to determine a transparent region of the current UI frame to be displayed according to a preset strategy.

US Pat. No. 10,796,669

METHOD AND APPARATUS TO CONTROL AN AUGMENTED REALITY HEAD-MOUNTED DISPLAY

Sony Corporation, Tokyo ...

1. A display control apparatus to control an augmented reality head-mounted display comprising:a display controller configured to display a first screen in a first display mode and display a second screen in a second display mode,
wherein, upon switching of a mode from the first display mode to the second display mode, in the case where a first object included in the first screen corresponds to a second object included in the second screen, the display controller performs a transition from the first object to the second object by translating between a cylindrical coordinate system of the first object in the first screen and a local coordinate system of the second object in the second screen;
a region limiter configured to limit a display region with respect to a height of a visual field on a three dimensional coordinate surrounding a display; and
the display controller including a geomagnetic sensor to detect an orientation of the head mounted display;
wherein, when the head mounted display changes orientation, frequency components of the first object in the first screen or frequency components of the second object in the second screen, that are higher than a predetermined frequency, do not respond to a change in orientation, and a display position of frequency components of the first object in the first screen or frequency components of the second object in the second screen that are lower than the predetermined frequency are fixed.

US Pat. No. 10,796,668

VIRTUAL OBJECT CONTROL METHOD AND RELATED DEVICE

TENCENT TECHNOLOGY (SHENZ...

1. A control method for controlling a virtual object, comprising:at an electronic device having one or more processors, memory, and a display:
activating the virtual object in a virtual scene;
obtaining a current location and area feature data of the virtual object in the virtual scene on the display;
determining an associated area of the virtual object according to the area feature data;
determining whether the current location of the virtual object is located outside the associated area of the virtual object, wherein the virtual object is configured to return to a pre-specified location within the associated area when the virtual object is outside the associated area;
in accordance with a determination that the current location of the virtual object is outside the associated area of the virtual object, determining a current state of the virtual object at the current location;
in accordance with a determination that the virtual object is performing an action of a first state:
controlling the virtual object to return to the pre-specified location within the associated area in the virtual scene after waiting for the virtual object to complete the action of the first state; and
in accordance with a determination that the virtual object is in a second state:
controlling the virtual object to return to the pre-specified location within the associated area after waiting for a predetermine time period.

US Pat. No. 10,796,667

REGISTER SPILL/FILL USING SHARED LOCAL MEMORY SPACE

INTEL CORPORATION, Santa...

1. An apparatus comprising:one or more processors including a graphics processor, the graphics processor including a plurality of hardware threads;
a plurality of registers associated with the graphics processor; and
a shared local memory (SLM), wherein the one or more processors are to:
estimate an amount of space required for one or more of spilling or filling for the plurality of registers in execution of an application,
allocate a first portion of the SLM to perform the one or more of spilling and filling relating to the plurality of registers associated with the graphics processor, wherein the first portion of the SLM includes a plurality of spaces for the plurality of hardware threads, and allocate a second portion of the SLM to load and hold one or more constants, the second portion of the SLM being a global space for access by the plurality of hardware threads, and
utilize the first portion of the SLM as a register buffer for the one or more of spilling and filling relating to the plurality of registers store one or more constants in the second portion of the SLM during execution of the application.

US Pat. No. 10,796,666

DISPLAY INTERFACE PARTITIONING

INTEL CORPORATION, Santa...

1. A display source, comprising:circuitry to communicate pixel data with a display panel via a display port link, the display port link comprising a plurality of lanes, the display panel comprising a plurality of segments, each of the plurality of segments coupled to a respective driver of a plurality of drivers;
a processor coupled to the circuitry; and
memory coupled to the processor, the memory comprising instructions that when executed by the processor cause the processor to:
divide the pixel data into at least a first group of pixel data and a second group of pixel data, the first group of pixel data comprising indications of pixels associated with a first segment of the plurality of segments and the second group of pixel data comprising indications of pixels associated with a second segment of the plurality of segments different than the first segment of the plurality of segments;
assign the first group of pixel data to at least a first lane of the plurality of lanes of the display port link, the first lane to couple to a first driver of the plurality of drivers, the first driver associated with the first segment; and
assign the second group of pixel data to at least a second lane of the plurality of lanes of the display port link, the second lane to couple to a second driver of the plurality of drivers, the second driver associated with the second segment.

US Pat. No. 10,796,665

CONTROL APPARATUS FOR DRIVING DISPLAY PANEL AND METHOD THEREOF

Novatek Microelectronics ...

1. A control apparatus for driving a display panel, comprising:an image flickering detector for detecting whether a present image displayed on the display panel is flickering or not; and
a chopper mode selector, coupled to the image flickering detector, wherein the display panel includes at lease one gamma operational amplifier with an input stage differential pair,
wherein the chopper mode selector selects a first chopper mode from a plurality of chopper modes, and the image flickering detector detects whether the present image displayed on the display panel according to a display image data is flickering or not, and
the chopper mode selector selects a second chopper mode from the plurality of chopper modes in response to the present image flickering, wherein the first chopper mode is different from the second chopper mode,
wherein the chopper modes are used to switch polarities of the input stage differential pair by different sequences in every fixed number of lines at one frame or different sequences in every fixed number of frames in the display image data for reduce a difference of an output voltage of the at least one gamma operational amplifier,
the chopper mode selector comprises a buffer configured to temporarily store a selected chopper mode from the plurality of chopper modes,
wherein the chopper mode selector stores the selected chopper mode and the selected chopper mode is used to adjust the gamma voltages of the display image data,
wherein the at lease one gamma operational amplifier is served as an output buffer of a source driving circuit,
wherein the control apparatus further comprising:
a chopper control circuit, coupled to the gamma operational amplifier,
wherein the chopper control circuit is controlled by the selected chopper mode for reducing an output voltage offset of an output node in the at least one gamma operational amplifier.

US Pat. No. 10,796,664

DISPLAY MODULE AND PREPARATION METHOD, CONTROL METHOD AND CONTROL DEVICE, DISPLAY DEVICE

BOE Technology Group, Co....

1. A display module, comprising:a display panel, comprising a fingerprint recognition area;
an optical compensation layer on a light exiting side of the display panel, and a via in an area thereof opposite to the fingerprint recognition area, wherein the optical compensation layer is a quarter wave plate;
wherein the via is configured to transmit light emitted by the display panel.

US Pat. No. 10,796,663

COLOR COMPENSATION DEVICE, ELECTRONIC DEVICE INCLUDING SAME, AND COLOR COMPENSATION METHOD OF ELECTRONIC DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A color compensation device comprising:a first color converter which receives an image signal, converts the image signal into initial tristimulus values based on a basic look-up table, and generates a conversion look-up table using the basic look-up table;
a parameter generator which extracts 2N number of representative parameters from the conversion look-up table and generates N number of compensation parameters on the basis of the 2N number of representative parameters, N being a natural number;
an operator which generates compensated tristimulus values at each gray scale based on the N number of compensation parameters, generates a compensation look-up table, and converts the initial tristimulus values into the compensated tristimulus values using the compensation look-up table; and
a second color converter which converts the compensated tristimulus values into a compensated image signal.

US Pat. No. 10,796,662

USER INTERFACE DISPLAY COMPOSITION WITH DEVICE SENSOR/STATE BASED GRAPHICAL EFFECTS

Futurewei Technologies, I...

1. A method comprising:receiving a first sensor data from a light sensor;
determining a first visual effect based at least in part on the first sensor data;
applying the first visual effect to one or more application surfaces;
displaying the one or more application surfaces with the first visual effect on a display;
receiving a second sensor data sensed by the light sensor;
determining a second visual effect based at least in part on the second sensor data in response to a change in ambient light sensed by the light sensor;
applying the second visual effect to the one or more application surfaces;
displaying the one or more application surfaces with the second visual effect on the display, wherein the first and the second visual effect are color effects obtained by applying a color value modifier that maps a first color in the first visual effect to a second color in the second visual effect.

US Pat. No. 10,796,661

DISPLAY DRIVER INTEGRATED CIRCUIT WITH OPERATING FREQUENCY ADJUSTMENT AND METHOD OF ADJUSTING OPERATING FREQUENCY

MagnaChip Semiconductor, ...

1. A display driver Integrated Circuit (IC), comprising:a register map configured to store a trim code, a window size, compensation information, and a compensation option;
an oscillator configured to generate an oscillator clock based on the trim code;
a timing controller configured to generate an internal synchronization signal based on the generated first oscillator clock;
a Display Serial Interface (DSI) block configured to output a first data valid signal which is activated based on a data clock and an image data packet update; and
a frequency compensating block configured to compare a periodic value of the oscillator clock with a target periodic value, and generate a compensation trim code obtained by compensating the trim code in accordance with a result of the comparing and the compensation option, in accordance with the first data valid signal,
wherein the periodic value is calculated from the data clock and the internal synchronization signal, and
wherein the oscillator is configured to output a compensation oscillator clock in accordance with the compensation trim code.

US Pat. No. 10,796,660

CONTENT ADAPTIVE DISPLAY INTERFACE

Samsung Display Co., Ltd....

1. A display interface of a display device comprising:an encoder for receiving a stream of data, and for compressing the received data to generate compressed data;
a transmit (TX) rate-buffer for receiving and storing the compressed data from the encoder;
a physical interface (PHY) for receiving the compressed data from the TX rate-buffer;
a receive (RX) rate-buffer for receiving and storing the compressed data from the PHY; and
a decoder for receiving the compressed data from the RX rate-buffer, and for decompressing the compressed data to reconstructed original data,
wherein the PHY is configured to operate according to a burst-mode transmission policy such that the PHY:
enters a SLEEP state to consume less power when the TX rate-buffer transmits a last bit of the compressed data in the TX rate-buffer to the PHY; and
enters an ACTIVE state when:
a fullness of the TX rate-buffer reaches a reference threshold; or
a last bit of compressed data corresponding to a last pixel of a line of pixels is placed in the TX rate-buffer.

US Pat. No. 10,796,659

DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME

SHARP KABUSHIKI KAISHA, ...

1. A display device comprising:a display panel including: a plurality of scanning signal lines each being connected to a plurality of pixel formation portions; and a scanning signal line drive circuit configured to perform vertical scanning by sequentially turning the plurality of scanning signal lines to a selected state in each frame period; and
a direct current voltage generation circuit configured to generate a direct current voltage for turning the scanning signal lines to the selected state,
wherein
the display panel includes a direct current voltage input terminal configured to receive the direct current voltage generated by the direct current voltage generation circuit,
the scanning signal line drive circuit includes a shift register composed of a plurality of unit circuits provided to correspond to the plurality of scanning signal lines, the shift register being configured to perform a shift operation based on a plurality of clock signals,
each unit circuit includes:
a first output node configured to output a scanning signal to a corresponding scanning signal line;
a second output node configured to output a control signal for controlling operations of another unit circuit;
a first node configured to change from an OFF level to an ON level based on a control signal outputted from a second output node of another unit circuit;
a first output control transistor including a control terminal connected to the first node, a first conductive terminal connected to the direct current voltage input terminal, and a second conductive terminal connected to the first output node;
a second output control transistor including a control terminal connected to the first node, a first conductive terminal given a corresponding clock signal, and a second conductive terminal connected to the second output node;
a second node configured to change from an OFF level to an ON level based on a corresponding clock signal;
a second node turn-off transistor including a control terminal connected to the first node, a first conductive terminal connected to the second node, and a second conductive terminal given a potential of the OFF level;
a first first-output-node turn-off transistor including a control terminal connected to the second node, a first conductive terminal connected to the first output node, and a second conductive terminal given a potential of turning a scanning signal line to a non-selected state; and
a second first-output-node turn-off transistor including a control terminal connected to a second output node of an another unit circuit a first conductive terminal connected to the first output node, and a second conductive terminal given a potential of turning a scanning signal line to a non-selected state,
the direct current voltage generation circuit changes a voltage level of the direct current voltage in each frame period,
the potential given to the second conductive terminal of the first first-output-node turn-off transistor and the potential given to the second conductive terminal of the second first-output-node turn-off transistor are different from each other,
the first first-output-node turn-off transistor and the second first-output-node turn-off transistor are n-channel transistors, and
the potential given to the second conductive terminal of the second first-output-node turn-off transistor is lower than the potential iven to the second conductive terminal of the first first-output-node turn-off transistor.

US Pat. No. 10,796,658

GAMMA REFERENCE VOLTAGE GENERATING CIRCUIT, LIQUID CRYSTAL DISPLAY PANEL DRIVING CIRCUIT AND METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A gamma reference voltage generating circuit applied in a liquid crystal display panel, wherein the gamma reference voltage generating circuit comprises a first gamma reference voltage generating module and a second gamma reference voltage generating module;the first gamma reference voltage generating module is configured to receive a source voltage signal from the liquid crystal display panel, use an amplifier to amplify the source voltage signal to obtain a first gamma reference voltage signal, and output the first gamma reference voltage signal to a source driving circuit of the liquid crystal display panel;
the second gamma reference voltage generating module is configured to receive the source voltage signal from the liquid crystal display panel through two inverse amplifiers, use the two inverse amplifiers to inverse-amplify the source voltage signal to obtain two second gamma reference voltage signals and divide a current on the second gamma reference voltage generating module into two output currents, and transmit the two output currents to the source driving circuit through different two paths;
wherein input terminals of the two inverse amplifiers are connected together to receive the source voltage signal, and the obtained two second gamma reference voltage signals are output to different signal input terminals of the source driving circuit
wherein a plurality of positive input terminals of the two inverse amplifiers are connected together to receive the source voltage signal;
wherein a plurality of negative input terminals of the two inverse amplifiers are connected together to receive a reference voltage signal, and an output terminal of each of the two inverse amplifiers outputs the second gamma reference voltage signal.

US Pat. No. 10,796,657

CONVERSION CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE

WuHan TianMa Micro-electr...

1. A conversion circuit, comprising:at least one switch signal input terminal;
a first input terminal;
a second input terminal;
a first output terminal; and
a second output terminal,
wherein the at least one switch signal input terminal receives a switch control signal;
the first input terminal and the second input terminal respectively receive a first input signal and a second input signal, and a polarity of the first input signal and a polarity of the second input signal are different and alternately switch; and
depending on the switch control signal, the first input terminal is in communication with the first output terminal and the second input terminal is in communication with the second output terminal, or the second input terminal is in communication with the first output terminal and the first input terminal is in communication with the second output terminal, so that a first output signal outputted from the first output terminal has a consistent polarity at any time and a second output signal outputted from the second output terminal has a consistent polarity at any time.

US Pat. No. 10,796,656

GOA CIRCUIT

WUHAN CHINA STAR OPTOELEC...

1. A gate driver on array (GOA) circuit, comprising: a plurality of cascaded GOA units, each GOA unit further comprising: a forward/backward scan control module, an output module, a second node control module, a first node control module, and an output terminal control module;for positive integers N and M, N?3, in the N-th GOA unit:
the forward/backward scan control module being configured to control a voltage of a first node according to a scan signal of the (N?2)th GOA unit, a scan signal of the (N+2)th GOA unit, a forward scan control signal, and a backward scan control signal;
the output module being configured to output a scan signal according to an M-th clock signal and the voltage of the first node;
the second node control module being configured to control a voltage of a second node according to an (M+2)th clock signal, the voltage of the first node, and a constant voltage low voltage;
the output terminal control module being configured to pull down the voltage of the scan signal according to the voltage of the second node and the constant low voltage;
the first node control module comprising a tenth thin film transistor (TFT), an eleventh TFT, and a twelfth TFT; the tenth TFT having a gate electrically connected to the second node, a source connected to the constant low voltage, a drain electrically connected to a source of the twelfth TFT; the eleventh TFT having a gate electrically connected to the second node, and a drain electrically connected to the first node, and a source electrically connected to the source of the twelfth TFT; the twelfth TFT having a gate electrically connected to the first node, and a drain connected to a constant high voltage; the tenth TFT, the eleventh TFT and the twelfth TFT being N-type TFTs.

US Pat. No. 10,796,655

DISPLAY DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A display device comprising:a display panel including a plurality of scanning lines and a scanning line drive circuit, the plurality of scanning lines being connected respectively to a plurality of pixel formation portions, the scanning line drive circuit selectively driving the plurality of scanning lines;
a voltage generation circuit configured to receive external power supply and generate one kind of scanning line selecting voltage and one kind of scanning line unselecting voltage, the scanning line selecting voltage being a voltage for turning the scanning lines to a selected state, the scanning line unselecting voltage being a voltage for turning the scanning lines to an unselected state; and
a drive control circuit configured to control an operation of the scanning line drive circuit using the scanning line selecting voltage and the scanning line unselecting voltage which are generated by the voltage generation circuit, wherein
the scanning line drive circuit includes a shift register including a plurality of unit circuits provided so as to respectively correspond to the plurality of scanning lines, the shift register being configured to perform a shift operation based on a plurality of clock signals,
each of the plurality of unit circuits includes:
an output node connected to a corresponding scanning line;
an output control transistor having a control terminal, a first conducting terminal to which one of the plurality of clock signals is supplied, and a second conducting terminal connected to the output node;
an output control node connected to the control terminal of the output control transistor; and
an off control transistor having a control terminal, a first conducting terminal, and a second conducting terminal connected to the output control node,
in normal times, the drive control circuit sets a voltage of the plurality of clock signals to the scanning line selecting voltage and the scanning line unselecting voltage alternatingly, and sets a voltage supplied to the control terminal of the off control transistor and a voltage supplied to the first conducting terminal of the off control transistor to the scanning line unselecting voltage,
when the power supply is stopped, the drive control circuit sets the voltage of the plurality of clock signals, the voltage supplied to the control terminal of the off control transistor, and the voltage supplied to the first conducting terminal of the off control transistor to the scanning line selecting voltage,
an off control signal outputted from the drive control circuit is supplied to the control terminal of the off control transistor via a dedicated line, and
the drive control circuit sets the off control signal to the scanning line unselecting voltage in normal times, and sets the off control signal to the scanning line selecting voltage when the power supply is stopped.

US Pat. No. 10,796,654

SWITCHING CIRCUIT, CONTROL CIRCUIT, DISPLAY DEVICE, GATE DRIVING CIRCUIT AND METHOD

BOE TECHNOLOGY GROUP CO.,...

1. A switching circuit, comprising a gate scanning signal receiving terminal, a second output terminal, a third output terminal, an inverter sub-circuit, an output control sub-circuit, and an output sub-circuit;wherein the gate scanning signal receiving terminal of the switching circuit is configured to receive a gate scanning signal, and the switching circuit is configured to output the gate scanning signal to the second output terminal and the third output terminal simultaneously under control of the gate scanning signal;
the inverter sub-circuit is configured to control a level of a first node in the switching circuit under control of the gate scanning signal;
the output control sub-circuit is configured to transmit a common voltage input by a common voltage terminal to the third output terminal under control of the level of the first node; and
the output sub-circuit is configured to output the gate scanning signal to both the second output terminal and the third output terminal simultaneously under control of the gate scanning signal.

US Pat. No. 10,796,653

GOA CIRCUIT

WUHAN CHINA STAR OPTOELEC...

1. A GOA circuit, which is used in a liquid crystal display panel, comprising m cascaded GOA units, wherein a nth-stage GOA unit comprises: a forward-reverse scan control module, a first gate signal output module and a second gate signal output module, wherein m?n?1;the forward-reverse scan control module is used for controlling the GOA circuit to perform a forward scanning or a reverse scanning in accordance with a forward scan control signal or a reverse scan control signal;
the first gate signal output module comprises: a seventh thin film transistor (TFT), a ninth TFT and a sixteenth TFT; a third terminal of the seventh TFT receives a high potential signal, a first terminal of the seventh TFT is connected to an output terminal of the forward-reverse scan control module, and a second terminal of the seventh TFT is connected to a third terminal of the ninth TFT; a first terminal of the ninth TFT receives a nth clock signal, and a second terminal of the ninth TFT is for outputting a nth gate driving signal; a second terminal of the sixteenth TFT receives the high potential signal and thereby the second terminal of the sixteenth TFT and the third terminal of the seventh TFT are connected to receive the same high potential signal, a first terminal of the sixteenth TFT is connected to the first terminal of the seventh TFT, and a third terminal of the sixteenth TFT is connected to a node between the second terminal of the seventh TFT and the third terminal of the ninth TFT;
the second gate signal output module comprises: a twelfth TFT, a thirteenth TFT and a fifteenth TFT; a third terminal of the twelfth TFT receives the high potential signal, a first terminal of the twelfth TFT is connected to the output terminal of the forward-reverse scan control module, and a second terminal of the twelfth TFT is connected to a third terminal of the thirteenth TFT; a first terminal of the thirteenth TFT receives a (n+2)th clock signal, and a second terminal of the thirteenth TFT is for outputting a (n+2)th gate driving signal; a second terminal of the fifteenth TFT receives the high potential signal and thereby the second terminal of the fifteenth TFT and the third terminal of the twelfth TFT are connected to receive the same high potential signal, a first terminal of the fifteenth TFT is connected to the first terminal of the twelfth TFT, and a third terminal of the fifteenth TFT is connected to another node between the second terminal of the twelfth TFT and the third terminal of the thirteenth TFT;
wherein, the first terminal is one of source and drain, the second terminal is another one of source and drain, and the third terminal is gate.

US Pat. No. 10,796,652

DISPLAY DEVICE WITH NON-RECTANGULAR PIXELS

FLEXENABLE LIMITED, (GB)...

1. A display device for conformal mounting on a curved surface inclined at an oblique angle relative to a horizontal plane, the display device comprising:a plurality of pixels;
a first set of conductive lines connected to the plurality of pixels; and
a second set of conductive lines connected to the plurality of pixels,
wherein the first set of conductive lines and the second set of conductive lines are arranged to define a shape of each of the plurality of pixels such that the pixels appear, to a viewer, to extend at least one of horizontally or vertically across the display device when the display device is mounted on the curved surface, and
wherein the shape of each of the plurality of pixels in a parallelogram, and has a pair of equal opposing oblique angles corresponding to said oblique angle of inclination of the curved surface.

US Pat. No. 10,796,650

LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD THEREFOR

SHARP KABUSHIKI KAISHA, ...

1. A liquid crystal display device comprising:a plurality of pixels arranged in a matrix pattern having a plurality of rows and a plurality of columns, each of the pixels having a pixel electrode;
a plurality of gate bus lines, each of the gate bus lines being associated with any of a plurality of pixel rows of the plurality of pixels;
a plurality of source bus lines, each of the source bus lines being associated with any of a plurality of pixel columns of the plurality of pixels; and
a plurality of TFTs, each of the TFTs being associated with any of the plurality of pixels,
wherein the plurality of pixel rows include a plurality of pixel row groups, each of the pixel row groups including N pixel rows which adjoin one another in a column direction (N is an integer not less than 2), each of the plurality of pixel row groups being selected by a common scan signal voltage in each frame period,
N pixel rows in each of the plurality of pixel row groups are associated with different ones of the source bus lines in each pixel column,
where, in each frame period, a pth selected one of the pixel row groups is a pth group (p is an integer not less than 1), and two pixel rows of the plurality of pixel rows which adjoin each other in a column direction and which are included in different ones of the pixel row groups are a first pixel row and a second pixel row,
the first pixel row includes a pixel which has one of the pixel electrodes capacitively coupled with one of the gate bus lines which is associated with the second pixel row, and
when the first pixel row is included in a qth group (q is an integer not less than 1) and the second pixel row is included in a (q+1)th group,
in each frame period, a scan signal voltage supplied to the gate bus lines which are associated with the (q+1)th group switches from low to high before a scan signal voltage supplied to the gate bus lines which are associated with the qth group switches from high to low.

US Pat. No. 10,796,649

NANO-PARTICLE BASED VARIABLE TRANSMISSION DEVICES

E Ink Corporation, Bille...

1. A method of varying the opacity of a variable transmission assembly comprising:providing a variable transmission assembly including a first light-transmissive electrode, a second light-transmissive electrode, and a variable transmission medium disposed between the first and second light-transmissive electrodes, wherein the variable transmission medium comprises zirconium dioxide nanoparticles, titanium dioxide nanoparticles, or zinc oxide nanoparticles dispersed in a fluid having a dielectric constant less than 10, wherein the zirconium dioxide nanoparticles, titanium dioxide nanoparticles, or zinc oxide nanoparticles have adsorbed thereon a stabilizing material that comprises a carboxylic acid or carboxylate group attached to a chain of at least 10 carbon atoms;
providing a first electric current between the first and second light-transmissive electrodes and through the variable transmission medium, wherein the first electric current has a square or sinusoidal AC form and includes one or more rests, wherein a zero potential is applied during the rest, and wherein the first electric current produces a proton gradient in the variable transmission medium, causing the nanoparticles to flocculate and form aggregates that scatter light; and
providing a second electric current, wherein the second electric current is an AC current having frequency of 60 Hz and higher, causing thermally-induced de-flocculation of the nanoparticles that increases the light-transmissivity of the variable transmission assembly.

US Pat. No. 10,796,648

SMART PIXEL LIGHTING AND DISPLAY MICROCONTROLLER

Apple Inc., Cupertino, C...

1. A light emitting assembly comprising:an array of light emitting diode (LED) device and an array of microcontroller chips arranged in an array of micro-matrices, each micro matrix including a matrix of light emitting diode (LED) devices electrically connected with a microcontroller chip;
wherein each microcontroller chip includes a first output pin that is electrically coupled with a first string of LED devices to drive the first string of LED devices, and a second output pin that is electrically coupled with a second string of LED devices to drive the second string of LED devices; and
distribution lines to electrically connect the array of microcontroller chips and the array of LED devices, wherein the distribution lines electrically connect a plurality of microcontroller chips of the array of microcontroller chips to one another.

US Pat. No. 10,796,647

DISPLAY DEVICE INCLUDING OPTICAL SENSOR AND DRIVING METHOD THEREOF

Semiconductor Energy Labo...

8. A display device comprising:a first substrate, wherein a terminal portion, a switching transistor, a first optical sensor, a second optical sensor, an optical sensor control circuit, a pixel portion and a driver circuit are provided on the first substrate,
a second substrate provided with a counter electrode, the second substrate facing with the first substrate,
wherein the first optical sensor includes a first photoelectric conversion element including an amorphous semiconductor, and a first amplifier circuit,
wherein the second optical sensor includes a second photoelectric conversion element including a polycrystalline semiconductor, and a second amplifier circuit,
wherein the counter electrode is electrically connected to the terminal portion through the switching transistor,
wherein the first optical sensor detects visible light and has a maximum sensitivity at a wavelength of approximately 0.6 ?m, and
wherein the second optical sensor detects visible light and infrared light and has a maximum sensitivity at a wavelength of approximately 0.7 ?m.

US Pat. No. 10,796,646

BACKLIGHT MODULE AND CONTROL METHOD, DISPLAY SCREEN AND WEARABLE DEVICE

FUZHOU BOE OPTOELECTRONIC...

1. A backlight module, comprising a light source and a light guide plate, wherein said light guide plate comprises a transparent substrate and a plurality of dimming units having a reflecting function, said light source is disposed on at least one side of said transparent substrate, and said plurality of dimming units is disposed on a lower surface of the transparent substrate and adjusts intensity of light incident from said light source into said light guide plate and emergent from an upper surface of said transparent substrate facing away from said dimming units,wherein at least one of the dimming units comprises a squeezing unit and at least one elastic reflecting element located between said squeezing unit and a surface of said transparent substrate; said squeezing unit is configured to provide a pressure towards said elastic reflecting element, said elastic reflecting element is configured to produce an elastic deformation when the pressure is provided by said squeezing unit and change a contact area with said transparent substrate, and
wherein said elastic reflecting element is an elastic sphere having a reflecting surface, and two adjacent elastic reflecting elements have a space therebetween.

US Pat. No. 10,796,645

DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a display panel comprising a plurality of display blocks;
a gate driver which outputs a gate signal to the display panel;
a data driver which outputs a data voltage to the display panel; and
a backlight assembly which provides light to the display panel,
wherein sequences of outputting the gate signals from the gate driver to the display blocks are different from each other in adjacent frames,
wherein
a display block of the plurality of display blocks is in a first state when the backlight assembly provides the light to the display block and the gate signal is outputted to the display block,
the display block is in a second state when the backlight assembly does not provide the light to the display block and the gate signal is outputted to the display block, and
when the first state and the second state of the display blocks represent a periodicity, the sequences of outputting the gate signals from the gate driver to the display blocks are different from each other in the adjacent frames.

US Pat. No. 10,796,644

METHOD OF DRIVING DYNAMIC BACKLIGHT AND DISPLAY DEVICE

HISENSE VISUAL TECHNOLOGY...

1. A method of driving a dynamic backlight, comprising:obtaining a vertical synchronization signal meeting a processor output standard;
generating a first level signal with a time length of nT1 when detecting a change edge of the vertical synchronization signal, and generating a second level signal in a period of time from an ending of the first level signal to a next detection of a change edge, wherein T1 is a cycle of a target signal, and n is determined by a multiple relation between cycles of the vertical synchronization signal and the target signal; and
transmitting the first level signal and the second level signal to a drive chip, so that the drive chip generates a PWM signal according to the first level signal and the second level signal;
wherein obtaining the vertical synchronization signal meeting the processor output standard comprises receiving the vertical synchronization signal transmitted by a scan chip, judging whether a frequency of the vertical synchronization signal transmitted by the scan chip meets the processor output standard, and in response to the frequency of the vertical synchronization signal transmitted by the scan chip not meeting the processor output standard, performing frequency multiplication processing on the vertical synchronization signal transmitted by the scan chip, to enable a vertical synchronization signal generated after the frequency multiplication processing to meet the processor output standard.

US Pat. No. 10,796,643

AMOLED DISPLAY PANEL WITH TRANSMITTING GOA CIRCUIT DISPOSED BELOW EFFECTIVE DISPLAY REGION

WUHAN CHINA STAR OPTOELEC...

1. An AMOLED display panel, comprising a GOA circuit and an effective display region;wherein the GOA circuit comprises a transmitting GOA circuit, the transmitting GOA circuit being disposed below the effective display region and completely covered by the effective display region;
wherein the GOA circuit further comprises a first scanning GOA circuit and a second scanning GOA circuit;
wherein the first scanning GOA circuit, the second scanning GOA circuit and the transmitting GOA circuit are disposed in parallel, the first scanning GOA circuit and the second scanning GOA circuit are respectively disposed in edge areas at two sides outside the effective display region or disposed below the effective display region and the first scanning GOA circuit and the second scanning GOA circuit completely covered by the effective display region;
wherein the display panel further comprises multiple rows of pixel units disposed on the effective display region;
the first scanning GOA circuit, the second scanning GOA circuit and the transmitting GOA circuit comprise a first scanning unit, a second scanning unit and a transmitting unit disposed corresponding to each row of the pixel units;
wherein the first scanning unit provides a first scanning signal to a first pixel in each row of the pixel units, the second scanning unit provides a second scanning signal to a second pixel in each row of the pixel units, and the transmitting unit provides a transmitting signal to the first pixel and the second pixel in each row of the pixel units;
the display panel further comprises a power signal for driving the pixel units;
wherein in each row of the pixel units, the pixel unit disposed above the transmitting GOA circuit and the adjacent pixel unit not disposed above the transmitting GOA circuit share the power signal.

US Pat. No. 10,796,642

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:first pixels in a first pixel area and coupled to first scan lines;
a first scan driver configured to supply first scan signals to the first scan lines;
second pixels in a second pixel area and coupled to second scan lines;
a second scan driver configured to supply second scan signals to the second scan lines;
third pixels in a third pixel area and coupled to third scan lines;
a third scan driver configured to supply third scan signals to the third scan lines; and
a timing controller configured to supply a first start signal to the first scan driver, to supply a second start signal to the second scan driver, and to supply a third start signal to the third scan driver,
wherein the second pixel area is between the first pixel area and the third pixel area,
wherein the first scan driver comprises a first dummy stage and first scan stages,
wherein the second scan driver comprises a second dummy stage and second scan stages,
wherein the second dummy stage is configured to receive the second start signal,
wherein a first one of the second scan stages is configured to receive an output signal of the second dummy stage, and
wherein a dummy scan line is coupled between the second dummy stage and a gate electrode of a transistor of one of the second pixels.

US Pat. No. 10,796,641

PIXEL UNIT CIRCUIT, PIXEL CIRCUIT, DRIVING METHOD AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A pixel unit circuit comprising:a light-emitting component with a first terminal coupled with a first voltage input terminal;
a storage capacitor module with a first terminal coupled with a direct current voltage input terminal;
a driver transistor with a gate electrode coupled with a second terminal of the storage capacitor module, and a first electrode coupled with a second terminal of the light-emitting component;
a light-emitting control circuit with a control terminal coupled with a light-emitting control line, a first terminal coupled with a second voltage input terminal and a second terminal coupled with a second electrode of the driver transistor; wherein the light-emitting control circuit is configured to, under control of the light-emitting control line, control whether the second electrode of the driver transistor is coupled with the second voltage input terminal;
a charging compensation control circuit that is coupled with a gate line, a data line and the gate electrode of the driver transistor, respectively; wherein the charging compensation control circuit is configured to, under control of the gate line, control whether the gate electrode of the driver transistor is coupled with the data line; and
a voltage control circuit coupled with the first voltage input terminal and configured to control a voltage value of a first voltage input to the first voltage input terminal;
wherein the pixel unit circuit further includes a reset circuit that is coupled with the light-emitting control line, the first electrode of the driver transistor and a reset voltage input terminal, respectively; wherein the reset circuit is configured to, under control of the light-emitting control line, control whether the first electrode of the driver transistor is coupled with the reset voltage input terminal;
wherein the reset circuit includes a reset switching transistor with a gate electrode coupled with the light-emitting control line, a first electrode coupled with the first electrode of the driver transistor and a second electrode coupled with the reset voltage input terminal;
wherein the light-emitting control circuit includes a light-emitting control transistor with a gate electrode coupled with the light-emitting control line, a first electrode coupled with the second voltage input terminal and a second electrode coupled with the second electrode of the driver transistor; and
wherein one of the light-emitting control transistor and the reset switching transistor is a p-type transistor, and the other of the light-emitting control transistor and the reset switching transistor is an n-type transistor.

US Pat. No. 10,796,640

PIXEL CIRCUIT, DISPLAY PANEL, DISPLAY APPARATUS AND DRIVING METHOD

BOE TECHNOLOGY GROUP CO.,...

1. A pixel circuit comprising:a data write circuit connected to a scan line, a data line and a first node and configured to supply a data voltage on the data line to the first node in response to a scan signal on the scan line;
a reset circuit connected to the scan line, a reference voltage terminal and a second node and configured to supply a reference voltage from the reference voltage terminal to the second node in response to the scan signal on the scan line;
a first storage circuit connected between the second node and a third node and configured to be charged or discharged with a voltage across the second node and the third node;
a second storage circuit connected between a first power supply terminal and the third node and configured to be charged or discharged with a voltage across the first power supply terminal and the third node;
a light-emitting control circuit connected to a light-emitting control line, the first power supply terminal, the first node, the second node, and the third node and configured to, in response to a control signal on the light-emitting control line, provide a conduction path between the first power supply terminal and the third node and a conduction path between the first node and the second node; and
a drive transistor having a gate connected to the first node, a source connected to the third node, and a drain connected to a light-emitting device and configured to drive the light-emitting device to emit light.

US Pat. No. 10,796,639

DISPLAY DEVICE AND METHOD FOR CALIBRATING THE SAME

INT TECH CO., LTD., Hsin...

1. A display device, comprising:a light emitting device configured to emit light, the light emitting device having a plurality of light emitting units;
a photo sensing layer configured to receive the light and to generate a first signal according to the received light, the first signal corresponding to a parameter of the light emitting units;
a first electronic component configured to control the light emitting units; and
a second electronic component configured to compare the first signal with data corresponding to a predetermined parameter of the light emitting units and to identify which light emitting unit has a different parameter with respect to the predetermined parameter.

US Pat. No. 10,796,637

DISPLAY DEVICE

Sony Corporation, Tokyo ...

1. A display device comprising:a plurality of pixel circuits disposed in a matrix including a plurality of rows;
a scanner circuit including an output stage that includes a first transistor and a second transistor serially connected between a first line and a second line, the output stage being configured to output a pulse signal from a node between the first transistor and the second transistor;
a scanning line extending in a row direction of the matrix, and directly connected to the node of the output stage, the scanning line being configured to propagate the pulse signal for driving the pixel circuits in one of the plurality of rows of the matrix,
wherein each of the pixel circuits in said one of the plurality of rows includes:
a storage capacitor configured to store a voltage corresponding to an image signal,
a sampling transistor including a gate electrode connected to the scanning line, and configured to sample the image signal based on the pulse signal supplied from the scanning line, and
a driving transistor configured to control a driving current for a light emitting element based on the voltage stored in the storage capacitor,
wherein the scanner circuit is disposed adjacent to the plurality of pixel circuits on both sides of the plurality of pixel circuits, in the row direction,
a respective channel of each of the first transistor and the second transistor is divided into a plurality of regions, and
a total channel width of each of the first transistor and the second transistor is respectively greater than a pixel pitch in a column direction of the matrix.