US Pat. No. 10,191,872

SEMICONDUCTOR DEVICE AND CONTROL METHOD OF SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a CPU section configured to execute a plurality of software modules; and
a hardware IP configured to perform processing based on operation requests transmitted by the CPU section,
wherein the hardware IP includes
a first storage unit including a plurality of control receiving units configured to receive the operation requests transmitted by respective ones of the software modules,
a calculation unit configured to perform processing based on the operation requests transmitted from the control receiving units to generate response information, and
an arbitration unit configured to control information transmission between the control receiving units and the calculation unit such that the calculation unit receives only one of the operation requests at a time from any one of the control receiving units, and
wherein, while forming a first information transmission path between the calculation unit and one of the control receiving units, the arbitration unit transmits the operation request output from the one of the control receiving units to the calculation unit and transmits the response information generated based on the transmitted operation request from the calculation unit to the one of the control receiving units.

US Pat. No. 10,191,871

SAFE DOUBLE BUFFERING USING DMA SAFE LINKED LISTS

Infineon Technologies AG,...

1. A Direct Memory Access (DMA) controller, comprising:a set of transaction control registers configured to receive a sequence of transaction control sets which are arranged in a linked list and which collectively describe a data transfer by which the DMA controller is to move data, wherein the data transfer is to move the data from a peripheral and alternatingly to a first memory buffer and a second memory buffer, the first and second memory buffers being arranged in parallel with one another at an interface of the peripheral; and
wherein the DMA controller is configured to transfer a first portion of the data from the peripheral to the first memory buffer according to a first transaction control set in the sequence, and is configured to subsequently transfer a second portion of the data from the peripheral to the second memory buffer according to a second transaction control set in the sequence; and
an integrity checker configured to determine an actual error detection code based on the first and/or second portions of the data or an address actually processed by the DMA controller during execution of the first and/or second transaction control sets, the integrity checker being further configured to selectively flag an error based on whether the actual error detection code is the same as an expected error detection code contained in a third transaction control set in the sequence.

US Pat. No. 10,191,870

DATA POLLING USING A CHAIN SLEEP TECHNIQUE

BAKER HUGHES, A GE COMPAN...

1. A computer-implemented method for data polling using a chain sleep technique, the method comprising:computing, by a processing device, a least common multiplier (LCM) based on a polling time for each of a plurality of devices deployed in a well operation to be polled;
generating, by the processing device, a sequence of polling elements, wherein each of the polling elements represents a multiple of the polling time for each of the plurality of devices, wherein the sequence of polling elements begins with the lowest polling time and ends with the LCM;
sorting, by the processing device, the sequence of polling elements from lowest value to highest value as an ordered list;
calculating, by the processing device, a distance between each of the polling elements of the ordered list;
generating, by the processing device, a polling chain based on the ordered list and the distance between each of the polling elements; and
polling, by the processing device, the plurality of devices in the well operation based on the polling chain.

US Pat. No. 10,191,869

INPUT DEVICE WITH MULTI-HOST SWITCHING

Logitech Europe S.A., La...

1. A method of switching wireless connections between a plurality of data input devices and a plurality of host computing devices, the method comprising:establishing a first direct wireless connection between a first data input device and a first host computing device from the plurality of host computing devices, and independently establishing a second direct wireless connection between a second data input device and the first host computing device;
determining a predetermined location on a display of the first host computing device that is configured to be triggered by a cursor entering the predetermined location on the display;
receiving a user input from the first data input device that causes the cursor to enter the predetermined location;
in response to determining that the cursor has entered the predetermined location on the display:
sending a first command to the first data input device that causes the first data input device to establish a direct wireless connection between the first data input device and a second host computing device from the plurality of host computing devices and break the direct wireless connection between the first data input device and the first host computing device; and
sending a second command to the second data input device that causes the second data input device to establish a direct wireless connection between the second data input device and the second host computing device and break the direct wireless connection between the second data input device and the first host computing device.

US Pat. No. 10,191,868

PRIORITY FRAMEWORK FOR A COMPUTING DEVICE

AMPERE COMPUTING LLC, Sa...

1. A system for managing priority to a memory subsystem, comprising:a first level memory access handling unit configured to generate memory access requests in accordance with corresponding instructions originating from multiple levels of a computing system architecture, the multiple levels comprising at least an application level, a network level, an operating system level, and a micro-architectural level, wherein the first level memory access handling unit is of a higher level of the computing system architecture relative to the memory subsystem, and the instructions generated by the multiple levels have associated priority indicators assigned in accordance with prioritization schemes respectively associated with the multiple levels, the priority indicators comprising first priority indicators assigned to a first subset of the instructions originating at the application level based on user-defined application priorities, second priority indicators assigned to a second subset of the instructions originating at the network level based on a determination of whether the instructions originate from the network level or an internal level, and third priority indicators assigned to a third subset of the instructions originating at the operating system level based on a determination of whether the third subset of the instructions are associated with an interrupt at the operating system level; and
a memory controller unit of the memory subsystem configured to receive the memory access requests and the priority indicators, and to assign respective memory access priorities of the memory access requests based on the priority indicators.

US Pat. No. 10,191,867

MULTIPROCESSOR SYSTEM HAVING POSTED TRANSACTION BUS INTERFACE THAT GENERATES POSTED TRANSACTION BUS COMMANDS

Netronome Systems, Inc., ...

1. An integrated circuit comprising a plurality of rectangular islands disposed in a two-dimensional array, wherein the rectangular islands are intercoupled by a posted transaction bus, wherein one of the rectangular islands comprises:a first processor;
a second processor that executes the same instruction set that the first processor executes; and
an interface means for receiving addresses from the first processor via a first bus and for receiving addresses from the second processor via a second bus and for interfacing to the posted transaction bus, wherein neither the first bus nor the second bus is a posted transaction bus, wherein an address received by the interface means via the first bus is an address in shared address space shared by the first and second processors, wherein the interface means generates a posted transaction bus read command from the address received via the first bus and causes a posted transaction bus read transaction to occur using the generated posted transaction bus read command such that read data is obtained from the posted transaction bus and is then stored into a shared memory in the interface means at a memory location indicated by the first processor.

US Pat. No. 10,191,866

MEMORY CONTROLLER FOR SELECTIVE RANK OR SUBRANK ACCESS

1. A memory controller integrated circuit, comprising:transaction queue circuitry to implement transaction queues;
a register to store a selective one of a first mode select value and a second mode select value;
command path circuitry to receive memory access commands from the transaction queues and to transmit the memory access commands to first and second memory devices over a common command path connection; and
data exchange circuitry to exchange data with the first and second memory devices via respective first and second data paths; wherein based on the first mode select value the command path circuitry is to drive the common command path connection responsive to a single one of the transaction queues, and the data exchange circuitry is to responsively exchange data via both of the respective first and second data paths in association with each memory access command from the single one of the transaction queues; and
wherein based on the second mode select value
the command path circuitry is to is to drive the common command path connection to time-multiplex first and second memory access commands from respective transaction queues, and
the data exchange circuitry is to concurrently exchange first data in association with the first memory access command via the first data path and second data in association with the second memory access command via the second data path.

US Pat. No. 10,191,865

CONSOLIDATING WRITE TRANSACTIONS FOR A NETWORK DEVICE

Amazon Technologies, Inc....

1. A network device comprising:a network interface operable to send and receive a packet;
a bus interface operable to send and receive bus traffic on a bus; and
processing logic coupled to the bus interface and the network interface, wherein the processing logic is operable to:
store information associated with the packet in a queue;
mask interrupts for the network device;
send an interrupt to a host processor to notify the host processor of completion of packet processing;
receive, by the bus interface, a Memory-Mapped Input/Output (MMIO) write transaction that includes an update for a pointer associated with a completion queue and an interrupt unmasking value;
update the pointer associated with the completion queue; and unmask the interrupts for the network device based on the MMIO write transaction.

US Pat. No. 10,191,864

STANDARDIZED INTERFACE FOR STORAGE USING AN INPUT/OUTPUT (I/O) ADAPTER DEVICE

Amazon Technologies, Inc....

1. An Input/Output (I/O) adapter device comprising:a storage device interface configured to communicate with a first storage device and a second storage device communicatively coupled to the I/O adapter device;
a host interface configured to communicate with a host device communicatively coupled to the I/O adapter device, wherein the host device is configured to run an operating system and wherein the operating system executes a standardized storage frontend driver to communicate with the I/O adapter device through the host interface and using a standardized interface implemented in the operating system; and
a processing core communicatively coupled to the storage device interface and to the host interface, wherein the processing core is configured to execute a plurality of computer-executable instructions to execute:
a first emulated storage backend driver to communicate with the standardized storage frontend driver through the host interface using the standardized interface, and to communicate with the first storage device, to provide the standardized storage frontend driver with access to the first storage device; and
a second emulated storage backend driver to communicate with the standardized storage frontend driver through the host interface using the standardized interface, and to communicate with the second storage device, to provide the standardized storage frontend driver with access to the second storage device.

US Pat. No. 10,191,861

TECHNIQUE FOR IMPLEMENTING MEMORY VIEWS USING A LAYERED VIRTUALIZATION ARCHITECTURE

FireEye, Inc., Milpitas,...

1. A system comprising:a memory to store a guest process, a guest operating system kernel and a virtualization layer;
a memory management unit (MMU) coupled to the memory and including a guest page table hierarchy associated with the guest process; and
a central processing unit (CPU) coupled to the MMU, the CPU to execute the guest process, the guest operating system kernel and the virtualization layer, the virtualization layer when executed operable to:
classify the guest process when the guest operating system kernel switches to the guest process for execution on the CPU;
bind a first memory view to the guest process based on the classification of the guest process; and
activate the first memory view bound to the guest process, the first memory view used as a container for the guest process, the first memory view using a first nested page table hierarchy to constrain access to the memory while the guest process is active.

US Pat. No. 10,191,860

SECURING SENSITIVE HISTORIAN CONFIGURATION INFORMATION

Schneider Electric Softwa...

1. A computer system comprising:a cloud-based data store comprising a plurality of data sets in at least one storage account thereof, at least one of the data sets storing time series data representative of historical plant process information and at least one other of the data sets storing configuration information, wherein the configuration information is configured for use by a cloud service associated with the data store, and wherein the configuration information comprises at least an access key related to the storage account; and
a service role terminal, comprising:
one or more processors coupled to the cloud service and a process historian via a data communication network, wherein the service role terminal is coupled between the cloud service and the process historian; and
a memory device coupled to the one or more processors, said memory device storing computer-executable instructions that, when executed by the one or more processors, cause the service role terminal to perform a method for securely providing the configuration information to the cloud service, wherein the method comprises:
receiving, by the service role terminal, the configuration information related to the cloud service downloaded from the process historian when the service role terminal is authorized for said receiving according to a deploy service role of the cloud service;
storing, by the service role terminal, the received configuration information in a configuration data file;
applying, by the service role terminal, a public certificate without a private key to the configuration data file to transform the configuration data file into a protected configuration data file; and
uploading, by the service role terminal, the protected configuration data file to the cloud service, wherein configuration settings of the uploaded protected configuration data file are available for reading by the cloud service via the public certificate while the configuration data file is protected, and wherein the uploaded protected configuration data file is available for querying by a query service role of the cloud service while the configuration data file is protected.

US Pat. No. 10,191,859

MEMORY ACCESS PROTECTION APPARATUS AND METHODS FOR MEMORY MAPPED ACCESS BETWEEN INDEPENDENTLY OPERABLE PROCESSORS

Apple Inc., Cupertino, C...

1. A method for providing access to a shared memory resource, comprising:during a boot process of a second processor:
generating, by a first processor, a first window register value associated with the shared memory resource;
transmitting the first window register value from the first processor to a window register of the second processor, the first window register value defining a first extent of address space within the shared memory resource that is directly accessible by the second processor; and
wherein the first extent of address space is mapped to a memory map of the second processor during the boot process.

US Pat. No. 10,191,858

VIRTUAL MACHINE MEMORY LOCK-DOWN

1. A method of memory lock-down, the method comprising:storing, by a guest virtual machine, a secure datum at a location within a memory range;
responsive to storing the secure datum, sending, by the guest virtual machine, a request to disable access to the memory range;
receiving, by a hypervisor from the guest virtual machine, the request to disable access to the memory range;
disabling, by the hypervisor, access to the memory range;
detecting, by the hypervisor, a prohibited access attempt, wherein the prohibited access attempt is an access attempt to the memory range;
responsive to detecting the prohibited access attempt, stopping, by the hypervisor, the guest virtual machine;
receiving, by the hypervisor, a request to reboot the guest virtual machine;
rebooting, by the hypervisor, the guest virtual machine; and
responsive to rebooting the guest virtual machine, enabling, by the hypervisor, access to the memory range.

US Pat. No. 10,191,856

METHOD OF MANAGING WEB BROWSER CACHE SIZE USING LOGICAL RELATIONSHIPS AND CLUSTERING

Yandex Europe AG, Lucern...

1. A computer-implemented method for managing a browser cache, the method comprising:storing in a cache of a web browser on a user device a plurality of web pages visited by a user during one or more web browsing sessions;
generating a web page identifier for each web page of the plurality of web pages;
defining a plurality of clusters of the plurality of web pages stored in the cache by:
determining logical relationships among the plurality of web pages stored in the cache, and
associating each web page of the plurality of web pages with one or more clusters of the plurality of clusters based on the determined logical relationships among the plurality of web pages such that each given cluster of the plurality of clusters includes at least one web page of the plurality of web pages, a list of identifiers, and a unique cluster identifier, the list of identifiers including the web page identifier of each web page of the at least one web page of the given cluster;
upon detecting a usage size of the cache equal to or exceeding a threshold value, determining, based on information associated with the plurality of clusters, at least a portion of at least one cluster of the plurality of clusters to be deleted from the cache, the information associated with the plurality of clusters including at least: (i) the list of identifiers and (ii) the unique cluster identifier of each cluster of the plurality of clusters; and
deleting from the cache at least the portion of the at least one cluster based on at least one corresponding web page identifier of the list of identifiers of the at least one cluster.

US Pat. No. 10,191,854

EMBEDDED RESILIENT DISTRIBUTED DATASET SYSTEMS AND METHODS

Levyx, Inc., Irvine, CA ...

1. An embedded memory system, comprising:a logical block addressing table that maps logical block addresses to secondary memory addresses of a secondary memory having a second type of memory;
a data block table having:
a secondary address portion that maps data block addresses to logical block addresses of the logical block addressing table, and
a primary address portion that maps data block addresses to physical memory addresses of a primary memory having a first type of memory, wherein the first type of memory and the second type of memory are different; and
a read module programmed to:
receive a request to read a data block at a first data block address from a first thread;
correlate the first data block address to a first physical memory address using the primary address portion of the data block table; and
return a read-only pointer to the first physical memory address to the first thread.

US Pat. No. 10,191,853

APPARATUS AND METHOD FOR MAINTAINING ADDRESS TRANSLATION DATA WITHIN AN ADDRESS TRANSLATION CACHE

ARM Limited, Cambridge (...

1. An apparatus comprising:an address translation cache having at least one entry, each entry to store address translation data used when converting a virtual address into a corresponding physical address of a memory system;
control circuitry to perform an allocation process to determine the address translation data to be stored in each entry;
the control circuitry arranged when performing the allocation process for a selected entry in the address translation cache:
to perform a page table walk process using a virtual address in order to obtain from a page table a plurality of descriptors including a descriptor identified using the virtual address;
to determine whether predetermined criteria are met by said plurality of descriptors, said predetermined criteria comprising page alignment criteria and attribute match criteria, each descriptor comprising physical address data and attribute data identifying a plurality of attributes, and the attribute match criteria allowing the plurality of descriptors to have different values for a first subset of the attributes when determining that the attribute match criteria is met;
when said predetermined criteria are met, to generate coalesced address translation data from said plurality of adjacent descriptors and to store said coalesced address translation data in said selected entry; and
in absence of said predetermined criteria being met, to generate address translation data from the descriptor identified using the virtual address and to store that address translation data in said selected entry.

US Pat. No. 10,191,852

METHODS AND APPARATUS FOR LOCKING AT LEAST A PORTION OF A SHARED MEMORY RESOURCE

Apple Inc., Cupertino, C...

1. A method for locking a shared memory, comprising:attempting to lock at least a portion of the shared memory by a first processor;
verifying whether a second processor has locked the at least the portion of the shared memory;
responsive to determining that the at least the portion of the shared memory is successfully locked based on the verifying whether the second processor has locked the at least the portion of the shared memory, executing a critical section, the critical section comprising one or more computer instructions accessible only to the first processor; and
otherwise, responsive to determining, based on the verifying whether the second processor has locked the at least the portion of the shared memory, that the at least the portion of the shared memory is not successfully locked, attempting to lock the at least the portion of the shared memory at a later time.

US Pat. No. 10,191,851

METHOD FOR DISTRIBUTED TRANSACTION PROCESSING IN FLASH MEMORY

TSINGHUA UNIVERSITY, Bei...

1. A method for distributed transaction processing in a flash memory, comprising the following steps:S1. performing two-phase commit on a transaction and removing a state log record of a two-phase commit protocol, wherein the function and information stored in the state log record of the two-phase commit protocol is internalized as an operation on flash memory metadata in a transaction interface, thereby removing the step of creating and updating the state transaction log file for the two-phase commit; wherein final commit of a coordinator is used as a distributed transaction end identifier;
S2. in a process of performing the transaction, storing a temporary data object as a shadow version,
using a shadow mapping table to store an address of the shadow version or the state of a page in the transaction processing, wherein the shadow mapping table is a memory structure that records the address of the shadow version in the first phase of the two-phase commit and records the state of the page participating in the transaction in the second phase of the two-phase commit,
using page metadata to record transaction information wherein the page metadata is an out-of-band (OOB) area of a flash memory page,
using a transaction metadata page to record a transaction state wherein the transaction metadata page stored in a transaction state table is used to determine whether the transaction is committed or aborted: the shadow mapping table records commit identifier, and the transaction metadata page records transaction commit, and
using the transaction state table to record an address of the transaction metadata page, wherein the transaction state table is a persistently stored mapping table, and before the transaction metadata page is written, the transaction state table stores a mapping from a transaction identification (ID) to the address of the transaction metadata page; and
S3. when the coordinator or a participant fails, scanning a part of the storage, reading the flash memory metadata, and recovering a FTL mapping table, the shadow mapping table, and the transaction state table to determine the state of the transaction in the two-phase commit with the state log record of the two phase commit protocol removed;
wherein the step S2 further comprises: when the transaction is written, the shadow mapping table stores a location of new data; and
the page metadata records logic page number, the transaction ID, and the quantity of transaction pages, and when the transaction is committed, the location of the new data is updated to the FTL mapping table and changed to a user readable state; the shadow mapping table records a commit identifier, and the transaction metadata page records transaction commit; if the transaction is aborted, the shadow mapping table records an abort identifier, and the transaction metadata page records transaction abort, and the new data is set as invalid;
if a flash memory block is used completely and all transactions on the flash memory block are completed, the flash memory block is marked as a CHECKED block; if there is an uncompleted transaction, the flash memory block is marked as a WAIT block; if the flash memory block is partially used, the flash memory block is marked as an UPDATE block; if the flash memory block is not used, the flash memory block is marked as a FREE block; and the first page of the block is used to differentiate a block state;
when a failure occurs in the two-phase commit process, the FTL mapping table, the shadow mapping table, and the transaction state table are recovered to determine the transaction state, and the WAIT block and the UPDATE block are scanned,
wherein the step S3, when the coordinator or a participant fails, scanning a part of the storage, reading the flash memory metadata, and recovering the FTL mapping table, the shadow mapping table, and the transaction state table to determine the state of the transaction in the two-phase commit, comprises the following steps:
step (1): scanning and finding all UPDATE blocks and WAIT blocks,
step (2): scanning the UPDATE blocks, recovering the FTL mapping table, the shadowing mapping table, and the transaction state table, and determining a transaction state on these blocks: a mapping (Logic Page Number (LPN), transaction ID, (TxID)) is written in page metadata and the transaction metadata page is located before all transaction data ages; and pages on the UPDATE blocks are scanned in sequence; and
step (3): scanning the WAIT block, and reading the transaction identification from the page metadata.

US Pat. No. 10,191,850

PROVIDING MEMORY BANDWIDTH COMPRESSION USING MULTIPLE LAST-LEVEL CACHE (LLC) LINES IN A CENTRAL PROCESSING UNIT (CPU)-BASED SYSTEM

QUALCOMM Incorporated, S...

1. A central processing unit (CPU)-based system comprising:a system memory;
a system cache;
a last-level cache (LLC) comprising a plurality of LLC lines each sized to store a plurality of sub-lines corresponding to a plurality of system cache lines of the system cache; and
a compressed memory controller (CMC), comprising a memory interface configured to access the system memory and the system cache via a system bus, and communicatively coupled to the LLC;
the CMC configured to:
receive, from the system cache, a memory read request comprising a memory address;
determine whether the memory address corresponds to a valid sub-line of the plurality of sub-lines within an LLC line of the plurality of LLC lines of the LLC; and
responsive to determining that the memory address does not correspond to a valid sub-line of the plurality of sub-lines within an LLC line of the plurality of LLC lines of the LLC:
read a master table entry containing an offset value and a length value for the LLC line from a master table in the system memory;
retrieve one or more blocks from the system memory based on the memory address, the offset value, and the length value;
store data from the retrieved one or more blocks in a sub-line of the plurality of sub-lines within an LLC line of the plurality of LLC lines of the LLC; and
return the data from the retrieved one or more blocks to the system cache.

US Pat. No. 10,191,848

SYSTEM AND METHOD FOR CACHING TIME SERIES DATA

InMobi PTE Ltd., Singapo...

1. A computer system for caching time series data, the computer system comprising:one or more processors;
at least one cache; and
a non-transitory computer readable storage medium,
wherein the non-transitory computer readable storage medium includes instructions that, when executed by the one or more processors, cause the one or more processors to perform a set of steps comprising:
receiving a request for the time series data;
fetching the time series data from a time series data source, wherein the time series data comprises a plurality of time series datum and a fetch timestamp;
calculating one or more expiry timestamps, wherein each expiry timestamp from the one or more expiry timestamps is calculated using a composite function of the fetch timestamp of the time series data and a recording time associated with a time series datum, such that the expiry timestamp is inversely proportional to the recording time associated with the time series datum so that newer time series data expires on or before older time series data, and the expiry time stamp is directly proportional to the fetch timestamp of the time series data;
grouping the plurality of time series datum in to one or more time data chunks based on the one or more expiry timestamps, wherein each time data chunk from the one or more time data chunks comprises a distinct set of time series datum from the time series data;
determining the validity of the one or more time data chunks of the time series data based on the one or more expiry timestamps;
storing a copy of the time series data and the one or more expiry timestamps in the at least one cache;
serving the requests from one of a group consisting of the time series data source and the at least one cache, based on the validity of the one or more time data chunks of the time series data; and
utilizing the one or more expiry timestamps to respond to requests for the time series data.

US Pat. No. 10,191,847

PREFETCH PERFORMANCE

International Business Ma...

1. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processor to cause the processor to:receive at least a first request in a plurality of requests to pre-fetch data from a stream in a plurality of streams;
assign a confidence level to the at least the first request based on an amount of confirmations observed in the stream, wherein the at least the first request is in a confident state if the confidence level exceeds a specified phase threshold and wherein the at least the first request is in a non-confident state if the confidence level does not exceed the specified phase threshold;
prioritize requests to prefetch data in the plurality of requests having a higher confidence level than the confidence level of the first request to pre-fetch data;deprioritize requests to prefetch data in the plurality of requests that are associated with respective streams with a low prefetch utilization ratio; anddetermine whether to drop the at least the first request based on the confidence level, based upon a prefetch utilization ratio of the stream, and based upon a memory resource utilization threshold.

US Pat. No. 10,191,846

CACHE MEMORY FOR PARTICULAR DATA

TOSHIBA MEMORY CORPORATIO...

1. A cache unit comprising:a first memory configured to temporarily hold data and an address of the data;
a second memory configured to temporarily hold an address of a particular data set in advance, the particular data being not held by the first memory; and
a controller configured to, when an instruction to load first data is made for a first specified address, search for a storage destination of the first specified address, output the data of the first specified address if the storage destination is the first memory, and output the particular data if the storage destination is the second memory, and configured to, when an instruction to store a specified data at a second specified address is made, judge whether the specified data is the particular data or not, store the second specified address and the specified data into the first memory if the specified data is not the particular data, and store the second specified address into the second memory if the specified data is the particular data.

US Pat. No. 10,191,845

PREFETCH PERFORMANCE

International Business Ma...

1. A method, comprising:receiving at least a first request in a plurality of requests to pre-fetch data from a stream in a plurality of streams;
assigning a confidence level to the at least the first request based on an amount of confirmations observed in the stream, wherein the at least the first request is in a confident state if the confidence level exceeds a specified phase threshold and wherein the at least the first request is in a non-confident state if the confidence level does not exceed the specified phase threshold;
prioritizing requests to prefetch data in the plurality of requests having a higher confidence level than the confidence level of the first request to pre-fetch data;deprioritizing requests to prefetch data in the plurality of requests that are associated with respective streams with a low prefetch utilization ratio; anddetermining whether to drop the at least the first request based on the confidence level, based upon a prefetch utilization ratio of the stream, and based upon a memory resource utilization threshold.

US Pat. No. 10,191,844

AUTOMATIC GARBAGE COLLECTION THRASHING MONITORING

Cisco Technology, Inc., ...

1. A method for monitoring a garbage collection process in a business transaction over a computer network, comprising:monitoring, by an agent on a server, the garbage collection process to identify a source of a garbage thrashing in the garbage collection process, the garbage collection process executed in association with one or more business transaction applications executing on the server;
determining, by the agent, a memory usage associated with the garbage collection process;
collecting, by the agent, a plurality of data objects handled by the garbage collection process;
graphing, by the agent, the plurality of data objects handled by the garbage collection process into a memory usage versus time graph, wherein the graph is divided into garbage collection time intervals;
determining, by the agent, a memory usage associated with each of the collected data objects handled by the garbage collection process during each of the garbage collection time intervals based on the graph of the plurality of data objects handled by the garbage collection process;
comparing, by the agent, graphically the memory usage of each of the collected data objects to the memory usage of the garbage collection process by comparing one or more stack traces obtained at a time of creation of the collected data objects to identify one or more commonalities regarding the creation of the collected data objects to identify the source of the garbage trashing;
identifying, by the agent, a suspicious sub-set of the collected data objects that most closely resemble the memory usage of the garbage collection process, wherein the suspicious sub-set of the collected data objects is the source of the garbage thrashing in the garbage collection process; and
reporting, by the agent, the sub-set of identified data objects as the source of the garbage thrashing in the garbage collection process.

US Pat. No. 10,191,843

UNALIGNED DATA COALESCING

Micron Technology, Inc., ...

1. A method for unaligned data coalescing, comprising:receiving a first write command associated with an unaligned portion of data; and
coalescing, using a coalescing tree, the unaligned portion of data with data associated with another write command, wherein a logical address of the unaligned portion of data and a logical address of the data associated with the another write command correspond to a particular logical page.

US Pat. No. 10,191,842

APPARATUS WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY

VIRIDENT SYSTEMS, LLC, S...

1. An apparatus, comprising:a mother board;
a plurality of processors coupled to the mother board;
an interconnect fabric coupled to the plurality of processors and the mother board;
a first controller means for controlling a first memory channel, the first controller means being distinct from the plurality of processors;
a second controller means for controlling a second memory channel, the second controller means being distinct from the plurality of processors and the first controller means;
one or more DRAM DIMMS coupled to the first controller means and the first memory channel, wherein the first controller means controls the one or more DRAM DIMMS; and
one or more non-DRAM DIMMS coupled to the second controller means and the second memory channel, wherein the second controller means controls the one or more non-DRAM DIMMS, wherein the first controller means, the second controller means, the one or more DRAM DIMMS and the one or more non-DRAM DIMMS are coupled to the motherboard.

US Pat. No. 10,191,841

HOST DEVICE, ACCESS SYSTEM, AND ACCESS METHOD

SHANNON SYSTEMS LTD., Sh...

1. A host device comprising:a storage device storing a physical mapping table;
a processor checking the physical mapping table according to a first logical block address and a second logical block address of an access operation to find a first physical block address, a second physical block address, a first solid state disk (SSD) identification code, and a second SSD identification code; and
an interface, coupled to the processor,
wherein the processor transmits the first physical block address which is found from the physical mapping table to one of a plurality of SSDs through the interface according to the first SSD identification code to access data at the first physical block address and transmits the second physical block address which is found from the physical mapping table to another one of the plurality of SSDs through the interface according to the second SSD identification code to access a horizontal parity code at the second physical block address,
wherein the plurality of SSDs are disposed outside of the processor,
wherein the plurality of SSDs form a redundant array of independent disks (RAID), and the RAID stores the data into a first SSD among the plurality of SSDs and further stores the horizontal parity code and a vertical parity code which correspond to the data respectively into a second SSD and a third SSD among the plurality of SSDs, and
wherein the processor generates the horizontal parity code and the vertical parity code according to the data and checks or recovers the data according to the horizontal parity code and the vertical parity code.

US Pat. No. 10,191,840

MAPPING TABLE UPDATING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A mapping table updating method for a memory storage device having a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical programming units, the mapping table updating method comprising:allocating a mapping table storage area for storing a physical address-logical address mapping table in a buffer memory;
determining whether a remaining storage space of the mapping table storage area is less than a first threshold;
if the remaining storage space is less than the first threshold, updating mapping information of the physical address-logical address mapping table stored in the mapping table storage area into at least one logical address-physical address mapping table;
clearing the mapping information of the physical address-logical address mapping table stored in the mapping table storage area; and
programming a plurality of writing data belonging to a plurality of logical programming units into the physical programming units of an active physical erasing unit among the physical erasing units, establishing a plurality of updated mapping information between the physical programming units programmed with the writing data and the logical programming units, and storing the updated mapping information into the physical address-logical address mapping table in the mapping table storage area,
wherein the logical address-physical address mapping table records a mapping relation between the logical programming units and the physical erasing units, and the physical address-logical address mapping table records a mapping relation between the programmed active physical erasing unit and the logical programming units.

US Pat. No. 10,191,839

SEARCH DEVICE INCLUDES ASSOCIATIVE MEMORY, SEARCH DATA GENERATING UNIT FOR GENERATING SEARCH INFORMATION BASED ON HIT INFORMATION AND A SEARCH KEY GENERATING UNIT GENERATING SEARCH KEYS BASED ON SEARCH INFORMATION AND THE SEARCH DATA

RENESAS ELECTRONICS CORPO...

1. A search device comprising:a first associative memory that is searched with a first search key;
a second associative memory that is searched with a second search key;
a first concatenated search data generating unit that generates first search information based on hit information including multiple hits in the first associative memory; and
a search key generating unit that includes a first search key generating unit generating the first search key based on search data and a second search key generating unit generating the second search key based on the first search information and the search data.

US Pat. No. 10,191,838

METHOD AND DEVICE FOR CHECKING INFLUENCE OF DELETING CACHE FILE, AND MOBILE TERMINAL

BEIJING KINGSOFT INTERNET...

1. A method for checking an influence of deleting a cache file, comprising:acquiring a program to be checked, and acquiring a click path set and a cache path set corresponding to the program to be checked, wherein the click path set includes a plurality of click paths, and the cache path set includes a plurality of cache paths, and each click path set corresponds to a cache path;
acquiring a cache path to be checked in the cache path set, and deleting a cache file to be checked from the cache path to be checked;
conducting a click simulation on the program to be checked according to a click path corresponding to the cache path to be checked; and
acquiring the influence of deleting the cache file to be checked according to an operating result of the program to be checked.

US Pat. No. 10,191,836

SOFTWARE WATCHPOINTS APPARATUS FOR VARIABLES STORED IN REGISTERS

NXP USA, Inc., Austin, T...

1. A method for debugging a compiled computer program comprising one or more variables, the method comprising:generating variable location information for a first variable stored in a CPU register using debug information and runtime disassembly information for the compiled computer program, wherein the first variable comprises a global variable;
generating a search pattern for the first variable based on the variable location information, wherein
the search pattern comprises an address range for the first variable, and
said generating the search pattern comprises creating a regular expression for the first variable;
searching the runtime disassembly information for the search pattern to identify a first program address for the first variable, wherein said searching the runtime disassembly information comprises
searching the runtime disassembly information between the address range to identify the first program address as a machine address for a change of flow pattern that matches the regular expression, and
returning the first program address with a marker flag being set; and
setting a software program watchpoint for the first variable at the first program address.

US Pat. No. 10,191,835

MULTI-THREADED DEBUGGER SUPPORT

International Business Ma...

1. A method for managing debugging requests associated with a multi-threaded application, the method comprising:receiving, by a control program, a first memory buffer including a Transmission Control Protocol (TCP) request from a debugger, responsive to a first request from a set of debugging requests being input by a user via a graphical user interface, wherein the first memory buffer is associated with a thread of a process that has been designated for debugging, wherein the first memory buffer is separate and distinct from the thread, and wherein the TCP request instructs the control program to perform at least one action on the thread;
generating a bracket for the thread, based on analysis of the first memory buffer, wherein the bracket comprises a set of control registers and an address range associated with execution of the thread;
determining whether the action associated with the TCP request to be performed on the thread is one of an execute type action and a service type action;
responsive to determining the execute type action:
waking up the thread associated with the bracket;
placing the thread on a list for execution of the action; and
executing the thread, while performing the execute type action on the thread, until said thread falls into the address range specified by the bracket, wherein the execute type action manipulates the thread:
responsive to determining the service type action:
setting up a Program Control Block (PCB) for the thread; and
performing the service type action on the thread;
generating, by the control program, debugging event information comprising results associated with one of the execute type action and the service type action, wherein the debugging event information is at least based on the manipulated thread;
inserting the debugging information into the memory buffer associated with a TCP reply of the thread;
determining whether a reply flag associated with the memory buffer is ready to be sent out;
responsive to determining that the reply flag is ready:
passing the memory buffer to the debugger in accordance with the TCP reply; and responsive to determining that the reply flag is not ready;
checking a communication socket for determining whether a further user request has been made from the debugger:
if the further request has not been made:
sleeping the debugger for a period of time, while performing a subsequent check of the reply flag; and
if the further request has been made:
retrieving a user thread associated with the further user request:
modifying a new memory buffer to process the user thread; and
processing the user thread in accordance with the TCP request.

US Pat. No. 10,191,834

METHODS AND SYSTEMS TO IDENTIFY AND REPRODUCE CONCURRENCY VIOLATIONS IN MULTI-THREADED PROGRAMS

Intel Corporation, Santa...

1. A method to identify threads responsible for causing a concurrency violation in a multi-threaded program comprising:executing, with a processor, at least one of a plurality of thread controllers inserted into respective threads of a plurality of threads of a multi-threaded program to be debugged, a first thread controller of the plurality of thread controllers controlling an order in which first operations of a first respective thread of the plurality of threads are executed relative to second operations of a second thread of the plurality of threads, the controlling of the order in which first operations are executed relative to second operations including, when a first condition is met in the first thread, the first thread controller causing the first thread to stall, the stalling of the first thread to cause the first condition to remain satisfied while the other threads of the multi-threaded program continue to execute;
causing the concurrency violation to occur based on a determination that a threshold number of a plurality of respective conditions defined in the respective thread controllers have been concurrently satisfied;
based on the occurrence of the concurrency violation, identifying the respective threads that define the respective conditions that have been satisfied as being responsible for causing the concurrency violation; and
when the threshold number of the plurality of respective conditions have not been satisfied within a threshold duration, halting the plurality of threads of the multithreaded program.

US Pat. No. 10,191,832

MULTI-LANGUAGE PLAYBACK FRAMEWORK

Microsoft Technology Lice...

1. One or more computer-readable storage media storing computer-executable instructions, which when executed by a computer, cause the computer to perform operations, the operations comprising:receiving a language-neutral script comprising a plurality of recorded actions to perform on respective user interface elements of a software product supporting multiple languages;
receiving a language file mapping properties of the respective user interface elements of the language-neutral script to properties of user interface elements in a target language among the multiple languages supported by the software product; and
executing the language-neutral script on a playback engine interfacing with a build of the software product in the target language, wherein executing the language-neutral script on the playback engine comprises:
identifying, among the plurality of recorded actions of the language-neutral script, a given recorded action corresponding to a recorded user interface element of the language-neutral script, the recorded user interface element comprising a plurality of properties, wherein each property of the plurality of properties is a different property type;
finding an under-test user interface element of the build of the software product in the target language equivalent to the recorded user interface element of the language-neutral script by performing an ordered search for the properties of the recorded user interface element within the language file, the ordered search evaluating the properties of the recorded user interface element in a predefined order that prioritizes the different property types relative to each other; and
performing the given recorded action of the language-neutral script on the matching under-test user interface element of the build of the software product in the target language.

US Pat. No. 10,191,830

DATA PROCESSING SYSTEMS FOR PROCESSING AND ANALYZING DATA REGARDING SELF-AWARENESS AND EXECUTIVE FUNCTION

EXQ, LLC, Atlanta, GA (U...

1. A data processing system for processing data regarding performance evaluation for use in the development of a first user's executive functions, the data processing system comprising:a. at least one computer processor; and
b. memory operatively coupled to the at least one computer processor; wherein the at least one computer processor is adapted for:
i. executing computer-readable instructions that, when executed by the at least one computer processor, facilitate performing an electronic activity by the first user;
ii. gathering performance data indicating the first user's performance while the first user performs the electronic activity;
iii. calculating a performance score for the first user based at least in part on the gathered performance data indicating the first user's performance;
iv. digitally storing the performance score for the first user in an electronic record associated with the first user;
v. executing computer-readable instructions that, when executed by the at least one computer processor, facilitate evaluating, by the first user, the electronic activity completed by the first user;
vi. displaying, via a graphical user interface, a visual representation that presents a replay of the first user completing the electronic activity;
vii. while displaying the visual representation presenting a replay of the first user completing the electronic activity, gathering feedback data from the first user indicating the first user's performance on the electronic activity;
viii. automatically calculating a self-awareness score of the first user based at least in part on the feedback data provided by the first user, wherein the self-awareness score of the first user is different from the performance score for the first user; and
ix. digitally storing the self-awareness score of the first user in the electronic record associated with the first user.

US Pat. No. 10,191,829

SEMICONDUCTOR DEVICE AND FAULT DETECTION METHOD THEREFOR

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a processor coupled to a storage device storing instructions for executing:
an arithmetic unit that performs processing for executing a computer program;
a plurality of sound units that convert sound data stored in a memory into a serial signal, add sampling frequency information of the sound data to the serial signal and output the serial signal to a plurality of external terminals, and convert the sound data input from one of the plurality of the external terminals into a parallel signal, add the sampling frequency information of the sound data to the parallel signal, and transfer the parallel signal to the memory;
a route switching unit that switches a transfer route of sound data input to and output from the plurality of sound units, the route switching unit being provided between the plurality of sound units and the plurality of external terminals; and
a memory transfer controller that includes a plurality of memory-transfer control units that control transmission and reception of data between the memory and the plurality of sound units, and a unit control unit that controls the plurality of memory-transfer control units,
wherein the arithmetic unit controls the route switching unit according to the computer program to configure first to third sound data transfer routes configured by one of the sound units and one of the memory-transfer control units, transfers reproduction sound data stored in the memory from the memory to a side of the external terminals via the first sound data transfer route, and transfers two recording sound data generated on account of the reproduction sound data from. the side of the external terminals to the memory via the second and third sound data transfer routes,
wherein the arithmetic unit accumulates, in the memory, two pieces of the recording sound data transferred using the second and third sound. data transfer routes and compares the reproduction sound data and the two pieces of recording sound data and detects a fault in the sound data transfer routes,
wherein the plurality of sound units generate a first count value indicating a length of a cycle of a sampling frequency of the sound data,
wherein the plurality of memory-transfer control units generate a second count mile indicating a length of a transfer interval of the sound data,
wherein the unit control unit generates a third count value indicating a length of a generation interval of a data control signal output by the sound units,
wherein, when the first count value and a first expected value indicating an expected value of the first count value set in advance do not coincide with each other, the arithmetic unit determines that the sound unit has a fault,
wherein, when the second count value and a second expected value indicating an expected value of the second count value set in advance do not coincide with each other, the arithmetic unit determines that the memory-transfer control unit has a fault, and
wherein, when the third count value and a third expected value indicating an expected value of the third count value set in advance do not coincide with each other, the arithmetic unit determines that the sound data transfer route has a fault.

US Pat. No. 10,191,827

METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR UTILIZING LOOPBACK OPERATIONS TO IDENTIFY A FAULTY SUBSYSTEM LAYER IN A MULTILAYERED SYSTEM

SANDISK TECHNOLOGIES LLC,...

1. A method for utilizing loopback operations to identify a faulty subsystem layer in a multilayered system, the method comprising:executing a plurality of loopback operations using a respective plurality of loopback points positioned among subsystem layers of a multilayered system, wherein:
the plurality of loopback operations incrementally test loopback points in the plurality of loopback points; and
each loopback operation tests loopback points that have been previously tested during previously executed loopback operations;
detecting a failed loopback operation among the plurality of loopback operations; and
identifying a faulty subsystem layer among the subsystem layers by comparing the failed loopback operation against a previously conducted successful loopback operation corresponding to a preceding subsystem layer that is adjacent to the faulty subsystem layer within the multilayered system.

US Pat. No. 10,191,826

METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR PROVIDING AN ANTICIPATED DATA INTEGRITY CHECK

KEYSIGHT TECHNOLOGIES SIN...

1. A method for providing an anticipated data integrity check, the method comprising:generating a test message including an anticipated data integrity check value (ADICV), wherein the ADICV is computed using at least one expected value based on at least one expected modification to at least one actual value in the test message by at least one system under test (SUT), wherein the ADICV is computed and inserted in the test message prior to the test message being sent to the at least one SUT for modification;
sending the test message to the at least one SUT;
receiving, from the at least one SUT, a modified version of the test message, wherein the modified version of the test message includes the ADICV; and
determining whether the at least one SUT operates as expected by analyzing the modified version of the test message using the ADICV.

US Pat. No. 10,191,825

SYSTEM AND METHOD FOR TESTING A DEVICE USING A LIGHT WEIGHT DEVICE VALIDATION PROTOCOL

WIPRO LIMITED, Bangalore...

1. A method for testing a device, the method comprising:accessing, via a testing engine, a test script corresponding to a test case for testing the device, wherein the test script comprises a set of mutually independent primitive executables;
packetizing, via the testing engine, one or more of the set of primitive executables based on a light weight device validation (LWDV) protocol, wherein the LWDV protocol is configured to represent a message as a series of data fields, wherein the data fields comprise a SYNC byte field, a start byte field, a payload length field, a session identification field, a message identification field, a sequence identification field, a test case identification field, a core data field, and a checksum field, and wherein the message identification field comprises a more bit field; and
transmitting, via the testing engine, the one or more primitive executables to the device for execution, wherein transmitting the one or more primitive executables comprises:
determining an availability of each of one or more resources in the device via the LWDV protocol; and
transmitting the one or more primitive executables to the device based on the availability.

US Pat. No. 10,191,824

SYSTEMS AND METHODS FOR MANAGING A CLUSTER OF CACHE SERVERS

MZ IP Holdings, LLC, Pal...

1. A cache data management system, comprising:a plurality of webserver computers to handle cache data requests;
a computer cluster comprising a plurality of master cache data server computers without a corresponding plurality of slave cache data server computers to store reserve cache data; and
a plurality of proxy computers in communication with the plurality of webserver computers and the computer cluster,
wherein the plurality of proxy computers routes the cache data requests from the plurality of webserver computers to the computer cluster, and
wherein each proxy computer comprises:
a sentinel module to monitor a health of the computer cluster,
wherein the sentinel module detects failures of master cache data server computers; and
a trask monitor agent to manage the computer cluster,
wherein, in response to the sentinel module detecting a failed master cache data server computer, the trask monitor agent replaces the failed master cache data server computer with an initially empty reserve master cache data server computer, and
wherein the initially empty reserve master cache data server computer is populated with the reserve cache data from a master database.

US Pat. No. 10,191,823

SYSTEM AND METHOD FOR RESTORING ORIGINAL MACHINES FROM REPLICATED MACHINES IN A SECONDARY COMPUTING ENVIRONMENT

CloudEndure Ltd., Ramat ...

1. A method for restoring an original component from a replicated component, comprising:instructing the original component in a first computing environment to boot from a restoration boot disk;
synchronizing at least one original disk of the original component with at least one corresponding replicated disk of a replicated component in a second computing environment different from the first computing environment, wherein the at least one original disk maintains at least an original operating system of the original component, wherein the replicated component is configured to function in place of the original component;
receiving a request to restore the original component; and
instructing the original component to boot from the at least one original disk, upon determination the at least one original disk and the at least one corresponding replicated disk are consistent.

US Pat. No. 10,191,822

HIGH PERFORMANCE PERSISTENT MEMORY

Rambus Inc., Sunnyvale, ...

1. A non-volatile memory module comprising:a circuit board;
a first memory device of a first memory type, the first memory device being disposed on the circuit board;
a second memory device of a second memory type, the second memory device being disposed on the circuit board, wherein the first memory device is volatile memory and the second memory device is non-volatile memory; and
a control element coupled to the first memory device and the second memory device, the control element being disposed on the circuit board, the control element to:
capture a base image of data stored in the first memory device;
store the base image of data in the second memory device;
capture incremental updates to the data stored in the first memory device;
update the base image stored in the second memory device with the incremental updates; and
in response to loss of power to the non-volatile memory module, restore the base image and any incremental updates to the first memory device.

US Pat. No. 10,191,821

COOPERATIVE DATA RECOVERY IN A STORAGE STACK

Dell Products, LP, Round...

1. A computer-implemented method of recovering data in response to a failed input/output request, the method comprising:in a memory storage stack having layers, including a lowest layer, at least one intermediate layer, and a highest layer, in a hierarchical order, wherein each layer has associated storage memory and one or more associated processor and wherein each intermediate layer has a first single layer immediately lower in hierarchical order and a second single layer immediately above in hierarchical order:
seeking data in hierarchical order from the highest layer to the lowest layer in the storage stack and responsive to a failed input/output (I/O) request for data, from a higher layer of the memory storage stack to a lower layer of the memory storage stack in the hierarchical order, generating, at the lower layer, a first help response and sending the first help response from the lower layer to the higher layer to recover the data;
at the higher layer, determining whether a recovery mechanism can fulfill the I/O request and, if not, generating a second help response and sending the second help response to a next higher layer of the memory storage stack in the hierarchical order;
at the next higher layer, determining whether a recovery mechanism can fulfill the I/O request and, if not, generating a third help response and sending the third help response to an even next higher layer of the memory storage stack in the hierarchical order;
in response to determining a recovery mechanism can fulfill the I/O request, obtaining the data using the recovery mechanism and providing the data to the higher layer in response to the I/O request; and
upon the help response reaching the highest layer of the memory storage stack, generating an error at the highest layer.

US Pat. No. 10,191,820

VIRTUAL PROXY BASED BACKUP

EMC IP Holding Company LL...

1. A backup method, comprising:configuring, by one or more processors, one or more virtual proxies associated with backup operations, wherein the one or more virtual proxies are hosted by one or more physical nodes in a cluster environment;
assigning, by one or more processors, one or more virtual machines in the cluster environment to a corresponding at least one of the one or more virtual proxies, wherein at least a subset of the one or more virtual machines is selected to be assigned to the at least one of the one or more virtual proxies based on a localization of the at least the subset of the one or more virtual machines in relation to the corresponding at least one virtual proxy;
performing, by one or more processors, data rollover during backup of at least one of the one or more virtual machines in the cluster environment that is subjected to backup using the corresponding at least one of the one or more virtual proxies to which the at least one of the one or more virtual machines is assigned.

US Pat. No. 10,191,819

DATABASE PROTECTION USING BLOCK-LEVEL MAPPING

Commvault Systems, Inc., ...

1. A data storage system for protecting database files, the system comprising:one or more primary storage devices that store a plurality of application-level blocks associated with a database, and one or more secondary storage devices that store a secondary copy of the database with a plurality of storage blocks, the plurality of storage blocks having a first granularity that is larger than a second granularity of the application-specific blocks;
an index stored in memory that maps the plurality of storage blocks with corresponding application-level blocks, wherein each of the plurality of storage blocks in the secondary copy spans a plurality of the application-level blocks;
in response to instructions to retrieve one or more requested application-level blocks associated with of a database file from the secondary copy, one or more secondary storage controller computers comprising computer hardware are configured to:
access the index that provides a mapping between the plurality of requested application-level blocks and corresponding plurality of storage blocks;
retrieve the corresponding plurality of storage blocks from the secondary copy; and
a data agent executing on one or more computer processors and configured to divide the corresponding plurality of storage blocks retrieved from the secondary copy into the one or more requested application-level blocks; and
a database application executing on one or more computer processors, the database application in communication with the data agent, the database application configured to receive the requested application-level blocks from the data agent.

US Pat. No. 10,191,818

FILTERED REPLICATION OF DATA IN DISTRIBUTED SYSTEM OF DATA CENTERS

SAP SE, Walldorf (DE)

1. A non-transitory computer readable storage medium storing instructions, which when executed by a computer cause the computer to:receive data from a first persistent storage unit associated with a primary data center, wherein receiving the data includes:
determine a modification of the data in the first persistent storage unit at regular time intervals, and
receive the data upon determining the modification of the data in the first persistent storage unit;
determine at least a part of the received data to be replicated by filtering the data based on one or more predetermined conditions, wherein the one or more predetermined conditions define relevant data to be replicated and the one or more predetermined conditions comprise filtering out the data not relevant to other data centers and filtering out restorable data; and
transmit the determined part of the data to replicate in a second persistent storage unit associated with a secondary data center to recover the part of the data during failure of the primary data center.

US Pat. No. 10,191,816

CLIENT-SIDE REPOSITORY IN A NETWORKED DEDUPLICATED STORAGE SYSTEM

Commvault Systems, Inc., ...

1. A method for restoring data to a client system from one or more secondary storage devices, the method comprising:performing with a media agent executing in or more computer processors, a secondary copy operation that copies a plurality of data blocks associated with one or more primary storage devices in a client system to one or more secondary storage devices located remotely from the one or more primary storage devices;
copying at least a portion of the data blocks and a first copy of hash signatures associated with the portion of the data blocks to a client-side repository comprising at least computer memory, wherein the client-side repository is different than the one or more secondary storage devices;
populating an index in communication with the media agent with a second copy of the hash signatures associated with the plurality of the data blocks stored in the one or more secondary storage devices;
receiving a request to restore data to the client system;
querying the client-side repository with the second copy of the hash signature from the index to determine whether the first copy of the hash signature is stored in the client-side repository;
if the querying the client-side repository with the second copy of the hash signature indicates that client-side repository is populated with the first hash signature, accessing the at least one data block associated with the restore data from the client-side repository;
if the querying the client-side repository with the second copy of the hash signature indicates that the client-side repository is not populated with the first hash signature, accessing the at least one data block associated with the restore data from the one or more secondary storage devices; and
monitoring the usage of the client-side repository and the one or more secondary storage devices and pruning the data in the client-side repository based at least in part on the percentage of data restored from the client-side repository.

US Pat. No. 10,191,815

PARALLEL NODE BACKUP FOR CSV

EMC IP Holding Company LL...

1. A method of backing up data stored on a cluster shared volume (CSV), comprising:storing on the cluster shared volume a snapshot of the cluster shared volume;
assigning to each of one or more cluster servers available to participate in backing up the cluster shared volume a task to back up a corresponding assigned portion of the snapshot to a backup storage node separate from the cluster shared volume and the one or more cluster servers, wherein the cluster shared volume is separate from the one or more cluster servers; and
monitoring the respective assigned tasks to completion,
wherein the one or more cluster servers have shared access to the snapshot as stored on the cluster shared volume and each is configured to perform the task assigned to it in parallel with any other cluster servers assigned to back up other portions of the same cluster shared volume snapshot.

US Pat. No. 10,191,814

RESTORING DATA IN A HIERARCHICAL STORAGE MANAGEMENT SYSTEM

International Business Ma...

1. A method for storing data in a hierarchical storage management (HSM) system, the method comprising:receiving, by a first controller, a request to migrate a data item to a first storage tier managed by the first controller, wherein (i) the request associates the data item with at least an initial object ID that is an object ID of a first version of the data item and (ii) the data item is associated with a HSM status parameter value that indicates that the data item is in a resident state, and, in response:
generating, by the first controller, a new object ID;
identifying, by the first controller, a first record in a data structure that includes a plurality of records based, at least in part, on the initial object ID being identical to an object ID of the first record and to a parent object ID of the first record;
replacing, by the first controller, the object ID of the first record with the new object ID;
creating, by the first controller, a new record in the data structure, wherein the new record is associated with the data item;
setting, by the first controller, an object ID field of the new record and a parent object ID field of the new record to the initial object ID; and
storing, by the first controller, the data item to the first storage tier.

US Pat. No. 10,191,813

DATA REPLICATION SNAPSHOTS FOR PERSISTENT STORAGE USING OPERATION NUMBERS

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:maintaining a master copy and a slave copy of a data volume, the master copy including data for a plurality of operations having respective sequential operation numbers, the data for the plurality of the operations being replicated to the slave copy;
generating a snapshot of the master copy, the snapshot being assigned a next operation number in an operation number sequence, the snapshot comprising snapshot data;
writing the snapshot data, as well as the operation number and metadata for the snapshot, to persistent storage; and
while writing the snapshot data to the persistent storage, processing subsequent input/output (I/O) operations by the master copy.

US Pat. No. 10,191,812

RECOVERY MECHANISM FOR LOW LATENCY METADATA LOG

Pavilion Data Systems, In...

1. A storage server comprising:a plurality of physical drives;
a management controller comprising a first memory; and
an input/output (IO) controller operatively coupled to the plurality of physical drives and to the management controller, the IO controller comprising a second memory, wherein the IO controller is to:
generate a first metadata update for a first page of a first metadata table, wherein the first metadata update is associated with storage of first data in at least one of a first physical block address (PBA) on a first physical drive of the plurality of physical drives or a first virtual block address (VBA) mapped to the first PBA;
generate a second metadata update for a second page of one of the first metadata table or a second metadata table, wherein the second metadata update is associated with at least one of the first VBA or the first PBA;
write a first cache entry to a first cache in a first memory of the management controller, the first cache entry comprising the first metadata update and the second metadata update;
write a copy of the first cache entry to a second cache in a second memory of the IO controller, wherein the second cache is a copy of the first cache; and
increment a commit pointer in the first cache and the second cache to indicate that the data has been stored in the first PBA and that all metadata updates associated with storage of the data at the first PBA have been committed.

US Pat. No. 10,191,811

DUAL BOOT COMPUTER SYSTEM

QUANTA COMPUTER INC., Ta...

1. A computer system, comprising:a processor;
a complex programmable logic device (CPLD);
a locally protected primary boot;
a locally modifiable secondary boot, wherein the CPLD is connected to the processor, and configured to control the processor with regard to selecting either the locally protected primary boot or the locally modifiable secondary boot, wherein the locally protected primary boot and the locally modifiable boot are individually partitioned, and the way the locally protected primary boot being partitioned is different from the way the locally modifiable boot being partitioned;
a computer-readable memory storing instructions which, when executed by the processor, causes the processor to perform operations comprising:
commencing a first boot sequence for the computer system with the primary boot;
restarting the computer system and commencing, in response to the restarting, a second boot sequence with the locally modifiable secondary boot;
if the second boot sequence with the secondary boot is successful, storing a copy of the secondary boot in a partition of the primary boot as one of a ONIE u-boot code, a u-boot environment, or a kernel code; and
if the second boot sequence with the secondary boot fails, restarting the computer system and re-commencing a third boot sequence with the primary boot.

US Pat. No. 10,191,810

MOBILE TERMINAL AND RELATED REPAIR METHOD

MEDIATEK SINGAPORE PTE. L...

1. A repair method for a mobile terminal, comprising:obtaining a current storage integrity information of a system partition of the mobile terminal;
matching the current storage integrity information and an original storage integrity information; and
connecting to a server, and obtaining an original system partition document from the server, and repairing the system partition according to the original system partition document when the matching fails,
wherein the step of connecting to the server, and obtaining original system partition document from the server, and repairing the system partition according to the original system partition document when the matching fails further comprising:
checking whether a logic block address of a storage device of the mobile terminal is damaged;
if the logic block address is not damaged, finding abnormal document of the system partition, and repairing the abnormal document according to the original system partition document; and
if the logic block address is damaged, connecting to the server, acquiring the original system partition document from the server, and repairing all document of the system partition according to the original system partition document.

US Pat. No. 10,191,809

CONVERTING A DATA CHUNK INTO A RING ALGEBRAIC STRUCTURE FOR FAST ERASURE CODING

International Business Ma...

1. A method comprising:at a storage manager of a storage system:
arranging a first data chunk into a ring structure;
tagging the first data chunk by appending extra data to the ring structure;
performing erasure coding on the first data chunk utilizing only exclusive or (XOR) operations and the ring structure, wherein erasure coded encoded data resulting from the erasure coding is written to a persistent storage device; and
maintaining an index pointer that references a portion of the ring structure;
wherein the ring structure allows for multiplication of data included in the first data chunk to be implemented by rotation of the data utilizing the index pointer, thereby increasing efficiency of the storage system as the multiplication is simplified to an adjustment of the index pointer.

US Pat. No. 10,191,808

SYSTEMS AND METHODS FOR STORING, MAINTAINING, AND ACCESSING OBJECTS IN STORAGE SYSTEM CLUSTERS

QUALCOMM Incorporated, S...

1. A method, implemented by processor-based logic of a storage system storing source objects as a plurality of fragments upon storage nodes of a plurality of cluster instances of storage system infrastructure components comprising a cluster set, wherein each cluster instance of the plurality of cluster instances operates as a unit for providing reliable storage of a different portion of a source object stored by the storage system, the method comprising:generating a plurality of first encoding fragments from the source object using a first encoding;
partitioning the plurality of first encoding fragments into a plurality of disjoint sets of first encoding fragments, wherein each set of first encoding fragments of the plurality of disjoint sets of first encoding fragments includes a plurality of first encoding fragments;
assigning a first set of first encoding fragments of the plurality of disjoint sets of first encoding fragments to a first cluster instance of the plurality of cluster instances, wherein the first set of first encoding fragments comprise a portion of the plurality of first encoding fragments of the source object to be stored upon the storage nodes of the first cluster instance of the plurality of cluster instances;
assigning a second set of first encoding fragments of the plurality of disjoint sets of first encoding fragments to a second cluster instance of the plurality of cluster instances, wherein the second set of first encoding fragments comprise a different portion of the plurality of first encoding fragments of the source object to be stored upon the storage nodes of the second cluster instance of the plurality of cluster instances;
generating a plurality of second encoding fragments from the first set of first encoding fragments using a second encoding, wherein the plurality of second encoding fragments include the plurality of first encoding fragments of the first set of first encoding fragments and one or more repair fragments generated from the first encoding fragments of the first set of encoding fragments; and
generating a plurality of third encoding fragments from the second set of first encoding fragments using a third encoding, wherein the plurality of third encoding fragments include the plurality of first encoding fragments of the second set of first encoding fragments and one or more repair fragments generated from the first encoding fragments of the second set of encoding fragments.

US Pat. No. 10,191,807

MEMORY SYSTEMS AND OPERATION METHOD THEREOF

SK hynix Inc., Icheon-si...

14. A memory system, comprising:a memory controller including a first-type error correction circuit suitable for generating a first error correction code using a first write data which is a portion of a write data form a host, and a second-type error correction circuit suitable for generating a second error correction code using a second write data which is a remaining portion of the write data, wherein error correction algorithms used by the first-type error correction circuit and the second-type error correction circuit are different from each other; and
a memory module including a plurality of first memory devices suitable for storing the first write data and the first error correction code, and one or more second memory device suitable for storing the second write data and the second error correction code.

US Pat. No. 10,191,806

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method for a rewritable non-volatile memory module comprising a plurality of memory cells, the decoding method comprising:reading, through a memory interface coupled to the rewritable non-volatile memory module, first data from a plurality of first memory cells under a read voltage among the memory cells;
performing, by an error checking and correcting circuit, a first decoding operation on the first data based on a first strict level of a plurality of predetermined strict levels of locating an error bit in the first data;
performing, by the error checking and correcting circuit, the first decoding operation again or a second decoding operation on the first data based on a second strict level or a third strict level of a plurality of predetermined strict levels of locating an error bit in the first data if the first decoding operation fails, comprising:
if an iteration number of the first decoding operation reaches a predetermined number, switching to the second strict level which is higher than the first strict level and performing the second decoding operation based on the second strict level, in order to reduce a probability of a bit being wrongly flipped in the second decoding operation;
if a number of bits flipped by the first decoding operation is zero, switching to the third strict level which is lower than the first strict level and performing the second decoding operation based on the third strict level, in order to raise a probability that at least one bit is flipped in the second decoding operation; and
otherwise, performing the first decoding operation on the first data based on the first strict level again; and
outputting the decoded first data by the error checking and correcting circuit.

US Pat. No. 10,191,805

SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor memory device, comprising:a memory cell array including first and second bank arrays, each bank array including first and second sub arrays;
an error correction circuit configured to perform an error correction code (ECC) encoding on write data to be stored in the memory cell array, and configured to perform an ECC decoding on read data from the memory cell array; and
a control logic circuit configured to control access to the memory cell array and configured to generate an engine configuration selection signal and a density mode signal based on a command,
wherein the error correction circuit is configured to reconfigure a number of units for which ECC including the ECC encoding and the ECC decoding is performed, in response to the engine configuration selection signal,
wherein each unit for which ECC is performed corresponds to correcting an error bit among the read data having n bits, wherein n is a natural number greater than 2 and is variable in response to the engine configuration selection signal,
wherein when the density mode signal indicates a first density mode and the engine configuration selection signal indicates a first engine configuration mode, the error correction circuit is configured to operate as one ECC engine configured to perform an ECC encoding on 2h-bit write data to generate (h+1)-bit parity data, configured to perform an ECC decoding on 2h-bit read data and (h+1)-bit read parity data, and configured to store the 2h-bit write data and the (h+1)-bit parity data in the first bank array, wherein h is a natural number equal to or greater than two, and
wherein when the density mode signal indicates a second density mode and the engine configuration selection signal indicates a second engine configuration mode, the error correction circuit is configured to operate as a plurality of ECC engines, each ECC engine configured to perform an ECC encoding on 2f-bit write data of 2h-bit write data to generate (f+1)-bit parity data, and configured to perform an ECC decoding on 2f-bit read data and (f+1)-bit read parity data, and the ECC engines configured to store a group of the 2f-bit write data in a first sub array of the first bank array and to store a group of the (f+1)-bit parity data in a first sub array of the second bank array, wherein f is a natural number smaller than h.

US Pat. No. 10,191,804

UPDATING RELIABILITY DATA

Micron Technology, Inc., ...

1. An apparatus, comprising:a memory device;
a reliability circuit coupled to the memory device and configured to receive hard data from the memory device and to determine reliability data assigned thereto, the reliability data comprising a first reliability data value in response to the hard data comprising a first value or comprising a second reliability data value in response to the hard data comprising a second value;
an error correction circuit coupled to the reliability circuit and configured to receive the hard data and the reliability data from the reliability circuit, wherein the error correction circuit is further configured to:
iteratively compute parity data for the hard data; and
increment or decrement the reliability data once per L-number of layers of parity data, wherein one iteration includes a plurality of layers of parity data.

US Pat. No. 10,191,803

REWRITING FLASH MEMORIES BY MESSAGE PASSING

California Institute of T...

1. A data storage device comprising:a host interface configured to receive a binary representation of a message m;
a non-volatile memory device;
a memory device interface coupled to the non-volatile memory device; and
a controller configured to:
receive the message m for storing the message m into n cells of the non-volatile memory device;
read a current state s of the n cells of the non-volatile memory device in which a previously received message has been stored;
determine a vector x based on the message m and the current state s of the n cells, wherein the vector x represents the message m and can be written into the n cells over the current state s of the n cells without erasing the n cells; and
if the vector x cannot be determined,
provide a FAIL indication; and
implement an error handling routine;
otherwise,
provide the vector x to the memory device interface for storing the vector x into the n cells of the non-volatile memory device without erasing the n cells.

US Pat. No. 10,191,802

EXTRACT-TRANSFORM-LOAD DIAGNOSTICS

Oracle International Corp...

1. A method for diagnosing extract-transform-load (ETL) errors in a cloud-based data integration system, comprising:initiating, by a computer system, a first process of an extract-transform-load process within the cloud-based data integration system, the first process comprising extracting data from a cloud-based application;
receiving, by the computer system, a first data set associated with the first process;
initiating, by the computer system, a second process of the extract-transform-load process within the cloud-based data integration system, the second process comprising caching the extracted data into a first schema, and the first schema being associated with the cloud-based application;
receiving, by the computer system, a second data set associated with the second process;
initiating, by the computer system, a third process of the extract-transform-load process within the cloud-based data integration system, the third process comprising loading the extracted data from a first schema to a second schema, the second schema being associated with a cloud-based data warehouse, and the first process, the second process, and the third process being distinct processes performed at different times during the extract-transform-load process;
receiving, by the computer system, a third data set associated with the third process;
determining, by the computer system, a first error and a second error in the extract-transform-load process based at least in part on the first data set, the second data set, or the third data set;
determining, by the computer system, a first characteristic associated with the first error, the first characteristic indicating at least that the first error is correctable;
determining, by the computer system, a second characteristic associated with the second error, the second characteristic indicating at least that the second error is fault tolerant;
rejecting, by the computer system, based at least in part on the first characteristic, at least a portion of data associated with the first error; and
transforming, by the computer system, based at least in part on the second characteristic, at least a portion of data associated with the second error.

US Pat. No. 10,191,801

ERROR CORRECTION CODE MANAGEMENT OF WRITE-ONCE MEMORY CODES

TEXAS INSTRUMENTS INCORPO...

1. An electronic device comprising:a write-once memory (WOM) device; and
a memory controller that includes:
a host interface to receive a data word including a first symbol and a second symbol, each of the first and second symbols having at least two bits;
a WOM controller to encode the first symbol and the second symbol and outputs a WOM-encoded word that includes a first WOM code corresponding to the first symbol and a second WOM code corresponding to the second symbol, wherein each of the first and second WOM codes include at least three bits with at least two of the at least three bits having the same logic value;
an error correction code (ECC) controller to encode the WOM-encoded word and output an ECC-encoded word that includes the first and second WOM codes and a first set of ECC bits corresponding to a first write operation; and
a memory device interface to write the ECC-encoded word to a first address of the WOM device as part of the first write operation.

US Pat. No. 10,191,800

METRIC PAYLOAD INGESTION AND REPLAY

Cisco Technology, Inc., ...

1. A method for metric payloads ingestion and playback, the method including:receiving, by a collector executing on a server, time series of metric payloads for a plurality of performance metrics indicating performance of a node or machine, wherein the collector is communicatively connected to a coordinator that provides collectors with information on a plurality of aggregators including assignments of the performance metrics to each aggregator;
storing, by a database executing on the server, the received time series of metric payloads in a payload tracking table of a database, wherein the storing includes:
storing the received time series of metric payloads in different layers and partitioned regions of the payload tracking table, wherein the layers represent time ranges corresponding to time points when the time series of metric payloads are received, and wherein the partitioned regions are assigned to received certain ones of the received time series of metric payloads; and
replaying the stored time series of metric payloads from a select one or more of the partitioned region or layer or both.

US Pat. No. 10,191,799

BER MODEL EVALUATION

SanDisk Technologies LLC,...

1. A storage system comprising:a memory; and
a controller configured to:
read a data set from a target storage location of the memory;
measure a first parameter and a second parameter of the data set to obtain a first actual value of the first parameter and a second actual value of the second parameter;
apply the first actual value or the second actual value to a model; and
based on the application, identify a deviation level of the target storage location relative to the model.

US Pat. No. 10,191,798

EXTENDED INTERFRAME SPACE (EIFS) EXEMPTIONS

QUALCOMM Incorporated, S...

1. An apparatus for wireless communications, comprising:a first interface configured to obtain a frame received over a medium;
a processing system configured to:
detect an occurrence of an error when processing the frame;
determine an intended recipient of the frame based on information included in the frame; and
after detecting the occurrence of the error, select a deferral period based, at least in part, on the determination, wherein the selection comprises selecting a first deferral period if the determination is that the apparatus is not the intended recipient of the frame, wherein the first deferral period is greater than a second deferral period; and
a second interface configured to refrain from outputting a frame for transmission on the medium during the selected deferral period.

US Pat. No. 10,191,797

ELECTRONIC SYSTEM GENERATING MULTI-PHASE CLOCKS AND TRAINING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. An electronic system comprising:a memory controller configured to generate a plurality of controller clocks having different phases from one another based on a reference clock signal, and to transmit a first clock and a second clock having phase difference from each other between the plurality of controller clocks, the phase difference between the first clock and the second clock is 90 or 270 degrees; and
a memory configured to generate a plurality of internal clocks having different phases from one another by receiving the first clock and the second clock, and selectively output a plurality of odd-ordered data or a plurality of even-ordered data among a plurality of data in synchronization with the plurality of internal clocks,
wherein the memory comprises:
a clock receiver configured to generate a first differential clock and a second differential clock in response to the first and second clocks;
a duty cycle correction portion configured to correct duty ratios of the first differential clock and the second differential clock;
a clock division portion configured to output the first and second groups of clocks by dividing an output of the duty cycle correction portion; and
a data input/output portion configured to transmit the plurality of the odd-ordered data or the plurality of the even-ordered data to the memory controller in response to the first group of clocks and an even-odd flag signal.

US Pat. No. 10,191,796

SYSTEM AND METHOD FOR STATISTICAL APPLICATION-AGNOSTIC FAULT DETECTION IN ENVIRONMENTS WITH DATA TREND

Open Invention Network, L...

1. A system, comprising:one or more memory locations configured to store one or more applications and one or more statistical models, wherein each of said one or more application is comprised of one or more processes and threads;
one or more Central Processing Units operatively connected to said one or more memory locations, configured to execute said one or more applications on a host with a host operating system, and configured to generate one or more statistical events for said one or more executing applications and said host operating system; and
a fault detector configured to create one or more statistical models for the execution of said one or more applications, each comprising: one or more of calculating one or more distributions for said one or more statistical events, de-trending the data for said one or more statistical events, transforming the data for said statistical events, and detecting faults in the execution of said one or more applications by detecting significant deviation of recent statistical events from said one or more distributions.

US Pat. No. 10,191,795

METHOD AND SYSTEM FOR TIMEOUT MONITORING

Infineon Technologies AG,...

1. A method for timeout monitoring of commands comprising:assigning, by a first microcontroller, each one of the commands to a corresponding one of a plurality of timeout timers in a FIFO manner when corresponding commands are to be transmitted by the first microcontroller over a high speed serial link (HSSL) to a second microcontroller within a same system;
for a first type of command, transmitting over the HSSL, by the first microcontroller, a subsequent command only after receiving a command acknowledge or a timeout to a previously transmitted command; and
for a second type of command, transmitting over the HSSL, by the first microcontroller, a subsequent command before a command acknowledge or a timeout to a previously transmitted command has been received.

US Pat. No. 10,191,793

MICROPROCESSOR DEVICE WITH RESET TIMER

Nordic Semiconductor ASA,...

1. A microprocessor device comprising a timer capable of resetting the device and a plurality of hardware registers arranged so that a collective predetermined state of the registers fixed by a hard-wired logical relationship between the registers resets the timer, the device further comprising software having a plurality of functions arranged to place said registers in said predetermined state if each of said functions has executed properly.

US Pat. No. 10,191,792

APPLICATION ABNORMALITY DETECTION

International Business Ma...

1. A method of operating a computer system comprising:collecting, from the computer system, data indicative of variations in throughput and response time over a period of time;
calculating processing power of the computer system over the period of time;
recording a maximal power;
calculating a standard deviation of the response time (RT-StdDev);
recording the standard deviation of the response time corresponding to a time of the maximal power (RT-StdDevMaxPower); and
generating a notification that the computer system is in a bottleneck state using a comparison of a current processing power to the maximal power and a comparison of the RT-StdDev to the RT-StdDevMaxPower.

US Pat. No. 10,191,791

ENHANCED ADDRESS SPACE LAYOUT RANDOMIZATION

Intel Corporation, Santa...

1. An enhanced address space layout randomization apparatus comprising:a linear address space comprising a metadata data structure;
metadata logic to generate a metadata value; and
enhanced address space layout randomization (ASLR) logic to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address,
the address pointer corresponding to an apparent address in an enhanced address space, a size of the enhanced address space greater than a size of the linear address space.

US Pat. No. 10,191,790

DATA STORAGE DEVICE AND ERROR RECOVERY METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A data storage device comprising:a nonvolatile memory device including a memory block having a plurality of memory regions; and
a controller suitable for searching a first memory region for which error correction is passed, by scanning the plurality of memory regions in a reverse order of a write sequence for the memory block, determining a target memory region in the memory block based on data stored in the first memory region, and performing a recovery operation for the target memory region,
wherein, when it is determined that transaction-begin data is stored in the first memory region, the controller determines a memory region which is indicated by the transaction-begin data, as the target memory region.

US Pat. No. 10,191,789

TRACING SYSTEM OPERATIONS ACROSS REMOTE PROCEDURE LINKAGES TO IDENTIFY REQUEST ORIGINATORS

CrowdStrike, Inc., Irvin...

1. A computing device comprising:one or more processors; and
a security agent configured to be operated by the one or more processors to perform operations including:
receiving one or more event notifications respectively associated with one or more kernel-mode events;
determining, based on the one or more event notifications, that the one or more kernel-mode events are associated with user-mode processing by a remote-procedure-call-utilizing (RPC-utilizing) process of a request message;
retrieving the request message based on information included in one or more remote procedure call (RPC) data structures and based on the one or more event notifications, wherein the retrieving includes:
determining a thread environment block (TEB) of a worker thread that is associated with the user-mode processing by the RPC-utilizing process of the request message, and
tracing from the TEB to the request message through an RPC-specific field of an operating system (OS) data structure; and
identifying an originator of the request message based on metadata of the request message.

US Pat. No. 10,191,788

PROGRAMMABLE DEVICE, HEIRARCHICAL PARALLEL MACHINES, AND METHODS FOR PROVIDING STATE INFORMATION

Micron Technology, Inc., ...

1. A method of providing state information from a parallel machine to another device, wherein the parallel machine includes a plurality of programmable elements, wherein each of the programmable elements is configured to have a corresponding state, comprising:determining state information, wherein the state information comprises the state of each of the programmable elements in the parallel machine;
compressing the state information, wherein compressing the state information comprises aggregating final states in a finite state machine implemented on the parallel machine; and
providing the compressed state information to the other device.

US Pat. No. 10,191,787

APPLICATION PROGRAM INTERFACE FOR INTERFACE COMPUTATIONS FOR MODELS OF DISPARATE TYPE

Ansys, Inc., Canonsburg,...

1. A computer-implemented method for performing a simulation of a physical system by interfacing between a model interface of a physical system and a solver interface of a solver model, the method comprising:accessing a virtual object model of a physical object, the virtual object model having the model interface;receiving, from a solver interface, data comprising at least one solver function;mapping the at least one solver function to at least one modeling function;providing, to a model interface, data comprising the at least one modeling function corresponding to the at least one solver function;detecting a presence of an event occurrence based on a plurality of interface functions, wherein the plurality of interface functions are mapped to the at least one solver function and the at least one modeling function;
providing, to the solver interface, the plurality of interface functions to determine a solution;
receiving, from the solver interface, the solution;
initiating rendering of the solution on a graphical user interface; and
creating or modify the physical object based at least in part on the solution.

US Pat. No. 10,191,786

APPLICATION PROGRAM INTERFACE MASHUP GENERATION

FUJITSU LIMITED, Kawasak...

1. A method of generating application program interface (API) mashups, the method comprising:grouping, via at least one processor, a plurality of APIs into a plurality of sub-clusters based on at least one keyword for each API of the plurality of APIs;
identifying, via the at least one processor, at least one keyword combination for the plurality of sub-clusters based on real-world data and two or more keywords for the plurality of sub-clusters;
determining, via the at least one processor, one or more possible API mashups including two or more APIs of the plurality of APIs for the at least one keyword combination;
determining, via the at least one processor, a similarity score for each possible API mashup of the one or more possible API mashups; and
identifying, via the at least one processor, at least one API mashup from the one or more possible API mashups based on the similarity score for each possible API mashups of the one or more possible API mashups.

US Pat. No. 10,191,784

ADAPTIVE QUEUED LOCKING FOR CONTROL OF SPECULATIVE EXECUTION

Intel Corporation, Santa...

1. An apparatus, comprising:a queue controller to control removal of threads from a queue, the queue to contain threads that are waiting to be permitted to speculatively execute in a critical section of a multi-threaded program;
a first thread associated with a head node of the queue, the queue controller to control the removal of threads from the queue in response to operations performed by the first thread, and when a number of threads executing in the critical section reaches a quota, the first thread to retry speculatively executing in the critical section and to remain associated with the head node of the queue to prevent a second thread corresponding to a second node of the queue from retrying speculatively executing in the critical section; and
an adjuster to change a number of threads permitted to speculatively execute based on a rate of threads currently speculatively executing transactions in the critical section, the adjuster is implemented via a logic circuit.

US Pat. No. 10,191,783

UDP MULTICAST OVER ENTERPRISE SERVICE BUS

Red Hat, Inc., Raleigh, ...

1. A method comprising:receiving application data from an event listener comprising a transport component and a web component by a processing device of an infrastructure service system, wherein the infrastructure service system comprises a first enterprise service bus (ESB) associated with an enterprise messaging system, wherein the application data comprises business rules to be shared between a first application in communication with the first ESB and a second application in communication with a second ESB associated with the enterprise messaging system;
forming, using the application data, a message by the processing device; and
transmitting, by the processing device, via the first ESB, the message via User Datagram Protocol (UDP) multicast over a public channel to a multicast address associated with a plurality of receivers associated with the second ESB, wherein the second ESB is subscribed to the multicast address.

US Pat. No. 10,191,782

SYSTEM TO SCHEDULE AND PERFORM AUTOMATED SOFTWARE TASKS DURING UNATTENDED SYSTEM TIME USING PREDICTED KNOWLEDGE OF INDIVIDUAL USER BEHAVIOR

Dell Products, LP, Round...

1. A method, comprising:determining, by an information handling system, a future predicted system time that an unattended task is to be executed on the information handling system, the future predicted system time based at least in part on first usage parameters for a user of the information handling system, the first usage parameters indicating first periods of usage activity and second periods of inactivity associated with the information handling system recorded during a first duration, and the first usage parameters indicating critical system parameters relevant to the present state of the information handling system;
ensuring, by the information handling system, that system resources of the information handling system are available for the unattended task to be able to complete;
in response to an arrival of the future predicted system time, executing, by the information handling system, the unattended task;
incrementing, by the information handling system, a count of wake events in response to the executing of the unattended task at the arrival of the future predicted system time;
comparing, by the information handling system, the count of the wake events to a threshold value, the threshold value based on the first periods of usage activity and the second periods of inactivity; and
recording, by the information handling system, the future predicted system time as a wake event of the wake events in response to the count of the wake events being less than the threshold value.

US Pat. No. 10,191,781

CLASSIFICATION BASED AUTOMATED INSTANCE MANAGEMENT

SERVICENOW, INC., Santa ...

1. A method for commissioning and decommissioning an application instance on a computer, the method comprising:receiving, via a processor, a request to commission an application instance on the computer, the request including a classification metric for the application instance, wherein the classification is indicative of whether the application instance is an internal instance or an external instance, an operational environment for the application instance, an operational type for the application instance, or a combination thereof;
automatically commissioning, via the processor, the application instance based at least in part on the classification metric;
automatically monitoring, via the processor, the application instance based on the classification metric by determining whether the application instance has been extended or whether the application instance has expired;
automatically decommissioning, via the processor, the application instance when the application instance has expired, wherein automatically decommissioning the application instance comprises:
identifying and evaluating one or more decommissioning policies associated with the classification metric;
archiving the application instance, comprising generating a backup of the application instance for storage in an online backup system or at an offline backup facility; and
reclaiming resources utilized by the application instance, comprising deleting application instance data from one or more data storage systems, removing records associated with the application instance data from one or more databases, and updating an inventory tracking system to indicate that the resources are available or unassigned.

US Pat. No. 10,191,779

APPLICATION EXECUTION CONTROLLER AND APPLICATION EXECUTION METHOD

FUJITSU LIMITED, Kawasak...

1. An application execution controller, configured to instruct an execution of an application in a computing environment having available to allocate to executing applications: one or both of different amounts of computing resources in a plurality of computing resource categories and different types of computing resources in a plurality of computing resource categories; the controller comprising a memory and a processor coupled to the memory, the processor being configured:to collect available resource information detailing configurations of computing resources available to execute the application, wherein the configurations each include an indication of respective an amount and type of computing resources available in each category among the plurality of computing resource categories;
to collect application execution scalability information including, in respect of computing resources in at least one of the categories among the plurality of computing resource categories, an indication of how the one of or both of different amounts and types of computing resources in the respective computing resource category correlate with execution rate of a first portion of the application, the application execution scalability information being specific to an execution mode for the first portion of the application;
to collect performance target information including an indication of one or more performance targets for the execution of the application;
to perform a selection of a configuration from among the configurations detailed in the available resource information which, based on the application execution scalability information will come closest out of the configurations to meeting, the one or more performance targets; and
to instruct the computing environment to execute the first portion of the application using the selected configuration; wherein
for a change in an execution mode during the execution of the application caused by progressing from the first portion of the application to a forthcoming second portion:
the processor is configured to collect an updated version of the application execution scalability information, specific to the changed execution mode for the forthcoming second portion of the execution of the application, and to use the updated version to update a currently held version of the application execution scalability information; and
using the updated version of the application execution scalability information, the processor is configured to perform an updated selection of configuration from among the configurations detailed in the available resource information which, based on the updated application execution scalability information will come closest out of the configurations to meeting the one or more performance targets specified in the performance target information; wherein
the application execution scalability information is provided as a scalability matrix, the scalability matrix including an entry for each pair of factors from among factors comprising each category from among the plurality of computing resource categories and execution rate, the entry representing an effect of a proportional change along a linear scale representing usage of respective different amounts and types of a first factor from a pair of factors on the respective amount and type required of a second factor from the pair of factors, in terms of a proportional change along a linear scale representing the respective different amounts and types of the second factor, and
the processor is configured to instruct the computing environment to perform the execution of the forthcoming second portion of the application using the updated selection of configuration.

US Pat. No. 10,191,778

SYSTEMS, APPARATUS AND METHODS FOR MANAGEMENT OF SOFTWARE CONTAINERS

TURBONOMIC, INC., Boston...

1. A computer-implemented method, comprising:determining, by a pod manager running on a data processor in a container system, a computer resource bundle to be purchased for a pod in the container system using virtual currency units, wherein the pod is a cluster of two or more containers in the computer system sharing at least one resource;
identifying multiple resource providers in the container system offering the computer resource bundle;
determining a purchase price for the computer resource bundle, in virtual currency units, for each of the multiple resource providers;
automatically selecting, by the pod manager, a first one of the multiple resource providers based at least in part on the purchase price for the computer resource bundle for each of the multiple resource providers;
allocating the computer resource bundle from the selected first one of the multiple resource providers to the pod; and
determining, following an increase in the purchase price for the computer resource bundle offered by the selected first one of the multiple resource providers, that the pod is to be moved from the selected first one of the multiple resource providers to a second one of the multiple resource providers based at least in part on a lower purchase price for the computer resource bundle offered by the second one of the multiple resource providers.

US Pat. No. 10,191,777

SPECIALLY PROGRAMMED COMPUTING SYSTEMS WITH ASSOCIATED DEVICES CONFIGURED TO IMPLEMENT CENTRALIZED SERVICES ECU BASED ON SERVICES ORIENTED ARCHITECTURE AND METHODS OF USE THEREOF

GuardKnox Cyber Technolog...

1. A system, comprising:an electronic control unit having a service oriented architecture (SOA ECU);
wherein the SOA ECU is located within a vehicle;
wherein the SOA ECU comprises:
at least one partition that comprises:
at least one SOA server;
wherein the at least one SOA server is configured to provide:
i) at least one first service to at least one first external client that is located outside the vehicle;
wherein the at least one SOA server is configured to assign at least one first service dedicated processing resource and at least one first service dedicated memory resource to provide the at least one first service;
a separation kernel; and
wherein the separation kernel is configured to ensure that
i) the at least one first service dedicated processing resource is allocated from at least one first respective partition dedicated processing resource and
ii) the at least one first service dedicated memory resource is allocated from at least one first respective partition dedicated memory resource.

US Pat. No. 10,191,776

INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, INFORMATION PROCESSING PROGRAM, AND STORAGE MEDIUM

FUJIFILM CORPORATION, To...

1. An information processing system comprising:a control device that transfers data that is a processing target and a control command describing processing content for the data;
a plurality of processing devices that are provided outside the control device and perform processing according to the control command on the data in a case where the control command is transferred from the control device; and
a planning device that determines a division size of the data such that a difference between a transfer time to transfer divided data obtained by dividing the data from the control device to each of the plurality of processing devices and a processing time to process the divided data in the processing device falls within a predetermined range, on the basis of an amount of the data, the transfer time, and the processing time,
wherein the control device sequentially transfers the divided data obtained by dividing the data according to the division size determined by the planning device to any one of the plurality of processing devices,
each of the plurality of processing devices performs processing according to the corresponding control command on the previously transferred divided data in parallel with the transfer of the divided data from the control device to the processing device in a case where the control command is transferred from the control device,
the transfer time and the processing time are determined in advance for each of the plurality of processing devices, and
the planning device determines the division size for each of the plurality of processing devices, calculates a processing completion time from start of transfer of the divided data from the control device to each of the plurality of processing devices to end of transfer of all pieces of data obtained by processing the divided data from each of the plurality of processing devices to the control device on the basis of the determined division size, and determines a processing device having a shortest processing completion time to be a transfer destination of the divided data of the control device.

US Pat. No. 10,191,775

METHOD FOR EXECUTING QUERIES ON DATA CHUNKS USING GRAPHIC PROCESSING UNITS

SQREAM TECHNOLOGIES LTD.,...

1. A method for optimizing the throughput of hardware accelerators (HWAs), by maintaining a maximal rate of data transfer from storage units to the said HWAs, said method comprising the steps of:storing and managing, by a File-System, access to data on a plurality of storage modules in the computerized abstraction system's environment;
allocating a memory cache space, per each of the HWAs, to minimize the time required for reading data from storage instances to target HWAs;
allocating spoolers, per each of the HWAs, to buffer the input data, and ensure a continuous flow of input data in the target HWA's maximal input bandwidth;
wherein the said memory cache space is optimally allocated, by an Opaque File System, to cache the input data, and minimize the time required for reading data from storage modules to target HWAs;
wherein the said spoolers are optimally allocated, by the Opaque File System, to buffer the input data and ensure a continuous flow of input data, in the target HWA's maximal input bandwidth; and
wherein the allocation of said memory cache space and said spoolers is adapted dynamically according to the current quantities and properties of HWA and storage instances within the computerized system.

US Pat. No. 10,191,773

METHODS, SYSTEMS, AND DEVICES FOR ADAPTIVE DATA RESOURCE ASSIGNMENT AND PLACEMENT IN DISTRIBUTED DATA STORAGE SYSTEMS

Open Invention Network LL...

1. A distributed data storage system for automatic constraint-based data resource arrangement, the data storage system comprising:a plurality of data storage components communicatively coupled to each other, each of said data storage components comprising at least one data resource selected from a data storage media for storing client-related digital information, a data processor for processing said client-related digital information, and a network communications interface for communicating said client-related digital information; and
a constraint engine comprising a constraint processor and a constraint database, said constraint database receiving and storing changeable digital constraint parameters indicative of permissible operational constraints on said data storage system, and said constraint processor automatically determining permissible data resource assignment arrangements in accordance with said changeable digital constraint parameters so to assign at least some of said data resources for use with said client-related digital information in compliance with said permissible operational constraints on said data storage system;
wherein, in response to an operational change to said data storage system, at least some said data resource are automatically reassigned from a current permissible data resource assignment arrangement to an alternate permissible data resource assignment arrangement and wherein a reassignment is selected when a number of reassignment steps is less than a designated reassignment threshold and thereby determined to comply with a designated set of said changeable digital constraint parameters.

US Pat. No. 10,191,771

SYSTEM AND METHOD FOR RESOURCE MANAGEMENT

HUAWEI TECHNOLOGIES CO., ...

1. A method of managing resources of a computing system, the method comprising:monitoring, at a distributed resource management system, a total utilization of a non-elastic resource of the resources of the computing system being used by a plurality of workloads during runtime of the plurality of workloads, wherein monitoring includes obtaining a current utilization of the non-elastic resource by each workload and a resource allocation limit for the non-elastic resource for each workload, each workload associated with one of a plurality of tenants;
determining, at a distributed resource management system, whether a utilization condition is met based on the total utilization of the non-elastic resource;
after determining that both the utilization condition is met, and the current utilization of the non-elastic resource by at least two workloads of the plurality of workloads exceeds its respective resource allocation limit for the non-elastic resource, selecting, at the distributed resource management system, at least one of the at least two workloads on which to perform an enforcement action based on at least one selection criteria; and
performing, at the distributed resource management system, the enforcement action on each selected workload, the enforcement action comprising one of terminating, suspending, or checkpointing each selected workload;
wherein selecting the at least one of the at least two workloads based on the at one selection criteria comprises:
selecting a workload of the least two workloads having a greatest resource overuse ratio or exceeds its resource allocation limit by a greatest amount:
or
selecting a workload of the least two workloads having a lowest priority level when each of the at least two workloads has a priority level;
or
selecting a workload of the least two workloads associated with a tenant having a greater total utilization of the resources of the computing system when each of the at least two workloads is associated with a different one of the plurality of tenants.

US Pat. No. 10,191,770

MAINTENANCE TASKS BASED ON DEVICE ROLE

Microsoft Technology Lice...

1. A computer system comprising:one or more processors; and
one or more computer-readable media having stored thereon instructions that are executable by the one or more processors to configure the computer system to update a computing device, including instructions that are executable to configure the computer system to perform at least the following:
identify a defined computing system role for the computing device, wherein the defined computing system role defines a specific predefined purpose of the computing device;
based on the defined computing system role for the computing device, identify a schedule correlated to the defined computing system role, wherein the schedule comprises predetermined time periods, the predetermined time periods defining at least one of when computing devices having the defined computing system role should he active, when computing devices having the defined computing system role should be idle, or when computing devices having the defined computing system role should have maintenance tasks performed;
based on the predetermined time periods in the schedule, identify one or more times for performing maintenance tasks for the defined computing system role, and thus for the computing device such that the times for performing maintenance on the computing device are directly correlated to and based on the defined computing role for the computing device; and
perform one or more maintenance tasks on the computing device, at the one or more times identified for maintenance for the defined computing system role according to the identified schedule; and
wherein the performing one or more maintenance tasks on the computing device comprises performing updates, including at least one of application updates, operating system updates, application store updates, or security updates.

US Pat. No. 10,191,769

EFFICIENT EVENT FILTER

British Telecommunication...

1. A sequence identification apparatus comprising a processor, wherein the apparatus is adapted to access a directed acyclic graph data structure of equivalence classes of events in event sequences identified in a plurality of time-ordered events, and wherein the graph is optimized such that initial and final sub-sequences of event sequences having common equivalence classes are combined in the graph, the apparatus comprising:a code generator adapted to generate executable code corresponding to the graph such that the code includes an instruction sequence for each event classification of the graph, the instruction sequence for an event classification being adapted to evaluate criteria to determine if an event corresponds to the event classification;
an executor adapted to execute the generated executable code such that, in use, the executable code filters incoming time-ordered events based on the graph; and
a sequence identifier adapted to identify the event sequence and further event sequences based on at least one sequence extending relation defining at least one relation between events, and wherein, in use, the executable code filters incoming time-ordered events satisfying the at least one sequence extending relation,
wherein the filtered incoming time-ordered events indicate an occurrence of interest by the identification of one of: a partial sequence of events in the incoming time-ordered events based on the graph, and a full sequence of events in the incoming time-ordered events based on the graph,
and wherein the incoming time-ordered events are events arising from an arrangement of computing components, and the occurrence of interest is a security occurrence, the apparatus further including a notifier for generating a notification of the security occurrence.

US Pat. No. 10,191,767

SEAMLES SDN-SUPPORTED RAN-APP MIGRATION

NEC CORPORATION, Tokyo (...

1. A method for performing centralized radio access network (CRAN) process migration in a CRAN, wherein the CRAN comprises a number of remote radio access points and a centralized processing center including a number of physical compute hosts that perform at least part of a radio access network (RAN) functionality, wherein the method comprising:executing a CRAN process on a first of the physical compute hosts and starting a new instance of the CRAN process on a second of the physical compute hosts,
duplicating traffic destined to the CRAN process to both instances of the CRAN process,
during a first time interval, processing the traffic on the first and the second physical compute host in parallel and suppressing the output of the second physical compute host, and
when the second physical compute host reaches a same state with respect to the CRAN process as the first physical compute host, forwarding duplicate outputs from both instances to higher layers.

US Pat. No. 10,191,766

AUTHORING AND RUNNING TASK-BASED FLOWS WITHIN A COMPUTING SYSTEM

Microsoft Technology Lice...

1. A computing system, comprising:a processor; and
memory storing instructions executable by the processor, wherein the instructions, when executed, configure the computing system to provide:
an application component configured to:
run a parent application; and
navigate a user through a plurality of parent application pages, each parent application page having user interface (UI) controls;
launch point detector logic configured to detect a launch point indicator that is indicative of a launch point corresponding to a task associated with an application object in the parent application;
flow identifier logic configured to identify a sub-application to be launched based on the launch point indicator; and
a sub-application runtime system configured to:
launch the identified sub-application having a sub-application page configured to perform the task, the sub-application page having a set of UI controls comprising a subset of the UI controls on a parent application page;
receive an indication of user input through the sub-application page; and
provide data associated with the user input to the application object in the parent application.

US Pat. No. 10,191,765

TRANSACTION COMMIT OPERATIONS WITH THREAD DECOUPLING AND GROUPING OF I/O REQUESTS

SAP SE, Walldorf (DE)

1. One or more tangible computer-readable media storing computer-executable instructions for causing a server programmed thereby to perform a method at a master node of a database system, the method comprising:for each of multiple database transactions, receiving from one or more database clients one or more operations to manipulate data stored in the database system;
receiving one or more requests to commit the multiple database transactions to disk; and
performing operations to commit the multiple transactions to disk, including:
with a first thread at the master node:
writing a first prepare log to disk at the master node for a first transaction of the multiple transactions;
defining a first job to direct a slave node of the database system to write a first prepare commit log to disk, the first prepare commit log being for at least a portion of the one or more operations of the first transaction;
enqueuing the first job in a queue maintained by the master node, the queue comprising a data structure, physically stored in memory, configured to store a plurality of jobs, the enqueuing comprising storing the job in the data structure; and
after enqueuing the first job, releasing the first thread;
with a second thread at the master node, which may be the first thread after having been released after enqueuing the first job:
writing a second prepare log to disk at the master node for a second transaction of the multiple transaction;
defining a second job to direct the slave node to write a second prepare commit log to disk, the second prepare commit log being for at least a portion of the one or more operations of the second transaction;
enqueuing the second job in the queue; and
after enqueuing the second job, releasing the second thread;
with a third thread at the master node:
dequeuing the first and second jobs from the queue, the dequeuing comprising removing the first and second jobs from the data structure;
grouping the first and second jobs in a single request to be sent to the slave node; and
sending the request to perform the first and second jobs to the slave node, the slave node processing the first and second jobs after receiving the request, writing the first and second prepare commit logs, and sending an acknowledgement to the master node that the first and second prepare commit logs were written;
receiving the acknowledgement from the slave node;
committing the first and second transactions at the master node;
writing a commit log for the first transaction at the master node;
writing a commit log for the second transaction at the master node; and
sending commit acknowledgements to the one or more database clients for the first and second transactions.

US Pat. No. 10,191,764

AGENT-BASED END-TO-END TRANSACTION ANALYSIS

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method for agent-based transaction analysis comprising:building an instrumented binary code of a software application for a transaction;
configuring an analysis agent for the software application;
starting the software application in an application process environment with the instrumented binary code;
attaching the analysis agent to the instrumented binary code of the software application;
extracting by the analysis agent the metadata from the software application wherein the metadata includes data transmitted as a part of the transaction;
sending the metadata to a central analysis server in an environment separate from the application process environment; and
building by the central analysis server an end-to-end description of the transaction from the metadata.

US Pat. No. 10,191,763

ARCHITECTURE OF NETWORKS WITH MIDDLEBOXES

NICIRA, INC., Palo Alto,...

1. A system for implementing a logical network to communicatively connect a plurality of end machines, the logical network comprising (i) a set of logical forwarding elements collectively implemented by a set of managed forwarding elements and (ii) at least two logical middleboxes, the system comprising:a plurality of host computers on each of which (i) a managed forwarding element executes to implement the set of logical forwarding elements and (ii) a middlebox element executes to implement a first logical middlebox of the logical network, wherein the middlebox elements collectively implement the first logical middlebox and each store state information for the first logical middlebox but do not communicate the state information with the other middlebox elements; and
a set of separate physical middleboxes for implementing a second logical middlebox of the logical network, wherein the second logical middlebox performs an operation that requires state information relating to packets between several different sets of end machines connected by the logical network and the set of separate physical middleboxes share the state information for the second logical middlebox with each other;
wherein the middlebox elements and the set of separate physical middleboxes perform middlebox services on packets between the end machines of the logical network.

US Pat. No. 10,191,760

PROXY RESPONSE PROGRAM, PROXY RESPONSE DEVICE AND PROXY RESPONSE METHOD

Fujitsu Limited, Kawasak...

10. A method for a proxy response by a computer, the method comprising:requesting suspension or pausing of a virtual machine when an idle state of the virtual machine is detected;
changing, when the virtual machine is suspended or paused, settings information of a communication control device that controls communication between a terminal device and the virtual machine, so as to transfer access from the terminal device to the virtual machine that is to be suspended or paused, to the computer;
sending, when the access to the virtual machine that is suspended or paused is transferred, a response to the terminal device on the basis of communication response settings information relating to a communication response to the terminal device by the virtual machine that is suspended or paused; and
requesting resumption of the virtual machine that is suspended or paused in response to the transfer of the access.

US Pat. No. 10,191,759

APPARATUS AND METHOD FOR SCHEDULING GRAPHICS PROCESSING UNIT WORKLOADS FROM VIRTUAL MACHINES

Intel Corporation, Santa...

1. A system comprising:a graphics processing unit (GPU) comprising multiple GPU engines;
a microcontroller in the GPU; and
a storage medium having stored thereon instructions which, when executed, implement a virtual machine manager (VMM) to instantiate a virtualization driver interface (vdriver interface) that is adapted to
(a) communicate with the GPU via the microcontroller,
(b) enable multiple virtual machines (VMs) to communicate with the GPU,
(c) store, to memory that is accessible to the microcontroller, a first GPU state for a first VM among the multiple VMs, and
(d) store, to the memory that is accessible to the microcontroller, a second GPU state for a second VM among the multiple VMs;
wherein each VM, when instantiated, is associated with a unique Peripheral Component Interconnect (PCI) device function number and comprises a paravirtualized GPU driver (pdriver) to enable that VM to communicate with the GPU via the vdriver interface, at least in part by enabling that VM to send GPU state for that VM to the vdriver interface of the VMM, for subsequent utilization by the microcontroller in the GPU;
wherein the microcontroller is adapted to
(a) obtain the first GPU state for the first VM, after the vdriver interface of the VMM has received the first GPU state from the pdriver of the first VM and stored the first GPU state to the memory,
(b) obtain the second GPU state for the second VM, after the vdriver interface of the VMM has received the second GPU state from the pdriver of the second VM and stored the second GPU state to the memory,
(c) assign a first schedule slot for the first VM to access a first GPU engine among the multiple GPU engines,
(d) assign a second schedule slot for the second VM to access a second GPU engine among the multiple GPU engines, and
(e) in preparation for transitioning execution from the first VM to a third VM among the multiple VMs, saving the first GPU state for the first VM and restoring a third GPU state for the third VM;
wherein the GPU is adapted to grant exclusive access to the first GPU engine for the first VM when the first VM accesses the first GPU engine; and
wherein, when the first GPU engine executes a memory access instruction provided by the first VM, the first GPU engine is adapted to use the PCI device function number associated with the first VM to execute the memory access instruction.

US Pat. No. 10,191,757

SEAMLESS ADDRESS REASSIGNMENT VIA MULTI-TENANT LINKAGE

Microsoft Technology Lice...

1. A system having a processor, and storage media with computer-executable instructions embodied thereon that, when executed by the processor, performs a method for deploying a pool of computing devices from a staged environment to a production environment, the system comprising:a first pool of two or more virtual machines associated with a single virtual Internet protocol address configured to provide a first version of a service;
a second pool of two or more virtual machines associated with the single virtual Internet protocol address configured to provide a second version of the service,
wherein the first pool of two or more virtual machines running the first version of a service and the second pool of two or more virtual machines running the second version of the service are simultaneously active to receive a request; and
a load-balancing component configured to:
1) receive from a client device a request for the service addressed to the single virtual Internet protocol address,
2) apply a routing policy that facilitates a testing of the second version of the service running on the second pool of two or more virtual machines, and
3) based on the routing policy, route the request to the second pool of two or more machines.

US Pat. No. 10,191,755

VIRTUAL REPLICATION

EMC IP Holding Company LL...

1. A system for data replication, the system comprising:a hypervisor having a virtualization layer; wherein the virtualization layer runs in the hypervisor; wherein the virtualization layer consumes storage;
a splitter running in the virtualization layer;
a storage entity corresponding to a virtual disk; wherein the virtual disk is exposed by the virtualization layer to one or more virtual machines running in the hypervisor; wherein the virtual disk is mapped to a portion of the consumed storage; and
memory; one or more processors; computer-executable program logic, stored in one or more portions of the memory, wherein the computer-executable program logic, executed by the one or more processors to perform:
exposing, via the virtualization layer, the storage entity;
splitting IO in the splitter in the virtualization layer; wherein the splitting includes the splitter intercepting IO directed to the virtual disk and creating a copy of the IO sent to the virtual disk.

US Pat. No. 10,191,754

VIRTUAL MACHINE DEVICE HAVING KEY DRIVEN OBFUSCATION AND METHOD

KONINKLIJKE PHILIPS N.V.,...

1. A device comprising:a memory to store multiple operation routines, wherein each operation routine is configured to perform a particular instruction;
at least one processor configured to:
receive an encoded instruction, the encoded instruction being obtained by encoding a plain instruction with a code encoding;
look-up a corresponding operation routine of the multiple operation routines based on the encoded instruction using a look-up table in the memory, the corresponding operation routine being configured to perform the plain instruction corresponding to the encoded instruction; and
receive input data encoded with a first encoding;
perform the corresponding operation routine based on the input data encoded with the first encoding to produce an output; and
encode the output with a second internal encoding.

US Pat. No. 10,191,753

GENERATING VERIFICATION METADATA AND VERIFYING A RUNTIME TYPE BASED ON VERIFICATION METADATA

Oracle International Corp...

1. A non-transitory computer readable medium comprising instructions which, when executed by one or more hardware processors, causes performance of operations comprising:receiving a request to verify a first runtime type, loaded based on a first runtime type reference, wherein the first runtime type includes a statement associated with a second runtime type reference and a third runtime type reference;
responsive to receiving the request to verify the first runtime type:
identifying verification metadata associated with the first runtime type reference for verifying the first runtime type;
determining that the verification metadata comprises a stored assignable relationship between the second runtime type reference and the third runtime type reference;
determining whether an actual assignable relationship between a second runtime type, loaded based on the second runtime type reference, and a third runtime type, loaded based on the third runtime type reference, adheres to the stored assignable relationship between the second runtime type reference and the third runtime type reference; and
responsive at least to determining that the actual assignable relationship adheres to the stored assignable relationship, determining that the first runtime type is verified based on the verification metadata.

US Pat. No. 10,191,751

INFORMATION PROCESSING DEVICE FOR GENERATING APPLICATION PROGRAMMING INTERFACE INFORMATION

FUJITSU LIMITED, Kawasak...

1. An information processing device comprising:a memory; and
a processor coupled to the memory and the processor configured to:
execute an application software,
execute a specific process for coordinating a software module described in a first language with a software module described in a second language that is different from the first language, and
perform loading of a device driver for using a peripheral device, the device driver including a first software module described in the first language and a second software module described in the second language, the first software module being a software module in which a first plurality of interfaces are defined, the second software module being a software module in which a second plurality of interfaces are defined, in response to the loading, generate interface information for associating the first plurality of interfaces with the second plurality of interfaces respectively,
wherein for using the peripheral device,
the application software is configured to make a first access to a first interface selected from the first plurality of first interfaces,
the first software module is configured to make a second access to the specific process based on the first access,
the specific process is configured to make, on the basis of the second access and the generated interface information, a third access to a second interface selected from the second plurality of interfaces, the second interface being associated with the selected first interface, and
the second software module is configured to make a fourth access to the peripheral device based on the third access.

US Pat. No. 10,191,750

DISCOVERING NEW BACKUP CLIENTS

EMC IP Holding Company LL...

1. A system for discovering a new backup client, comprising:an input interface configured to receive a notice from a backup client over a network, wherein the notice indicates the backup client is being added to the network and includes information associated with the backup client, wherein the backup client is configured to provide the notice to the system upon determining a backup server address for one or more backups associated with the backup client; and
a processor configured to:
determine that the backup client is not already configured to perform backups based at least in part on the information associated with the backup client, wherein the information associated with the backup client includes a hardware and software configuration of the backup client;
in response to a determination that the backup client is not already configured to perform backups, provide an indication of the notice;
determine a set of available configuration modes based at least in part on the hardware and software configuration of the backup client; and
configure the backup client according to a selected configuration mode.

US Pat. No. 10,191,749

SCATTER REDUCTION INSTRUCTION

Intel Corporation, Santa...

5. A processor comprising:a register array comprising a first element that stores a first register value that identifies a first memory location, a second element that stores a second register value that identifies a second memory location, and a third element that stores a third register value that identifies a third memory location;
a decoder circuit to:
receive a single instruction multiple data (SIMD) instruction from an application, the SIMD instruction identifying the register array and an array of input values comprising at least a first input value, a second input value, and a third input value; and
decode the SIMD instruction; and
a processor core to:
perform an operation on the first input value and the first register value to obtain a first operation value, and wherein the first register value is stored at a first location of the register array;
perform the operation on the second input value and the second register value to obtain a second operation value, and wherein the second register value is stored at a second register array location of the register array; and
perform the operation the third input value and the third register value, and wherein the second register value is stored at a third location of the register array,
wherein the operation on the first, second, and third input values are performed in parallel;
associate the first operation value with the first location;
associate the second operation value with the second location;
associate a third operation value with the third location;
determine that the first register value and the second register value are the same value, wherein the third register value is different than the first register value and the second register value;
perform a horizontal add operation on the first operation value and the second operation value to obtain a result value;
write the result value to the second memory location, wherein the second memory location and the first memory location are the same when the first register value and the second register value are the same; and
write the third operation value to the third memory location.

US Pat. No. 10,191,748

INSTRUCTION AND LOGIC FOR IN-ORDER HANDLING IN AN OUT-OF-ORDER PROCESSOR

Intel IP Corporation, Sa...

1. A processor comprising:a core comprising an out-of-order pipeline including a decode logic, an issue logic to issue decoded instructions, and at least one execution logic to execute issued instructions of a program, wherein the at least one execution logic is to execute at least some instructions of the program out-of-order, the decode logic to decode a first in-order memory instruction of the program and provide the decoded first in-order memory instruction to the issue logic, the issue logic to order the first in-order memory instruction ahead of a second in-order memory instruction of the program, the first in-order memory instruction comprising a user-level instruction of an instruction set architecture to specify in-order execution of the first in-order memory instruction, wherein the issue logic is to issue the first in-order memory instruction to the at least one execution logic with a higher priority than the second in-order memory instruction by association of a priority indicator with the first in-order memory instruction.

US Pat. No. 10,191,747

LOCKING OPERAND VALUES FOR GROUPS OF INSTRUCTIONS EXECUTED ATOMICALLY

Microsoft Technology Lice...

1. A method comprising:fetching a first group of instructions, configured to execute by a processor, including a group header for the first group of instructions, wherein the group header includes a field including locking information for at least a first operand and a second operand for processing by the first group of instructions;
storing a value of the first operand in a first operand buffer of the processor and storing a value of the second operand in a second operand buffer of the processor;
detecting completion of execution of the first group of instructions by counting:
(1) register writes associated with the first group of instructions or (2) stores associated with the first group of instructions;
based on the locking information, locking a value of the first operand in the first operand buffer of the processor such that the first operand is not cleared from the first operand buffer of the processor in response to the completion of the execution of the first group of instructions even when a second group of instructions, for execution by the processor after the completion of the execution of the first group of instructions, is a new group of instructions comprising different instructions from the first group of instructions; and
based on the locking information, in response to the completion of the execution of the first group of instructions, clearing the value of the second operand from the second operand buffer of the processor.

US Pat. No. 10,191,746

ACCELERATED CODE OPTIMIZER FOR A MULTIENGINE MICROPROCESSOR

INTEL CORPORATION, Santa...

1. A method for accelerating code optimization in a microprocessor, comprising:fetching an incoming macro instruction sequence using an instruction fetch component;
transferring the incoming macro instruction sequence to a decoding component for decoding into a microinstruction sequence;
performing optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups, wherein performing the optimization processing includes checking for true dependencies, output dependencies, and anti-dependencies in the microinstruction sequence to determine which microinstructions of the microinstruction sequence are grouped into a same dependent code group of the plurality of dependent code groups;
outputting the plurality of dependent code groups to a plurality of engines of the microprocessor for execution in parallel; and
storing a copy of the optimized microinstruction sequence into a sequence cache for subsequent use upon a subsequent hit on the optimized microinstruction sequence.

US Pat. No. 10,191,745

OPTIMIZED CALL-RETURN AND BINARY TRANSLATION

Intel Corporation, Santa...

1. A processor, comprising:a region formation engine to perform aggressive region formation of a region of code for translation from a guest instruction set architecture code to a translated instruction set architecture code,
wherein the aggressive region formation comprises forming the region of code across a boundary of a return (RET) instruction; and
a binary translator to:
translate the region of code; and
prevent a side entry into the translated region of code at a translated return target (RET_TGT?) included in the translated region of code, wherein the RET_TGT? is translated from a return target (RET_TGT) in the guest instruction set architecture code, and
wherein the side entry is prevented based on an indication mapped to an instruction pointer of the RET_TGT.

US Pat. No. 10,191,743

VERSATILE PACKED DATA COMPARISON PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

Intel Corporation, Santa...

1. A processor comprising:a decode unit to decode a versatile packed data compare instruction, the versatile packed data compare instruction to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, each data element of the second source packed data operand to correspond to a data element of the first source packed data operand in a same relative position, and to indicate a source comparison operation indication operand that is to include at least four comparison operation indicators each operable to versatilely indicate a potentially different comparison operation for a different corresponding pair of corresponding data elements from the first and second source packed data operands, wherein the source comparison operation indication operand comprises a packed data operand that is to include at least four data elements that are each to include a different corresponding one of the comparison operation indicators, and wherein each comparison operation indicator is to be specified in a least significant byte of the corresponding data element; and
an execution unit coupled with the decode unit, the execution unit, in response to the versatile packed data compare instruction, to store a result in a destination storage location to be indicated by the versatile packed data compare instruction, the result to include at least four result indicators that are each to correspond to a different one of the at least four comparison operation indicators, each result indicator to indicate a result of a comparison operation, which is to be indicated by the corresponding comparison operation indicator, which is to have been performed on the corresponding pair of data elements from the first and second source packed data operands.

US Pat. No. 10,191,742

MECHANISM FOR SAVING AND RETRIEVING MICRO-ARCHITECTURE CONTEXT

Intel Corporation, Santa...

1. An apparatus comprising:an execution unit within a processor to execute a code block having been compiled to have a reserved space appended to one end, the reserved space including a metadata block associated with the code block, and a switch code sign signifying an end of the code block and a beginning of the reserved space, wherein the code block and the reserved space appended to its end occupy a contiguous region of memory and boundaries of the code block are defined by conditional instructions;
power management hardware coupled to the execution unit, wherein the power management hardware is to:
monitor a first execution of the code block;
store a micro-architectural context of the processor in the associated metadata block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters;
read the associated metadata block upon a second execution of the code block; and
tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block; and
wherein the metadata block associated with the code block stores the performance data collected from executing the associated code block on two different processor cores that have different performances, and wherein the power management hardware is to determine which one of the two different processor cores is to execute the associated code block based on the performance data.

US Pat. No. 10,191,741

SYSTEM AND METHOD FOR MITIGATING THE IMPACT OF BRANCH MISPREDICTION WHEN EXITING SPIN LOOPS

Oracle International Corp...

1. A method, comprising:performing by a computer:
determining that a sequence of program instructions comprises a conditional branch type instruction that includes a hint or parameter that indicates that a particular branch path should be predicted;
performing dynamic branch prediction of the conditional branch instruction;
in response to said determining, predicting that the path taken following the conditional branch type instruction will be the particular branch path indicated by the hint or parameter included in the conditional branch type instruction, wherein the prediction of the particular branch path according to the hint or parameter overrides an outcome of the dynamic branch prediction;
if the particular branch path is correctly predicted, continuing on the predicted branch path; and
if the particular branch path is incorrectly predicted, incurring a misprediction stall.

US Pat. No. 10,191,740

DEINTERLEAVE STRIDED DATA ELEMENTS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

Intel Corporation, Santa...

1. A processor comprising:a plurality of packed data registers;
a decode unit to decode an instruction, the instruction to indicate a source operand, to indicate a stride, to indicate at least one set of strided data element positions out of all sets of strided data element positions for the indicated stride, and to indicate at least one destination packed data register of the plurality of packed data registers; and
an execution unit coupled with the plurality of packed data registers, and coupled with the decode unit, the execution unit, in response to the instruction, for each of the indicated at least one set of strided data element positions, to store a corresponding result packed data operand, in a corresponding destination packed data register of the plurality of packed data registers, each result packed data operand to include a plurality of data elements, which are to be from the corresponding indicated set of strided data element positions of the source operand, in which strided data element positions of the set are to be separated from one another by integer multiples of the indicated stride.

US Pat. No. 10,191,739

STATE ESTIMATION PROCESSOR AND STATE ESTIMATION SYSTEM

MEGACHIPS CORPORATION, O...

1. A state estimation processor connected to an external detection device and an external computer, comprising:interface circuitry configured to obtain detection information obtained by the external detection device and output state information to the external computer;
calculating circuitry including a SIMD type arithmetic processing circuitry processes a plurality of information by one command and provided with at least four single precision floating point computing circuits, the one command being executed in parallel to a plurality of data set to each of the at least four single precision floating point computing circuits in a single cycle;
the calculating circuitry configured to:
estimate a state of an object based on the detection information obtained by the interface circuitry;
generate the state information according to the state of the object;
compare first detection information received at a first point in time with second detection information received at a second point in time, which is subsequent to the first point in time;
control the interface circuitry to output a notification to the external computer when it is determined that a difference between the first detection information and the second detection information is less than a predetermined threshold value; and
switch an operational mode from a first operation mode, during which the state information is generated, to a second operation mode in which power consumption is smaller than the first operation mode after controlling the interface circuitry to output the notification to the external computer.

US Pat. No. 10,191,737

PROGRAM CODE COMPARISON AND REPORTING

Accenture Global Solution...

1. A device, comprising:one or more memories; and
one or more processors, communicatively coupled to the one or more memories, configured to:
obtain a first code set and a second code set,
the first code set having at least one difference from the second code set,
the at least one difference relating to addition, removal, or modification of code of the first code set in comparison to code of the second code set, and
the first code set and the second code set relating to one or more of:
extracting input data from a source file,
transforming the input data to form output data, or
storing the output data in a target file;
identify one or more code portions of the first code set and one or more code portions of the second code set,
the one or more code portions of the first code set and the one or more code portions of the second code set including one or more lines of code that are associated with a particular format including at least one of:
a source definition,
a target definition,
a workflow, or
a transformation,
each code portion of the first code set to be compared to a corresponding code portion of the second code set,
the one or more code portions of the first code set including a first code portion and a second code portion and the one or more code portions of the second code set include a third code portion and a fourth code portion,
the first code portion of the first code set corresponding to a format of the third code portion of the second code set,
the second code portion of the first code set corresponding to a format of the fourth code portion of the second code set;
concurrently compare:
the first code portion of the first code set to the third code portion of the of the second code set to identify at least a first difference, and
the second code portion of the first code set to the fourth code portion of the second code set to identify at least a second difference,
where the one or more processors, when concurrently comparing the first code portion of the first code set to the third code portion of the second code set and the second code portion of the first code set to the fourth code portion of the second code set, are to:
perform parallel processing with regard to comparing the first code portion to the third code portion and the second code portion to the fourth code portion;
generate comparison information identifying the at least first difference and the at least second difference; and
store or provide the comparison information.

US Pat. No. 10,191,736

SYSTEMS AND METHODS FOR TRACKING CONFIGURATION FILE CHANGES

ServiceNow, Inc., Santa ...

1. A system for tracking configuration file changes comprising:non-transitory memory; and
one or more hardware processors configured to read instructions from the non-transitory memory to perform operations comprising:
receiving a definition of a pattern used to identify a configuration file to be tracked;
resolving the pattern to obtain obtained file paths for external configuration files;
performing horizontal discovery using the pattern to discover the configuration file when external file paths exist inside the pattern, joining the obtained file path with the existing file paths defined in the pattern;
determining whether an entry in a configuration management database corresponding to a previously discovered configuration file has been discovered during the horizontal discovery;
when the previously discovered configuration file has not been discovered in the horizontal discovery, deleting the entry from the configuration management database;
when the previously discovered configuration file has been discovered in the horizontal discover, determining whether changes have occurred in the configuration file;
updating a configuration management database with the discovered configuration file as a configuration item; and
tracking changes to the discovered configuration file including a timeline and history of the discovered configuration file.

US Pat. No. 10,191,735

LANGUAGE-INDEPENDENT PROGRAM COMPOSITION USING CONTAINERS

1. An apparatus comprising:a memory;
at least one hardware processor, coupled to said memory, and,
a non-transitory computer readable medium comprising computer executable instructions which when loaded into said memory configure said at least one hardware processor to:
obtain:
an action sequence comprising a plurality of actions; and
a corresponding input dictionary;
instantiate a first container running a first image for a first one of said actions implemented in a first programming language;
execute said first image for said first one of said actions on said input dictionary to obtain a first action result;
update said input dictionary with said first action result to obtain an updated input dictionary;
instantiate a second container running a second image for a second one of said actions implemented in a second programming language different than said first programming language;
execute said second image for said second one of said actions on said updated input dictionary to obtain a second action result; and
update said updated input dictionary with said second action result to obtain a further updated input dictionary;
wherein said input dictionary, said updated input dictionary, and said further updated input dictionary are independent of said first and second programming languages.

US Pat. No. 10,191,734

METHOD AND SYSTEM FOR SOFTWARE APPLICATION OPTIMIZATION USING NATURAL LANGUAGE-BASED QUERIES

Open Text Corporation, W...

1. A method for software application optimization using natural language-based queries, comprising:obtaining, by an application development engine executing on a computing device, a user-provided query input via a user interface,
wherein the user-provided query comprises at least one software application optimization constraint and an optimization action, the at least one software application optimization constraint including information for an identification of an application element that matches the at least one software application optimization constraint, as a candidate for the optimization action, from a plurality of application elements of a software application, and
wherein the user-provided query is a string comprising a human language sentence;
deriving, by the application development engine, a formalized query from the user-provided query by translating the user-provided query into a syntactic construct of segmented sentence elements;
obtaining, by the application development engine, the application element that matches the at least one software application optimization constraint from an application repository, comprising:
deriving a pattern representation of the user-provided query from the formalized query; and
identifying the application element that matches the pattern representation of the user-provided query from the plurality of application elements, including identifying the application element as the candidate for the optimization action; and
optimizing the software application, by the application development engine, by performing the optimization action, including performing a software application revision on the identified application element that matches the pattern representation of the user-provided query.

US Pat. No. 10,191,733

SOFTWARE CHANGE PROCESS ORCHESTRATION IN A RUNTIME ENVIRONMENT

SAP SE, Walldorf (DE)

1. A method comprising:defining, by a computer system, a set of software change processes across different platforms and environments;
mapping, by the computer system, each software change process to at least one tool for performing each software change process to generate a software change process map comprising a list of software change processes and at least one corresponding tool for performing each software change process;
receiving, at the computer system, an indication to initiate a software change process orchestration;
identifying, by the computer system, a first software change process and a second software change process to be performed for the software change process orchestration in response to receiving the indication;
accessing, by the computer system, the software change process map comprising the list of change processes mapped to at least one corresponding tool for performing each change process to identify at least one first corresponding tool for the first software change process and at least one second corresponding tool for the second software change process;
creating, by the computer system, a composed process by combining the first software change process to be performed for the software change process orchestration and the at least one first corresponding tool for performing the first software change process, and the second software change process and the at least one second corresponding tool for performing the second software change process;
triggering, by the computer system, execution of the at least one first corresponding tool for performing the first software change process and the at least one second corresponding tool performing the second software change process of the composed process, using a uniform software logistic protocol that manages calls to tools across different platforms and environments, the software logistic protocol comprising a uniform process interface that starts and monitors a software change process;
monitoring, by the computer system, status of an execution of the at least one first corresponding tool and the at least one second corresponding tool during the first software change process and the second software change process of the composed process; and
presenting, by the computer system, the status of the execution of the at least one first corresponding tool and the at least one second corresponding tool during the software first change process and the second software change process of the composed process on a uniform user interface that is process independent.

US Pat. No. 10,191,732

SYSTEMS AND METHODS FOR PREVENTING SERVICE DISRUPTION DURING SOFTWARE UPDATES

Citrix Systems, Inc., Fo...

1. A method for preventing service disruptions in a computing system, comprising:receiving, at a cloud-based computing system, a plurality of messages for initiating software updates requiring system reboots by a plurality of remote computing machines, where each said message is sent by a respective one of the remote computing machines to itself through a hosted maintenance service; and
performing operations by the cloud-based computing system to schedule maintenance operations across the plurality of remote computing machines for a performance of the system reboots in a one-machine-at-a-time manner, where the operations comprise
sequencing the plurality of messages across the remote computing machines so as to ensure that an operational state of only one remote computing machine of the plurality of remote computing machines is transitioned from an online state to an offline state at any given time; and
making the plurality of messages available to the remote computing machines in accordance with the sequencing.

US Pat. No. 10,191,731

SAFE AND AGILE ROLLOUTS IN A NETWORK-ACCESSIBLE SERVER INFRASTRUCTURE USING SLICES

Microsoft Technology Lice...

1. A method of rolling out updates to a network-accessible server infrastructure which operates a plurality of instances of a supporting service, the supporting service comprised by a plurality of service portions, the instances of the supporting service each including the plurality of service portions, the method comprising:receiving an indication of a partition of the instances of the supporting service into a plurality of slices, each instance of the supporting service partitioned to include one or more slices of the plurality of slices, each slice of an instance of the supporting service including one or more of the service portions of the instance of the supporting service; and
deploying a software update to the plurality of instances of the supporting service by
applying the software update to the plurality of slices in a sequence such that the software update is applied to a same slice in parallel across the instances of the supporting service containing that same slice before being applied to a next slice and
waiting a wait time after each applying of the software update to a slice of the plurality of slices before applying the software domain to a next slice of the plurality of slices in the sequence.

US Pat. No. 10,191,730

APPLICATION UPGRADE METHOD AND APPARATUS

HUAWEI TECHNOLOGIES CO., ...

1. A system for upgrading a deployed application, comprising:a user equipment configured to send an application deployment request to the application deployment server, wherein the application deployment request comprises:
a node template of a to-be-deployed application;
a deployed application identifier of the deployed application to be upgraded by the to-be-deployed application;
a node template identifier of a node template of the deployed application;
a first platform node template identifier of a first platform node template; and
a version requirement of the first platform node template required by the node template of the to-be-deployed application; and
an application deployment server configured to:
receive the application deployment request from the user equipment;
acquire, according to the deployed application identifier, a first platform node identifier of a first platform node corresponding to the first platform node template identifier and acquire a version of the first platform node indicated by the first platform node identifier; wherein the to-be-deployed application runs based on a capability provided by the first platform node, and wherein the first platform node is deployed according to the first platform node template prior to the to-be-deployed application;
determine that the version of the first platform node is below the version requirement of the first platform node template;
acquire a first platform node upgrade package that meets the version requirement, wherein the first platform node upgrade package is acquired according to the version requirement of the first platform node template required by the node template of the to-be-deployed application;
upgrade the first platform node indicated by the first platform node identifier using the first platform node upgrade package;
determine an identifier of a to-be-upgraded application node; and
upgrade the application node after the first platform node is upgraded, wherein the application node is indicated by the identifier of the to-be-upgraded application node.

US Pat. No. 10,191,729

SYSTEM AND METHODOLOGY FOR UPDATING INDIVIDUALIZED SYSTEM DATA TO FACILITATE REPAIR AND/OR REPLACEMENT SERVICE PROVISION

Lenovo Enterprise Solutio...

1. A system, comprising:a storage device hosting a file system and implementing an operating system, the file system storing first individualized system data identifying a computer hardware component;
a replacement computer hardware component comprising an embedded storage module storing second individualized system data identifying the replacement computer hardware component;
wherein the embedded storage module is configured to implement a routine stored thereon using a processor or a controller of the system;
wherein the routine is configured to overwrite the first individualized system data with the second individualized system data in response to determining a mismatch between the first individualized system data and the second individualized system data;
wherein the storage device is physically separate from the computer hardware component and the replacement computer hardware component;
wherein the embedded storage module is configured to automatically implement the routine during a boot process of the system using a target disk mode function of the boot process;
wherein the embedded storage module is further configured to automatically implement the routine as part of a startup process of the operating system;
wherein the first individualized system data and the second individualized system data each comprise vital product data (VPD) corresponding to the computer hardware component; and
wherein the VPD comprises:
a manufacturer name corresponding to the replacement computer hardware component;
a location corresponding to the replacement computer hardware component, wherein the location includes a city name, a state, and a country name;
a serial number corresponding to the replacement computer hardware component, wherein the serial number is an uninterrupted string of alphanumeric characters excluding special characters and spaces;
a component type corresponding to the replacement computer hardware component, wherein the component type comprises a model name;
a universally unique identifier (UUID) corresponding to the replacement computer hardware component, wherein the UUID is a 128-bit value selected from the group consisting of: a MAC address: a DCE security value, a MD5 hash, and a SHA-1 hash; and
asset tag information corresponding to the replacement computer hardware component, wherein the asset tag information is a string encoded as a barcode on a physical tag applied to the replacement computer hardware component.

US Pat. No. 10,191,728

SYSTEM AND METHOD TO REDUCE STORAGE AREA USAGE OF ANDROID APPLICATION

Samsung Electronics Co., ...

1. A mobile device based on an Android™ operating system comprising:a storage device configured to store data;
transceiver circuitry configured to access a server via a wireless communication network and download, from the server, an Android™ application package; and
a package manager configured to:
analyze resources in the downloaded Android™ application package;
identify unnecessary ones of the resources, the unnecessary resources comprising resources that are not suitable for use by the mobile device;
delete the unnecessary resources;
generate, from only resources remaining after deletion of the unnecessary resources, without adding new resources, an optimized Android™ application package having a smaller size than the downloaded Android™ application package;
store the optimized Android™ application package in the storage device in place of the downloaded Android™ application package; and
determine, based on a new signing key, that the optimized Android™ application package has a smaller size than the downloaded Android™ application package.

US Pat. No. 10,191,696

IMAGE FORMING SYSTEM INCLUDING A FIRST IMAGE FORMING APPARATUS AND A SECOND IMAGE FORMING APPARATUS CONNECTED ON A DOWNSTREAM SIDE OF THE FIRST IMAGE FORMING APPARATUS

KONICA MINOLTA, INC., Ch...

1. An image forming system comprising: a first image forming apparatus; and a second image forming apparatus connected on a downstream side of the first image forming apparatus in a paper conveying direction,wherein the first image forming apparatus includes:
a first expander that expands a first image having image expansion time per page including a first time; and
a first image former that forms the first image expanded by the first expander, onto a first face of paper, and
the second image forming apparatus includes:
a second expander that expands a second image having image expansion time per page including a second time longer than the first time; and
a second image former that forms the second image expanded by the second expander, onto the first face on which the first image has been formed.

US Pat. No. 10,191,668

METHOD FOR DYNAMICALLY MODELING MEDIUM ERROR EVOLUTION TO PREDICT DISK FAILURE

EMC IP Holding Company LL...

1. A computer-implemented method for predicting disk failures in a redundant array of independent disks (RAID) environment, the method comprising:respectively receiving hard disk status information from each set of a plurality of sets of hard disks in a storage system, wherein the hard disk status information comprises a plurality of states within the set, a number of hard disks within the set, and an indicator of how many hard disks have failed within the set;
for each set of the plurality of sets of hard disks,
calculating a transitional probability that a hard disk will fail within a predetermined period of time based on the respective hard disk status information, wherein calculating the transitional probability comprises:
querying a medium error history of hard disks within the set,
using the medium error history to identify which of the hard disks has experienced at least one medium error,
counting a number of transitions of each of the hard disks having the at least one medium error according to different transition types, each of the transition types representing a specific transition from one of the plurality of states to another of the plurality of states, wherein the one state and the other state are of same state or different states, and
identifying a number of transition types based on the counting, and
generating a first risk profile for the hard disk based on the calculated transitional probability;
generating a second risk profile for a set of hard disks based on two or more of the first risk profiles; and
determining which of the plurality of sets of hard disks has a highest probability of failing within the predetermined period of time based on the second risk profile.

US Pat. No. 10,191,664

MEMORY SYSTEM

SK Hynix Inc., Gyeonggi-...

1. A memory system comprising:a first memory device including a first memory and a first memory controller configured to control the first memory to store data;
a second memory device including a second memory and a second memory controller configured to control the second memory to store data; and
a processor is configured to execute an operating system (OS) and an application to access a data storage memory through the first and second memory devices,
wherein the first and second memories are separated from the processor,
wherein the second memory controller transfers a signal between the processor and the second memory device based on at least one of values of a handshaking information field included in the signal,
wherein the first memory includes a plurality of first high-capacity memory cores configured to work as cache memories for the second memory,
wherein the first memory device further includes a first memory management logic operatively and commonly coupled with the plurality of first high-capacity memory cores, and configured to support high-speed data communication between the processor and the plurality of first high-capacity memory cores,
wherein the second memory includes a plurality of second high-capacity memory cores configured to work as system memories,
wherein the second memory device further includes a second memory management logic operatively and commonly coupled with the plurality of second high-capacity memory cores, and configured to support data communication between the processor and the plurality of second high-capacity memory cores,
wherein the second memory management logic includes a buffer configured to buffer write data, based on which the plurality of second memory cores are updated,
wherein the second memory controller firstly buffers the write data in the buffer, and then the second memory management logic independently updates the plurality of second memory cores based on the buffered write data, and
wherein the at least one of values of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

US Pat. No. 10,191,643

USING CLAMPING TO MODIFY SCROLLING

Facebook, Inc., Menlo Pa...

1. A method comprising:by a computing device, receiving a first user input to scroll within a graphical user interface (GUI) displayed on a touch screen of the computing device, the first user input comprising a touch gesture on the touch screen, the touch gesture comprising a path that comprises a starting point and one or more other points on the touch screen;
by the computing device, determining a plurality of regions of the touch screen defined with respect to the starting point, a first one of the regions corresponding to a first scrolling axis, a second one of the regions corresponding to a second scrolling axis that is perpendicular to the first scrolling axis;
by the computing device, determining that the path corresponds to the first one of the regions;
by the computing device, based on the determining that the path corresponds to the first one of the regions, scrolling within the GUI according to the first user input linearly and parallel to the first scrolling axis;
by the computing device, receiving a second user input to scroll within the GUI;
by the computing device, determining that the second user input occurred within a pre-determined amount of time from the first user input; and
by the computing device, based on the determining that the second user input occurred within the pre-determined amount of time, scrolling within the GUI linearly and parallel to the first scrolling axis according to a component of the second user input along the first scrolling axis.

US Pat. No. 10,191,605

TOUCH PANEL, DRIVING METHOD THEREOF, AND DISPLAY DEVICE BASED ON ELECTROMAGNETIC INDUCTION

BOE TECHNOLOGY GROUP CO.,...

1. A touch panel, comprising:a first substrate;
a second substrate opposite to the first substrate;
a plurality of magnetic protrusions arranged on the first substrate and protruding towards the second substrate;
a first coil group comprising a plurality of coils extending in a first direction; and
a second coil group comprising a plurality of coils extending in a second direction;
wherein the first coil group and the second coil group are stacked above the second substrate and insulated from each other,
wherein the coils in the first and second coil group and corresponding magnetic protrusions constitute a plurality of inductive sensors, the inductive sensors being capable of generating inductance variations responsive to variations in distances between the coils and the corresponding magnetic protrusions.

US Pat. No. 10,191,249

SUBMINIATURE OPTICAL SYSTEM AND PORTABLE DEVICE INCLUDING THE SAME

Samsung Electro-Mechanics...

1. An optical system, comprising:a first lens which has positive refractive power;
a second lens which has negative refractive power;
a third lens which has positive refractive power, a convex object-side surface, and a concave image-side surface;
a fourth lens which has negative refractive power, a concave object-side surface, and a concave image-side surface;
a fifth lens which has positive refractive power, and a meniscus shape of which an image-side surface is convex; and
an image sensor,
wherein the first lens to the image sensor are sequentially disposed from an object side, and
wherein when a distance from an object-side surface of the first lens to an image plane of the image sensor is TTL and a focal length of the optical system is F, 0.7

US Pat. No. 10,191,247

IMAGING LENS HAVING FOUR LENS ELEMENTS, AND ELECTRONIC APPARATUS HAVING THE SAME

Genius Electronic Optical...

1. An imaging lens comprising first, second, third, and fourth lens elements arranged from an object side to an image side in the given order, each of the first, second, third, and fourth lens elements having an object-side surface facing toward the object side and an image-side surface facing toward the image side, wherein:the image-side surface of the first lens element comprises a concave portion in a vicinity of a periphery of the first lens element;
the image-side surface of the second lens element comprises a convex portion in a vicinity of an optical axis of the second lens element;
the third lens element has a positive refractive power and the object-side surface of the third lens element comprises a concave portion in a vicinity of an optical axis of the third lens element;
the object-side surface of the fourth lens element comprises a convex portion in a vicinity of an optical axis of the fourth lens element;
the imaging lens has a fixed focal length and does not include any lens element with refractive power other than the first, second, third, and fourth lens elements; and
the imaging lens satisfies
1.30?Gaa/(G12+G23)?1.83, where
Gaa represents a sum of a distance between the image-side surface of the first lens element and the object-side surface of the second lens element at the optical axis, a distance between the image-side surface of the second lens element and the object-side surface of the third lens element at the optical axis, and a distance between the image-side surface of the third lens element and the object-side surface of the fourth lens element at the optical axis,
G12 represents a distance between the image-side surface of the first lens element and the object-side surface of the second lens element at the optical axis,
G23 represents a distance between the image-side surface of the second lens element and the object-side surface of the third lens element at the optical axis.

US Pat. No. 10,191,246

ZOOM LENS AND IMAGING APPARATUS

FUJIFILM Corporation, To...

1. A zoom lens consisting of, in order from an object side:a first lens group that has a positive refractive power;
a second lens group that has a negative refractive power;
a third lens group that has a positive refractive power;
a fourth lens group that has a negative refractive power; and
a fifth lens group that has a positive refractive power,
wherein all intervals between the lens groups adjacent to each other change during zooming,
wherein an aperture diaphragm is disposed between a surface of the second lens group closest to an image side and a surface of the fourth lens group closest to the object side,
wherein the first lens group and the fifth lens group each consist of two or less lenses,
wherein a lens of the second lens group closest to the object side is a meniscus lens which has a negative refractive power and of which an object side surface has a convex shape,
wherein a lens of the fourth lens group closest to the image side is a meniscus lens which has a negative refractive power and of which an image side surface has a convex shape, and
wherein the following conditional expression (3) is satisfied,
?0.35 where f4 is a focal length of the fourth lens group, and
f1 is a focal length of the first lens group.

US Pat. No. 10,191,243

EXPANDABLE MIRRORS

FORD GLOBAL TECHNOLOGIES,...

5. A mirror implementable in a vehicle, comprising:a first pane having a first reflective surface;
a second pane having a second reflective surface;
a third pane having a third reflective surface,
a mechanism connected with each of the first and second panes, wherein the mechanism is configured, when actuated, to expand a viewing area of the mirror from a first size to a second size larger than the first size, the expanded viewing area comprising the first and second reflective surfaces; and
a positioning motor configured to integrally position the first pane and the second pane as a whole for adjusting an orientation of the viewing area of the mirror,
wherein the mechanism comprises a plurality of guiding rails connecting the first, second and third panes, and wherein the mechanism is configured to expand the viewing area of the mirror by sliding the second and third panes along the plurality of guiding rails to expose each of the first, second and third reflective surfaces such that the viewing area of the mirror comprises the first, second and third reflective surfaces.

US Pat. No. 10,191,242

MOVEABLE MIRROR ASSEMBLY FOR ELECTRONIC DEVICE CASE

Scandit AG, Zurich (CH)

1. A case for a portable electronic device having a display screen on a front of the portable electronic device, the case comprising:a housing having a shape fitted at least in part to a shape of at least a portion of an exterior of the portable electronic device and arranged to receive and hold the at least the portion of the portable electronic device, the housing comprising:
a first opening on a front surface of the housing to correspond to a position of the display screen on the front of the portable electronic device when the portable electronic device is disposed in the housing;
a protrusion extending from a back surface of the housing and integrated with the housing, the protrusion having a protrusion top surface, the protrusion being arranged to extend away from a back of the portable electronic device when the portable electronic device is disposed in the housing;
at least one second opening in the protrusion top surface of the protrusion from the housing; and
at least one optical element, disposed within the protrusion from the housing, to convey light between the at least one second opening in the protrusion top surface of the housing and the back of the portable electronic device when the portable electronic device is disposed in the housing, the at least one optical element comprising at least one light-redirecting component arranged in the protrusion so as to redirect light entering the at least one second opening in the protrusion top surface of the protrusion, when the portable electronic device is disposed in the housing, to a camera disposed on the back of the portable electronic device,
wherein:
the protrusion comprises one or more mounting elements, disposed inside the protrusion, to provide a mount that is angled with respect to the back of the portable electronic device and angled with respect to the protrusion top surface; and
the at least one light-redirecting component is mounted on the one or more mounting elements so as to be mounted angled with respect to the back of the portable electronic device and angled with respect to the protrusion top surface.

US Pat. No. 10,191,240

LENS BARREL

KONICA MINOLTA, INC., To...

1. A lens barrel, comprising:a frame body for holding an optical element;
a frame body holding member holding the frame body; and
a mounting member arranged on an object side or an image side of the frame body, mounted on the frame body holding member and having a reference portion on which another member is to be mounted,
wherein the mounting member includes an opening portion open to penetrate from the object side to the image side,
wherein the frame body includes a frame main body portion for holding the optical element, and adjusters arranged at positions spaced apart from each other in a circumferential direction of the frame main body portion for adjusting the position of the frame body with respect to a predetermined axis of the frame body holding member to adjust the orientation of an optical axis in the optical element and the position of the optical element in a direction of the optical axis,
wherein the adjusters are arranged at respective positions that are each adjustable from the opening portion, each of the adjusters including a biasing member for biasing the frame main body portion toward the image side in the optical axis direction, and a bolt-like engaging member held in the frame main body portion and being operable from the opening portion for moving the frame main body portion toward an object side of the optical axis direction against biasing force provided by the biasing member,
wherein the frame body holding member includes main body mounting pieces, each main body mounting piece being configured to receive a respective bolt-like engaging member, the main body mounting pieces being fixed to the frame body holding member.

US Pat. No. 10,191,239

HYBRID CABLE TRANSITION ASSEMBLY

CommScope Technologies LL...

1. An assembly for breaking out hybrid power/fiber cable, comprising:a hybrid power/fiber cable comprising a plurality of conductors and a plurality of optical fibers, wherein first lengths of the conductors and the optical fibers are circumferentially surrounded by an armor layer, and wherein a portion of the armor layer is circumferentially surrounded by a cable jacket, and wherein second lengths of the conductors and the optical fibers are free of the armor layer and the cable jacket;
a breakout sleeve having an internal bore, a portion of the cable jacket and a portion of the armor layer residing in the internal bore, and portions of the second lengths of the conductors and optical fibers residing in the internal bore;
wherein the breakout sleeve is fixed to the cable jacket and includes arcuate, flexible electrical contacts in the internal bore, and wherein the electrical contacts engage the armor layer.

US Pat. No. 10,191,238

FIBER OPTIC CABLE MANAGEMENT KIT AND CHASSIS

DMSI International, Veni...

1. A fiber optic cable management kit, comprising:a plate adapted to secure to a chassis floor, the plate comprising a plurality of slide-lock apertures disposed through a top face of the plate, the plurality of slide-lock apertures comprising a first group of slide-lock apertures and a second group of slide-lock apertures spaced apart from the first group of slide-lock apertures, wherein each of the first and second groups of slide-lock apertures comprise first slide-lock apertures oriented in a first direction and second slide-lock apertures orientated in a second direction opposite the first direction;
a cable tie down adapted to slide-lock engage the plate, the cable tie down comprising a slide-lock engagement feature and a compliant mechanism each adapted to engage in one of the plurality of slide-lock apertures of the plate, the cable tie down further comprising opposing first and second rows of spaced apertures adapted to receive cable tie downs therethrough; and
a fiber organizer adapted to slide-lock engage the plate, the fiber organizer comprising a slide-lock engagement feature and a compliant mechanism each adapted to engage in one of the plurality of slide-lock apertures of the plate, the fiber organizer further comprising a plurality of spaced parallel arcuate walls each capped with a cable retention feature configured to retain at least one cable between adjacent ones of the spaced parallel arcuate walls, the cable retention feature comprising first and second spaced projections extending perpendicularly from a respective parallel arcuate wall in a direction of an adjacent parallel arcuate wall.

US Pat. No. 10,191,230

OPTICAL CONNECTORS WITH REVERSIBLE POLARITY

Senko Advanced Components...

1. A reversible polarity fiber optic connector comprising:at least first and second optical ferrules;
a connector housing at least partially surrounding the first and second optical ferrules and having a first exterior wall positioned above the first and second optical ferrules and a second exterior wall positioned beneath the first and second optical ferrules;
a latch coupling positioned on each of the first and second exterior walls of the housing;
a removable latch for engaging either of the first and second exterior wall latch couplings on the connector housing;
wherein positioning the removable latch on the first exterior wall of the connector housing yields a fiber optic connector with a first polarity and positioning the removable latch on the second exterior wall of the housing yields a fiber optic connector with a second polarity, the second polarity being opposite to the first polarity.

US Pat. No. 10,191,229

PLUGGABLE MECHANISM OF OPTICAL TRANSCEIVER

Sumitomo Electric Industr...

1. An optical transceiver that electrically communicates with a host system by being engaged with and disengaged from a cage provided in the host system, the optical transceiver comprising:a housing providing an optical receptacle in one end and an electrical plug in another end thereof, the optical receptacle receiving an optical connector therein, the electrical plug to be engaged with the cage and
a slider movable between a first position and a second position along a direction connecting the optical receptacle with the electrical plug, the slider having a composite opening assembled with both of a bail and a pull-tab, alternatively; and
wherein the composite opening includes a curved opening and a square opening,
wherein the bail provides a hook engaged with the curved opening in the slider; the hook causing a motion of the slider to be movable between the first position and the second position by sliding within the curved opening synchronizing with a rotation of the bail in front of the optical receptacle, and
wherein the pull-tab provides a tab engaged with the square opening of the slider, the tab causing the motion of the slider to be movable between the first position and the second position synchronizing with a linear motion of the pull-tab.

US Pat. No. 10,191,226

CYLINDRICAL OPTICAL FERRULE ALIGNMENT APPARATUS

CommScope, Inc. of North ...

1. A device comprising:a housing including a first port for receiving a first connector;
a ferrule alignment sleeve attached to said housing, wherein said sleeve extends in a longitudinal direction and forms an inner, generally tubular area;
a first rim formed around a first opening at one end of said generally tubular area to receive an end of a first ferrule of the first connector, such that the first ferrule engages said inner, generally tubular area as the first ferrule is inserted into said sleeve;
a first tab adjacent said first rim and projecting away from said first rim and said generally tubular area to interact with a feature attached to the first ferrule to angularly align the first ferrule within said generally tubular area; and
a second tab adjacent said first rim and projecting away from said first rim and said tubular area, wherein said second tab is spaced a predetermined distance away from said first tab.

US Pat. No. 10,191,223

OPTICAL CONNECTOR

Sumitomo Electric Industr...

1. An optical connector comprising:a first plug that secures a first fiber with a first ferrule in an end thereof;
a second plug that secures a second fiber with a second ferrule in an end thereof, the first plug and the second plug jointly rotating around an optical axis common to the first ferrule and the second ferrule, the second plug having a projection;
a sleeve that receives the first ferrule of the first plug in one end thereof and the second ferrule of the second plug in another end thereof;
a shell that encloses the first plug and the second plug therein, the shell providing a hollow that engages with the projection of the second plug; and
a spring provided between the first plug and the shell, the spring pushing the first plug against the second plug outward from the shell,
wherein the first ferrule of the first plug makes physical contact against the second ferrule of the second plug,
wherein the shell has a slit and a cut, the slit providing the hollow in one end thereof,
wherein the cut extends from an edge of the shell facing the second plug to another end of the slit, and
wherein the slit circumferentially extends on a surface of the shell and has an edge closer to the edge of the shell, the edge of the slit making a distance to the edge of the shell gradually increasing from the end continuous to the cut to the hollow.

US Pat. No. 10,191,219

OPTICAL SELECTOR ARRANGEMENT

BAE Systems plc, London ...

1. An optical selector arrangement, comprising:a first set of optical ports, having a first number of optical ports, the first number being greater than or equal to 2;
a second set of optical ports for communicating with the first set of optical ports, the second set of optical ports having a second number of optical ports, the second number being greater than the first number;
a selector interface comprising the second set of optical ports; and
a selector arranged to selectively optically couple the first set of optical ports to a subset of the second set of optical ports of the selector interface corresponding to the first number of optical ports, the selector being rotatable relative to the selector interface to facilitate the selection by optically aligning the first set of optical ports to the subset of the second set of optical ports of the selector interface, the selector being configured to be continuously relatively rotatable over multiple rotations, so as to selectively optically couple the first set of optical ports to a different subset of the second set of optical ports of the selector interface.

US Pat. No. 10,191,148

RADAR SYSTEM FOR VEHICLE AND METHOD FOR MEASURING AZIMUTH THEREIN

MANDO CORPORATION, Pyeon...

1. A system for blocking a reflection signal from a ground surface or from an elevation angle direction, the system comprising:two or more main reception antennas configured to receive echo signals reflected from a target, and generate a main reception signal based on the received echo signals;
a single side lobe suppression antenna configured to receive a side lobe suppression reception signal reflected from the ground surface or from the elevation angle direction; and
a radar configured to
compare a magnitude of the main reception signal with a magnitude of the received side lobe suppression reception signal, and
calculate an azimuth angle of the target by using the received main reception signal when the magnitude of the main reception signal is larger than the magnitude of the side lobe suppression reception signal,
wherein the azimuth angle is calculated by using the speed of light, a measured phase difference of the received echo signals, a distance between the two or more main reception antennas, and a frequency of the main reception signal, and
wherein
each main reception antenna of the two or more main reception antennas includes a phase delay unit installed in a center of a line of the each main reception antenna, and configured to adjust, by using the phase delay unit, a first phase and a second phase of the received echo signals with reference to the center of the line of the each main reception antenna, to have the same phase, in the radar, and
the side lobe suppression antenna includes a vertical connection part installed in a center of a line of the side lobe suppression antenna, and configured to adjust, by using the vertical connection part, a first phase and a second phase of the side lobe suppression reception signal with reference to the center of the line of the side lobe suppression antenna, to have 180 degree phase difference, in the radar.

US Pat. No. 10,191,097

SQUARE-WAVE-BASED IMPEDANCE ANALYSIS

TEXAS INSTRUMENTS INCORPO...

1. An impedance analyzer to analyze the impedance of a device under test (DUT) over a range of frequencies, the impedance analyzer comprising:a microcontroller to generate a first square wave signal at a first frequency;
parallel signal transmission paths between the microcontroller and the DUT, each parallel path to transmit one of the first square wave signal or a square wave signal based on the first square wave signal, the parallel paths comprising:
a first path comprising a first anti-aliasing filter for filtering the first square wave signal to remove frequencies higher than a first filter frequency, the first path to deliver the first square wave signal to the DUT; and
a second path comprising a clock synthesizer integrated circuit (IC), separate from the microcontroller, to generate a second square wave signal, based on the first square wave signal, at a second frequency, the second path further comprising a second anti-aliasing filter for filtering the second square wave signal to remove second frequencies higher than a second filter frequency, the second filter frequency being higher than the first filter frequency; and
a path selection switch controllable by the microcontroller to select one of the parallel paths.

US Pat. No. 10,191,036

SYSTEM FOR DETECTING AND REMOVING BIOLOGICAL ANALYTES IN FLUIDS

NUB4U, Inc., Huntsville,...

1. A fluid cleaning system comprising:a detector module for detecting the presence of one or more biological contaminants in a fluid, said detector module comprising:
a detector module housing having a fluid outlet;
one or more pairs of microcantilever sensors enclosed within said detector module housing, each said pair comprising a reference microcantilever sensor and a detection microcantilever sensor comprising a polymerized receptor, said polymerized receptor having an affinity with a biological contaminant of said one or more biological contaminants, said detection sensor configured to provide a detection signal in the presence of said one or more biological contaminants; and
a contaminant capture manifold enclosed within a contaminant capture housing having an inlet in fluid communication with, and downstream of said detector module outlet and comprising one or more stages, each said stage comprising a contaminant capture element each said contaminant capture element comprising one of a spiral ramp comprising said polymerized receptor, a cylindrical wall coated with said polymerized receptor, and a plurality of microbeads comprised of said polymerized receptor.

US Pat. No. 10,191,018

DUAL ONLINE LIQUID CHROMATOGRAPHY DEVICE AND CONTROL METHOD THEREOF

KOREA UNIVERSITY RESEARCH...

1. A dual online liquid chromatography device comprising:a first pump for injecting a first solvent or a mixed solution containing the first solvent and a second solvent;
a second pump for injecting the first solvent or the mixed solution containing the first solvent and the second solvent;
a sample intake valve connected to the first pump and a sample injector for injecting a sample;
a column selection valve connected to the second pump and the sample intake valve; and
a dual column valve having one side connected to the column selection valve and the other side connected to a first column and a second column, and comprising a plurality of ports, wherein the dual column valve further comprises:
a first column port connected to the first column;
a solid phase extraction column selection port and a solid phase extraction column channel port constituting opposite ends of a first solid phase extraction column (SPE1);
a solid phase extraction column inlet port connected to one side of the column selection valve and selectively connected to the solid phase extraction column selection port or the solid phase extraction column channel port;
a first outlet port adjacent to the solid phase extraction column channel port;
a second outlet port adjacent to the first outlet port;
a second solid phase extraction column selection port and a second solid phase extraction column channel port constituting opposite ends of a second solid phase extraction column (SPE2);
a second solid phase extraction column inlet port connected to the other side of the column selection valve and selectively connected to the second solid phase extraction column selection port and the second solid phase extraction column channel port; and
a second column port connected to the second column.

US Pat. No. 10,191,017

DYNAMIC CHARACTERISTIC CALCULATION APPARATUS AND ITS METHOD FOR MACHINE TOOL

JTEKT CORPORATION, Osaka...

1. An apparatus calculating a dynamic characteristic of a machine tool that executes an interrupted machining of a workpiece by moving a rotational tool having one or plural tool tips relative to the workpiece comprising:a vibration detector configured to detect a vibration property of said rotational tool mounted on the machine tool when said rotational tool is excited to vibrate by a target member prior to the interrupted machining of the workpiece; and
a processor configured to:
calculate a natural frequency of said rotational tool mounted on the machine tool on a basis of said detected vibration property,
replace a pre-excitation natural frequency stored in a memory with said calculated natural frequency, said pre-excitation frequency being determined based on constructional information of said machine tool before said rotation tool is excited to vibrate by the target member, and
generate a command for said machine tool to change a rotational velocity of said rotational tool in said interrupted machining based upon said calculated natural frequency, wherein
said machine tool includes a driving device configured to move said rotational tool relative to said workpiece; and
said rotational tool is excited to vibrate, prior to the interrupted machining of the workpiece, by contacting said rotational tool with said target member mounted on said machine tool without use of man power by driving said driving device without said rotational tool being rotated, or
said rotational tool is excited to vibrate prior to the interrupted machining of the workpiece by contacting said rotational tool with said target member by driving said driving device while said rotational tool is rotated in a counter rotational direction against a rotational direction of the tool when machining.

US Pat. No. 10,191,016

METHOD AND SYSTEM FOR PASSIVE DETECTION, LOCALIZATION AND CHARACTERIZATION OF MECHANICAL WAVE SOURCES USING ULTRASONIC GUIDED WAVES

1. A method of estimating and storing for subsequent, non-contemporaneous use, one or more spatial channel impulse responses corresponding to one or more spatial points of interest on a structure when the structure is in a known state comprising:collecting first data at one or more spatial points of interest on the structure using a movable transducer, used only in this step, wherein collecting first data includes individually exciting at least one fixed transducer on the structure with a known excitation function and recording measurements at the one or more spatial points of interest with the movable transducer;
computing one or more spatial channel impulse response estimates for each of the one or more spatial points of interest based on the collected first data; and
storing said spatial channel impulse response estimates for subsequent, non-contemporaneous use after the structure has transitioned to an unknown state.

US Pat. No. 10,191,015

OBJECT INFORMATION ACQUIRING APPARATUS AND LASER APPARATUS

CANON KABUSHIKI KAISHA, ...

1. An object information acquiring apparatus comprising:irradiation means configured to irradiate an object with a laser beam;
a shutter unit having a shutter disposed on a light path of the laser beam from the irradiation means to the object, configured to restrict an output of the laser beam from the irradiation means to the object;
control means configured to control an irradiation of the laser beam by the irradiation means and an operation of the shutter unit;
a probe configured to receive an acoustic wave generated from the object irradiated with the laser beam; and
construction means configured to generate, using the acoustic wave, characteristic information relating to the object,
wherein the irradiation means is configured to generate the laser beam at a plurality of wavelengths and to irradiate the laser beam with a wavelength selected from among the plurality of wavelengths, and
wherein the control means performs, while the wavelength of the laser beam is switched, a control of closing the shutter and a control of stopping or suppressing the generation of the laser beam by the irradiation means.

US Pat. No. 10,191,014

SYSTEM AND METHOD FOR NONDESTRUCTIVE EVALUATION OF A TEST OBJECT

The Boeing Company, Chic...

1. A system for nondestructive evaluation of a test object, the system comprising:a platform;
an electromagnetic acoustic transducer (EMAT) mounted on the platform and positioned to generate a magnetic field in the test object to create acoustic vibrations that travel along a surface of the test object;
an infrared detector mounted on the platform and positioned to record thermal images of a plurality of test areas on the surface of the test object to detect flaws in the surface of the test object within the plurality of test areas as at least one of the platform and the test object move relative to each other;
a velocity interferometer system for any reflector (VISAR) mounted on the platform and oriented to detect a presence of one of the vibrations in the test object caused by the EMAT in one of the plurality of test areas aligned with the infrared detector; and
a controller connected to the EMAT, the VISAR, and the infrared detector, wherein the controller actuates the EMAT to create the vibrations in the test object the VISCAR, and the infrared detector, wherein the connection synchronizes the creation of the vibrations by the EMAT with the recording of the thermal images of the plurality of test areas by the infrared detector, wherein the controller receives signals from the VISAR indicating the presence of the vibrations in the one of the plurality of test areas aligned with the infrared detector, and the infrared detector is triggered to record each of the thermal images of the one of the plurality of test areas aligned with the infrared detector in response to the VISCAR detecting the one of the vibrations in the one of the plurality of test areas, wherein the controller receives a signal from the infrared detector indicative of the thermal images of the surface of the test object, and the controller records locations of the flaws appearing on the thermal images of the plurality of test areas, wherein the controller receives and records as at least one of the platform and the test object move relative to each other.

US Pat. No. 10,191,013

IMPLEMENTATION OF HETERODYNE EFFECT IN SHM AND TALKING SHM SYSTEMS

The Florida International...

1. A method for a structural health monitoring system, the method comprising:connecting a first signal generator to a first actuator;
connecting a second signal generator to a second actuator;
connecting the first actuator and the second actuator to a subject structure;
generating, by the first signal generator a first signal with a first frequency, and exciting the first actuator with the first signal;
generating, by the second signal generator, a second signal with a second frequency, and exciting the second actuator with the second signal;
retrieving an output signal from the subject structure; and
analyzing the output signal of a sensor to determine whether a structural defect exists by determining whether a third frequency has been created,
the third frequency being equal to the absolute value of the result of the subtraction of the second frequency from the first frequency,
a verbal message being embedded into the first signal, which is set to the first frequency, and the second signal being set to the first frequency.

US Pat. No. 10,191,012

MONITORING ENGINE COMPONENTS

Oxford University Innovat...

1. A method for monitoring local defects in one or more transmission gears of a gearbox during service, comprising:arranging one or more eddy current sensor(s) to interact with the transmission gear(s) as they are rotating during service, wherein the one or more eddy current sensor(s) are carried by a monitoring gear or part of a monitoring gear that is shaped so as to enmesh with the transmission gear(s) to be monitored thereby to pass the sensor(s) across a portion of a surface of the transmission gear(s) during relative movement therebetween;
measuring an amplitude of an output signal from the eddy current sensor(s) resulting from interaction with the rotating engine component; and
detecting a change in shape of the amplitude of the output signal indicative of a local defect, wherein the detecting of the change in shape of the amplitude of the output signal comprises processing the output signal to distinguish the change in shape of the amplitude of the output signal from a bulk change in amplitude of the output signal which indicates a misalignment of the one or more transmission gears, thereby distinguishing the local defect from the misalignment of the one or more transmission gears.

US Pat. No. 10,191,011

RUGGEDIZED APPARATUS FOR ANALYSIS OF NUCLEIC ACID AND PROTEINS

NetBio, Inc., Waltham, M...

1. An apparatus for processing a sample of biomolecular analyte, the apparatus comprising:a holder for supporting a test module, said test module comprising a transparent plate comprising one or more channels, at least one channel in fluid communication with the sample;
an electrophoresis device connected to the holder and for providing energy to the test module;
a light source for emitting a light beam that excites fluorescence in the sample of biomolecular analyte;
a light detector; and
a plurality of optical devices rigidly mounted to a base plate, the base plate being supported by a frame including at least one damping device to reduce the transmission of vibrations generated below the frame to base plate.

US Pat. No. 10,191,010

TRANSFER MEMBRANE RETAINING JIG AND SEPARATION-TRANSFER DEVICE

SHARP LIFE SCIENCE CORPOR...

1. A transfer-membrane retaining jig for retaining a transfer membrane in a separation-transfer device that separates analyte by way of electrophoresis, dispenses the analyte thus separated from a dispensing part, and transfers the analyte thus separated to the transfer membrane by causing the transfer membrane to abut the dispensing part and move along a predetermined direction, the transfer-membrane retaining jig comprising:a fixing part that fixes at least one end of the transfer membrane in the predetermined direction,
wherein the fixing part includes: an elastic body that abuts the transfer membrane from an opposite side to the dispensing part; and
a pressing member that presses the transfer membrane against the elastic body.

US Pat. No. 10,191,009

ELECTROCHEMICAL DETERMINATION OF HEAVY METALS

UNIVERSITY OF LOUISVILLE ...

1. A method of analyzing dissolved metals in a sample solution, the sample solution being contained in a cell having a fixed and known volume, the method comprising:initiating a first reduction reaction in the sample solution which contains two or more dissolved metals by applying a first deposition potential for an interval of time representing a first deposition pulse, wherein the first reduction reaction results in non-exhaustive deposition of one or more of the dissolved metals upon an electrode, wherein the one or more dissolved metals deposited during the first reduction reaction comprise one or more interferents;
initiating a first oxidation reaction by applying a stripping potential for an interval of time, representing a first stripping pulse, that is sufficient to strip the one or more interferents from the electrode that were deposited during the first reduction reaction, and measuring electrical current generated during the first stripping pulse;
after the first oxidation reaction, initiating a second reduction reaction by applying a deposition potential for an interval of time, representing a second deposition pulse, that results in exhaustive deposition of the one or more interferents upon the electrode;
initiating a second oxidation reaction by applying a stripping potential for an interval of time, representing a second stripping pulse, that is sufficient to strip all the one or more interferents from the electrode that were deposited during the second reduction reaction, and measuring electrical current generated during the second stripping pulse;
after the second oxidation reaction, initiating a third reduction reaction in the sample solution by applying a second deposition potential different from the first deposition potential for an interval of time representing a third deposition pulse, wherein the third reduction reaction results in non-exhaustive deposition of the one or more dissolved metals comprising the one or more interferents and at least one analyte upon the electrode;
initiating a third oxidation reaction by applying a stripping potential for an interval of time, representing a third stripping pulse, that is sufficient to strip the one or more interferents and the at least one analyte from the electrode that were deposited during the third reduction reaction, and measuring electrical current generated during the third stripping pulse;
after the third oxidation reaction, initiating a fourth reduction reaction by applying a deposition potential different from the first deposition potential, for an interval of time that results in exhaustive deposition of the one or more interferents and the at least one analyte upon the electrode;
initiating a fourth oxidation reaction by applying a stripping potential for an interval of time, representing a fourth stripping pulse, that is sufficient to strip the one or more interferents and the at least one analyte from the electrode that were deposited during the fourth reduction reaction, and measuring electrical current generated during the fourth stripping pulse; and
calculating a concentration of the at least one analyte in the sample solution based on a quantitative difference between the absolute charge associated with stripping the one or more interferents from the electrode, subtracted from the absolute charge associated with stripping the one or more interferents and the at least one analyte from the electrode.

US Pat. No. 10,191,008

GAS SENSOR WITH SOLID ELECTROLYTE HAVING WATER VAPOR DIFFUSION BARRIER COATING

Life Safety Distribution ...

1. A gas sensor comprising:(a) a housing;
(b) a ceramic substrate having a capillary extending through the ceramic substrate, and at least one of a sensing electrode, a reference electrode, or a counter electrode disposed on a first surface;
(c) solid electrolyte in contact with the at least one of the sensing electrode, the reference electrode, or the counter electrode;
(d) a barrier coating disposed over the solid elect wherein the barrier coating encapsulates the at least one of the sensing electrode, the reference electrode, or the counter electrode and the solid electrolyte, wherein the barrier coating comprises a layer of silicone and a layer of parylene, wherein the layer of parylene is on the outer surface of the layer of silicone, wherein the layer of silicone directly covers the solid electrolyte.

US Pat. No. 10,191,007

SULFUR OXIDES DETECTION SYSTEM

TOYOTA JIDOSHA KABUSHIKI ...

1. A sulfur oxides detection system comprising:a device part arranged in an exhaust passage of an internal combustion engine and comprising a first electrochemical cell having a first solid electrolyte layer having oxide ion conductivity, a first electrode arranged on one surface of the first solid electrolyte layer so as to be exposed to gas to be measured, and a second electrode arranged on an other surface of the first solid electrolyte layer so as to be exposed to the atmospheric air, and a diffusion regulating layer to regulate diffusion of the gas to be measured;
a power supply to supply voltage across the first electrode and the second electrode;
a detector to detect a first current correlation parameter correlated with a current flowing between the first electrode and the second electrode; and
an electronic control part to control the power supply and to acquire the first current correlation parameter from the detector, wherein
the electronic control part is to control the power supply so that a first voltage which is a decomposition start voltage of water and sulfur oxides or greater is to be applied across the first electrode and the second electrode and to calculate a concentration of sulfur oxides in the gas to be measured based on the first current correlation parameter detected by the detector if the first voltage is applied across the first electrode and the second electrode and
the electronic control part is to judge whether a concentration of water in the gas to be measured is stable and does not calculate the concentration of sulfur oxides in the gas to be measured if the electronic control part judges that the concentration of water in the gas to be measured is not stable.

US Pat. No. 10,191,006

HUMIDITY SENSOR

ABLIC INC., (JP)

1. A humidity sensor, comprising:a semiconductor substrate;
an insulating film formed on a surface of the semiconductor substrate;
a plurality of first electrodes and a plurality of second electrodes, both formed on the insulating film and arranged so that each of the plurality of first electrodes is adjacent to one of the plurality of second electrodes in each of four directions of up, down, right, and left when viewed in plan view, while each of the plurality of second electrodes is adjacent to one of the plurality of first electrodes in each of four directions of up, down, right, and left when viewed in plan view, except in a perimeter of the arrangement;
a first metal wiring completely embedded in the insulating film and electrically connecting, through a via, one of the plurality of first electrodes to another one of the plurality of first electrodes;
a second metal wiring completely embedded in the insulating film and electrically connecting, through a via, one of the plurality of second electrodes to another one of the plurality of second electrodes; and
a humidity sensitive film formed on the plurality of first electrodes and the plurality of second electrodes.

US Pat. No. 10,191,005

ULTRA-COMPACT, PASSIVE, VARACTOR-BASED WIRELESS SENSOR USING QUANTUM CAPACITANCE EFFECT IN GRAPHENE

Regents of the University...

1. A sensor comprising:a graphene quantum capacitance varactor comprising:
an insulator layer;
a dielectric layer;
a gate electrode between the insulator layer and the dielectric layer;
a graphene layer on the dielectric layer, wherein capacitance of the graphene layer changes in response to a sensed electrical charge collected proximate to the graphene layer upon exposure to a sample, and wherein the graphene layer comprises an exposed surface opposite the dielectric layer; and
at least one contact electrode on the graphene layer and making electrical contact with the graphene layer.

US Pat. No. 10,191,004

MICROCANTILEVER BASED SELECTIVE VOLATILE ORGANIC COMPOUND (VOC) SENSORS AND METHODS

University of South Carol...

1. A system for identifying a volatile organic compound; the system comprising:a fluid flow path configured for carrying a volatile organic compound;
a power source configured for supplying a driving voltage; and
a triangular microcantilever held in electrical communication with the power source, the microcantilever comprising a first arm extending from a base, a second arm extending from the base, and a tip at a junction of the first arm and the second arm, the first arm having a cross section that decreases in size with a first regular taper, the first regular taper beginning at the base and extending to the tip, the second arm having a cross section that decreases in size with a second regular taper, the second regular taper beginning at the base and extending to the tip, the tip being in the fluid flow path, wherein upon contact between the microcantilever and the volatile organic compound in conjunction with application of the driving voltage to the microcantilever, the first arm exhibits a first electrical resistance, the second arm exhibits a second electrical resistance, and the tip exhibits a third electrical resistance, the third electrical resistance differing from the first and second electrical resistances.

US Pat. No. 10,191,003

METHODS AND APPARATUS FOR A MOISTURE DETECTOR

Helvetia Wireless LLC, S...

1. A sensor for detecting a spread of a liquid, the sensor comprising:a substrate;
a first conductor, the first conductor having a first sheet resistance;
a second conductor, the second conductor having a second sheet resistance; and
a processing circuit; wherein:
a magnitude of the first sheet resistance is greater than a magnitude of the second sheet resistance;
a portion of the first conductor is positioned a first distance away from a portion of the second conductor;
a first portion of the liquid is positioned relative to a first end portion of the first conductor in accordance with a first voltage applied between the first end portion of the first conductor and a first end portion of the second conductor;
a second portion of the liquid is positioned relative to a second end portion of the first conductor in accordance with a second voltage applied between the second end portion of the first conductor and the first end portion of the second conductor;
the first portion of the liquid is positioned a second distance away from the second portion of the liquid along the first conductor;
the second distance relates to the spread of the liquid with respect to the first conductor;
the processing circuit determines a third distance from the first end portion of the first conductor to the first portion of the liquid in accordance with the first voltage;
the processing circuit determines a fourth distance from the second end portion of the first conductor to the second portion of the liquid in accordance with the second voltage; and
the processing circuit relates a position of at least one of the third distance from the first end portion of the first conductor and the fourth distance from the second end portion of the first conductor to a position on the substrate.

US Pat. No. 10,191,002

GAS SENSOR WITH FREQUENCY MEASUREMENT OF IMPEDANCE

Stichting IMEC Nederland,...

1. A gas sensor comprising:at least one sensing element comprising an ionic liquid;
at least one pair of electrodes coupled to the at least one sensing element;
an electric power source configured to provide a frequency-controllable electrical AC signal to the at least one pair of electrodes so as to generate an impedimetric response signal from the at least one sensing element; and
readout circuitry configured to analyze resistive and capacitive components of the impedimetric response signal.

US Pat. No. 10,191,001

CONVEYOR-BELT SYSTEM FOR MEASURING CONDITIONS THAT VARY THE RESONANT FREQUENCY OF A RESONANT CIRCUIT

Laitram, L.L.C., Harahan...

1. A conveyor belt comprising:an endless belt body;
a plurality of resonant circuits disposed at sensor positions in the endless belt body, each of the resonant circuits including:
an inductor; and
a capacitor connected to the inductor to form the resonant circuit with a resonant frequency determined by the inductance of the inductor and the capacitance of the capacitor;
a plurality of capacitor plates, wherein each of the resonant circuits is connected to one or more capacitor plates to capacitively couple the resonant circuit through one or more stationary capacitor plates external to the conveyor belt;
wherein at least one of the inductance of the inductor and the capacitance of the capacitor is varied by a varying condition affecting the conveyor belt.

US Pat. No. 10,191,000

STABLE NANOCRYSTALLINE ORDERING ALLOY SYSTEMS AND METHODS OF IDENTIFYING SAME

Massachusetts Institute o...

1. An alloy comprising:a mixture of a solute element and a solvent element, the mixture having a phase including at least one of a stable nanocrystalline phase, a metastable nanocrystalline phase, and a non-nanocrystalline phase,
the phase having a first thermodynamic parameter associated with grain boundary segregation of the alloy system, a second thermodynamic parameter associated with phase separation of the alloy system, and a third thermodynamic parameter associated with intermetallic compound formation of the alloy system,
wherein the phase is stable when the first thermodynamic parameter, the second thermodynamic parameter, and the third thermodynamic parameter are within a predetermined region of a stability map of the alloy.

US Pat. No. 10,190,999

NUCLEAR MAGNETIC RESONANCE AND SATURATION WELL LOGS FOR DETERMINING FREE WATER LEVEL AND RESERVOIR TYPE

Saudi Arabian Oil Company...

5. A method for determining characteristics of a hydrocarbon reservoir, the method comprising:conducting, using a nuclear magnetic resonance (NMR) logging tool, a nuclear magnetic resonance (NMR) logging operation of a targeted reservoir section of a wellbore extending into a hydrocarbon reservoir to generate a nuclear magnetic resonance (NMR) log of the targeted reservoir section;
conducting, using a resistivity logging tool, a resistivity logging of the targeted reservoir section to generate an uninvaded water saturation (Sw) log of the targeted reservoir section;
determining, by a control unit, for each of a plurality of depths in the targeted reservoir section, a T2 cutoff point for the depth based on values of the NMR log and the uninvaded water saturation (Sw) log for the depth;
identifying, by the control unit, a subset of the T2 cutoff points that exhibit a hyperbolic trend;
determining, by the control unit, a theoretical cutoff curve corresponding to the subset of the T2 cutoff points;
determining, by the control unit, a free water level (FWL) of the reservoir based on the theoretical cutoff curve; and
determining, by the control unit, a rock type of the reservoir based on the theoretical cutoff curve.

US Pat. No. 10,190,998

METHOD AND DEVICE FOR EVALUATING AND PREDICTING A SHALE OIL ENRICHMENT AREAS OF FAULT LACUSTRINE BASINS

1. A method for evaluating and predicting a shale oil enrichment area of a fault lacustrine basin, wherein the method comprising:Step 1, obtaining analytical test material for a key core well in a fine-grained facies region of the shale oil enrichment area of the fault lacustrine basin, and obtaining key data of the target stratum logging interpretation based on the analytical test material, wherein the key data of the target stratum logging interpretation includes a dolomite-to-formation ratio, dolomite thickness, a lithology profile, a total organic carbon (TOC) average value, and effective source rock thickness;
Step 2, determining a source-reservoir configuration relationship according to a longitudinal superposition relationship of different types of rock in the lithology profile, and establishing a single-well lithofacies mode in conjunction with the dolomite-to-formation ratio and the TOC average value;
Step 3, in the single-well lithofacies mode, forming a dolomite-to-formation ratio contour map, a TOC contour map and a source-reservoir configuration relationship plane distribution map respectively by using the dolomite-to-formation ratio, the TOC average value and the source-reservoir configuration relationship, and superposing the dolomite-to-formation ratio contour map, the TOC contour map and the source-reservoir configuration relationship plane distribution map to form a lithofacies plane distribution map; and
Step 4: on the basis of the lithofacies plane distribution map, superposing a vitrinite reflectance contour map and a dolomite thickness contour map formed through the dolomite thickness to obtain a corresponding evaluation and prediction map of the shale oil enrichment area of the fault lacustrine basin.

US Pat. No. 10,190,997

X-RAY DEVICE, METHOD, MANUFACTURING METHOD FOR STRUCTURE, PROGRAM, AND RECORDING MEDIUM ON WHICH PROGRAM IS RECORDED

NIKON CORPORATION, Tokyo...

1. An X-ray device comprising:an irradiator configured to irradiate an X-ray to a measuring object;
a detector configured to detect transmission X-ray transmitted through the measuring object; and
a controller connected to the irradiator and the detector, and configured to:
generate first information, based on an image reconstructed from a result of detecting the transmission X-ray, the first information including information of an area in which an absorption coefficient of X-ray detected falls within a first range and information of an area in which an absorption coefficient of X-ray detected falls within a second range that is different from the first range;
acquire ratio information indicating a ratio between a first substance and a second substance included in the measuring object;
based on the ratio information and the first information, generate second information including information of an area which corresponds to the first substance and in which an absorption coefficient of X-ray falls within a third range obtained by merging the first range and the second range, so that a frequency distribution of signal intensity representing the absorption coefficient within the first range and the absorption coefficient within the second range is reconstructed to a frequency distribution of signal intensity representing the absorption coefficient within the third range; and
generate a modified image in which an area corresponding to the first substance is determined based on the second information.

US Pat. No. 10,190,996

METHOD AND DEVICE FOR CONTROLLING ROTARY TABLE

MITUTOYO CORPORATION, Ka...

1. A method for controlling a rotary table for rotating an object disposed on the rotary table, the method comprising:intermittently rotating the rotary table by a minute angle;
shifting the rotary table in a two-dimensional direction orthogonal to a rotation axis of the rotary table; and
performing, using a processor, control of a shift position of the rotary table in the two-dimensional direction in synchronization with rotation of the rotary table, wherein rotation is made possible about a virtual rotation center that is set at an arbitrary position on the rotary table, the performing the control comprising:
setting coordinates (a, b) of a position as a rotation center of the rotary table represented by a=L cos ? and b=L sin ?;
moving the rotation center to a new position (a?, b?) with rotation of ??;
shifting “a” by L cos(?+??)?L cos ?;
shifting “b” is shifted by L sin(?+??)?L sin ?, in order to bring the new position (a?, b?) back to the original position (a, b); and
correcting rotation eccentricity owing to eccentricity of the rotary table;
producing an eccentricity correction table in advance;
calculating a destination of the center of the rotary table;
interpolating an eccentric amount in the eccentricity correction table to calculate an eccentric amount r? of a rotation angle ?;
thereafter calculating a correction amount from the eccentric amount;
correcting the destination of the center of the rotary table is corrected on the eccentricity;
calculating a center C?? of the rotary table after the correction; and
shifting the center of the rotary table to the center C??, while the rotary table is rotated by a rotation angle ?.

US Pat. No. 10,190,995

METHODS AND APPARATUSES FOR ANALYSING FLUID SAMPLES

Liverpool John Moores Uni...

1. A method for analysing a fluid sample, the method comprising:loading the sample in a sample space in a sensor comprising an input and an output;
applying an electromagnetic input signal to the input;
measuring at the output a response signal comprising an output signal produced by the sensor while the sensor is contacted by the sample and the electromagnetic input signal is applied to the input;
comparing the response signal against the electromagnetic input signal to generate a comparison;
matching the comparison against a set of comparisons for known substances; and
sweeping the electromagnetic input signal across a range of frequencies and detecting a resonance, wherein the swept frequency range includes more than one resonance.

US Pat. No. 10,190,994

APPARATUS, METHOD AND COMPUTER PROGRAM PRODUCT FOR INSPECTION OF AT LEAST SIDE FACES OF SEMICONDUCTOR DEVICES

KLA-Tencor Corporation, ...

1. An apparatus for inspecting at least side faces of a semiconductor device comprising:a camera, defining an imaging beam path;
a mirror block, having a first mirror, a second mirror, a third mirror, and a fourth mirror, the mirrors being arranged such that they surround a free space in the form of a rectangle, and the opposing first mirror and third mirror are fixedly mounted and the opposing second mirror and fourth mirror are movably mounted; and
a tilted mirror, for directing an image of at least the side faces semiconductor device from the mirror block to the camera.

US Pat. No. 10,190,992

STRUCTURE STATUS DETERMINATION DEVICE, STATUS DETERMINATION SYSTEM, AND STATUS DETERMINATION METHOD

NEC CORPORATION, Tokyo (...

1. A status determination device comprising:a displacement calculation circuit that, from time-series images of a structure surface before and after loading application, calculates a two-dimensional spatial distribution of a displacement of the time-series images;
a correction amount calculation circuit that calculates a correction amount based on a moving amount of the structure surface in a normal direction due to the loading application, from the two-dimensional spatial distribution of the displacement of the time-series images;
a displacement correction circuit that extracts a two-dimensional spatial distribution of a displacement of the structure surface, by subtracting the correction amount from the two-dimensional spatial distribution of the displacement of the time-series images; and
an abnormality determination circuit that identifies a defect of the structure, based on comparison between the two-dimensional spatial distribution of the displacement of the structure surface and a prepared spatial distribution of a displacement having been prepared in advance.

US Pat. No. 10,190,991

METHOD FOR ADAPTIVE SAMPLING IN EXAMINING AN OBJECT AND SYSTEM THEREOF

Applied Materials Israel ...

1. A method of examining an object, the method comprising:(a) identifying, by a processor, a plurality of potential defects, each potential defect of the plurality of potential defects being associated with a potential defect location;
(b) performing, by the processor, a first clustering of the plurality of potential defects to obtain a first subset and one or more second subsets, the clustering performed in accordance with spatial distances between potential defect locations such that potential defects in the first subset are characterized by higher density in at least one physical area than potential defects in the one or more second subsets;
(c) assigning, by the processor, first probabilities to potential defects in the first subset to be valid defects, the first probabilities being calculated in accordance with a first policy;
(d) assigning, by the processor, second probabilities to potential defects in the one or more second subsets to be valid defects, the second probabilities being calculated in accordance with one or more second policies specifying how to combine at least two second factors associated with potential defect locations;
(e) selecting, by the processor, at least one potential defect from the first subset and the one or more second subsets for review by a review tool in accordance with a third policy specifying how to combine potential defects from a plurality of subsets into a merged list, and wherein the selecting of the at least one potential defect for review by the review tool is further in accordance with a strategy indicating how to combine top elements from the merged list and randomly selected elements from the merged list in accordance with a number of reviews from the review tool;
(f) receiving, by the processor, validity or class indications for potential defects in a potential defect lists associated with the selected at least one potential defect, the validity or class indications being received subsequent to potential defects in the potential defect lists being reviewed by the review tool; and
(g) subsequent to a stopping criteria not being observed:
(i) updating, by the processor, the first, second, or third policy in accordance with validation or classification of an item in the first subset and the one or more second subsets; and
(ii) repeating, by the processor, steps (c)-(g) in accordance with the first, second, or third policy as updated, until the stopping criteria is observed.

US Pat. No. 10,190,990

LED-BASED FIBER PROPERTY MEASUREMENT

Uster Technologies, AG, ...

1. An apparatus for measuring at least one of color and trash in a fiber sample, the apparatus comprising:a light emitting diode light source for generating an incident light that is directed toward the fiber sample, and reflected by the fiber sample, thereby producing a reflected light,
a sensor for receiving the reflected light and producing a signal,
a controller for controlling the light source and the sensor, and at least one of receiving and adjusting the signal, and
means for conditioning at least one of the incident light, the reflected light and the signal to compensate for differences between the light emitting diode light source and a xenon light source.

US Pat. No. 10,190,989

METHOD AND APPARATUS FOR INSPECTING APPEARANCE OF OBJECT USING IMAGES PICKED UP UNDER DIFFERENT LIGHT QUANTITIES

DENSO WAVE INCORPORATED, ...

1. An apparatus for inspecting an appearance of an object, comprising:a lighting unit radiating light to an object being inspected, the lighting unit being capable of selectively adjusting a quantity of the light to a first light quantity and a second light quantity, the second light quantity being different from the first light quantity;
a camera optically imaging the object, the camera being fixed positionally; and
a control unit configured to
control the lighting unit and the camera so as to provide a first image picked up by the camera in a state where the light is selected to be of the first light quantity and is radiated to the object and a second image picked up by the camera in a state where the light is selected to be of the second light quantity and is radiated to the same object, each of the first and second images being composed of pixels having pixel values;
calculate differences, pixel by pixel, between the pixel values of the first image and the pixel values of the second image; and
determine whether the object has a non-defective appearance or a defective appearance based on a comparison between the calculated differences of the pixel values and reference pixel values which are set, pixel by pixel, as a reference for the determination,
wherein the reference pixel values are set as difference pixel values between pixel values of a third image and pixel values of a fourth image, the third image being picked up by the camera in a state where the light is selected to be of the first light quantity and is radiated to a reference object which serves as a reference to the object being inspected, the fourth image being picked up by the camera in a state where the light is selected to be of the second light quantity and is radiated to the reference object.

US Pat. No. 10,190,988

METHODS OF LASER WELDING DISPOSABLE DIAGNOSTIC TEST ELEMENTS

Roche Diabetes Care, Inc....

17. A disposable diagnostic test element for analyzing a body fluid sample having or suspected of having an analyte of interest, the test element comprising:a stacked or layered arrangement of a base layer, a cover layer, and optionally an intermediate layer, wherein one of the layers is made of an absorbing material configured to absorb radiation from a laser beam and at least one other of the layers is made of a transparent material configured to transmit radiation from the laser beam, wherein the absorbing and transparent materials are fused together in a weld area by laser welding seams, wherein at least one of the layers includes a coating in the form of a chemistry layer adapted to react with the analyte of interest when conducting a test, and wherein the coating covers the weld area and contains one or more components that absorb and/or scatter the radiation from the laser beam at least in part.

US Pat. No. 10,190,987

METHOD FOR INLINE MEASUREMENT ON SIMULATED MOVING BED UNITS OR HYBRID UNITS FOR SEPARATION BY SIMULATED MOVING BED AND CRYSTALLIZATION, AND APPLICATION TO THE CONTROL AND REGULATION OF SAID UNITS

IFP Energies Nouvelles, ...

1. A method for measuring concentrations of species present at at least one point during a separation process operating as a simulated moving bed (SMB) reactor, or a hybrid separation operating as a simulated moving bed (SMB) separation and a further crystallization, said method employing:an immersion probe placed at a point of the reactor or at a point located on a stream entering or leaving said reactor (termed the measurement point),
a thermocouple placed at a distance between an immersed end of the probe and the thermocouple which is at most 30 cm from the measurement point,
a sampling point downstream of the measurement point for analysis by a reference analytical technique during a calibration step,in a manner such as to provide, a Raman spectrum and a temperature simultaneously for each measurement point, said method comprising:a) calibration by inline acquisition of Raman spectra for different mixtures covering a range of concentrations of the species which are to be measured and under temperature and pressure conditions which are representative of an industrial unit and sampling, simultaneously in situ at the sampling point, of moving mixture for analysis by a reference technique, enabling one or more mathematical model(s) to be constructed per constituent as a function of its content;
b) analysis by inline signal processing of the Raman spectrum obtained at each measurement point by means of a chemometric mathematical method employing the or said models constructed during the calibration for each constituent, taking into account the temperature (Tspl) at the measurement point under consideration as well as the range of concentrations Cj of the species present at said measurement point, in order to obtain the concentration Ci of each species present, in which, for each of a) and b), the acquisition of each Raman spectrum is carried out by:
sending a monochromatic signal through a first optical fibre connected to the immersion probe, originating from a laser source with a wavelength of 785 nm plus or minus 1 nm,
retrieving, through a second optical fibre also connected to the immersion probe, a signal corresponding to the Raman effect termed the Raman signal, which is sent to a spectrometer,
retrieving the Raman spectrum of the signal under consideration at the output from the spectrometer.

US Pat. No. 10,190,986

SPATIALLY RESOLVED LIGAND-RECEPTOR BINDING ASSAYS

Abbott Laboratories, Abb...

1. A method for determining the concentration of an analyte in a sample comprising the steps of:(a) combining in a reaction mixture (i) a sample suspected of containing an analyte, (ii) a first receptor attached to a microparticle that binds to the analyte, and (iii) a fluorescently labeled second receptor that binds to the analyte, and allowing formation of a complex comprising the microparticle attached to the first receptor, the analyte, and the fluorescently labeled second receptor;
(b) acquiring a white light image of the reaction mixture in order to determine the location of the microparticle in the reaction of step (a) and a fluorescence image of the reaction mixture in order to determine the location of the fluorescently labeled second receptor in the reaction of step (a);
(c) selecting at least one region of interest from the images acquired in step
(b), wherein the at least one region of interest is a region from which light signals emanate from the complex formed in step (a);
(d) selecting pixels in the at least one region of interest for analysis;
(e) calculating and recording the average and variance of the counts per pixel for the pixels selected in step (d), wherein the counts per pixel is the number of photons counted per pixel per unit of time;
(f) omitting pixels that have counts greater or less than a specified variance;
(g) calculating average counts per pixel of the remaining pixels; and
(h) determining the concentration of the analyte from the data in step (g).