US Pat. No. 10,797,005

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor package comprising:a die comprising a first surface and a second surface opposite to the first surface;
a warpage control unit disposed over the second surface of the die and entirely overlapping the second surface, wherein the warpage control unit comprises:
an adhesive portion disposed over the second surface of the die; and
a warpage adjustable portion sandwiched between the adhesive portion and the die; and
a molding compound surrounding the die and the warpage control unit,
wherein a thickness of the warpage adjustable portion is directly proportional to a fan-out ratio, wherein the fan-out ratio is between an area of the die and an area of the semiconductor package,
wherein the adhesive portion has a first surface facing the die and a second surface opposite to the first surface, and the second surface of the adhesive portion of the warpage control unit aligns with a surface of the molding compound.

US Pat. No. 10,797,004

SEMICONDUCTOR DEVICE PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a lead frame comprising a connection element and a plurality of leads;
a package body encapsulating the lead frame, wherein the package body includes a lower surface and an upper surface opposite to the lower surface, the package body includes a cavity exposing at least one of the leads;
at least one conductive via disposed in the cavity of the package body, electrically connected to the connection element, and exposed from the upper surface of the package body; and
a conductive layer disposed on the upper surface of the package body and the conductive via.

US Pat. No. 10,797,003

CIRCUIT MODULE

TDK CORPORATION, Tokyo (...

1. A circuit module comprising:a wiring structure;
an electronic component arranged on an upper surface of the wiring structure;
an insulating resin layer which is provided on the upper surface of the wiring structure and in which the electronic component is embedded; and
a metal layer provided on a side surface of the insulating resin layer and a side surface of the wiring structure,
wherein when the surface roughness of the side surface of the insulating resin layer is expressed as R1, and the surface roughness of the side surface of the wiring structure is expressed as R2, R1 and R2 differ from each other.

US Pat. No. 10,797,002

SPUTTERING SYSTEMS AND METHODS FOR PACKAGING APPLICATIONS

Skyworks Solutions, Inc.,...

1. A device for processing a plurality of packaged modules, the device comprising:a ring having an inner boundary and configured to be utilized in a deposition apparatus;
a stencil having a first side and a second side, and defining a plurality of openings, each opening dimensioned to receive a portion of a packaged module to be processed from the first side of the stencil;
a tape that attaches at least some of the second side of the stencil to the ring such that the stencil is positioned at least partially within the inner boundary of the ring, to allow an assembly of the stencil, the tape and the ring to be utilized in the deposition apparatus; and
a two-sided adhesive member attached to the first side of the stencil, and having a plurality of openings corresponding to the openings of the stencil, each opening of the two-sided adhesive dimensioned to engage an underside of the respective packaged module while allowing the portion of the packaged module to enter the corresponding opening of the stencil, each opening of the two-sided adhesive smaller than the corresponding opening of the stencil such that an edge of the opening of the two-sided adhesive member forms an overhang relative to an edge of the corresponding opening of the stencil.

US Pat. No. 10,797,001

THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES

Taiwan Semiconductor Manu...

1. A three-dimensional integrated circuit structure, comprising:a first die comprising a first integrated circuit region, a first seal ring region surrounding the first integrated circuit region, and a first alignment mark within the first integrated circuit region; and
a second die bonded to the first die, and comprising a second integrated circuit region and a second seal ring region surrounding the second integrated circuit region,
wherein the first alignment mark is around a corner of the second seal ring region from a top view, and
wherein the first alignment mark comprises a first alignment pattern parallel to a first border of the second seal ring region, and a second alignment pattern parallel to a second border of the second seal ring region.

US Pat. No. 10,797,000

EMBEDDED MULTI-DEVICE BRIDGE WITH THROUGH-BRIDGE CONDUCTIVE VIA SIGNAL CONNECTION

Intel Corporation, Santa...

1. A microelectronic structure comprising:a microelectronic substrate having a cavity, wherein the microelectronic substrate includes a plurality of conductive routes extending from a first surface of the microelectronic substrate and a plurality of conductive routes extending into the microelectronic substrate from a bottom surface of the cavity;
a bridge disposed within the cavity, wherein the bridge has a plurality of signal lines, wherein the bridge has a plurality of through-bridge conductive vias extending from the first surface of the bridge to a second surface of the bridge, and wherein at least one through-bridge conductive vias of the plurality of through-bridge conductive vias is electrically connected to at least one conductive route of the plurality of conductive routes at the bottom surface of the cavity;
a first microelectronic device, wherein the first microelectronic device is electrically attached to at least one conductive route of the plurality of conductive routes extending from a first surface of the microelectronic substrate, wherein the first microelectronic device is electrically attached to at least one signal line of the plurality of the signal lines, and wherein the first microelectronic device is electrically attached to at least one through-bridge conductive via of the plurality of through-bridge conductive vias; and
a second microelectronic device, wherein the second microelectronic device is electrically attached to at least one conductive route of the plurality of conductive routes extending from a first surface of the microelectronic substrate, wherein the second microelectronic device is electrically attached to at least one signal line of the plurality of the signal lines, and wherein the second microelectronic device is electrically attached at least one through-bridge conductive via of the plurality of through-bridge conductive vias;
wherein the first microelectronic device is electrically connected to the second microelectronic device through at least one signal line of the plurality of signal lines of the bridge.

US Pat. No. 10,796,999

FLOATING-BRIDGE INTERCONNECTS AND METHODS OF ASSEMBLING SAME

Intel Corporation, Santa...

1. A semiconductor apparatus, comprising:an interconnect bridge, wherein the interconnect bridge includes a footprint dimension;
a middle semiconductive device positioned within the interconnect-bridge footprint dimension;
a first semiconductive device and a subsequent semiconductive device positioned across the middle semiconductive device, wherein the first semiconductive device and the subsequent semiconductive device are coupled through the interconnect bridge further including:
a semiconductor package substrate onto which the first semiconductive device, the middle semiconductive device and the subsequent semiconductive device are mounted, and wherein the interconnect bridge is suspended above the semiconductor package substrate;
an interlayer dielectric that at least partially encapsulates the middle semiconductive device;
a bridge-interconnect filled via that penetrates the interlayer dielectric to contact the interconnect bridge; and
a filled via that penetrates the interconnect layer dielectric to contact the middle semiconductive device.

US Pat. No. 10,796,998

EMBEDDED PACKAGING FOR HIGH VOLTAGE, HIGH TEMPERATURE OPERATION OF POWER SEMICONDUCTOR DEVICES

GaN Systems Inc., Ottawa...

1. A semiconductor device comprising:a package comprising a dielectric body;
a semiconductor die embedded in the dielectric body of the package;
the semiconductor device being rated for operation with at least one of an operating voltage ?100V and an operating temperature ?100 C,
wherein, the dielectric body comprises a dielectric polymer composition characterised by:
a conduction transition temperature Tc,
a first activation energy EaLow for conduction in a first range of temperatures below Tc,
a second activation energy EaHigh for conduction in a second range of temperatures above Tc,
and
the dielectric polymer composition having values of Tc, EaLow, and EaHigh that provide a conductivity less than a reliability threshold value of conduction for the rated operating voltage and temperature.

US Pat. No. 10,796,997

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package, comprising:a semiconductor chip having an active surface on which a connection pad is disposed;
a connection member disposed on the active surface of the semiconductor chip and including a pad layer disposed on an upper surface thereof, a redistribution layer electrically connected to the connection pad, and an insulating layer;
a bonding member disposed between the connection pad of the semiconductor chip and the pad layer of the connection member to connect the semiconductor chip with the connection member;
a surface treatment layer disposed on an upper surface of the pad layer of the connection member and including at least one metal layer; and
an under-bump metallurgy (UBM) layer embedded in the connection member and electrically connected to the redistribution layer of the connection member,
wherein the UBM layer includes a UBM pad embedded in the insulating layer of the connection member, at least one plating layer disposed on the UBM pad, and a UBM via penetrating through at least a portion of the insulating layer of the connection member and electrically connecting the redistribution layer of the connection member with the UBM pad,
the surface treatment layer is disposed only on one surface of the pad layer facing the bonding member, and the plating layer of the UBM layer is disposed only on one surface of the UBM pad opposing the UBM via,
the surface treatment layer is substantially planar,
the surface treatment layer and the plating layer of the UBM layer include the same electrolytic metal layers,
the surface treatment layer includes a first plating layer including gold (Au), and a second plating layer disposed between the pad layer and the first plating layer and including nickel (Ni), and
the plating layer of the UBM layer includes a third plating layer including gold (Au), and a fourth plating layer disposed between the UBM pad and the third plating layer and including nickel (Ni).

US Pat. No. 10,796,996

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate having an active device thereon;
a dielectric layer disposed on the substrate; and
a conductive stack disposed within the dielectric layer, the conductive stack electrically connecting to the active device, wherein the conductive stack comprises:
at least one first conductive layer and a second conductive layer disposed over the at least one first conductive layer; and
a contact structure disposed between the at least one first conductive layer and the second conductive layer, the contact structure comprising:
a contact via electrically connecting the at least one first conductive layer to the second conductive layer; and
a glue layer conformal to sidewalls and a bottom surface of the contact via, the glue layer having a plurality of isolated lattices and an amorphous region that includes an interface, wherein the isolated lattices are stacked over one another and separately arranged above and below the interface of the amorphous region, and a lowest one of the isolated lattices is in a position higher than a bottommost surface of the amorphous region.

US Pat. No. 10,796,995

SEMICONDUCTOR DEVICES INCLUDING A FIRST COBALT ALLOY IN A FIRST BARRIER LAYER AND A SECOND COBALT ALLOY IN A SECOND BARRIER LAYER

TOHOKU UNIVERSITY, Senda...

1. A semiconductor device, comprising:a substrate;
a conductive wiring which comprises cobalt or copper and is electrically connected to the substrate;
an insulating material which electrically isolates the conductive wiring from neighboring wiring;
a first barrier layer which (i) comprises a first cobalt alloy which comprises cobalt and at least one of hafnium (Hf), tantalum (Ta) and titanium (Ti) and (ii) is disposed between the conductive wiring and the insulating material; and
a second barrier layer which includes a second cobalt alloy and is disposed between the conductive wiring and the substrate;
wherein the first barrier layer separates the conductive wiring from a gate electrode, and
wherein both the first barrier layer and the second barrier layer are in contact with the conductive wiring.

US Pat. No. 10,796,994

SEMICONDUCTOR DEVICE AND IO-CELL

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first wiring layer in which a plurality of first power supply lines supplied with first electric power and a plurality of second power supply lines supplied with second electric power are alternately arranged in a first direction;
a second wiring layer in which a third power supply line connected to adjacent first power supply lines among the plurality of first power supply lines through first vias is disposed, the third power supply line being supplied with the first electric power; and
an upper wiring layer having an upper layer power supply line connected to the first electric power, the upper layer power supply line being electrically connected through second vias to the third power supply line of the second wiring layer, wherein
all of the first, second and third power supply lines are formed so as to extend in a second direction perpendicular to the first direction;
the number of second vias that electrically connect the third power supply line and the upper layer power supply line is larger than the number of first vias that electrically connect the first power supply line and the third power supply line;
the plurality of first power supply lines do not have a concavo-convex shape along their sides, and
the third power supply line has a concavo-convex shape along at least one of its sides.

US Pat. No. 10,796,993

METHOD FOR FORMING THREE-DIMENSIONAL INTEGRATED WIRING STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF

Yangtze Memory Technologi...

1. A method for forming a 3D integrated wiring structure, comprising:forming an insulating layer on a front side of a first substrate;
forming a plurality of semiconductor structures over the insulating layer, wherein the plurality of semiconductor structures comprise a plurality of 3D NAND memory arrays, a plurality of conductive contacts and a first conductive layer;
forming a peripheral device structure on a second substrate;
joining the second substrate with the first substrate such that the peripheral device structure and the plurality of 3D NAND memory arrays are disposed face to face with each other;
exposing the insulating layer and a first end of the plurality of conductive contacts from a backside of the first substrate; and
forming a conductive wiring layer on the exposed insulating layer.

US Pat. No. 10,796,992

STACK OF LAYERS FOR PROTECTING AGAINST A PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS WITHIN AN INTEGRATED CIRCUIT

STMicroelectronics (Rouss...

1. A method for protecting an integrated circuit against an electrical conduction assisted by the presence of defects within a dielectric region, at least in part porous, separating two electrically conducting elements of an interconnection part of the integrated circuit, wherein the interconnection part comprises a plurality of metallization levels including a last metallization level which, of the plurality of metallization levels, is the metallization level located furthest from a semiconductor substrate, the method comprising:etching an encapsulation layer formed above the last metallization level of the interconnection part;
etching an electrically conducting layer situated above the etched encapsulation layer for the formation of contact pads;
forming, on the etched electrically conducting layer and on revealed part or parts of the etched encapsulation layer, a stack comprising a non-porous lower passivation layer having a first thickness, an electrically insulating layer having a second thickness and an upper passivation layer having a third thickness, wherein the third thickness is greater than the first thickness; and
locally etching through the stack so as to reveal an upper surface of the contact pads.

US Pat. No. 10,796,991

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a semiconductor substrate;
a cell planar pattern on the semiconductor substrate;
a peripheral circuit between the semiconductor substrate and the cell planar pattern;
a dummy structure on the semiconductor substrate;
cell gate conductive patterns on the cell planar pattern; and
a cell vertical structure disposed on the cell planar pattern and passing through the cell gate conductive patterns,
wherein a portion of the cell vertical structure directly contacts the cell planar pattern,
wherein the dummy structure is electrically isolated,
wherein the dummy structure includes at least four dummy patterns disposed at different levels from each other with respect to an upper surface of the semiconductor substrate,
wherein the at least four dummy patterns include:
a dummy gate pattern;
a first dummy pattern disposed at a higher level than the dummy gate pattern;
a second dummy pattern disposed at a higher level than the first dummy pattern; and
a third dummy pattern disposed at a higher level than the second dummy pattern, and
wherein the peripheral circuit includes:
a peripheral gate disposed at substantially the same level as the dummy gate pattern;
a first peripheral interconnection pattern disposed at substantially the same level as the first dummy pattern; and
a second peripheral interconnection pattern disposed at substantially the same level as the second dummy pattern.

US Pat. No. 10,796,990

SEMICONDUCTOR STRUCTURE, PACKAGE STRUCTURE, AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:at least one integrated circuit component, comprising:
a first semiconductor substrate and a second semiconductor substrate electrically coupled to the first semiconductor substrate, wherein the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface, at least one of the first semiconductor substrate or the second semiconductor substrate comprises at least one first embedded capacitor, and the second semiconductor substrate comprises first through silicon vias penetrating therethrough, wherein the first through silicon vias are free from the first semiconductor substrate.

US Pat. No. 10,796,989

3D INTERCONNECT MULTI-DIE INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES

Micron Technology, Inc., ...

1. A semiconductor package, comprising:a first die;
a second die disposed over the first die; and
a coupled inductor including:
a magnetic core having a single through-substrate via (TSV) extending at least substantially through the first die and including a portion projecting from the first die and extending into an opening in the second die,
a primary winding disposed in the first die around the TSV, and
a secondary winding disposed in the second die around the TSV.

US Pat. No. 10,796,988

LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

Intel Corporation, Santa...

1. An apparatus comprising:a medium including low density interconnect routing therein;
a first conductive adhesive and a second conductive adhesive;
a metal pad in contact with a top surface of the medium;
a semiconductor die interconnect element including a top surface and an opposing, bottom surface, the bottom surface of the semiconductor die interconnect element facing the top surface of the medium, the bottom surface of the semiconductor die interconnect element connected to the metal pad through a third adhesive, the interconnect element including high density routing therein, the semiconductor die interconnect element including a plurality of electrically conductive members, an electrically conductive member of the plurality of electrically conductive members electrically coupled to the first conductive adhesive and the second conductive adhesive; and
wherein the first conductive adhesive is electrically coupled to a first pad, the first pad on, or at least partially in, the top surface of the semiconductor die interconnect element, the first pad situated between the first conductive adhesive and a first end of the electrically conductive member, wherein a footprint of the third adhesive is the same as a footprint of the semiconductor die interconnect element.

US Pat. No. 10,796,987

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor packaging device, comprising:a first patterned insulation layer having a first surface, a second surface opposite the first surface, and comprising a first portion and an island portion having the first surface, the island portion being adjacent to the first portion, the first patterned insulation layer defining a tapered groove surrounding the island portion and disposed between the first portion and the island portion;
a patterned conductive layer disposed on the first surface of the island portion;
a connection structure penetrating the first portion of the first patterned insulation layer;
a semiconductor device electrically connected to the patterned conductive layer, the connection structure being disposed within a projection area of the semiconductor device on the first patterned insulation layer; and
an encapsulant encapsulating the semiconductor device, the first patterned insulation layer and the patterned conductive layer;
wherein the tapered groove is filled with an insulation material.

US Pat. No. 10,796,986

LEADFRAME LEADS HAVING FULLY PLATED END FACES

Infineon Technologies AG,...

1. A semiconductor device comprising:a leadframe comprising a first main face disposed entirely in a first plane and a second main face opposite to the first main face disposed entirely in a second plane, the leadframe comprising leads wherein each lead comprises a fully plated planar end face extending between an unplated first sidewall on a first side of the lead and an unplated second sidewall on a second side of the lead that is opposite to the unplated first sidewall, wherein the fully plated planar end face and the unplated first sidewall and the unplated second sidewall of each lead are perpendicular to the first and second main faces;
a semiconductor die attached to the leadframe; and
an encapsulation material encapsulating the semiconductor die and a portion of the leadframe and forming a plurality of side surfaces of the semiconductor device at an outline of the encapsulation material,
wherein each lead includes a bottom fully plated second main face interior to the outline and below the encapsulation material to improve the solderability of the fully plated second main face to a circuit board, wherein each lead extends from a side surface of the plurality of side surfaces and includes a plated first sidewall on the first side of the lead that is between the unplated first sidewall and the encapsulation material and a plated second sidewall on the second side of the lead that is between the unplated second sidewall and the encapsulation material, wherein each lead, on the first side of the lead, includes only the unplated first sidewall and the plated first sidewall, wherein each lead, on the second side of the lead, includes only the unplated second sidewall and the plated second sidewall, and
where the plated first sidewall is nonplanar with the unplated first sidewall, and where the plated second sidewall is nonplanar with the unplated second sidewall.

US Pat. No. 10,796,985

LEAD FRAME AND METHOD OF FABRICATING THE SAME

Danfoss Silicon Power Gmb...

1. A lead frame for placement on a substrate, the lead frame comprising, prior to placement on the substrate:a power sub lead frame including one or more power terminals; and
a control sub lead frame including one or more control terminals;
wherein at least one of the one or more control terminals is externally terminated with a press-fit contact member; and
wherein the power sub lead frame is formed of a first material;
wherein the control sub lead frame is formed of a second material;
wherein the first material is a different material than the second material; and
wherein the power sub lead frame and the control sub lead frame are secured together at a bimetallic interface.

US Pat. No. 10,796,984

LEADFRAME HAVING A CONDUCTIVE LAYER PROTRUDING THROUGH A LEAD RECESS

STMICROELECTRONICS, INC.,...

16. A system, comprising:a leadframe package including a leadframe supporting a semiconductor die, the semiconductor die and the leadframe being covered by an encapsulant, the leadframe including a lead and a die pad, the semiconductor die being on the die pad and electrically coupled to the lead by an electrical connector, the lead having a through opening, wherein a conductive layer is on a surface of the lead and extending through the through opening to form a protrusion that extends beyond an outer surface of the lead.

US Pat. No. 10,796,983

POSITIONAL RELATIONSHIP AMONG COMPONENTS OF SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a die pad including a first surface and a second surface opposite to the first surface;
a semiconductor chip including a main surface, a plurality of bonding electrodes formed on the main surface and a back surface opposite to the main surface, and mounted on the first surface of the die pad via a die bond material such that the back surface faces the first surface of the die pad, the semiconductor chip essentially comprising a first material having a first linear expansion coefficient;
a plurality of leads electrically connected with the plurality of bonding electrodes via a plurality of wires, respectively; and
a sealing body including an upper surface located on the same side as the main surface of the semiconductor chip, a lower surface opposite to the upper surface, a first side surface located between the upper surface and the lower surface, and a second side surface located between the upper surface and the lower surface and also opposite to the first side surface, and sealing the semiconductor chip and the plurality of wires, the sealing body essentially comprising a second material having a second linear expansion coefficient, the second linear expansion coefficient being higher than the first linear expansion coefficient,
wherein each of the plurality of leads has an inner part sealed with the sealing body, and an outer part exposed from the sealing body,
wherein the outer part has:
a first part connected to the inner part and extending in a horizontal direction, which is along the upper surface of the sealing body,
a second part connected to the first part via a first bending portion that bends the outer part in a thickness direction, which is from the upper surface toward the lower surface, of the sealing body, and
a third part connected to the second part via a second bending portion that bends the outer part in the horizontal direction,
wherein the plurality of leads has:
a first lead electrically connected with a first bonding electrode of the plurality of bonding electrodes via a first wire of the plurality of wires and protruding from the first side surface of the sealing body, and
a second lead electrically connected with a second bonding electrode of the plurality of bonding electrodes via a second wire of the plurality of wires and protruding from the second side surface of the sealing body,
wherein, in cross-section view, the semiconductor chip is located between the inner part of the first lead and the inner part of the second lead,
wherein, in cross-section view, a thickness of the semiconductor chip is greater than a thickness from the second surface of the die pad to the lower surface of the sealing body, which is greater than a thickness of each of the die pad and the die bond material,
wherein, in cross-section view, a stand-off amount of each of the plurality of leads, which is a distance, in the thickness direction of the sealing body, from the lower surface of the sealing body to the third part of the outer part, is greater than a high-stand value of a stand-off amount of QFP (Quad Flat Package) based on JEITA (Japan Electronics and Information Technology Industries Association) and less than a thickness from the upper surface of the sealing body to the lower surface of the sealing body, and
wherein, in cross-section view, the stand-off amount of each of the plurality of leads is greater than a thickness from an upper surface of the inner part of each of the plurality of leads, which is located on the same side as the main surface of the semiconductor chip, to the upper surface of the sealing body, or a thickness from a lower surface of the inner part of each of the plurality of leads, which is located on the same side as the second surface of the die pad, to the lower surface of the sealing body.

US Pat. No. 10,796,982

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a first die pad;
a first inner lead which does not have any outer lead and which is arranged inside a molded resin;
a second die pad; and
a second inner lead which does not have any outer lead and which is arranged inside the resin,
wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other,
a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and
an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin,
the semiconductor device further comprising:
a lead which includes an outer lead arranged outside the resin and an inner lead arranged inside the resin; and
a third inner lead which does not have any outer lead and which is arranged inside the resin,
wherein a part of the inner lead of the lead and a part of the third inner lead are adhered and electrically connected to each other,
the first semiconductor chip is electrically connected to the second semiconductor chip via the lead and the third inner lead, and
an end face of one end of the third inner lead is exposed to a side surface of the molded resin.

US Pat. No. 10,796,981

CHIP TO LEAD INTERCONNECT IN ENCAPSULANT OF MOLDED SEMICONDUCTOR PACKAGE

Infineon Technologies AG,...

1. A packaged semiconductor device, comprising:an electrically insulating first encapsulant body comprising an upper surface;
a first semiconductor die encapsulated within the first encapsulant body, the first semiconductor die comprising a main surface with a first conductive pad that faces the upper surface of the first encapsulant body;
a plurality of electrically conductive leads, each of the leads comprising interior ends that are encapsulated within the first encapsulant body and outer ends that are exposed from the first encapsulant body; and
a first direct electrical connection between the first conductive pad and the interior end of a first lead from the plurality of electrically conductive leads,
wherein the first direct electrical connection comprises a first conductive track that is formed in the upper surface of the first encapsulant body,
wherein the first encapsulant body comprises a laser activatable mold compound, and
wherein the first conductive track is formed in a first laser activated region of the laser activatable mold compound.

US Pat. No. 10,796,980

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor substrate having a first surface and a second surface, the second surface being positioned on an opposite side of the first surface;
a first wiring and a second wiring each formed on the first surface side of the semiconductor substrate;
a bypass wiring formed on a second surface side of the semiconductor substrate;
a first through via passing through the semiconductor substrate and electrically connected with the first wiring; and
a second through via passing through the semiconductor substrate, electrically connected with the second wiring, and arranged in a position different from the first through via,
wherein the bypass wiring is connected with the first through via and the second through via,
wherein the first wiring and the second wiring are included in a wiring structure formed on the first side of the semiconductor substrate, and
wherein a sheet resistance value of the bypass wiring is smaller than a sheet resistance value of wiring included in the wiring structure.

US Pat. No. 10,796,979

POWER MODULE

Mitsubishi Electric Corpo...

1. A power module comprising:a power chip;
a control chip controlling the power chip;
a power terminal connected to the power chip;
a control terminal connected to the control chip; and
a package covering the power chip, the control chip, the power terminal, and the control terminal with mold resin, the package having first and second main faces facing each other, wherein
first and second recesses are provided on the second main face, which is opposite to the first main face that is in direct contact with a fin, and are respectively provided on opposite side faces of the package, the opposite side faces facing each other and being side faces from which neither the power terminal nor the control terminal protrudes,
the first and second recesses are configured to receive and engage at least one lug of the fin, to attach the fin to the package, and
the first and second recesses are arranged at positions that are not directly opposite to each other on the second main face, such that there are no recesses arranged directly opposite to each other.

US Pat. No. 10,796,978

TIM STRAIN MITIGATION IN ELECTRONIC MODULES

INTERNATIONAL BUSINESS MA...

1. A heat spreading lid, comprising:a lid body including:
a bottom surface;
a recess formed into the bottom surface; and
a wing portion formed into the recess with a gap between a top surface of the wing portion and a surface of the lid body at a top of the recess,
wherein the wing portion flexibly moves independently from the lid body,
wherein a portion of the lid is arranged above the wing portion, on a side of the wing portion, and
wherein a bottom surface of the wing portion installed in the recess is coplanar with the bottom surface of the lid body.

US Pat. No. 10,796,977

METHOD AND APPARATUS TO CONTROL TEMPERATURE OF A SEMICONDUCTOR DIE IN A COMPUTER SYSTEM

Intel Corporation, Santa...

1. An apparatus comprising:a die to operate in an overclocked mode; and
circuitry to apply supplemental heat to the die while a die junction temperature is below an operating temperature range for the die junction temperature.

US Pat. No. 10,796,976

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, the method comprising:attaching a first semiconductor device to a first surface of a substrate;
forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate;
forming an underfill material in the first region; and
removing the sacrificial structure after forming the underfill material.

US Pat. No. 10,796,975

SEMICONDUCTOR PACKAGE WITH SUPPORTED STACKED DIE

INTEL CORPORATION, Santa...

1. A semiconductor package, comprising:a substrate having a top substrate surface;
a first integrated circuit provided on the top substrate surface, wherein the first integrated circuit is electrically connected to the substrate;
a first intermediate integrated circuit comprising a first top surface and a first bottom surface, the first bottom surface of the first intermediate integrated circuit on the first integrated circuit, wherein the first intermediate integrated circuit comprises a first bond pad on the first top surface;
a second intermediate integrated circuit comprising a second top surface and a second bottom surface, the second bottom surface on the first top surface such that a first portion of the first top surface is exposed, wherein the second intermediate integrated circuit comprises a second bond pad;
a second integrated circuit comprising a third top surface and a third bottom surface, the second integrated circuit on the second top surface, wherein a first portion of the third bottom surface overhangs the second intermediate integrated circuit; and
an underfill support at least partially between the first portion of the third bottom surface and the first portion of the first top surface, wherein within the underfill support, a wire connects the first bond pad with the second bond pad, wherein the electrical connection between the first integrated circuit and the substrate is external to the underfill support.

US Pat. No. 10,796,974

SCAN TESTABLE THROUGH SILICON VIAS

Texas Instruments Incorpo...

1. An integrated circuit comprising:(a) a die having a top surface and a bottom surface;
(b) a top contact point on the top surface and a bottom contact point on the bottom surface;
(c) a through silicon via in the die having a top end coupled to the top contact point and a bottom end coupled to the bottom contact point;
(d) a buffer having an input coupled to one of the top end and the bottom end of the through silicon via and having an output coupled to a contact point;
(e) a switch having a first terminal coupled to the buffer input, a second terminal coupled to the buffer output, a third terminal, and a control input; and
(f) a scan cell having a reference voltage input, a serial data input, a control input, a stimulus output coupled to the other one of the top end and the bottom end of the through silicon via, a response input coupled to the third terminal, and a serial data output.

US Pat. No. 10,796,973

TEST STRUCTURES CONNECTED WITH THE LOWEST METALLIZATION LEVELS IN AN INTERCONNECT STRUCTURE

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a device-under-testing including one or more first source/drain regions;
a first metallization level arranged over the device-under-testing, the first metallization level including one or more first interconnect lines;
a contact level including one or more first contacts arranged between the first metallization level and the device-under-testing, the one or more first contacts directly connecting the one or more first interconnect lines with the one or more first source/drain regions;
a second metallization level arranged over the first metallization level, the second metallization level including a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad; and
a via level including a plurality of vertical interconnects connecting the one or more first interconnect lines with the one or more second interconnect lines,
wherein each of the one or more first interconnect lines is connected with one of the one or more first source/drain regions by only one of the one or more first contacts.

US Pat. No. 10,796,972

DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display panel comprising:a base substrate including a display area through which an image is displayed and a non-display area which surrounds the display area, wherein the display area includes a pixel which includes a switching element and a pixel electrode, and the non-display area does not include the pixel;
a first data line which extends in a second direction which crosses a first direction, and is disposed on the base substrate in the display area;
a second data line which extends in parallel with the first data line and is disposed on the base substrate in the display area;
a first line which is electrically connected to the first data line and disposed in the non-display area;
a second line which is electrically connected to the second data line and disposed in the non-display area;
a first pad electrically connected to the first line and disposed in the non-display area; and
a second pad electrically connected to the second line and disposed in the non-display area,
wherein the first pad and the second pad are formed from different layers.

US Pat. No. 10,796,971

PRESSURE-ACTIVATED ELECTRICAL INTERCONNECTION WITH ADDITIVE REPAIR

X Display Company Technol...

1. A method of making a repaired electrical connection structure, comprising:providing a substrate comprising a first contact pad and a second contact pad electrically connected in parallel with the first contact pad;
providing one or more component source wafers comprising a first component and a second component functionally identical to the first component;
disposing a first adhesive layer over and in contact with a first portion of the substrate, wherein the first portion is adjacent to, on, or adjacent to and on the first contact pad;
transferring the first component onto the first adhesive layer so that (i) the first component is in alignment with the first contact pad and (ii) the first adhesive layer contacts a portion of the first component between the first component and the substrate;
curing the first adhesive layer;
testing the first component after curing the first adhesive layer to determine that the first component is a faulty component;
if a second portion of the substrate is covered with the cured first adhesive layer, removing the cured first adhesive layer from the second portion, wherein the second portion is adjacent to, on, or adjacent to and on the second contact pad;
disposing a second adhesive layer over and in contact with the second portion of the substrate, by performing an unpatterned blanket deposition over the substrate and the first component;
transferring the second component onto the second adhesive layer so that (i) the second component is in alignment with the second contact pad and (ii) the second adhesive layer contacts a portion of the second component between the second component and the substrate; and
curing the second adhesive layer after curing the first adhesive layer.

US Pat. No. 10,796,970

METHOD FOR FABRICATING ELECTRONIC PACKAGE

Siliconware Precision Ind...

1. A method for fabricating an electronic package, comprising:providing a first circuit structure having opposite first and second surfaces, wherein the first circuit structure has at least a first redistribution layer;
disposing a plurality of first electronic elements on the first surface of the first circuit structure;
disposing at least a first conductive element on the first surface of the first circuit structure;
forming a first encapsulant on the first surface of the first circuit structure to encapsulate the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant;
forming a first metal layer on the first encapsulant, wherein the first metal layer is a circuit layer and in direct contact with the first conductive element and the first encapsulant;
forming a second circuit structure on the second surface of the first circuit structure, wherein the second circuit structure is in direct contact with the second surface of the first circuit structure and has at least a second redistribution layer;
disposing a plurality of second electronic elements on the second circuit structure; and
forming a second encapsulant on the second circuit structure to encapsulate the second electronic elements.

US Pat. No. 10,796,969

SYSTEM AND METHOD FOR FABRICATING SEMICONDUCTOR WAFER FEATURES HAVING CONTROLLED DIMENSIONS

KLA-TENCOR CORPORATION, ...

1. A method, comprising:identifying a top surface of a semiconductor wafer, wherein the top surface of the semiconductor wafer is a hard mask deposited on a substrate of the semiconductor wafer;
vertically etching a first portion of the top surface of the semiconductor wafer to a select depth to form a step down from a second portion of the top surface of the semiconductor wafer, the step comprised of:
a horizontal face at a lower height than the second portion of the top surface of the semiconductor wafer, and
a vertical sidewall extending from the second portion of the top surface of the semiconductor wafer to the horizontal face;
performing chemical mechanical polishing (CMP) of the step;
after performing the CMP of the step, uniformly depositing a film of a select thickness across the horizontal face and the vertical sidewall of the step;
after uniformly depositing the film across the horizontal face and the vertical sidewall of the step, performing CMP on the second portion of the top surface of the semiconductor wafer to reduce a height of the step;
after performing the CMP on the second portion of the top surface of the semiconductor wafer to reduce a height of the step, vertically etching, to a select depth, the second portion of the top surface of the semiconductor wafer from the film by vertically etching through a first portion of the hard mask and a first portion of the substrate of the semiconductor wafer on which the first portion of the hard mask is deposited, to expose, as a feature of the semiconductor wafer, the film deposited across the vertical sidewall of the step,
wherein dimensions of the feature are controlled according to the select thickness by which the film is deposited and the select depth by which the second portion of the top surface of the semiconductor wafer is vertically etched.

US Pat. No. 10,796,968

DUAL METAL SILICIDE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a P-type semiconductor device above a substrate, the P-type semiconductor device comprising:
first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode, respectively; and
a first metal silicide layer directly on the first and second semiconductor source or drain regions, wherein the first metal silicide layer comprises nickel, platinum and silicon; and
an N-type semiconductor device above the substrate, the N-type semiconductor device comprising:
third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode, respectively; and
a second metal silicide layer directly on the third and fourth semiconductor source or drain regions, respectively, wherein the first metal silicide layer comprises at least one metal species not included in the second metal silicide layer, and wherein the second metal silicide layer comprises titanium and silicon.

US Pat. No. 10,796,967

VERTICAL FIELD EFFECT TRANSISTOR (FET) WITH CONTROLLABLE GATE LENGTH

International Business Ma...

1. A semiconductor device, comprising:a vertical transistor on a substrate, wherein the vertical transistor comprises:
a first set of fins and a second set of fins;
a bottom source/drain region disposed on the substrate and around a bottom portion of each of the fins in the first set of fins and the second set of fins;
a first spacer layer disposed on the bottom source/drain region and around of each of the fins in the first set of fins and the second set of fins;
a gate structure disposed on the first spacer layer and around each of the fins in the first set of fins and the second set of fins, wherein a gate length is the same or substantially the same on each side of each of the fins in the first set of fins and the second set of fins;
a second spacer layer disposed in a portion of the gate structure and on each of the fins in the first set of fins and the second set of fins, wherein the second spacer layer is configured to extend above each of the fins in the first set of fins and the second set of fins to define an opening therein and expose a top surface of each of the fins in the first set of fins and the second set of fins;
a top source/drain region disposed on the top surface of each of the fins in the first set of fins and the second set of fins and in the opening and configured to extend above the second spacer layer; and
a first dielectric layer disposed on the substrate and between the first set of fins and the second set of fins.

US Pat. No. 10,796,966

VERTICAL FET WITH VARIOUS GATE LENGTHS BY AN OXIDATION PROCESS

International Business Ma...

1. A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:patterning fins having a uniform height in a substrate, the fins comprising at least one first fin and at least one second fin;
selectively recessing the at least one second fin using a low-temperature directional oxidation process such that the at least one first fin has a height H1? and the at least one second fin has a height H2?, wherein H2?>H1?;
forming bottom source and drains at a base of the fins;
forming bottom spacers on the bottom source and drains;
forming gates above the bottom spacers alongside the fins, wherein the gates alongside the at least one first fin have a first gate length Lg1?, wherein the gates alongside the at least one second fin have a second gate length Lg2?, and wherein Lg2?>Lg1?;
forming top spacers above the gates at tops of the fins; and
forming top source and drains above the top spacers.

US Pat. No. 10,796,965

NANO SENSING CHIP INCLUDING SENSING MATERIALS OPERATING THROUGH DEVICE-LOCALIZED JOULE HEATING

NATIONAL CHIAO TUNG UNIVE...

1. A nano sensing chip, comprising:a plurality of nanodevices divided into a first group and a second group, each of the first group and the second group comprising one or more nanodevices of the plurality of nanodevices, each nanodevice of the plurality of nanodevices comprising a source, a drain, and a device channel with two ends electrically connecting the source and the drain, wherein the device channel comprises a lightly-doped region;
a first sensing material deposited on the one or more lightly-doped regions of one or more nanodevices in the first group; and
a second sensing material deposited on the one or more lightly-doped regions of one or more nanodevices in the second group,
wherein the second sensing material is different from the first sensing material, and the nanodevices in the first group and the second group are configured to function under Joule self-heating at different working temperatures to simultaneously sense different target gases by the first sensing material and the second sensing material, respectively, and
wherein the one or more nanodevices in the first group and the one or more nanodevices in the second group are independently applied with bias voltage to achieve the Joule self-heating at the lightly-doped regions.

US Pat. No. 10,796,964

TRANSISTOR STRUCTURE

UNITED MICROELECTRONICS C...

1. A transistor structure, comprising:a source region and a drain region disposed in a substrate and extend extending along a first direction; and
a polysilicon layer, disposed over the substrate and extending along a second direction perpendicular to the first direction, wherein the polysilicon layer comprises a first edge region, a second edge region, and a channel region between the first edge region and the second edge region, the first edge region, the channel region and the second edge region formed as a gate region between the source region and the drain region in a plane view,
wherein the polysilicon layer comprises a first opening pattern at least partially disposed in the first edge region and a second opening pattern at least partially disposed in the second edge region, the first opening pattern has a first portion located in the gate region, and the second opening pattern has a second portion located in the gate region,
wherein the first opening pattern comprises at least one opening, disposing over and between the source region and the drain region,
wherein the second opening pattern comprises at least one opening, disposing over and between the source region and the drain region,
wherein the first opening pattern and the second opening pattern are not distributed into the channel region,
wherein the first opening pattern is different from the second opening pattern in opening distribution,
wherein the at least one opening of the first opening pattern or the second opening pattern comprises a first opening and a second opening, the first opening disposed over and adjacent to the source region, the second opening disposed over and adjacent to the drain region,
wherein the at least one opening of a remaining opening pattern comprises a third opening disposed over and between the drain region and the source region.

US Pat. No. 10,796,963

BACKSIDE METAL PATTERNING DIE SINGULATION SYSTEMS AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. A method of singulating a plurality of die comprised in a substrate, the method comprising:forming a plurality of die on a first side of a substrate;
forming a backside metal layer on a second side of the substrate;
applying an organic layer over the backside metal layer;
forming a groove entirely through the organic layer and partially through a thickness of the backside metal layer, wherein the groove is located in a die street of the substrate;
etching through a remaining portion of the backside metal layer located in the die street;
removing the organic layer; and
singulating the plurality of die comprised in the substrate by removing substrate material in the die street.

US Pat. No. 10,796,962

SEMICONDUCTOR WAFER PROCESSING METHOD

DISCO CORPORATION, Tokyo...

1. A semiconductor wafer processing method comprising:a device forming step of forming a functional layer on a front side of a semiconductor wafer, the functional layer having a first area where a plurality of semiconductor devices are formed and a second area where a plurality of division lines for separating the plurality of semiconductor devices from each other are formed, each semiconductor device including a distribution layer and a metal electrode formed above the distribution layer;
a protective layer forming step of forming an protective layer on a front side of the functional layer to fully cover the front side of the functional layer with the protective layer, thereby forming a device wafer having the semiconductor wafer, the functional layer, and the protective layer;
a laser processed groove forming step of applying a laser beam having an absorption wavelength to the functional layer and the semiconductor wafer along each division line to partially remove the semiconductor wafer, the protective layer, and the functional layer, and thereby expose the front side of the semiconductor wafer, thereby forming a laser processed groove along each division line on a front side of the device wafer;
a mask layer forming step of forming a mask layer on a front side of the protective layer except in an area above each metal electrode;
a first etching step of performing plasma etching using a first gas through the mask layer to the protective layer, thereby exposing each metal electrode;
a second etching step of performing plasma etching using a second gas to each laser processed groove through the mask layer used in the first etching step, thereby partially removing the functional layer and the semiconductor wafer exposed from the mask layer to thereby expand each laser processed groove both along its width and along its depth; and
a dividing step of dividing the semiconductor wafer along each laser processed groove expanded in the second etching step, thereby obtaining a plurality of device chips respectively including the plurality of semiconductor devices.

US Pat. No. 10,796,961

METHOD OF SEPARATING ELECTRONIC DEVICES HAVING A BACK LAYER AND APPARATUS

SEMICONDUCTOR COMPONENTS ...

1. A method of singulating a wafer comprising:providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces, wherein the wafer has first and second opposing major surfaces, and wherein a layer of material is formed atop the second major surface, and wherein the layer of material comprises one or more of a conductive material, a wafer-back coating, or a die-attach film adapted to remain at least in part atop surfaces of the plurality of die upon completion of the method of singulating the wafer;
placing the wafer onto a carrier substrate so that the layer of material is interposed between the carrier substrate and the wafer;
etching portions of the wafer through the spaces to form singulation lines, wherein etching comprises leaving portions of the layer of material underlying the singulation lines; and
separating the layer of material underlying the singulation lines by:
applying pressure to the wafer; and
applying high frequency vibrations to fatigue the layer of material during at least a portion of the step of applying pressure to the wafer.

US Pat. No. 10,796,960

MANUFACTURING PROCESS OF ELEMENT CHIP

PANASONIC INTELLECTUAL PR...

1. A manufacturing process of an element chip, comprising:a substrate preparing step for preparing a substrate having first and second sides opposed to each other, and including a plurality of dicing regions and element regions defined by the dicing regions, the first side being covered by a protective film;
a first laser-grooving step for forming a plurality of grooves by irradiating a laser beam to the first side of the substrate along the dicing regions, each of the grooves being shallower than a thickness of the substrate;
a plasma-dicing step for plasma-etching the substrate along the grooves in depth through a plasma exposure of the substrate, thereby to dice the substrate into a plurality of the element chips each having the element region; and
a removing step for removing the protective film from the plurality of the element chips after the plasma-dicing step,
wherein the second side of the substrate and an annular frame surrounding the substrate are held on a holding sheet in the substrate preparing step,
wherein the laser beam is irradiated only in a region inside an outer edge of the substrate in the first laser-grooving step, and
wherein the substrate is plasma-etched along the grooves and a peripheral region of the substrate in the plasma-dicing step in a state without the protective film in the peripheral region.

US Pat. No. 10,796,959

LASER PROCESSING METHOD AND LASER PROCESSING APPARATUS

HAMAMATSU PHOTONICS K.K.,...

1. A method of manufacturing a semiconductor device, the method comprising:irradiating a substrate with a pulsed laser light at a converging point within the substrate, so that the converging point of the pulsed laser light is positioned within the substrate to form a modified spot within the substrate at the converging point, the pulsed laser light having a wavelength at which an internal transmittance of the laser light within the substrate is at least 80%; and
performing the irradiating step at multiple locations along each of a plurality of intersecting cutting lines along which the substrate is to be cut to form a plurality of modified spots within the substrate at converging points of the pulsed laser light, respectively, without melting a pulsed laser light incident surface of the substrate, the modified spots each including a modified region, the modified spots being formed intermittently along each of the plurality of intersecting cutting lines, the modified spots being formed in the substrate only by the laser irradiation converging within the substrate; and
cutting the substrate into parts by dry processing along the plurality of intersecting cutting lines by growing cracks from the modified spots which grow towards a front and a back surface of the substrate, without causing modifications to be formed in the front and back surfaces of the substrate other than the cracks cutting the substrate into parts, in order to provide at least one manufactured semiconductor device.

US Pat. No. 10,796,958

3D INTEGRATION METHOD USING SOI SUBSTRATES AND STRUCTURES PRODUCED THEREBY

International Business Ma...

1. An article of manufacture comprising at least two bonded device layers, of which at least one first device layer comprises a first set of silicon on insulator (SOI) front-end-of-line (FEOL) circuits disposed on a buried oxide (BOX) layer having a BOX surface and a first set of middle of the line (MOL) interconnects on the opposite side of the SOI circuits from the BOX surface and a first set of back end of the line (BEOL) interconnects disposed at a side of said first set of MOL interconnects that is opposite said FEOL circuits, said at least one first device layer further being flipped and bonded atop a second device layer that comprises a second set of front-end-of-line (FEOL) circuits, a second set of middle of line (MOL) interconnects adjacent said second set of FEOL circuits and a second set of back end of the line (BEOL) interconnects at a side of said second set of MOL interconnects that is opposite said second set of FEOL circuits, with said first and second sets of BEOL interconnects proximate each other and said first and second sets of FEOL circuits distal from each other, and said at least one first device layer and said second device layer being interconnected together by means of metal filled vias located within said first set of MOL interconnects and said BOX layer of said at least one first device layer and connecting on one end to bonding pads associated with said second device layer and adjacent to said second set of BEOL interconnects and on another end to metal features provided on a third set of BEOL interconnects located atop said BOX surface, wherein said third set of BEOL interconnects located atop said BOX surface is not directly in contact with said SOI circuits of said at least one first device layer, thus forming an enhanced 3D device stack.

US Pat. No. 10,796,957

BURIED CONTACT TO PROVIDE REDUCED VFET FEATURE-TO-FEATURE TOLERANCE REQUIREMENTS

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming a first semiconductor fin opposite a surface of a first active region of a substrate, the first active region comprising a first dopant type;
forming a second semiconductor fin opposite a surface of a second active region of the substrate, the second active region comprising a second dopant type complementary to the first dopant type;
forming a first gate over the first active region of the substrate, the first gate on a sidewall of the first semiconductor fin;
forming a second gate over the second active region of the substrate, the second gate on a sidewall of the second semiconductor fin;
forming a self-aligned buried contact over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin;
forming a dielectric layer over portions of the self-aligned buried contact, the dielectric layer comprising a first dielectric material on a surface of the first gate;
forming a spacer between the first gate and the self-aligned buried contact, the spacer comprising a spacer material having an etch selectivity relative to the first dielectric material; and
forming a contact in the dielectric layer, a bottommost surface of the contact positioned in direct contact with a topmost surface of the self-aligned buried contact and a topmost surface of the first gate.

US Pat. No. 10,796,956

CONTACT FABRICATION TO MITIGATE UNDERCUT

TEXAS INSTRUMENTS INCORPO...

1. A method of fabricating a contact structure, the method comprising:forming a barrier layer at least partially on a conductive feature of a wafer or die;
forming a seed layer at least partially on the barrier layer, the seed layer including tin;
forming a copper structure on the seed layer above the conductive feature of the wafer or die;
heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure;
removing an exposed portion of the seed layer to expose a portion of the barrier layer; and
removing the exposed portion of the barrier layer.

US Pat. No. 10,796,955

FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH INTERCONNECT STRUCTURE

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device structure, comprising:forming a first metal layer over a substrate;
forming an etch stop layer over the first metal layer;
forming a dielectric layer over the etch stop layer, the dielectric layer having a single continuous composition;
forming a trench opening and a via opening in the dielectric layer, wherein the trench opening has an extending portion, a bottom surface of the extending portion extends toward the etch stop layer as the bottom surface extends from the via opening toward a sidewall of the trench;
forming an adhesion layer on sidewalls and bottom surfaces of the trench opening and the via opening;
removing a portion of the etch stop layer directly above the first metal layer and removing a portion of the adhesion layer to expose an exposed portion of the dielectric layer adjacent the extending portion; and
filling a second metal layer in the via opening and the trench opening, wherein the second metal layer is electrically connected to the first metal layer.

US Pat. No. 10,796,954

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a first substrate;
a metallic pad disposed over the first substrate;
a dielectric structure disposed over the first substrate and a portion of the metallic pad;
a bonding structure disposed over and electrically connected to the metallic pad;
a barrier ring surrounding the bonding structure; and
a through-hole penetrating the first substrate and the dielectric structure,wherein the bonding structure includes a bottom and a sidewall, the bottom of the bonding structure is in contact with the metallic pad, a first portion of the sidewall of the bonding structure is in contact with the dielectric structure, and a second portion of the sidewall of the bonding structure is in contact with the barrier ring.

US Pat. No. 10,796,953

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A manufacturing method for a semiconductor integrated circuit device, comprising:(a) forming a first interconnect made of a first metal over a main surface of a semiconductor substrate;
(b) forming a first barrier insulating film on the first interconnect so as to contact with a top surface of the first interconnect,
(c) forming a first interlayer insulating film over the first barrier insulating film;
(d) forming a first via hole in the first interlayer insulating film and the first barrier insulating film so as to contact with the first interconnect;
(e) forming a first interconnect trench in the first interlayer insulating film so as to contact with the first via hole;
(f) forming a second interconnect by filling a second metal in the first interconnect trench and the first via hole;
(g) forming a third interconnect made of a third metal over the second interconnect and the first interlayer insulating film;
(h) forming a second barrier insulating film on the third interconnect so as to contact with a top surface of the third interconnect;
(i) forming a second interlayer insulating film over the second barrier insulating film, and forming an etching stopper film in the second interlayer insulating film;
(j) forming a second via hole in the second interlayer insulating film, the etching stopper film and the second barrier insulating film so as to contact with the third interconnect;
(k) forming a second interconnect trench in the second interlayer insulating film and the etching stopper film so as to contact with the second via hole; and
(l) forming a fourth interconnect by filling a fourth metal in the second interconnect trench and the second via hole,
wherein the etching stopper film is arranged nearer to a bottom surface of the second interconnect trench than to a top surface of the third interconnect and a top surface of the second interconnect trench,
wherein the second interlayer insulating film is thicker than the first interlayer insulating film,
wherein a depth of the second interconnect trench is greater than a depth of the first interconnect trench,
wherein a depth of the second via hole is greater than a depth of the first via hole,
wherein a dielectric constant of the first interlayer insulating film is lower than a dielectric constant of the second interlayer insulating film,
wherein the first barrier insulating film includes silicon, carbon and nitrogen,
wherein the second barrier insulating film includes silicon, carbon and nitrogen, and
wherein the second interlayer insulating film includes silicon, fluorine and oxygen.

US Pat. No. 10,796,952

MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A method of fabricating a memory device, comprising:forming a stacked structure on the substrate;
forming a pillar in the stacked structure, wherein the pillar has a recess thereon;
forming a stop material layer on the stacked structure and the pillar and in the recess;
removing the stop material layer on sidewalls of the recess to form a first stop layer on the stacked structure, and a second stop layer on a bottom surface of the recess;
forming a contact plug in the recess;
forming a dielectric layer on the first stop layer and the contact plug; and
forming a contact in the dielectric layer, wherein the contact is electrically connected to the contact plug.

US Pat. No. 10,796,951

ETCH-STOP LAYER TOPOGRAPHY FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate, individual ones of the plurality of conductive interconnect lines having an upper surface below an upper surface of the ILD layer, wherein individual ones of the plurality of conductive interconnect lines comprise a barrier layer along sidewalls and a bottom of a conductive fill material, and wherein both the barrier layer and the conductive fill material have an uppermost surface below the upper surface of the ILD layer;
an etch-stop layer on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines; and
a conductive via on and electrically coupled to an individual one of the plurality of conductive interconnect lines, the conductive via in an opening of the etch-stop layer, the opening over the individual one of the plurality of conductive interconnect lines but not overlapping the upper surface of the ILD layer.

US Pat. No. 10,796,950

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of fabricating a semiconductor device, comprising:forming a bit line and a bit-line capping pattern sequentially stacked on a semiconductor substrate;
forming a sacrificial spacer and a first spacer on sidewalls of the bit line and the bit-line capping pattern;
forming a contact plug to be in contact with the first spacer;
removing upper portions of the sacrificial spacer and the first spacer;
after removing the upper portions of the sacrificial spacer and the first spacer, forming a conductive layer to cover the sacrificial spacer, the first spacer and the bit-line capping pattern;
patterning the conductive layer to form landing pads;
exposing the sacrificial spacer between the landing pads;
removing the sacrificial spacer to form an air gap exposing a sidewall of the first spacer; and
forming an insulating pattern on the air gap and the first spacer.

US Pat. No. 10,796,949

AIRGAP VIAS IN ELECTRICAL INTERCONNECTS

International Business Ma...

1. An interconnect structure comprising: one or more layer pairs, each layer pair having an upper layer and a lower layer, the upper layer comprising an upper dielectric, and the lower layer comprising a lower dielectric; a pair of upper interconnects, being a first and second upper interconnect, the first and second upper interconnect being separated by an upper separation distance, the upper separation distance having an upper centerline; a pair of lower interconnects, being a first and second lower interconnects, the first and second lower interconnect being separated by a lower separation distance, the lower separation distance having a lower centerline, the lower center line being parallel to the upper centerline and being within an offset distance from being coincident with the upper centerline; a pair of vias, being a first and second via, the first and second via separated by a via separation distance, the via separation distance having a via centerline, the via centerline being colinear with the upper centerline, the first via passing through the upper dielectric and mechanically and electrically connecting the first upper interconnect to the first lower interconnect to form a first electrical connection, the second via passing through the upper dielectric and the second via mechanically and electrically connecting the second upper interconnect to the second lower interconnect to form a second electrical connection; a lower barrier layer chemically and electrically isolating the first and second lower interconnects from the first dielectric layer, where the upper separation distance and the via lower separation distance are in fluid communication forming a gap filled with air electrically separating the first and second electrical connection by an airgap separation distance, the gap having a gap bottom.

US Pat. No. 10,796,948

PATTERN FORMING METHOD AND IMPRINT APPARATUS

TOSHIBA MEMORY CORPORATIO...

1. A pattern forming method, comprising:dispensing an uncured first resist material on to a substrate in a first resist pattern;
curing the uncured first resist material with a first light to form a cured first resist pattern on the substrate;
exposing the cured first resist pattern to a second light;
dispensing an uncured second resist material on to the cured first resist pattern; and
contacting the uncured second resist material with a patterned imprint template and curing the uncured second resist material.

US Pat. No. 10,796,947

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, the method comprising:providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface of the gate electrode is leveled with the first surface;
forming an alignment layer over the first surface of the wafer and the top surface of the gate electrode;
forming a photoresist on the alignment layer to cover a portion of the top surface of the gate electrode;
removing portions of the alignment layer uncovered by the photoresist to form an alignment structure on the top surface of the gate electrode;
forming a dielectric surrounding the alignment structure on the first surface;
removing the alignment structure to expose at least a portion of the gate electrode; and
forming a gate conductor over and in contact with the gate electrode.

US Pat. No. 10,796,946

METHOD OF MANUFACTURE OF A SEMICONDUCTOR ON INSULATOR STRUCTURE

SunEdison Semiconductor L...

1. A method of preparing a multilayer structure, the method comprising:(a) forming a front handle silicon dioxide layer on a front handle surface of a single crystal silicon handle wafer and a back handle silicon dioxide layer on a back handle surface of a single crystal silicon handle wafer, wherein the single crystal silicon handle wafer comprises two major, generally parallel surfaces, one of which is the front handle surface of the single crystal silicon handle wafer and the other of which is the back handle surface of the single crystal silicon handle wafer, a circumferential edge joining the front handle surface and the back handle surface of the single crystal silicon handle wafer, a central plane between the front handle surface and the back handle surface of the single crystal silicon handle wafer, and a bulk region between the front and back handle surfaces of the single crystal silicon handle wafer;
(b) forming a front handle silicon nitride layer on the front handle silicon dioxide layer;
(c) bonding the front handle silicon nitride layer to a donor silicon dioxide layer on a front donor surface of a single crystal silicon donor wafer to thereby form a bonded structure, wherein the single crystal silicon donor wafer comprises two major, generally parallel surfaces, one of which is the front donor surface of the single crystal silicon donor wafer and the other of which is the back donor surface of the single crystal silicon donor wafer, a circumferential edge joining the front donor surface and the back donor surface of the single crystal silicon donor wafer, a central plane between the front donor surface and the back donor surface of the single crystal silicon donor wafer, and a bulk region between the front and back donor surfaces of the single crystal silicon donor wafer, and further wherein the single crystal silicon donor wafer comprises a damage layer formed by ion implantation; and
(d) removing the back handle silicon dioxide layer.

US Pat. No. 10,796,945

HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY HE—N2 CO-IMPLANTATION

GlobalWafers Co., Ltd., ...

1. A multilayer structure comprising:a single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, a front surface region having a depth, D, as measured from the front surface and toward the central plane, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface region comprises nitrogen-reacted nanovoids;
a dielectric layer in contact with the front surface of the single crystal semiconductor handle substrate; and
a single crystal semiconductor device layer in contact with the dielectric layer.

US Pat. No. 10,796,944

METHOD AND DEVICE FOR SURFACE TREATMENT OF SUBSTRATES

EV Group E. Thallner GmbH...

1. A method for surface treatment of an at least primarily crystalline substrate surface of a substrate, the method comprising:amorphizing the substrate surface without deposition of a material to form an amorphous layer for bonding at the substrate surface of the substrate and produce a thermodynamically metastable state at the substrate surface, the amorphous layer having a thickness d>0 nm.

US Pat. No. 10,796,943

MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE

UNITED MICROELECTRONICS C...

1. A manufacturing method of a semiconductor structure, comprising:forming a patterned mask layer on a semiconductor substrate, wherein the patterned mask layer comprises a first mask layer and a second mask layer disposed on the first mask layer;
forming an isolation trench in the semiconductor substrate by removing a part of the semiconductor substrate;
forming a liner layer conformally on an inner sidewall of the isolation trench;
performing an implantation process to the liner layer, wherein the implantation process comprises a noble gas implantation process configured to implant noble gas atoms in the liner layer;
forming an isolation structure at least partially in the isolation trench after the implantation process; and
performing an etching process to remove the patterned mask layer after the isolation structure is formed and expose a top surface of the semiconductor substrate, wherein a part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process, and a part of the semiconductor substrate is exposed by the inner sidewall of the isolation trench after the etching process, wherein the etching process comprises:
a first etching step configured to remove the second mask layer; and
a second etching step configured to remove the first mask layer and performed after the first etching step, wherein a topmost surface of the liner layer is higher than a topmost surface of the first mask layer in a thickness direction of the semiconductor substrate after the first etching step and before the second etching step.

US Pat. No. 10,796,942

SEMICONDUCTOR STRUCTURE WITH PARTIALLY EMBEDDED INSULATION REGION

STMICROELECTRONICS S.r.l....

1. A structure, comprising:a substrate including a first N type semiconductor region;
a first insulation region at least partially embedded within the first N type semiconductor region and with a first surface of the first insulation region exposed from the first N type semiconductor region;
a second N type semiconductor region over the first insulation region, the first insulation region adjacent to a first surface of the second N type semiconductor region and at least partially surrounding a first sidewall of the second N type semiconductor region; and
a second insulation region over the second N type semiconductor region, the second N type semiconductor region adjacent to a first surface of the second insulation region and at least partially surrounding a sidewall of the second insulation region.

US Pat. No. 10,796,941

MOUNTING MEMBER

NITTO DENKO CORPORATION, ...

1. A mounting member, comprising an aggregate of carbon nanotubes for forming a mounting surface, and a substrate,wherein a standard deviation of diameters of the carbon nanotubes is 3 nm or less,
a ratio of a plan view area of recessed portions occurring in a carbon nanotube aggregate-side surface of the mounting member to a total area of the carbon nanotube aggregate-side surface is 5% or less, and
the carbon nanotube aggregate-side surface is a surface of the aggregate of carbon nanotubes opposite to the substrate.

US Pat. No. 10,796,940

ENHANCED AUTOMATIC WAFER CENTERING SYSTEM AND TECHNIQUES FOR SAME

Lam Research Corporation,...

27. A non-transitory, computer-readable medium storing computer-executable instructions thereon for controlling one or more processors to:a) cause a first set of one or more wafers of nominal diameter D1 to be retrieved using a wafer handling robot configured to support the first set of one or more wafers when the first set of one or more wafers is placed thereupon, the first set of one or more wafers defining a silhouette edge in a horizontal plane when viewed along a vertical axis;
b) obtain information regarding a first reference point of the wafer handling robot using a first edge-detection system;
c) obtain information indicative of first horizontal coordinates of at least five points along the silhouette edge of the first set of one or more wafers relative to the first reference point using the first edge-detection system;
d) determine, for the first set of one or more wafers, the smallest circle that, when viewed along a vertical axis, circumscribes the first horizontal coordinates of the at least five points determined in (c);
e) determine, for the first set of one or more wafers, a first center deviation by determining information indicative of the length and direction of a first reference line segment extending from the center of the smallest circle for the first set of one or more wafers to the first reference point;
f) determine a first slip amount for the first set of one or more wafers that is based on the difference between the diameter of the smallest circle and D1; and
g) determine whether the first slip amount for the first set of one or more wafers exceeds a first threshold amount.

US Pat. No. 10,796,939

TEMPORARY ADHESIVE FILM ROLL FOR SUBSTRATE PROCESSING, METHOD FOR MANUFACTURING THIN WAFER

SHIN-ETSU CHEMICAL CO., L...

1. A temporary adhesive film roll for substrate processing, comprising:a roll axis and a composite film-shaped temporary-adhesive material for temporarily bonding a substrate to be processed to a support, the composite film-shaped temporary-adhesive material being rolled up around the roll axis;
wherein the composite film-shaped temporary-adhesive material includes a first temporary adhesive layer (A) composed of a thermoplastic resin, a second temporary adhesive layer (B) composed of a thermosetting resin, and a third temporary adhesive layer (C) composed of a thermosetting resin which is different from that of the second temporary adhesive layer.

US Pat. No. 10,796,938

MICRO-TRANSFER PRINTING WITH SELECTIVE COMPONENT REMOVAL

X Display Company Technol...

1. A method of micro-transfer printing, comprising:providing a component source wafer having micro-transfer printable components disposed on or in the component source wafer, each micro-transfer printable component comprising a device and an ablation layer disposed on the device;
providing a stamp comprising a body and spaced-apart posts protruding away from the body, the posts having a spatial distribution on the body matched to a spatial distribution of ones of the micro-transfer printable components on or in the component source wafer;
providing a light source;
providing a destination substrate;
contacting each of the posts to a micro-transfer printable component of the micro-transfer printable components to adhere the micro-transfer printable component to the post, thereby forming adhered micro-transfer printable components;
removing the stamp with the adhered micro-transfer printable components from the component source wafer;
disposing the stamp with the adhered micro-transfer printable components in alignment with the destination substrate;
irradiating one or more of the posts and the ablation layer of the micro-transfer printable component adhered to each of the one or more of the posts with light from the light source to detach the micro-transfer printable component from the post, thereby forming one or more detached micro-transfer printable components; and
removing the stamp from the destination substrate, leaving the one or more detached micro-transfer printable components in contact with the destination substrate,
wherein the body and the posts are substantially transparent to the light.

US Pat. No. 10,796,937

EQUIPMENT FRONT END MODULE

CLEAN FACTOMATION, INC., ...

1. An equipment front end module (EFEM) comprising:a transfer chamber;
a load port module on which a wafer receiving container, provided by an overhead hoist transport (OHT), is seated;
a wafer transfer robot positioned in the transfer chamber and configured to transfer a wafer in the wafer receiving container seated on the load port module toward a process equipment side; and
a buffer module configured to store the wafer receiving container before or after the seating of the wafer receiving container on the load port module and inject an inert gas into the wafer receiving container to purge the wafer, wherein the buffer module injects the inert gas into the wafer receiving container with or without the inert gas being injected into the wafer receiving container by the load port module,
wherein the buffer module comprises:
a plurality of supply nozzles connected to an injection port of the wafer receiving container to supply the inert gas into the wafer receiving container;
a storage housing having a space to accommodate the wafer receiving container, wherein the load port module is disposed outside the space; and
a buffer port mounted with the plurality of supply nozzles, formed to support the wafer receiving container, and configured to be moved so as to move the wafer receiving container between an inside and an outside of the space along a first path different than a second path along which the overhead hoist transport unloads the wafer receiving container on the load port, wherein the buffer port is placed in the second path such that the buffer port can receive the wafer receiving container from the overhead hoist transport when the buffer port has been moved to the outside of the space.

US Pat. No. 10,796,936

DIE TRAY WITH CHANNELS

Invensas Bonding Technolo...

1. An apparatus, comprising:a substantially planar tray;
an array of support posts disposed at a surface of the tray, each post configured to elevate an element off the surface of the tray, the element having a substantially planar shape with a plurality of vertices;
a quantity of retaining posts equal to the number of element vertices disposed on a surface of the tray, each retaining post positioned at a first side of each vertex of the element and arranged to laterally restrain the element loaded onto the support posts;
a quantity of mount posts equal to the number of element vertices disposed on a surface of the tray, each mount post positioned at a second side of each vertex of the element, paired with each retaining post and arranged to longitudinally restrain the element loaded onto the support posts, the retaining posts and the mount posts trapping each vertex of the element; and
one or more channels under the said element arranged to direct fluids away from the element.

US Pat. No. 10,796,935

ELECTRONIC DEVICE MANUFACTURING SYSTEMS, METHODS, AND APPARATUS FOR HEATING SUBSTRATES AND REDUCING CONTAMINATION IN LOADLOCKS

Applied Materials, Inc., ...

1. A loadlock of an electronic device manufacturing system comprising:a housing having a first interior chamber configured to receive a substrate therein from a transfer chamber of the electronic device manufacturing system;
a plurality of gas lines coupled to the first interior chamber;
a plurality of gas line heaters configured to heat a gas in one or more of the plurality of gas lines to deliver heated gas to the first interior chamber;
a plurality of gas line temperature sensors coupled at different locations to the plurality of gas lines; and
a gas line heater controller configured to receive one or more sensed gas temperatures from one or more of the plurality of gas line temperature sensors and to adjust a setting of one or more of the plurality of gas line heaters in response to receiving the one or more sensed gas temperatures.

US Pat. No. 10,796,934

SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ELECTRODE FIXING PART

Kokusai Electric Corporat...

1. A substrate processing apparatus comprising:a reaction tube defining a processing chamber wherein a substrate is processed;
an electrode provided at an outer circumferential surface of the reaction tube and configured to generate plasma in the process chamber;
an electrode fixing part configured to fix the electrode thereto;
a heater provided at an outer circumferential surface of the electrode fixing part and configured to heat an inside of the reaction tube; and
a spacer configured to provide a predetermined gap between the electrode and a surface of the electrode fixing part,
wherein the electrode fixing part comprises a fixing portion comprising a protrusion shaft portion engaged with the electrode and a protrusion head portion configured to suppress the electrode from being released from the fixing portion, and
wherein the spacer comprises an elastic body to generate a pressing force applied on the electrode toward the protrusion head portion.

US Pat. No. 10,796,933

DISPLAY DEVICE MANUFACTURING APPARATUS AND METHOD

Samsung Display Co., Ltd....

1. A manufacturing method of a display device, the manufacturing method comprising:forming a pattern layer on a substrate;
forming a photoresist pattern on the pattern layer to expose a portion of the pattern layer;
placing the substrate on a support in a chamber; and
removing the portion of the pattern layer exposed by the photoresist pattern and discharging by-products from the chamber through a first baffle and a second baffle during the removing the portion of the pattern layer,
wherein the first baffle has a first through hole through which the by-products is discharged,
wherein the second baffle overlaps with the first baffle in a plan view, covers the first through hole in a plan view and alter a path of the by-products discharged from the chamber,
wherein the second baffle completely covers the first through hole in a plan view, and
wherein the second baffle is in a plate shape having no through hole.

US Pat. No. 10,796,932

PLASMA PROCESSING APPARATUS

Panasonic Intellectual Pr...

1. A plasma processing apparatus for plasma-processing a wafer attached on an adhesive sheet held by a holder frame, the plasma processing apparatus comprising:a vacuum chamber;
an electrode generating plasma in the vacuum chamber;
a stage disposed in the vacuum chamber, on which the adhesive sheet held by a holder frame is placed; and
a cover member having an opening, an upper surface and a lower surface, and configured to move such that the cover member is disposed above the adhesive sheet and the holder frame when the adhesive sheet held by the holder frame is placed on the stage, the upper surface being exposed to the plasma, wherein:
a diameter of the opening is greater than a diameter of the wafer so that when the adhesive sheet held by the holder frame is placed on the stage, the wafer attached to the adhesive sheet is disposed in the opening of the cover member, a part of the cover member is located above the adhesive sheet and the holder frame, and the cover member is not contact with the wafer and the adhesive sheet,
the lower surface of the cover member includes a first annular lower surface, a second annular lower surface and a third lower surface,
the first annular lower surface is disposed closer to the opening than the second annular lower surface, and the second annular lower surface is disposed closer to the opening than the third annular lower surface,
at least a part of the third lower surface is disposed above the stage,
the first annular lower surface and the third annular lower surface is disposed lower than the second annular lower surface,
the stage includes an annular groove, of which bottom surface is located below an upper surface of a center part of the stage and an outer part of the stage, and which faces the second annular lower surface, and
the third annular lower surface does not face the annular groove, and at least part of the first annular lower surface faces the center part of the stage and does not face the annular groove.

US Pat. No. 10,796,931

MANUFACTURING METHOD OF PACKAGE STRUCTURE

Powertech Technology Inc....

1. A manufacturing method of a package structure, comprising:providing a carrier;
disposing a semiconductor die and at least one sacrificial structure on the carrier, wherein a plurality of bonding pads are disposed on the sacrificial;
electrically connecting the semiconductor die to the bonding pads on the sacrificial structure through a plurality of conductive wires;
forming an encapsulant on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires;
debonding the carrier;
removing at least a portion of the sacrificial structure through a thinning process; and
forming a redistribution layer on the semiconductor die and the encapsulant, the redistribution layer is electrically connected to the semiconductor die through the conductive wires.

US Pat. No. 10,796,930

SEMICONDUCTOR DEVICE WITH DECREASED WARPAGE AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. A method of fabricating a semiconductor device package, the method comprising:providing a substrate having a first surface and a second surface opposite to each other;
forming a dielectric material and a redistribution structure on the first surface of the substrate, the redistribution structure extending within the dielectric material;
mounting a semiconductor chip on the redistribution structure and electrically connecting the semiconductor chip to the redistribution structure; and
forming an encapsulation layer on the dielectric material to encapsulate the semiconductor chip,
wherein each of the substrate and the encapsulation layer includes molding compound, and
wherein a thickness of the substrate in a first direction perpendicular to the first surface of the substrate and a thickness of the encapsulation layer in the first direction are substantially same.

US Pat. No. 10,796,929

METHOD FOR PRODUCING A METAL-CERAMIC SUBSTRATE WITH AT LEAST ONE VIA

Infineon Technologies AG,...

1. A method for producing a metal-ceramic substrate with at least one electrically conductive via, the method comprising:attaching a first metal layer in a planar manner to a first surface side of a ceramic layer and attaching a second metal layer in a planar manner to a second surface side of the ceramic layer opposite the first surface side;
introducing a metal-containing powdery substance into a hole in the ceramic layer delimiting the at least one electrically conductive via prior to the attachment of both the first and the second metal layers, or subsequent to the attachment of one of the first and the second metal layers and prior to the attachment of the other one of the first and the second metal layers, to form an assembly; and
subjecting the assembly to a high-temperature step above 500° C. in which the metal-containing powdery substance wets the ceramic layer at least partially with a wetting angle of less than 90°.

US Pat. No. 10,796,928

WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A wiring structure, comprising:a first unit disposed at a first elevation and having a first circuit layer and a first dielectric layer surrounding the first circuit layer;
a second unit disposed at the first elevation and having a second circuit layer and a second dielectric layer surrounding the second circuit layer;
a first insulation wall disposed between the first unit and the second unit;
a first redistribution layer disposed on the first unit and the second unit, and electrically connected between the first unit and the second unit; and
a third unit disposed on the first redistribution layer and having a third circuit layer and a third dielectric layer surrounding the third circuit layer.

US Pat. No. 10,796,927

INTEGRATED CIRCUIT PACKAGE PAD AND METHODS OF FORMING

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:forming a first layer over a carrier substrate;
forming a second layer over the first layer;
forming an opening through the second layer;
forming a conductive structure on the second layer, the conductive structure extending through the opening;
placing an integrated circuit die over the second layer, the integrated circuit die having contact pads facing away from the carrier substrate;
forming a molding compound over the second layer, the molding compound extending along sidewalls of the integrated circuit die and the conductive structure, wherein a smallest width of the conductive structure in the molding compound is greater than a largest width of the conductive structure in the second layer, wherein the conductive structure protrudes from the second layer;
removing the carrier substrate, exposing the first layer; and
removing the first layer, exposing the second layer and the conductive structure.

US Pat. No. 10,796,926

METHOD OF MANUFACTURING GLASS INTERPOSER

DISCO CORPORATION, Tokyo...

1. A method of manufacturing a glass interposer by dividing a glass substrate along a plurality of division lines set in a grid pattern into glass interposers of a reduced size, the glass substrate including a plurality of through electrodes penetrating a front surface and a back surface of the glass substrate, stacked bodies having wiring layers and resin layers alternately formed on the front surface and the back surface of the glass substrate, and the division lines, the method comprising:a first groove forming step of processing the stacked bodies, formed on the front surface and the back surface of the glass substrate, along the division lines to form first grooves having a first width and such a depth as not to reach the glass substrate, while leaving a residual resin portion at bottoms of the first grooves;
a second groove forming step of applying a laser beam of such a wavelength as to be absorbed in the resin layer to the bottoms of the first grooves formed in the first groove forming step to perform ablation processing of the residual resin portion, thereby exposing the front surface and the back surface of the glass substrate and forming second grooves in the residual resin portion having a second width narrower than the first width;
a modified layer forming step of applying a laser beam of such a wavelength as to be transmitted through the glass substrate through the second groove on the front surface or the back surface of the glass substrate along the division lines, with a focal point set in inside of the glass substrate, to form modified layers in the inside of the glass substrate; and
a dividing step of exerting an external force on the glass substrate to divide the glass substrate, with the modified layers as division starting points,
wherein the glass interposers obtained by dividing the glass substrate to the reduced size are provided with the stacked bodies on the front surface and the back surface, the stacked bodies each formed at an outer peripheral portion thereof with the residual resin portion formed in the first groove forming step.

US Pat. No. 10,796,925

CERAMIC CIRCUIT SUBSTRATE AND METHOD FOR MANUFACTURING SAME

Denka Company Limited, T...

1. A ceramic circuit substrate for a power module comprising a metal circuit, a ceramic substrate, a weir part comprising a first insulating resin and an insulating part comprising a second insulating resin,wherein the metal circuit and the ceramic substrate are bonded;
the weir part is formed on a main surface of the metal circuit and is formed in a band shape along an edge of the metal circuit;
the insulating part is provided to at least one selected from the group consisting of an outer peripheral part of the metal circuit and between the metal circuits; and
the weir part and the insulating part are provided independently so as not to contact each other.

US Pat. No. 10,796,924

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF BY FORMING THIN UNIFORM SILICIDE ON EPITAXIAL SOURCE/DRAIN STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device including a fin field effect transistor (FinFET), the method comprising:forming a fin structure over a substrate, the fin structure extending in a first direction in plan view;
forming an isolation insulating layer over the substrate so that a lower portion of the fin structure is embedded in the isolation insulating layer and an upper portion of the fin structure is exposed from the isolation insulating layer;
forming a gate structure over a part of the fin structure, the gate structure including a gate electrode and a gate dielectric layer, the gate structure extending in a second direction crossing the first direction in plan view;
recessing an upper portion of the fin structure not covered by the gate structure below an upper surface of the isolation insulating layer;
forming an epitaxial structure over the recessed fin structure;
forming a silicide layer over at least a part of the epitaxial structure; and
forming a contact plug, wherein:
the epitaxial structure includes an n-type semiconductor layer formed over the recessed fin structure and a Si1-xGex layer doped with phosphorous formed over the n-type semiconductor layer,
the forming the silicide layer includes:
forming a Ti layer over the Si1-xGex layer; and
performing a thermal process to form an alloy of Ti, Si and Ge,
the Ti layer is fully consumed to form the alloy layer by the thermal operation or a remaining Ti layer is removed after the thermal operation so that the contact plug is in direct contact with the silicide layer,
the n-type semiconductor layer includes a first SiP layer formed on the recessed fin structure and a second SiP layer formed directly on the first SiP layer,
a concentration of phosphorous in the first SiP layer is smaller than a concentration of phosphorous in the second SiP layer,
a depth of the second SiP layer from an interface between the epitaxial structure and the Si1-xGex layer is in a range from 30 nm to 60 nm,
the concentration of phosphorous in the first SiP layer is in a range from 2×1020 atoms cm?3 to 7×1021 atoms cm?3, and
the concentration of phosphorous in the second SiP layer is in a range from 3×1020 atoms cm?3 to 4×1021 atoms cm?3.

US Pat. No. 10,796,923

POLYSILICON ETCHING METHOD

WUHAN CHINA STAR OPTOELEC...

1. A polysilicon etching method, comprising the following steps:S1: ionizing oxygen and/or ozone, and fluorine-based gas to obtain a first etching gas having a plasma state, and etching a polysilicon coated by a photoresist with the first etching gas for a preset time;
S2: ionizing chlorine gas to obtain a second etching gas in a plasma state, and etching the polysilicon through the second etching gas until the polysilicon etching is completed;
wherein the step S1 comprises:
placing the polysilicon coated by the photoresist in a plasma reactor and introducing oxygen and/or ozone, and the fluorine-based gas into the plasma reactor, and turning on an excitation power supply of the plasma reactor to ionize the oxygen and/or ozone, and the fluorine-based gas to obtain the first etching gas; and
turning on a bias power supply of the plasma reactor and controlling the first etching gas to etch the polysilicon for the preset time;
wherein an output power ratio of the excitation power supply and the bias power supply ranges from ½ to ?.

US Pat. No. 10,796,922

SYSTEMS AND METHODS FOR INTERNAL SURFACE CONDITIONING ASSESSMENT IN PLASMA PROCESSING EQUIPMENT

Applied Materials, Inc., ...

1. A plasma processing system, comprising:a remote plasma system for ionizing first source gases; and
two processing units, each of the two processing units configured to receive at least the ionized first source gases from the remote processing system, and second source gases;
each of the processing units comprising:
a plasma generation chamber that is bounded by:
a first planar electrode that is configured for transfer of the ionized first source gases and the second plasma source gases into the plasma generation chamber through first perforations therein,
a second planar electrode that is configured with perforations configured for transfer of plasma products from the plasma generation chamber toward a process chamber, and
a ring shaped insulator that is disposed about and in contact with a periphery of the first planar electrode, and about and in contact with a periphery of the second planar electrode;
and a power supply that provides electrical power across the first and second planar electrodes to ignite a plasma with the ionized first source gases and the second plasma source gases in the plasma generation chamber, to produce the plasma products;
wherein: one of the first planar electrode, the second planar electrode and the ring shaped insulator includes a port that provides an optical signal from the plasma, the port being disposed and oriented such that the optical signal is not influenced by interactions of the plasma products after they transfer through the second planar electrode toward the process chamber.

US Pat. No. 10,796,921

CMP FLUID AND METHOD FOR POLISHING PALLADIUM

HITACHI CHEMICAL COMPANY,...

1. A polishing method for a substrate, the method comprising:polishing a palladium layer on a substrate with a polishing cloth while supplying a CMP polishing liquid between the substrate and the polishing cloth, wherein:
the CMP polishing liquid comprises an organic solvent, 1,2,4-triazole in an amount ranging from 0.01 to 20 mass %, phosphoric acid in an amount ranging from 0.001 to 20 mass %, hydrogen peroxide in an amount ranging from 0.05 to 20 mass %, and an abrasive, all amounts being based on a total mass of the CMP polishing liquid, and the organic solvent comprises at least one kind selected from among an alcohol, a carbonic acid ester, a carboxylic acid ester and a glycol derivative.

US Pat. No. 10,796,920

METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES

Samsung Electronics Co., ...

1. A method of manufacturing an integrated circuit device, the method comprising:sequentially forming a device layer, a wiring insulating layer, and a hard mask layer on a semiconductor substrate, the device layer comprising a plurality of semiconductor devices;
sequentially removing a first region and a second region of the hard mask layer by using a first mask layer having a first opening extending in a first horizontal direction and a second mask layer having a second opening extending in the first horizontal direction as an etch mask, respectively, wherein a portion of the second opening overlaps in a vertical direction a stitch region that comprises a first portion of the wiring insulating layer and overlaps a portion of the first opening in the vertical direction;
forming a first wiring recess passing through the wiring insulating layer and a second wiring recess having a depth that is less than a depth of the first wiring recess by removing the first portion of the wiring insulating layer by using as an etch mask a third region of the hard mask layer that remains after removing the first region and the second region of the hard mask layer; and
forming a wiring structure that is in the first wiring recess and the second wiring recess and is electrically connected to the plurality of semiconductor devices.

US Pat. No. 10,796,919

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A method of fabricating a semiconductor device, comprising:forming a fin-type pattern protruding on a substrate;
forming a gate electrode intersecting the fin-type pattern;
forming a first recess adjacent the gate electrode, within the fin-type pattern, and by using dry etching;
forming a second recess by treating a surface of the first recess with a surface treatment process including a deposit process and an etch process, wherein the deposit process includes forming a semiconductor liner film along the surface of the first recess, and the semiconductor liner film is an undoped semiconductor film, and wherein the etch process includes etching at least a portion of the undoped semiconductor film; and
forming an epitaxial pattern in the second recess,
wherein a temperature for performing the deposit process is less than or equal to a temperature for performing the etch process,
wherein the surface of the first recess comprises high-index crystal planes and low-index crystal planes, and wherein the etch process includes etching the at least a portion of the undoped semiconductor film and etching the high-index crystal planes faster than the low-index crystal planes,
wherein the surface treatment process is performed for a plurality of times,
wherein the surface treatment process includes a first surface treatment process and a second surface treatment process,
the first surface treatment process includes a first deposit process and a first etch process,
the second surface treatment process includes a second deposit process and a second etch process,
the first deposit process and the second deposit process have substantially identical process conditions, and
the first etch process and the second etch process have substantially identical process conditions, and
wherein a flow of an etching gas is discontinuous in a stabilizing interval between the first deposit process and the first etch process and between the second deposit process and the second etch process.

US Pat. No. 10,796,918

INTEGRATED CIRCUITS WITH BACKSIDE METALIZATION AND PRODUCTION METHOD THEREOF

STMicroelectronics S.r.l....

1. A device, comprising:a substrate having a first surface and a second surface;
an integrated circuit structure extending into the substrate from the first surface;
a plurality of first contact terminals coupled to the integrated circuit structure and extending from the first surface of the substrate;
a second contact terminal consisting of a single material on the second surface of the substrate, the second contact terminal having a width that is greater than a width of the integrated circuit structure; and
a coupling layer in direct contact with the second surface of the substrate and in direct contact with the second contact terminal, the coupling layer including a combination of the single material of the second contact terminal and a material of the substrate and having a homogenous aggregate of first and second silicide-like compounds each having a stoichiometric ratio different from each other and consisting essentially of NiSi as a majority quantity and Ni2Si as a minority quantity and being insoluble to each other and coexisting in the solid phase, wherein a contact resistivity of the coupling layer and the second contact terminal is above 1×10?5.4 and less than 1×10?4.3 ohms*cm2 and the substrate has a resistivity between 3.5 and 18.0 mohms*cm.

US Pat. No. 10,796,917

METHOD FOR MANUFACTURING GATE INSULATOR FOR HEMT

FUJITSU LIMITED, Kawasak...

1. A method for producing a semiconductor device, the method comprising:forming, on a substrate, a first semiconductor layer of a nitride semiconductor;
forming, on the first semiconductor layer, a second semiconductor layer of a nitride semiconductor;
forming a source electrode and a drain electrode on the second semiconductor layer;
forming a metal oxide film by oxidizing, with water vapor, a surface of the second semiconductor layer between the source electrode and the drain electrode such that the metal oxide film includes AlOx and InOx and AIOx/InOx in the metal oxide film is greater than or equal to 4.6; and
forming a gate electrode on the metal oxide film.

US Pat. No. 10,796,916

MICROWAVE PLASMA DEVICE

TOKYO ELECTRON LIMITED, ...

1. A plasma processing system, comprising:a plasma chamber comprising a plasma processing region that can support a semiconductor substrate;
a power transmission element comprising:
(i) an interior cavity to propagate electromagnetic waves,
(ii) an annular continuous slit along one side of the power transmission element, the slit forming an opening between the interior cavity and an exterior surface of the power transmission element,
(iii) a first power feed opening of the interior cavity to receive the electromagnetic waves,
(iv) a first power distribution element disposed within the interior cavity and opposite the power feed opening and the annular continuous slit, the first power distribution element comprising a geometry that splits the electromagnetic waves along opposing directions within the interior cavity;
a microwave power source that can provide the electromagnetic waves to the power transmission element;
a dielectric component arranged to cover at least a portion of the annular continuous slit and to transmit at least a portion of energy from the electromagnetic waves through the opening;
a splitter disposed between the microwave power source and the first power feed opening, the splitter to divide the electromagnetic waves between the first power feed opening and a second power feed opening of the interior cavity;
one or more field rotation components disposed between the splitter and power transmission element, the one or more field rotation components configured to rotate a field of the electromagnetic waves relative to the annular continuous slit, wherein the one or more field rotation components comprise a rotation waveguide configured to variably rotate the field of the electromagnetic waves during plasma processing of the semiconductor substrate, by changing a rotation angle of the rotation waveguide and adjust a magnitude of power emitted into the plasma processing region; and
the plasma processing region disposed adjacent to the power transmission element.

US Pat. No. 10,796,915

METHOD FOR FORMING EPITAXIAL LAYER AT LOW TEMPERATURE

EUGENE TECHNOLOGY CO., LT...

1. A method for forming an epitaxial layer, the method comprising:transferring a substrate into an epitaxial chamber; and
performing an epitaxial process on the substrate to form an epitaxial layer on the substrate,
wherein the epitaxial process comprises:
heating the substrate at a temperature of about 700° C. or less and injecting a silicon gas into the epitaxial chamber in a state in which the inside of the epitaxial chamber is adjusted to a pressure of about 300 Torr or less to form a first epitaxial layer;
stopping the injection of the silicon gas and injecting a purge gas into the epitaxial chamber to perform first purge inside the epitaxial chamber;
heating the substrate at a temperature of about 700° C. or less and injecting the silicon gas into the epitaxial chamber in the state in which the inside of the epitaxial chamber is adjusted to a pressure of about 300 Torr or less to form a second epitaxial layer; and
stopping the injection of the silicon gas and injecting the purge gas into the epitaxial chamber to perform second purge inside the epitaxial chamber, wherein,
in the forming of the first and second epitaxial layers, the substrate is heated at a temperature of about 480, and
in the epitaxial process, the epitaxial layer having a thickness that is greater than about 60 ? and less than about 74 ? is formed on the substrate.

US Pat. No. 10,796,914

METHOD FOR PROCESSING A WAFER, AND LAYER STACK

Infineon Technologies AG,...

1. A method comprising:forming a vertical layer stack comprising a vertical outer wall exposed to an exterior of the vertical layer stack, comprising a support layer and a useful layer and a sacrificial region between them, said sacrificial region having, vis-à-vis a processing fluid, at least one of a lower mechanical or chemical resistance than the support layer and than the useful layer, wherein a main processing surface of the support layer and a main processing surface of the useful layer each extend in lateral plane perpendicular to the vertical outer wall;
forming a depression in the support layer that extends vertically from a main surface of the support layer through the support layer so as to expose the sacrificial region; and
forming, after the forming of the depression, at least one channel in the exposed sacrificial region by means of the processing fluid, wherein the channel connects the depression to the exterior of the layer stack, wherein the channel is a thru-hole laterally adjacent to the depression and wherein the channel extends laterally from the outer wall to the depression,
wherein the useful layer and the support layer are at least partially in direct contact with each other, and
wherein the depression is formed in an inner section of the support layer so that the remaining support layer forms a support ring extending along a lateral edge of the vertical layer stack,
the method further comprising forming the useful layer by epitaxially growing the useful layer onto the support layer and the sacrificial region.

US Pat. No. 10,796,913

METHOD FOR HYBRID WAFER-TO-WAFER BONDING

CHENGDU IMAGE DESIGN TECH...

1. A method for hybrid wafer-to-wafer bonding, wherein comprises the following steps in sequence:S01: providing two silicon wafers with Cu pattern structures, wherein each of the silicon wafers has a planarized surface with copper and dielectric by a conventional Cu BEOL process;
S02: removing part of the copper on the planarized surface of the Cu pattern structure on each of the silicon wafers by adopting an etching process to form a certain amount of copper recesses;
S03: separately depositing a layer of bonding metal on the surface of the copper on each of the silicon wafers by adopting a selective deposition process before aligning and bonding the two silicon wafers;
S04: performing surface activation on the bonding metal and the dielectric on each of the silicon wafers by adopting a surface activation process;
S05: aligning and pressing the two silicon wafers together to obtain the dielectric bonding;
S06, obtaining the metal bonding through the annealing process.

US Pat. No. 10,796,912

ELIMINATING YIELD IMPACT OF STOCHASTICS IN LITHOGRAPHY

LAM RESEARCH CORPORATION,...

1. A method of processing semiconductor substrates, the method comprising:providing a substrate having a first feature and a second feature formed by lithography in a first hard mask material,
wherein the first feature is partially formed by the lithography and comprises a bottom, and the first hard mask material comprises a field region between feature openings of the first feature and the second feature;
depositing a second hard mask material over the first hard mask material for a duration sufficient to preferentially form second hard mask material on the field region to a thickness greater than thickness of the second hard mask material in the first feature; and
directionally etching the second hard mask material to remove material at the bottom of the first feature by exposing the second hard mask material to an etching species to form a modified surface and igniting a plasma in an inert gas environment without the etching species while applying a bias to remove the modified surface, the material at the bottom of the first feature is the first hard mask material or the second hard mask material.

US Pat. No. 10,796,911

HARDMASK STRESS, GRAIN, AND STRUCTURE ENGINEERING FOR ADVANCED MEMORY APPLICATIONS

International Business Ma...

1. A semiconductor device, comprising:one or more memory device layers disposed over a bottom contact structure;
a plurality of hardmask layers disposed on the one or more memory device layers in a stacked configuration; and
a top contact structure disposed on the plurality of hardmask layers;
wherein alternating hardmask layers of the stacked configuration are different from each other in at least one respect;
wherein the plurality of hardmask layers and the one or more memory device layers are in a pillar shape;
wherein the plurality of hardmask layers are electrically conductive; and
wherein the alternating hardmask layers of the stacked configuration comprise a buffer hardmask layer stacked on a large grain hardmask layer.

US Pat. No. 10,796,910

METHOD FOR PERFORMING A PHOTOLITHOGRAPHY PROCESS

Taiwan Semicondutor Manuf...

1. A method for performing a photolithography process, comprising:forming a layer over a substrate;
exposing a portion of the layer to form an exposed region;
performing a baking process on the layer, so that voids are formed in the exposed region of the layer, wherein the layer comprises a polymer and an acid labile group (ALG), and the ALG cleaves from the polymer when performing the baking process on the layer; and
filling the void with a post treatment coating material, wherein the post treatment coating material is over the exposed region of the layer.

US Pat. No. 10,796,909

SURFACE-ALIGNED LITHOGRAPHIC PATTERNING APPROACHES FOR BACK END OF LINE (BEOL) INTERCONNECT FABRICATION

Intel Corporation, Santa...

10. An integrated circuit structure, comprising:a substrate;
a plurality of alternating first and second conductive lines along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above the substrate;
a conductive via on and electrically coupled to one of the conductive lines of the plurality of alternating first and second conductive lines, the conductive via having a flat top surface and outwardly tapered sidewalls, and the conductive via centered over the one of the conductive lines; and
a second ILD layer above the plurality of alternating first and second conductive lines and laterally adjacent to the conductive via, the second ILD layer having an uppermost surface substantially co-planar with the flat top surface of the conductive via.

US Pat. No. 10,796,908

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device including a transistor, the method comprising the steps of:forming an oxide semiconductor layer over an insulating layer;
preforming a first heat treatment on the oxide semiconductor layer under an inert atmosphere at a first temperature equal to or higher than 400° C.;
forming an oxide insulating layer over and in contact with a first part of the oxide semiconductor layer after the first heat treatment; and
performing a second heat treatment heating the oxide insulating layer at a second temperature equal to or higher than 150° C. and lower than 350° C.,
wherein the first part of the oxide semiconductor layer is included in a channel formation region of the transistor.

US Pat. No. 10,796,907

METAL-ORGANIC PULSED LASER DEPOSITION FOR STOICHIOMETRIC COMPLEX OXIDE THIN FILMS

Wisconsin Alumni Research...

1. A method of forming a complex oxide film, the method comprising:providing a deposition substrate and at least one metal oxide target comprising a first cation metal and oxygen in a deposition chamber;
introducing a metal-organic precursor comprising a second cation metal and oxygen into the deposition chamber; and
laser ablating the metal oxide target using a pulsed laser in the presence of the metal-organic precursor to generate a flux of the metal oxide, wherein the metal oxide and the metal and oxygen from the metal-organic precursor are sequentially deposited onto the deposition substrate to form a layered complex oxide film.

US Pat. No. 10,796,906

SILICON CARBIDE SEMICONDUCTOR SUBSTRATE, METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide semiconductor substrate, comprising:a silicon carbide substrate of a first conductivity type and having a front surface and a back surface opposite to the front surface;
a silicon carbide epitaxial layer of the first conductivity type, provided at the front surface of the silicon carbide substrate and having a low impurity concentration that is at most one third of an impurity concentration of the silicon carbide substrate, the low impurity concentration being in a range from 1×1017/cm3 to 1×1018/cm3, the silicon carbide epitaxial layer having a film thickness in a range from 1 ?m to 5 ?m, the silicon carbide epitaxial layer having a first side and a second side opposite to the first side and facing the silicon carbide substrate;
a silicon carbide buffer layer of the first conductivity type, provided at a surface of the first side of the silicon carbide epitaxial layer, the silicon carbide buffer layer having an impurity concentration that is at least three times the low impurity concentration of the silicon carbide epitaxial layer, the silicon carbide buffer layer having a first side and a second side opposite to the first side and facing the silicon carbide substrate; and
a silicon carbide drift layer of the first conductivity type, provided at a surface of the first side of the silicon carbide buffer layer, the silicon carbide drift layer having an impurity concentration that is at most one third of the impurity concentration of the silicon carbide buffer layer.

US Pat. No. 10,796,905

MANUFACTURE OF GROUP IIIA-NITRIDE LAYERS ON SEMICONDUCTOR ON INSULATOR STRUCTURES

GlobalWafers Co., Ltd., ...

1. A multilayer structure comprising:a thermally conductive carrier substrate selected from the group consisting of diamond and diamond coated silicon;
an interfacial bonding layer comprising aluminum oxide having a thickness between about 1 nanometer and 5 nanometers; and
a Group IIIA-nitride layer, the Group IIIA-nitride layer having a thickness between about 500 nanometers and about 2000 micrometers and comprising threading dislocations at a threading dislocation density between about 103/cm2 and 105/cm2, and further comprising components of a lateral HEMT power device, a laser diode, or a vertical gallium nitride-on-gallium nitride high voltage power device.

US Pat. No. 10,796,904

CONDUCTIVE C-PLANE GAN SUBSTRATE

MITSUBISHI CHEMICAL CORPO...

1. A conductive C-plane GaN substrate having a resistivity of 2×10?2 ?·cm or less or an n-type carrier concentration of 1×1018 cm?3 or more at room temperature, whereinat least one first line segment which is a virtual line segment with a length of 40 mm can be drawn at least on one main surface of the substrate, the first line segment satisfying the following condition (A1):
(A1) when an XRC of (004) reflection is measured at 1 mm intervals on the first line segment with a plane of incidence of X-rays parallel to the first line segment in each ? scan, a maximum value of XRC-FWHMs across all measurement points is less than 30 arcsec.

US Pat. No. 10,796,903

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A manufacturing method of a semiconductor device, comprising:forming a first insulating film over a substrate;
forming an oxide semiconductor film over the first insulating film;
forming a second insulating film over the oxide semiconductor film;
forming a gate electrode over the second insulating film;
forming a third insulating film over the oxide semiconductor film and the gate electrode; and
forming a source electrode and a drain electrode over the third insulating film and electrically connected to the oxide semiconductor film,
wherein:
the step of forming the oxide semiconductor film comprises:
forming a first oxide semiconductor film;
forming a second oxide semiconductor film over the first oxide semiconductor film; and
forming a third oxide semiconductor film over the second oxide semiconductor film,
the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film are formed using the same sputtering target,
the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film are successively formed with a sputtering apparatus in vacuum, and
the second oxide semiconductor film is formed under a lower oxygen partial pressure than one or both of the first oxide semiconductor film and the third oxide semiconductor film.

US Pat. No. 10,796,902

FILM DEPOSITION METHOD

Tokyo Electron Limited, ...

1. A method performed by a film deposition apparatus that includes a vacuum chamber, a rotary table disposed in the vacuum chamber, and multiple gas supply parts, whereinthe vacuum chamber includes an adsorption region, a reaction region, a modification region, and a hydroxyl formation region that are arranged in a rotational direction of the rotary table, the hydroxyl formation region being disposed apart from the modification region, and
the gas supply parts are disposed in the hydroxyl formation region and arranged along a radial direction of the rotary table at predetermined intervals,
the method comprising:
in the adsorption region, supplying a first reaction gas to a surface of a substrate and causing the first reaction gas to be adsorbed onto the surface of the substrate, the first reaction gas being adsorbable to hydroxyl groups;
in the reaction region, supplying a second reaction gas to the substrate and causing the second reaction gas to react with the first reaction gas adsorbed onto the surface of the substrate to form a reaction product on the substrate;
in the modification region, supplying an activated third reaction gas to the substrate to modify a surface of the reaction product;
selecting at least one gas supply part of the gas supply parts as a first gas supply part that supplies a fourth reaction gas including a hydrogen-containing gas; and
in the hydroxyl formation region,
supplying the fourth reaction gas from the selected first gas supply part selectively to a partial area of the modified surface of the reaction product, the partial area corresponding to a position of the selected first gas supply part in the radial direction of the rotary table, and
supplying only an inert gas from second gas supply parts of the gas supply parts other than the selected first gas supply part to control a concentration distribution of the hydrogen-containing gas in the radial direction of the rotary table to compensate for thickness deviations of a deposited film in the radial direction and to form hydroxyl groups selectively on the partial area.

US Pat. No. 10,796,901

SHELLING OF HALIDE PEROVSKITE NANOPARTICLES FOR THE PREVENTION OF ANION EXCHANGE

Nanoco Technologies Ltd.,...

1. A photoluminescent core/shell semiconductor nanoparticle comprising:a core comprising a halide perovskite semiconductor of the form ABX3; and
a shell substantially surrounding the core and comprising BaTiO3, SrTiO3, BiFeO3, LaNiO3, CaTiO3, PbTiO3 or LaYbO3, wherein
the shell is substantially free of halide perovskites,
A is selected from the group consisting of Li+, Na+, K+, Rb+ and Cs+,
M is a divalent metal cation selected from the group consisting of Mg2+, Mn2+, Pb2+, Sn2+ and Zn2+, and
X is selected from the group consisting of F?, Cl?, Br? and I?.

US Pat. No. 10,796,900

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Kokusai Electric Corporat...

1. A method of manufacturing a semiconductor device comprising:(a) generating an oxygen active species and a hydrogen active species by exciting a process gas containing an oxygen-containing gas and a hydrogen-containing gas; and
(b) forming an oxide layer by supplying the oxygen active species and the hydrogen active species to a substrate with a concave structure formed thereon to subject a film formed on an inner surface of the concave structure to oxidation from a surface of the film,
wherein the oxide layer is formed in (b) such that a thickness of the oxide layer on the inner surface of the concave structure is greater than that of the oxide layer at an upper end portion of the concave structure by setting a ratio of a flow rate of the hydrogen active species to a total flow rate of the oxygen active species and the hydrogen active species supplied to the substrate to a predetermined ratio greater than a first ratio at which a rate of forming the oxide layer is maximized at the upper end portion of the concave structure.

US Pat. No. 10,796,899

SILICON DOPING FOR LASER SPLASH BLOCKAGE

Micron Technology, Inc., ...

1. A method of dicing a silicon substrate, the method comprising:applying a mask to a front side of the silicon substrate, wherein the mask includes one or more openings exposing one or more regions to be doped;
introducing dopant atoms at the one or more regions;
diffusing the dopant atoms into the one or more regions using a rapid thermal procession until the one or more regions have a dopant concentration of at least 1015 cm?3;
forming an active layer of circuitry at the front side of the substrate;
stealth dicing the substrate from a back surface thereof using laser irradiation to cleave one or more portions of a silicon lattice of the substrate, the one or more portions being vertically aligned with the one or more regions; and
back-grinding the back surface of the substrate to mechanically separate adjacent semiconductor dice from the substrate on opposing sides of the one or cleaved more portions of the silicon lattice of the substrate,
wherein the dopant concentration of the one or more regions is configured to absorb a laser splash from the stealth dicing or to reflect the laser splash away from the active layer of circuitry.

US Pat. No. 10,796,898

TREATMENT SYSTEM AND METHOD

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:etching a dielectric layer to expose a first surface of the dielectric layer; and
treating the first surface using a first treatment precursor and a recovery precursor, wherein treating the first surface comprises:
removing nitrogen atoms from the first surface of the dielectric layer using the first treatment precursor; and
replacing the removed nitrogen atoms with carbon atoms using the recovery precursor.

US Pat. No. 10,796,897

SUPERCRITICAL FLUID PRODUCING APPARATUS AND SUBSTRATE PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A supercritical fluid producing apparatus comprising:a gas supply line that supplies a gaseous processing fluid from a gas supply tank;
a cooler connected to the gas supply line and configured to cool the gaseous processing fluid from the gas supply line so as to produce a liquid processing fluid;
a pump connected to the cooler and configured to send out the liquid processing fluid from the cooler by increasing a pressure of the liquid processing fluid;
a buffer tank connected to the pump and configured to absorb a pressure fluctuation or pulsation of the processing fluid from the pump, the buffer tank including an accommodation space therein;
a first heater connected downstream from the buffer tank and configured to heat the processing fluid from the buffer tank; and
a supercritical fluid supply line connected to the first heater and configured to send out a processing fluid in a supercritical state from the first heater to a processing chamber,
wherein an inlet port into which the processing fluid from the pump flows is formed at a vertically upper portion of the buffer tank, and an outlet port through which the processing fluid flows out is formed at a vertically lower portion of the buffer tank which is different from the inlet port, such that when a pressure fluctuation or pulsation of the processing fluid from the pump occurs, an interface between the liquid processing fluid in a vertically upper portion of the accommodation space and the processing fluid in the supercritical state in the vertically lower portion of the accommodation space moves up and down, and
the buffer tank includes a buffer tank body that stores the processing fluid from the pump, and a second heater wrapped around the buffer tank and configured to heat the processing fluid inside the buffer tank body into a supercritical state.

US Pat. No. 10,796,896

DESORPTION BEAM CONTROL WITH VIRTUAL AXIS TRACKING IN TIME-OF-FLIGHT MASS SPECTROMETERS

1. A method for the operation of a time-of-flight mass spectrometer, comprising the steps:pulsed ionization of a sample deposited on a sample support in an ion source using a desorption beam, where the desorption beam is deflected from an axis of the ion source for part of the time in order to sweep a sample surface, and
acceleration of ions onto a flight path using diaphragms which act as ion-optical lenses, where at least one of the diaphragms is subdivided into a plurality of segments and the segments are supplied with asymmetrical voltages, harmonized with the deflection of the desorption beam, such that ions which are produced in a desorption beam spot off the axis are accelerated in phase into an ion beam by a lens center off the axis, which acts in said at least one diaphragm, said ion beam running parallel to the axis.

US Pat. No. 10,796,895

SPRAY CHAMBERS AND METHODS OF USING THEM

PerkinElmer Health Scienc...

1. A spray chamber comprising:an outer chamber comprising an inlet end, an outlet end, a drain and dual makeup gas inlet ports each configured to receive a gas to provide a tangential gas flow within the outer chamber, wherein the inlet end is configured to couple to a nebulizer to receive a liquid sample from the nebulizer, and wherein the outlet end is configured to provide an aerosolized sample spray; and
an inner tube within the outer chamber, the inner tube comprising two or more microchannels, wherein at least one microchannel is positioned at each side of the inner tube, and wherein each of the at least one microchannels is sized and arranged to receive makeup gas to reduce droplet deposition on the inner tube.

US Pat. No. 10,796,894

SYSTEM AND METHOD FOR IONIZATION OF MOLECULES FOR MASS SPECTROMETRY AND ION MOBILITY SPECTROMETRY

University Of The Science...

29. A system, comprising:an ionizing apparatus, the ionizing apparatus including:
an analyzer device having an inlet;
a tube having a first end and a second end, the tube defining a channel extending from the first end to the second end, wherein the channel defines an ionizing region in which net neutral particles of a sample are received and become electrically charged, at least in part, due to a pressure differential between the first end and the second end of the tube as the net neutral particles move through the channel,
wherein molecular and fragment ions of an analyte are generated prior to entering the inlet of the analyzer device in the absence of an ion source other than the channel itself.

US Pat. No. 10,796,893

RF ION GUIDE WITH AXIAL FIELDS

PerkinElmer Health Scienc...

1. An apparatus, comprising:a RF ion guide having an ion guide axis extending between an input end of the RF ion guide and an exit end of the RF ion guide, the RF ion guide comprising:
a first rectilinear electrode extending along the ion guide axis, the first electrode configured to be connected to a DC voltage source, and
a second rectilinear electrode extending along the ion guide axis, the second electrode configured to be connected to a RF source, at least a portion of the second electrode being positioned between the first electrode and the ion guide axis, the second electrode defining a longitudinal elongated slot extending through a plane of the second electrode, and wherein the first electrode is disposed beyond the plane of the second electrode,
wherein a distance between the first electrode and the second electrode varies along the ion guide axis, and
wherein the RF ion guide is configured, during operation of the apparatus, to produce RF electric fields within a central portion of the RF ion guide throughout a region between the second electrode and the ion guide axis to radially confine ions, and
wherein the RF ion guide is configured, during operation of the apparatus, to generate a DC electric field at the RF ion guide axis that has a non-zero axial component throughout at least a portion of the length of the RF ion guide.

US Pat. No. 10,796,892

SAMPLE MOUNTING PLATE AND METHOD FOR MANUFACTURING THE SAME

CITIZEN FINEDEVICE CO., L...

1. A sample mounting plate used for mass spectrometry by MALDI process and comprising one or more sample mounting spots for mounting a sample thereon, on a substrate, whereina hydrophilic surface of a first hydrophilic film is formed in the sample mounting spots on a face of the substrate where the sample mounting spots are provided,
a hydrophobic surface of a hydrophobic film extends around the hydrophilic surface as seen in a plan view of the sample mounting plate, and
a boundary part formed of a second hydrophilic film or a hydrophilic member, which has higher hydrophilicity than that of the hydrophilic surface, is formed between the hydrophilic surface and the hydrophobic surface as seen in the plan view of the face of the sample mounting plate.

US Pat. No. 10,796,891

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD

SEMES CO., LTD., Chungch...

1. An apparatus for processing a substrate, the apparatus comprising:a chamber having a processing space inside;
a support unit configured to support the substrate in the processing space;
a gas supply unit configured to supply gas into the processing space;
a plasma source configured to generate plasma from the gas supplied into the processing space; and
a detection unit provided in a hole formed in a sidewall of the chamber, the detection unit being configured to measure an impedance change varying with a degree of deposition of particles introduced through the hole in the sidewall and detect a degree of adsorption of particles on an inner wall of the chamber or a surface of a part that is exposed to the processing space,
wherein the detection unit includes:
a diaphragm installed in an inspection space in the sidewall of the chamber and deformed by deposition of particles, the inspection space being in communication with the processing space.

US Pat. No. 10,796,890

PLASMA PROCESSING APPARATUS AND SAMPLE STAGE THEREOF

HITACHI HIGH-TECH CORPORA...

1. A plasma processing method comprising the steps of:mounting a wafer to be processed on an upper surface of a sample stage which is disposed in a processing chamber inside a vacuum vessel;
generating a plasma inside the processing chamber; and
adjusting a temperature of the wafer in a predetermined permissible range using at least one of heater units which is disposed inside a dielectric film constituting the upper surface of the sample stage and configured to generate heat,
wherein the at least one of heater units is comprised of a plurality of arcuate portions which are arranged in a ring-shape so as to surround a central region of the dielectric film and connected in series inside the dielectric film, and the at least one of heater units is supplied DC power from a DC power supply, wherein each of the plurality of arcuate portions constituting a circuit arranged in a ring-shape is connected to an adjacent arcuate portion by each of a plurality of connection portions and has a same length forming a same circumferential angle around the central region, and each of the heater units disposed in each of the plurality of the ring-shaped regions constitutes a loop, and the arcuate portions disposed in one of the ring-shaped regions closer to the center region form a greater circumferential angle around the central region than those of the arcuate portions disposed in the ring-shaped region outwardly located, and
the step of adjusting the temperature of the wafer includes a step of adjusting amounts of DC current in each of the plurality of arcuate portion of the at least one of heater units supplied from the DC power supply.

US Pat. No. 10,796,889

PROCESSING APPARATUS FOR TARGET OBJECT AND INSPECTION METHOD FOR PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A processing apparatus for a target object, comprising:a chamber main body in which a chamber is provided;
a stage, configured to support the target object placed thereon and provided within the chamber, having therein a first passage for a coolant and a space communicating with the first passage;
a first pipeline having a first end portion inserted into the space to be connected to the first passage and a second end portion connected to a coolant supply mechanism; and
a first sealing member provided at a gap between a wall surface confining the space and the first end portion and configured to seal the gap,
wherein a second passage having one end and the other end is formed within the stage, and the one end of the second passage is connected to the gap, and
the first sealing member is in contact with the wall surface at a side of the first passage with respect to the second passage,
wherein the processing apparatus further comprises:
a second pipeline connected to the other end of the second passage; and
a detecting device connected to the second pipeline and configured to detect an amount of the coolant flowing in the second pipeline, and
wherein the first sealing member is disposed to be in direct contact with the first pipeline.

US Pat. No. 10,796,888

ION ASSISTED DEPOSITION FOR RARE-EARTH OXIDE BASED THIN FILM COATINGS ON PROCESS RINGS

Applied Materials, Inc., ...

1. A chamber component for a processing chamber comprising:a ring shaped body defined by an inner diameter and an outer diameter, the ring shaped body comprising at least one of an oxide based ceramic, a nitride based ceramic or a carbide based ceramic, wherein the ring shaped body is a sintered ceramic body comprising a top flat region, a ring inner side along the inner diameter of the ring shaped body and a ring outer side along the outer diameter of the ring shaped body, wherein the ring inner side comprises an approximately vertical wall and a step on a plasma-facing surface of the ring shaped body; and
a protective layer on at least the top flat region, the ring inner side and the ring outer side of the ring shaped body, wherein the protective layer is a conformal layer comprising a plasma resistant rare earth oxide, has a porosity of less than 1%, has an average surface roughness of less than 6 micro-inches, and has a first thickness of less than 300 ?m on the top flat region and a second thickness on the approximately vertical wall of the ring inner side, wherein the second thickness is 45-70% of the first thickness, and wherein the protective layer comprises a composition of 40-45 mol % of Y2O3, 5-10 mol % of ZrO2, 35-40 mol % of Er2O3, 5-10 mol % of Gd2O3, and 5-15 mol % of SiO2.

US Pat. No. 10,796,887

EFFICIENT NANOSECOND PULSER WITH SOURCE AND SINK CAPABILITY FOR PLASMA CONTROL APPLICATIONS

Eagle Harbor Technologies...

1. A high voltage, high frequency switching circuit comprising:a high voltage switching power supply that produces pulses having a voltage between 1 kV and 100 kV and with frequencies between 10 kHz and 1 MHz;
a transformer having a primary side including a primary winding and a secondary side including a secondary winding;
an output electrically coupled with the secondary side of the transformer, wherein the output is coupled with a plasma load that is capacitive in nature; and
a primary sink electrically coupled with both the primary side of the transformer and the output and ground, the primary sink comprising at least one resistor that discharges the plasma load coupled with the output.

US Pat. No. 10,796,886

DETECTION DEVICE, MICROWAVE OUTPUT DEVICE AND PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A detection device comprising:a substrate on which a connector connected to a transmission line for microwaves, a detection circuit configured to convert the microwaves inputted from the transmission line via the connector to a detection value indicating power of the microwaves, and an output port configured to output the detection value obtained by the detection circuit are disposed;
a housing that has a first opening and a second opening and accommodates the substrate in a state where the connector is inserted into the first opening and the output port is inserted into the second opening;
a first sealing member provided at the first opening of the housing to seal a periphery of the connector; and
a second sealing member provided at the second opening of the housing to seal a periphery of the output port.

US Pat. No. 10,796,885

CIRCUIT FOR IMPEDANCE MATCHING BETWEEN A GENERATOR AND A LOAD AT MULTIPLE FREQUENCIES, ASSEMBLY COMPRISING SUCH A CIRCUIT AND RELATED USE

Centre National de la Rec...

1. A circuit for impedance matching able to achieve simultaneous impedance matching between a generator (G) and a load (CH) for a supply signal comprising at least one first frequency and one second frequency, both being distinct from one another, said circuit comprising an impedance matching stage (S1) able to achieve impedance matching between the generator and the load for the first frequency, this stage (S1) comprising a circuit (C1) comprising at least a tuning impedance (ZTUNE) intended to be arranged in series between the generator (G) and the load (CH) and a load impedance (ZLOAD) intended to be arranged between the generator (G) and an earth,wherein said circuit for impedance matching further comprises at least one pair of additional stages (S2, S?2) able to achieve impedance matching, simultaneously, between the generator and the load for the second frequency, said pair of additional stages (S2, S2?) comprising:
a first additional stage (S2) comprising a load circuit (C2) arranged in parallel with respect to the load impedance (ZLOAD) of the impedance matching stage (S1), said load circuit (C2) comprising at least an inductance (Lload2) and a capacitor (Cload2) arranged in series, and
a second additional stage (S?2) comprising a tuning circuit (C?2) arranged in series with respect to the tuning impedance (ZTUNE) of the impedance matching stage (S1), said load circuit (C?2) comprising at least an inductance (L?tune2) and a capacitor (C?tune2) arranged in parallel,
the impedance matching stage (S1) furthermore being arranged between the first additional stage (S2) and the second additional stage (S?2)
and wherein said circuit for impedance matching further comprises at least one supplementary pair of additional stages able to achieve impedance matching, simultaneously, between the generator and the load for a third frequency, distinct from said first and second frequencies, said at least one supplementary pair of additional stages (S3, S?3) comprising:
a first supplementary additional stage (S3) comprising a load circuit (C3) arranged in parallel with respect to the load impedance (ZTUNE) of the impedance matching stage (S1), said load circuit (C3) comprising at least an inductance (Lload3) and a capacitor (Cload3) arranged in series,
a second supplementary additional stage (S?3) comprising a tuning circuit (C?3) arranged in series with respect to the tuning impedance (ZTUNE) of the impedance matching stage (S1), said load circuit (C?3) comprising at least an inductance (L?tune3) and a capacitor (C?tune3) arranged in parallel,
the assembly formed by the impedance matching stage (S1) and by the pair of additional stages (S2, S?2) furthermore being arranged between the first supplementary additional stage (S3) and the second supplementary additional (S?3) stage.

US Pat. No. 10,796,884

PLASMA PROCESSING APPARATUS

HITACHI HIGH-TECH CORPORA...

1. A plasma processing apparatus comprising:a processing chamber for plasma processing of a sample;
a dielectric window for air-tightly sealing the processing chamber;
two induction antennas provided outside the dielectric window for generating an induced magnetic field;
two radio frequency power sources for supplying radio frequency power to the induction antennas; and
a controller configured to periodically change a phase difference of a radio frequency current flowing to the induction antennas over time,
wherein a first of the two induction antennas comprises a first plurality of U-shaped elements which receives radio frequency power from a first radio frequency power source, a first of said first plurality of U-shaped elements comprising first and second element portions extending in a first direction and connected at respective first ends to a third element portion which extends in a second direction orthogonal to said first direction, and a second of said first plurality of U-shaped elements comprising first and second element portions extending in said second direction and connected at respective first ends to a third element portion which extends in the first direction,
wherein a second of the two induction antennas comprises a second plurality of U shaped elements which receives radio frequency power from a second radio frequency power source, a first of said second plurality of U-shaped elements comprising first and second element portions extending in the second direction and connected at respective first ends to a third element portion which extends in the first direction, and a second of said first plurality of U-shaped elements comprising first and second element portions extending in said first direction and connected at respective first ends to a third element portion which extends in the second direction,
wherein the first plurality of induction antennas is arranged to have a first fold of a predetermined length in the first direction, and a second fold of a predetermined length in the second direction, and the second plurality of induction antennas is arranged to have a first fold of a predetermined length in the second direction, and a second fold of a predetermined length in the first direction, the two induction antennas being arranged such that the first and second pluralities of induction antennas cross with each other at right angles, and are adjacent and parallel to each other,
wherein a second end of said second element of said first plurality of U-shaped elements, and a second end of said second element of said second plurality of U-shaped elements, are connected only via an intermediate wiring connection, and
wherein all elements of said first induction antenna are connected only in series, and all elements of said second induction antenna are connected only in series.

US Pat. No. 10,796,883

DISCRETE CAPACITANCE SWITCHING CIRCUIT AND CAPACITOR ARRAY CIRCUIT INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A discrete capacitance switching circuit, comprising:a direct current (DC) decoupling capacitor connected between a power node that receives an alternating current (AC) signal and a first node;
a diode connected between the first node and a second node;
a unit capacitor connected between the second node and a reference node that receives a ground voltage; and
a bias circuit configured to apply a first DC voltage to the first node and apply a second DC voltage to the second node, wherein the first DC voltage and the second DC voltage control a switching operation of the diode.

US Pat. No. 10,796,882

CHARGED PARTICLE BEAM WRITING APPARATUS AND CHARGED PARTICLE BEAM WRITING METHOD

NuFlare Technology, Inc.,...

1. A charged particle beam writing apparatus comprising:a storage device configured to store writing pattern data defining a plurality of figure patterns;
detection circuitry configured to detect a figure portion whose shape needs to be corrected in the plurality of figure patterns, by interpreting shapes of the plurality of figure patterns;
correction figure data generation circuitry configured to generate pattern data of a correction figure pattern for correcting the figure portion detected, where the pattern data includes dose information to identify a dose of the correction figure pattern;
writing pattern data conversion circuitry configured to convert the writing pattern data of the plurality of figure patterns into writing pattern pixel data defining a value corresponding to a dose for each pixel;
correction figure pattern data conversion circuitry configured to convert the pattern data of the correction figure pattern into correction figure pattern pixel data defining a value corresponding to a dose for the each pixel, based on pixel setting common to that of the writing pattern pixel data;
combined-value pixel data generation circuitry configured to generate, for the each pixel, combined-value pixel data by adding the value defined in the writing pattern pixel data and the value defined in the correction figure pattern pixel data; and
a writing mechanism configured to write, using a charged particle beam, a pattern on a target object such that the each pixel is irradiated with a beam of a dose corresponding to a value defined in the combined-value pixel data.

US Pat. No. 10,796,881

METHOD FOR PROCESSING AN OBJECT

Carl Zeiss Microscopy Gmb...

1. A method for processing an object, comprising:directing a particle beam on the object so that a location of incidence of the particle beam on the object carries out a movement along a principal scanning path and a movement along a sub-scanning direction oriented transverse to the principal scanning path, the movement of the location of incidence of the particle beam along the sub-scanning direction being controlled on the basis of a reference signal and a detection signal;
modulating the directing of the particle beam in accordance with the reference signal; and
detecting secondary particles and producing the detection signal, which represents an intensity of the detected secondary particles,
wherein the method removes material from the object.

US Pat. No. 10,796,880

CHARGED PARTICLE BEAM DEVICE AND CHARGED PARTICLE BEAM DEVICE NOISE SOURCE DETERMINATION METHOD

HITACHI HICH-TECH CORPORA...

6. A charged particle beam device noise source determination method for extracting information regarding a noise source of a charged particle beam device, the method comprising:observing a control signal of a control unit that controls an electron optical system of the charged particle beam device;
executing frequency conversion processing on the observed signal by a first frequency conversion processing unit;
executing frequency conversion processing on an image signal output from a detector of the electron optical system of the charged particle beam device by a second frequency conversion processing unit; and
receiving a result of the frequency conversion processing executed by the first frequency conversion processing unit and a result of the frequency conversion processing executed by the second frequency conversion processing unit, and associating a peak frequency of a superimposed noise of the image signal with a noise source of the control unit which generates a noise having a peak frequency corresponding to the peak frequency of the superimposed noise within the image signal by the frequency analysis and comparison processing unit.

US Pat. No. 10,796,879

SCANNING ELECTRON MICROSCOPE

Phenom-World Holding B.V....

1. Scanning electron microscope including an electron optical imaging system and a sample carrier, wherein the sample carrier is movable between a loading position for loading a sample and an imaging position for imaging the sample,wherein the scanning electron microscope includes a sliding vacuum seal between the electron optical imaging system and the sample carrier, wherein the sliding vacuum seal includes a first plate having a first aperture associated with the electron optical imaging system and resting against a second plate having a second aperture associated with the sample carrier, the first and second plates being slideably movable with respect to each other, the first and second apertures overlapping in the imaging position, and the first and second apertures not overlapping in the loading position,
wherein the first plate and/or the second plate includes a groove circumscribing the first and/or second aperture, wherein the groove is arranged for being in communication with a vacuum system.

US Pat. No. 10,796,878

REPELLER, CATHODE, CHAMBER WALL AND SLIT MEMBER FOR ION IMPLANTER AND ION GENERATING DEVICES INCLUDING THE SAME

VALUE ENGINEERING, LTD., ...

1. A chamber wall mounted inside an arc chamber of an ion generating device for an ion implanter to define a space where ions are generated wherein the chamber wall covers four sides of the arc chamber and its portion corresponding to at least one of the four sides of the arc chamber has a refractory metal material as a base material forming its shape and has a coating structure comprising a semicarbide layer on at least one surface of the base material,wherein the coating structure comprising a semicarbide layer comprises a refractory metal carbide structure in which a continuous or discontinuous refractory metal monocarbide layer is layered on a continuous or discontinuous refractory metal semicarbide layer.

US Pat. No. 10,796,877

CHARGED PARTICLE BEAM IMAGE ACQUISITION APPARATUS

NUFLARE TECHNOLOGY, INC.,...

1. A charged particle beam image acquisition apparatus comprising:a rectangular parallelepiped chamber where a target object is disposed;
a primary electron optical column placed on an upper surface of the chamber so that a point of intersection between two diagonal lines on the upper surface of the chamber is located at a center of a horizontal section of the primary electron optical column, a primary charged particle beam optics irradiating the target object with a primary charged particle beam being disposed in the primary electron optical column;
a secondary electron optical column connected to a lower portion of the primary electron optical column, a secondary charged particle beam optics being disposed in the secondary electron optical column and a secondary charged particle beam emitted as a result of an irradiation of the target object with the primary charged particle beam passing through the secondary charged particle beam optics;
a plurality of stage pedestals disposed on a same contour line in a state of being deformed by a differential pressure between internal and external pressures of the chamber on a bottom plate inside surface of the chamber, the stage pedestals being three or more in number; and
a stage supported by the plurality of stage pedestals and movable in a height direction, the target object being placed on the stage.

US Pat. No. 10,796,876

LOW WORK FUNCTION ELECTRON BEAM FILAMENT ASSEMBLY

COLORADO STATE UNIVERSITY...

1. A filament assembly comprising:a button having a planar emitter region with one or more apertures extending from an emission surface of the planar emitter region to an internal surface opposite of the emission surface;
an inlet electrical lead coupled to the button at a first side;
an outlet electrical lead coupled to the button at a second side opposite of the first side; and
a low work function object positioned adjacent to the internal surface of the planar emitter region and retained to the button, wherein:
the low work function object includes barium and is configured to evolve barium therefrom when heated;
the low work function material of the low work function object includes a porous ceramic material having the barium;
the porous ceramic material includes a refractory metal distributed with a ceramic that includes barium oxide, calcium oxide, and an other oxide;
the other oxide includes at least one of aluminum oxide, samarium oxide, or magnesium oxide; and
the refractory metal makes up at least 50% of the low work function object by weight.

US Pat. No. 10,796,875

LOW VOLTAGE ELECTRON TRANSPARENT PELLICLE

1. A system, comprising:a cathode;
an apparatus creating a voltage gradient that becomes more positive as distance from the cathode increases;
an arrangement enclosing at least the cathode and at least a portion of the voltage gradient and holding the cathode and the voltage gradient in position such that the voltage gradient originates with and extends from the cathode;
an electrical circuit, the electrical circuit connected to and supplying a voltage difference between the cathode and apparatus, supporting the voltage gradient; and
one or more pellicle structures, disposed within the arrangement, the one or more pellicle structures disposed between the cathode and the point distant from the cathode and comprising:
a deflecting structure;
an insulating structure; and
a pellicle;
wherein the deflecting structure of the pellicle structure nearest the cathode is in contact with a supporting surface supporting the cathode, the insulating structure is in contact with the deflecting structure without being in contact with the cathode, the deflecting layer coupling the insulating structure and the pellicle without being in contact with the cathode or apparatus, the pellicle being connected to the insulating structure without being in contact with the cathode or apparatus;
wherein at least the pellicle structure nearest the cathode further comprises a vacuum chamber, the vacuum chamber enclosing the cathode;
wherein the voltage gradient accelerates electrons emitted by the cathode toward the more positive regions of the gradient; and
wherein the pellicle allows electrons to pass and blocks atomic particles larger than electrons.

US Pat. No. 10,796,874

3D PRINTED MICRO CHANNEL PLATE, METHOD OF MAKING AND USING 3D PRINTED MICRO CHANNEL PLATE

UCHICAGO ARGONNE, LLC, C...

1. A gain device comprising a plurality of channels having a polygonal shape with four or more sides, wherein the device has an open area ratio of at least 80 percent.

US Pat. No. 10,796,873

FUSIBLE LINK IN BATTERY MODULE VOLTAGE SENSING CIRCUIT

NIO USA, Inc., San Jose,...

1. An electrical interconnect device providing an electrical interconnection between a battery module and a battery management system, comprising:a first dielectric substrate layer comprising a first planar surface and a second planar surface disposed opposite the first planar surface by a thickness of the first dielectric substrate layer;
a first electrical trace formed from an electrically conductive material directly on the first planar surface of the dielectric layer, the first electrical trace running a first length from a first end of the first electrical trace electrically interconnected with a positive terminal of a first battery cell in the battery module to a second end of the first electrical trace disposed at a corresponding first terminal of the battery management system, wherein the first electrical trace provides a voltage measurement of the first battery cell to the battery management system;
a first fusible link portion integrally formed in the first electrical trace on the first planar surface and disposed along a middle of the first length of the first electrical trace between the first and second ends of the first electrical trace, the first fusible link portion including a first controlled cross-sectional area in the first electrical trace configured to melt at a predetermined electrical current and break the first electrical trace and the electrical interconnection between the positive terminal of the first battery cell and the first terminal of the battery management system at the predetermined electrical current, wherein a total length of the first controlled cross-sectional area runs from a first point along the middle of the first length of the first electrical trace to a second point along the middle of the first length of the first electrical trace, wherein a width of the first controlled cross-sectional area running from the first point to the second point is disposed entirely within a width of the first electrical trace measured at the first point and at the second point, and wherein the width of the first controlled cross-sectional area tapers to the width of the first electrical trace at the first point and at the second point;
a second electrical trace formed from the electrically conductive material directly on the first planar surface of the dielectric layer immediately adjacent to the first electrical trace, the second electrical trace running a second length from a first end of the second electrical trace electrically interconnected with a positive terminal of a second battery cell in the battery module to a second end of the second electrical trace disposed at a corresponding second terminal of the battery management system, wherein the second electrical trace provides a voltage measurement of the second battery cell to the battery management system, and wherein the second battery cell is disposed immediately adjacent to the first battery cell in the battery module;
a second fusible link portion integrally formed in the second electrical trace on the first planar surface and disposed along a middle of the second length of the second electrical trace between the first and second ends of the second electrical trace, the second fusible link portion including a second controlled cross-sectional area in the second electrical trace configured to melt at a predetermined electrical current and break the second electrical trace and the electrical interconnection between the positive terminal of the second battery cell and the second terminal of the battery management system at the predetermined electrical current; and
a second dielectric substrate layer comprising a contact surface and an outer surface disposed opposite the contact surface by a thickness of the second dielectric substrate layer, wherein the contact surface of the second dielectric substrate layer is disposed in direct contact with the first planar surface of the first dielectric substrate layer, the first electrical trace, and the second electrical trace;
wherein the first electrical trace has a first cross-sectional area at the first and second ends, and wherein the first controlled cross-sectional area is sized less than the first cross-sectional area.

US Pat. No. 10,796,872

VEHICLE CIRCUIT BREAKER

KUOYUH W.L. ENTERPRISE CO...

1. A vehicle circuit breaker, comprising:a housing;
an electrode assembly, disposed in said housing and comprising a first electrode configured on said housing and a second electrode configured on said housing, said second electrode positioned at one side of said first electrode;
a first conducting element, configured on said first electrode, positioned inside said housing, and being a silver contact;
an electrode connection portion, configured on said second electrode and positioned inside said housing;
a first insertion portion, configured on said first electrode and positioned outside said housing;
a second insertion portion, configured on said second electrode and positioned outside said housing;
a bimetal conducting sheet, configured inside said housing and positioned correspondingly to said electrode assembly;
a plurality of conducting concave portions, configured on two respective sides of said bimetal conducting sheet, the depression depth of said conducting concave portions being 0.15 to 0.4 mm, and said bimetal conducting sheet is connected to said electrode connection portion through one of said conducting concave portions;
a second conducting element, configured on another of said conducting concave portions and positioned correspondingly to said first conducting element, thereby allowing said second conducting element to contact and electrically connect with said first conducting element, and said second conducting element being a silver contact;
a blocking element, movably configured inside said housing and positioned between said electrode assembly and said bimetal conducting sheet;
an elastic element, said blocking element and electrode assembly respectively connected to two ends thereof, and said blocking element adapted to move to between said first conducting element and second conducting element through the elastic force of said elastic element; and
a pressing portion, configured on said blocking element and passed out of said housing.

US Pat. No. 10,796,871

ELECTRIC SWITCH

Marquardt GmbH, Rietheim...

1. An electric switch comprising a contact system; a movable actuating element for switching over the contact system between two switch positions; and a drivable actuator, which is operatively connected to the actuating element such that the actuating element in at least one of the two positions is moved, on driving the actuator, into the other switch position by the actuator for switching the contact system, wherein the actuator is an electromagnet having a coil and an armature such that the operative connection between the actuator and the actuating element is effected by the armature, wherein the actuating element is moved by the actuator into the other switch position by acting of the armature via a plunger on a lip on the actuating element,wherein the switch has a housing, the actuator and electronics are located in the housing, the electronics are programmable electronics, which are arranged on a printed circuit board located in the housing,
wherein the printed circuit board has one of (i) a lug, by which the electronics are operated in an operating mode, and by at least partially removing the lug, the electronics are operated in another operation mode, such that the operation mode is a test mode and in the another operation mode the test mode is ended, or (ii) a programming lug, with contact-making points on the programming lug, and
wherein one of final inspection, or programming of the switch is made possible.

US Pat. No. 10,796,870

ELECTRONIC SWITCHING DEVICE AND SYSTEM

1. An electronic switch device for controlling a load, the device comprising:a housing assembly including a front cover assembly having a user accessible surface, a back body assembly, and a plurality of terminals configured to be coupled to an AC power source and the load;
an antenna assembly comprising an antenna substrate disposed inside the housing assembly adjacent a portion of the front cover assembly, an antenna being disposed on the antenna substrate having a conductive grid structure; and
a circuit assembly disposed inside the housing assembly coupled to the plurality of terminals, the circuit assembly comprising a printed circuit board, the printed circuit board including a ground plane, the circuit assembly being electrically connected to the antenna assembly via a conductor, the printed circuit board being separated from the antenna assembly by a predetermined distance, the circuit assembly including a relay switch having at least one solenoid winding connected to the circuit assembly and a set of contacts.

US Pat. No. 10,796,869

ELECTRICAL SWITCHING DEVICE

Siemens Aktiengesellschaf...

1. An electrical switching device, comprising:a first switching contact piece and a second switching contact piece, said switching contact pieces being movable relative to one another, said first switching contact piece having a lateral surface side and an enveloping contour with an end facing said second switching contact piece;
a fluid flow guiding device surrounding said lateral surface side of said first switching contact piece and forming a flow duct delimited between said fluid flow guiding device and said first switching contact piece, said flow duct having an enveloping contour with an end facing said second switching contact piece; and
at least said end of said enveloping contour of said flow duct facing said second switching contact piece, being larger than said end of said enveloping contour of said first switching contact piece facing said second switching contact piece.

US Pat. No. 10,796,868

THOMSON COIL INTEGRATED MOVING CONTACT IN VACUUM INTERRUPTER

EATON INTELLIGENT POWER L...

1. A vacuum chamber contact assembly for a circuit breaker, said circuit breaker including a housing assembly, said vacuum chamber contact assembly comprising:a vacuum housing assembly defining a sealed enclosed space;
a conductor assembly including a first stationary conductor assembly, a second stationary conductor assembly, and a movable conductor assembly;
an operating mechanism including a number of stationary components, a number of movable components and an actuator/latch assembly;
wherein said movable conductor assembly and said operating mechanism movable components are disposed entirely within said vacuum housing assembly enclosed space;
wherein said actuator/latch assembly includes an open, first latch unit and a close, second latch unit;
said movable conductor assembly moves between an open, first position, wherein said movable conductor assembly is spaced from, and is not in electrical communication with said first stationary conductor assembly and said second stationary conductor assembly, and, a second position, wherein said movable conductor assembly is coupled to, and is in electrical communication with said first stationary conductor assembly and said second stationary conductor assembly; and
wherein said actuator/latch assembly is structured to maintain said movable conductor assembly in both said first position and said second position.

US Pat. No. 10,796,867

COIL-TYPE AXIAL MAGNETIC FIELD CONTACT ASSEMBLY FOR VACUUM INTERRUPTER

Eaton Intelligent Power L...

1. An electrode assembly for a vacuum interrupter, the electrode assembly comprising:a contact plate;
an electrode coil connected to the contact plate, the electrode coil including:
a base for attachment to a terminal post of the vacuum interrupter, and
at least one arcuate arm between the base and the contact plate, each arcuate arm extending along a curved path in a plane approximately perpendicular to a direction of travel of the electrode assembly; and
at least one support member;
wherein:
each arcuate arm of the electrode coil includes an end surface that includes an aperture that is positioned to align with a corresponding aperture of an adjacent end surface of an arcuate arm of the electrode coil, and
each support member is partially positioned within aligned apertures to maintain a gap between adjacent end surfaces.

US Pat. No. 10,796,866

DIRECT CURRENT CIRCUIT BREAKER

HUAZHONG UNIVERSITY OF SC...

1. A direct current circuit breaker, comprising:n in number circuit breaker modules connected in series;
one energy-absorbing and voltage-limiting module connected in parallel to the n in number circuit breaker modules; and
a trigger module;whereinthe n in number circuit breaker modules each comprise a mechanical switch and a commutation branch circuit which are connected in parallel;
each commutation branch circuit comprises a charging commutation module and a commutation capacitor which are connected in series;
the charging commutation module is configured to charge up the commutation capacitor and produce reverse current to cut off the mechanical switch;
the one energy-absorbing and voltage-limiting module is configured to absorb energy stored in inductive elements of power systems after a fault current is cut off, so as to limit voltage and protect the mechanical switch;
the trigger module is connected in parallel to n in number charging commutation modules, and is configured to trigger and turn on the n in number charging commutation modules after faults; and
n is a positive integer greater than or equal to 1.

US Pat. No. 10,796,865

BLOCKING MEMBERS AND CIRCUIT BREAKERS HAVING QUICK-MAKE FEATURE

ABB Schweiz AG, Baden (C...

1. A blocking member for an actuator having a movable arm for effecting a quick-make feature, the blocking member comprising:an elongated member having a first end and a second end, wherein a portion of the elongated member is configured such that (i) when the blocking member is disposed in a first position, the movable arm is disposed through the blocking member and the blocking member engages a portion of the movable arm of the actuator to restrain movement of the movable arm and (ii) when the blocking member is disposed in a second position, the movable arm is disposed through the blocking member and the blocking member disengages from the portion of the movable arm of the actuator to permit movement of the movable arm.

US Pat. No. 10,796,864

STRUCTURE OF A FOB KEY FOR INCREASING THE OPERATING FORCE OF A BUTTON

Continental Automotive Gm...

1. A fob key for a vehicle, comprising:a housing accommodating a printed circuit board mounted with touch switches and electrical parts,
buttons arranged on the housing and able to move toward the touch switches, and
a button-supporting structure elastically supporting the buttons in a direction far away from the touch switches,
wherein said button includes the following structures:
a body portion on which an operating force is exerted, and
a rod portion protruding from the body portion toward a touch switch to transfer the operating force to the touch switch
wherein said button-supporting structure elastically supports the body portion of said button and said button-supporting structure is supported by a support block formed on said housing, and
wherein said button-supporting structure includes:
a base plate, which is a sheet plate supported by said support block, and
elastic support pieces protruding aslant from said base plate to elastically support said body portions of said buttons.

US Pat. No. 10,796,863

FABRIC KEYBOARD

APPLE INC., Cupertino, C...

1. An input device, comprising:a frame defining an aperture and a frame flange extending from the aperture;
a keycap within the aperture and operable to move with respect to the frame, the keycap comprising a top surface projecting above the aperture and a keycap flange laterally extending from the keycap and operable to contact the frame flange to block movement of the keycap relative to the aperture;
a switch positioned under the keycap; and
a fabric disposed over the frame and the keycap and comprising:
a first region bonded to the top surface of the keycap using adhesive;
a second region bonded to the frame using adhesive; and
a set of sidewalls connected to the first region and the second region, the set of sidewalls having a height less than a total distance between the top surface and the keycap flange of the keycap;
wherein the set of sidewalls extends downward beneath the frame and upward along a side of the keycap when the keycap is not traveling to permit the keycap to travel without stretching the fabric or exerting force on the keycap.

US Pat. No. 10,796,862

KEYBOARD

Chicony Electronics Co., ...

1. A keyboard, comprising:a first substrate having a first through hole;
a second substrate disposed on the first substrate and having a second through hole, wherein the second through hole is connected to the first through hole and located within an inner edge of the first through hole;
a keyswitch circuit disposed on one of the first substrate and the second substrate;
a connecting member engaged with the second through hole and extended onto a bottom surface of the second substrate facing toward the first substrate; and
a keyswitch assembly located on a top surface of the second substrate facing away from the first substrate, connected to the connecting member, and configured to trigger the keyswitch circuit,
wherein the connecting member comprises an engaging portion, the engaging portion is located in the first through hole, and in a cross section passing through the first through hole and the second through hole, a width of the engaging portion is smaller than a width of the first through hole and greater than a width of the second through hole.

US Pat. No. 10,796,861

KEY MODULE

LITE-ON ELECTRONICS (GUAN...

1. A key module, comprising:a key cap;
a bottom plate; and
a scissors structure having a first supporting member and a second supporting member pivoted to the key cap and the bottom plate respectively, wherein the first supporting member has a plurality of protruding shafts, the second supporting member has a plurality of axle holes, and the plurality of protruding shafts are movably pivoted to the plurality of axle holes respectively,
wherein the first supporting member has a first body and a plurality of first extending portions, the first body is pivoted to the key cap, and the plurality of first extending portions extend from the first body toward the second supporting member and are pivoted to the bottom plate; the second supporting member has a second body and a plurality of second extending portions, the second body is pivoted to the key cap, and the plurality of second extending portions extend from the second body toward the first supporting member and are pivoted to the bottom plate,
wherein the plurality of first extending portions have a first material and a second material, the plurality of second extending portions have the first material and the second material, the first material is different from the second material, and the first material partially covers the second material.

US Pat. No. 10,796,860

HERMETICALLY SEALED OVER-MOLDED BUTTON ASSEMBLY

N2 Imaging Systems, LLC, ...

1. A button assembly comprising: a plastic cover; an elastomeric button over-molded on the plastic cover; and a plastic housing, wherein the plastic housing includes a wall having an exterior surface and an interior surface, and wherein the wall has an aperture extending therethrough from the exterior surface to the interior surface; and wherein a raised ridge is formed on the exterior surface of the wall surrounding the aperture;wherein the plastic cover is mechanically attached to the plastic housing, the elastomeric button disposed at least partially between the plastic cover and the plastic housing;
wherein the button includes an upper actuation portion and a lower body portion, wherein the lower body portion of the button has an outer wall with a bottom surface having a channel for accommodating the raised ridge surrounding the aperture in the housing.

US Pat. No. 10,796,859

HAND-HELD POWER TOOL

Robert Bosch GmbH, Stutt...

1. A hand-held power tool, comprising:a tool receiver;
a tool housing;
a drive motor arranged in the tool housing and configured to drive the tool receiver, the drive motor further configured to be switched on and off via an electric On/Off switch; and
an actuating device configured to actuate the On/Off switch, the actuating device having a pivotably mounted actuating element and a pivotably mounted pawl configured to be coupled to the actuating element,
wherein the pawl is further configured, in a free-running state, to move pivotably relative to the actuating element without exerting an actuating force upon the actuating element and, in an actuation state, to exert upon the actuating element the actuating force that actuates the actuating device.

US Pat. No. 10,796,858

SOLAR CELL COMPRISING GRAINS OF A DOPED SEMICONDUCTING MATERIAL AND A METHOD FOR MANUFACTURING THE SOLAR CELL

Exeger Operations AB, St...

1. A solar cell comprising:a porous insulating substrate (2),
a first porous conducting layer (4) and a second porous conducting layer (6) disposed on opposite sides of the porous insulating substrate (2),
a light absorbing layer (8) in electrical contact with the first porous conducting layer (4) and disposed on top of said first porous conducting layer (4) opposite said porous insulating substrate (2) to directly face unrestricted incident light, and
an electrolyte integrally positioned through the first and second porous conductive layers (4, 6), the porous insulating substrate (2) and the light absorbing layer (8) to transfer charge carriers between the second porous conducting layer (6) and the light absorbing layer (8),
wherein the light absorbing layer (8) comprises a single layer of a plurality of grains (10) composed of doped semiconducting material adapted to generate photo-exited electrons when directly impacted by the unrestricted incident light,
said grains (10) are arranged in a single layer along the first porous conducting layer (4) with each said grain (10) having an upper portion (20) of doped semiconducting material directly facing the unrestricted incident light and away from said first porous conducting layer (4), and a lower portion (22) of doped semiconducting material in physical and electrical contact with the first porous conducting layer (4), said grains (10) not containing dye adsorbed on surfaces thereof, and
said electrolyte fills spaces between the grains (10) in said light absorbing layer (8).

US Pat. No. 10,796,856

ALUMINUM CAPACITOR POSITIVE ELECTRODE FOIL PRODUCT HAVING HIGH VOLTAGE RESISTANCE AND MANUFACTURING METHOD THEREOF

Trusval Technology Co., L...

1. A manufacturing method of an aluminum capacitor positive electrode foil product having high voltage resistance, comprising the following steps conducted in a vacuum environment:(a) preparing an aluminum foil substrate on a roller in a rolling-out chamber and heating the aluminum foil substrate at a temperature of 250° C.-350° C. for 30-60 seconds;
(b) transferring the aluminum foil substrate from the rolling-out chamber to a first chamber for heating at a temperature of 250° C.-350° C. for 30-60 seconds and ion bombarding a surface of the aluminum foil substrate for 30-60 seconds to form a pyramid surface layer on the surface of the aluminum foil substrate;
(c) transferring the aluminum foil substrate from the first chamber to a second chamber and reverse sputtering the surface of the aluminum foil substrate for 30-60 seconds for cleaning, decontamination and degreasing;
(d) transferring the aluminum foil substrate to a third chamber and depositing the pyramid surface layer of the aluminum foil substrate by an aluminum target material for 30-60 seconds to form a deposition layer;
(e) transferring the aluminum foil substrate to an oxidation chamber filled with mixed gases of argon (Ar) and oxygen (O2) for oxidation and spraying the mixed gases on an outer surface of the deposition layer of the aluminum foil substrate at a temperature of 150° C.-600° C. for 30-300 seconds to form an oxidized crystallizing layer;
(f) cooling the aluminum foil substrate to a temperature below 100° C. in a cooling chamber; and
(g) rolling the aluminum foil substrate by a cooling roll disposed in a rolling-back chamber to form a finished product.

US Pat. No. 10,796,855

MULTILAYER CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a body including a stacked structure formed of a plurality of dielectric layers and a plurality of internal electrodes; and
a plurality of external electrodes, each including a conductive layer disposed at a respective end of the body and connected to a respective portion of the plurality of internal electrodes, and a plating layer covering the conductive layer,
wherein, in each external electrode, the conductive layer includes nickel (Ni) and barium titanate (BT), an area occupied by nickel with respect to a total area of the conductive layer is 30% to 65%, and the plating layer directly contacts the conductive layer including nickel (Ni) and barium titanate (BT).

US Pat. No. 10,796,854

ELECTRONIC DEVICE

TDK CORPORATION, Tokyo (...

1. An electronic device comprising:a chip component including a terminal electrode formed on an element body; and
a metal terminal connectable with the terminal electrode of the chip component, wherein
the metal terminal includes:
a terminal body facing an end surface of the terminal electrode of the chip component; and
a pair of holding pieces formed on the terminal body,
a connection member configured to connect the terminal body and the end surface of the terminal body exists in a joint region within a predetermined range between the terminal body and the end surface of the terminal electrode, and
a pair of reinforcement pieces is formed on the terminal body so as not to overlap with the joint region in a direction extending from one to the other of the pair of holding pieces.

US Pat. No. 10,796,853

ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a capacitor body;
an external electrode disposed on an end of the capacitor body in a first direction and containing copper (Cu) as a main component;
a metal frame connected to the external electrode; and
a bonding member disposed between the external electrode and the metal frame,
wherein the bonding member includes a tin (Sn)-based solder layer;
a tin-copper based alloy solder layer disposed between the tin-based solder layer and the external electrode; and
a tin-based alloy solder layer disposed between the tin-based solder layer and the metal frame.

US Pat. No. 10,796,852

FILM CAPACITOR AND METHOD FOR MANUFACTURING FILM CAPACITOR

PANASONIC INTELLECTUAL PR...

1. A film capacitor comprising:a capacitor unit; and
an outer packaging resin covering the capacitor unit,
wherein:
the capacitor unit includes:
a capacitor group including a plurality of capacitor elements;
a first bus bar that extracts electricity from the capacitor group;
a second bus bar that extracts electricity from the capacitor group, the second bus bar facing the first bus bar;
a first fixation portion to which the first bus bar is fixed; and
a second fixation portion to which the second bus bar is fixed, the second fixation portion being different from the first fixation portion,
the first bus bar includes a connection terminal part formed at one end of the first bus bar, the second bus bar includes a connection terminal part formed at one end of the second bus bar,
each of the connection terminal part of the first bus bar and the connection terminal part of the second bus bar is exposed from the outer packaging resin to be connected to an external terminal,
the connection terminal part of the first bus bar is coupled to the first fixation portion,
the connection terminal part of the second bus bar is coupled to the second fixation portion, the first fixation portion and the second fixation portion are spaced apart along a direction from the connection terminal part of the first bus bar to the connection terminal part of the second bus bar,
the first bus bar further includes a coupling part formed at the one end of the first bus bar, and the second bus bar further includes a coupling part formed at the one end of the second bus bar,
the first bus bar is connected to an end-face electrode formed on one end face of each of the capacitor elements,
the second bus bar is connected to an end-face electrode formed on another end face of each of the capacitor elements,
the connection terminal part of the first bus bar and the coupling part of the second bus bar are coupled to the first fixation portion, and
the connection terminal part of the second bus bar and the coupling part of the first bus bar are coupled to the second fixation portion.

US Pat. No. 10,796,851

CAPACITOR COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A capacitor component comprising:a body including a plurality of dielectric layers and first and second internal electrodes, alternately disposed to face each other with respective dielectric layers interposed therebetween, the body having first and second surfaces, disposed to oppose each other, third and fourth surfaces, connected to the first and second surfaces and disposed to oppose each other, and fifth and sixth surfaces connected to the first, second, third, and fourth surfaces and disposed to oppose each other; and
first and second external electrodes disposed on external surfaces of the body and connected to the first and second internal electrodes, respectively,
wherein the body includes a capacitance forming portion, in which capacitance is formed by including the first and second internal electrodes disposed to face each other with respective dielectric layers interposed therebetween, cover portions disposed above and below the capacitance forming portion in a stacking direction of the first and second internal electrodes, and margin portions disposed on opposite sides of the capacitance forming portion, and
at least one selected from the cover portions and the margin portions includes a plurality of graphene platelets.

US Pat. No. 10,796,850

METALIZED FILM AND FILM CAPACITOR

PANASONIC INTELLECTUAL PR...

1. A metalized film comprising:a dielectric film having a strip-shape; and
a metal vapor-deposited electrode which is formed on a surface of the dielectric film and contains vapor-deposited metal, wherein:
an insulation margin where the vapor-deposited metal does not exist is provided on a first end portion of the dielectric film, the first end portion being located at one end in a width direction of the dielectric film, the insulation margin having a strip-shape that extends in a longitudinal direction of the dielectric film,
a plurality of first slits where the vapor-deposited metal does not exist and a plurality of fuses are provided close to a second end portion of the dielectric film, each of the plurality of fuses being disposed between a corresponding pair of the plurality of first slits, the second end portion being located at an other end in the width direction of the dielectric film, the plurality of first slits each having a strip-shape that extends in the longitudinal direction of the dielectric film,
the metal vapor-deposited electrode has a first electrode and a second electrode, the first electrode being disposed closer to the second end portion than the plurality of first slits, the second electrode being disposed closer to the first end portion than the plurality of first slits,
the second electrode includes a plurality of divided electrodes which are separated by a corresponding one of a plurality of second slits where the vapor-deposited metal does not exist and are arranged in the longitudinal direction, each of the plurality of second slits extending from the insulation margin to a corresponding one of the plurality of first slits,
each of the plurality of divided electrodes is connected to the first electrode through a corresponding one of the plurality of fuses,
when the metalized film is cut along a cutting line extending in the width direction at any position in the longitudinal direction of the metalized film, at least two divided electrodes among the plurality of divided electrodes are respectively cut into pieces at the cutting line, the at least two divided electrodes being arranged in the longitudinal direction,
when the metalized film is cut along a first cutting line extending in the width direction at a first position between both edges of each of the plurality of divided electrodes in the longitudinal direction of the metalized film, three divided electrodes among the plurality of divided electrodes are respectively cut into pieces at the first cutting line, the three divided electrodes being arranged in the longitudinal direction, and
a length of each of the three divided electrodes at the first cutting line is greater than a length of the each of the plurality of fuses in the longitudinal direction of the metalized film.

US Pat. No. 10,796,848

WIRELESS POWER SUPPLY COIL UNIT

NISSAN MOTOR CO., LTD., ...

1. A wireless power supply coil unit for transmitting or receiving power wirelessly, the coil unit comprising:a coil having a hollow portion and a coil axis in a vertical direction;
a first magnetic body having an opening at a position corresponding to the hollow portion of the coil;
a second magnetic body having a plate-like shape and arranged in the hollow portion of the coil on one side of the first magnetic body; and
an insulating plate interposed between the first magnetic body and the second magnetic body,
wherein a periphery of the second magnetic body overlaps with a circumferential part around the opening of the first magnetic body.

US Pat. No. 10,796,847

IGNITION COIL FOR INTERNAL COMBUSTION ENGINES

DENSO CORPORATION, Kariy...

1. An ignition coil for an internal combustion engine, the ignition coil comprising:a center core;
a bobbin having an axial direction, a circumferential direction, a radial direction and an inner space extending in the axial direction, the bobbin being made of thermoplastic resin and dispersed phase particles dispersed in the thermoplastic resin, the dispersed phase particles being lower in elasticity than the thermoplastic resin and having the center core disposed in the inner space in close contact with the bobbin;
a primary coil directly wound around the bobbin in the circumferential direction;
a secondary coil magnetically connected to the primary coil; and
a mold resin member in which the primary coil, the secondary coil, the bobbin, and the center core are embedded in the inner space, wherein
the bobbin includes an elastomer layer on an outer circumferential surface of the bobbin and a skin layer disposed on the outer circumferential surface of the elastomer layer, in the radial direction, the skin layer being in direct contact with the primary coil that is disposed on the outer circumferential surface of the skin layer.

US Pat. No. 10,796,846

LONG RANGE COIL AND POWER SOURCE FOR A MAGNETIC FIELD GENERATOR

Matrix Design Group, LLC,...

1. A long range coil and power source for a magnetic field generator comprising:a driver circuit having an input electrically coupled to a controller, said driver generating an electric current in response to electrical signals from the controller;
a coil comprising a core and a conductive wire wound about said core in a basketweave pattern, wherein a first end and a second end of the conductive wire are electrically coupled to an output of said driver circuit for receiving said current to create a magnetic field; and
a first end cap formed from a non-conductive material covering a first end of the coil and a second end cap formed from a non-conductive material covering a second end of the coil; wherein each end cap is provided with a plurality of anchor points such that the conductive wire is wound about the anchor points alternating between anchor points on the first end cap and anchor points on the second end cap such that the alternating anchor points are radially offset from one another and the wire is wound about the core in a single direction.

US Pat. No. 10,796,845

MAGNETIC SHUNT ASSEMBLY FOR MAGNETIC SHIELDING OF A POWER DEVICE

ABB Power Grids Switzerla...

1. A magnetic shunt assembly for magnetic shielding of a power device, comprising:a plurality of joined ferromagnetic sheets in the form of strips wound in a spiral arrangement, each of the plurality of joined ferromagnetic sheets having a same width and each made from a same grain-oriented ferromagnetic material, and a plurality of bonding layers for bonding subsequent sheets of said plurality of ferromagnetic sheets to form an integral assembly, wherein each of the plurality of ferromagnetic sheets is bonded to an adjacent one of the plurality of ferromagnetic sheets via a respective one of the plurality of bonding layers, wherein the ferromagnetic sheets and the bonding layers are aligned, said bonding layers being one of:
obtained from a thermosetting resin;
formed from an adhesive system comprising an epoxy adhesive and a curing agent;
formed from an adhesive system comprising an epoxy adhesive curable by heat;
formed from an adhesive system comprising an acrylic adhesive and a curing agent;
wherein the plurality of joined ferromagnetic sheets form outermost layers of the magnetic shunt assembly; and
means for coupling the magnetic shunt assembly externally of the power device.

US Pat. No. 10,796,844

MULTILAYER ELECTRONIC COMPONENT

TDK CORPORATION, Tokyo (...

1. A multilayer electronic component comprising:a multilayer stack including a plurality of dielectric layers and a plurality of conductor layers stacked together;
a plurality of terminals integrated with the multilayer stack; and
a shield formed of a conductor and integrated with the multilayer stack, wherein
the multilayer stack has a top surface and a bottom surface located at opposite ends in a first direction, and four side surfaces connecting the top surface and the bottom surface,
the plurality of terminals are provided on the bottom surface of the multilayer stack,
the shield entirely covers the top surface and the four side surfaces of the multilayer stack, and
the shield includes a portion thicker than the other portions of the shield.

US Pat. No. 10,796,843

ANTENNA COIL AND ANTENNA DEVICE

Tokyo Parts Industrial Co...

1. An antenna coil comprising: a magnetic material core elongated in the X direction; a holder made of resin mounted on the magnetic material core; a coil wound on the magnetic material core; metal terminals having first ends to which the ends of the coil are electrically connected; and lead wires which are electrically connected to second ends of the metal terminals, wherein:the holder has a core holding part that holds the magnetic material core and a terminal holding part for holding the metal terminals;
the metal terminals are made of copper covered steel;
the terminal holding part has through holes penetrating in the Z direction and position restraining grooves formed continuous with the through holes, into which at least a portion of the metal terminals are fitted; and
with the metal terminals press-fitted into the through holes, the first ends are bent in the Y direction, and the second ends are bent in the X direction, such that the positions thereof are restrained by the position restraining grooves.

US Pat. No. 10,796,842

METHOD TO FORM AN INDUCTIVE COMPONENT

CYNTEC CO., LTD., Hsinch...

1. A method to form an inductive component, comprising:forming a unitary metal structure, wherein the unitary metal structure comprises a conductor wire and a lead frame, wherein the conductor wire is a bare metal wire, and the lead frame and the bare metal wire are integrally formed, wherein the lead frame comprises a first part and a second part spaced apart from the first part, wherein a contiguous metal path is formed from the first part of the lead frame to the second part of the lead frame via the bare metal wire; and
forming a magnetic body, wherein the magnetic body encapsulates the bare metal wire, a first portion of the first part of the lead frame adjacent to one end of the bare metal wire, and a first portion of the second part of the lead frame adjacent to the other end of the bare metal wire, wherein a second portion of the first part of the lead frame and a second portion of the second part of the lead frame are exposed outside the magnetic body, wherein said first portion of the first part of the lead frame is embedded inside the magnetic body and has a first width larger than a second width of the bare metal wire, wherein the entire bare metal wire is embedded inside the magnetic body and the outer surface of the bare metal wire is entirely in contact with the magnetic body.

US Pat. No. 10,796,841

INDUCTOR WITH FLUX PATH FOR HIGH INDUCTANCE AT LOW LOAD

Universal Lighting Techno...

1. A magnetic component comprising:a bobbin having a first end flange, a second end flange and a passageway through the bobbin from the first end flange to the second end flange;
at least one coil positioned around the passageway between the first end flange and the second end flange;
a first E-core and a second E-core, each E-core having a respective main body, a respective middle leg, a respective first outer leg and a respective second outer leg, the legs of each E-core extending from the respective main body to respective end surfaces, the middle legs of the two E-cores positioned in the passageway of the bobbin with the respective end surfaces of the middle legs juxtaposed within the passageway and spaced apart by a first magnetic gap, each middle leg having a respective first longitudinal surface perpendicular to the respective end surface, the first and second outer legs of the two E-cores positioned outside the bobbin with the end surface of the first outer leg of the first E-core engaging the end surface of the first outer leg of the second E-core and with the end surface of the second outer leg of the first E-core engaging the second outer leg of the second E-core; and
a first I-bar positioned in the passageway in alignment with the middle leg of the first E-core and in alignment with the middle leg of the second E-core, the first I-bar spanning the first magnetic gap with a first portion of the first I-bar parallel to and spaced apart from the first longitudinal surface of the middle leg of the first E-core to form a second magnetic gap between the first I-bar and the longitudinal surface of the middle leg of the first E-core with at least a portion of the second magnetic gap positioned within the passageway, and with a second portion of the first I-bar parallel to and spaced apart from the first longitudinal surface of the middle leg of the second E-core to form a third magnetic gap between the first I-bar and the longitudinal surface of the middle leg of the second E-core with at least a portion of the third magnetic gap positioned within the passageway.

US Pat. No. 10,796,840

COIL COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A coil component comprising:a body including a support member including a through-hole filled with a magnetic material and a via hole filled with a conductive material, and containing an insulating material; a coil including a first coil disposed on one surface of the support member and a second coil disposed on the other surface of the support member opposing the one surface thereof; and the magnetic material encapsulating the support member and the coil; and
external electrodes disposed on an external surface of the body and connected to the coil,
wherein the first and second coil, respectively, comprise first and second seed patterns, and a thickness of the first seed pattern is thinner than that of the second seed pattern, and
the support member includes a first support member including the one surface of the support member and a second support member including the other surface of the support member.

US Pat. No. 10,796,839

RADIO FREQUENCY TRANSFORMER WINDING COIL STRUCTURE

PPC BROADBAND, INC., Eas...

1. A radio-frequency (RF) transformer, comprising:a ferrite core having an outer surface;
a winding structure comprising a pair of conductive wires wound about a portion of the outer surface; and
a spacer positioned at least partially between the ferrite core and the winding structure and configured to provide a gap between the ferrite core and the winding structure,
wherein:
the pair of conductive wires comprises a first wire and a second wire,
the pair of conductive wires forms a first twisted wire pair placed as a middle turn of the winding structure, and including a first plurality of consecutive windings disposed over the outer surface,
for frequencies of signals rising through approximately 300 MHz, the placement of the first twisted wire pair on the ferrite core is configured to decrease effectiveness of magnetic coupling between the first twisted wire pair and the ferrite core, and to provide a dominant capacitive coupling among the first plurality of consecutive windings,
a first turn of the second wire, but not the first wire, is formed through the center of the ferrite core and around an outside portion of the ferrite core,
a second turn of the second wire, but not the first wire, is formed through the center of the ferrite core and around the outside portion of the ferrite core,
the first twisted wire pair is positioned as the middle turn between the first and second turns of the second wire,
the pair of conductive wires forms a second twisted wire pair including a second plurality of consecutive windings placed at a center of the winding structure and extending from the first twisted wire pair, and
for signals in the winding structure having frequencies from about 5 MHz to about 1700 MHz, the placement of the second twisted wire pair at the center of the winding structure is configured to increase high frequency coupling.

US Pat. No. 10,796,838

NETWORK TRANSFORMER MODULE

Delta Electronics, Inc., ...

1. A network transformer module, comprising:a first magnetic element, comprising:
a first iron core; and
a first coil winding, wound around the first iron core;
wherein the first coil winding is wound 7 to 14 turns around the first iron core;
wherein the first coil winding is composed of a first wire and a second wire; and
a second magnetic element, comprising:
a second iron core; and
a second coil winding, wound around the second iron core;
wherein the second coil winding is wound 2 to 5 turns around the second iron core;
wherein the second coil winding is composed of a third wire and a fourth wire;
wherein the first coil winding forms M layers of coil on the first iron core and M is a positive integer greater than 2;
wherein the second coil winding forms N layers of coil on the second iron core, and N is a positive integer greater than 1;
wherein the number of turns in each layer of the first coil winding is the same, and the number of turns in each layer of the second winding is the same; and
wherein a ratio of M to N is 2:1.

US Pat. No. 10,796,837

ELECTRONIC COMPONENT, DIAPHRAGM, AND ELECTRONIC DEVICE

Murata Manufacturing Co.,...

1. An electronic component comprising:an insulating base material including a first main surface on a mounting surface side, the insulating base material including a plurality of insulating base material layers that are laminated in a lamination direction;
a coil including a coil conductor provided on at least one of the plurality of insulating base material layers and including a winding axis extending in the lamination direction;
a mounting electrode provided on the first main surface and connected to the coil;
a projection provided on at least an electrode non-forming portion of the first main surface, the electrode non-forming portion including no mounting electrode; and
a recess or a through-hole provided in the electrode non-forming portion and disposed at a position including a coil opening of the coil when viewed from the lamination direction; wherein
the projection is provided along the coil conductor in a planar view of the first main surface;
the coil conductor is disposed across different positions in the lamination direction; and
a first portion of the coil conductor, which is positioned on an innermost peripheral side when viewed from a winding axis direction, is farther away from the first main surface in the lamination direction as compared to a second portion of the coil conductor which is located closest to the first main surface.

US Pat. No. 10,796,836

INDUCTOR

SAMSUNG ELECTRO-MECHANICS...

1. An inductor comprising:a body including a plurality of insulating layers stacked therein, wherein a plurality of coil patterns are respectively disposed on the plurality of insulating layers; and
first and second external electrodes disposed on an external surface of the body,
wherein:
the plurality of coil patterns are connected to each other by a plurality of coil connecting portions, and opposing ends of the plurality of coil patterns are connected to the first and second external electrodes through coil lead portions, respectively, to form a coil,
the plurality of coil patterns include outer coil patterns disposed in an outer portion of the body and inner coil patterns disposed in an inner portion of the body, the outer and inner coil patterns each being connected in parallel,
a first coil connecting portion of the plurality of coil connecting portions connects the outer coil patterns, and a second coil connecting portion of the plurality of coil connecting portions connects one coil pattern of the outer coil patterns and another coil pattern of the inner coil patterns adjacent to the one coil pattern of the outer coil patterns, and
the first and second coil connecting portions are disposed in a staggered manner.

US Pat. No. 10,796,835

STACKED LAMINATE INDUCTORS FOR HIGH MODULE VOLUME UTILIZATION AND PERFORMANCE-COST-SIZE-PROCESSING-TIME TRADEOFF

Qorvo US, Inc., Greensbo...

1. An electronic device comprising:a first substrate comprising a first substrate body and a first inductor portion integrated into the first substrate body;
a second substrate comprising a second substrate body and a second inductor portion integrated into the second substrate body; and
a conductive connection component, wherein:
the second substrate is mounted on the first substrate such that the second inductor portion is positioned over the first inductor portion, wherein the first substrate body is separate from the second substrate body with a gap in between;
the second inductor portion is electrically connected to the first inductor portion so that the first inductor portion and the second inductor portion form a three dimensional (3D) inductor; and
the first inductor portion includes a first stack of conductive vias and the second inductor portion includes a second stack of conductive vias, wherein:
each of the first stack of conductive vias is aligned with one another, and each of the second stack of conductive vias is aligned with one another;
adjacent conductive vias of the first stack of conductive vias do not have non-conductive material in between and adjacent conductive vias of the second stack of conductive vias do not have non-conductive material in between; and
the second stack of conductive vias is mounted on and electrically connected to the first stack of conductive vias by the conductive connection component, which resides within the gap, to form a first elongated column of conductive vias,
such that current eligible to propagate vertically along the first elongated column.

US Pat. No. 10,796,834

MAGNETIZATION METHOD, MAGNETIZATION APPARATUS AND MAGNET FOR MAGNETIC ENCODER

UCHIYAMA MANUFACTURING CO...

1. A magnetization method for forming an objective magnetized state presenting a half wavelength pulse of a sine wave in a one-dimensional region of a magnetic body, the magnetization method comprising:applying magnetism in one direction to an entire half wavelength interval of the sine wave on the magnetic body by a magnetizing yoke and forming a magnetized state of a first-order rectangle wave or of a first-order trapezoidal wave in the interval, the magnetized state presenting polarity information in a rectangle or trapezoidal pulse shape, and thereafter,
applying magnetism in opposite direction to a start point and a terminal point of the interval by the same magnetizing yoke or a different magnetizing yoke one time or several times and changing the magnetized state of the first-order rectangle wave or of the first-order trapezoidal wave into the objective magnetized state.

US Pat. No. 10,796,833

MAGNETIC TUNNEL JUNCTION WITH LOW SERIES RESISTANCE

INTERNATIONAL BUSINESS MA...

1. An electrical device structure comprising:a magnetic tunnel junction structure including a first tunnel junction dielectric layer positioned between a free magnetization layer and a fixed magnetization layer;
a magnetization enhancement stack present on the magnetic tunnel junction structure, wherein the magnetization enhancement stack comprises a second tunnel junction layer that is in contact with the free magnetization layer of the magnetic tunnel junction structure, a metal contact layer present on the second tunnel junction layer, and a metal electrode layer present on the metal contact layer;
a metallic ring on a sidewall of the magnetic enhancement stack, wherein a base of the metallic ring may be in contact with the free magnetization layer of the magnetic tunnel junction structure, the metallic ring having an L-shaped side cross-sectional geometry; and
a dielectric spacer present on an outer sidewall of the metallic ring and a base portion of the metallic ring, the outside sidewall of the dielectric spacer aligned with an outside sidewall of the base portion of the metallic ring having the L-shaped side cross-sectional geometry.

US Pat. No. 10,796,832

DETERMINING THE MOVEMENT PROFILE OF AN ARMATURE IN A MAGNET

Siemens Aktiengesellschaf...

1. A method for determining a movement profile of a plunger-type armature in a solenoid for monitoring a plunger-type armature movement for changes, the solenoid being an electromagnet in which a magnetic field can be generated by means of an electrical coil, and a measuring unit is connected to the electrical coil, which comprises the steps of:measuring a current profile with respect to time when the solenoid is operated;
examining a measured current profile with respect to time for a position of a first reversal point in respect of the time after operation of the solenoid and a current intensity;
assigning the position of the first reversal point to a movement end of the plunger-type armature; and
comparing the position of the first reversal point with a reference position, wherein a shift in the position of the first reversal point toward longer times after operation of the solenoid is assessed as a slowdown of a movement of the plunger-type armature in comparison to the reference position, wherein a shift in the position of the first reversal point toward lamer current intensities is assessed as an increase in friction losses in comparison to the reference position, and wherein the reference position of the first reversal point can be defined by a reference measurement, and in that, in subsequent operations of the solenoid, the position of the first reversal point is determined and compared with the reference position of the first reversal point.

US Pat. No. 10,796,831

MAGNETICALLY-RESPONSIVE SURFACE AND METHOD OF MANIPULATING PROPERTIES OF A SURFACE

The Board of Trustees of ...

1. A magnetically-responsive surface structure comprising:an array of hybrid microstructures on a substrate, each hybrid microstructure comprising an elastomeric micropillar attached to the substrate and a rigid tile attached to the elastomeric micropillar, the rigid tiles collectively defining a discontinuous, changeable surface, and the hybrid microstructures further comprising a ferromagnetic material,
wherein the elastomeric micropillars are deflectable under a magnetic field so as to alter an orientation of the rigid tiles, thereby allowing a characteristic of the discontinuous, changeable surface to be manipulated.

US Pat. No. 10,796,830

SINGLE INDUCTOR DUAL OUTPUT CONTROL METHOD

NXP B.V., San Jose, CA (...

1. A power controller, comprising:power stages configured to receive input power and charge an inductor, the power stages including:
output power stages configured to output a first voltage and a second voltage; and
feedback circuits to determine error signals of the first voltage and second voltage;
a first loop configured to determine an amount of energy to be stored in the inductor using the error signals; and
a second loop configured to determine a discharge of the inductor between the first voltage and the second voltage, wherein the second loop determines a moving average of at least one transition point between powering the first voltage and the second voltage.

US Pat. No. 10,796,829

COIL ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A coil electronic component comprising:a body including a plurality of insulating layers and coil patterns disposed on the insulating layers; and
external electrodes formed on an external surface of the body and connected to the coil patterns,
wherein the plurality of insulating layers include a Ni—Cu—Zn based ferrite,
the Ni—Cu—Zn based ferrite has a content of Ni within a range from 5 to 15%, a content of Cu within a range from 5 to 10%, and a content of Zn within a range from 28 to 35%, based on a mole ratio of the Ni—Cu—Zn based ferrite,
an average size of crystal grains of the Ni—Cu—Zn based ferrite is 10 ?m or more and 20 ?m or less, and
the Ni—Cu—Zn based ferrite does not contain Bi.