US Pat. No. 10,483,398

SEMICONDUCTOR DEVICE WITH GATE STACK

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a gate stack over a semiconductor substrate, wherein the gate stack has a work function layer and a metal filling, and tops of the work function layer and the metal filling are at different height levels;
a protection element over the gate stack, wherein a top and a bottom of the protection element have different widths;
a spacer over a side surface of the protection element and a sidewall of the gate stack;
a conductive feature over the semiconductor substrate; and
a conductive contact electrically connected to the conductive feature.

US Pat. No. 10,483,397

FIN FIELD EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A fin field effect transistor, comprising:a semiconductor substrate having a fin structure between two trenches, wherein each of the two trenches has a top portion and a bottom portion, the top portion of each of the two trenches is closer to a top portion of the fin structure than the bottom portion of each of the two trenches;
shallow trench isolations respectively formed in the bottom portions of the two trenches, wherein the top portion of the fin structure is tapered and above the shallow trench isolations;
a gate electrode over the fin structure and the shallow trench isolations, wherein the gate electrode is perpendicular to the fin structure;
a gate dielectric layer along sidewalls of the fin structure; and
a source/drain doped region formed in the fin structure,
wherein each of the shallow trench isolations has a rounded and convex top corner, a rounded and convex bottom corner and a straight side edge,
wherein the rounded and convex top corner of each of the shallow trench isolations is close to and separated from the fin structure,
wherein the rounded and convex bottom corner of each of the shallow trench isolations is in contact with the bottom portion of each of the two trenches,
wherein the rounded and convex top corner of each of the shallow trench isolations is directly connected the straight side edge of each of the shallow trench isolations, and the shallow trench isolations are in contact with the fin structure,
wherein the gate dielectric layer has a convex top surface and a concave bottom surface, and an entirety of the gate dielectric layer is disposed at a level between a top surface of the fin structure and the rounded and convex top corner of each of the shallow trench isolations.

US Pat. No. 10,483,396

INTERFACIAL LAYER BETWEEN FIN AND SOURCE/DRAIN REGION

Taiwan Semiconductor Manu...

1. A semiconductor structure comprising:a substrate;
a fin on the substrate, the fin comprising silicon germanium and having recessed portions;
an interfacial layer over the recessed portions of the fin, the interfacial layer having a thickness in a range from about 1 nm to about 4 nm, wherein the interfacial layer encapsulates impurities on a surface of the fin; and
a source/drain region over the interfacial layer, the source/drain region comprising silicon germanium.

US Pat. No. 10,483,395

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method for fabricating semiconductor device, comprising:providing a substrate having a first region and a second region;
forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region;
forming a first liner on the first fin-shaped structure and the second fin-shaped structure;
forming a first buffer layer on the first liner;
removing the first buffer layer on the first region;
forming an insulating layer on the first fin-shaped structure and the second fin-shaped structure; and
performing a curing process to combine the first buffer layer and the insulating layer into one unit while the first liner is on the first fin-shaped structure and the second fin-shaped structure and a width of the first fin-shaped structure is different from a width of the second fin-shaped structure.

US Pat. No. 10,483,394

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a Fin FET device including:
a first fin structure disposed over a substrate;
an isolation insulating layer disposed over the substrate; and
a first source/drain stressor layer made of semiconductor material and disposed over the first fin structure, wherein:
an upper surface of the isolation insulating layer has a valley portion and a peak portion disposed between the valley portion and the first fin structure, and
a height Ha of an interface between the first fin structure and the first source/drain stressor layer measured from the substrate is greater than a height Hb of the valley portion measured from the substrate, and is less than a height Hc of the peak portion measured from the substrate.

US Pat. No. 10,483,393

METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES

STMicroelectronics, Inc.,...

1. A device, comprising:a substrate having a first portion and a second portion extending away from the first portion, the second portion having a first length in a first direction and a first width in a second direction orthogonal to the first direction;
a microfabricated structure on the substrate, the microfabricated structure having a fin including:
the second portion of the substrate;
a strain-inducing layer on the second portion of the substrate, the strain-inducing layer having a second length in the first direction and a second width in the second direction, the first length approximately equal to the second length and the first width approximately equal to the second width; and
a semiconductor layer on the strain-inducing layer.

US Pat. No. 10,483,390

INSULATED GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

FUJI ELECTRIC CO., LTD., ...

1. An insulated gate semiconductor device, comprising:a drift layer of a first conductivity type made of a semiconductor material having a wider bandgap than silicon, a top surface of the semiconductor material having an off-angle;
a base region of a second conductivity type made of said semiconductor material, disposed above the drift layer;
a first high-impurity region of the first conductivity type, embedded in a top of the base region and having a higher impurity density than the drift layer, wherein a trench is provided penetrating the first high-impurity region and the base region;
a gate insulating film disposed on side surfaces and a bottom surface of the trench;
an embedded gate electrode embedded inside the trench, with the gate insulating film being interposed between the trench and the embedded gate electrode;
a second high-impurity region of the first conductivity type made of said semiconductor material, disposed on a bottom surface side of the drift layer;
a gate bottom protection region of the second conductivity type, embedded in the drift layer at a bottom of the trench; and
a base bottom embedded region of the second conductivity type, embedded in the drift layer below the base region separately from the gate bottom protection region, and having a higher impurity density than the base region,
wherein a cross-section of the base bottom embedded region has a trapezoid-shaped portion on at least a bottom side of the base bottom embedded region, an upper base and a lower base of the trapezoid are parallel, and a virtual straight line that connects a midpoint of the upper base and a midpoint of the lower base is tilted from a line normal to the top surface of the drift layer towards a direction of the off-angle by a prescribed tilt angle, and
wherein a bottom surface of the base bottom embedded region is deeper than a bottom surface of the gate bottom protection region.

US Pat. No. 10,483,389

SILICON CARBIDE SEMICONDUCTOR DEVICE

HESTIA POWER INC., Hsinc...

12. A silicon carbide (SiC) semiconductor device, comprising:an n-type substrate, having a first doping concentration;
an n-type drift layer, disposed on the substrate, having a second doping concentration less than the first doping concentration;
a plurality of first doped regions and a plurality of second doped regions, disposed at the n-type drift layer, each of the first doped regions comprising a first p-well, a heavily doped n-type (n+) region located in the first p-well, and a first heavily doped p-type (p+) region located in the first p-well and surrounded by the heavily doped n+ region, each of the second doped regions comprising at least one sub-doped region, wherein each of a plurality of first junction field effect transistor (JFET) regions having a third doping concentration formed between each of the first doped regions and the second doped regions, and each of a plurality of second junction field effect transistor (JFET) regions having a fourth doping concentration formed between each of the sub-doped regions or enclosed by the sub-doped region;
a gate dielectric layer, disposed on the n-type drift layer;
a gate electrode, disposed on the gate dielectric layer;
an inter-layer dielectric layer, disposed on the gate dielectric layer and the gate electrode;
a plurality of source openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the heavily doped n+ region and the first heavily doped p+ region, and the plurality of source openings are separated by the gate electrode and the inter-layer dielectric layer, wherein a top surface of n-type drift layer and a top surface of the heavily doped p+ region are in a same first plane;
a plurality of junction openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the plurality of second JFET regions and the second doped regions, and the plurality of junction openings are separated by the gate electrode and the inter-layer dielectric layer;
a plurality of gate openings, penetrating through the inter-layer dielectric layer to a surface portion of the gate electrode;
a first metal layer, disposed only at a bottom of the source openings, formed an Ohmic contact with the surface portion of the heavily doped n+region and the first heavily doped p+ region;
a second metal layer, comprising a first portion and a second portion, wherein the first portion covers the source openings and the junction openings, is electrically connected to the first metal layer, and forms a Schottky contact with the surface portion of the plurality of second JFET regions, the second portion covers the gate openings and is electrically insulated from the first portion, wherein a bottom surface of the first metal layer and a bottom surface of a part of the second metal layer are in a same second plane, and
wherein the third doping concentration is greater than the second doping concentration.

US Pat. No. 10,483,384

TRANSISTOR DEVICE WITH HIGH CURRENT ROBUSTNESS

Infineon Technologies AG,...

1. A transistor device, comprising:a first emitter region of a first doping type, a second emitter region of a second doping type, a body region of the second doping type, a drift region of the first doping type, a field-stop region of the first doping type, and at least one boost structure; and
a gate electrode dielectrically insulated from the body region by a gate dielectric,
wherein the body region is arranged between the first emitter region and the drift region, the field-stop region is arranged between the drift region and the boost structure, and the boost structure is arranged between the field-stop region and the second emitter region,
wherein the at least one boost structure comprises a base region of the first doping type and at least one auxiliary emitter region of the second doping type separated from the second emitter region by the base region,
wherein an overall dopant dose in the drift region and the field-stop region in a current flow direction of the transistor device is higher than a breakthrough charge of a semiconductor material of the drift region and the field-stop region.

US Pat. No. 10,483,381

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A semiconductor device, comprising:a tunnel field-effect transistor comprising:
a first substrate; and
a first electrical element, wherein the first electrical element is formed on one side of the first substrate, wherein the first electrical element comprises:
a first drain region;
a second drain region, wherein the first drain region and the second drain region are opposite to each other and separated by a part of the first substrate;
a first shallow trench isolation region;
a second shallow trench isolation region, wherein the first drain region and the second drain region are disposed between the first shallow trench isolation region and the second shallow trench isolation region;
a planar device comprising:
a second substrate; and
a second electrical element, wherein the second substrate and the first substrate are an integrated structure and form a main substrate, wherein the second electrical element is formed on one side of the second substrate, wherein the second electrical element and the first electrical element are disposed on a same side of the main substrate, and wherein the planar device comprises at least one of a metal oxide semiconductor transistor, a capacitor, or a resistor.

US Pat. No. 10,483,376

METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE

UNISANTIS ELECTRONICS SIN...

1. A method for producing a semiconductor device, the method comprising:depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate;
forming a first hole for forming a gate electrode in the second insulating film;
filling the first hole with a first metal to form the gate electrode;
forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole;
performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film;
forming a gate insulating film on a side surface of the second hole; and
epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.

US Pat. No. 10,483,375

FIN CUT ETCH PROCESS FOR VERTICAL TRANSISTOR DEVICES

International Business Ma...

1. A method for fabricating a semiconductor device including a vertical transistor, comprising:forming a fin structure from a substrate, the fin structure including a fin;
forming a bottom source/drain region on the substrate adjacent to the fin;
etching a longitudinal end portion of the fin to create a gap exposing the substrate;
forming a gate and a top source/drain region; and
forming a contact wrapping around a horizontal portion and a vertical portion of the bottom source/drain region in a region including a location where the longitudinal end portion of the fin was removed by the etching.

US Pat. No. 10,483,364

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A method for manufacturing a semiconductor structure, the method comprising:forming a dielectric layer on at least one gate structure and at least one source drain structure;
forming an opening in the dielectric layer to expose the source drain structure;
forming a protection layer on at least one sidewall of the opening;
forming a conductive plug in the opening, wherein the conductive plug is electrically connected to the source drain structure;
etching back the dielectric layer to expose a sidewall of the protection layer after the forming the conductive plug; and
removing the protection layer after the forming the conductive plug.

US Pat. No. 10,483,357

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate having a drift region of a first conductivity type;
a cathode region formed on a lower surface of the semiconductor substrate;
a diode portion having the cathode region formed on the lower surface of the semiconductor substrate;
a first dummy trench portion provided from an upper surface of the semiconductor substrate to the drift region, including one part provided inside the diode portion and the other part provided outside the diode portion, and provided extending in series from inside the diode portion to outside the diode portion in a predetermined extending direction on the upper surface of the semiconductor substrate; and
a first lead-out portion provided on the upper surface of the semiconductor substrate, and electrically connected to the first dummy trench portion outside the diode portion.

US Pat. No. 10,483,356

POWER SEMICONDUCTOR DEVICE WITH OPTIMIZED FIELD-PLATE DESIGN

SILICONIX INCORPORATED, ...

1. A semiconductor device comprising:a source bonding pad;
a drain bonding pad;
a drain metallization structure comprising a drain field plate; and
a source metallization structure comprising a source field plate;
at least a portion of the source bonding pad being situated directly over an active area of the device in a first area of the device;
at least a portion of the drain bonding pad being situated directly over an active area of the device in a second area of the device;
wherein the source field plate has a first dimension positioned in the first area, and a second dimension different from the first dimension positioned in an area of the device other than the first area; and
wherein the drain field plate has a first dimension positioned in the second area, and a second dimension different from the first dimension positioned in an area of the device other than the second area.

US Pat. No. 10,483,350

SEMICONDUCTOR DEVICE

HOSEI UNIVERSITY, Tokyo ...

1. A semiconductor device, comprising:a semiconductor member having a mesa structure in which a second semiconductor layer having one of a p-type conductivity type and an n-type conductivity type is laminated on a first semiconductor layer having the other one of the p-type conductivity type and the n-type conductivity type, so that the second semiconductor layer is exposed on an upper surface of the mesa structure, a pn junction interface is exposed on a side surface of the mesa structure, and the first semiconductor layer is exposed on an outside upper surface of the mesa structure;
an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure;
a first electrode electrically connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and
a second electrode electrically connected to the first semiconductor layer on a lower surface of the first semiconductor layer,
wherein the insulating film is formed including a first insulating layer and a second insulating layer,
the first insulating layer is disposed so as to cover a corner portion where the side surface of the mesa structure and the outside upper surface of the mesa structure are connected to each other,
the second insulating layer is disposed so as to cover the pn junction interface exposed on the side surface of the mesa structure, or disposed so as to cover an area directly under an electrode end in a state of constituting an entire thickness of the insulating film directly under the electrode end of the first electrode,
a relative dielectric constant of the second insulating layer is equal to or larger than a relative dielectric constant of the semiconductor member, and
the relative dielectric constant of the first insulating layer is smaller than the relative dielectric constant of the second insulating layer, and
wherein the first insulating layer is in direct contact with the corner portion,
the second insulating layer is in direct contact with the pn junction interface, or in direct contact with the semiconductor member at an area directly under the electrode end of the first electrode, and
the second insulating layer is not in contact with the corner portion.

US Pat. No. 10,483,348

SEMICONDUCTOR DEVICE

SOCIONEXT, INC., Kanagaw...

1. A semiconductor device comprising:a substrate;
a first transistor which includes a first impurity region of a first conductivity type formed in the substrate, and which includes a second impurity region of the first conductivity type formed in the substrate;
a first guard ring of a second conductivity type different from the first conductivity type, formed in the substrate, the first guard ring surrounding the first transistor in a plan view;
a first wiring formed on the first guard ring and electrically connected to the first guard ring; and
a ground wiring formed on the first wiring, the ground wiring being electrically connected to the first wiring and the second impurity region,
wherein
the first transistor includes a first part and a second part which are respectively arranged in a first direction in a plan view,
the first part of the first transistor is separated with a first distance from the first guard ring in a second direction which is perpendicular to the first direction in a plan view,
the second part of the first transistor is separated with a second distance from the first guard ring in the second direction in a plan view,
the second distance is shorter than the first distance,
the first part is separated from the ground wiring in a plan view, and
the second part is overlapped with the ground wiring in a plan view.

US Pat. No. 10,483,347

SEMICONDUCTOR DEVICE, STARTER CIRCUIT, AND SWITCHED-MODE POWER-SUPPLY CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate of a first conductivity type;
a drift layer of a second conductivity type provided on the semiconductor substrate;
a drain region of the second conductivity type in contact with the drift layer to be provided on the semiconductor substrate at a center of the drift layer;
a gate region of the first conductivity type provided on the semiconductor substrate in an outer side of the drift layer, the gate region including U-shaped first and second concave patterns in a planar pattern, each of which having entrances of the U-shapes located with equal distances from the drain region, the bottoms of the U-shapes protruding toward an outer side of the planar pattern;
source regions of the second conductivity type provided in an inner side of the first concave patterns, each of the source regions contacts with the drift layer and the gate region; and
surge-current guiding-regions of the second conductivity type provided in an inner side of the second concave patterns, each of the surge-current guiding-regions contacts with the drift layer and the gate region.

US Pat. No. 10,483,344

FABRICATION OF A MIM CAPACITOR STRUCTURE WITH VIA ETCH CONTROL WITH INTEGRATED MASKLESS ETCH TUNING LAYERS

International Business Ma...

1. A method for fabricating a semiconductor device, comprising:forming a first plate of a metal-insulator-metal (MIM) capacitor structure and a first etch tuning layer adjacent to the first plate on a base structure, the base structure including contacts formed within a base layer;
forming a first dielectric layer on the first plate and the first etch tuning layer;
forming a second plate of the MIM capacitor structure and a second etch tuning layer adjacent to the second plate on the first dielectric layer;
forming a second dielectric layer on the second plate and the second etch tuning layer; and
forming a third plate of the MIM capacitor structure and a third etch tuning layer adjacent to the third plate on the second dielectric layer, wherein the etch tuning layers include materials for balancing etch depth during formation of a plurality of vias.

US Pat. No. 10,483,340

TRANSISTOR ARRAY PANEL, INCLUDING A SOURCE CONNECTING MEMBER AND A DRAIN CONNECTING MEMBER MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A transistor display panel comprising:a substrate;
a first transistor disposed on the substrate; and
a pixel electrode connected to the first transistor,
wherein the first transistor includes:
a first semiconductor on the substrate,
a first insulating layer covering the first semiconductor,
a first gate electrode on the first insulating layer overlapping the first semiconductor,
a first connecting member disposed on the first insulating layer and connected to the first semiconductor, the first connecting member including a first source connecting member and a first drain connecting member,
a second insulating layer covering the first gate electrode, the first source connecting member and the first drain connecting member, and
a first source electrode and a first drain electrode disposed on the second insulating layer,
wherein the first gate electrode includes at least three layers and the first connecting member includes at least two layers,
wherein the first source electrode is connected to the first source connecting member,
wherein the first semiconductor includes a first channel, and a first source region and a first drain region disposed at respective sides of the first channel, and
wherein the first source region and the first drain region are respectively connected to the first source connecting member and the first drain connecting member.

US Pat. No. 10,483,338

ORGANIC LIGHT-EMITTING DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE

SHANGHAI TIANMA MICRO-ELE...

1. An organic light-emitting display panel, comprising:an array substrate;
a plurality of pixel driving circuits disposed on the array substrate;
a planarization layer disposed on the array substrate, wherein a plurality of connection holes corresponding to the plurality of pixel driving circuits is provided in the planarization layer;
a pixel defining layer disposed on the planarization layer, wherein the pixel defining layer comprises a plurality of pixel apertures; and
a plurality of organic light-emitting devices, wherein at least two organic light-emitting devices of the plurality of organic light-emitting devices for emitting a same color are disposed in each of the plurality of pixel apertures, each of the plurality of organic light-emitting devices comprises an anode and at least one organic light-emitting function layer, and anodes of the plurality of organic light-emitting devices are electrically connected to the plurality of pixel driving circuits through the plurality of connection holes in one-to-one correspondence,
wherein a plurality of grooves is provided in the planarization layer, wherein one groove of the plurality of grooves is disposed between two adjacent organic light-emitting devices of the plurality of organic light-emitting devices disposed in a respective one of the plurality of the pixel apertures; the plurality of grooves is filled with a hydrophobic layer having a trench, an extending direction of the trench in each groove of the plurality of grooves is the same as an extending direction of said groove.

US Pat. No. 10,483,335

ORGANIC LIGHT EMITTING DISPLAY DEVICE HAVING PIXEL DEFINING LAYER

LG Display Co., Ltd., Se...

1. An organic light emitting display device, comprising:a first electrode in an emission area of a subpixel;
a pixel defining layer surrounding the first electrode in a non-emissive area of the subpixel;
a light emitting layer on the first electrode;
a second electrode on the light emitting layer;
a first encapsulation layer on the second electrode; and
a color filter on the first encapsulation layer in the subpixel,
wherein the pixel defining layer includes:
a first pixel defining layer;
a second pixel defining layer on the first pixel defining layer, a width of the second pixel defining layer at any height thereof is wider than a width of the first pixel defining layer at any height thereof;
a first metal layer on the second pixel defining layer; and
a third pixel defining layer on the first metal layer;
wherein a thickness of the third pixel defining layer is thicker than a thickness of each of the first pixel defining layer, the second pixel defining layer, and the first metal layer.

US Pat. No. 10,483,332

FLEXIBLE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...

1. A flexible display device, comprising:a first base having an active area and a dead area surrounding the active area, the first base including a pad portion provided in the dead area on one side of the active area;
an array in the active area of the first base;
an encapsulation layer configured to cover the array;
a second base opposite to the first base;
a touch electrode array on the second base to be opposite to the active area of the first base;
a plurality of path holes in the dead area on at least one of the other sides of the active area on which the pad portion is not located;
an inorganic dummy pattern spaced apart from the encapsulation layer among the path holes in a plane; and
an adhesive layer between the encapsulation layer and the touch electrode array to fill the path holes,
wherein the adhesive layer fills the path holes outside an edge of the encapsulation layer to surround the array and the touch electrode array.

US Pat. No. 10,483,328

ORGANIC LIGHT-EMITTING ELEMENT AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE

Duk San Neolux Co., Ltd, ...

1. An organic light emitting element having first, second, and third sub-pixels with different colors on a substrate, the organic light emitting element comprising:first electrodes disposed on the substrate;
a second electrode disposed on the substrate to face the first electrodes;
organic light emitting layers disposed between the first electrodes and the second electrode, the organic light emitting layers comprising a first organic light emitting layer disposed in the first sub-pixel, a second organic light emitting layer disposed in the second sub-pixel, and a third organic light emitting layer disposed in the third sub-pixel;
a hole transport layer disposed between the first electrodes and the organic light emitting layers; and
auxiliary light emitting layers disposed between the hole transport layer and the organic light emitting layers, the auxiliary light emitting layers comprising: a first auxiliary light emitting layer commonly disposed in the first sub-pixel, the second sub-pixel, and the third sub-pixel; a second auxiliary light emitting layer disposed in the second sub-pixel between the first auxiliary light emitting layer and the second organic light emitting layer, and a third auxiliary light emitting layer disposed in the third sub-pixel between the first auxiliary light emitting layer and the third light emitting layer,
wherein the first sub-pixel comprises the first auxiliary light emitting layer disposed between the hole transport layer and the first organic light emitting layer,
wherein the second sub-pixel comprises the first auxiliary light emitting layer and the second auxiliary light emitting layer between the hole transport layer and the second organic light emitting layer,
wherein the third sub-pixel comprises the first auxiliary light emitting layer and the third auxiliary light emitting layer between the hole transport layer and the third organic light emitting layer, and
wherein the highest occupied molecular orbital (HOMO) level of the first auxiliary light emitting layer is larger than the HOMO level of the hole transport layer, and smaller than the HOMO level of the second auxiliary light emitting layer and the third auxiliary light emitting layer,
wherein the first auxiliary light emitting layer, the second auxiliary light emitting layer, and the third auxiliary light emitting layer are formed of a hole transporting material.

US Pat. No. 10,483,324

3D VERTICAL MEMORY ARRAY CELL STRUCTURES AND PROCESSES

1. A method for forming a vertical memory structure, comprising:forming a layer stack comprising word line layers separated by insulator layers;
forming an opening through the layer stack to expose internal surfaces of the word line layers;
depositing a selector material directly on the internal surfaces of the word line layers, wherein the depositing forms segments of the selector material, and wherein each segment is deposited on a corresponding internal surface of a respective word line layer;
depositing a memory material directly on the selector material; and
depositing bit line material directly on the memory material.

US Pat. No. 10,483,322

MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A memory device, comprising:a plurality of transistors;
a first inter-layer dielectric layer over the transistors;
a plurality of first conductive features embedded in the first inter-layer dielectric layer;
a plurality of memory structures respectively over the first conductive features, wherein each of the memory structures has a top electrode, a bottom electrode coupled electrically to a respective one of the first conductive features, and a resistive material layer sandwiched between the top and bottom electrodes;
a filler in between the memory structures; and
a second inter-layer dielectric layer over the filler and the memory structures, the second inter-layer dielectric layer and the filler forming an interface, the interface extending from one of the memory structures to another of the memory structures, wherein the second inter-layer dielectric layer has a first portion over the filler and the memory structures and a second portion around the first portion, and a top surface of the first portion of the second inter-layer dielectric layer is higher than a top surface of the second portion of the second inter-layer dielectric layer.

US Pat. No. 10,483,318

SOLID STATE LIGHTING DEVICES WITH OPPOSING EMISSION DIRECTIONS

CREE, INC., Durham, NC (...

1. A solid-state lighting device comprising:a primary light-extraction face and a secondary light-extraction face that generally opposes the primary light-extraction face;
a plurality of light-emitting diodes (LEDs) supported by a light-transmissive submount;
at least one light-segregation element positioned between different LEDs of the plurality of LEDs proximate to the primary light-extraction face; and
at least one lumiphoric material arranged between different LEDs of the plurality of LEDs registered with the at least one light-segregation element, wherein the at least one lumiphoric material is arranged between the at least one light-segregation element and the secondary light-extraction face.

US Pat. No. 10,483,316

FABRICATION AND OPERATION OF MULTI-FUNCTION FLEXIBLE RADIATION DETECTION SYSTEMS

mPower Technology, Inc., ...

1. A radiation detector comprising:an array of singulated microscale semiconductor sensors disposed on a flexible substrate; and
at least one type of conversion layer;
wherein said conversion layer is sufficiently thin to enable the detector to flex in accordance with said substrate;
wherein the radiation detector is formable into an arbitrary three-dimensional shape; and
wherein the radiation detector comprises a rigid backer to maintain said shape of the radiation detector.

US Pat. No. 10,483,311

SOLID-STATE IMAGE PICKUP DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGE PICKUP DEVICE, AND IMAGE PICKUP DEVICE

CANON KABUSHIKI KAISHA, ...

1. A solid-state image pickup device, comprising:a semiconductor substrate including
a first photoelectric conversion portion having a first semiconductor region of a first conductivity type that collects signal charges,
a second photoelectric conversion portion having a second semiconductor region of the first conductivity type that collects signal charges, and
a third semiconductor region of a second conductivity type different from the first conductivity type,
wherein the third semiconductor region is arranged between the first semiconductor region and the second semiconductor region in plan view with respect to a first surface of the semiconductor substrate, and
an impurity concentration of the third semiconductor region has a local minimum value and an impurity concentration of the first semiconductor region has a local maximum value in a depth direction from the first surface to a second surface opposite to the first surface, and a depth range from a position 0.5 ?m shallower than a position indicating the local minimum value to a position 0.5 ?m deeper than the position indicating the local minimum value and a depth range from a position 0.5 ?m shallower than a position indicating the local maximum value to a position 0.5 ?m deeper than the position indicating the local maximum value are overlapped with each other.

US Pat. No. 10,483,307

IMAGING DEVICE

CANON KABUSHIKI KAISHA, ...

1. An imaging device comprising:a substrate;
a pixel array in which a plurality of pixels are arranged in a two-dimensional manner on the substrate, wherein each of the pixels includes a photoelectric conversion unit configured to accumulate charges generated from an incident light, a charge holding unit configured to hold the charges transferred from the photoelectric conversion unit, and an amplification unit having an input node that receives the charges transferred from the charge holding unit; and
a light-shielding portion arranged to cover at least the charge holding unit,
wherein the photoelectric conversion unit and the charge holding unit included in one of the pixels are aligned in a first direction in a top view from a direction orthogonal to the substrate,
wherein a plurality of the charge holding units of the plurality of the pixels that are adjacent to each other are aligned in a second direction intersecting the first direction in the top view, and
wherein the light-shielding portion extends in the second direction and over the plurality of the charge holding units, and covers a region between the plurality of the charge holding units,
wherein each of the pixels further includes a plurality of contacts that connect electrodes provided to the substrate and a wiring layer formed above the substrate,
wherein the plurality of contacts are formed in a region between the plurality of the charge holding units aligned in the first direction in the top view, and
wherein the light-shielding portion includes a part extending in the first direction and provided between the photoelectric conversion unit and the plurality of contacts.

US Pat. No. 10,483,297

ENERGY HARVESTING DEVICES AND METHOD OF FABRICATION THEREOF

Baupil Photonoics, Inc., ...

1. A thermal energy harvester, comprising:a substrate;
a buffer layer;
a first electrode;
a second electrode;
an absorption layer electrically connected between the first and second electrodes comprising,
a first material;
a second material of a different type that the first material; and
a third material of a different type than the second material;wherein at least one of the first material, the second material, and the third materials are selected from the group consisting of InSb, InAs, GaSb, and PbTe, or a combination thereof, wherein when GaSb is selected, at least one of the first material, the second material, or the third material is selected from the group consisting of InSb, GaAs, InP, GaN, AlN, InAs, and PbTe, or a combination thereof, wherein the first, the second, and the third materials are in a p-n or pin junction with each other in the absorption layer comprises two or more p-n or p-i-n junctions comprising three-dimensional-structures, wherein the two or more p-n or pin junctions are in series increasing the open circuit voltage, and wherein the two or more p-n or p-i-n junctions comprising cutoff wavelength between 2 ?m to 40 ?m.

US Pat. No. 10,483,294

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. An array substrate, comprising a gate electrode layer, an active layer, and a source-drain electrode layer that are disposed on a substrate,wherein the substrate comprises a storage capacitance region thereon, in the storage capacitance region, projections of the gate electrode layer and the active layer on the substrate are at least partially overlapped, and projections of the active layer and the source-drain electrode layer on the substrate are at least partially overlapped,
wherein the array substrate further comprises a gate insulation layer between the gate electrode layer and the active layer and an etch-stopper layer between the active layer and the source-drain electrode layer,
wherein the etch-stopper layer is an insulating layer, and
wherein, in the storage capacitance region, the gate electrode layer and the active layer are spatially separated by the gate insulation layer so as to form a capacitor between them, and the active layer and the source-drain electrode layer are spatially separated by the etch-stopper layer so as to form another capacitor between them,
wherein the gate electrode layer comprises a portion in the storage capacitance region, the gate insulation layer comprises a portion in the storage capacitance region, the active layer comprises a portion in the storage capacitance region, the etch-stopper layer comprises a portion in the storage capacitance region, and the source-drain electrode layer comprises a portion in the storage capacitance region,
wherein the substrate further comprises a thin film transistor region, and a thickness of the gate insulation layer formed in the storage capacitance region is smaller than a thickness of the gate insulation layer formed in the thin film transistor region,
wherein the gate electrode layer at a contact hole in the gate insulation layer is in contact with the source-drain electrode layer.

US Pat. No. 10,483,292

ARRAY SUBSTRATE AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a plurality of signal lines;
a plurality of secondary discharging lines arranged substantially parallel to each other, each of the plurality of secondary discharging lines being arranged to cross the plurality of signal lines;
a plurality of first electrostatic discharging units arranged in one-to-one correspondence with the plurality of signal lines and arranged at an identical side of an entirety of the plurality of secondary discharging lines; and
a primary discharging line connected to the plurality of secondary discharging lines,
wherein a first end of each of the plurality of first electrostatic discharging units is connected to a corresponding signal line of the plurality of signal lines, and a second end of the each of the plurality of first electrostatic discharging units is connected to one of the plurality of secondary discharging lines,
each first electrostatic discharging unit of the plurality of first electrostatic discharging units comprises a first thin film transistor (TFT), a second TFT, and a third TFT;
a gate electrode and a source electrode of the first TFT are short-circuited and connected to one of the plurality of signal lines corresponding to the each first electrostatic discharging unit, and a drain electrode of the first TFT is connected to a source electrode of the second TFT and a gate electrode of the third TFT;
a gate electrode and a drain electrode of the second TFT are short-circuited and connected to the one of the plurality secondary discharging lines corresponding to the each first electrostatic discharging unit;
a source electrode of the third TFT is directly connected to the one of the plurality of signal lines, and a drain electrode of the third TFT is directly connected to the one of the plurality of secondary discharging lines; and
an extension portion of the one of the plurality of signal line corresponding to the each first electrostatic discharging unit is formed into the source electrode of the first TFT and the source electrode of the third TFT, the source electrode of the first TFT is connected to the gate electrode of the first TFT through a first via-hole, an active region of the first TFT is formed above the gate electrode of the first TFT, and the source electrode and the drain electrode of the first TFT are in direct contact with the active region of the first TFT so as to form a source region and a drain region of the first TFT.

US Pat. No. 10,483,288

LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE USING THE SAME

Semiconductor Energy Labo...

1. A light-emitting device comprising:a substrate;
an oxide semiconductor over the substrate, the oxide semiconductor comprising indium, zinc, and gallium;
a gate electrode over the oxide semiconductor;
a first insulating film over the gate electrode, the first insulating film comprising an inorganic insulating material;
a source electrode and a drain electrode over the first insulating film, the source electrode and the drain electrode each comprising a region in contact with the oxide semiconductor;
a color filter over the first insulating film;
a light-emitting element over the color filter, the light-emitting element electrically connected to one of the source electrode and the drain electrode; and
an organic resin over the light-emitting element,
wherein the color filter is positioned between the first insulating film and the light-emitting element,
wherein the color filter comprises a region overlapping with the light-emitting element,
wherein the color filter does not overlap with the oxide semiconductor and the gate electrode,
wherein the light-emitting element comprises:
a first electrode;
a second electrode over the first electrode;
a charge generation layer between the first electrode and the second electrode;
a first light-emitting layer between the first electrode and the charge generation layer;
a second light-emitting layer between the charge generation layer and the second electrode; and
a third light-emitting layer between the charge generation layer and the second electrode,
wherein the first light-emitting layer comprises a blue-emissive fluorescent substance,
wherein the second light-emitting layer comprises a first phosphorescent substance,
wherein the first phosphorescent substance is a red-emissive phosphorescent substance,
wherein the third light-emitting layer comprises a second phosphorescent substance and overlaps with the second light-emitting layer, and
wherein the first electrode is positioned over the one of the source electrode and the drain electrode.

US Pat. No. 10,483,287

DOUBLE GATE, FLEXIBLE THIN-FILM TRANSISTOR (TFT) COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (MOS) (CMOS) CIRCUITS AND RELATED FABRICATION METHODS

QUALCOMM Incorporated, S...

1. A complementary metal-oxide semiconductor (CMOS) circuit, comprising:a flexible substrate;
at least one P-type Field-Effect Transistor (FET) (PFET) formed on a first surface of the flexible substrate, each of the at least one PFET comprising:
a first gate disposed on the first surface of the flexible substrate;
a P-type thin-film semiconductor structure disposed over the first gate in a first axis direction, the P-type thin-film semiconductor structure comprising a first source/drain region, a second source/drain region, and a first channel region between the first and second source/drain regions; and
a second gate disposed over the P-type thin-film semiconductor structure in the first axis direction opposite to the first gate;
at least one N-type FET (NFET) formed on the first surface of the flexible substrate, each of the at least one NFET comprising:
a third gate disposed on the first surface of the flexible substrate;
an N-type thin-film semiconductor structure disposed over the third gate in the first axis direction, the N-type thin-film semiconductor structure comprising a third source/drain region, a fourth source/drain region, and a second channel region between the third and fourth source/drain regions; and
a fourth gate disposed over the N-type thin-film semiconductor structure in the first axis direction opposite to the third gate; and
at least one metal contact electrically coupling the second source/drain region of the at least one PFET and the third source/drain region of the at least one NFET.

US Pat. No. 10,483,286

ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY, THIN FILM TRANSISTOR, AND MANUFACTURING METHOD OF ARRAY SUBSTRATE

Mitsubishi Electric Corpo...

1. An array substrate comprising a first thin film transistor and a second thin film transistor on a substrate, whereinthe first thin film transistor includes
a first gate electrode provided on the substrate,
a gate insulating film provided covering the first gate electrode,
a first oxide semiconductor layer and a second oxide semiconductor layer provided on the gate insulating film while overlapping the first gate electrode in plan view, with a first separation portion separating the first oxide semiconductor layer and the second oxide semiconductor layer from each other,
a first source electrode and a first drain electrode provided extending from above the first oxide semiconductor layer and above the second oxide semiconductor layer, respectively, onto the gate insulating film while overlapping the first oxide semiconductor layer or the second oxide semiconductor layer in plan view, with a second separation portion, greater than the first separation portion, separating the first source electrode and the first drain electrode from each other, and
an amorphous silicon layer provided extending on the first separation portion on the gate insulating film, the second separation portion, a part of the first source electrode, and a part of the first drain electrode, and
the second thin film transistor includes
a second gate electrode provided on the substrate,
the gate insulating film provided covering the second gate electrode,
a third oxide semiconductor layer provided on the gate insulating film while overlapping the second gate electrode in plan view, and
a second source electrode and a second drain electrode provided extending from above the third oxide semiconductor layer onto the gate insulating film while overlapping the third oxide semiconductor layer in plan view, with a third separation portion separating the second source electrode and the second drain electrode from each other.

US Pat. No. 10,483,285

ELEMENT SUBSTRATE AND DISPLAY DEVICE

Innolux Corporation, Mia...

4. A display device, comprising:an element substrate comprising a substrate and an element layer, wherein the element layer is disposed on the substrate, the element layer comprises a plurality of active elements, the plurality of active elements respectively comprises:
a gate disposed on the substrate;
a gate insulating layer disposed on the substrate and overlapping the gate;
a metal oxide semiconductor layer disposed on the gate insulating layer;
a source and a drain disposed on the metal oxide semiconductor layer,
wherein the metal oxide semiconductor layer has a first portion and a second portion, the source and the drain overlap the first portion, the source and the drain do not overlap the second portion, the first portion has a first thickness, the second portion has a second thickness, the first thickness is greater than the second thickness,
wherein a difference between the first thickness and the second thickness is greater than or equal to 200 ? and less than or equal to 600 ?, and
wherein the source and the drain respectively comprise a first layer and a second layer, the first layer is disposed between the second layer and the metal oxide semiconductor layer, a material of the first layer comprises titanium nitride, a distance is between an edge of the first layer and an edge of the second layer, and the distance is greater than or equal to 0.1 ?m and less than or equal to 0.3 ?m;
an opposing substrate disposed relative to the element substrate; and
a display layer disposed between the element substrate and the opposing substrate.

US Pat. No. 10,483,284

LOGIC SEMICONDUCTOR DEVICE

Korea University Research...

1. A semiconductor device comprising:a plurality of stacked transistors,
wherein:
each of the transistors comprises:
a semiconductor column including a first conductive region of a first conductivity type, a second conductive region of a second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region;
a gate electrode disposed to cover the intrinsic region; and
a gate insulating layer disposed between the gate electrode and the intrinsic region;
wherein not all of the plurality of stacked transistors have a same first conductivity type, and
wherein:
the plurality of stacked transistors include a first transistor disposed at a lower portion and a second transistor disposed above the first transistor,
the first conductivity type of the first transistor is n-type, and
the first conductivity type of the second transistor is p-type.

US Pat. No. 10,483,281

SEMICONDUCTOR MEMORY DEVICE

SK hynix Inc., Gyeonggi-...

1. A method of manufacturing a semiconductor memory device comprising:forming bit lines on a substrate, wherein the substrate includes a cell array region, a word line contact region and a page buffer region;
wherein the page buffer region is coupled to the cell array region through bit lines,
wherein the bit lines include a first bit line and a second bit line, and
wherein the second bit line has a curved structure toward the word line contact region and a curvedness of the second bit line is greater than a curvedness of the first bit line.

US Pat. No. 10,483,276

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, comprising the steps of:forming, over a first surface of a semiconductor substrate located in a region where a first transistor is to be formed, a first gate insulating film having a first oxide film, a first nitride film placed over the first oxide film, and a second oxide film placed over the first nitride film; and
forming a second gate insulating film over the first surface located in a region where a second transistor is to be formed,
wherein the second oxide film includes a first layer and a second layer placed over the first layer,
wherein the first gate insulating film formation step includes a step of forming a second nitride film placed over the first layer, and
wherein the second layer is formed by oxidation of at least a portion of the second nitride film,
wherein the second gate insulating film is formed by thermal oxidation,
wherein the method further comprises forming, over the first surface located in a region where a third transistor is to be formed, a third gate insulating film thinner than the second gate insulating film,
wherein the portion of the second nitride film remains at the time of formation of the second gate insulating film,
wherein the second nitride film oxidized at the time of formation of the second gate insulating film is removed by etching prior to the third gate insulating film formation step, and
wherein the portion of the second nitride film which has remained at the time of formation of the second gate insulating film is oxidized into the second layer at the time of formation of the third gate insulating film.

US Pat. No. 10,483,270

INTEGRATED ASSEMBLIES AND METHODS OF FORMING INTEGRATED ASSEMBLIES

Micron Technology, Inc., ...

1. An integrated assembly, comprising:a first channel structure extending substantially vertically;
a second channel structure extending substantially vertically; each of the first and the second semiconductor channel structures having a first doped channel region interfacing a second doped channel region at a boundary region, the first doped channel regions being differently doped relative to the second doped channel regions; and
a gating structure extending between the first channel structure and the second channel structure and having a first gating region extending along the first channel structure, a second gating region extending along the second channel structure, and an interconnecting region extending laterally between the first and second gating regions, the interconnecting region being vertically narrower than first and second the gating regions.

US Pat. No. 10,483,269

EEPROM DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device comprising:a semiconductor substrate;
a first dielectric layer having a first thickness on the semiconductor substrate;
a first opening having a first width in the first dielectric layer;
a second dielectric layer having a second thickness disposed in a middle region of the first opening; and
a third dielectric layer having a first portion and a second portion disposed on opposite sides of second dielectric layer, the first portion and the second portion having a second width smaller than the first width, and the third dielectric layer having a third thickness smaller than the first thickness and the second thickness.

US Pat. No. 10,483,267

EIGHT-TRANSISTOR STATIC RANDOM-ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A Static Random Access Memory (SRAM) cell, comprising:a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and
a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each other, gate electrodes of the read pull-down transistor, the second pull-down transistor, and the second pull-up transistors being electrically connected to each other,
wherein a first doping concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doping concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.

US Pat. No. 10,483,263

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A manufacturing method for a semiconductor device, comprising:providing a substrate structure, wherein the substrate structure comprises:
a semiconductor substrate;
a single fin protruding from the semiconductor substrate, wherein trenches are formed on sides of the fin;
a pad insulator layer for padding the trenches;
a first insulator layer separately formed from the pad insulator layer and partially filling the trenches, wherein the single fin protrudes from the first insulator layer; and
a second insulator layer covering the single fin;
forming a plurality of pseudo gate structures on the second insulator layer, wherein each pseudo gate structure wraps a part of the single fin, wherein each pseudo gate structure comprises a pseudo gate located on the second insulator layer, wherein the plurality of pseudo gate structures comprises at least a first pseudo gate structure, a second pseudo gate structure, and a third pseudo gate structure that are spaced from each other, and wherein the second pseudo gate structure and the third pseudo gate structure are located at two opposite edge corners of the single fin and the first pseudo gate structure is a only pseudo gate structure disposed between the second pseudo gate structure and the third pseudo gate structure, and a first part of each of the second pseudo gate structure and the third pseudo gate is on and in direct contact with the first insulator layer and a second part of each of the second pseudo gate structure and the third pseudo gate structure is on and in direct contact with the second insulator layer;
forming, above the first insulator layer and the second insulator layer, spacers at two sides of each of the second pseudo gate structure and the third pseudo gate structure, where a bottom face of one of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the first insulator layer whereas a bottom face of another of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the second insulator layer;
etching, after forming the spacers, the second insulator layer and at least a part of the single fin that are not covered by the spacers and the pseudo gates, to form recesses in the single fin; and
forming at least one source or drain in the recesses.

US Pat. No. 10,483,261

INTEGRATED CIRCUIT HAVING CHEMICALLY MODIFIED SPACER SURFACE

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit (IC), comprising:sidewall spacers having a second dielectric material on a first dielectric material, wherein the second dielectric material comprises carbon and silicon and the first dielectric material comprises silicon and another element besides carbon, and wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material,
wherein the transition region has a composition that includes silicon, carbon and the another element besides carbon, and
wherein at a widest point of the sidewall spacers, the transition region is thicker than the second dielectric material.

US Pat. No. 10,483,256

OPTOELECTRONIC SEMICONDUCTOR DEVICE AND APPARATUS WITH AN OPTOELECTRONIC SEMICONDUCTOR DEVICE

OSRAM OPTO SEMICONDUCTORS...

1. An optoelectronic semiconductor device comprising:an emission region comprising a semiconductor layer sequence with a first semiconductor layer, a second semiconductor layer and, arranged between the first semiconductor layer and the second semiconductor layer, an active region configured to generate radiation;
a protection diode region; and
a contact for external electrical contacting of the optoelectronic semiconductor device,
wherein the contact comprises a first contact region electrically conductively connected to the emission region,
wherein the contact comprises a second contact region located at a distance from the first contact region and electrically conductively connected to the protection diode region,
wherein the second contact region is not directly electrically connected to the emission region,
wherein the first contact region and the second contact region are externally electrically contactable by a common end of a single connecting lead,
wherein the single connecting lead is a wire bond connection,
wherein the semiconductor layer sequence is arranged on a carrier,
wherein the first semiconductor layer is electrically conductively connected in the emission region to a first connection layer, and
wherein the first connection layer extends in places between the carrier and the emission region.

US Pat. No. 10,483,245

LIGHT BAR, EDGE-TYPE BACKLIGHT MODULE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A light bar, comprising: a circuit board and an integrated light emitting body arranged on the circuit board,wherein the integrated light emitting body comprises a package and a plurality of light sources, and the package is configured to package the plurality of light sources,
wherein a light emitting surface of the integrated light emitting body is perpendicular to a surface of the circuit board on which the integrated light emitting body is mounted, a distance between the light emitting surface and an edge of the surface of the circuit beard on which the integrated light emitting body is mounted, close to the light emitting surface and parallel to the light emitting surface is W1, and 0.3 mm?W1?1.0 mm.

US Pat. No. 10,483,244

POWER SEMICONDUCTOR MODULE

ABB Schweiz AG, Baden (C...

1. A power semiconductor module comprising:a first main electrode, a second main electrode, and a control terminal, controllable power semiconductor components arranged between the first main electrode and the second main electrode, wherein each controllable power semiconductor component has a first electrode, a second electrode and a control electrode, and the first electrode of each controllable power semiconductor component is electrically connected to the first main electrode, the second electrode of each controllable power semiconductor component is electrically connected to the second main electrode, and the control electrode of each controllable power semiconductor component is electrically connected to the control terminal, wherein the controllable power semiconductor components are arranged in a plurality of ring arrangements, and
an electrically conductive contact element arranged between the second main electrode of the power semiconductor module and each controllable power semiconductor component, said contact element connecting the second main electrode to the second electrode of the power semiconductor component, wherein the contact element and the power semiconductor component define a current carrying direction that is at least approximately at right angles with respect to the first main electrode,
wherein each ring arrangement of the plurality of ring arrangements has the respective controllable power semiconductor components arranged at least approximately along a first circular line as well as a control conductor track which is arranged on the first main electrode and runs at least approximately along a second circular line, the second circular line of the respective ring arrangement runs concentrically and outside relative to the first circular line of the respective ring arrangement, wherein all of the controllable power semiconductor components are arranged in the plurality of ring arrangements,
wherein the control electrode of each controllable power semiconductor component of the respective ring to the control conductor track of the respective ring arrangement, and the control conductor track of the respective ring arrangement is connected via a further electrical connection to the control terminal, and
wherein the further electrical connection runs at least substantially parallel to the current carrying direction.

US Pat. No. 10,483,237

VERTICALLY STACKED MULTICHIP MODULES

Semiconductor Components ...

1. A circuit assembly apparatus comprising:a first semiconductor die;
a second semiconductor die;
a first substrate including:
a first insulating layer;
a first metal layer disposed on a first side of the first insulating layer, a first side of the first semiconductor die being disposed on and electrically coupled with the first metal layer;
a second metal layer disposed on a second side of the first insulating layer, the second side of the first insulating layer being opposite the first side of the first insulating layer, a first side of the second semiconductor die being disposed on and electrically coupled with the second metal layer; and
a conductive via disposed through the first insulating layer, the conductive via electrically coupling the first metal layer with the second metal layer,
the first metal layer, the conductive via and the second metal layer electrically coupling the first semiconductor die with the second semiconductor die; and
a second substrate having:
a second insulating layer;
a third metal layer disposed on a first side of the second insulating layer, a second side of the first semiconductor die being disposed on and electrically coupled with the third metal layer, the second side of the first semiconductor die being opposite the first side of the first semiconductor die; and
a fourth metal layer disposed on a second side of the second insulating layer, the second side of the second insulating layer being opposite the first side of the second insulating layer, the fourth metal layer being electrically isolated from the third metal layer by the second insulating layer.

US Pat. No. 10,483,236

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a substrate including an insulating layer, a first conductive layer on a first surface of the insulating layer, a second conductive layer on a second surface of the insulating layer that is opposite to the first surface, a third conductive layer extending in a plane direction of the substrate along the first and second surfaces in the insulating layer, and a via extending in a thickness direction of the substrate in the insulating layer; and
a semiconductor chip disposed on a first principal surface of the substrate above the first surface, wherein the substrate further includes:
a planar detection interconnection provided as part of either the first conductive layer or the third conductive layer, wherein the planar detection interconnection is not part of signal interconnections that are used during operation of the semiconductor chip and is not electrically connected to any circuit of the semiconductor chip, and a width of the planar detection interconnection is smaller than a width of the signal interconnections; and
first and second pads to be connected to part of a ball grid array (BGA) or a land grid array (LGA), the first and second pads provided as part of the second conductive layer and electrically connected to the planar detection interconnection through the via.

US Pat. No. 10,483,234

CHIP PACKAGES AND METHODS OF MANUFACTURE THEREOF

Taiwan Semiconductor Manu...

1. A chip package comprising:a plurality of first chips laterally adjacent to each other, each of the plurality of first chips having a plurality of first contact pads on a first surface thereof;
first redistribution layers (RDLs) at the first surfaces of the first chips, wherein the first RDLs are separate from each other, wherein each of the first RDLs contacts the first surface of a respective first chip and is laterally conterminous with the respective first chip;
a second chip attached to the first surfaces of the plurality of first chips, the second chip having a plurality of second contact pads on a first surface thereof, wherein the first surface of the second chip faces away from the plurality of first chips, wherein a first portion of the second chip is disposed within lateral extents of a third chip of the plurality of first chips, and a second portion of the second chip is disposed within lateral extents of a fourth chip of the plurality of first chips;
an adhesive layer between the second chip and the plurality of first chips, the adhesive layer being attached to and contacting a second surface of the second chip opposing the first surface of the second chip, the adhesive layer having a same width as the second chip, a first portion of the adhesive layer being attached to the third chip of the plurality of first chips, and a second portion of the adhesive layer being attached to the fourth chip of the plurality of first chips;
a second RDL coupled to the plurality of second contact pads of the second chip, wherein the second chip is between the second RDL and the plurality of first chips;
a plurality of first conductive pillars laterally separated from the second chip, the plurality of first conductive pillars extending from the second RDL to corresponding ones of a first group of the plurality of first contact pads, the first group disposed outside a width of the second chip; and
a molding compound around the plurality of first chips, the second chip, and the plurality of first conductive pillars.

US Pat. No. 10,483,233

SPLIT BALL GRID ARRAY PAD FOR MULTI-CHIP MODULES

International Business Ma...

1. A multi-chip module, comprising:a substrate containing multiple wiring layers, each wiring layer having multiple wires, first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, wherein the first section is connected by a first wire of the multiple wires to a pad of a first group of the first pads, wherein the non-contiguous second section is connected by a second wire of the multiple wires to a pad of a second group of the first pads, and wherein another pad of the second pads is a conventional pad having a contiguous top surface and a contiguous bottom surface;
a first solder ball in direct physical contact with the contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height in a first direction, and wherein the first direction is perpendicular to the contiguous bottom surface of the conventional pad; and
a second solder ball in direct physical contact with the first section and the non-contiguous second section of the split pad, wherein the second solder ball has a second height in the first direction, and wherein the second height is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging,
wherein a first active component is attached to the first group of the first pads and a second active component is attached to the second group of the first pads.

US Pat. No. 10,483,231

BONDING METHOD OF FIXING AN OBJECT TO A ROUGH SURFACE

Tsinghua University, Bei...

1. A bonding method comprising:placing a sheet structure on a substrate surface of a substrate, wherein a surface roughness of the substrate surface is larger than 1.0 micrometer; the sheet structure comprises a first surface and a second surface opposite to the first surface, the first surface is in direct contact with the substrate surface, and a surface roughness of the second surface is less than or equal to 1.0 micrometer;
laying a carbon nanotube structure on the second surface, wherein the carbon nanotube structure comprises a first portion, a second portion, and a third portion, the first portion and the second portion are connected together by the third portion, the first portion and the second portion extend out of the second surface and are in direct contact with the substrate surface, the third portion is in direct contact with the sheet structure; the carbon nanotube structure comprises a super-aligned carbon nanotube film, the super-aligned carbon nanotube film comprises a plurality of carbon nanotubes, the plurality of carbon nanotubes extends substantially along a same direction, and an extending direction of the plurality of carbon nanotubes is substantially parallel to the second surface;
adding an organic solvent to the first portion and the second portion, to fix the sheet structure on the substrate surface only by the carbon nanotube structure;
laying an object on and in direct contact with the third portion, wherein the carbon nanotube structure is located between the sheet structure and the object, and a surface of the object being in direct contact with the third portion has a surface roughness less than or equal to 1.0 micrometer; and
applying a pressure to the object to make the object bonded to the substrate surface and forming a structure comprising the substrate, the sheet structure, the carbon nanotube structure and the object.

US Pat. No. 10,483,226

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

9. A method of forming a semiconductor device, comprising:providing a first substrate having at least two chip regions separated by an insulating deep trench, wherein the first substrate has, in each chip region, a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump;
forming a first insulating layer over the metal bumps and the passivation stacks;
patterning the first insulating layer to form a first opening pattern and a second opening pattern therein, wherein a bottom of the first opening pattern and a bottom of the second opening pattern are at different height levels;
providing a second substrate having a second insulating layer thereon;
bonding the second substrate to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer; and
removing the first insulating layer and portions of the passivation stacks by flowing an etch gas from the insulating deep trench.

US Pat. No. 10,483,225

PACKAGING ASSEMBLY AND METHOD OF MAKING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A packaging assembly, comprising:a semiconductor device comprising:
a conductive pad having a first width,
a passivation layer over the conductive pad, wherein the passivation layer directly contacts the conductive pad,
a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad,
an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width,
a conductive pillar on the UBM layer, and
a cap layer over the conductive pillar, wherein the cap layer exposes sidewalls of the UBM layer;
a substrate comprising:
a conductive region, and
a mask layer overlying the substrate and exposing a portion of the conductive region; and
a joint solder structure between the conductive pillar and the conductive region.

US Pat. No. 10,483,224

SEMICONDUCTOR CHIP

Samsung Electronics Co., ...

1. A semiconductor chip comprising:a semiconductor substrate including a bump region, a non-bump region, and a dummy region between the bump region and the non-bump region;
a dummy pattern on the dummy region;
a bump on the bump region, the non-bump region having no bump; and
a passivation layer on the bump region, the dummy region, and the non-bump region of the semiconductor substrate,
a thickness of the passivation layer at the bump region being thicker than a thickness of the passivation layer at the non-bump region,
the passivation layer covering the dummy pattern and insulating the dummy pattern, and
the passivation layer including a step between the bump region and the non-bump region, the step defined by an upper surface of the passivation layer at a portion of the passivation layer that protrudes upward over a boundary between the dummy region and the non-bump region.

US Pat. No. 10,483,216

POWER MODULE AND FABRICATION METHOD FOR THE SAME

ROHM CO., LTD., Kyoto (J...

1. A power module comprising:a substrate;
a first electrode pattern, a second electrode pattern, a first signal electrode pattern, and a second signal electrode pattern respectively disposed on the substrate;
a semiconductor device disposed on a first surface of the second electrode pattern, the first surface being opposite to a second surface of the second electrode pattern on which the substrate is disposed; and
a leadframe bonded to an upper surface of the semiconductor device, wherein
the leadframe is divided into a plurality of leadframes, wherein
the leadframe divided into the plurality of frames comprises:
a first leadframe configured to conduct a principal current, the first leadframe being bonded to the first electrode pattern and the upper surface of the semiconductor device, and
a second leadframe electrically insulated from the first leadframe, the power module further comprising:
a first bonding wire connecting between the first leadframe and the first signal electrode pattern; and
a second bonding wire connecting between the second leadframe and the second signal electrode pattern.

US Pat. No. 10,483,211

FAN-OUT PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

MediaTek Inc., Hsin-Chu ...

1. A semiconductor package structure, comprising:a first semiconductor package, comprising:
a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto;
two electronic components respectively disposed on and electrically coupled to the first and second surface of the first RDL structure;
a first semiconductor die disposed on and electrically coupled to the first surface of the first RDL structure;
a first molding compound disposed on the first surface of the first RDL structure and surrounding the first semiconductor die;
a plurality of screen printed solder balls embedded in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure;
wherein the first molding compound comprises a plurality of openings to correspondingly expose the plurality of screen printed solder balls;
wherein the semiconductor package structure further comprises a plurality of first conductive structures that fill the plurality of openings and are in contact with the plurality of screen printed solder balls; and
wherein the semiconductor package structure further comprises a second semiconductor package coupled to the first semiconductor package by the plurality of first conductive structures, the second semiconductor package being spaced within 50 microns of the first semiconductor package.

US Pat. No. 10,483,209

IMPEDANCE CONTROLLED ELECTRICAL INTERCONNECTION EMPLOYING META-MATERIALS

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a plurality of layers to be secured to provide electrical interconnection between a plurality of first bond pads of a first device and a plurality of second bond pads of a second device, wherein the plurality of layers includes:
a first conductor layer arranged to extend continuously along a portion of a length of the first device and the second device, such that the first conductor layer physically contacts the plurality of first bond pads of the first device and the plurality of second bond pads of the second device when secured;
a second conductor layer disposed over the first conductor layer, wherein the second conductor layer includes a plurality of electrically independent conductors arranged to span a length that is about the portion of the length of the first device and the second device when secured; and
a third conductor layer disposed over the second conductor layer, such that the second conductor layer is disposed between the first conductor layer and the third conductor layer, wherein the third conductor layer is arranged to extend continuously along the portion of the length of the first device and the second device when secured.

US Pat. No. 10,483,208

INTERCONNECTION STRUCTURE, FABRICATING METHOD THEREOF, AND SEMICONDUCTOR DEVICE USING THE SAME

Taiwan Semiconductor Manu...

1. A device comprising:a multi-gate transistor, the multi-gate transistor including an epitaxial source/drain region;
a dielectric layer overlying the epitaxial source/drain region;
a contact extending through an opening in the dielectric layer and electrically contacting the epitaxial source/drain region, the contact including:
a silicide layer contacting the epitaxial source/drain region, wherein a Si concentration of the silicide is varied along a height of the silicide;
a barrier layer contacting the silicide layer;
a metal layer contacting the barrier layer and contacting sidewalls of the opening in the dielectric layer, wherein the silicide layer is a silicide of the epitaxial source/drain region and the metal layer; and
a conductor contacting the barrier layer, wherein the barrier layer extends between and separates the conductor and the silicide layer.

US Pat. No. 10,483,207

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a first semiconductor region of a first conductivity type;
a stacked body provided on the first semiconductor region, the stacked body including a plurality of electrode layers stacked with an insulating body interposed, the stacked body including a first stacked portion and a second stacked portion, the plurality of electrode layers of the second stacked portion including a plurality of terrace portions arranged in a staircase configuration with a level difference in a first direction;
a first columnar portion extending through the first stacked portion in a stacking direction of the stacked body and including a first semiconductor body contacting the first semiconductor region;
an insulating layer provided on the plurality of terrace portions;
a plurality of contact portions extending through the insulating layer in the stacking direction and contacting the plurality of terrace portions;
a second columnar portion extending through the insulating layer and through the second stacked portion in the stacking direction, and including a second semiconductor body contacting the first semiconductor region; and
a first insulating portion dividing the first semiconductor region in the first direction, the first insulating portion provided under a boundary portion between the first stacked portion and the second stacked portion.

US Pat. No. 10,483,204

LOGIC CELL STRUCTURE WITH INTERCONNECTION DESIGN AND CONFIGURATION

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:a semiconductor substrate;
a plurality of field-effect transistors (FETs) disposed on the semiconductor substrate, wherein the FETs include gates with elongated shape oriented in a first direction;
a first metal layer disposed over the gates, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction;
a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction; and
a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction, wherein
the first metal lines have a first pitch P1;
the second metal lines have a second pitch P2;
the third metal lines have a third pitch P3; and
the gates have a fourth pitch P4, wherein a ratio of the second pitch over the fourth pitch P2:P4 is about 3:2.

US Pat. No. 10,483,197

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a first connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package, the first connection member including an insulating member and a first redistribution layer embedded in the insulating member and having exposed regions in the second surface;
a semiconductor chip having an active surface having connection electrodes disposed thereon, and an inactive surface opposing the active surface in the stacking direction and disposed on the first connection member, the inactive surface facing the second surface of the first connection member;
an encapsulant disposed on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region positioned in the vicinity of the semiconductor chip;
a second redistribution layer including connection vias penetrating through the first region of the encapsulant and connected to the connection electrodes, through-vias penetrating through the second region of the encapsulant and connected to the exposed regions of the first redistribution layer, and a wiring pattern disposed on the encapsulant and having an integrated structure with the connection vias and the through-vias; and
a second connection member having a third surface disposed on the encapsulant and a fourth surface opposing the third surface in the stacking direction, the second connection member including a third redistribution layer connected to the second redistribution layer,
wherein an area of a surface of at least one of the through-vias adjacent to the first connection member is smaller than an area of a surface of the at least one of the through-vias adjacent to the second connection member.

US Pat. No. 10,483,195

RESIN BOARD, METHOD OF MANUFACTURING RESIN BOARD, CIRCUIT BOARD, AND METHOD OF MANUFACTURING CIRCUIT BOARD

FUJITSU LIMITED, Kawasak...

1. A resin board comprising:a first resin layer;
a columnar electrode buried in the first resin layer, the columnar electrode including a protruding portion that protrudes from a side surface of the columnar electrode and configured to cause an electric field applied to the columnar electrode to shift to inside of the first resin layer, the protruding portion having an exposed surface exposed from the first resin layer and a non-linear lateral surface connecting the exposed surface and the side surface, such that the exposed surface and the lateral surface form an obtuse angle; and
a second resin layer formed on the first resin layer so as to be in close contact with no gaps and including a plurality of wiring layers electrically connected to the columnar electrode through the exposed surface,
wherein a portion corresponding to a maximum diameter at the lateral surface of the protruding portion is embedded in the first resin layer,
a diameter of the exposed surface is smaller than the maximum diameter, and
the exposed surface has a shape which is recessed in a direction different from a direction of the second resin layer at a surface of the first resin layer.

US Pat. No. 10,483,193

ELECTRICAL CONNECTIVITY FOR CIRCUIT APPLICATIONS

Infineon Technologies Ame...

1. A method comprising:aligning a face of a chip substrate with respect to an electrically conductive surface of a host substrate, the chip substrate fabricated to include first switch circuits and second switch circuits, a sequence of nodes of the second switch circuits disposed on the face of the chip substrate alongside and substantially parallel to a sequence of nodes of the first switch circuits; and
coupling the sequence of nodes of the first switch circuits and the sequence of nodes of the second switch circuits to an electrically conductive surface of the host substrate.

US Pat. No. 10,483,191

BOTTOM PACKAGE EXPOSED DIE MEMS PRESSURE SENSOR INTEGRATED CIRCUIT PACKAGE DESIGN

STMICROELECTRONICS, INC.,...

1. A package containing a MEMS sensor circuit, comprising:a lead frame having an open region in a middle of the lead frame and a first surface exposed to an ambient atmosphere;
a monolithic MEMS semiconductor die being laterally adjacent to the lead frame, the monolithic MEMS semiconductor die having an exposed outer surface thereof exposed to the ambient atmosphere, the exposed outer surface having a plurality of apertures, the plurality of apertures exposing an internal chamber of the monolithic MEMS semiconductor die to the ambient atmosphere;
a second semiconductor die attached to the monolithic MEMS semiconductor die;
a first plurality of bonding wires connected between the lead frame and the second semiconductor die;
a second plurality of bonding wires connected at least between one of the lead frame and the monolithic MEMS semiconductor die or the monolithic MEMS semiconductor die and the second semiconductor die; and
a molding compound partially covering the monolithic MEMS semiconductor die and the lead frame and encapsulating the second semiconductor die and the plurality of bonding wires, a first surface of the molding compound being flush with the exposed outer surface of the monolithic MEMS semiconductor die and also with the first surface of the lead frame, the exposed outer surface of the monolithic MEMS semiconductor die being a semiconductor material, and an opening of the apertures being flush with the first surface of the molding compound.

US Pat. No. 10,483,183

SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor element;
a temperature detecting element provided at a central part of a surface of the semiconductor element; and
a heat conductor jointed to the surface of the semiconductor element via a jointing element,
wherein
the jointing element comprises a central part positioned over the temperature detecting element, and a peripheral part positioned on a periphery of the central part of the jointing element, and
the heat conductor comprises a metal part being in contact with the central part of the jointing element, and a graphite part being in contact with the peripheral part of the jointing element.

US Pat. No. 10,483,182

INTERMEDIATE CONNECTOR, SEMICONDUCTOR DEVICE INCLUDING INTERMEDIATE CONNECTOR, AND METHOD OF MANUFACTURING INTERMEDIATE CONNECTOR

NODA SCREEN CO., LTD., A...

1. An intermediate connector that is provided between a semiconductor integrated circuit and a circuit board on which the semiconductor integrated circuit is mounted, and electrically connects the semiconductor integrated circuit and the circuit board,the semiconductor integrated circuit including a bump mounting face on which a power source pad row including a plurality of power source pads, a ground pad row including a plurality of ground pads, and a signal pad row including a plurality of signal pads are arranged in parallel,
the intermediate connector comprising:
a power source bus bar in a form of an elongated thin plate that has a length of at least a length of the power source pad row, and is to be connected to each of the power source pads of the power source pad row;
a ground bus bar in a form of an elongated thin plate that has a length of at least a length of the ground pad row, and is to be connected to each of the ground pads of the ground pad row;
a thin film insulator layer that is formed between the power source bus bar and the ground bus bar; and
a conductive path portion in a form of an elongated thin plate that has a length of at least a length of the signal pad row, and includes a plurality of conductive paths to be connected to each of the signal pads of the signal pad row,
wherein the power source bus bar, the ground bus bar, and the conductive path portion are joined together in a parallel arrangement corresponding to the parallel arrangement of the power source pad row, the ground pad row, and the signal pad row, each of which being in a standing state such that a longitudinal direction of the thin plate is parallel to the bump mounting face of the semiconductor integrated circuit.

US Pat. No. 10,483,179

SEMICONDUCTOR DEVICE WITH SEALING PORTION TO SUPPRESS CONNECTION CORROSION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor element having a first pad formed of AlSiCu or AlCu;
a frame member having a second pad;
a connection member that contains at least one of copper and silver and connects the first pad and the second pad; and
a sealing portion that is formed of resin composition containing no sulfur in excess of 100 ppm as measured by extraction from the sealing portion by ion chromatographic analysis under an extraction condition that the temperature is 150° C. and the duration of time is 100 hours, the sealing portion sealing the semiconductor element, the frame member, and the connection member,
wherein arithmetic mean roughness of an upper surface of the first pad is equal to or greater than 0.02 ?m.

US Pat. No. 10,483,178

SEMICONDUCTOR DEVICE INCLUDING AN ENCAPSULATION MATERIAL DEFINING NOTCHES

Infineon Technologies AG,...

1. A semiconductor device comprising:a first contact element on a first side of the semiconductor device;
a second contact element on a second side of the semiconductor device opposite to the first side;
a semiconductor chip electrically coupled to the first contact element and the second contact element; and
an encapsulation material encapsulating the semiconductor chip and portions of the first contact element and the second contact element, the encapsulation material defining at least two notches on a third side of the semiconductor device extending between the first side and the second side, the third side having a length extending between the first side and the second side and having a width perpendicular to the length, wherein the width is less than the length, wherein the at least two notches extend across the width.

US Pat. No. 10,483,172

TRANSISTOR DEVICE STRUCTURES WITH RETROGRADE WELLS IN CMOS APPLICATIONS

GLOBALFOUNDRIES Inc., Gr...

1. A device, comprising:a substrate comprising an N-active region and a P-active region;
a layer of silicon-carbon positioned on an upper surface of said N-active region but not on an upper surface of said P-active region;
a first layer of a first semiconductor material positioned on said layer of silicon-carbon, wherein an upper surface of said first layer of said first semiconductor material is substantially level with an upper surface of an isolation region defining said N-active region;
a second layer of said first semiconductor material positioned on said upper surface of said P-active region;
a layer of a second semiconductor material positioned on said second layer of said first semiconductor material;
an N-type transistor positioned in and above said N-active region; and
a P-type transistor positioned in and above said P-active region.

US Pat. No. 10,483,171

METHOD AND APPARATUS WITH CHANNEL STOP DOPED DEVICES

SYNOPSYS, INC., Mountain...

1. A method of performing channel stop doping in an integrated circuit, comprising:implanting a first part of a surface of a semiconductor substrate with n-type dopants and a second part of the surface with p-type dopants;
making epitaxial semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface implanted with the p-type dopants, the epitaxial semiconductor material having a dopant concentration on the first part of the surface and on the second part of the surface, the dopant concentration changing by a decade over a depth of less than 3 nanometers at an interface between the epitaxial semiconductor material and the semiconductor substrate under process conditions including temperature developed to cause the dopant concentration changing at the interface; and
making a transistor with a transistor channel in the epitaxial semiconductor material, such that the transistor channel, in the epitaxial semiconductor material, of the transistor remains essentially undoped throughout manufacture of the integrated circuit.

US Pat. No. 10,483,168

LOW-K GATE SPACER AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A method comprising:forming a dielectric surface over an active area on a substrate;
forming an inhibitor layer on an exposed surface of the active area;
after forming the inhibitor layer, selectively depositing a low-k spacer along the dielectric surface, the low-k spacer having a dielectric constant equal to or less than 3.9 , wherein a portion of an upper surface of the inhibitor layer remains free of a layer of a material of the low-k spacer while selectively depositing the low-k spacer; and
after selectively depositing the low-k spacer, forming a gate structure along the low-k spacer.

US Pat. No. 10,483,139

SUBSTRATE PROCESSING APPARATUS, METHOD OF OPERATING THE SAME AND NON-TRANSITORY STORAGE MEDIUM

Tokyo Electron Limited, ...

1. A substrate processing apparatus comprising:a plurality of processing units each processing unit being configured to accommodate one substrate of a plurality of substrates therein, the plurality of substrates including a monitor substrate and a product substrate;
a substrate transfer mechanism that transfers substrates to the plurality of processing units; and
a control device,
wherein the control device controls an operation mode of each of the processing units, the operation mode including one of a normal mode or a monitoring mode, the monitoring mode being an operation mode for subjecting the monitor substrate to a first predetermined process based on a characterizing processing condition for the first predetermined process, the normal mode being an operation mode for subjecting the product substrate to a second predetermined process based on a characterizing processing condition for the second predetermined process,
wherein the control device is configured to compare the characterizing processing condition of the second predetermined process, related to the normal mode, with the characterizing processing condition of the first predetermined process, related to the monitoring mode,
wherein the control device is configured to judge, based on a result of the comparison, whether loading of the product substrate to be subjected to the second predetermined process in the processing unit set in the monitoring mode is allowed or prohibited,
wherein the control device is configured to judge that the loading of the product substrate to be subjected to the second predetermined process in the processing unit set in the monitoring mode is allowed, if the characterizing processing condition of the second predetermined process is different from the characterizing processing condition of the first predetermined process, and
wherein the control device is configured to control the substrate transfer mechanism to load the product substrate into one of a processing unit set in the normal mode or a processing unit set in the monitoring mode into which loading of the product substrate is allowed by the judgment.

US Pat. No. 10,483,137

SUBSTRATE LIQUID PROCESSING APPARATUS, SUBSTRATE LIQUID PROCESSING METHOD, AND STORAGE MEDIUM

Tokyo Electron Limited, ...

1. A substrate liquid processing apparatus comprising:a processing bath configured to accommodate therein a processing liquid including a phosphoric acid aqueous solution and a plurality of substrates arranged in a vertical direction, and process the substrates using the processing liquid;
a processing liquid supply pipe configured to supply the processing liquid into the processing bath; and
a plurality of gas supply pipes provided in the processing bath and configured to form bubbles by supplying a gas into the processing liquid,
wherein the gas supply pipes are provided below the substrates, and extend in a horizontal direction perpendicular to circuit-formed surfaces of the substrates, a flow direction of a gas flowing through one gas supply pipe being directed opposite to a flow direction of a gas flowing through another adjacent gas supply pipe, and
each of the gas supply pipes has a plurality of ejection holes formed directly on an outer surface of each of the gas supply pipes, ejection holes of one gas supply pipe and ejection holes of another gas supply pipe adjacent to the one gas supply pipe are arranged in a zigzag manner as viewed from a top of the processing bath, and the plurality of ejection holes are arranged to face upward in a direction parallel to the circuit-formed surfaces of the substrates.

US Pat. No. 10,483,133

METHOD FOR FABRICATING A SEMICONDUCTOR CHIP PANEL

Infineon Technologies AG,...

1. A method for fabricating a semiconductor chip panel, the method comprising:providing a plurality of semiconductor chips, wherein each semiconductor chip comprises a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces;
providing an adhesive layer located on a carrier;
placing at least one interposer on the adhesive layer located on the carrier;
placing the semiconductor chips on the at least one interposer with the second main faces facing the carrier; and
applying an encapsulation material by molding thereby forming the semiconductor chip panel, wherein the encapsulation material is applied so that the side faces of the semiconductor chips are covered with the encapsulation material while the first main faces are not.

US Pat. No. 10,483,117

SYSTEMS AND METHODS FOR PERFORATION AND OHMIC CONTACT FORMATION FOR GAN EPITAXIAL LIFT-OFF USING AN ETCH STOP LAYER

MICROLINK DEVICES, INC., ...

1. A method for forming a GaN-based device or an AlN-based device free of a substrate, the method comprising:providing a device structure comprising:
a substrate having a first surface and a second surface facing away from the first surface, wherein the substrate comprises GaN or AlN or a layer comprising GaN or AlN is disposed on the first surface of the substrate;
an etch stop layer formed over the first surface of the substrate, the etch stop layer having a first bandgap energy level;
a release layer formed on the etch stop layer, the release layer having a second bandgap energy level, the second bandgap energy level lower than the first bandgap energy level;
one or more device layers formed on the release layer to form the GaN-based device or the AlN-based device; and
a perforated support layer formed on one of the one or more device layers forming an outermost layer of the structure;
removing portions of the release layer and of the one or more device layers underlying perforations in the perforated support layer, the removing comprising exposing the device structure to a photoenhanced vertical etch environment to vertically etch portions of the release layer and of at least one of the one or more device layers underlying the perforations in the support layer; and
exposing the device structure to a photoenhanced lateral wet etch environment to laterally etch the release layer, the photoenhanced lateral wet etch environment impinging photons having an energy level greater than or equal to that of the second bandgap energy level of the release layer and lower than that of the first bandgap energy level of the etch stop layer, thereby removing the release layer from between the etch stop layer and the one or more device layers and separating the substrate from the one or more device layers and the perforated support layer.

US Pat. No. 10,483,110

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:an n-type oxide semiconductor layer;
a first electrode joined to a first main surface of the n-type oxide semiconductor layer; and
a second electrode provided on the first main surface of the n-type oxide semiconductor layer or on a second main surface that is a surface on a rear side of the first main surface,
wherein current flows between the first electrode and the second electrode via the n-type oxide semiconductor layer provided between the first electrode and the second electrode,
the semiconductor device further comprising:
a p-type oxide semiconductor layer provided adjacent to a junction between the first electrode and the n-type oxide semiconductor layer; and
a nitride layer provided between the p-type oxide semiconductor layer and the n-type oxide semiconductor layer.

US Pat. No. 10,483,106

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device including a transistor, the method comprising the steps of:forming an oxide semiconductor layer over an insulating layer;
preforming a first heat treatment on the oxide semiconductor layer under an inert atmosphere at a first temperature equal to or higher than 400° C.;
forming an oxide insulating layer over and in contact with a first part of the oxide semiconductor layer after the first heat treatment; and
performing a second heat treatment heating the oxide insulating layer at a second temperature equal to or higher than 150° C. and lower than 350° C.,
wherein the first part of the oxide semiconductor layer is included in a channel formation region of the transistor.

US Pat. No. 10,483,104

METHOD FOR PRODUCING STACKED ELECTRODE AND METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A method for producing a stacked electrode, comprising:preparing a multi-layered graphene film directly on an insulating substrate;
applying a dispersion liquid of metal nanowires directly onto the multi-layered graphene film;
removing a solvent from the dispersion liquid to prepare a metal wiring on the multi-layered graphene film;
pressing the metal wiring to prepare a metal wiring on the multi-layered graphene filing and to strengthen the connection between the multi-layered graphene film and the metal nanowires;
forming a polymer directly on the multi-layered graphene film and the metal wiring to fill asperities of the metal nanowires, wherein the polymer covers the multi-layered graphene film and the metal wiring to obtain a stacked member including the insulating substrate, the multi-layered graphene film, the metal wire, and the polymer; and
cleaving a side of the stacked member where the multi-layered graphene and the insulating substrate are in direct contact and obtaining the stacked electrode including the multi-layered graphene film, the metal wire, and the polymer.

US Pat. No. 10,483,100

METHOD FOR FORMING TION FILM

TOKYO ELECTRON LIMITED, ...

1. A TiON film forming method comprising:accommodating a target substrate in a processing chamber;
maintaining an inside of the processing chamber in a depressurized state; and
repeating multiple times a cycle of forming a unit TiN film at a predetermined processing temperature by alternately supplying a Ti-containing gas and a nitriding gas into the processing chamber and oxidizing the unit TiN film by supplying an oxidizing agent into the processing chamber,
wherein in an initial stage of the film formation, a cycle of supplying the oxidizing agent after repeating the alternate supply of the Ti-containing gas and the nitriding gas X1 times is repeated Y1 times,
wherein in a later stage of the film formation; a cycle of supplying the oxidizing agent after repeating the alternate supply of the Ti-containing gas and the nitriding gas X2 times is repeated Y2 times until a desired film thickness is obtained,
wherein the number of repetition X1 in the initial stage of the film formation is set to be greater than the number of repetition X2 in the later stage of the film formation, and
wherein the Y1 is within a range of wherein a relation between X1 and X2 is selected based on a desired film surface smoothness.

US Pat. No. 10,483,098

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A method of manufacturing a display apparatus, the method comprising:preparing a substrate having a display portion on an upper surface of the substrate;
attaching a protection film having an opening to a lower surface of the substrate so that the protection film overlaps the display portion;
attaching a support film to the lower surface so that the support film is disposed within the opening of the protection film, wherein the support film is spaced apart from the protection film before the support film is attached to the lower surface;
attaching a driving circuit chip to the upper surface so that the driving circuit chip is spaced apart from the display portion and the opening;
removing at least a part of the support film; and
bending the substrate along a longitudinal direction of the opening.

US Pat. No. 10,483,083

SCANNING ELECTRON MICROSCOPE AND IMAGE PROCESSING APPARATUS

HITACHI, LTD., Tokyo (JP...

1. A scanning electron microscope (SEM) comprising:a sample stage for mounting a sample;
a detector for detecting an electron emitted from the sample;
an SEM control section for controlling a distance between the sample stage and the detector;
a memory, which stores:
a material database storing a plurality of datasets comprising information associated with a material, information of a crystal structure of the material, and information of an electron emitted from the material; and
a first relationship between the information of electron emitted from the material, the distance, and a signal detected by the detector.

US Pat. No. 10,483,079

METHOD FOR MANUFACTURING RADIATION WINDOW AND A RADIATION WINDOW

HS FOILS OY, Espoo (FI)

1. A method for manufacturing a radiation window for an X-ray measurement apparatus, comprising:producing an etch stop layer on a polished surface of a carrier,
using a thin film deposition technique to produce a first boron carbide layer on an opposite side of said etch stop layer than said carrier,
soldering the combined structure comprising said carrier, said etch stop layer, and said first boron carbide layer to a region around an opening in a support structure with said first boron carbide layer facing said support structure,
etching away the middle area of said carrier forming an additional support structure, and
after etching away the middle area of said carrier, producing a second boron carbide layer as an additional layer on the exposed etch stop layer on an opposite side of the etch stop layer than said first boron carbide layer.

US Pat. No. 10,483,070

FUSES AND METHODS OF FORMING FUSES

LITTELFUSE, INC., Chicag...

11. A method of forming a fuse, comprising;connecting a leadframe to a base, the leadframe including a first terminal having a first end and a second end and a second terminal having a first end and a second end, the second ends connected by a bridge, and the base including a first aperture and a second aperture to receive the respective first and second terminals;
bonding a plurality of wires at each of the first end of the first terminal and the first end of the second terminal;
attaching a cover to the base, the cover including a cavity such that the first end of the first terminal and the first end of the second terminal are enclosed by the cover; and
wherein the bridge has one or more protrusions disposed between the first and second terminals and extending from the bridge, the plurality of wires being bonded to each of the one or more protrusions therebetween.

US Pat. No. 10,483,065

MOLDED-CASE CIRCUIT BREAKER FOR DC

LSIS CO., LTD., Anyang-s...

1. A molded-case circuit breaker for DC that contains a plurality of interruption units within an outer casing, the DC circuit breaker comprising a two-unit connecting heater that connects fixed contacts of adjacent interruption units, the two-unit connecting heater being placed within the outer casing,wherein the adjacent interruption units are connected to each other as a series circuit,
wherein the two-unit connecting heater is formed in a U-shape, and comprises:
a pair of head portions respectively connected to the fixed contacts of the adjacent interruption units;
a pair of body portions extending downward from the head portions; and
a leg portion connecting the pair of body portions, and
wherein one of the pair of body portions has a tripping mechanism that detects an over-current in a circuit and interrupts the circuit,
wherein a trip portion case for receiving the two-unit connecting heater and the tripping mechanism is placed within the outer casing, and
wherein the trip portion case has a partition for insulation between the interruption units, and a cut groove is formed on a part of the partition to insert the leg portion.

US Pat. No. 10,483,064

ELECTROMAGNETIC DEVICE, AND ELECTROMAGNETIC RELAY USING SAME

Panasonic Intellectual Pr...

1. An electromagnetic device comprising:an excitation coil;
a stator surrounded by the excitation coil, the stator having a first end;
a movable element surrounded by the excitation coil and configured to, when current is flown in the excitation coil, be attracted to the stator by magnetic flux generated at the excitation coil to move in a first direction from a first position to a second position, wherein the movable element is in contact with the first end of the stator when the movable element moves to the second position;
a yoke having a first end and a second end, and forming a part of a magnetic path for the magnetic flux generated at the excitation coil, wherein the first end of the yoke is magnetically combined with the stator, the second end of the yoke is positioned on a side of the first position of the movable element, and the excitation coil is disposed between the first end of the yoke and the second end of the yoke; and
a yoke extension connected to the second end of the yoke and extending from the second end of the yoke to the first end of the stator, the yoke extension being magnetically combined with the yoke, the stator, and the movable element,
and
wherein the yoke extension surrounds entirety of the movable element positioned between the first position and the second position and surrounds the first end of the stator.

US Pat. No. 10,483,062

ELECTRIC WIRE PROTECTION DEVICE

AutoNetworks Technologies...

1. An electric wire protection device comprising:a pyrotechnic cutoff switch, provided partway along an electric wire connecting a load to a vehicle-mounted power supply connected to a reference potential, the pyrotechnic cutoff switch including a conductive part that conducts current between the vehicle-mounted power supply and the load, a cutting blade that cuts the conductive part, a drive part that propels the cutting blade in a direction that cuts the conductive part using the explosive power of gunpowder, and two terminals that input and output current that drives the drive part;
a conductive wire, one end of the conductive wire being connected to the electric wire and another end of the conductive wire being connected to one of the terminals;
a diode, an anode of the diode being connected to the reference potential and a cathode of the diode being connected to the other of the terminals;
a switch, one end of the switch being connected to the other of the terminals and another end of the switch being connected to the reference potential;
a control unit that opens and closes the switch;
a current detecting unit that detects current flowing in the electric wire; and
a temperature detecting unit that detects a surrounding temperature,
wherein the control unit:
includes a temperature calculating unit that calculates a temperature of the electric wire on the basis of the value of the current detected by the current detecting unit and the surrounding temperature detected by the temperature detecting unit; and
a comparing unit that compares the temperature calculated by the temperature calculating unit with a threshold, and wherein the control unit closes the switch in the case where the temperature is greater than or equal to the threshold;
a timer unit that measures a time for which current flows in the electric wire;
a remaining lifespan calculating unit that calculates a remaining lifespan of the electric wire on the basis of the temperature calculated by the temperature calculating unit and the time measured by the timer unit; and
a remaining lifespan communicating unit that communicates information based on a length of the remaining lifespan calculated by the remaining lifespan calculating unit.

US Pat. No. 10,483,054

MONO OR BIDIRECTIONAL CONTACTOR

Telarc S.r.l., Milan (IT...

1. A mono- or bi-directional contactor device for applications involving switching of a power supply for high current and/or voltage electrical loads, comprisinga containing and protective casing made of synthetic plastic insulating material, said casing having a bottom wall from which there extends an actuator portion, said actuator portion comprising a coil and auxiliary contacts,
an intermediate portion for housing fixed and movable contact poles, and
an upper arc chute portion for dissipating an electric arc;
said casing having a flat parallelepiped form, the bottom wall of the casing extending at 90° with respect to a side wall of the casing, said side wall being on a shorter side of said flat parallelepiped form;
a support plate for the contactor being connected to an outer surface of the bottom wall or to an outer surface of said side wall, so as to support the casing as a vertical extension from a horizontal plane or as a horizontal projection from a vertical plane, and
wherein said arc chute portion occupies a quadrant of the parallelepiped form which is situated at a top and/or side with respect to said bottom wall and/or said side wall.

US Pat. No. 10,483,047

ELECTROCHEMICAL REACTION DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A method of using an electrochemical reactor, comprising:preparing an electrochemical reactor, the electrochemical reactor having
a tank including a first room and a second room,
a first electrode disposed in the first room and configured to reduce a first substance,
a second electrode disposed in the second room and configured to oxidize a second substance,
a first pipe connected to the first room, and
a second pipe connected to the first room and disposed above the first pipe;
supplying a first liquid into the first room and the first pipe and a second liquid into the first room and the second pipe to form a first electrolytic solution, and supplying a second electrolytic solution into the second room, the first liquid containing water and forming a first liquid phase in the first electrolytic solution, the second liquid containing an organic solvent and forming a second liquid phase in the first electrolytic solution, the second electrolytic solution containing the second substance, and at least one liquid selected from the group consisting of the first and second liquids further containing the first substance;
applying a voltage between the first and second electrodes to reduce the first substance and thus form a reduction product and to oxidize the second substance and thus form a oxidization product; and
recovering the reduction product with the second liquid through the second pipe, and recovering the oxidization product.

US Pat. No. 10,483,046

ORGANOMETALLIC HALIDE PEROVSKITE SINGLE CRYSTALS HAVING LOW DEFECT DENSITY AND METHODS OF PREPARATION THEREOF

KING ABDULLAH UNIVERSITY ...

1. A method of making a single crystal, comprising:providing a first reservoir including a first liquid, wherein the first liquid includes a first precursor and an organic cation precursor dissolved in a first liquid solvent;
providing a second reservoir including a second liquid, wherein the second liquid is a non-solvent;
wherein the first reservoir and second reservoir are separated by a boundary so that the first liquid and the second liquid do not contact one another, wherein the first reservoir and the second reservoir are in a closed system;
allowing for vapor diffusion of the second liquid into the first liquid so that the solubility of the first precursor and organic cation precursor gradually decreases; and
precipitating out an organometallic halide perovskite single crystal in the first reservoir.

US Pat. No. 10,483,044

MATERIAL FOR ELECTRODE OF POWER STORAGE DEVICE, POWER STORAGE DEVICE, AND ELECTRICAL APPLIANCE

Semiconductor Energy Labo...

1. A material for an electrode of a power storage device comprising:a granular active material comprising a carbon atom; and
a film having a structure over the granular active material,
wherein the structure comprises a plurality of bonds between the carbon atom and one of a silicon atom and a metal atom through an oxygen atom, and
wherein the film partly covers a surface of the granular active material so that the surface of the granular active material has a first region which is covered with the film, and a second region which is not covered with the film.

US Pat. No. 10,483,040

ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a multilayer ceramic capacitor including a capacitor body and a pair of external electrodes disposed on opposite ends of the capacitor body, respectively; and
an interposer including an interposer body having grooves in opposite surfaces thereof, respectively, and a pair of external terminals disposed at opposite ends of the interposer body, respectively,
wherein each of the external terminals includes a bonding portion disposed on an upper surface of the interposer body and connected to a respective one of the external electrodes, a mounting portion disposed on a lower surface of the interposer body, and a connection portion disposed on a respective one of the grooves of the interposer body to connect the bonding portion and the mounting portion to each other, and
?L/L?0.100 in which L is a length of the multilayer ceramic capacitor and ?L=|A?A?|/2, where A is a distance from one end portion of the interposer in a length direction to one end portion of the multilayer ceramic capacitor in the length direction, and A? is a distance from the other end portion of the interposer in the length direction to the other end portion of the multilayer ceramic capacitor in the length direction.

US Pat. No. 10,483,038

MULTILAYER CERAMIC CAPACITOR AND MANUFACTURING METHOD OF MULTILAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a multilayer structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, a main component of the dielectric layers being ceramic, a main component of the internal electrode layers being a metal,
wherein:
at least one of the internal electrode layers includes grains of which a main component is ceramic; and
an area ratio of a total area of the grains to a total area of the at least one of the internal electrode layers in a cross section of the at least one of the internal electrode layers in a stacking direction of the dielectric layers and the internal electrode layers is 12% or more.

US Pat. No. 10,483,030

COIL UNIT, POWER TRANSMISSION DEVICE, AND POWER RECEPTION DEVICE

Toyota Jidosha Kabushiki ...

1. A coil unit comprising:ferrite cores each of which is in a form of a plate; and
a coil that is disposed to face the ferrite cores, the coil surrounding an area around a winding axis extending in a thickness direction of each of the ferrite cores, and the coil including a plurality of curve portions, wherein
each of the plurality of curve portions of the coil is wound across a virtual straight line extending through a curvature center of the curve portion,
the ferrite cores include curve portion ferrite cores that are disposed to face the plurality of the curve portions, respectively, and
each of the curve portion ferrite cores is provided such that a width of a region with a highest magnetic flux density is larger than a width of a region other than the region with the highest magnetic flux density,
in a region that faces the coil,
in a case where a length direction is defined as a direction in which the virtual straight line extends, and
a width direction is defined as a direction perpendicular to the virtual straight line.

US Pat. No. 10,483,022

DEVICE AND METHOD FOR MANUFACTURING CABLE SENSORS

Robert Bosch GmbH, Stutt...

1. A device for manufacturing wire sensors that each includes at least one sensor and a wire trimmed to a respective variably pre-defined length, the device comprising:at least two processing units configured to load and trim a wire blank;
at least one conveying unit via which the at least two processing units are configured to convey the wire blank sequentially between the at least two processing units along a pre-defined motion track; and
at least one deflection unit disposed between successive ones of said at least two processing units that includes:
at least one deflection element that is either (i) in contact with or (ii) is configured to come into contact with the wire blank; and
a displacement unit assigned to the at least one deflection element and configured to modify a position of the assigned deflection element in order to influence a length of the motion track;
wherein one of the at least two processing units is configured to load the wire blank with at least one feature from a group comprising an electrical contact, a sensor, a sensor electronics and an encapsulation of the sensor, and wherein another different one of the at least two processing units is configured to trim the wire blank, said different one of the at least two processing units positioned sequentially apart from said one of the at least two processing units along said pre-defined motion track,
wherein a respective one of the at least one deflection unit is positioned between each of the at least two processing units.

US Pat. No. 10,483,000

MEDICINE ADMINISTERING SYSTEM INCLUDING INJECTION PEN AND COMPANION DEVICE

Companion Medical, Inc., ...

1. A system for administering a medicine to a patient, comprising:an injection pen device comprising:
a housing including a main body structured to include a chamber to encase a cartridge containing medicine upon loading of the cartridge in the chamber;
a dose setting and dispensing mechanism to set and dispense a particular dose of the medicine from the cartridge, the dose setting and dispensing mechanism including a dose knob, a shaft, and a plunger, wherein the dose knob is rotatable to cause the shaft to move to a position proportional to a set dose of the medicine, and wherein the dose knob is operable to move translationally to cause the shaft to drive the plunger to dispense the medicine from the cartridge;
a sensor to detect a dispensed dose, and
an electronics unit in communication with the sensor unit, the electronics unit including a processor and a non-transitory memory to process the detected dispensed dose and time data associated with a dispensing event to generate dose data, a power source to provide electrical power to the electronics unit, and a transmitter; and
a mobile communication device including a software application program product stored in a memory of the mobile communication device and including instructions operable to cause the mobile communication device to process one or more of the dose data corresponding to one or more dispensing events to form a dose dispensing sequence such that the dispensing events of the dose dispensing sequence all occur in temporal proximity of one another that span less than a predetermined temporal threshold, and the last dispensing event in the dose dispensing sequence is identified as the injection event and one or more of the dispensing events other than the last dispensing events in the dose dispensing sequence are identified as the priming events regardless of relative sizes of the dispensing events,
wherein the transmitter of the injection pen device is operable to wirelessly transmit the dose data to the mobile communication device.

US Pat. No. 10,482,990

MEMORY DEVICE AND MEMORY SYSTEM

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:memory elements which store data and parity;
a first decoder which, when a first operation including checking of the data is performed while no external access is being made to the memory device, uses a syndrome generated from the data and the parity to correct an error of a maximum of a first number of bits in a unit of the data; and
a second decoder which, when reading of the data is performed, uses the syndrome to correct an error of a maximum of a second number of bits in a unit of the data,
wherein the second number of bits is smaller than the first number of bits,
wherein in response to a first command, the memory device:
reads the data and the parity from the memory elements,
generates the syndrome from the data and the parity, and
uses the syndrome to correct the error of the data, and
wherein in response to a read command, the memory device:
reads the data and the parity from the memory elements,
generates the syndrome from the data and the parity,
uses the syndrome to correct the error of the data, and
transmits the data in which the error has been corrected.

US Pat. No. 10,482,977

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMEORY CORPORATI...

1. A semiconductor memory device, comprising:a first pad to which a first voltage is supplied;
a second pad to which a second voltage different from the first voltage is supplied; and
a power supply protection circuit including:
a first transistor including a first end electrically connected to the first pad and a second end electrically connected to a first node,
a second transistor including a first end electrically connected to the second pad and a second end electrically connected to the first node,
a third transistor including a first end electrically connected to the second pad, a second end electrically connected to the first node, and a gate electrically connected to a second node, and having a size different from that of the second transistor,
a fourth transistor including a first end electrically connected to the first pad, a second end electrically connected to the second node, and a gate electrically connected to the first node, and
a fifth transistor including a first end electrically connected to the second pad, a second end electrically connected to the second node, and a gate electrically connected to the first node.

US Pat. No. 10,482,970

SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory system comprising:a first semiconductor memory device; and
a signal line connected to the first semiconductor memory device,
wherein the first semiconductor memory device outputs a signal according to existence of a peak current to the signal line, and
wherein when the peak current is larger than a reference current, the first semiconductor memory device is in a waiting state that does not transfer to an operating state using the current larger than the reference current.

US Pat. No. 10,482,964

THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A three-dimensional (3D) semiconductor memory device comprising:a substrate comprising a cell array region and a connection region;
an electrode structure extending from the cell array region onto the connection region in a first direction, the electrode structure comprising a lower stack structure comprising a plurality of lower electrodes vertically stacked on the substrate and a plurality of intermediate stack structures vertically stacked on the lower stack structure to comprise a first stair step structure in the first direction;
an upper stack structure comprising a plurality of upper electrodes vertically stacked on the electrode structure; and
an upper dummy stack structure comprising a plurality of upper dummy electrodes which are horizontally spaced apart from the upper stack structure and are vertically stacked on the electrode structure,
wherein each of the plurality of intermediate stack structures comprises a plurality of intermediate electrodes vertically stacked to comprise a second stair step structure extending in a second direction that is substantially perpendicular to the first direction.

US Pat. No. 10,482,962

TCAM DEVICE AND OPERATING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A ternary content addressable memory (TCAM) device comprising:a plurality of memory cells, each of the plurality of memory cells comprising:
a data storage circuit comprising a first resistor and a second resistor connected in series to divide a search voltage corresponding to search data, and configured to store cell data;
a limiter circuit configured to receive the divided voltage through an input terminal and transmit an output voltage through an output terminal based on a level of the divided voltage; and
a discharge circuit configured to discharge a matching line indicating whether the stored cell data matches with the search data, based on the output voltage of the limiter circuit.

US Pat. No. 10,482,958

RRAM-BASED MONOTONIC COUNTER

Taiwan Semiconductor Manu...

1. A circuit, comprising:a memory array having a plurality of memory cells;
a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state, and a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state;
a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state, and again increment the count by one in response to the first memory cell's transition from the second to the third resistance state; and
an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.

US Pat. No. 10,482,949

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device including a first mode and a second mode different from the first mode, comprising:a memory circuit comprised of a first switch, a memory array, and a peripheral circuit;
a first power source line electrically coupled with an I/O circuit of the peripheral circuit, and supplied with a first voltage in the first mode; and
a second power source line electrically coupled with a memory cell of the memory array, and supplied with a second voltage lower than the first voltage in the second mode,
wherein the first switch is comprised of a first field effect transistor and a second field effect transistor,
wherein a source of the first field effect transistor is electrically coupled with the first power source line,
wherein a source of the second field effect transistor is electrically coupled with the second power source line,
wherein the first field effect transistor is formed on a first well located in a region where the memory cell is formed, and
wherein the second field effect transistor is formed on a second well located in a region where the I/O circuit is formed.

US Pat. No. 10,482,946

MANAGEMENT OF STROBE/CLOCK PHASE TOLERANCES DURING EXTENDED WRITE PREAMBLES

Micron Technology, Inc., ...

1. A memory device comprising circuitry configured to:receive a preamble signal associated with a first preamble of a plurality of preambles;
receive a data strobe signal;
receive a write command signal;
capture a preamble feature of the data strobe signal based on the preamble signal, wherein the preamble feature comprises a rising edge, a falling edge, a high logic value, a low logic value, or a first combination thereof; and
capture a first bit of a data signal based on a data strobe feature that follows the preamble feature, wherein the data strobe feature comprises the rising edge, the falling edge, the high logic value, the low logic value, or a second combination thereof.

US Pat. No. 10,482,945

METHODS FOR INDEPENDENT MEMORY BANK MAINTENANCE AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Micron Technology, Inc., ...

1. A method comprising:refreshing first data stored in a first memory bank of a plurality of memory banks of a memory device; and
subsequent to refreshing the first data, and before refreshing data stored in any of the other ones of the plurality of memory banks, refreshing second data stored in the first memory bank of the plurality of memory banks.

US Pat. No. 10,482,941

MAGNETIC MEMORY DEVICE

Toshiba Memory Corporatio...

1. A magnetic memory device, comprising:a first memory portion including
a first magnetic portion including a first portion and a second portion,
a first magnetic layer, and
a first nonmagnetic layer provided between the second portion and the first magnetic layer;
a first conductive portion electrically connected to the first portion;
a first interconnection electrically connected to the first magnetic layer; and
a controller electrically connected to the first conductive portion and the first interconnection,
the controller being configured to apply a first pulse between the first conductive portion and the first interconnection in a first write operation, the first pulse having a first pulse height and a first pulse length,
the controller being configured to apply a second pulse between the first conductive portion and the first interconnection in a first shift operation, the second pulse having a second pulse height and a second pulse length,
an absolute value of the second pulse height being less than an absolute value of the first pulse height,
the second pulse length being longer than the first pulse length.

US Pat. No. 10,482,940

COMPUTATIONAL ACCURACY IN A CROSSBAR ARRAY

HEWLETT PACKARD ENTERPRIS...

1. A system, comprising:a crossbar array, comprising a plurality of memory elements at junctions, usable in performance of computations;
a calculate engine to calculate ideal conductance of memory elements at a plurality of junctions of the crossbar array;
a determine engine to determine conductance of the memory elements at the plurality of junctions of the crossbar array; and
an adjust engine to adjust conductance of at least one memory element to improve computational accuracy by reduction of a difference between the ideal conductance and the determined conductance of the at least one memory element, wherein the adjusting of the conductance of the at least one memory element is based on an input of a number of actual crossbar parameters comprising a number of models of signal output variation in crossbar arrays.

US Pat. No. 10,482,932

VOLTAGE REFERENCE COMPUTATIONS FOR MEMORY DECISION FEEDBACK EQUALIZERS

Micron Technology, Inc., ...

1. A device, comprising:a voltage reference generator configured to produce one or more distortion correction factors; and
a selection circuit configured to:
receive the one or more distortion correction factors from the voltage reference generator;
select a distortion correction factor of the one or more distortion correction factors as a selected distortion correction factor; and
transmit the selected distortion correction factor such that the selected distortion correction factor is used to offset an interference associated with a data stream on a distorted bit.

US Pat. No. 10,482,927

WATERPROOF MODULE AND SEAL MEMBER THEREOF

ETAC TECHNOLOGY CORPORATI...

1. A module, comprising:a housing having an opening, wherein the opening penetrates through an outer surface of the housing;
an inserting element adapted to enter and exit the housing through the opening; and
a seal member comprising a connecting portion and a resilient portion, wherein the resilient portion surrounds and extends away from a periphery of the connecting portion, the connecting portion is fixed to the inserting element, the connecting portion is proportioned to fit in the opening, and the resilient portion and the connecting portion are proportioned and arranged such that when the inserting element is moved from an ejected position to a retracted position, the connecting portion at least partially enters into the opening, the resilient portion is pressed against the outer surface of the housing at a periphery of the opening, the resilient portion is deformed at a junction of the resilient portion and the connecting portion so as to bend away from the inserting element, and a waterproof seal is created between the resilient portion and the outer surface of the housing.

US Pat. No. 10,482,924

RECORDING MEDIUM, PLAYBACK DEVICE, AND PLAYBACK METHOD

PANASONIC INTELLECTUAL PR...

1. A playback device that reads out and plays contents from a non-transitory computer-readable medium,wherein, recorded in the non-transitory computer-readable medium are
a base video stream that is encoded video information,
an enhanced video stream that is encoded video information, for enhancing luminance of the base video stream by being played synchronously with the base video stream, and
a management information file in which is described a playback path of the base video stream,
wherein a playback path of the enhanced video stream is further described in the management information file so that the enhanced video stream is played synchronously with the base video stream,
wherein the playback device includes
a video playback unit that reads out and plays the base video stream and the enhanced video stream based on the management information file,
wherein the base video includes High Dynamic Range (HDR), and
wherein the enhanced video stream, by being played synchronously with the base video stream, realizes a higher luminance than the base video stream.

US Pat. No. 10,482,921

ERROR DETECTION CODE HOLD PATTERN SYNCHRONIZATION

Micron Technology, Inc., ...

1. A method, comprising:detecting a first scenario, comprising an initialization phase of a memory device, an impending end of an error correction checksum data delivery burst, or both;
upon detection of the first scenario:
asserting an error detection code (EDC) hold reset; and
de-asserting the EDC hold reset synchronous to a rising edge of a command clock (CK_t clock), such that when transmission of an EDC hold pattern from data path circuitry timed to a data path clock (WCK_t) having a WCK_t frequency different than a CK_t frequency of the CK_t clock is triggered based upon a falling edge of the EDC hold reset, the transmission is synchronous to the rising edge of the CK_t clock.

US Pat. No. 10,482,913

MAGNETIC TAPE HAVING CHARACTERIZED MAGNETIC LAYER

FUJIFILM Corporation, To...

1. A magnetic tape comprising:a non-magnetic support;
a non-magnetic layer including non-magnetic powder and a binding agent on the non-magnetic support; and
a magnetic layer including ferromagnetic powder and a binding agent on the non-magnetic layer,
wherein the total thickness of the non-magnetic layer and the magnetic layer is equal to or smaller than 0.60 ?m,
the magnetic layer includes an abrasive,
the percentage of a plan view maximum area of the abrasive confirmed in a region having a size of 4.3 ?m ×6.3 ?m of the surface of the magnetic layer with respect to the total area of the region, obtained by plane observation performed by using a scanning electron microscope is equal to or greater than 0.02% and less than 0.06%,
the logarithmic decrement acquired by a pendulum viscoelasticity test performed regarding the surface of the magnetic layer is 0.010 to 0.050, and
the logarithmic decrement on the magnetic layer side is determined by the following method:
securing a measurement sample of the magnetic tape with the measurement surface, which is the surface on the magnetic layer side, facing upward on a substrate in a pendulum viscoelasticity tester;
disposing a columnar cylinder edge which is 4 mm in diameter and equipped with a pendulum 13 g in weight on the measurement surface of the measurement sample such that the long axis direction of the columnar cylinder edge runs parallel to the longitudinal direction of the measurement sample;
raising the surface temperature of the substrate on which the measurement sample has been positioned at a rate of less than or equal to 5° C./min up to 80° C.;
inducing initial oscillation of the pendulum;
monitoring the displacement of the pendulum while it is oscillating to obtain a displacement-time curve for a measurement interval of greater than or equal to 10 minutes; and
obtaining the logarithmic decrement ? from the following equation:

wherein the interval from one minimum displacement to the next minimum displacement is adopted as one wave period; the number of waves contained in the displacement-time curve during one measurement interval is denoted by n, the difference between the minimum displacement and the maximum displacement of the nth wave is denoted by An, and the logarithmic decrement is calculated using the difference between the next minimum displacement and maximum displacement of the nth wave (An+1 in the above equation).

US Pat. No. 10,482,912

MICROWAVE-ASSISTED MAGNETIC RECORDING APPARATUS AND METHOD

Seagate Technology LLC, ...

1. An apparatus, comprising:a magnetic recording medium having a recording surface comprising a plurality of recording layers each having a different ferromagnetic resonant frequency; and
a recording head arrangement configured for microwave-assisted magnetic recording (MAMR) and writing user data to a first recording layer of the plurality of recording layers, the recording head arrangement comprising:
a write pole configured to generate a write magnetic field; and
a write-assist arrangement proximate the write pole, the write-assist arrangement configured to generate a radiofrequency assist magnetic field at a frequency that corresponds to a first ferromagnetic resonant frequency of the first recording layer.

US Pat. No. 10,482,893

SOUND PROCESSING METHOD AND SOUND PROCESSING APPARATUS

YAMAHA CORPORATION, Hama...

1. A sound processing method comprising:supplying an acoustic signal;
improving a sound quality of the supplied acoustic signal by:
applying a nonlinear filter to a temporal sequence of original spectral envelope of the supplied acoustic signal to smooth fine temporal perturbation of the original spectral envelope without smoothing out a larger temporal change of the original spectral envelope; and
adjusting the supplied acoustic signal having the original spectral envelope using a temporal sequence of spectral envelope smoothed by the nonlinear filter to generate an acoustic signal having the spectral envelope in which the fine temporal perturbation has been smoothed; and
outputting the acoustic signal having the spectral envelope in which the fine temporal perturbation has been smoothed.

US Pat. No. 10,482,892

VERY SHORT PITCH DETECTION AND CODING

HUAWEI TECHNOLOGIES CO., ...

1. A method for pitch detection, implemented by an encoder, comprising:determining a value of an initial pitch lag candidate of a current frame of a signal in a range from a second minimum pitch limitation to a first minimum pitch limitation using a time domain pitch detection technique, wherein the first minimum pitch limitation is a pitch limitation value defined in the Code Excited Linear Prediction Technique (CELP) algorithm, and the second minimum pitch limitation is a value smaller than the first minimum pitch limitation, and wherein the signal is a speech signal or an audio signal;
determining whether a lack of low frequency energy in the current frame is detected; and
determining the initial pitch lag candidate is a final pitch lag when the lack of low frequency energy in the current frame is detected.

US Pat. No. 10,482,890

DETERMINING MEDIA DEVICE ACTIVATION BASED ON FREQUENCY RESPONSE ANALYSIS

The Nielsen Company (US),...

1. A meter to monitor a media device, the meter comprising:a microphone to sense audio;
a device activation detector to:
reuse first frequency values of the sensed audio to determine a first frequency response of the sensed audio, the first frequency values having been determined to perform watermark detection during a first monitoring time interval;
compare the first frequency response to a reference frequency response to determine whether the media device was active during the first monitoring time interval; and
control operation of the meter based on the determination of whether the media device was active during the first monitoring time interval; and
a data reporter to output a device activity determination indicating whether the media device was active during the first monitoring time interval.

US Pat. No. 10,482,889

AUDIO SIGNAL PROCESSING APPARATUSES AND METHODS

HUAWEI TECHNOLOGIES CO., ...

1. An audio signal downmixing apparatus (105) for processing an input audio signal including a plurality of input channels (113), comprising:an auxiliary downmix matrix determiner (107) configured to determine an auxiliary downmix matrix (DW) by:
computing a plurality of eigenvectors of a covariance matrix (COV) defined by the plurality of input channels (113) of the input audio signal;
determining for at least one eigenvector of the plurality of eigenvectors of the covariance matrix (COV) a subspace angle between the at least one eigenvector and a vector defined by a column of a primary downmix matrix (DU);
selecting at least one eigenvector from the plurality of eigenvectors based on the subspace angle and a preset threshold angle ?MIN; and
defining at least one column of the auxiliary downmix matrix (DW) by the at least one selected eigenvector; and
a processor (109) configured to process the input audio signal into an output audio signal including a plurality of primary output channels (123) and at least one auxiliary output channel (125) using a downmix matrix (D), wherein the downmix matrix (D) includes the primary downmix matrix (DU) for providing the plurality of primary output channels (123) and the auxiliary downmix matrix (DW) for providing the at least one auxiliary output channel (125).

US Pat. No. 10,482,876

HIERARCHICAL SPEECH RECOGNITION DECODER

Interactions LLC, Frankl...

1. A computer-implemented method, comprising:receiving, over a computer network, an utterance of a user, the utterance having been accepted from the user at a client device as spoken input;
storing the utterance, the storing comprising identifying a plurality of sub-expressions by applying a parameterized statistical model that determines likely n-grams of literal word tokens and concept placeholders included in the utterance and storing each of the sub-expressions in the data structure as either: a set of literal word tokens representing the sub-expression, or a concept placeholder representing the sub-expression and providing an indication of a language sub-model;
determining likely textual representations of the sub-expressions stored as concept placeholders by applying the indicated language sub-models to the sub-expressions;
generating a user-specific textual interpretation of the utterance, the textual interpretation being a combination of the literal word tokens and the determined likely textual representations of the sub-expressions.

US Pat. No. 10,482,874

HIERARCHICAL BELIEF STATES FOR DIGITAL ASSISTANTS

Apple Inc., Cupertino, C...

1. An electronic device, comprising:one or more processors;
a memory; and
one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for:
receiving a user utterance of a dialogue;
parsing one or more text representations of the user utterance to determine a plurality of semantic interpretations for the user utterance, the plurality of semantic interpretations including more than two concepts or properties, wherein the parsing includes determining that a first concept or property and a second concept or property in the more than two concepts or properties have a joint semantic relationship;
determining, based on the plurality of semantic interpretations, a belief state for the dialogue, the belief state comprising a plurality of dialogue slots representing the more than two concepts or properties, wherein each dialogue slot of the plurality of dialogue slots includes a respective marginal certainty for a respective concept or property represented by the respective dialogue slot, and wherein a first dialogue slot of the plurality of dialogue slots further includes a joint certainty for the first concept or property and the second concept or property based on the determined joint semantic relationship;
determining a plurality of candidate policy actions from the determined belief state;
selecting, based on the marginal certainty of each dialogue slot of the plurality of dialogue slots and the joint certainty, a policy action from the plurality of candidate policy actions; and
performing the selected policy action, including outputting results of the policy action for presentation.

US Pat. No. 10,482,872

SPEECH RECOGNITION APPARATUS AND SPEECH RECOGNITION METHOD

Olympus Corporation, Tok...

1. A speech recognition apparatus comprising:a microphone configured to acquire an audio stream in which speech vocalized by a person is recorded;
a camera configured to acquire an image data in which at least a mouth of the person is captured;
an operation element configured to recognize speech including a consonant vocalized by the person based on the audio stream, estimate the consonant vocalized by the person based on a mouth shape of the person in the image data, and specify the consonant based on the estimated consonant and the speech-recognized consonant,
wherein the operation element specifies a consonant vocalization frame which is a frame in which it is estimated that the person in the image data has vocalized a consonant before a vowel based on a timing when the vowel is detected, and estimates the consonant vocalized by the person based on the mouth shape of the person in the consonant vocalization frame and a mouth shape model that indicates a change in mouth shape for each consonant.

US Pat. No. 10,482,863

METHODS AND APPARATUS TO EXTRACT A PITCH-INDEPENDENT TIMBRE ATTRIBUTE FROM A MEDIA SIGNAL

THE NIELSEN COMPANY (US),...

1. An apparatus comprising:an interface to receive a media signal;
a timbre database to store reference pitch-less timbre spectrums; and
one or more processors to:
compare a pitch-less timbre spectrum of the media signal to the reference pitch-less timbre spectrums; and
classify the media signal based on data corresponding to a reference pitch-less timbre spectrum of the reference pitch-less timbre spectrums that matches the pitch-less timbre spectrum, the classification corresponding to at least one of an instrument or a genre.

US Pat. No. 10,482,860

KEYBOARD INSTRUMENT AND METHOD

CASIO COMPUTER CO., LTD.,...

1. A keyboard instrument comprising:a keyboard that includes a first key specifying a first pitch, a second key specifying a second pitch and a third key specifying a third pitch, when operated, wherein
the first key is associated with first section data corresponding to a first section among a plurality of sections in a piece of music, the first section data includes at least two notes and corresponds to a first period from a first timing to a second timing of the piece of music,
the second key is associated with second section data corresponding to a second section following the first section among the plurality of sections in the piece of music, the second section data includes at least two notes and corresponds to a second period from the second timing to a third timing of the piece of music, and
the third key is not associated with any section data corresponding to any section among the plurality of sections in the piece of music, and
at least one processor electrically connected to the keyboard, wherein the at least one processor is configured to:
display at least one identifier such that the first key and the second key are distinguishable from the third key;
output the first section data as a musical sound when the first key is operated; and
output the second section data as a musical sound when the second key is operated.

US Pat. No. 10,482,858

GENERATION AND TRANSMISSION OF MUSICAL PERFORMANCE DATA

ROLAND VS LLC, Snohomish...

1. A method of capturing musical performance data, the method comprising:generating, by a musical input device comprising a processor, a first command encoding a first musical event;
generating, by the musical input device, a first message corresponding to the first command, wherein the first message encodes a first acoustic attribute type of the first musical event and a first acoustic attribute value, wherein the first acoustic attribute value specifies a first value of the first acoustic attribute type;
generating, by the musical input device, a second message corresponding to the first command, wherein the second message encodes a second acoustic attribute type of the first musical event and a second acoustic attribute value, wherein the second acoustic attribute value specifies a second value of the second acoustic attribute type;
generating, by the musical input device, timestamp data denoting a time of an occurrence of the first musical event, the timestamp data corresponding to the first message and the second message; and
sending the timestamp data, the first command, the first message, and the second message to a computing device.

US Pat. No. 10,482,856

AUTOMATIC PERFORMANCE SYSTEM, AUTOMATIC PERFORMANCE METHOD, AND SIGN ACTION LEARNING METHOD

YAMAHA CORPORATION, Hama...

1. An automatic performance system for a collaborative performance of a musical piece by at least one performer and an automatic performance device, the automatic performance system comprising:a controller, including at least one processor or circuit, configured to execute a plurality of tasks, including:
a sign action detecting task that detects a sign action of the at least one performer performing the musical piece based on a received detection signal;
a performance analyzing task that estimates a performance position in the musical piece based on a received acoustic signal representing a performed sound generated currently by the at least one performer; and
a display control task that controls a display device to display an image corresponding to performance contents at the performance position in the musical piece estimated by the performance analyzing task.

US Pat. No. 10,482,854

HYBRID SNARE DRUM STICK

Freer Precussion LLC, Cl...

1. A drum stick for use by a percussionist comprising a first end section that includes a first threaded portion, a second end section that includes a second threaded portion, and a middle section interposed between and connected to the first end section and to the second end section, wherein the middle section is connected to the first threaded portion of the first end section and to the second threaded portion of the second end section by a threaded connection, wherein the first end section and the second end section are fabricated from a wood laminate material, and wherein the middle section is formed from a woven carbon material.

US Pat. No. 10,482,849

APPARATUS AND METHOD FOR COMPOSITING IMAGE IN A PORTABLE TERMINAL

Samsung Electronics Co., ...

1. An apparatus for compositing images in a portable terminal, the apparatus comprising:a first camera;
a second camera;
a display; and
a processor configured to:
control the display to display a first image and a second image, wherein the first image and the second image are respectively obtained from the first camera and the second camera;
identify, in the displayed first image, a first touch input for selecting a first portion of the first image;
identify, in the displayed second image, a second touch input for selecting a second portion of the second image;
determine that the first portion and the second portion can be composed together by comparing shapes of the first portion and the second portion;
based on a determination that the first portion and the second portion have different shapes, adjust the first portion and the second portion so that the first portion and the second portion have the same shape; and
composite, in response to identifying the first touch input and the second touch input or in response to adjusting the first portion and the second portion, the first portion of the first image on the second portion of the second image such that a background of the second portion of the second image is a background of the first portion of the first image; and
display the composited image.

US Pat. No. 10,482,847

DRIVING METHOD AND DRIVING APPARATUS FOR DISPLAY PANEL, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A driving method for a display panel, the display panel having a first resolution, the driving method comprising:converting RGB signals of an input image having a second resolution into YUV signals corresponding to an output image, a resolution of the output image being not smaller than the second resolution;
converting the YUV signals into RGB signals corresponding to the output image;
converting the RGB signals corresponding to the output image into driving signals for driving the display panel; and
outputting the driving signals to the display panel,
wherein the converting the RGB signals of the input image having the second resolution into the YUV signals corresponding to the output image comprises:
segmenting the input image into N sub-image, N being a positive integer; and
converting RGB signals of each of the sub-images into a group of YUV signals, to obtain N groups of YUV signals,
wherein, in a case where the input image cannot be segmented into N sub-images having a same resolution, the segmenting the input image into N sub-images comprises:
segmenting the input image into N initial sub-images, the N initial sub-images including K first initial sub-images having a third resolution and (N-K) second initial sub-images having a fourth resolution, the third resolution being smaller than the fourth resolution, K being a positive integer and smaller than N; and
inserting a predetermined number of blank pixels at a predetermined position of the first initial sub-images, an amount of the blank pixels being equal to a difference between the fourth resolution and the third resolution.

US Pat. No. 10,482,844

METHOD TO IMPROVE DISPLAY PERFORMANCE AT EDGES OF CIRCULAR DISPLAY SCREEN

SHANGHAI TIANMA AM-OLED C...

1. A method for improving display performance at edges of a circular display screen, comprising:determining an edge area and a central area of the circular display screen, the edge area surrouding the central area;
along a direction from a geometric center of the circular display screen to the edge area of the circular display screen, dividing the edge area into n display regions each having a different luminance-level, where n is a positive integer larger than 1; and
according to luminance of pixels in the central area and the luminance-level of each of the n display regions, adjusting luminance of pixels in each of the n display regions to corresponding target luminance, wherein:
the pixels in each of the n display regions have different corresponding target luminance,
the pixels in a same display region have same corresponding target luminance, and
along the direction from the geometric center to the edge area of the circular display screen, the corresponding target luminance of each of the pixels in different display regions sequentially decreases and ratios between the corresponding target luminance of the pixels in the n display regions and the luminance of the pixels in the central area form an arithmetic sequence, and the arithmetic sequence has a common ratio of approximately ½.

US Pat. No. 10,482,842

MACRO I/O UNIT FOR IMAGE PROCESSOR

Google LLC, Mountain Vie...

1. A device comprising:one or more processors; and
a plurality of channel units that are each configured to implement a separate respective channel of data transfer to an external memory,
wherein each channel unit comprises formatting logic that is configured to receive image data from the external memory in a first format and convert the image data into a second format, and
wherein each channel unit comprises addressing logic that is configured to determine an order in which image data should be read from the external memory,
wherein the plurality of channel units comprises a pair of the channel units that are configured to implement separate respective channels of data transfer to the external memory and to implement ad hoc reading of non-sequential regions of image data from the external memory,
wherein a first channel unit of the pair of channel units is configured to receive coordinate values generated by a processor of the one or more processors, the coordinate values identifying a location within the image data, and wherein the first channel unit is configured to forward the coordinate values to a second channel unit of the pair of channel units,
wherein the second channel unit of the pair of channel units is configured to receive the coordinate values forwarded from the first channel unit of the pair of channel units, to use
the addressing logic to request, from the external memory, a region of image data having a location identified by the coordinate values generated by the processor, the region being a portion of a first row of the image data that is less than all of the first row of a full frame of image data stored in the external memory, to use the reformatting logic to reformat the region of image data, and to forward the reformatted region of image data for access by the processor that generated the coordinate values.

US Pat. No. 10,482,837

LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING LIQUID CRYSTAL DISPLAY

Mitsubishi Electric Corpo...

1. A liquid crystal display, comprising:a plurality of scanning lines and a plurality of signal lines arranged in a matrix pattern on a substrate;
a pixel being formed at a crossing portion of each of the plurality of scanning lines and each of the plurality of signal lines, and comprising a thin film transistor that is connected to each of the plurality of scanning lines and each of the plurality of signal lines;
a plurality of first nonlinear resistance elements formed respectively in the plurality of scanning lines, each of the plurality of first nonlinear resistance elements being connected to one of the plurality of scanning lines at one end thereof and being connected to a first short ring line at another end thereof; and
a plurality of second nonlinear resistance elements formed respectively in the plurality of signal lines, each of the plurality of second nonlinear resistance elements being connected to one of the plurality of signal lines at one end thereof and being connected to a second short ring line at another end thereof, wherein
a voltage is applied to the plurality of first nonlinear resistance elements and the plurality of second nonlinear resistance elements independently of each of the plurality of scanning lines and each of the plurality of signal lines; and
the first short ring line and the second short ring line are electrically isolated from one another to permit application of respective voltages different from one another through the plurality of first nonlinear resistance elements and the plurality of second nonlinear resistance elements.

US Pat. No. 10,482,836

GATE DRIVER AND CONFIGURATION SYSTEM AND CONFIGURATION METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A gate driver for providing a gate drive signal for a thin film transistor array substrate, the gate driver comprising:a driving capability detector configured to receive at least the gate drive signal and to detect a driving capability of the gate drive signal based at least on the gate drive signal, the driving capability being represented by a rising time taken by the gate drive signal in form of a voltage pulse signal to rise from a low level to a high level, wherein the driving capability detector is further configured to output a detection signal indicative of the driving capability to an external controller;
a register configured to receive and store an adjustment instruction in form of a digital signal from the external controller;
a push-pull output circuit comprising a first MOS transistor and a second MOS transistor connected in series; and
a driving capability adjustor connected in series with the first and second MOS transistors and between the first and second MOS transistors, wherein the driving capability adjustor is configured to adjust the driving capability of the gate drive signal in response to the adjustment instruction stored in the register.

US Pat. No. 10,482,833

OPERATION METHOD OF ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. An operation method of an electronic device comprising a first display element, a second display element, a first circuit, and an optical sensor, comprising:measuring an illuminance of external light by the optical sensor;
transmitting an illuminance data including the illuminance of external light to the first circuit;
obtaining a first data and a second data by the first circuit;
setting a first gain value to 0 by the first circuit and determining a second gain value with use of a first function and the illuminance of external light by the first circuit when the illuminance of external light in the first circuit is lower than a first illuminance;
determining the first gain value with use of a second function and the illuminance of external light by the first circuit and determining the second gain value with use of a third function and the illuminance of external light by the first circuit when the illuminance of external light in the first circuit is higher than or equal to the first illuminance and lower than a second illuminance;
determining the first gain value with use of a fourth function and the illuminance of external light by the first circuit and setting the second gain value to 0 by the first circuit when the illuminance of external light in the first circuit is higher than or equal to the second illuminance;
multiplying the first data by the first gain value or a value corresponding to the first gain value to generate a third data in the first circuit and multiplying the second data by the second gain value or a value corresponding to the second gain value to generate a fourth data in the first circuit after the first gain value and the second gain value are determined; and
displaying an image based on the third data using the first display element and an image based on the fourth data using the second display element.

US Pat. No. 10,482,826

GOA DRIVING CIRCUITS AND DISPLAY DEVICES

Shenzhen China Star Optoe...

1. A gate driver on array (GOA) driving circuit, comprising:N number of cascaded-connected GOA units, wherein N is a natural number not smaller than four, wherein the GOA unit at the i-th level comprises a first transistor, a second transistor; a third transistor, a first capacitor, and a first pull-down maintain unit, wherein 1?i?a and a is a natural number smaller than or equal to N/2;
a source and a gate of the first transistor receives turn-on signals, and a drain of the first transistor respectively connects to the first pull-down maintain unit and a node at the i-th level;
a source of the second transistor receives the turn-on signals, a gate of the second transistor receives second clock signals, and a drain of the second transistor connects to the node at the i-th level;
a source of the third transistor receives first clock signals, a gate of the third transistor connects to the node at the i-th level, and a drain of the third transistor respectively connects to the other end of the first capacitor and a gate signal output end at the i-th level;
one end of the first capacitor connects to the node at the i-th level, and the other end of the first capacitor connects to the first pull-down maintain unit, the first pull-down maintain unit connects to a direct-current low voltage end;
the GOA unit at the j-th level comprises a fourth transistor, a fifth transistor, a second capacitor, and a second pull-down maintain unit, wherein a+1?j?N;
a source of the fourth transistor connects to a gate signal output end in the (j?a)-th level, a gate of the fourth transistor receives the second clock signals, a drain of the fourth transistor respectively connects to second pull-down maintain unit and the node at the j-th level Q(j); a source of the fifth transistor receives the first clock signals, a gate of the fifth transistor connects to the node at the j-th level Q(j), and a drain of the fifth transistor respectively connects to the other end of the second capacitor and the gate signal output end at the j-th level; and one end of the second capacitor connects to the node in the j-th level, and the other end of the second capacitor connects to the second pull-down maintain unit, and the second pull-down maintain unit connects to a turn-off voltage; and
wherein the second clock signals and the first clock signals are two different clock signals in one clock signals set;
the clock signals set comprises M number of clock signals, wherein M is a positive integer, wherein a period of each of the clock signals is 8H, and a high level duration of each of the clock signals is 3.2H, a rising edge of the (m+1)-th clock signals is delayed by a time delay of the rising edge of the m-th clock signals, wherein m is a positive integer in a range from 1 to M, and m is not equal to three, the rising edge of the third clock signals is delayed by 1.2H of the rising edge of the second clock signals.

US Pat. No. 10,482,825

DISPLAY DEVICE

Samsung Display Co., Ltd....

15. A display device comprising:a display panel comprising a reference voltage providing portion configured to apply a first reference voltage from a first reference voltage line to a readout line and a pixel portion comprising a plurality of pixels, the first reference voltage being a voltage for detecting a crack in the display panel;
a scan driver configured to provide a scan signal to the pixels via a plurality of scan lines;
a data driver configured to provide a data signal to the pixels via a plurality of data lines; and
a readout circuit configured to convert a voltage of the readout line to digital data, and configured to apply a second reference voltage that is different from the first reference voltage to one of the readout lines,
wherein at least two of the pixels are connected to one of the scan lines and connected to the readout line, and
wherein the reference voltage providing portion comprises a sensing transistor comprising:
a gate electrode coupled to one of the scan lines or to a control line;
a first electrode coupled to the first reference voltage line; and
a second electrode connected both to the readout circuit via the readout line and to the at least two pixels.

US Pat. No. 10,482,816

METHOD FOR DRIVING DISPLAY ELEMENT, DISPLAY DEVICE, AND ELECTRONIC DEVICE

SONY CORPORATION, Tokyo ...

1. A method for driving a display element, the method comprising:in driving the display element including an n-channel drive transistor in which a voltage is applied to one source/drain region and a light-emitting unit is connected to another source/drain region, and a capacitor connected between a gate electrode of the n-channel drive transistor and the other source/drain region,
performing threshold voltage cancellation processing that applies a drive voltage to the one source/drain region in a state where a reference voltage is applied to the gate electrode of the n-channel drive transistor, to bring a potential of the other source/drain region closer to a potential obtained by subtracting a threshold voltage of the n-channel drive transistor from the reference voltage;
subsequently, setting the gate electrode of the n-channel drive transistor in a floating state, and changing a potential of the gate electrode in the floating state via a parasitic capacitance and causing a current to flow via the n-channel drive transistor to increase a voltage between the other source/drain region and the gate electrode, and then applying the reference voltage to the gate electrode of the n-channel drive transistor;
afterwards, performing write processing that applies a video signal voltage to the gate electrode of the n-channel drive transistor; and
subsequently, setting the gate electrode of the n-channel drive transistor in the floating state to cause the light-emitting unit to emit light.

US Pat. No. 10,482,815

PIXEL DRIVING CIRCUIT AND DISPLAY PANEL

Shenzhen China Star Optoe...

1. A pixel driving circuit, comprising a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, a charge-voltage terminal, a reset-voltage-signal terminal, a data-voltage-signal terminal, and a driving-voltage-signal terminal; wherein the driving transistor comprises a gate terminal, a source terminal, and a drain terminal;the first switch is disposed between the gate terminal and the drain terminal, the gate terminal is connected with the reset-voltage-signal terminal via the second switch; the source terminal is respectively connected with the driving-voltage-signal terminal and the data-voltage-signal terminal via the third switch and the fourth switch;
the first capacitor is connected between the gate terminal and the charge-voltage terminal; the charge-voltage terminal is connected with a control terminal of the first switch, the second capacitor is connected between the gate terminal and the driving-voltage-signal terminal;
the pixel driving circuit further comprising:
a first control-signal terminal, wherein the first control-signal terminal is connected with the charge-voltage terminal, the control terminal of the first switch, a control terminal of the third switch, and a control terminal of the fourth switch, so as to control on/off of the first switch, the third switch, and the fourth switch;
a second control-signal terminal, wherein the second control-signal terminal is connected with a control terminal of the second switch, so as to control on/off of the second switch;
a fifth switch, a light-emitting diode and a negative voltage-signal terminal; wherein the light-emitting diode comprises a positive terminal and a negative terminal; the fifth switch is connected between the drain terminal and the positive terminal, so as to control on/off of the driving transistor and the light-emitting diode, and the negative terminal is connected with the negative voltage-signal terminal;
a third control-signal terminal, wherein the third control-signal terminal is connected with a control terminal of the fifth switch, so as to control on/off of the fifth switch;
wherein when the first control-signal terminal and the third control-signal terminal are loaded with a high-level signal, and the second control-signal terminal is loaded with a low-level signal, the potential of the charge-voltage terminal is at a high level, the second switch and the third switch are turned on, and the first switch, the fourth switch, and the fifth switch are turned off; and the gate terminal is connected with the reset-voltage-signal terminal via the second switch, the source terminal is connected with the driving-voltage-signal terminal via the third switch, so as to reset a potential of the gate terminal and a potential of the source terminal.

US Pat. No. 10,482,793

PERSONAL ARTICLE IDENTIFICATION SYSTEM

1. A personal article identification system comprising:a substrate having a top surface and a bottom surface, the bottom surface configured to be secured to a personal article, and the top surface of the substrate having a first indicia;
a top layer having a top surface and a bottom surface, the top layer comprising a second indicia on the top surface and overlaying the substrate;
an intermediary layer between the substrate and the top layer; and
a plurality of dots forming a two dimensional patterned array in the top layer, each of the dots is removably attached to the substrate via the intermediary layer, and when removed expose the underlying first indicia of the top surface of the substrate to create a design element in the two dimensional patterned array;
wherein the first indicia comprises a first color, and the second indicia comprises a second color in contrast to the first color, and the first color on the substrate is exposed when a plurality of selected dots are removed to define the design element.

US Pat. No. 10,482,789

CONTROLLABLE PROPULSIVE FORCE DEVICES INCLUDING PARAMETER ADJUSTMENTS FOR WIRELESS SMART DEVICES

PASCO SCIENTIFIC, Rosevi...

1. A propulsive force device for providing a propulsive force to an integrated wireless device during a science experiment, comprising:a motor to drive a rotating member to generate the propulsive force;
a motor driver coupled to the motor, the motor driver to control operation of the motor; and
at least one processing unit communicatively coupled to the motor driver, the at least one processing unit is configured to receive a control signal from the integrated wireless device, the propulsive force device detachably attached to an exterior of the integrated wireless device and communicatively coupled with a second processing unit of the integrated wireless device, the control signal generated by the second processing unit of the integrated wireless device and communicated to the at least one processing unit to provide the control signal to the motor driver to control operation of the motor driver including adjustment of the at least one parameter of the propulsive force device during the science experiment.

US Pat. No. 10,482,787

SELECTIVE PRESENTATION OF COASTING COACH INDICATOR FOR CONSECUTIVE LEARNED DECELERATION AREAS IN CLOSE PROXIMITY

1. A method for a vehicle, the vehicle being configured to provide coasting coach support when approaching a learned deceleration area, the vehicle being configured to present a coasting coach indicator within the vehicle for the learned deceleration area, the method comprising:identifying, while the vehicle is in use, consecutive learned deceleration areas including a first learned deceleration area and a second learned deceleration area, the second learned deceleration area being subsequent to the first learned deceleration area along a travel path of the vehicle, the first learned deceleration area and the second learned deceleration area being identified using a navigation system within the vehicle, the navigation system including a global positioning system, a local positioning system, a geolocation system, camera-based localization, laser-based localization, or combinations thereof;
determining whether the first learned deceleration area and the second learned deceleration area are located in close proximity to each other;
responsive to determining that the first learned deceleration area and the second learned deceleration area are located in close proximity to each other:
presenting the coasting coach indicator within the vehicle for the first learned deceleration area, whereby a driver is informed that coasting coach support is provided for the first learned deceleration area, and wherein the vehicle provides coasting coach support for the first learned deceleration area; and
disabling the coasting coach indicator for the second learned deceleration area, whereby the coasting coach indicator is not presented within the vehicle for the second learned deceleration area such that the driver is informed that coasting coach support is not provided for the second learned deceleration area, and wherein the vehicle does not provide coasting coach support for the second learned deceleration area.

US Pat. No. 10,482,785

MULTI-SENSOR SYSTEM AND METHOD TO DETER OBSESSIVE COMPULSIVE BEHAVIOR

SHAVE AWAY EUROPE, INC., ...

1. A proximity alert system to be worn by a user, the system comprising:at least two sensor subsystems worn on a first portion of the user's body in relative spaced relation each said sensor subsystem comprising a magnetic field detector, said sensor subsystems further comprising a calibration subsystem configured to calibrate the sensitivity of said sensor subsystems to responsively eliminate the affect of earth's magnetic field on said at least two sensor subsystems by comparing the magnetic field detected by one said sensor subsystem to the magnetic field detected by another said sensor subsystem;
at least one trigger subsystem worn on a second portion of the user's body, said trigger subsystem including a magnetic field detectable by said sensor subsystems; and
wherein each said sensor subsystem provides an alert perceptible to the human senses when one said trigger subsystem is placed within a threshold distance from one said sensor subsystem.

US Pat. No. 10,482,778

SHAPE AND SIGNAL ADJUSTABLE MOTION SIMULATION SYSTEM

Senaptec LLC, Beaverton,...

1. A system for training and/or testing an individual's visual, oculomotor, or sensorimotor abilities that comprises:an apparatus comprising a plurality of light sources provided on a first side of a flexible substrate;
an actuator configured to be at least electrically connected to the apparatus to activate each of the plurality of light sources from which light is emitted that is visible to an individual;
a response input device that receives a response input from the individual, the response input made in response to emitted light from one or more of the plurality of light sources, wherein the response input device comprises a manually operable button; and
a controller in communication with the actuator and the response input device, wherein the controller controls at least one of a sequence, color, and luminance of each of the plurality of light sources, receives the response input, and electronically collects data in an electronic format for further processing, wherein the plurality of light sources provide a visual impression of a straight or curved path of motion simulation by progressively activating individual lights on the flexible substrate.

US Pat. No. 10,482,777

SYSTEMS AND METHODS FOR CONTENT ANALYSIS TO SUPPORT NAVIGATION AND ANNOTATION IN EXPOSITORY VIDEOS

FUJI XEROX CO., LTD., To...

1. A computer-implemented method performed in a computerized system comprising a central processing unit, a display device and a memory, the computer-implemented method performed in connection with a captured video of a content being added to a medium, the computer-implemented method comprising:a. using the central processing unit to analyze changes within a plurality of frames of the captured video to automatically detect scrolling, depicted in the captured video, of the medium to which the content is being added (a video boundary event);
b. using the central processing unit to automatically segment the video into a plurality of video segments based on the detected video boundary event;
c. using the central processing unit to generate an overview image using at least a portion of the video, wherein the overview image is a single image comprising content from the plurality of video segments;
d. using the central processing unit to map a plurality of portions of the overview image to the plurality of video segments;
e. generating a graphical user interface on the display device, the graphical user interface comprising a first graphical user interface portion displaying at least the mapped plurality of portions of an overview image; and
f. in response to detection of a selection event of one of the mapped plurality of portions of the overview image by a user, playing the video segment associated with the selected mapped portion of the overview image, wherein the video segment is played in a second portion of the generated graphical user interface.

US Pat. No. 10,482,774

MANAGEMENT OF NOTICES TO AIRMEN

THALES, Courbevoie (FR)

1. A method, implemented by a computer, for managing a notice to airmen, comprising steps of:receiving at least one notice to airmen message with a computer;
receiving one or more elements of a navigation database associated with a flight plan of an aircraft with the computer;
comparing with the computer a content of the received notice to airmen message with the one or more elements of the navigation database associated with the flight plan of the aircraft; and
carrying out semantic analysis with the computer of the content of the received notice to airmen message expressed in natural language.

US Pat. No. 10,482,768

VEHICLE FUNCTION IMPAIRMENT DETECTION

DENSO International Ameri...

1. A system comprising:a receiver module that is configured to receive at least one radar signal;
a control module that includes a processor that is configured to execute instruction stored in a nontransitory memory, wherein the control module is configured to:
generate a Fourier transformation based on the at least one radar signal; and
determine a presence of wave interference in response to the Fourier transformation having a harmonic distortion value that is greater than a threshold harmonic distortion value; and
a primary indicator module that is configured to, in response to the control module determining the presence of wave interference, generate an indication, wherein the indication corresponds to the presence of wave interference;wherein:the primary indicator module includes at least one of a vibration module, an LED module, and an auditory alert module;
the vibration module includes a vibration motor, a switching element, and a filtering element;
in response to the control module determining the presence of wave interference, the control module is configured to provide an indication signal to the switching element;
in response to the switching element receiving the indication signal, the switching element is configured to activate the vibration motor;
in response to the vibration motor being activated, the vibration motor is configured to generate the indication; and
the indication is a haptic alert.

US Pat. No. 10,482,764

METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR EVALUATING PUBLIC TRANSPORTATION USE

HERE Global B.V., Eindho...

1. A mapping system comprising:a memory comprising map data; and
processing circuitry configured to:
receive probe data points associated with movement of a plurality of people;
associate the movement of the plurality of people with a public transit route within the map data having a plurality of transit stop locations;
determine, from the probe data points associated with movement of the plurality of people, transit stop locations at which people board a public transit vehicle associated with the public transit route;
determine, from the probe data points associated with movement of the plurality of people, transit stop locations at which people exit the public transit vehicle associated with the public transit route;
calculate, from the probe data points associated with the movement of the plurality of people, a number of people boarding the public transit vehicle at each respective transit stop location, and a number of people exiting the public transit vehicle at each respective transit stop location; and
determine, from the number of people boarding the public transit vehicle at each respective transit stop location and the number of people exiting the public transit vehicle at each respective transit stop location, ridership data associated with the public transit route.

US Pat. No. 10,482,756

INTELLIGENT ALERTS IN MULTI-USER ENVIRONMENT

QUALCOMM Incorporated, S...

30. An apparatus for providing a notification to a user in a home network, comprising:a transceiver configured to receive an alert from an electronic device; and
at least one processor operably coupled to the transceiver and configured to:
determine a location for one or more users in the home network;
determine an activity for the one or more users in the home network;
determine an alert relevancy for the one or more users in the home network based on the electronic device;
determine a notification user and a notification device based at least in part on the location, the activity, and the alert relevancy for the one or more users in the home network;
generate a notification message for the notification user based at least in part on the notification user, the notification device, and the alert; and
send the notification message to the notification device.

US Pat. No. 10,482,754

SYSTEM AND METHOD FOR REMOTE PROPERTY MANAGEMENT

TURNKEY VACATION RENTALS,...

1. A system for use in a residential property, the system comprising:a first computing system positionable in the residential property and including a first memory and a first processor;
a second computing system including a second memory and a second processor, the second computing system in communication with the first computing system over a network;
wherein the first memory comprises program instructions executable by the processor of the first computing system to:
recognize a sound indicative of an unexpected event;
retrieve, from a database stored in the first memory, an acoustic profile of the unexpected event; and
responsive to retrieving the acoustic profile of the unexpected event, transmit a notification including an identity of the acoustic profile of the unexpected event to the second computing system over the network, the notification including a passcode to an electronic lock that controls access to the residential property.

US Pat. No. 10,482,744

SYSTEM FOR DETECTING FALLS AND DISCRIMINATING THE SEVERITY OF FALLS

FallCall Solutions, LLC, ...

23. A method for detecting and discriminating the severity of a fall, the method comprising:providing a wearable device including a fall monitor and an activity log resident on the wearable device, operating as background tasks and recording detected movement on the activity log with the fall monitor;
effecting a setting on the wearable device of a rate of communication between a notification module of the wearable device and the activity log based on at least part of a predetermined pattern of a fall discriminator within the activity log, the setting defining a predetermined period of communication between the notification module and activity log set based on at least part of the predetermined pattern independent from a determination of the fall discriminator;
determining, with the fall discriminator, when the activity log of the wearable device includes a notable fall event based on the predetermined pattern.

US Pat. No. 10,482,739

WIRELESS MERCHANDISE SECURITY SYSTEM

InVue Security Products I...

1. A security system configured for securing an item of merchandise from theft, the security system comprising:a sensor configured to be secured to an item of merchandise; and
at least one monitoring component configured to wirelessly communicate with the sensor,
wherein the monitoring component and/or the sensor is configured to initiate an audible and/or a visual security signal indicative of an unsecured state or condition when the proximity between the monitoring component and the sensor is within a predetermined range or distance,
wherein the sensor is configured to removably engage an input port of the item of merchandise to be in electrical communication therewith, and wherein the monitoring component and/or the sensor is configured to initiate a security signal in response to the sensor being removed from the input port of the item of merchandise.

US Pat. No. 10,482,734

SYSTEMS AND METHODS FOR PROTECTING RETAIL DISPLAY MERCHANDISE FROM THEFT

InVue Security Products I...

1. A security system configured for securing a portable electronic device from theft, the security system comprising:a portable electronic device;
a sensor configured to attach to and be in electrical communication with the portable electronic device; and
a monitoring component configured to wirelessly communicate with the sensor,
wherein the monitoring component and the sensor are configured to wirelessly communicate with one another to determine a proximity of the portable electronic device relative to the monitoring component and to be associated with one another using an identifier of the monitoring component and/or the sensor,
wherein the monitoring component and/or the sensor is configured to initiate a security signal based on the proximity between the monitoring component and the sensor, and
wherein the portable electronic device is programmed to initiate a security signal in response to the sensor being removed from the portable electronic device.

US Pat. No. 10,482,723

MULTIDIRECTIONAL MEDIA DISPENSING SELF SERVICE TERMINAL

NCR Corporation, Atlanta...

1. A media dispenser comprising:a media store operable to store a plurality of media items in sheet form;
a pick unit operable to pick media items from the media store;
an intermediate staging area coupled to the pick unit by a first transport, the first transport being operable to convey a picked media item from the pick unit to the intermediate staging area; and
a second transport operable to convey media from the intermediate staging area to a customer delivery area by moving the media in a direction transverse to the first transport, wherein the intermediate staging area includes a first arm and a second arm, the first arm initially closed against the second arm, wherein the first arm is configured to rotationally pivot with respect to the second arm to open to receive the picked media item from the first transport, wherein, after receiving the picked media item, the first arm is configured to rotationally pivot with respect to the second arm to close, securing the picked media item against the second arm.

US Pat. No. 10,482,720

GAMING SYSTEM, GAMING DEVICE, AND METHOD FOR PROVIDING A SPORTS-BASED CARD GAME

Uber Boss, Inc., Austin,...

1. An electronic gaming table configured to accommodate a plurality of users, the table comprising:at least one electronic processor;
at least one electronic memory;
at least one electronic player input device; and
at least one electronic display, wherein the electronic display serves as a gaming surface and a table surface, and wherein the electronic memory, the input device, and the display are operatively connected to the processor, and wherein the memory stores computer readable instructions for the processor that, when executed, cause the processor to:
(a) provide a virtual deck of cards, wherein the virtual cards in the deck have been selected from a virtual pool of cards, the cards in the pool being divided into five different player position categories and the deck comprising 12 virtual cards from each of the five player position categories, wherein the virtual cards comprise identifying information and real-life statistics related to player's actions in real-life sporting events, and wherein the cards in the deck have been selected from the pool of cards such that the probability of the cards in the deck generating a winning total based on the real-life statistics of the selected cards in the deck is maintained within a pre-determined range;
(b) randomly select a hand of a designated quantity of cards from the virtual deck of cards;
(c) display, via the display device, the randomly selected cards face-up;
(d) enable the users, via an input device, to place a bet or to fold and exit the hand;
(e) enable each user to select, via an input device, which, if any, of the displayed cards to keep for the current hand;
(f) discard any cards not selected by the user to be kept for the current hand;
(g) complete the hand by, for each of any discarded cards of the hand, randomly selecting one of the cards remaining in the virtual deck of cards, and displaying, via the display device, that randomly selected card in place of any of the discarded cards;
(h) enable the users, via an input device, to place a bet or to fold and exit the hand;
(i) randomly select a statistic from among the real-life statistics related to player's actions in real-life sporting events for each card in the user's hand and display the selected statistic on the card as a score;
(j) evaluate the completed hand of each user and determine a wining user based on a winning total; and
(k) display, via the display device, any awards or payout values associated with any winning card combinations or a winning total formed by the completed hands.

US Pat. No. 10,482,719

BACCARAT PATTERN WAGERING SYSTEM

1. A method of hosting a side bet wagering event during a game of baccarat on an electronic gaming machine including a housing, player input control, video display including touchscreen sensitivity, processor, memory, and a value-in-value-out credit creation component selected from the group consisting of a) a ticket-in-ticket-out system having a ticket-reading imager and ticket printer, b) a currency validation system having a motor drive to advance currency past a scanner and c) a near field communication receiver and transmitter responsive to an external near field emitting element, the side bet wagering event in an underlying game of baccarat comprising:a player position committing credit through the player input controls on the side bet wagering event;
upon the processor recognizing entry of a wager at a player position on the side bet wagering event, allowing the player position to create a pattern identifying at least three expected underlying baccarat game outcomes that include both player winning outcomes and banker winning outcomes in the pattern;
the processor tracking the actual at least three underlying baccarat game outcomes after the player position has committed credit as a wager in the side bet wagering event;
the processor resolving the side bet wager by comparing correspondence of the identified at least three expected underlying baccarat game outcomes and actual at least three underlying baccarat game outcomes and then resolving the side bet wager against a pay table identifying the correspondence, and crediting winning outcomes and decrementing credit in losing outcomes.

US Pat. No. 10,482,707

GAME INFORMATION ANALYSIS SYSTEM WITH FAILURE RISK DISPLAY

Universal Entertainment C...

1. A game information analysis system comprising an analysis server, the analysis server including:a game information reception part for receiving, from a gaming machine, game information including pieces of information pertinent to an investment money amount and a payout money amount; and
a game information analysis part for conducting an analysis process based on the game information,
the game information including a failure signal indicating occurrence of failure of each gaming machine,
wherein the game information analysis part totalizes values of machine attributes indicating attributes of the gaming machine from the game information,
wherein the game information analysis part determines a failure risk indicating possibility of the occurrence of failure related to the gaming machine based on the failure signal and the values of the attributes,
wherein the game information analysis part also determines a fraudulence risk indicating possibility of a fraudulent act against the gaming machine from the information pertinent to the investment money amount and the payout money amount included in the game information, and
wherein the game information analysis part determines a phased-sign based on both the failure risk and the fraudulence risk and generates data for displaying a report showing said phased-sign so as to be associated with the corresponding gaming machine, the phased-sign indicating a value of the combined failure risk and fraudulence risk in more than just a binary manner.

US Pat. No. 10,482,705

GAMING MACHINE AND SYSTEM FOR CONCURRENT GAMING PLAYER INTERFACE MANIPULATION BASED ON VISUAL FOCUS

Bally Gaming, Inc., Las ...

1. A gaming system configured to visually present a user interface to a player, the user interface including a plurality of concurrently active gaming displayed visual presentations, the gaming system comprising:a virtual-reality (VR) headset including one or more integrated visual output devices, the one or more visual output devices providing a virtual environment for displaying the plurality of concurrently active gaming presentations;
one or more passive input devices incorporated into the VR headset, the one or more passive input devices configured to generate positional input related to a center of attention of the player, the positional input being directly measured relative to the one or more integrated visual output devices; and
one or more processors configured to:
receive the positional input,
determine the center of attention of the player from the positional input,
designate a primary gaming presentation from the plurality of concurrently active gaming presentations, the primary gaming presentation corresponding to the center of attention,
open and display a context-sensitive menu of wager options related to the primary gaming presentation concurrently with displaying the plurality of concurrently active gaming presentations, the options being selectable and activatable by the positional input.

US Pat. No. 10,482,694

SYSTEMS AND METHODS FOR REDUNDANT ACCESS CONTROL SYSTEMS BASED ON MOBILE DEVICES

ACSYS HOLDINGS LIMITED, ...

1. A lock comprising:a bolt;
a hardware processor configured to receive and validate authentication information;
a button configured to unlock the bolt in response to the hardware processor validating the authentication information;
a rechargeable power source coupled to the hardware processor, wherein the button is a freely rotating button configured to energize the rechargeable power source when the button is rotated, and wherein the rotational energy generated by the movement of the button is converted to electric energy and stored in the rechargeable power source.

US Pat. No. 10,482,676

SYSTEMS AND METHODS TO PROVIDE AN INTERACTIVE ENVIRONMENT OVER AN EXPANDED FIELD-OF-VIEW

Meta View, Inc., San Mat...

1. A system configured to provide an interactive environment over an expanded field-of-view, the system comprising:a headset configured to be installed on a head of a user;
a first image forming component held by the headset configured to generate light rays to form a first set of images of virtual content, the first image forming component being configured such that (i) when the headset is installed on the head of the user, the first set of images of virtual content is presented to a first eye of the user over a first angular portion of the user's monocular field-of-view from the user's first eye, wherein the first angular portion is centered along a straight-ahead gaze direction of the user's first eye and (ii) the first set of images of virtual content is superimposed over a view of the real world to create at least part of an augmented reality environment;
a second image forming component held by the headset configured to generate light rays to form a second set of images of virtual content, the second image forming component being configured such that (i) when the headset is installed on the head of the user, the second set of images of virtual content is presented to the first eye of the user over a second angular portion of the user's monocular field-of-view from the user's first eye, wherein the second angular portion is adjacent to the first angular portion, and (ii) the second set of images of virtual content are superimposed over the view of the real world to create at least a second part of the augmented reality environment; and
one or more physical processors configured by machine-readable instructions to: control the first image forming component to generate the light rays to form the first set of images of virtual content; and
control the second image forming component to generate the light rays to form the second set of images of virtual content.

US Pat. No. 10,482,675

SYSTEM AND METHOD FOR PRESENTING PLACARDS IN AUGMENTED REALITY

The Toronto-Dominion Bank...

1. A computing device comprising:a processor;
a communications module coupled to the processor; and
a memory module coupled to the processor and storing instructions that, when executed by the processor, cause the computing device to:
receive, from a mobile computing device via a network using the communications module, an indication of an image of at least a portion of a first placard as extracted from an image captured in an environment based on a machine-interpretable indicium included in the first placard;
identify, based on the indication, in a data store storing information related to a plurality of placards, a placard matching the indication;
retrieve, from the data store, images of further placards related to the matching placard;
select, based on configuration data, one of the images of further placards; and
send, to the mobile computing device via the network using the communications module, the selected one of the images of further placards for display in augmented reality.

US Pat. No. 10,482,674

SYSTEM AND METHOD FOR MOBILE AUGMENTED REALITY

Beijing Jingdong Shangke ...

1. A system for realizing augmented reality, comprising:a visual sensor configured to capture images of an environment; and
a computing device in communication with the visual sensor, wherein the computing device comprises a processor and a storage device storing computer executable code, and the computer executable code, when executed at the processor, is configured to:
identify two-dimensional (2D) objects in the captured images;
construct a three-dimensional (3D) map of the environment using the captured images;
define 3D objects in the 3D map by mapping the 2D objects identified in the captured images to corresponding feature points in the 3D map;
measure dimension and recognize function and style of the 2D objects;
project the 2D objects to the 3D map to define dimension, function and style of the 3D objects in the 3D map corresponding to the 2D objects;
recommend a product that is not present in the environment based on the dimension, function and style of the 3D objects; and
place and render a 3D model of the product to the 3D map based on the 3D objects defined in the 3D map,
wherein the computer executable code is further configured to recommend a product by:
determining a plurality of products based on a category of the environment;
selecting a first subset of products from the plurality of products based on the style of the 3D objects;
selecting a second subset of products from the first subset of products with a function complementary to the function of the 3D objects; and
determining at least one product from the second subset of products that has a size fitting an empty space around the 3D objects.

US Pat. No. 10,482,668

MINIATURE VISION-INERTIAL NAVIGATION SYSTEM WITH EXTENDED DYNAMIC RANGE

THALES VISIONIX, INC., C...

1. A method for vision-inertial navigation, comprising:receiving image data from each of a first sunlight imaging apparatus for capturing images in a first range of lighting conditions, a first indoor lighting imaging apparatus for capturing images in a second range of lighting conditions, and a first night vision imaging apparatus for capturing images in a third range of lighting conditions of a first navigation subsystem, wherein the image data captures visual features of an environment, and wherein the first range of lighting conditions, the second range of lighting conditions, and the third range of lighting conditions are different from one another;
receiving first inertial measurement data from a first inertial sensor (IMU) of the first navigation subsystem;
tracking positions of the visual features based on the image data received from the first sunlight imaging apparatus, the first indoor lighting imaging apparatus, and the first night vision imaging apparatus and the first inertial measurement data received from the first IMU;
assembling a plurality of the tracking positions into representative positional visual image information; and
displaying the representative positional visual image information.

US Pat. No. 10,482,665

SYNCHING AND DESYNCING A SHARED VIEW IN A MULTIUSER SCENARIO

Microsoft Technology Lice...

1. A computer system for synchronizing and desynchronizing mixed-reality datasets between multiple devices comprising:one or more processors; and
one or more computer-readable media having stored thereon executable instructions that when executed by the one or more processors configure the computer system to perform at least the following:
identify multiple users in a mixed-reality environment, wherein the mixed-reality environment is defined by a global mixed-reality dataset;
display a synchronized view of the global mixed-reality dataset to each of the multiple users within a shared coordinate system, wherein the shared coordinate system is simultaneously established in relation to at least a first tangible object within the physical environment of a first user of the multiple users and in relation to a different tangible object within the physical environment of at least one different user of the multiple users;
receive a command from the first user to desynchronize from the multiple users;
display to the first user a first desynchronized view of the global mixed-reality dataset, wherein the first desynchronized view is also displayed to the first user according to the shared coordinate system, wherein the first desynchronized view comprises a view of the global mixed-reality dataset, but with a capability of the first user to, independent from other synchronized users, for the global mixed-reality dataset, view additional data , view less data, view different data, or manipulate data; and
display, within the mixed-reality environment, a visualization associated with the first user, wherein the visualization at least:
indicates to at least one other user of the multiple users that the first user is desynchronized from the multiple users; and
is rendered to correspond with the position of the first user within the mixed-reality environment.

US Pat. No. 10,482,661

DISPLAYING OF AUGMENTED REALITY OBJECTS

International Business Ma...

1. A computer-implemented method for displaying one or more augmented reality (AR) objects on a transparent display device, the method comprising:associating data of one or more transparent areas corresponding to one or more real objects with a first layer;
associating one or more AR objects with a second layer;
determining a concentration level of one or more users as it relates to at least one AR object of the one or more AR objects;
based on determining that the concentration level does not exceed a threshold, increasing a playback speed associated with the at least one AR object;
based on determining that determining that the concentration level exceeds a threshold, decreasing a playback speed associated with the at least one AR object; and
overlaying the first layer with the second layer to display the one or more AR objects on a transparent display device based on a priority, wherein the one or more real objects are seen through the one or more transparent areas on the transparent display device by a user utilizing the transparent display device.

US Pat. No. 10,482,652

IMAGE CONVERSION FOR SIGNAGE

AIM SPORT AG, Kriens-Luc...

1. A method of image conversion for signage, comprising:determining a shape model of a three-dimensional object;
determining geometric properties of a display surface of a display device, including a position and orientation of the display surface in a space;
determining a viewing position in the space;
determining a position and orientation of the shape model in the space;
determining a shape model of physical objects that are present around the display surface;
computing a two-dimensional view of the three-dimensional object and of the shape model of the physical objects around the display surface, as seen from the viewing position, wherein the two-dimensional view shows the three-dimensional object in the context of the physical objects;
displaying the two-dimensional view as a preview image of an image that is visible through a camera at the viewing position;
computing an inverse perspective projection of at least a part of the object that is visible from the viewing position onto the display surface based on the viewing position to generate a display image, where the display image, when displayed on the display surface and viewed from the viewing position, appears to show the three-dimensional object with a position and orientation according to the position and orientation of the shape model in the space;
displaying the display image on the display surface; and
capturing an image of the display surface displaying the display image, using the camera at the viewing position.

US Pat. No. 10,482,648

SCENE-BASED FOVEATED RENDERING OF GRAPHICS CONTENT

QUALCOMM Incorporated, S...

1. An apparatus configured to render graphics content, the apparatus comprising:a fovea estimation engine configured to generate an indication of a first portion of graphics content based on scene information related to the graphics content, the graphics content further including a second portion; and
a rendering engine responsive to the fovea estimation engine, the rendering engine configured to perform a comparison of a first value of an evaluation metric associated with the graphics content with a second value of the evaluation metric, the first value associated with the first portion and the second value associated with the second portion, wherein the evaluation metric is based on at least one of a number of visible triangles associated with a bin of the graphics content, a number of pixels updated per triangle of the graphics content, a number of texture samples read per triangle of the graphics content, or a number of arithmetic logic unit (ALU) instructions associated per triangle or bin of the graphics content, wherein the rendering engine is further configured to render the graphics content using predictive adjustment based on the comparison.

US Pat. No. 10,482,639

DEEP HIGH-RESOLUTION STYLE SYNTHESIS

Adobe Inc., San Jose, CA...

1. A computer-implemented method for synthesizing an image style based on a plurality of neural networks, the computer-implemented method comprising:selecting, by a computer system, a style image based on user input that identifies the style image;
generating, by a generator neural network, a synthesized image based on the style image, wherein the generator neural network is a feed-forward generator neural network and is trained using a loss neural network by:
generating, by different layers of the generator neural network and based on a training image, a first output image at a first resolution and a second output image at a second resolution, wherein the first resolution is smaller than the second resolution, the training image and the style image having a same resolution;
applying the loss neural network to the first output image to generate a first set of output style features;
applying the loss neural network to the second output image to generate a second set of output style features;
generating a first set of training image style features and a second set of training image style features based on the training image and the loss neural network;
determining, by the computer system, a first loss based on the first set of output style features and the first set of training image style features, and a second loss based on the second set of output style features and the second set of training image style features; and
adjusting, by the computer system, parameters of different layers of the generator neural network based, at least in part, upon the first and the second losses; and
providing, by the computer system, the synthesized image to a user device in response to the user input.

US Pat. No. 10,482,634

SYSTEMS AND METHODS FOR IMAGING WITH ANISOTROPIC VOXELS

GENERAL ELECTRIC COMPANY,...

1. A system comprising:at least one detector configured to acquire imaging information;
a microprocessor operably coupled to the at least one detector and configured to acquire the imaging information from the at least one detector, the microprocessor configured to reconstruct an image using the imaging information, wherein the imaging information is organized into voxels having non-uniform dimensions, the microprocessor configured to:
perform a penalized likelihood (PL) image reconstruction using the imaging information, the PL image reconstruction comprising a penalty function, wherein performing the penalty function comprises:
interpolating a voxel size in at least one dimension from an original size to an interpolated size before determining a penalty function;
determining the penalty function using the interpolated size to provide an initial penalty;
interpolating the initial penalty to the original size to provide a modified penalty; and
applying the modified penalty in the PL image reconstruction; and
a display unit configured to display the image generated using the PL image reconstruction.

US Pat. No. 10,482,629

SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR AUTOMATIC OPTIMIZATION OF 3D TEXTURED MODELS FOR NETWORK TRANSFER AND REAL-TIME RENDERING

KUBITY, Paris (FR)

1. A computer-implemented method of automatic optimization of 3D textured models, the method comprises the steps of:extracting with at least one processor from a 3D textured model composed of a plurality of meshes, a 3D geometry and a plurality of textures;
by using with the at least one processor a first set of target parameters from a database of parameters, wherein the database comprises target parameters and optimal parameters predefined for target applications and target devices, applying an aggregating algorithm on the 3D geometry to obtain an aggregated 3D geometry, and applying a simplification algorithm on the aggregated 3D geometry to obtain a plurality of simplified 3D geometry versions;
by using with the at least one processor a second set of target parameters from the database of parameters, applying a degradation algorithm on the plurality of textures to obtain a plurality of degraded texture versions;
serializing with the at least one processor the plurality of simplified 3D geometry versions with the plurality of degraded textures versions to obtain a plurality of serialized 3D data content; and
by using with the at least one processor a set of optimal parameters, the optimal parameters being selected from the database of parameters for a target application and a target device, generating an optimized 3D textured model from a simplified geometry and a degraded texture, the optimized 3D textured model being optimized for real-time rendering in the target application of the target device.

US Pat. No. 10,482,625

CALIBRATION OF NETWORKED IMAGING DEVICES TO A GLOBAL COLOR SPACE

Amazon Technologies, Inc....

1. A computer implemented method, comprising:under control of one or more computing systems configured with executable instructions,
receiving, from each of a plurality of cameras, image data produced by the respective camera, each image data including a representation of one or more of a plurality of markers positioned within a materials handling facility, wherein each image data includes a plurality of pixel values;
determining that a first sum of a number of representations of markers included in the plurality of image data is greater than a second sum of a number of parameters of the plurality of cameras and a number of the plurality of markers;
determining from pixel values of each image data, a respective intensity value for each representation of each marker in each image data from each of the plurality of cameras;
determining based on the respective intensity value determined for each representation of each marker in each image data from each of the plurality of cameras, a plurality of parameters for each of the plurality of cameras;
generating for each camera of the plurality of cameras a respective transformation function based on the parameters for the camera;
receiving second image data from a first camera of the plurality of cameras, wherein the second image data includes a second plurality of pixel values; and
transforming at least a portion of the pixel values of the second image data according to a first transformation function corresponding to the first camera to produce transformed second image data corresponding to a global color space.

US Pat. No. 10,482,623

PLACEMENT OF AUGMENTED REALITY OBJECTS USING A BOUNDING SHAPE

Capital One Services, LLC...

1. A system, comprising:a camera;
a display;
one or more memories; and
one or more processors, communicatively coupled to the one or more memories, to:
output a bounding shape for presentation on the display,
the bounding shape being superimposed on an image being captured by the camera, and
a base of the bounding shape to be aligned with a base of a target object in the image;
determine three-dimensional (3D) coordinates of an intersection point associated with the bounding shape;
determine 3D coordinates of an augmented reality object based on the determined 3D coordinates of the intersection point associated with the bounding shape,
the augmented reality object being offset based upon at least one of:
a height of the target object in the image, or
a height of the bounding shape;
determine two-dimensional (2D) coordinates for presentation of the augmented reality object based on the determined 3D coordinates of the augmented reality object; and
superimpose the augmented reality object, according to the 2D coordinates, on the image, as the image is rendered for display.

US Pat. No. 10,482,619

METHOD AND APPARATUS FOR COMBINING DATA TO CONSTRUCT A FLOOR PLAN

AI Incorporated, Toronto...

1. A method of perceiving a spatial model of a working environment, the method comprising:capturing data by one or more sensors of a robot moving within a working environment, the data being indicative of depth within the working environment from respective sensors of the robot to objects in the working environment at a plurality of different sensor poses;
obtaining, with one or more processors of the robot, a plurality of depth images based on the captured data, wherein:
respective depth images are based on data captured from different positions within the working environment through which the robot moves,
respective depth images comprise a plurality of depth data, the depth data indicating distance from respective sensors to objects within the working environment at respective sensor poses, and
depth data of respective depth images correspond to respective fields of view;
aligning, with one or more processors of the robot, depth data of respective depth images based on an area of overlap between the fields of view of the plurality of depth images, wherein aligning comprises:
determining a first area of overlap between a first depth image and a second depth image among the plurality of depth images by:
detecting a feature in the first depth image;
detecting the feature in the second depth image;
determining a first value indicative of a difference in position of the feature in the first and second depth images in a first frame of reference of the one or more sensors:
obtaining a second value indicative of a difference in pose of the one or more sensors between when depth data from which the first depth image is obtained and when depth data from which the second depth image is obtained; and
determining the first area of overlap based on the first value and the second value; and
determining a second area of overlap between the second depth image and a third depth image among the plurality of depth images, the first area of overlap being at least partially different from the second area of overlap; and
determining, with one or more processors of the robot, based on alignment of the depth data, a spatial model of the working environment,
wherein at least some data processing of the spatial model is offloaded from the robotic device to the cloud,
wherein the spatial model is further processed to identify rooms in a floor plan, and
wherein the spatial model is stored in memory accessible to the robot during a subsequent operational session for use in autonomously navigating the working environment.

US Pat. No. 10,482,617

DISTANCE ESTIMATION METHOD BASED ON HANDHELD LIGHT FIELD CAMERA

Graduate School at Shenzh...

1. A distance estimation method based on a handheld light field camera, comprising the following steps:S1: extracting parameters of alight field camera, comprising a focal length, a curvature radius, a pupil diameter, and a central thickness of a main lens of the light field camera, and a focal length of a microlens array of the light field camera;
S2: setting a reference plane and a calibration point, wherein the calibration point is set on an object whose distance needs to be estimated, and obtaining a distance between the reference plane and the main lens;
S3: refocusing a collected light field image on the reference plane, to obtain a distance between the main lens and the microlens array of the light field camera, and recording an imaging diameter of the calibration point on the refocused image; and
S4: inputting the parameters of the light field camera that are extracted in step S1, the distance between the main lens and the microlens array that is obtained in step S3, and the imaging diameter of the calibration point on the refocused image that is recorded in step S3 to a light propagation mathematical model, and outputting a distance of the calibration point.

US Pat. No. 10,482,611

DETERMINING OPTICAL FLOW

Google LLC, Mountain Vie...

1. A computer-implemented method of forming an optical flow vector describing estimated displacement of a subject pixel, the method comprising:obtaining, by one or more computing devices, a plurality of input color vectors respectively associated with a plurality of input pixels, each input pixel having a known position within an image;
obtaining, by the one or more computing devices, a color rate of change associated with each input pixel in the image; and
determining, by the one or more computing devices, an optical flow estimate associated with a subject pixel within the image based at least in part on the plurality of input color vectors and the color rates of change associated with the input pixels in the image.

US Pat. No. 10,482,608

METHOD AND APPARATUS TO GENERATE HAPTIC FEEDBACK FROM VIDEO CONTENT ANALYSIS

IMMERSION CORPORATION, S...

1. A method of generating haptics for a video, comprising:tracking motion of an object in the video, the video including a plurality of image frames;
performing image processing on the plurality of image frames;
detecting an event based on the image processing to generate a detected event;
obtaining sensor information associated with the plurality of image frames, the sensor information including one or more sensor measurements of the motion of the object;
generating a first estimate of the motion of the object based on the plurality of image frames and a second estimate of the motion of the object based on the one or more sensor measurements;
updating the first estimate of the motion of the object with the second estimate of the motion of the object to generate an updated first estimate, and providing a control signal based on the detected event and the updated first estimateorupdating the second estimate of the motion of the object with the first estimate of the motion of the object to generate an updated second estimate, and providing the control signal based on the detected event and the updated second estimate, the control signal being configured to cause haptic feedback for the motion of the object in the video; and
providing the haptic feedback based on the control signal, the providing of the haptic feedback occurring in synchronization with the motion of the object in the video.

US Pat. No. 10,482,601

EVALUATION OF CAROTID PLAQUE USING CONTRAST ENHANCED ULTRASONIC IMAGING

KONINKLIJKE PHILIPS N.V.,...

1. An ultrasonic diagnostic imaging system for the evaluation of plaque by enhanced ultrasound, the system comprising:an ultrasound imaging probe,
wherein the ultrasound probe comprises an array transducer,
wherein the array transducer is arranged to acquire a sequence of ultrasound images of a plaque region in a carotid artery;
a time intensity curve calculator arranged to form a first plurality of time intensity curves for the plaque region,
wherein the plaque region comprises a plurality of pixels,
wherein the first plurality of time intensity curves includes a time intensity curve for a portion of the plurality of pixels;
a comparator circuit arranged to determine a perfusion, wherein the perfusion is based on a difference of a second plurality of time intensity curves for the plaque region and the first plurality of time intensity curves for the plaque region; and
a display arranged to display the perfusion in the plaque region.