US Pat. No. 10,170,890

METHOD OF FABRICATING SEMICONDUCTOR OPTICAL DEVICE AND SURFACE-EMITTING SEMICONDUCTOR LASER

SUMITOMO ELECTRIC INDUSTR...

1. A surface-emitting semiconductor laser comprising: a substrate; a first stacked semiconductor layer disposed on the substrate and including a first distributed Bragg reflector; an active layer disposed on the first stacked semiconductor layer; and a second stacked semiconductor layer disposed on the active layer and including a second distributed Bragg reflector; a first electrode; and a second electrode, the substrate, the first and second stacked semiconductor layers and the active layer providing a semiconductor structure with a first structure side, a second structure side opposite to the first structure side, and a side structure surface that extends from the second structure side to the first structure side, the side structure surface having an upper side free of chipping, the first electrode and the second electrode each being provided on the first structure side of the semiconductor structure, the semiconductor structure being formed by:preparing a substrate product that includes a first side and a second side opposite to the first side, the first side including device sections arranged in an array and a street region extending between the device sections, at least one of the device sections including the first and second electrodes and the semiconductor structure for the surface-emitting semiconductor laser;
forming a first mask on the first side of the substrate product, the first mask having a pattern that includes device covering portions covering the respective device sections and an opening defining the device covering portions, the opening being provided in the street region;
etching the substrate product using the first mask so as to form a groove in the street region, the groove defining the device sections;
after removing the first mask, securing the first side of the substrate product to a first support member; and
after securing the first side of the substrate product to the first support member, forming an array of semiconductor chips on the first support member by removing part of the substrate product from the second side until the groove provided in the first side is exposed so as to separate the at least one device section including the first and second electrodes and the semiconductor structure from other device sections to provide the surface-emitting semiconductor laser.

US Pat. No. 10,170,888

DUAL-USE LASER SOURCE COMPRISING A CASCADED ARRAY OF HYBRID DISTRIBUTED FEEDBACK LASERS

Oracle International Corp...

1. A laser source, comprising:a silicon waveguide formed in a silicon layer; and
a cascaded array of hybrid distributed feedback (DFB) lasers formed by locating sections of III-V gain material over the silicon waveguide;
wherein each DFB laser in the cascaded array comprises,
a section of III-V gain material located over the silicon waveguide, wherein the section of III-V gain material includes an active region that generates light, and
a Bragg grating located on the silicon waveguide, wherein the Bragg grating has a resonance frequency within a gain bandwidth of the section of III-V material and is transparent to frequencies that differ from the resonance frequency,
wherein the DFB laser has a hybrid mode that resides partially in the III-V gain material and partially in silicon.

US Pat. No. 10,170,855

WATERPROOF COMPONENT HAVING A COVER WITH EXCESSIVE DISPLACEMENT PREVENTION WALL

YAZAKI CORPORATION, Mina...

1. A waterproof component configured to insert an electric wire into an attachment hole penetrating a wall portion to lock, the waterproof component comprising:a housing body including:
an attachment hole insertion portion configured to be inserted into the attachment hole, a mat seal accommodating chamber having a bottom wall being formed inside the attachment hole insertion portion;
an abutting portion configured to abut a first peripheral surface of the attachment hole;
a locking claw provided in an elastically deformable manner on an insertion tip side of the attachment hole insertion portion, the locking claw being configured to be locked to a second peripheral surface of the attachment hole opposite to the first peripheral surface; and.
a cover locking portion provided on an insertion tip side of the attachment hole insertion portion;
a mat seal accommodated in the mat seal accommodating chamber, the mat seal having an electric wire press-fitting hole through which an electric wire is to penetrate; and
a mat seal cover locked to the cover locking portion, the mat seal cover interposing the mat seal between the mat seal cover and the bottom wall to hold the mat seal in the mat seal accommodating chamber,
wherein the mat seal cover is provided with an excessive displacement prevention wall on a side where the locking claw is elastically deformed when the locking claw is inserted into the attachment hole.

US Pat. No. 10,170,835

WIRELESS COMMUNICATION DEVICE

MURATA MANUFACTURING CO.,...

1. A wireless communication device comprising:a planar conductor including an opening;
a housing including the planar conductor;
a planar coil antenna opposed to the opening and including a coil pattern and a coil opening; and
a linear strip pattern including a plurality of linear strip portions parallel or substantially parallel with one another; wherein
a portion of the linear strip pattern which is connected to the planar conductor around the opening is provided in the opening;
the opening of the planar conductor is not connected to any peripheral edge of the planar conductor; and
the planar coil antenna is incorporated in the housing.

US Pat. No. 10,170,825

ANTENNA DEVICE

FUJIKURA LTD., Tokyo (JP...

1. An antenna device comprising:a film antenna;
a cable which is connected to a feed section of the film antenna; and
a support, around which at least part of the film antenna is wound,
the support including a holding section for holding the cable,
wherein:
the support has
a first supporting surface,
a second supporting surface intersecting the first supporting surface, and
a third supporting surface facing the first supporting surface and intersecting the second supporting surface;
the film antenna is wound around the support so as to be in contact with the first supporting surface, the second supporting surface, and the third supporting surface; and
the holding section includes a first holding part for holding the cable so that part of the cable extends in a direction along the first supporting surface and the second supporting surface.

US Pat. No. 10,170,822

COMMUNICATION DEVICE AND METHOD FOR DETERMINING A LOAD IMPEDANCE

Infineon Technologies AG,...

1. A communication device comprising:a signal path for supplying a signal;
two directional couplers arranged within the signal path, wherein each directional coupler is coupled to an adjustable impedance defining a characteristic impedance of each directional coupler;
a controller configured to set, for each of a plurality of impedances, the adjustable impedances of the directional couplers to an impedance;
a return loss measurement circuit configured to determine, for each of the plurality of impedances, a return loss of the signal path when the adjustable impedances of the directional couplers are set to the impedance;
a load impedance determination circuit configured to determine a load impedance of the signal path based on the determined return losses.

US Pat. No. 10,170,758

PROCESS FOR THE PREPARATION OF LITHIUM TITANIUM SPINEL AND ITS USE

Johnson Matthey Public Li...

1. A process for the preparation of phase-pure doped or non-doped lithium titanate Li4Ti5O12, comprising sintering a composite oxide at a temperature of ?780° C.,wherein the composite oxide comprises x wt.—parts Li2TiO3, y wt.—parts TiO2, z wt.—parts of Li2CO3 and/or lithium hydroxide, u wt.—parts of a carbon source and optionally v wt.—parts of a transition or main group metal compound and/or a sulfur containing compound,
wherein the Li2TiO3 is present in its cubic crystal structure,
wherein x is a number between 2 and 3, wherein y is a number between 3 and 4,
wherein z is a number between 0.001 and 1, u is a number between 0.05 and 1, and 0?v?0.1, and
wherein the metal of the transition or main group metal compound is selected from the group consisting of Al, Mg, Ga, Fe, Co, Sc, Y, Mn, Ni, Cr, V and mixtures thereof.

US Pat. No. 10,170,755

LITHIUM SULFUR CELL AND PREPARATION METHOD

Robert Bosch GmbH, Stutt...

1. A method of forming an electrochemical cell, comprising:forming a plurality of Li2S grains;
coating the plurality of Li2S grains;
exposing the coated plurality of Li2S grains and an uncoated plurality of Li2S grains to an organic solvent including dissolved sulfur;
dissolving the uncoated plurality of Li2S grains with the organic solvent;
rinsing the coated plurality of Li2S grains after exposing the coated plurality of Li2S grains to the organic solvent;
forming a positive electrode using the rinsed coated plurality of Li2S grains; and
locating a separator between the positive electrode and a negative electrode including a form of lithium.

US Pat. No. 10,170,737

BATTERY HOLDER, BATTERY UNIT, AND BATTERY COMPONENT INCLUDING BATTERY HOLDER AND BATTERY UNIT

Shimano Inc., Osaka (JP)...

1. A battery holder for holding a battery unit at least in a state in which the battery unit is located at a first holding position, the battery holder comprising:a first base that opposes a first end of the battery unit in the state in which the battery unit is located at the first holding position;
a first holding portion movably arranged on the first base between a first position, at which the first holding portion contacts a held portion of the battery unit and holds the battery unit at the first holding position, and a second position, at which the first holding portion is separated from the held portion; and
a second holding portion arranged on the first base at least partially on a downstream side of the first holding portion in a removal direction in which the battery unit is removed from the battery holder, and the second holding portion being configured to hold the battery unit at a second holding position that is located at the downstream side of the first holding position.

US Pat. No. 10,170,732

FLEXIBLE SECONDARY BATTERY

SAMSUNG SDI CO., LTD., Y...

1. A flexible secondary battery, comprising:an electrode assembly that includes a first electrode layer, a second electrode layer, and a separator between the first and second electrode layers;
a protection film on at least one of an upper surface or a lower surface of the electrode assembly;
a fixing unit, the fixing unit fixing one end portion of each of the first electrode layer, the separator, the second electrode layer, and the protection film; and
a sealing unit, the sealing unit sealing the electrode assembly and the protection film therein such that the protection film is between the electrode assembly and the sealing unit,
wherein a melting point of the protection film is higher than a melting point of the separator,
wherein the protection film includes at least one of polyphthalamide, polyethersulfone, polyphenylene sulfide, polyetherimide, or polyether ether ketone,
wherein the sealing unit includes a first sealing sheet and a second sealing sheet attached to each other and sealing the electrode assembly therein, and
wherein each of the first sealing sheet and the second sealing sheet include a first insulating layer, a metal layer, and a second insulating layer sequentially stacked.

US Pat. No. 10,170,728

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a substrate;
an encapsulation portion on the substrate;
a seal portion between the substrate and the encapsulation portion; and
at least one dummy seal portion adjacent to the seal portion,
wherein:
the substrate and the encapsulation portion at least partially overlap each other in a first direction perpendicular to a surface of the substrate;
the dummy seal portion is, when viewed in the first direction, arranged in an area between an edge of the seal portion and a boundary line of an overlapping area of the substrate and the encapsulation portion;
at least one other display device comprises the substrate; and
a cut line to split the display device from the at least one other display device overlaps the seal portion when viewed in the first direction.

US Pat. No. 10,170,727

DISPLAY DEVICE

Japan Display Inc., Toky...

15. A display device comprising:a first substrate having an insulating surface;
a display region having a plurality of pixels arranged in a matrix on the insulating surface, each of the plurality of pixels having a display element;
a first sealing film on the display element and covering the display element;
a first detection electrode layer on the first sealing film, the first detection electrode having a lower surface being in contact with the first sealing film, an upper surface at an opposite side from the lower surface, and a side surface between the lower surface and the upper surface;
a second sealing film on the first detection electrode layer, the second sealing film covering the upper surface and the side surface of the first detection electrode layer; and
a second detection electrode layer on the second sealing film, the second detection electrode having a lower surface being in contact with the second insulating film, an upper surface at an opposite side from the lower surface, and a side surface between the lower surface and the upper surface.

US Pat. No. 10,170,726

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A method for manufacturing a display device, comprising:forming an insulating film over and in contact with a first substrate with flexibility;
forming a first sealant continuously surrounding a display region over the insulating film;
irradiating the first sealant with a first laser beam;
bonding a second substrate with flexibility to the first substrate with the first sealant;
irradiating the first sealant with a second laser beam;
forming a second sealant continuously surrounding the first sealant in a gap between the first substrate and the second substrate and on a side surface of the first substrate and a side surface of the second substrate; and
forming a member in contact with a side surface of the second sealant,
wherein the member comprises a bottom surface portion in contact with a top surface of the insulating film.

US Pat. No. 10,170,723

ORGANIC LIGHT EMITTING ELEMENT AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. An organic light emitting element comprising:an anode as a first electrode;
a cathode as a second electrode;
an emission layer between the first electrode and the second electrode;
an electron injection layer between the second electrode and the emission layer; and
a barrier layer for controlling electron injection speed and for decreasing emission efficiency by slowing electron injection speed located between the electron injection layer and the second electrode, and having a work function that is larger than a work function of the second electrode,
wherein a work function difference between the barrier layer and the second electrode is less than or equal to about 1.0 eV.

US Pat. No. 10,170,714

DISPLAY PANEL

AU OPTRONICS CORPORATION,...

1. A display panel, having a first substrate and a second substrate disposed on the first substrate, and the display panel comprising a plurality of subpixels, wherein at least one of the subpixels comprises:a switch element, disposed on the first substrate, and comprising a first end, a second end, and a first gate, wherein the first end is electrically connected to a data line that extends in a first direction, the first gate is electrically connected to a scan line that extends in a second direction, and the first direction is not parallel to the second direction;
a driving element, disposed on the first substrate, and comprising a first end, a second end, and a second gate, wherein the first end is electrically connected to a power line, the second gate is electrically connected to the second end of the switch element, and the power line is electrically connected to a first voltage source;
a passivation layer, disposed on the first substrate, and covering the scan line, the data line, the power line, the switch element, the driving element, and the first substrate;
a patterned electrode layer, disposed on the passivation layer of the first substrate, wherein the patterned electrode layer includes a first capacitor electrode and a pixel electrode separated from the first capacitor electrode, the pixel electrode is electrically connected to the second end of the driving element, and the first capacitor electrode is electrically connected to the second end of the switch element;
an electroluminescent layer, located on the pixel electrode of the first substrate;
a counter electrode, disposed on the electroluminescent layer of the first substrate and electrically connected to a second voltage source, wherein the second voltage source is different from the first voltage source;
a conductive bump, protrusively disposed on the first capacitor electrode of the first substrate, wherein the conductive bump comprises a conductive material;
an upper capacitor electrode, disposed on an inner surface of the second substrate; and
a capacitor dielectric layer, covering the upper capacitor electrode of the second substrate, wherein the conductive bump, the capacitor dielectric layer, and the upper capacitor electrode form a storage capacitor.

US Pat. No. 10,170,712

ARTICLES HAVING FLEXIBLE SUBSTRATES

Hewlett-Packard Developme...

1. An article, comprising:flexible substrate;
a first layer disposed over at least a portion of the substrate, the first layer comprising a reflector;
a second layer disposed over at least a portion of the first layer, the second layer comprising an electrode;
a third layer disposed over at least a portion of the second layer, the third Dyer comprising a polymer and a light source;
a fourth layer disposed over at least a portion of the third layer, the fourth layer comprising a diffusor; and
a fifth layer disposed over at least a portion of the fourth layer, the fifth layer comprising at least one of a photochromic material and a thermochromic material.

US Pat. No. 10,170,709

PLATINUM COMPLEX HAVING CARBENE FRAGMENT, OLED USING THE SAME, AND NITROGEN-CONTAINING HETEROCYCLIC BIDENTATE CHELATE HAVING CARBENE UNIT

National Tsing Hua Univer...

1. A platinum complex having a carbene fragment, containing: a platinum cation, a zero-valent first nitrogen-containing heterocyclic bidentate chelate, and a dianionic second nitrogen-containing heterocyclic bidentate chelate, wherein the first nitrogen-containing heterocyclic bidentate chelate has at least one carbene unit coordinating to platinum, and the second nitrogen-containing heterocyclic bidentate chelate has at least one electron-withdrawing substituent and forms two N—Pt bonds, or one N—Pt bond and one C—Pt bond, with the platinum cation,wherein the platinum complex is represented by formula (I) or (II):
wherein X is CH or N, RF is —CmF2m+1 and m is an integer of 1 to 7.

US Pat. No. 10,170,707

COMPOUND, MATERIAL FOR ORGANIC ELECTROLUMINESCENCE ELEMENT, ORGANIC ELECTROLUMINESCENCE ELEMENT, AND ELECTRONIC DEVICE

IDEMITSU KOSAN CO., LTD.,...

1. A compound represented by formula (1):wherein:each of R1 to R6 is independently a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 ring carbon atoms, a substituted or unsubstituted aryl group having 6 to 18 ring carbon atoms, a substituted or unsubstituted haloalkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 18 ring carbon atoms, a halogen atom, or a cyano group;
one of R7 to R10 is a single bond bonded to *a, and each of the others of R7 to is independently a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 ring carbon atoms, a substituted or unsubstituted aryl group having 6 to 18 ring carbon atoms, a substituted or unsubstituted haloalkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 18 ring carbon atoms, a halogen atom, or a cyano group;
one of R11 to R14 is a single bond bonded to *b, and each of the others of R11 to R14 is independently a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 ring carbon atoms, a substituted or unsubstituted aryl group having 6 to 18 ring carbon atoms, a substituted or unsubstituted haloalkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 18 ring carbon atoms, a halogen atom, or a cyano group;
each of R15 to R18 is independently a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 ring carbon atoms, a substituted or unsubstituted aryl group having 6 to 18 ring carbon atoms, a substituted or unsubstituted haloalkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 18 ring carbon atoms, a halogen atom, or a cyano group;
with the proviso that each of adjacent two groups selected from R1 to R6, adjacent two groups selected from R7 to R10, adjacent two groups selected from R11 to R14, and adjacent two groups selected from R15 to R18 may be respectively bonded to each other to form a substituted or unsubstituted ring;
each of L1 and L2 is independently a single bond, a substituted or unsubstituted arylene group having 6 to 18 ring carbon atoms, or a substituted or unsubstituted heteroarylene group having 5 to 18 ring atoms; and
each of Ar1 and Ar2 is independently a substituted or unsubstituted aryl group having 6 to 18 ring carbon atoms;
provided that at least one selected from Ar1 and Ar2 is a substituted or unsubstituted fluoranthenyl group.

US Pat. No. 10,170,705

ORGANIC LIGHT-EMITTING DEVICE

Samsung Display Co., Ltd....

1. An organic light-emitting device, comprisinga first electrode;
a second electrode facing the first electrode;
an emission layer between the first electrode and the second electrode; and
an electron transport region between the emission layer and the second electrode;
wherein the electron transport region includes at least one condensed cyclic compound selected from the following Compounds 1 to 360:



US Pat. No. 10,170,703

CONDENSED CYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A condensed cyclic compound represented by Formula 1:
wherein, in Formula 1,
ring A1 and ring A2 are each independently selected from a benzene, a naphthalene, a pyridine, a pyrimidine, a pyrazine, a quinoline, an isoquinoline, a quinoxaline, a quinazoline, and a cinnoline, at least one of ring A1 and ring A2 is selected from a naphthalene, a pyridine, a pyrimidine, a pyrazine, a quinoline, an isoquinoline, a quinoxaline, a quinazoline, and a cinnoline,
X1 is N-[(L11)a11-(R11)b11], O, or S,
L1, L2, and L11 are each independently selected from a substituted or unsubstituted C3-C10 cycloalkylene group, a substituted or unsubstituted C1-C10 heterocycloalkylene group, a substituted or unsubstituted C3-C10 cycloalkenylene group, a substituted or unsubstituted C1-C10 heterocycloalkenylene group, a substituted or unsubstituted C6-C6 arylene group, a substituted or unsubstituted C1-C60 heteroarylene group, a substituted or unsubstituted divalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted divalent non-aromatic condensed heteropolycyclic group,
a1 and a2 are each independently an integer of 1 to 5, a11 is an integer of 0 to 5, wherein when a1 is 2 or more, two or more L1s are identical to or different from each other, when a2 is 2 or more, two or more L2s are identical to or different from each other, and when a11 is 2 or more, two or more L11s are identical to or different from each other,
R1 to R6 and R11 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, —N(Q1)(Q2), —Si(Q3)(Q4)(Q5), and —B(Q6)(Q7),
b1, b2, b5, b6, and b11 are each independently an integer of 0 to 4,
b3 and b4 are each independently an integer of 0 to 6,
c1 and c2 are each independently an integer of 0 to 4, a sum of c1 and c2 being 1 to 8, and
at least one substituent of the substituted C3-C10 cycloalkylene group, substituted C1-C10 heterocycloalkylene group, substituted C3-C10 cycloalkenylene group, substituted C1-C10 heterocycloalkenylene group, substituted C6-C60 arylene group, substituted C1-C60 heteroarylene group, substituted divalent non-aromatic condensed polycyclic group, substituted divalent non-aromatic condensed heteropolycyclic group, substituted C1-C60 alkyl group, substituted C2-C60 alkenyl group, substituted C2-C60 alkynyl group, substituted C1-C60 alkoxy group, substituted C3-C10 cycloalkyl group, substituted C1-C10 heterocycloalkyl group, substituted C3-C10 cycloalkenyl group, substituted C1-C10 heterocycloalkenyl group, substituted C6-C60 aryl group, substituted C6-C60 aryloxy group, substituted C6-C60 arylthio group, substituted C1-C60 heteroaryl group, substituted monovalent non-aromatic condensed polycyclic group, and substituted monovalent non-aromatic condensed heteropolycyclic group is selected from:
deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group;
a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —N(Q11)(Q12), —Si(Q13)(Q14)(Q15), and —B(Q16)(Q17);
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group;
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —N(Q21)(Q22), —Si(Q23)(Q24)(Q25), and —B(Q26)(Q27); and
—N(Q31)(Q32), —Si(Q33)(Q34)(Q35), and —B(Q36)(Q37),
wherein Q1 to Q7, Q1 to Q17, Q21 to Q27, and Q31 to Q37 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group.

US Pat. No. 10,170,694

MAGNETIC MEMORY

KABUSHIKI KAISHA TOSHIBA,...

1. A magnetic memory comprising:a first terminal and a second terminal;
a first conductive layer, which is nonmagnetic and includes at least a first element, the first conductive layer including a first region, a second region, a third region, a fourth region, and a fifth region, the second region being disposed between the first region and the fifth region, the third region being disposed between the second region and the fifth region, the fourth region being disposed between the third region and the fifth region, the first region being electrically connected to the first terminal, and the fifth region being electrically connected to the second terminal;
a first magnetoresistive element disposed to correspond to the third region, the first magnetoresistive element including a first magnetic layer, a second magnetic layer disposed between the first magnetic layer and the third region and including at least a second element, a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer, a second nonmagnetic layer disposed between the second magnetic layer and the first nonmagnetic layer and including at least a third element, and a third magnetic layer disposed between the second nonmagnetic layer and the first nonmagnetic layer;
a second conductive layer disposed to correspond to the second region, electrically connected to the second region, the second magnetic layer, and the second nonmagnetic layer, and including at least the first element, the second element, and the third element; and
a third conductive layer disposed to correspond to the fourth region, electrically connected to the fourth region, the second magnetic layer, and the second nonmagnetic layer, and including at least the first element, the second element, and the third element.

US Pat. No. 10,170,686

ELECTRIC ENERGY HARVESTER USING ULTRASONIC WAVE

1. An electric energy generator system comprising:an ultrasonic-wave emission device configured to generate an ultrasonic-wave and emit the ultrasonic-wave; and
an electric energy generator device configured to generate an electric energy upon a receipt of the emitted ultrasonic-wave,
wherein the electric energy generator device comprises:
a substrate;
an electrode on the substrate;
a first friction-charged member on the electrode;
a spacer disposed on the substrate and configured to surround the electrode and the first friction-charged member; and
a second friction-charged member disposed on the spacer to be spaced from the first friction-charged member,
wherein the second friction-charged member repeatedly contacts or is separated from the first friction-charged member, and
wherein a closed inner space is defined between the first friction-charged member and the second friction-charged member and the spacer.

US Pat. No. 10,170,682

DIELECTRIC ELASTOMER ACTUATOR

The Regents of the Univer...

1. A dielectric elastomer actuator (DEA) comprising:an elastomeric film presenting a first side and a second side, opposing the first side;
wherein the elastomeric film includes a first section, a second section, and a transition section disposed in an axial direction, between the first section and the second section;
an electrode material layer disposed on the transition section and at least one of the first section and the second section, on each of the first side and the second side, wherein the electrode material layer is electrically conductive;
wherein the first section and the second section are restrained in a pre-stretched configuration in each of the axial direction and a lateral direction, perpendicular to the axial direction;
wherein the transition section is not restrained in a pre-stretched configuration in the axial direction and is partially restrained in a pre-stretched configuration in the lateral direction as a function of the restraint of the first section and the second section in the pre-stretched configuration;
wherein the transition section is configured to elongate in the axial direction in response to the application of a voltage to the electrode material layers, such that the first section and the second section move away from one another, in the axial direction; and
wherein the transition section is configured to contract in the axial direction in an absence of a voltage applied to the electrode material layers, such that the first section and the second section move toward one another, in the axial direction.

US Pat. No. 10,170,671

METHODS OF FILLING A FLOWABLE MATERIAL IN A GAP OF AN ASSEMBLY MODULE

1. A method to fill an flowable material into a gap region in a semiconductor assembly module comprising:forming multiple semiconductor units on a substrate to create an array module;
attaching the array module to a backplane having circuitry to form the semiconductor assembly module having multiple gap regions inside the semiconductor assembly module and edge gap regions surround an edge of the semiconductor assembly module;
dispensing a flowable material on an edge of the semiconductor assembly module;
providing a high acting pressure environment to force the flowable material into the semiconductor assembly module gap regions;
creating voids in the gap region of the semiconductor assembly module by reducing the high acting pressure and;
applying heat or a photon energy to harden the flowable material to retain the harden flowable material and the voids in the gap regions.

US Pat. No. 10,170,638

NANOSHEET SUBSTRATE ISOLATED SOURCE/DRAIN EPITAXY BY DUAL BOTTOM SPACER

International Business Ma...

1. A semiconductor structure comprising:a plurality of stacked and suspended semiconductor channel material nanosheets located above a semiconductor substrate;
a functional gate structure surrounding a portion of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets;
a source/drain (S/D) region on each side of the functional gate structure and physically contacting sidewalls of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets; and
a dual spacer structure located on surfaces of the semiconductor substrate that are located adjacent the functional gate structure, wherein the dual spacer structure separates the source/drain region from the semiconductor substrate.

US Pat. No. 10,170,637

PERFECTLY SYMMETRIC GATE-ALL-AROUND FET ON SUSPENDED NANOWIRE

INTERNATIONAL BUSINESS MA...

1. A method of forming as semiconductor device comprising:forming a first replacement gate structure of light sensitive material is present on a channel region portion of the stack of suspended nanowires;
replacing the first replacement gate structure of the light sensitive material with a second replacement gate structure of a semiconductor gate material;
applying a surface treatment process to at least sidewall surfaces of the second replacement gate structure to convert a portion of the semiconductor gate material to a dielectric spacer on said at least the sidewall surfaces of the second replacement gate structure; and
replacing the second replacement gate structure with a functional gate structure.

US Pat. No. 10,170,633

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, the method comprising the steps of:forming an oxide semiconductor film over a substrate;
forming a conductive film over the oxide semiconductor film;
heating the conductive film formed over the oxide semiconductor film;
forming a first resist mask over the conductive film;
etching the conductive film using the first resist mask to form a source electrode and a drain electrode;
forming a second resist mask over the oxide semiconductor film after etching the conductive film;
etching the oxide semiconductor film using the second resist mask,
forming a gate insulating film over the oxide semiconductor film; and
forming a gate electrode over the gate insulating film.

US Pat. No. 10,170,628

METHOD FOR FORMING AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) DEVICE HAVING REDUCED PARASITIC CAPACITANCE AND CONTACT RESISTANCE DUE TO WRAP-AROUND STRUCTURE OF SOURCE/DRAIN REGIONS

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, comprising:forming first spacers on sides of a gate structure and second spacers on the first spacers;
etching a semiconductor layer below the gate structure using the second spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure;
forming undercuts in a buried dielectric layer below the semiconductor layer; and
epitaxially growing source and drain regions wrapped around the semiconductor layer from a top of the semiconductor layer and into the undercuts on an opposite side of the semiconductor layer.

US Pat. No. 10,170,620

SUBSTANTIALLY DEFECT FREE RELAXED HETEROGENEOUS SEMICONDUCTOR FINS ON BULK SUBSTRATES

International Business Ma...

1. A semiconductor structure comprising:a bulk semiconductor substrate of a first semiconductor material;
a plurality of spaced apart fin pedestal structures of a second semiconductor material located on said bulk semiconductor substrate of said first semiconductor material, wherein said second semiconductor material is different from said first semiconductor material;
a pair of spaced apart semiconductor fins of said second semiconductor material located on each fin pedestal structure, wherein one of said semiconductor fins of said pair of spaced apart semiconductor fins has a sidewall surface that is vertically aligned with a sidewall surface of a first end of each of said fin pedestal structures and another of said semiconductor fins of said pair of spaced apart semiconductor has a sidewall surface that is vertically aligned with a sidewall surface of a second end of each of said fin pedestal structures;
a first dielectric material structure located between each semiconductor fin of said pair of semiconductor fins, said first dielectric material structure is located on an exposed topmost surface of each of said fin pedestal structures; and
a second dielectric material structure located between each fin pedestal structure and present on said bulk semiconductor substrate, wherein said first and second dielectric material structures comprise a dielectric material having an upper undoped region and a lower doped region, and wherein said lower doped region of the first dielectric material structure has a topmost surface that is coplanar with a topmost surface of said lower doped region of said second dielectric material structure, and wherein said upper doped region of the first dielectric material structure has a topmost surface that is coplanar with a topmost surface of said upper doped region of said second dielectric material structure.

US Pat. No. 10,170,615

SEMICONDUCTOR DEVICE INCLUDING A LATERAL TRANSISTOR

Infineon Technologies Aus...

1. A semiconductor device, comprising:a drift contact region;
a drain region of a first conductivity type, the drift contact region and the drain region being arranged in a first direction parallel to a first main surface of a semiconductor substrate;
a layer stack comprising a drift layer of the first conductivity type and a compensation layer of a second conductivity type, the drain region being electrically connected with the drift layer;
a body region of the second conductivity type;
a connection region of the second conductivity type extending from the first main surface of the semiconductor substrate and into the layer stack, the connection region being electrically connected with the compensation layer; and
a buried semiconductor portion beneath the layer stack and in electrical contact with the connection region,
wherein the buried semiconductor portion does not fully overlap with the drift layer,
wherein in the first direction, the layer stack is interposed between the drain region and the drift contact region and the drift contact region is interposed between the layer stack and the body region.

US Pat. No. 10,170,613

SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a first transistor disposed on the semiconductor substrate, the first transistor including:
a first semiconductor layer;
an active region in the first semiconductor layer; and
a first conductive layer underlying the first semiconductor layer; and
a second transistor disposed on the semiconductor substrate, the second transistor including:
a second semiconductor layer;
another active region in the second semiconductor layer; and
a second conductive layer underlying the second semiconductor layer and electrically isolated from the first conductive layer.

US Pat. No. 10,170,612

EPITAXIAL BUFFER LAYERS FOR GROUP III-N TRANSISTORS ON SILICON SUBSTRATES

Intel Corporation, Santa...

1. A semiconductor material stack, comprising:a silicon substrate having a first lattice constant;
a group III-N device layer disposed over the silicon substrate, the group III-N device layer having a second lattice constant different than the first lattice constant;
a buffer disposed between the silicon substrate and the group III-N device layer, wherein the buffer includes an AlxIn1-xN layer, with x being less than unity; a top barrier layer formed above the group III-N device layer;
N-type group III-N source and drain regions disposed on the top barrier layer;
a gate electrode disposed between the N-type group III-N source and drain regions, wherein the top barrier layer has a first thickness between the gate electrode and the group III-N device layer and a second, greater, thickness between the N-type group III-N source and drain regions and the group III-N device layer, and
a third thickness between a spacer region disposed between the gate electrode and each of the group III-N source and drain regions and the group III-N device layer, wherein the third thickness is intermediate to the first thickness and the second thickness and a gate dielectric disposed below the gate electrode and adjacent to sidewalls of the gate electrode.

US Pat. No. 10,170,611

T-GATE FIELD EFFECT TRANSISTOR WITH NON-LINEAR CHANNEL LAYER AND/OR GATE FOOT FACE

HRL Laboratories, LLC, M...

1. A high electron mobility transistor (HEMT) comprising:a source contact spaced apart from a drain contact by a distance in a first direction;
a gate disposed between the source and drain contacts extending in a second direction perpendicular to the first direction comprising a gate head and a gate foot;
a first surface and a second surface of a channel;
a top barrier layer forming a 2DEG in the channel, wherein a surface of the source contact contacts a first surface of the channel and a first surface of the top barrier layer, and a surface of the drain contact contacts a second surface of the channel and a second surface of the top barrier layer, the first surface and the second surface of the channel facing away from one another;
wherein the gate foot comprises a curved section, and a contour width of the gate foot is greater than a superficial width of the gate head,
the first and second surfaces of the channel having sections with curved shapes related to the shape of the curved section of the gate foot, and
the curved section of the gate foot does not include a straight section.

US Pat. No. 10,170,554

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a gate structure on a substrate, the gate structure comprising:
a gate dielectric layer, disposed on the substrate;
a raised source/drain region adjacent to the gate structure, the raised source/drain region comprising a tip region under the gate structure;
a channel region under gate dielectric layer of the gate structure; and
a protection layer, wherein:
the protection layer is interposed between the substrate and the raised source/drain region, and
an atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region, and the atom stacking arrangement of the protection layer is an amorphous state having a higher degree of lattice disorder than that of the substrate and the raised source/drain region, and the protection layer has a first end portion with the amorphous state formed between the tip region under the gate structure and the channel region under the gate dielectric layer.

US Pat. No. 10,170,536

MAGNETIC MEMORY WITH METAL OXIDE ETCH STOP LAYER AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a first passivation layer over the substrate;
a second passivation layer over the first passivation layer;
a magnetic layer in the second passivation layer; and
an etch stop layer between the magnetic layer and the first passivation layer, wherein the etch stop layer is in contact with the magnetic layer, and the etch stop layer includes at least one acid resistant layer, and the acid resistant layer includes a metal oxide.

US Pat. No. 10,170,527

ORGANIC LIGHT EMITTING DIODE DISPLAY

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting diode display, comprising:a substrate including a pixel region and a peripheral region enclosing the pixel region;
a scan line on the substrate and transferring a scan signal;
a data line crossing the scan line and transferring a data voltage;
a switching transistor disposed in the pixel region and electrically connected to the scan line and the data line;
a driving transistor disposed in the pixel region and electrically connected to the switching transistor;
a pixel-area passivation layer disposed on the switching transistor and the driving transistor;
a pixel electrode disposed on the pixel-area passivation layer;
a pixel partition wall layer disposed on the pixel-area passivation layer and having a pixel opening overlapping the pixel electrode;
an organic light emission layer disposed in the pixel opening and disposed on the pixel electrode;
a common electrode disposed on the organic light emission layer and the pixel partition wall layer;
a common voltage line disposed in the peripheral region and electrically connected to the common electrode;
a peripheral passivation layer disposed in the peripheral region and contacting a side wall of the common voltage line;
a peripheral driving voltage line disposed in the peripheral region and which transfers a driving voltage ELVDD;
a driving voltage pad to which the driving voltage ELVDD is applied from the outside;
a driving voltage connecting part connecting the driving voltage pad and the peripheral driving voltage line,
wherein the driving voltage pad is disposed at the same layer as the common voltage line.

US Pat. No. 10,170,512

UNIFORM-SIZE BONDING PATTERNS

Taiwan Semiconductor Manu...

15. A method comprising:forming an image sensor comprising:
depositing a first passivation layer over a first substrate, the first substrate having a plurality of photosensitive elements therein;
forming a first plurality of bonding pads in the first passivation layer, the first plurality of bonding pads having a first width and a first pitch; and
forming a second plurality of bonding pads in the first passivation layer, the second plurality of bonding pads having the first width, the second plurality of bonding pads being grouped into clusters, the second plurality of bonding pads having a second pitch between neighboring clusters and the first pitch between adjacent bonding pads in a first cluster, the first pitch being smaller than the second pitch;
forming a second substrate comprising:
forming a second passivation layer over a second substrate; and
forming a third plurality of hybrid bonding pads in the second passivation layer; and
bonding the second substrate is to the image sensor such that the first plurality of bonding pads and the second plurality of bonding pads are coupled with respective ones of the third plurality of bonding pads.

US Pat. No. 10,170,505

DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A display apparatus comprising:a substrate comprising a display area and a peripheral area outside the display area;
a display unit over an upper surface of the substrate to correspond to the display area; and
a protective film comprising a protective film base and an adhesive layer, the protective film being attached to a lower surface of the substrate by the adhesive layer,
wherein the protective film base comprises a first protective film base corresponding at least to the display area, and a second protective film base having a physical property that is different from a physical property of the first protective film base and corresponding to at least a part of the peripheral area, and
wherein the second protective film base has a light transmittance that is greater than a light transmittance of the first protective film base.

US Pat. No. 10,170,493

ASSEMBLIES HAVING VERTICALLY-STACKED CONDUCTIVE STRUCTURES

Micron Technology, Inc., ...

1. An assembly, comprising:a stack of alternating first and second levels; the first levels comprising insulative material, and the second levels comprising conductive material; the assembly including channel material structures extending through the stack, and including insulative panel structures extending through the stack; the conductive material within the second levels having outer edges; the outer edges having proximal regions near the insulative panel structures and distal regions spaced from the insulative panel structures by the proximal regions; and
interface material along the outer edges of the conductive material, the interface material having a first composition along the proximal regions of the outer edges, and having a second composition along the distal regions of the outer edges; the first composition being different than the second composition.

US Pat. No. 10,170,492

MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A memory device, comprising:a semiconductor substrate;
a first conductive layer, disposed on the semiconductor substrate;
a plurality insulating layers, disposed on the first conductive layer;
a plurality of second conductive layers, alternatively stacked with the insulating layers and insulated from the first conductive layer;
at least one contact plug comprising a first conductive material, passing through the insulating layers and the second conductive layers, insulated from the second conductive layers and electrically contacting to the first conductive layer; and
at least one dummy plug, formed in an opening passing through a bottommost layer of the insulating layers and the second conductive layers, corresponding to the at least one contact plug, wherein the at least one dummy plug comprises a dielectric isolation layer formed on a sidewall and a bottom of the opening and a second conductive material fully filling the opening and insulated from the second conductive layers and the first conductive layer.

US Pat. No. 10,170,491

MEMORY INCLUDING BLOCKING DIELECTRIC IN ETCH STOP TIER

Micron Technology, Inc., ...

1. A memory comprising:a vertical pillar coupled to a source; and
a dielectric etch stop tier over the source, the dielectric etch stop tier comprising a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the dielectric etch stop tier and separating the dielectric etch stop tier into multiple dielectric tiers.

US Pat. No. 10,170,490

MEMORY DEVICE INCLUDING PASS TRANSISTORS IN MEMORY TIERS

Micron Technology, Inc., ...

1. An apparatus comprising:a piece of semiconductor material formed over a substrate;
a pillar extending through the piece of semiconductor material;
a select gate located along a first portion of the pillar;
memory cells located along a second portion of the pillar; and
transistors coupled to the select gate through a portion of the piece of semiconductor material, the transistors including sources and drains, the transistors including gates electrically uncoupled to each other, and at least a portion of the piece of semiconductor material forms the sources and drains of the transistors, and a portion of the select gate.

US Pat. No. 10,170,488

NON-VOLATILE MEMORY OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANF...

1. A semiconductor device, comprising:a substrate having a surface;
a plurality of isolation structures disposed in the substrate to at least define a first region, a second region, and a third region on the substrate;
a floating gate memory cell disposed in the first region, wherein the floating gate memory cell comprises:
an erase gate structure disposed on the surface of the substrate;
a first floating gate structure and a second floating gate structure recessed in the substrate and located at two opposite sides of the erase gate structure;
a first word line disposed on the surface of the substrate, wherein the first word line is adjacent to the first floating gate structure opposite to the erase gate structure;
a common source disposed in the substrate between the first floating gate structure and the second floating gate structure;
a second word line disposed on the surface of the substrate, wherein the second word line is adjacent to the second floating gate structure opposite to the erase gate structure;
a first spacer disposed between the first floating gate structure and the first word line; and
a second spacer disposed between the second floating gate structure and the second word line;
a first device disposed in the second region; and
a second device disposed in the third region.

US Pat. No. 10,170,487

DEVICE HAVING AN INTER-LAYER VIA (ILV), AND METHOD OF MAKING SAME

TAIWAN SEMICONDUCTOR MANU...

1. A three-dimensional integrated circuit comprising:a first transistor on a first level;
a word line coupled to the first transistor;
a first via coupled to the first transistor;
a second transistor on a second level different from the first level;
another word line coupled to the second transistor; and
a second via coupled between the first transistor and the second transistor.

US Pat. No. 10,170,486

SEMICONDUCTOR STORAGE DEVICE COMPRISING PERIPHERAL CIRCUIT, SHIELDING LAYER, AND MEMORY CELL ARRAY

Semiconductor Energy Labo...

1. A semiconductor storage device comprising:a first transistor;
a conductive film over the first transistor; and
a plurality of second transistors each comprising a channel region,
wherein a channel region of the first transistor comprises silicon,
wherein each of the plurality of channel regions of second transistors comprises an oxide semiconductor, and
wherein entirety of the plurality of second transistors overlaps with the conductive film.

US Pat. No. 10,170,480

METHODS FOR MANUFACTURING A FIN-BASED SEMICONDUCTOR DEVICE INCLUDING A METAL GATE DIFFUSION BREAK STRUCTURE WITH A CONFORMAL DIELECTRIC LAYER

TAIWAN SEMICONDUCTOR MANU...

16. A method of forming a fin-like field-effect transistor (FinFET) device, the method comprising:forming a first active region and a second active region on a substrate, such that the first active region and the second active region are spaced apart from each other in a first direction;
forming a first group of fins in the first active region and a second group of fins in the second active region, such that each fin of the first and second groups of fins extends along a second direction substantially perpendicular to the first direction;
forming one or more gates over the first active region and the second active region along the first direction, the one or more gates including a first isolation gate and a functional gate;
forming a first sidewall spacer along the first isolation gate; and
forming a source/drain feature on a side of the first sidewall spacer and extending into the substrate to a first depth,
wherein the first isolation gate includes a dielectric layer and a metal gate layer, the first isolation gate formed in a trench in the substrate, the dielectric layer conformed to a side surface of the first sidewall spacer and extending along the first sidewall spacer and into the substrate such that the dielectric layer physically contacts the first sidewall spacer, the source/drain feature, and the substrate at a bottom of the trench, the metal gate layer extending into the substrate to a second depth that is greater than the first depth.

US Pat. No. 10,170,471

BULK FIN FORMATION WITH VERTICAL FIN SIDEWALL PROFILE

International Business Ma...

1. A semiconductor device, comprising:a base layer; and
a plurality of fins atop the base layer, wherein:
each fin comprises:
an undoped silicon oxide fin layer atop the base layer;
a doped silicon oxide fin layer atop the undoped silicon oxide fin layer;
a silicon fin layer atop the doped silicon oxide fin layer; and
a hard mask cap atop the silicon fin layer;
each fin has a uniform width along a height of the respective fin along a first direction;
the height spans from an upper surface of the base layer to an upper surface of the hard mask cap; and
the first direction is a direction that intersects a first fin and a second fin of the plurality of fins.

US Pat. No. 10,170,470

SWITCHING DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A switching device, comprising:a semiconductor substrate;
a plurality of gate trenches provided in an upper surface of the semiconductor substrate;
bottom insulating layers covering bottom surfaces of the gate trenches;
gate insulating layers covering side surfaces of the gate trenches; and
gate electrodes arranged in the gate trenches and insulated from the semiconductor substrate by the bottom insulating layers and the gate insulating layers,
wherein
a device region is a region in the upper surface in which the plurality of gate trenches is provided,
the device region includes a peripheral portion provided at a periphery of the device region and a center portion surrounded by the peripheral portion, the gate insulating layers being located in the peripheral portion and the center portion,
the gate insulating layers in the center portion have a first thickness and a first dielectric constant,
one or more of the gate insulating layers in the peripheral portion has, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant, and
the semiconductor substrate comprises:
a first region being of a first conductivity type and in contact with the gate insulating layers in the center portion and the peripheral portion;
a body region being of a second conductivity type and in contact with the gate insulating layers under the first region in the center portion and the peripheral portion; and
a second region being of the first conductivity type and in contact with the gate insulating layers under the body region in the center portion and the peripheral portion.

US Pat. No. 10,170,469

VERTICAL FIELD-EFFECT-TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES

International Business Ma...

1. A semiconductor structure comprising:a first vertical field-effect transistor comprising a first threshold voltage; and
at least a second vertical field-effect transistor comprising a second threshold voltage that is different from the first threshold voltage,
wherein each of the first vertical field-effect transistor and the second vertical field-effect transistor comprises
a source layer and a drain layer, wherein each drain layer is formed in a region of the first vertical field-effect transistor and second vertical field-effect transistor, respectively, above the source layer,
substrate in contact with the source layer,
a first spacer layer on the source layer,
a second spacer layer, where a portion of the drain layer extends over the second spacer, and
metal gate in contact with sidewalls of the epitaxially grown channel layer, a top surface of the first spacer layer, and a bottom surface of the second spacer layer.

US Pat. No. 10,170,467

THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A three dimensional (3D) semiconductor memory device, comprising:a semiconductor substrate, having a first protruding portion;
a first transistor formed in the semiconductor substrate, comprising:
a first source line, disposed in the semiconductor substrate and partially extending below the first protruding portion;
a first gate line configured to surround and cover the first protruding portion and electrically separated from the first source line and the first protruding portion; and
a first drain electrode formed on and connecting to the first protruding portion;
a plurality of conductive planes stacked on the semiconductor substrate and electrically separated from each other;
a first conductive pillar passing through the conductive planes and connecting to the first drain electrode;
a first memory layer disposed between the conductive planes and the first conductive pillar; and
a plurality of memory cells formed at a plurality points of intersection correspondingly formed between the conductive planes, the first conductive pillar and the memory layer; and connected in series by the first conductive pillar.

US Pat. No. 10,170,465

CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE

International Business Ma...

9. A method of forming a vertical fin field effect transistor (finFET) and a vertical diode device on the same substrate, comprising:forming a bottom spacer layer on a substrate;
forming a dummy gate layer on the bottom spacer layer;
forming a top spacer layer on the dummy gate layer;
forming one or more fin trenches, where at least one of the one or more fin trenches passes through the top spacer layer, the dummy gate layer, and the bottom spacer layer;
forming a vertical fin in at least one of the one or more fin trenches;
forming one or more diode trenches, where at least one of the one or more diode trenches passes through the top spacer layer, the dummy gate layer, and the bottom spacer layer;
forming a first semiconductor segment in a lower portion of at least one of the one or more diode trenches; and
forming a second semiconductor segment in an upper portion of the at least one of the one or more diode trenches with the first semiconductor segment, wherein the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

US Pat. No. 10,170,463

BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION

INTERNATIONAL BUSINESS MA...

1. A method for fabricating two transistors, comprising:forming a first semiconductor fin and a second semiconductor fin, where each of the first and second semiconductor fins comprises a doped lower portion;
forming lower spacers around the first and second semiconductor fins, the lower spacer around the first semiconductor fin having a height lower than a height of the lower spacer around the second semiconductor fin;
forming a gate stack around the first semiconductor fin and the second semiconductor fin;
wherein the height of the lower spacer around the first semiconductor fin rises below a level of the doped lower portion of the first semiconductor fin and wherein the height of the lower spacer around the second semiconductor fin rises above a level of the doped lower portion of the second semiconductor fin;
forming an upper spacer around the first and second semiconductor fin and over the gate stacks;
etching away the gate stack around the second semiconductor fin; and
forming an extrinsic base around the second semiconductor fin and under the upper spacer in a region exposed by etching away the gate stack.

US Pat. No. 10,170,462

DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device comprising a display panel including an active area where an image is displayed and a pad area corresponding to a non-display area, the display device comprising:a first substrate and a second substrate, which face each other;
an organic light emitting diode arranged on the first substrate in the active area;
a signal pad arranged on the first substrate in the pad area;
a connection electrode connected with one side of the signal pad; and
a flexible circuit film connected with the connection electrode,
wherein the signal pad includes a plurality of lines arranged by interposing an insulating film therebetween, and the plurality of lines are electrically connected with each other, and
wherein the signal pad includes at least two lines of a first line arranged on the same layer as a gate line arranged in the active area, a second line arranged on the same layer as a data line arranged in the active area, and a third line arranged on the same layer as a pixel electrode arranged in the active area.

US Pat. No. 10,170,460

VOLTAGE BALANCED STACKED CLAMP

International Business Ma...

1. An apparatus for balancing voltages, comprising:a voltage supply pin operatively connected to a voltage divider, wherein the voltage supply pin supplies a total voltage to the voltage divider;
a stacked circuit operatively connected to the voltage divider, wherein the stacked circuit comprises a first layer and a second layer, wherein the first layer is not coupled to the second layer, and the voltage divider distributes the total voltage as to the stacked circuit;
a voltage grounder operatively connected to the voltage divider and wherein the first layer and the second layer comprise:
a group of inverters within the first layer operatively connected to a first n-type channel field effect transistor (NFET), wherein the group of inverters within the first layer comprise:
a first inverter, a second inverter, and a third inverter, wherein
the first inverter connects the voltage divider to the second inverter, the second inverter connects to the third inverter, and wherein the third inverter connects to the first n-type channel field effect transistor (NFET); and
a group of inverters within the second layer operatively connected to a second n-type channel field effect transistor (NFET), wherein the group of inverters within the second layer comprise:
a first inverter, a second inverter, and a third inverter, wherein
the first inverter connects the voltage divider to the second inverter, the second inverter connects to the third inverter, and wherein the third inverter connects to the second n-type channel field effect transistor (NFET); and
a third node, wherein the third node is point (principal nodes or junctions) coupled to a first p-type field effect transistor (PFET) at a gate terminal of the first PFET, the second inverter, and the third inverter of the first layer.

US Pat. No. 10,170,457

COWOS STRUCTURES AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method, comprising:attaching a first die and a second die to an interposer;
attaching a first substrate to a first surface of the first die and a first surface of the second die, the first substrate comprising silicon, the first surface of the first die being opposite to a second surface of the first die that is attached to the interposer, and the first surface of the second die being opposite to a second surface of the second die that is attached to the interposer;
forming a plurality of electrical connectors over the interposer, each electrical connector of the plurality of electrical connectors being electrically connected to a respective through via of a plurality of through vias comprised in the interposer, wherein the first substrate physically supports the interposer during the forming of the plurality of electrical connectors;
bonding the interposer to a second substrate using the plurality of electrical connectors; and
attaching a heat dissipation lid to the second substrate, the interposer being disposed in an inner cavity of the heat dissipation lid.

US Pat. No. 10,170,456

SEMICONDUCTOR PACKAGES INCLUDING HEAT TRANSFERRING BLOCKS AND METHODS OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer and laterally spaced apart from each other;
a heat transferring block disposed between the first and second semiconductor chips to be mounted on the interconnection layer;
an encapsulant filling spaces between the heat transferring block and the first and second semiconductor chips and covering sidewalls of the first and second semiconductor chips; and
a heat dissipation layer connected to a top surface of the heat transferring block opposite to the interconnection layer and extending to cover a top surface of the encapsulant,
wherein the heat transferring block emits heat trapped in a region of the encapsulant between the first and second semiconductor chips,
wherein the heat transferring block comprises a through via to emit the heat, and
the through via is electrically isolated from the interconnection layer and the first and second semiconductor chips.

US Pat. No. 10,170,454

METHOD AND APPARATUS FOR DIRECT TRANSFER OF SEMICONDUCTOR DEVICE DIE FROM A MAPPED WAFER

1. A system for performing a direct transfer of a plurality of semiconductor die from a first substrate to a second substrate, the system comprising:a first conveyance mechanism to convey the first substrate;
a second conveyance mechanism to convey the second substrate;
a transfer mechanism disposed adjacent to the first conveyance mechanism to effectuate the direct transfer;
a controller including one or more processors communicatively coupled with the first conveyance mechanism, the second conveyance mechanism, and the transfer mechanism, the controller having executable instructions, which when executed, cause the one or more processors to perform operations including:
determining positions of the plurality of semiconductor die based at least in part on map data, the map data describing the positions of the plurality of semiconductor die of a semiconductor wafer,
conveying at least one of the first substrate or the second substrate such that the first substrate, the second substrate, and the transfer mechanism are in a direct transfer position, and
activating the transfer mechanism to perform the direct transfer of the plurality of semiconductor die.

US Pat. No. 10,170,451

SEMICONDUCTOR DEVICE METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:encapsulating a semiconductor die, a first set of through vias, and a reference via with an encapsulant;
exposing the first set of through vias and the reference via with a planarization process on a first side of the semiconductor die;
connecting the first set of through vias on a second side of the semiconductor die opposite the first side to a second semiconductor die; and
after the connecting the first set of through vias, exposing a first surface of the reference via with a singulation process.

US Pat. No. 10,170,450

METHOD FOR BONDING AND INTERCONNECTING INTEGRATED CIRCUIT DEVICES

IMEC vzw, Leuven (BE)

1. A method for bonding and interconnecting a first IC device arranged on a first substrate to a second IC device arranged on a second substrate, wherein each IC device comprises a dielectric bonding layer at its outer surface, and wherein each IC device further comprises one or more metal contact structures, the method comprising:producing at least one cavity in the outer surface of the first IC device, the cavity traversing at least the dielectric bonding layer of the first IC device;
aligning the first substrate with respect to the second substrate, and forming a substrate assembly by direct bonding between the dielectric bonding layers, so that in the substrate assembly the cavity formed in the first IC device overlaps a metal contact structure of the second IC device;
after bonding, optionally thinning the first substrate;
producing a Through Substrate Via (TSV) opening in the first substrate, the TSV opening overlapping the cavity;
forming an aggregate opening comprising the TSV opening and the cavity, thereby exposing at least part of the metal contact structure of the second IC device;
after the formation of an isolation liner on at least part of the sidewalls of the aggregate opening, producing a metal interconnection plug in the aggregate opening, that contacts the metal contact structure of the second IC device, and forms at least part of an interconnection path between the metal contact structure of the second IC device and a metal contact structure of the first IC device, wherein the first IC device comprises a stack of dielectric layers with the dielectric bonding layer being present on top of the stack of dielectric layers, wherein the cavity further traverses one or more of the stack of dielectric layers, wherein the first IC device comprises a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion, and wherein the stack of dielectric layers comprises a stack of intermetal dielectric layers in the BEOL portion, or in the BEOL portion as well as in the FEOL portion of the first IC device.

US Pat. No. 10,170,449

DEFORMABLE CLOSED-LOOP MULTI-LAYERED MICROELECTRONIC DEVICE

International Business Ma...

1. A deformable closed-loop multi-layered microelectronic device comprising:a top layer comprising at least a first section and a second section, wherein the first section and the second section of the top layer are pivotable with respect to each other to deform the top layer;
a bottom layer comprising at least a first section and a second section, wherein the first section of the bottom layer is vertically aligned with the first section of the top layer and the second section of the bottom layer is vertically aligned with the second section of the top layer, wherein the first section and the second section of the bottom layer are pivotable with respect to each other to deform the bottom layer; and
a middle layer disposed between the top layer and the bottom layer, the middle layer comprising at least a first section and a second section, wherein the first section and the second section of the middle layer are pivotable with respect to each other to deform the middle layer,
wherein the middle layer comprises a first pivot provided to a first terminal end of the first section of the middle layer for allowing the first section to rotate about the first pivot, wherein the first terminal end of the first section of the middle layer is vertically sandwiched between a first terminal end of the first section of the top layer and a first terminal end of the first section of the bottom layer; and
wherein the first pivot is connected to the first terminal end of the first section of the bottom layer through a first adhesive and connected to the first terminal end of the first section of the top layer through a second adhesive, such that the first section of the bottom layer and the first section of the top layer are pivotable in a substantially synchronized manner to deform the bottom layer and the top layer in a substantially synchronized manner.

US Pat. No. 10,170,448

APPARATUS AND METHOD OF POWER TRANSMISSION SENSING FOR STACKED DEVICES

Micron Technology, Inc., ...

1. An apparatus comprising:a substrate;
a plurality of dies, each die of the plurality of dies comprising:
a circuit;
a first conductive via through each die, configured to provide a power supply voltage;
an on-die bus coupled to the first conductive via and configured to provide the power supply voltage from the first conductive via to the circuit;
a second conductive via through each die; and
a switch disposed between the on-die bus and the second conductive via, configured to selectively couple the on-die bus to the second conductive via,
a first conductive path across the substrate and the plurality of dies, configured to provide the power supply voltage to the first conductive via, the first conductive path comprising:
a first bump between the substrate and the plurality of dies, coupled to a corresponding first conductive via of a die of the plurality of dies adjacent to the substrate and the first bump configured to provide the power supply voltage to the corresponding first conductive via;
a plurality of the first pillars configured to couple the first conductive vias of adjacent dies of the plurality of dies to each other; and
the plurality of first conductive vias; and
a second conductive path across the substrate and the plurality of dies, the second conductive path comprising:
a second bump between the substrate and the plurality of dies, coupled to a corresponding second conductive via of the die of the plurality of dies adjacent to the substrate;
a plurality of second pillars configured to couple the second conductive vias of adjacent dies of the plurality of dies to each other; and
the plurality of the second conductive vias.

US Pat. No. 10,170,444

PACKAGES FOR SEMICONDUCTOR DEVICES, PACKAGED SEMICONDUCTOR DEVICES, AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A package for a semiconductor device, comprising:an integrated circuit die mounting region;
a molding material disposed around the integrated circuit die mounting region;
an interconnect structure disposed over the molding material and the integrated circuit die mounting region, the interconnect structure comprising a plurality of contact pads;
a connector coupled to each of the plurality of contact pads, wherein two or more connectors each comprises a first portion having a ball shape including a rounded top and sides and a second portion having a raised edge vertically further from a respective contact pad than the first portion, the second portion having vertical sidewalls and a planar top surface protruding from the rounded top of the first portion, wherein a material composition of the second portion has a same material composition as the first portion, wherein the first portion is in contact with a respective contact pad of the plurality of contact pads, wherein the second portion comprises an alignment feature, and wherein the first portion and second portion comprises a eutectic material; and
a raised insulating material layer disposed over at least one of the connectors having an alignment feature, the raised insulating material layer having a same shape as the alignment feature, the raised insulating material layer comprising an oxide of the material composition of the second portion.

US Pat. No. 10,170,443

DEBONDING CHIPS FROM WAFER

International Business Ma...

1. A debonding device comprising:a first member provided with a recess for receiving a carrier body, the carrier body including a first plate, a second plate, and a plurality of semiconductor chips, the semiconductor chips being sandwiched between the first plate and the second plate, the first plate being opposed to a bottom of the recess; and
a second member having a location figured to change with respect to the first member, wherein
the second member holds the second plate using a vacuum suction in a position; and
the first member is provided with an inlet to introduce gas into a gap between the first plate and the second plate.

US Pat. No. 10,170,441

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
an alignment mark adjacent to a surface of the substrate;
a plurality of pillars protruding from the substrate; and
a seal wall protruding from the surface of the substrate and surrounding the alignment mark, wherein the seal wall is between the plurality of pillars and the alignment mark, and the plurality of pillars are configured into at least two different groups wherein a group has an average height different from an average height of an another group.

US Pat. No. 10,170,440

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THEREOF

EPISTAR CORPORATION, Hsi...

1. A semiconductor device, comprising,a semiconductor die comprising a stacking structure, a first bonding pad with a flat top side in a cross-sectional view, positioned away from the stacking structure, and a second bonding pad, wherein a shortest distance between the first bonding pad and the second bonding pad is less than 150 microns;
a carrier comprising a connecting surface;
a third bonding pad and a fourth bonding pad on the connecting surface of the carrier; and
a conductive connecting layer comprising
a first conductive part formed between the first bonding pad and the third bonding pad, and comprising a first conductive material having a first shape with a width;
a second conductive part formed between the second bonding pad and the fourth bonding pad, and comprising the first conductive material; and
a blocking part covering the first conductive part and comprising a second conductive material having a second shape with a diameter less than the width in the cross-sectional view,
wherein the first shape has a height greater than the diameter, and
wherein the first conductive part fully covers the top flat side in the cross-sectional view.

US Pat. No. 10,170,435

GUARD RING STRUCTURE AND METHOD FOR FORMING THE SAME

MEDIATEK SINGAPORE PTE. L...

1. A method for forming a seal ring structure, comprising:providing a semiconductor substrate having a first doping region formed over a top portion thereof, wherein the semiconductor substrate has a first dopant type and the first doping region has the first dopant type or a second dopant type opposite to the first dopant type;
forming a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers comprises a plurality of parallel strip portions extending along a first direction and a plurality of bridge portions formed between the parallel strip portions and extending along a second direction perpendicular to the first direction;
performing an etching process to the first doping region using the patterned photoresist layers as an etching mask, removing the first doping region not covered by the patterned photoresist layers and forming a plurality of patterned first doping regions, wherein each of the patterned first doping regions comprises a plurality of parallel strip portions extending along the first direction and a plurality of bridge portions formed between the parallel strip portions and extending along the second direction perpendicular to the first direction;
removing the patterned photoresist layers;
forming an isolation region between and adjacent to the patterned first doping regions; and
forming a plurality of interconnect elements over the semiconductor substrate, respectively covering one of the patterned first doping regions thereunder.

US Pat. No. 10,170,434

WARPAGE CONTROL IN PACKAGE-ON-PACKAGE STRUCTURES

Taiwan Semiconductor Manu...

1. A package comprising:a bottom package comprising:
a package component; and
a device die over and bonded to the package component;
an adhesive layer over a top surface of the device die, wherein the adhesive layer comprises a slanted sidewall, a planar top surface, and a curved corner joining the slanted sidewall to the planar top surface;
a rigid plate over and contacting the planar top surface of the adhesive layer;
a molding compound, wherein at least a lower portion of the device die is in the molding compound; and
a top package bonded to the bottom package through solder regions penetrating through the molding compound.

US Pat. No. 10,170,433

INSULATED CIRCUIT BOARD, POWER MODULE AND POWER UNIT

Mitsubishi Electric Corpo...

1. An insulated circuit board comprising:an insulated substrate;
a first electrode formed on one main surface of the insulated substrate and having a polygonal shape in plan view; and
a second electrode formed on the other main surface opposite to the one main surface of the insulated substrate and having a polygonal shape in plan view,
a thin portion being formed in a corner portion, the corner portion being a region occupying, with regard to directions along outer edges from a vertex of at least one of the first and second electrodes in plan view, a portion of a length of the outer edges, so that the thin portion occupies only a portion of an entire length of the outer edges, the thin portion having a thickness smaller than a thickness of a region of the at least one of the first and second electrodes other than the thin portion,
the thin portion in the at least one of the first and second electrodes having a planar shape surrounded by first and second sides orthogonal to each other as portions of the outer edges from the vertex, and a curved portion away from the vertex of the first and second sides.

US Pat. No. 10,170,431

ELECTRONIC CIRCUIT PACKAGE

TDK CORPORATION, Tokyo (...

1. An electronic circuit package comprising:a substrate having a main surface, the main surface having a first region and a second region located on a same plane as the first region;
a first electronic component mounted on the first region;
a second electronic component mounted on the second region;
a mold resin that covers the main surface of the substrate so as to embed the first and second electronic components therein;
a magnetic film formed on the mold resin; and
a metal film formed on the mold resin, wherein the metal film covers the first electronic component with an intervention of the magnetic film while the metal film covers the second electronic component without an intervention of the magnetic film.

US Pat. No. 10,170,430

INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A method of fabricating an integrated fan-out package, the method comprising:attaching an integrated circuit component onto a carrier through a die attach film,
forming an insulating encapsulation on the carrier to laterally encapsulate the integrated circuit component and the die attach film, wherein an uplifted segment of the die attach film is lifted during forming the insulating encapsulation, and the uplifted segment raises toward sidewalls of the integrated circuit component; and
forming a redistribution circuit structure on the integrated circuit component and the insulating encapsulation, the redistribution circuit structure being electrically connected to the integrated circuit component.

US Pat. No. 10,170,429

METHOD FOR FORMING PACKAGE STRUCTURE INCLUDING INTERMETALLIC COMPOUND

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a package structure, comprising:forming a first bump over a substrate;
placing an integrated circuit die comprising a second bump over the substrate, wherein the second bump is placed on the first bump;
reflowing the first bump and the second bump to form a solder joint and bond the integrated circuit die and the substrate together through the solder joint, wherein a first intermetallic compound is formed between the solder joint and the first bump, and a second intermetallic compound is formed between the solder joint and the second bump;
annealing the solder joint, the first bump and the second bump to react the solder joint with the first bump and the second bump until the first intermetallic compound and the second intermetallic compound become connected to each other; and
migrating a remaining portion of the solder joint to the first bump or the second bump during a high-temperature storage test or a temperature cycling test.

US Pat. No. 10,170,427

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

7. A semiconductor device comprising:a gate stack over a semiconductor fin;
a source/drain region adjacent to the gate stack; and
a first contact to the source/drain region, wherein the first contact has a curved surface, the curved surface extending above a top surface of the gate stack.

US Pat. No. 10,170,426

MANUFACTURING METHOD OF WIRING STRUCTURE AND WIRING STRUCTURE

FUJITSU LIMITED, Kawasak...

1. A wiring structure, comprising:a first insulating film including a connection hole;
a second insulating film which is on the first insulating film and includes a wiring trench;
a first conductive material which fills an inside of the connection hole; and
a second conductive material which fills an inside of the wiring trench, wherein
the first conductive material is made of a first graphene layer which includes stacked plural graphenes formed in a direction along a bottom surface of the connection hole,
the second conductive material is made of a second graphene layer which includes stacked plural graphenes formed in a direction along a bottom surface of the wiring trench, and
the first graphene layer and the second graphene layer are directly connected to each other.

US Pat. No. 10,170,424

COBALT FIRST LAYER ADVANCED METALLIZATION FOR INTERCONNECTS

International Business Ma...

1. A method for fabricating an advanced metal conductor structure comprising:providing a pattern in a dielectric layer, wherein the pattern includes a set of features in the dielectric for a set of metal conductor structures and an adhesion promoting layer in the set of features;
depositing a ruthenium metal layer disposed on the adhesion promoting layer;
using a physical vapor deposition process to deposit a cobalt layer disposed on the ruthenium layer;
performing a thermal anneal which reflows the cobalt layer to fill a first portion of the set of features leaving a second, remaining portion of the set of features unfilled; and
depositing a second metal layer to fill the second, remaining portion of the set of features, wherein the second metal is a metal other than cobalt, wherein a thickness of the reflowed cobalt layer from the ruthenium layer to a bottom of the second metal layer and a thickness of the second metal layer after planarization are substantially equal.

US Pat. No. 10,170,423

METAL CAP INTEGRATION BY LOCAL ALLOYING

International Business Ma...

1. An interconnect structure, comprising:a dielectric layer having a top surface;
a plurality of open-ended trenches extending within the dielectric layer;
interconnects comprising copper within the open-ended trenches, a plurality of interconnects of the interconnect structure having top surfaces that are substantially coplanar with the top surface of the dielectric layer;
a plurality of metal alloy caps for preventing electromigration, each of the metal alloy caps being integral with one of the interconnects and comprising an alloy of copper and at least one of titanium, ruthenium and cobalt, wherein the metal alloy caps exhibit a stoichiometry of at least one part titanium, ruthenium or cobalt per one part of copper.

US Pat. No. 10,170,422

POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY

Taiwan Semiconductor Manu...

18. A method of forming an integrated chip, comprising:forming a plurality of gate structures extending in a second direction over an active area within a substrate;
forming a first middle-end-of-the-line (MEOL) structure and a second MEOL structure extending in the second direction over the active area and interleaved between the plurality of gate structures along a first direction perpendicular to the second direction, wherein the second MEOL structure extends a non-zero distance past the first MEOL structure along the second direction;
forming a first power rail extending in the first direction, wherein the first power rail is coupled to the second MEOL structure by a first conductive path comprising a conductive contact directly below the first power rail;
forming a first metal wire extending in the first direction over the first MEOL structure;
forming a metal strap coupled to the first metal wire; and
forming a second power rail extending in the first direction over the first power rail, wherein the second power rail is coupled to the first MEOL structure along a second conductive path comprising the first metal wire and the metal strap.

US Pat. No. 10,170,419

BICONVEX LOW RESISTANCE METAL WIRE

International Business Ma...

1. A semiconductor structure comprising:a dielectric material layer having at least one opening located in said dielectric material layer, said at least one opening physically exposing a pair of curved sidewalls of said dielectric material layer and having a biconvex shape comprising a lower portion having a first width, a middle portion having a second width, and an upper portion having a third width, wherein the second width is greater than the first and third widths;
a diffusion barrier liner located in said at least one opening and contacting at least said pair of curved sidewalls of said dielectric material layer;
a reflow enhancement liner located on said diffusion barrier liner; and
a metallic region located on said reflow enhancement liner, said metallic region having a pair of curved outermost sidewalls, said biconvex shape and comprising a lower metallic region portion having a first metallic region width, a middle metallic region portion having a second metallic region width, and an upper metallic region portion having a third metallic region width, wherein the second metallic region width is greater than the first and third metallic region widths.

US Pat. No. 10,170,418

BACKSIDE DEVICE CONTACT

International Business Ma...

1. A method for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, the method comprising:forming a trench in the device layer;
forming a sacrificial plug in the trench;
removing the handle wafer to reveal the buried insulator layer;
partially removing the buried insulator layer to expose the sacrificial plug at a bottom of the trench;
removing the sacrificial plug;
performing backside processing of the buried insulator layer;
filling the trench with a conductor to form a contact plug;
coupling a final substrate to the buried insulator layer such that the contact plug contacts metallization of the final substrate.

US Pat. No. 10,170,414

SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

10. A semiconductor device, comprising:a first group of dummy gate structures disposed over a substrate;
a first interlayer dielectric layer in which the first group of dummy gate structures are embedded;
a second interlayer dielectric layer disposed over the first interlayer dielectric layer;
a third interlayer dielectric layer disposed over the second interlayer dielectric layer; and
a resistor wire formed by a conductive material and embedded in the third interlayer dielectric layer, wherein:
the resistor wire is separated from the first group of dummy gate structures by the second and third interlayer dielectric layers,
the first group of dummy gate structure includes two or more first dummy gate structures and
at least one first dummy gate structure of the first group of dummy gate structures fully overlaps the resistor wire.

US Pat. No. 10,170,413

SEMICONDUCTOR DEVICE HAVING BURIED METAL LINE AND FABRICATION METHOD OF THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A device, comprising:a semiconductor substrate;
a fin field effect transistor (FinFet) comprising:
a fin over the semiconductor substrate;
a gate structure over the fin; and
a source/drain structure adjoining the fin and adjacent to the gate structure;
a shallow trench isolation structure surrounding the fin;
a buried metal line under a top surface of the shallow trench isolation structure; and
a metal segment over the source/drain structure, wherein a portion of the metal segment extends into the shallow trench isolation structure to be electrically coupled to the buried metal line.

US Pat. No. 10,170,412

SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT

Invensas Corporation, Sa...

1. An apparatus, comprising:conductive elements of a conductive layer on a bottom side of a package;
wire bond wires coupled to and extending from first upper surface portions of the conductive elements;
a microelectronic element coupled to second upper surface portions of the conductive elements through conductive contact structures;
a wire bond wire of the wire bond wires interconnected for electrical conductivity to a conductive contact structure of the conductive contact structures by a conductive element of the conductive elements for a redistribution on the bottom side of the package; and
a dielectric layer contacting the wire bond wires and side portions of the microelectronic element to define at least one dimension of the package, the conductive layer at least partially defining the bottom side of the package.

US Pat. No. 10,170,411

AIRGAP PROTECTION LAYER FOR VIA ALIGNMENT

International Business Ma...

1. A method for via alignment, comprising:depositing a pinch off layer to close off openings to first airgaps between interconnect structures;
forming a protection layer in divots formed in the pinch off layer; and
etching the pinch off layer using the protection layer as an etch stop to form and align a via and expose the interconnect structures through the via.

US Pat. No. 10,170,410

SEMICONDUCTOR PACKAGE WITH CORE SUBSTRATE HAVING A THROUGH HOLE

Samsung Electro-Mechanics...

1. A semiconductor package, comprising:a frame comprising a through hole;
an electronic component disposed in the through hole;
a metal layer disposed on either one or both of an inner surface of the through hole and an upper surface of the electronic component;
a redistribution portion disposed below the frame and the electronic component; and
a conductive layer electrically connected to the metal layer,
wherein the redistribution portion comprises an insulating layer formed of an insulating material, and a wiring layer provided in the insulating layer, and
wherein the insulating layer extends to a space formed by a portion of the metal layer formed on an inner surface of the frame and an outer surface of the electronic component.

US Pat. No. 10,170,409

PACKAGE ON PACKAGE ARCHITECTURE AND METHOD FOR MAKING

INTEL CORPORATION, Santa...

1. A method of fabricating a package assembly, the method comprising:forming a package-on-package (POP) land by partially embedding a prefabricated via bar in a region on a first side of a mold compound and extended to a location between the first side of the mold compound and a second side of the mold compound disposed opposite to the first side, wherein the prefabricated via bar extends across a plurality of package assemblies including a first package assembly and a second package assembly separated from the first package assembly, and wherein a die is at least partially embedded in the mold compound and has an active side proximal to the first side of the mold compound;
removing material of the mold compound to expose a portion of the POP land in a region on the second side of the mold compound after the forming of the POP land; and
depositing at least one of a conductive material, a passivation layer, or a noble metal on the exposed portion of the POP land.

US Pat. No. 10,170,408

MEMORY CIRCUITS AND ROUTING OF CONDUCTIVE LAYERS THEREOF

Taiwan Semiconductor Manu...

1. A memory circuit, comprising:at least one memory cell for storing a datum, the memory cell being coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line;
a first conductive layer arranged at a first level, the first conductive layer comprising a first landing pad and a second landing pad, the first landing pad forming a landing site formed in the first conductive layer and on which a via lands, the via connecting the first conductive layer to a second conductive layer;
the second conductive layer coupled to the first conductive layer and arranged at a second level different from and over the first level, the second conductive layer being routed to define the first voltage line and the second voltage line, the first voltage line and the second voltage line extending in a first direction, wherein the first voltage line and the second voltage line are located within the second conductive layer; and
a third conductive layer coupled to the second conductive layer and arranged at a third level different from the first level and the second level, the third level over the second level, the third conductive layer being routed to define the word line, the word line extending in a second direction perpendicular to the first direction, wherein the bit line is located within the first conductive layer adjacent to the first landing pad, wherein the bit line in the first conductive layer extends past a periphery of the at least one memory cell in the first direction, wherein the bit line bar is located within the first conductive layer adjacent to the second landing pad, and wherein the bit line bar in the first conductive layer extends past the periphery of the at least one memory cell in the first direction.

US Pat. No. 10,170,406

TRACE/VIA HYBRID STRUCTURE AND METHOD OF MANUFACTURE

INTERNATIONAL BUSINESS MA...

1. A method of forming an interconnect comprising:providing a sacrificial trace structure using an additive forming method;
forming a seed metal layer on the sacrificial trace structure;
removing the sacrificial trace structure, wherein the seed metal layer remains;
forming an interconnect metal layer on the continuous seed layer;
forming a dielectric material on the interconnect metal layer to encapsulate a majority of the interconnect metal layer, wherein ends of said interconnect metal layer are exposed to provide said interconnect extending through said dielectric material;
forming a solder bump on said ends of the interconnect metal layer; and
bonding said solder bump to a substrate including at least one microprocessor.

US Pat. No. 10,170,404

MONOLITHIC 3D INTEGRATION INTER-TIER VIAS INSERTION SCHEME AND ASSOCIATED LAYOUT STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:forming a first interconnect structure over a first substrate, wherein the first interconnect structure includes a plurality of first interconnect elements;
forming a second substrate over the first substrate such that the first interconnect structure is disposed between the first substrate and the second substrate;
forming a via that extends vertically through the second substrate, wherein the via is formed to be electrically coupled to the first interconnect structure; and
forming a dummy gate over the second substrate, wherein the dummy gate is formed to be electrically coupled to the via.

US Pat. No. 10,170,402

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite to the upper surface;
a first semiconductor chip having a first main surface, a plurality of first electrodes formed on the first main surface, and a first rear surface opposite to the first main surface, and mounted over the upper surface of the wiring substrate such that the first rear surface of the first semiconductor chip faces the upper surface of the wiring substrate; and
a plurality of wires electrically connected with the plurality of terminals, respectively,
wherein, in plan view, the first semiconductor chip is mounted over the upper surface of the wiring substrate such that the plurality of terminals of the wiring substrate is exposed from the first semiconductor chip,
wherein, in plan view, the plurality of terminals is arranged along a first side of the first main surface of the first semiconductor chip,
wherein the plurality of terminals has a plurality of first terminals, and a second terminal,
wherein, in plan view, the second terminal has a first part located on a virtual line comprised of an arrangement of the plurality of first terminals, and a second part not located on the virtual line,
wherein each of the plurality of wires has a ball part, and a stitch part,
wherein, in plan view, a width of the ball part is larger than a width of the stitch part,
wherein the plurality of wires has a plurality of first wires, and a second wire,
wherein, the plurality of first wires are connected to the plurality of first terminals, respectively, via the stitch part,
wherein the second wire is connected to the second part of the second terminal via the ball part, and
wherein a distance from the first side of the first main surface of the first semiconductor chip to the second part of the second terminal is greater than a distance from the first side of the first main surface of the first semiconductor chip to each of the first terminals in a direction perpendicular to the first side of the first main surface of the first semiconductor chip.

US Pat. No. 10,170,400

MULTI-FINGER TRANSISTOR AND SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A multi-finger transistor comprising:a plurality of gate fingers arranged in an active region on a semiconductor substrate;
a plurality of source fingers and a plurality of drain fingers which are alternately arranged in said active region in such a way as to sandwich said gate fingers therebetween, respectively;
a gate pad disposed outside said active region, said gate fingers being connected to said gate pad via a gate bus;
a source pad disposed in a region which is located outside said active region and on a side where said gate pad is disposed with respect to said active region, said source fingers being connected to said source pad;
a drain pad disposed in a region which is located outside said active region and which is located at an opposite side of said gate pad across said active region, said drain fingers being connected to said drain pad;
and a source via grounding said source pad, wherein
said multi-finger transistor further comprises a circuit suppressing a variation in voltage current distribution, said circuit connecting said gate fingers to each other, or connecting said source fingers to each other with a resistive member having a resistance higher than said source fingers, in a region which is located outside said active region and on a side where said drain pad is disposed, and
said multi-finger transistor is configured so as to be linearly symmetric with respect to a direction of propagation of a signal from said gate pad at a position of said gate pad.

US Pat. No. 10,170,399

CAPPED THROUGH-SILICON-VIAS FOR 3D INTEGRATED CIRCUITS

Board of Regents, The Uni...

1. A three dimensional (3D) integrated circuit comprising a plurality of electrically connected chips, at least one chip comprisinga wafer;
a back-end-of-line (BEOL) layer deposited on the wafer;
a chip through-silicon-via (TSV) in the wafer, the chip TSV containing a conductive material;
a chip cap layer disposed over the chip TSV and between the chip TSV and the BEOL layer, wherein the chip cap layer is configured to reduce via extrusion of conductive material located in the chip TSV during operation of the chip; and
an interposer on which the plurality of electrically connected chips are located, wherein the interposer comprises a plurality of interposer TSVs and a interposer cap layer configured to reduce via extrusion of conductive material located in the interposer TSV during fabrication or operation of the circuit, or both.

US Pat. No. 10,170,398

THREE-DIMENSIONAL INTEGRATED CIRCUIT

INDUSTRY-ACADEMIC COOPERA...

1. A three-dimensional integrated circuit divided into a plurality of groups, the three-dimensional integrated circuit comprising:a plurality of through-silicon vias (TSVs) vertically penetrating the three-dimensional integrated circuit and comprised in each of the groups; and
two or more redundant through-silicon vias (RTSVs) vertically penetrating the three-dimensional integrated circuit and comprised in each of the groups,
wherein an RTSV of two or more RTSVs in one group of the plurality of groups is configured to receive a signal of a first failed TSV of a plurality of TSVs in the one group and process the signal of the first failed TSV in the RTSV of the two or more RTSVs in the one group when a number of failed TSVs among the plurality of TSVs in the one group does not exceed a repairable number, and wherein each of the failed TSVs does not normally perform a function as an electrode, and the repairable number is a number of RTSVs capable of replacing functions of the failed TSVs in the one group, and
wherein the RTSV of the two or more RTSVs in the one group is configured to receive the signal of the first failed TSV of the plurality of TSVs in the one group, process the signal of the first failed TSV in the RTSV of the two or more RTSVs in the one group, receive a signal of a second failed TSV of the plurality of TSVs in the one group and output the signal of the second failed TSV to an RTSV of two or more RTSVs in another group of the plurality of groups such that a function of the second failed TSV is performed by the RTSV in the another group when the number of failed TSVs among the plurality of TSVs in the one group exceeds the repairable number, the another group being adjacent to the one group.

US Pat. No. 10,170,395

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a first semiconductor module housing a first semiconductor element and a third semiconductor element;
a second semiconductor module housing a second semiconductor element and a fourth semiconductor element, the second semiconductor element having a switching voltage threshold that is lower than a switching voltage threshold of the first semiconductor element of the first semiconductor module, and the fourth semiconductor element having a switching voltage threshold that is higher than a switching voltage threshold of the third semiconductor element of the first semiconductor module; and
a first busbar that connects an external terminal of the first semiconductor element of the first semiconductor module to an external terminal of the second semiconductor element of the second semiconductor module in parallel to a first common terminal; and
a second busbar that connects an external terminal of the third semiconductor element of the first semiconductor module to an external terminal of the fourth semiconductor element of the second semiconductor module in parallel to a second common terminal, wherein
an inductance of a current path from the first common terminal to the first semiconductor element in the first semiconductor module is lower than an inductance of a current path from the first common terminal to the second semiconductor element in the second semiconductor module, and
an inductance of a current path from the second common terminal to the third semiconductor element of the first semiconductor module is higher than an inductance of a current path from the second common terminal to the fourth semiconductor element of the second semiconductor module.

US Pat. No. 10,170,394

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

10. A semiconductor device comprising:a laminated substrate having a circuit board;
a semiconductor chip having electrodes on a front surface, and a rear surface fixed to the circuit board;
a terminal having a wiring portion with a plate shape, and a leading end portion with a hollow shape extending from the wiring portion, the wiring portion and the leading end portion being integrally formed of one conductive member, the leading end portion having a front open end forming an end of the terminal and a rear open end where a part of the leading end portion continues to the wiring portion; and
a joining material which electrically and mechanically connects the electrode and the front open end of the leading end portion,
wherein the front open end of the leading end portion is located to face the electrode, and is closed by the joining material entered into the front open end, and
a space is arranged between the front open end of the terminal and the electrode so that the joining material enters the front open end of the leading end portion and the space to connect the leading end portion to the electrode.

US Pat. No. 10,170,392

WAFER LEVEL INTEGRATION FOR EMBEDDED COOLING

INTERNATIONAL BUSINESS MA...

1. A device, comprising:a silicon wafer, comprising:
channel structures formed on a first surface of a silicon first wafer, wherein the channel structures respectively comprise radial channels that extend from central fluid distribution areas; and
integrated circuits formed on a second surface of the silicon first wafer that opposes the first surface; and
a manifold wafer bonded to the first surface of the silicon wafer, wherein portions of the manifold wafer enclose the radial channels and wherein inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas.

US Pat. No. 10,170,389

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A method of forming a semiconductor die assembly, the method comprising:electrically coupling a plurality of first semiconductor dies together in a single stack;
electrically coupling the single stack of first semiconductor dies to a second semiconductor die such that the stack of first semiconductor dies is centered with respect to the second semiconductor die along at least one axis, the second semiconductor die having a peripheral portion that extends laterally outward beyond at least one side of the stack of first semiconductor dies, and wherein the stack of first semiconductor dies forms a first thermal path that transfers heat away from the second semiconductor die;
depositing an underfill material between the first semiconductor dies, wherein the underfill material extends from between the first semiconductor dies onto the peripheral portion of the second semiconductor die;
adhering, via the underfill material, a thermal transfer feature to the peripheral portion of the second semiconductor die adjacent to at most a first side and a second side of the single stack of first semiconductor dies and spaced laterally apart from the at most first and second sides of the single stack of first semiconductor dies, wherein the thermal transfer feature is a blank silicon member, and wherein the thermal transfer feature forms a second thermal path away from the second semiconductor die that is separate from the first thermal path; and
thermally contacting a thermally conductive casing with the thermal transfer feature at an elevation generally corresponding to that of a topmost one of the first semiconductor dies in the stack of first semiconductor dies, wherein the blank silicon member extends continuously vertically from the underfill material on the peripheral portion to the elevation generally corresponding to that of the topmost one of the first semiconductor dies.

US Pat. No. 10,170,388

SURFACE PASSIVATION HAVING REDUCED INTERFACE DEFECT DENSITY

INTERNATIONAL BUSINESS MA...

1. A method of passivating a surface of a semiconductor, the method comprising:forming a semiconductor layer on a substrate;
contacting a surface of the semiconductor layer with a sulfur source comprising thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer;
forming a dielectric layer on the sulfur passivation layer; and
annealing the dielectric layer at a temperature of about 390 degrees Celsius for about 30 minutes;
wherein a minimum interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.0×1011 cm?2 eV?1.

US Pat. No. 10,170,387

TEMPORARY BONDING SCHEME

Taiwan Semiconductor Manu...

15. A structure comprising:an integrated circuit device;
a molding compound encapsulating the integrated circuit device, the molding compound having a major surface; and
a thermoplastic material within the molding compound having a concentration of from 1 ppm to 100 ppm at the major surface.

US Pat. No. 10,170,386

ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component package comprising:a frame having a cavity;
an electronic component disposed in the cavity of the frame;
a first metal layer disposed on an inner wall of the cavity of the frame;
a second metal layer disposed on a lower surface of the frame;
a third metal layer disposed on an upper surface of the frame;
an encapsulant encapsulating at least a portion of the electronic component; and
a redistribution layer disposed below the frame and the electronic component,
wherein a lower surface of the encapsulant is substantially coplanar with lower surfaces of the electronic component, the first metal layer and second metal layer.

US Pat. No. 10,170,385

SEMICONDUCTOR DEVICE AND METHOD OF FORMING STACKED VIAS WITHIN INTERCONNECT STRUCTURE FOR FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:a semiconductor die;
an encapsulant deposited over and around the semiconductor die;
a first insulating layer formed over the semiconductor die and encapsulant including a first opening formed through the first insulating layer;
a first conductive layer formed over a top surface of the first insulating layer and extending through the first opening to the encapsulant;
a second insulating layer formed over the semiconductor die and encapsulant including a second opening formed through the second insulating layer, wherein a size of the second opening at the first conductive layer is approximately equal to a size of the first opening, and the second opening is aligned with the first opening;
a second conductive layer formed over a top surface of the second insulating layer and extending through the second opening to the first conductive layer;
a third opening formed through the encapsulant, first conductive layer, and second conductive layer, wherein a size of the third opening at the first conductive layer is smaller than the size of the first opening and the size of the second opening; and
a solder material deposited in the third opening to form a conductive via, wherein the solder material in the third opening is exposed from a top surface of the encapsulant opposite the first conductive layer.

US Pat. No. 10,170,384

METHODS AND APPARATUS PROVIDING A GRADED PACKAGE FOR A SEMICONDUCTOR

TEXAS INSTRUMENTS INCORPO...

1. A method comprising:generating a graded package for encapsulating a die by spatially varying package material of the graded package based on a package grading design, wherein the generating of the graded package includes:
moving a printhead to a first location of the graded package;
printing at least one of a first material or a first combination of materials at the first location;
moving the printhead to a second location of the graded package; and
printing at least one of a second material or a second combination of materials at the second location, the second material being different from the first material and the second combination being different than the first combination.

US Pat. No. 10,170,383

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:an insulating board;
a circuit pattern disposed on the insulating board;
a semiconductor chip connected to the circuit pattern;
a case disposed on and entirely to one side of the insulating board to surround the circuit pattern and the semiconductor chip; and
a cured resin disposed in the case to seal the circuit pattern and the semiconductor chip, wherein
the case includes a surface portion directly opposing and adjacent to a surface portion of the insulating board, and
no bonding material other than the resin is disposed between the opposing and adjacent surface portions.

US Pat. No. 10,170,382

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package comprising:a first interconnection member having a through-hole;
a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad;
an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip;
a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and
a resin layer disposed between the encapsulant and the second interconnection member and contacting at least portions of side surfaces of the protrusion bump,
wherein the first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pad,
the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on both surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer and contacting the second interconnection member, and
the resin layer contacts at least portions of side surfaces of the third redistribution layer.

US Pat. No. 10,170,381

SEMICONDUCTOR WAFER AND METHOD OF BACKSIDE PROBE TESTING THROUGH OPENING IN FILM FRAME

SEMICONDUCTOR COMPONENTS ...

1. A method of making a semiconductor device, comprising:providing a semiconductor wafer including a non-active surface;
forming a conductive layer over the non-active surface;
providing a wafer holder;
forming a first opening through the wafer holder;
mounting the semiconductor wafer to the wafer holder with the conductive layer on the non-active surface oriented toward the wafer holder; and
probe testing the semiconductor wafer by contacting the conductive layer through the first opening in the wafer holder.

US Pat. No. 10,170,380

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a display region and a peripheral circuit region located outside the display region,
wherein a first gate line, a first data line and a pixel region adjacent to the first gate line and the first data line are arranged in the display region; the pixel region includes a first pixel electrode and a first thin film transistor, and the first thin film transistor includes a first gate electrode connected to the first gate line, a first source electrode connected to the first data line and a first drain electrode connected to the first pixel electrode;
wherein the array substrate further comprises a test unit arranged in the peripheral circuit region, the test unit comprising:
a second gate line and a second data line intersecting with each other, wherein when the array substrate is in a working state, a first signal inputted to the second gate line is identical with a second signal inputted to the first gate line, and a third signal inputted to the second data line is identical with a fourth signal inputted to the first data line;
a second testing pixel electrode arranged close to the intersection of the second gate line and the second data line;
a second testing thin film transistor arranged at the intersection of the second gate line and the second data line, wherein the second testing thin film transistor includes a second gate electrode connected to the second gate line, a second source electrode connected to the second data line and a second drain electrode connected to the second testing pixel electrode, wherein a first test port exposed outside of the display region is provided for the second gate electrode, a second test port exposed outside of the display region is provided for the second source electrode, and a third test port exposed outside of the display region is provided for the second drain electrode,
wherein, the display region is further provided with a first common electrode line and a first common electrode connected to the first common electrode line;
the test unit further includes: a second common electrode line and a second testing common electrode connected to the second common electrode line, wherein the second testing common electrode and the first common electrode are arranged on a same layer and are identical in material and shape; and the second testing common electrode is connected to a third test lead through a first transparent conductive connecting line which is located on the same layer with the second testing common electrode, wherein one end of the first transparent conductive connecting line is connected to the second testing common electrode and the other end of the first transparent conductive connecting line is connected to the third test lead, and the first transparent conductive connecting line and the second testing common electrode are identical in material,
wherein, the first transparent conductive connecting line is intersected with the second common electrode line in a plan view of the array substrate.

US Pat. No. 10,170,379

WAFER PROCESSING SYSTEM

DISCO CORPORATION, Tokyo...

1. A wafer processing system for processing wafers one at a time, the wafer processing system comprising:a plurality of trays each configured to accommodate a wafer;
a conveyor configured to transfer the wafers accommodated in the trays;
first and second tray holding apparatuses arranged to be spaced from each other along the conveyor, the first and second tray holding apparatuses unloading the trays from the conveyor and loading the unloaded trays onto the conveyor;
first and second apparatuses provided for the first and second tray holding apparatuses, respectively, the first and second apparatuses including processing means configured to process the wafers transferred by the conveyor, and loading/unloading means configured to unload a wafer from or load a wafer onto one of the trays that is held by the first or second tray holding apparatus; and
a pair of rail members, with one of said rail members formed on each side of the conveyor, wherein each of said rail members includes first and second accommodation grooves therein, and further wherein said pair of first accommodation grooves are configured and arranged to accommodate downward movement of said first tray holding apparatus and said pair of second accommodation grooves are configured and arranged to accommodate downward movement of said second tray holding apparatus.

US Pat. No. 10,170,378

GATE ALL-AROUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:forming a stacked structure of a plurality of first semiconductor layers, a plurality of second semiconductor layers, and a plurality of third semiconductor layers alternately stacked in a first direction over a substrate, wherein the first, second and third semiconductor layers are made froth different materials;
patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction;
removing a portion of the second and third semiconductor layers between adjacent first semiconductor layers of the first fin structure to form a first nanowire structure;
removing a portion of the first and third semiconductor layers between adjacent second semiconductor layers of the second fin structure to form a second nanowire structure;
forming first gate structures wrapping around first nanowires of the first nanowire structure at a first region of the first nanowires; and
forming second gate structures wrapping around second nanowires of the second nanowire structure at a first region of the second nanowires,
wherein the first and second gate structures include gate electrodes, and
wherein when viewed in a cross section taken along a third direction substantially perpendicular to the first direction and the second direction a height of the first nanowires along the first direction is not equal to a distance of a spacing along the first direction between immediately adjacent second nanowires.

US Pat. No. 10,170,376

DEVICE AND FORMING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A device, comprising:a first vertical nanowire disposed on a substrate, wherein the first vertical nanowire comprises a silicon germanium channel part, wherein the first vertical nanowire comprises a bottom silicon source/drain part directly contacting the substrate, a top silicon source/drain part on the bottom silicon source/drain part, and the silicon germanium channel part between the top silicon source/drain part and the bottom silicon source/drain part, wherein the material of the silicon germanium channel part is different from the materials of the bottom silicon source/drain part and the top silicon source/drain part;
a second vertical nanowire disposed on the substrate next to the first vertical nanowire, wherein the second vertical nanowire comprises a silicon channel part; and
a gate encircling the silicon germanium channel part and the silicon channel part.

US Pat. No. 10,170,375

FINFET DEVICES WITH UNIQUE FIN SHAPE AND THE FABRICATION THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a semiconductor device, comprising:forming a first layer over a substrate, the first layer spanning across both a first region and a second region;
forming a second layer over the first layer;
etching the first and second layers to form a plurality of openings in the first region and the second region, wherein the plurality of openings extend vertically through the first layer and the second layer;
forming a dielectric layer in the openings in the first region but not in openings of the second region; and
forming an insulating layer between the first and second layers in the second region.

US Pat. No. 10,170,374

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:at least one n-channel;
at least one p-channel;
at least one first high-k dielectric sheath surrounding the n-channel;
at least one second high-k dielectric sheath surrounding the p-channel, the first high-k dielectric sheath and the second high-k dielectric sheath comprising different high-k dielectric materials;
a first metal gate electrode surrounding and in contact with the first high-k dielectric sheath; and
a second metal gate electrode surrounding and in contact with the second high-k dielectric sheath, wherein the first and second metal gate electrodes are made of the same material.

US Pat. No. 10,170,372

FINFET CMOS WITH SI NFET AND SIGE PFET

International Business Ma...

1. A complementary metal oxide semiconductor (CMOS) device, comprising:pedestals with vertical sidewalls formed from a buried dielectric layer;
a SiGe fin and a Si fin, each formed on the pedestals, the SiGe fin and the Si fin including a same or substantially the same width dimension, wherein the pedestals extend wider than the SiGe fin and the Si fin for the entire length of the fins; and
epitaxial source and drain regions including a first epitaxial region grown from the SiGe fin and a second epitaxially region grown from the Si fin.

US Pat. No. 10,170,369

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A method for fabricating a semiconductor device, comprising:providing a substrate having thereon a trench isolation region and a plurality of fin structures extending along a first direction, wherein the plurality of fin structures protrude from a top surface of the trench isolation region;
blanket depositing a polysilicon layer over the substrate;
forming a poly cut opening and a dummy opening in the polysilicon layer;
blanket coating an organic dielectric layer (ODL) over the substrate, wherein the ODL fills into the poly cut opening and the dummy opening;
blanket depositing a hard mask layer on the ODL;
forming a plurality of photoresist line patterns comprising a first photoresist line pattern and a second photoresist line pattern extending along a second direction on the hard mask layer, wherein the first photoresist line pattern overlaps with the poly cut opening, and the second photoresist line pattern is disposed in proximity to the dummy opening, and does not overlap with the dummy opening; and
transferring the plurality of photoresist line patterns to the polysilicon layer, thereby forming a plurality of poly lines extending along the second direction.

US Pat. No. 10,170,368

FABRICATING FIN-BASED SPLIT-GATE HIGH-DRAIN-VOLTAGE TRANSISTOR BY WORK FUNCTION TUNING

International Business Ma...

1. A method for creating an asymmetrical split-gate structure, the method comprising:forming a first device over a semiconductor substrate, the first device having first source drain regions formed adjacent a first set of spacers;
forming a second device over the semiconductor substrate, the second device having second source/drain regions formed adjacent a second set of spacers;
forming a first gate stack between the first set of spacers of the first device and a second gate stack between the second set of spacers of the second device;
depositing a hard mask over the first and second gate stacks;
etching a first section of the first gate stack to create a first gap region and a second section of the second gate stack to create a second gap region;
forming a third gate stack within the first gap region of the first gate stack, the third gate stack having a different number of layers than the first gate stack, and a fourth gate stack within the second gap region of the second gate stack such that dual gate stacks are defined for each of the first and second devices; and
annealing the dual gate stacks of the first and second devices to form first and second replacement metal gate stacks, respectively.

US Pat. No. 10,170,367

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:patterning a plurality of mandrels over a mask layer;
forming an etch coating layer on top surfaces of the mask layer and the mandrels;
depositing a dielectric layer over the mask layer and the mandrels with a deposition process, a first deposition rate of the deposition process along sidewalls of the mandrels being greater than a second deposition rate of the deposition process along the etch coating layer, a first thickness of the dielectric layer along the sidewalls of the mandrels being greater than a second thickness of the dielectric layer along the etch coating layer;
removing horizontal portions of the dielectric layer; and
patterning the mask layer using remaining vertical portions of the dielectric layer as a first etching mask.

US Pat. No. 10,170,365

WRAP AROUND SILICIDE FOR FINFETS

Taiwan Semiconductor Manu...

1. A method comprising:forming a gate stack on a first portion of a semiconductor fin, wherein the semiconductor fin overlaps a semiconductor strip;
forming template dielectric regions on opposite sides of a second portion of the semiconductor fin;
forming a recess between the template dielectric regions, wherein the forming the recess comprises etching a top portion of the second portion of the semiconductor fin;
laterally expanding the recess to make the recess wider; and
epitaxially growing a source/drain region in the recess, wherein the source/drain region has substantially vertical sidewalls, and is wider than respective underlying portion of the semiconductor strip.

US Pat. No. 10,170,364

STRESS MEMORIZATION TECHNIQUE FOR STRAIN COUPLING ENHANCEMENT IN BULK FINFET DEVICE

International Business Ma...

1. A method for forming strained fins, comprising:forming a staircase fin structure in a substrate with narrow top portions for fins;
epitaxially growing raised source and drain regions over the fins; and
performing a pre-amorphization implant to generate defects in the substrate to induce strain and to couple the strain into the top portions of the fins.

US Pat. No. 10,170,363

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...

1. An interconnection structure of a semiconductor integrated circuit device comprising:a first conductive pattern having a first width and a first length;
a second conductive pattern arranged over the first conductive pattern, the second conductive pattern having a second width and a second length being different from the first length;
a dielectric layer interposed between the first conductive pattern and the second conductive pattern; and
a contact part configured to simultaneously make contact with the first conductive pattern and the second conductive pattern,
wherein the second conductive pattern is configured to expose an edge portion of the first conductive pattern, and the contact part is configured to make contact with the an edge portion of the second conductive pattern and the exposed edge portion of the first conductive pattern.

US Pat. No. 10,170,362

SEMICONDUCTOR MEMORY DEVICE WITH BIT LINE CONTACT STRUCTURE AND METHOD OF FORMING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a substrate, comprising a first active region and a plurality of second active regions;
a shallow trench isolation, disposed in the substrate and between the first active region and the second active regions;
a bit line contact opening, disposed in the first active region and the shallow trench isolation;
a bit line contact structure, disposed in the bit line contact opening and contacts the first active region; and
a spacer disposed in the bit line contact opening, wherein the spacer has a sidewall directly contacting one of the second active regions;
a mask layer disposed on the second active regions and exposing the bit line contact opening;
wherein the spacer extends beneath the mask layer to contact the first active region.

US Pat. No. 10,170,361

THIN FILM INTERCONNECTS WITH LARGE GRAINS

International Business Ma...

1. An integrated circuit, comprising:a surface of the integrated circuit, the surface comprising a semiconductor;
a via-line-via interconnect formed from a metal and comprising:
a first via formed in the surface;
a line formed integrally with the first via and orientated perpendicularly relative to the first via, wherein the line and the first via share at least one common grain, and wherein the line is further formed on the surface and orientated parallel to the surface, wherein a thickness of the line is defined in a dimension perpendicular to the surface, and a line width of the line is defined in a dimension parallel to the surface and is within the range of two nanometers to eighty nanometers, wherein an average grain size of the metal of the line is greater than or equal to at least half of a line width of the line, wherein the line has a tapered cross section, and wherein the thickness of the line remains constant; and
a second via formed integrally with the line and orientated perpendicular relative to the line, wherein the line and the second via share at least one common grain, and wherein the line is positioned between the first via and the second via and between the surface and the second via,
such that the via-line-via interconnect exhibits grain continuity and material continuity between the first via and the line and between the line and the second via, where the grain continuity is evident in the line sharing a respective common grain with each of the first via and the second via; and
an insulator deposited on the surface and surrounding the interconnect, wherein the insulator is formed from a material that is different from a material from which the surface is formed.

US Pat. No. 10,170,360

REFLOW ENHANCEMENT LAYER FOR METALLIZATION STRUCTURES

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:providing an opening in a dielectric-containing substrate;
forming a reflow enhancement layer in the opening and atop the dielectric-containing substrate;
forming a layer of a contact metal or metal alloy on the reflow enhancement layer;
performing a reflow anneal to completely fill a remaining volume of the opening with the contact metal or metal alloy of the layer of contact metal or metal alloy; and
removing the layer of contact metal or metal alloy, and the reflow enhancement layer located outside of the opening, wherein a portion of the layer of contact metal or metal alloy, and a portion of the reflow enhancement layer remain within the opening, and wherein the portion of the layer of contact metal or metal alloy that remains in the opening has a sidewall that is in direct physical contact with an inner sidewall of the portion of the reflow enhancement layer that remains in the opening.

US Pat. No. 10,170,359

DIFFUSION BARRIER LAYER FORMATION

International Business Ma...

1. A method of forming a titanium nitride diffusion barrier, the method comprising:exposing a deposition surface to a first pulse of a titanium-containing precursor gas to initiate a nucleation of the titanium nitride diffusion barrier in the deposition surface, wherein the deposition surface comprises sidewalls and a bottom of a contact opening;
exposing the deposition surface to a first pulse of a nitrogen-rich plasma to form a first titanium nitride layer with a first nitrogen concentration in the deposition surface, the first titanium nitride layer comprises a lower portion of the titanium nitride diffusion barrier;
exposing the first titanium nitride layer to a second pulse of the titanium-containing precursor gas to continue the nucleation of the titanium nitride diffusion barrier; and
exposing the first titanium nitride layer to a second pulse of the nitrogen-rich plasma to form a second titanium nitride layer with a second nitrogen concentration directly above and in contact with the first titanium nitride layer, the second titanium nitride layer comprises an upper portion of the titanium nitride diffusion barrier, wherein the second nitrogen concentration of the second titanium nitride layer is substantially increased by the second pulse of the nitrogen-rich plasma, the increased nitrogen concentration of the second titanium nitride layer lowers a reactivity of the upper portion of the titanium nitride diffusion barrier to prevent fluorine diffusion, and wherein the second pulse of the nitrogen-rich plasma has a substantially longer duration than the first pulse of the nitrogen rich plasma,
wherein the titanium nitride diffusion barrier comprises the first and the second titanium nitride layers; and
wherein the first pulse of the nitrogen-rich plasma has a duration of approximately 5 seconds and the second pulse of the nitrogen-rich plasma has a duration of approximately 60 seconds.

US Pat. No. 10,170,358

REDUCING CONTACT RESISTANCE IN VIAS FOR COPPER INTERCONNECTS

INTERNATIONAL BUSINESS MA...

1. An interconnect structure comprising:an interlevel dielectric layer on an electrically conductive feature;
an opening in the interlevel dielectric layer, the opening including a first width at a first depth into the interlevel dielectric layer, and a second width at a second depth that is greater than the first depth, wherein the second width is less than the first width of the opening and includes a portion of the opening that extends through the entirety of the interlevel dielectric layer into contact with the electrically conductive feature;
a conformal metal nitride layer present on vertical and horizontal surfaces of the opening, wherein the metal nitride layer is present directly on the interlevel dielectric layer;
a shield liner present over vertical sidewalls of the opening directly on the conformal metal nitride layer, wherein the conformal metal nitride layer is present between the interlevel dielectric layer and the shield liner; and
a contact extending through the opening into direct contact with the shield liner, the conformal metal nitride layer, and the electrically conductive feature, wherein a gouge is present at the interface of the contact and the electrically conductive feature.

US Pat. No. 10,170,355

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first dielectric layer disposed over a substrate;
a plurality of metal wirings surrounded by the first dielectric layer;
a second dielectric layer disposed over a portion of the first dielectric layer, wherein a portion of the second dielectric layer is disposed in a first recess between two adjacent metal wirings of the plurality of metal wirings; and
a third dielectric layer disposed over the first dielectric layer, the second dielectric layer, and the plurality of metal wirings, wherein a portion of the third dielectric layer is disposed in the first recess between the two metal wirings,
wherein the portion of the third dielectric layer comprises an upper portion and a lower portion, the upper portion being above the second dielectric layer and the lower portion being below the second dielectric layer.

US Pat. No. 10,170,354

SUBTRACTIVE METHODS FOR CREATING DIELECTRIC ISOLATION STRUCTURES WITHIN OPEN FEATURES

Tokyo Electron Limited, ...

1. A method for partially filling an open feature on a substrate, comprising:receiving a substrate having a layer with at least one open feature formed therein, the open feature penetrating into the layer from an upper surface and including sidewalls extending to a bottom of the open feature;
over-filling the open feature with an organic coating that covers the upper surface of the layer and extends to the bottom of the open feature;
removing a portion of the organic coating to expose the upper surface of the layer and recessing the organic coating to a pre-determined depth from the upper surface to create an organic coating plug of pre-determined thickness at the bottom of the open feature; and
converting the chemical composition of the organic coating plug to create an inorganic plug,
wherein the organic coating includes a polymeric material or co-polymeric material containing a carbonyl functionality, and
wherein removing the portion of the organic coating includes performing a wet etch process comprising:
exposing the organic coating to ultraviolet (UV) radiation to increase the solubility of the as-formed organic coating in a developing solution; and
controllably etching the organic coating to the pre-determined depth by exposing the organic coating to the developing solution.

US Pat. No. 10,170,348

PRODUCTION SYSTEM FOR PRINTING ELECTRONIC DEVICES

KONICA MINOLTA, INC., To...

1. A printing production system for an electronic device, whereina transport chamber provided with a robot transport line in which a self-traveling robot that transports a base material in a sheet-fed manner in a free state travels is provided,
a plurality of processing chambers for forming the electronic device on the base material by printing are provided on at least one side of the transport chamber,
a plurality of base material transfer areas, each of the base material transfer areas performs loading of the base material to a respective processing chamber of the processing chambers from the self-traveling robot and unloading of the base material to the self-traveling robot from the respective processing chamber,
the transport chamber and each of the base material transfer areas communicate with each other through respective openings that allow loading and unloading of the base material to be performed, a one-way air flow is formed in each of the respective openings moving to a side where the respective processing chamber is located from a side where the transport chamber is located, and
the one-way air flow in the each of the respective openings is formed by making an adjustment such that an air pressure in the transport chamber becomes higher than an air pressure in each of the base material transfer areas, wherein an air pressure P1 in the clean room, an air pressure P2 in the base material transfer areas, and an air pressure P3 in the transport chamber satisfy a relationship: P1

US Pat. No. 10,170,347

SUBSTRATE PROCESSING SYSTEM

TOKYO ELECTRON LIMITED, ...

1. A substrate processing system for performing a process with respect to a plurality of substrates, comprising:an annular process chamber configured to accommodate the plurality of substrates and to perform a predetermined process on the plurality of substrates, the annular process chamber having an inner lateral surface and an outer lateral surface;
a cassette mounting part configured to mount a cassette which accommodates the plurality of substrates;
a substrate transfer mechanism configured to transfer the plurality of substrates between the annular process chamber and the cassette mounting part; and
a gate valve is installed in the inner lateral surface of the annular process chamber facing the substrate transfer mechanism,
wherein the plurality of substrates is concentrically disposed within the annular process chamber in a plane view,
wherein the substrate transfer mechanism is disposed in a space surrounded by the inner lateral surface of the annular process chamber, and
wherein a vacuum transfer chamber is installed adjacent to the annular process chamber in the space surrounded by the inner lateral surface of the annular process chamber, and the substrate transfer mechanism is disposed within the vacuum transfer chamber.

US Pat. No. 10,170,346

RESIN SEALING APPARATUS AND RESIN SEALING METHOD

TOWA CORPORATION, Kyoto-...

1. A resin sealing apparatus for providing resin sealing for a component to be sealed by a sealing resin which is cured in a cavity, comprising:an upper mold on which a substrate is disposed, a component to be sealed being attached to the substrate;
a lower mold provided to face the upper mold;
a cavity provided at least in the lower mold;
a bottom surface member forming an inner bottom surface of the cavity;
a side surface member forming a side surface of the cavity;
an opening provided in the side surface member and corresponding to an outer circumference of the bottom surface member;
an opening circumferential edge portion provided in the side surface member and having an inner edge shape formed to correspond to an outer edge of an end surface planar shape, an end surface of the sealing resin having the end surface planar shape;
an inclined surface portion provided in the side surface member and inclined to expand upwardly from the opening circumferential edge portion,
a frame-like member provided to surround a mold having at least the upper mold and the lower mold;
a space surrounded by the frame-like member and including the cavity;
a seal member for shutting off the space from ambient air; and
a pressure reducing mechanism for reducing pressure of the space with the space being shut off from the ambient air, wherein
the side surface member is fitted to the outer circumference of the bottom surface member so as to be slidable on the outer circumference, and
during a period from when the space is shut off from the ambient air to when a step of clamping the upper mold and the lower mold is completed, the pressure of the space shut off from the ambient air is reduced by the pressure reducing mechanism.

US Pat. No. 10,170,345

SUBSTRATE PROCESSING APPARATUS

Ebara Corporation, Tokyo...

1. A substrate processing apparatus comprising:a substrate processing table;
a processing device configured to perform a predetermined processing on the substrate processing table;
a nozzle configured to drop a fluid at a position that corresponds to a fluid dropping position set on the substrate processing table and is lower than a top surface of the processing device;
a nozzle moving mechanism configured to move the nozzle above the processing device between a retreat position set outside the substrate processing table and the fluid dropping position; and
a nozzle tip retreating mechanism configured to bring a tip end of the nozzle into a retreated state above the top surface of the processing device when the nozzle moves between the fluid dropping position and the retreat position,
wherein the nozzle tip retreating mechanism is an extension/contraction mechanism that extends and contracts the tip end of the nozzle.

US Pat. No. 10,170,344

WASHING DEVICE AND WASHING METHOD

EBARA CORPORATION, Tokyo...

1. A washing device comprising:a substrate rotation mechanism configured to hold a substrate and rotate the substrate about a central axis of the substrate as a rotary axis; a rinse supply; a chemical supply, wherein the chemical liquid is different than the rinse liquid;
a first single tube nozzle configured to discharge the rinse liquid from the rinse liquid supply as a first washing liquid toward an upper surface of the substrate held by the substrate rotation mechanism; and
a second single tube nozzle configured to discharge the chemical liquid from the chemical liquid supply as a second washing liquid toward the upper surface of the substrate held by the substrate rotation mechanism,
wherein the first single tube nozzle is placed to discharge the first washing liquid so that the first washing liquid lands in front of the center of the substrate and the landed first washing liquid flows on the upper surface of the substrate toward the center of the substrate,
a liquid flow on the upper surface of the substrate after landing of the first washing liquid discharged from the first single tube nozzle passes through the center of the substrate,
the second single tube nozzle is placed to discharge the second washing liquid so that the second washing liquid lands in front of the center of the substrate and the landed second washing liquid flows on the upper surface of the substrate toward the center of the substrate,
a second liquid flow on the upper surface of the substrate after landing of the second washing liquid discharged from the second single tube nozzle passes through the center of the substrate,
discharging of the first washing liquid by the first single tube nozzle and discharging of the second washing liquid by the second single nozzle are simultaneously performed, and
the first single tube nozzle supplies the first washing liquid so that a liquid-landing position of the first washing liquid is located in an area up to a 180° rotation in a reverse direction of a rotational direction of the substrate from the liquid-landing position of the second washing liquid.

US Pat. No. 10,170,343

POST-CMP CLEANING APPARATUS AND METHOD WITH BRUSH SELF-CLEANING FUNCTION

TAIWAN SEMICONDUCTOR MANU...

1. An apparatus for performing a post Chemical Mechanical Polish (CMP) cleaning, the apparatus comprising:a chamber configured to receive a wafer in need of having CMP residue removed;
a spray unit configured to apply a first cleaning solution to at least one surface of the wafer;
a brush cleaner configured to scrub the at least one surface of the wafer; and
at least one inner tank disposed in the chamber for storing a second cleaning solution that is used to clean the brush cleaner;
wherein the at least one inner tank comprises an inner compartment and an outer compartment, wherein the inner compartment is configured to store the second cleaning solution and receive the brush cleaner, and the outer compartment is configured to receive the second cleaning solution overflowing from the inner compartment.

US Pat. No. 10,170,337

IMPLANT AFTER THROUGH-SILICON VIA (TSV) ETCH TO GETTER MOBILE IONS

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:disposing a mask on a substrate;
etching the mask to form an opening in the mask;
etching a trench in the substrate beneath the opening in the mask;
implanting a dopant, by an implantation technique, in an area of the substrate beneath the opening of the mask such that the dopant extends within the substrate from a substantially vertical sidewall of the trench and substantially horizontal bottom endwall of the trench, the dopant capable of gettering mobile ions that can contaminate the substrate; and
simultaneous with implanting the dopant, implanting a source/drain region of an nFET device adjacent the trench with an element selected from the group consisting of arsenic and phosphorous.

US Pat. No. 10,170,334

REDUCTION OF DISHING DURING CHEMICAL MECHANICAL POLISH OF GATE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a gate structure over the semiconductor substrate; and
a plurality of chemical mechanical polish (CMP) resistant structures embedded in a top surface of the gate structure, the CMP resistant structures having a CMP resistance property different from a CMP resistance property of the gate structure,
wherein the gate structure comprises a base portion and a plurality fins protruding from the base portion, and each of the fins is connected to the base portion,
wherein the CMP resistant structures and the fins are arranged in an alternating manner along a first lengthwise direction,
wherein the CMP resistant structures extend along a second lengthwise direction which is different from the first lengthwise direction.

US Pat. No. 10,170,332

FINFET THERMAL PROTECTION METHODS AND RELATED STRUCTURES

Taiwan Semiconductor Manu...

14. A method, comprising:providing a substrate including a plurality of fins and interposing dielectric features;
after providing the plurality of fins and interposing dielectric features, forming a dummy channel on an end of each of the plurality of fins, wherein the dummy channel has a different composition than each of the plurality of fins;
recessing the interposing dielectric features to expose the dummy channel;
after recessing the interposing dielectric features, forming a dummy gate stack over the exposed dummy channel and forming source/drain regions in each of the plurality of fins;
depositing a first inter-layer dielectric (ILD) layer on the substrate including the plurality of fins;
planarizing the first ILD layer to expose the dummy gate stack;
after planarizing the first ILD layer, removing the dummy gate stack and etching the dummy channel to form a recess in each of the plurality of fins; and
forming a material in the recess in each of the plurality of fins.

US Pat. No. 10,170,329

SPACER FORMATION FOR SELF-ALIGNED MULTI-PATTERNING TECHNIQUE

Tokyo Electron Limited, ...

1. A method of forming a spacer pattern on a substrate, the method comprising:providing a substrate with a plurality of spacer cores having a conformal coating of spacer material thereon wherein the conformal coating includes bottom portions on the substrate between the plurality of spacer cores, sidewall portions on sidewalls of the plurality of spacer cores, top portions on top surfaces of the plurality of spacer cores, and shoulder portions joining the sidewall portions and the top portions;
performing a spacer freeze treatment process that forms a buildup of byproducts on the shoulder portions of the conformal coating while leaving the top and bottom portions exposed;
performing an etch and clean process on the substrate to remove the exposed top and bottom portions of the conformal coating and to remove the plurality of spacer cores to substantially leave the sidewall portions as the spacer pattern, wherein the buildup of byproducts serves as a protective layer to reduce etching of the sidewall portions; and
controlling one or more process parameters of the spacer freeze treatment process and the etch and clean process in order to achieve one or more spacer formation objectives selected from a target height of the spacer pattern, a target maximum facet depth on the spacer pattern, a target critical dimension of the spacer pattern, a target maximum height difference between the plurality of spacer cores and the spacer pattern, a target uniformity of the spacer pattern, and a target maximum amount of spacer footings in the spacer pattern.

US Pat. No. 10,170,327

FIN DENSITY CONTROL OF MULTIGATE DEVICES THROUGH SIDEWALL IMAGE TRANSFER PROCESSES

International Business Ma...

1. A method for fabricating multigate devices comprising:forming a mandrel on a semiconductor substrate;
forming a first sidewall composed of a first material directly in contact with the mandrel previously formed on the semiconductor substrate; and
forming a second sidewall composed of a second material that is different from the first material directly in contact with the mandrel, wherein the second sidewall is opposite the first sidewall on the same mandrel.

US Pat. No. 10,170,326

WAFER ELEMENT WITH AN ADJUSTED PRINT RESOLUTION ASSIST FEATURE

INTERNATIONAL BUSINESS MA...

1. A wafer element fabrication method, comprising:patterning photoresist (PR) over an anti-reflective coating (ARC) disposed over a planarization layer (PL) and a substrate,
the patterning comprising forming the PR into PR device element and adjusted print resolution assist feature (APRAF) sections having first and second dimensions, respectively;
removing portions of the ARC and the PR device element and APRAF sections such that ARC device element and APRAF posts remain underneath remainders of the PR device element and APRAF sections having third and fourth dimensions based on the first and second dimensions, respectively;
removing the remainders of the PR device element and APRAF sections and portions of the PL such that PL device element and APRAF posts remain underneath the ARC device element and APRAF posts; and
removing the ARC device element and APRAF posts such that the PL device element and APRAF posts remain with fifth and sixth dimensions based on the third and fourth dimensions, respectively.

US Pat. No. 10,170,324

TECHNIQUE TO TUNE SIDEWALL PASSIVATION DEPOSITION CONFORMALITY FOR HIGH ASPECT RATIO CYLINDER ETCH

Lam Research Corporation,...

1. A method of forming an etched feature in a substrate comprising dielectric material, the method comprising:(a) generating a first plasma comprising an etching reactant, exposing the substrate to the first plasma, and partially etching the feature in the substrate;
(b) after (a), depositing a protective film on sidewalls of the feature, wherein the protective film is deposited through a plasma assisted atomic layer deposition reaction comprising:
(i) exposing the substrate to a first deposition reactant and allowing the first deposition reactant to adsorb onto the sidewalls of the feature;
(ii) after (i), exposing the substrate to a second plasma comprising a second deposition reactant, wherein exposing the substrate to the second plasma drives a surface reaction between the first deposition reactant and the second deposition reactant, thereby forming the protective film on the sidewalls of the feature; and
(c) repeating (a)-(b) until the feature is etched to a final depth, wherein the protective film deposited in (b) substantially prevents lateral etch of the feature during (a), and wherein the feature has an aspect ratio of about 5 or greater at its final depth.

US Pat. No. 10,170,323

TECHNIQUE TO DEPOSIT METAL-CONTAINING SIDEWALL PASSIVATION FOR HIGH ASPECT RATIO CYLINDER ETCH

Lam Research Corporation,...

1. A method of etching a feature in a dielectric-containing stack on a substrate, the method comprising:(a) generating a first plasma comprising an etching reactant, exposing the substrate to the first plasma, and partially etching the feature in the dielectric-containing stack;
(b) after (a), depositing a protective film on sidewalls of the feature, the protective film comprising a metal, wherein the protective film comprises an electrically conductive film; and
(c) repeating (a)-(b) until the feature is etched to a final depth, wherein the protective film deposited in (b) substantially prevents lateral etch of the feature during (a), and wherein the feature has an aspect ratio of about 5 or greater at its final depth.

US Pat. No. 10,170,322

ATOMIC LAYER DEPOSITION BASED PROCESS FOR CONTACT BARRIER LAYER

TAIWAN SEMICONDUCTOR MANU...

9. A method comprising:forming a contact opening in a dielectric layer;
performing at least one first cycle of a first nitrogen-containing plasma pulse and a first purge, thereby nitridizing surfaces of the dielectric layer that define the contact opening;
performing at least one second cycle of a titanium-containing pulse, a second purge, a second nitrogen-containing plasma pulse, and a third purge, thereby forming a titanium nitride layer on the nitridized surfaces of the dielectric layer that define the contact opening; and
forming a cobalt layer on the titanium nitride layer.

US Pat. No. 10,170,320

FEATURE FILL WITH MULTI-STAGE NUCLEATION INHIBITION

Lam Research Corporation,...

1. A method comprising:providing a substrate including a feature having one or more feature openings and a feature interior; and
performing a multi-stage inhibition treatment comprising exposing the feature to a plasma generated from a treatment gas in multiple stages and multiple intervals, with successive stages separated by one of the multiple intervals, wherein one or more of a plasma source power, a substrate bias power, or a treatment gas flow rate is reduced at the start of each interval and increased at the end of the interval, and wherein the inhibition treatment preferentially inhibits nucleation of a metal at the feature openings.

US Pat. No. 10,170,317

SELF-PROTECTIVE LAYER FORMED ON HIGH-K DIELECTRIC LAYER

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a first gate structure and a second gate structure formed on a substrate; wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further comprises:
a gate dielectric layer;
a self-protective layer having metal phosphate; and
the first work function metal on the self-protective layer.

US Pat. No. 10,170,316

CONTROLLING THRESHOLD VOLTAGE IN NANOSHEET TRANSISTORS

International Business Ma...

1. A semiconductor device comprising:a nanosheet stack over a substrate, the nanosheet stack comprising a first nanosheet vertically stacked over a second nanosheet;
an inner nitride layer on a surface of each nanosheet; and
a doped transition metal layer on each inner nitride layer formed from alternating pulses of a first precursor comprising a transition metal and a second precursor comprising an aluminum carbide.

US Pat. No. 10,170,312

SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME

Taiwan Semiconductor Manu...

1. A method for manufacturing a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer, comprising:providing the semiconductor wafer with a first dopant concentration of a dopant having a first conductivity type;
forming a polysilicon layer over the front surface;
forming an oxide layer over a back surface of the semiconductor wafer;
removing the polysilicon layer from the front surface; and
depositing the epitaxial layer at the front surface with a second dopant concentration of the dopant having the first conductivity type under a predetermined temperature, the second dopant concentration being lower than the first dopant concentration,
wherein a defect density in a center portion of the semiconductor wafer is below 1E9/cm3 from a cross sectional perspective after depositing the epitaxial layer at the front surface.

US Pat. No. 10,170,311

METHOD FOR HANDLING THIN BRITTLE FILMS

International Business Ma...

1. A method comprising:providing a structure comprising:
a spalled layer having a first side and a second side; anda tape layer formed on the first side of the spalled layer, wherein the tape layer is provided at below a first temperature range, wherein the structure comprises providing a stressor layer on the first side of the spalled layer, and a providing the tape layer as a handle layer on the stressor layer;applying a temporary substrate layer to the second side of the spalled layer,
wherein the temporary substrate layer is applied at a second temperature range, and
wherein at least a portion of the second temperature range is lower than the first temperature range;
after applying the temporary substrate layer, separating the tape layer from the spalled layer; and
after separating the tape layer from the spalled layer, separating the stressor layer from the spalled layer.

US Pat. No. 10,170,307

METHOD FOR PATTERNING SEMICONDUCTOR DEVICE USING MASKING LAYER

Taiwan Semiconductor Manu...

1. A method comprising:forming a first mask layer on a substrate;
patterning first spacers over the first mask layer;
forming an anti-reflective layer over the first spacers;
forming an etch stop layer over the anti-reflective layer;
forming a second mask layer over the etch stop layer;
patterning first openings in the second mask layer, each of the first openings overlying respective pairs of the first spacers;
after patterning the first openings, patterning second openings in the second mask layer, each of the second openings overlying respective pairs of the first spacers;
extending the first and second openings through the anti-reflective layer and between the respective pairs of the first spacers;
forming a reverse material over the second mask layer and in the first and second openings;
removing the anti-reflective layer, the etch stop layer, the second mask layer, and portions of the reverse material; and
patterning the first mask layer using the first spacers and remaining portions of the reverse material as a first etching mask.

US Pat. No. 10,170,306

METHOD OF DOUBLE PATTERNING LITHOGRAPHY PROCESS USING PLURALITY OF MANDRELS FOR INTEGRATED CIRCUIT APPLICATIONS

Taiwan Semiconductor Manu...

1. A method comprising:forming mandrels comprising a first mandrel strip, wherein the first mandrel strip comprises a first portion and a second portion separated from each other by a first opening;
depositing a blanket spacer layer over the first mandrel strip;
etching horizontal portions of the blanket spacer layer to form spacers, wherein the first opening is filled by a portion of the spacers;
etching the first portion and the second portion of the first mandrel strip to form a second opening and a third opening encircled by the mandrels and the spacers; and
using the mandrels and the spacers as an etching mask to etch a target layer, with trenches formed in the target layer.

US Pat. No. 10,170,305

SELECTIVE FILM GROWTH FOR BOTTOM-UP GAP FILLING

Taiwan Semiconductor Manu...

1. A method comprising:etching a portion of a semiconductor material between isolation regions to form a trench;
forming a first semiconductor seed layer extending on a bottom surface and sidewalls of the trench;
etching-back the first semiconductor seed layer until a top surface of the first semiconductor seed layer is lower than top surfaces of the isolation regions;
performing a first selective epitaxy to grow a first semiconductor region from the first semiconductor seed layer; and
forming an additional semiconductor region over the first semiconductor region to fill the trench.

US Pat. No. 10,170,303

GROUP IIIA NITRIDE GROWTH SYSTEM AND METHOD

1. A method for growing a gallium nitride (GaN) structure comprising:providing a template having a surface; and
growing at least a first GaN layer on the template using a first sputtering process, wherein the first sputtering process includes:
growing the at least first GaN layer under at least two surface conditions, wherein the two surface conditions include a gallium-rich surface condition and a gallium-lean surface condition, wherein the gallium-rich surface condition includes a gallium-to-nitrogen ratio having a first value that is greater than 1, wherein the gallium-lean surface condition includes the gallium-to-nitrogen ratio having a second value that is less than the first value;
alternating between the two surface conditions for at least a first growing under a first of the two surface conditions, a second growing under a second of the two surface conditions after the first growing, and a third growing under the first of the two surface conditions after the second growing.

US Pat. No. 10,170,300

PROTECTIVE FILM FORMING METHOD

Tokyo Electron Limited, ...

1. A protective film forming method, comprising steps of:depositing an oxide film of either an organic metal compound or an organic metalloid compound on a flat surface region between adjacent recessed shapes formed in a surface of a substrate; and
removing a lateral portion of the oxide film deposited on the flat surface region by etching.

US Pat. No. 10,170,296

TIN PULL-BACK AND CLEANING COMPOSITION

BASF SE, Ludwigshafen (D...

1. A composition, comprising the following components a)-f), based on total weight of the composition:a) 0.05-4 wt. % of an aliphatic or aromatic sulfonic acid;
b) 0.1 to 10 wt % of an inhibitor selected from the group consisting of imidazolidinones, imidazolidines, and 2-oxazolidinones;
c) 5 to 50 wt % of an aprotic solvent;
d) 1 to 60 wt % of a glycol ether;
e) water; and
an oxidant,
wherein a weight ratio of the aprotic solvent to the water is from 1:10 to 2:1 and wherein the oxidant is present in a volume ratio of components a) to e)to the oxidant ranging from 65:1 to 8:1.

US Pat. No. 10,170,293

ENHANCED LIGHTING CERAMIC METAL-HALIDE LAMP ASSEMBLY

1. An enhanced lighting ceramic metal-halide lamp assembly, the assembly comprising:an at least partially transparent container defined by an inner surface, an outer surface, a pair of sealed conductive ends, and an inner volume defined by a vacuum;
a plurality of ceramic arc tubes disposed in the inner volume of the at least partially transparent container, the ceramic arc tubes being filled with an ionizable gaseous mixture;
a ballast disposed in the inner volume of the ceramic arc tubes, the ballast comprising at least one electrode generating an electric arc through the ionizable gaseous mixture;
whereby the electric arc vaporizes the gaseous mixture to generate illumination;
whereby the ceramic arc tube produces about 630 watts of power when illuminating;
a wire extending between the pair of sealed conductive ends of the at least partially transparent container, the wire carrying an electrical current through the ballast;
two U-shaped coupling mechanisms integral to the wire, the two U-shaped coupling mechanisms connecting each of the ceramic arc tubes to one of the sealed conductive ends of the container, the two U-shaped coupling mechanisms defined by a conductive material, the two U-shaped coupling mechanisms being generally resilient;
whereby the two U-shaped coupling mechanisms provide conductivity and a buffering clearance between the ceramic arc tubes and the sealed conductive ends of the container; and
at least one fastening bracket defined by a first end and a second end, the first end engaging the inner surface of the at least partially transparent container for stabilizing the ceramic arc tubes, the second end engaging the ceramic arc tubes.

US Pat. No. 10,170,292

METHOD AND APPARATUS FOR INJECTION OF IONS INTO AN ELECTROSTATIC ION TRAP

Thermo Fisher Scientific ...

1. An apparatus for injecting ions into an electrostatic trap, comprising:an ion source for generating ions;
an ion store downstream of the ion source for receiving ions that have been generated in the ion source;
a non-trapping ion guide downstream of the ion store for receiving ions that have been released by the ion store and for accelerating the received ions into an orbital electrostatic trap downstream of the ion guide; and
a pulser configured to provide a voltage pulse in the ion guide for increasing the average velocity of the ions at the exit of the ion guide from the average velocity of the ions at the entrance to the ion guide, wherein a delay is arranged between releasing the ions from the ion store and providing the voltage pulse to the ion guide such that for ions of the same m/z forming an ion packet, the duration of the ion packet as it enters the electrostatic trap is substantially shorter than when the ion packet enters the ion guide from the ion store.

US Pat. No. 10,170,291

APPARATUS FOR ON-LINE MONITORING PARTICLE CONTAMINATION IN SPECIAL GASES

Industrial Technology Res...

1. An apparatus for on-line monitoring particle contamination in a special gas, comprising:a single particle inductively coupled plasma mass spectrometry (sp-ICPMS); and
a gas exchange device, coupled to the sp-ICPMS and comprising:
a corrosion resistant outer tube; and
a polytetrafluoroethylene (PTFE) inner tube, disposed inside the corrosion resistant outer tube, a gap being formed between the corrosion resistant outer tube and the PTFE inner tube, and a length of the PTFE inner tube being 1 meter or more, wherein
the gap is applied for flowing an argon gas, and the PTFE inner tube is applied for flowing the special gas.

US Pat. No. 10,170,287

TECHNIQUES FOR DETECTING MICRO-ARCING OCCURRING INSIDE A SEMICONDUCTOR PROCESSING CHAMBER

Taiwan Semiconductor Manu...

1. A system comprising:a radio frequency (RF) generator configured to output a RF signal;
a transmission line coupled to the RF generator;
a plasma chamber coupled to RF generator via the transmission line, wherein the plasma chamber is configured to generate a plasma based on the RF signal; and
a micro-arc detecting element configured to determine whether a micro-arc has occurred in the plasma chamber based on the RF signal;
wherein the micro-arc detecting element comprises:
a magnetic-field sensor configured to generate a magnetic-field signal based on the RF signal passing through the transmission line; and
analysis circuitry configured to evaluate the magnetic-field signal to determine whether the micro-arc has occurred in the plasma chamber.

US Pat. No. 10,170,283

FOCUS RING FOR PLASMA PROCESSING APPARATUS

COORSTEK KK, Tokyo (JP)

1. A focus ring made of silicon comprising:a plurality of arc-shaped members, each of the plurality of arc-shaped members including a flat plate portion having an arc shape, open-topped first depressions formed at both circumferential ends of the flat plate portion, a stepped portion formed with an open-topped second depression at an inner circumferential side of the flat plate portion, and convex fitting portions formed on bottom surfaces of the first depressions;
a plurality of connecting members connecting the plurality of arc-shaped members to form a ring shape without an adhesive, each of the plurality of connecting members including a plate-like main body having an arc shape to be accommodated within the first depressions of the adjacent arc-shaped members, a stepped portion formed with an open-topped depression at an inner circumferential side of the plate-like main body, and concave fitting portions formed in a lower surface of the plate-like main body and configured to engage with the respective convex fitting portions of the adjacent arc-shaped members,
wherein a thickness between an upper surface of the connecting member and a bottom surface of the concave fitting portion of the connecting member is greater than a thickness between an upper surface of the arc-shaped member and a bottom surface of the second depression of the arc-shaped member; and
wherein the plurality of arc-shaped members is disposed to be in contact with one another at opposing end portions of the arc-shaped members, thereby forming a ring shape, and the connecting members are accommodated in the first depressions of the adjacent arc-shaped members, and wherein the plurality of arc-shaped members is connected with the connecting members whereby the concave fitting portions of the connecting members are engaged with the convex fitting portions of the arc-shaped members,
wherein the concave fitting portions of the connecting members are not positioned above end surfaces of the opposing end portions of the adjacent arc-shaped members, and
wherein when the connecting member engages the arc-shaped members, a gap is formed between the convex fitting portion of the arc-shaped member and the concave fitting portion of the connecting member, the gap being equal to or greater than 50 ?m and equal to or less than 100 ?m.

US Pat. No. 10,170,276

METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-OUTLIER-TREATMENT FOR OPTIMIZED PATTERN DENSITY UNIFORMITY

TAIWAN SEMICONDUCTOR MANU...

1. A method of semiconductor device fabrication, comprising:receiving an integrated circuit (IC) layout pattern including a plurality of templates;
identifying, from the plurality of templates, a first template having a first layout pattern with a first pattern density (PD) and a second template having a second layout pattern with a second PD less than the first PD;
splitting the first template into a plurality of subset templates, wherein each subset template of the plurality of subset templates includes a portion of the first layout pattern, and wherein each subset template has a subset PD that satisfies a PD target;
performing a PD uniformity (PDU) optimization to the second template; and
performing multiple individual electron beam (e-beam) lithography exposure processes with an e-beam lithography tool to a semiconductor substrate, using respective ones of the subset templates, thereby patterning the semiconductor substrate.

US Pat. No. 10,170,275

CRYOGENIC SPECIMEN PROCESSING IN A CHARGED PARTICLE MICROSCOPE

FEI Company, Hillsboro, ...

1. A method comprising:directing a charged-particle beam onto a portion of a specimen, situated in a vacuum chamber and maintained at a cryogenic temperature so as to perform a surface modification thereof;
providing a thin film monitor in the vacuum chamber and maintaining at least a detection surface thereof at a cryogenic temperature; and
using the thin film monitor to measure a precipitation rate of frozen condensate in the vacuum chamber,
wherein when either the precipitation rate falls below a first pre-defined threshold, the surface modification is initiated, or when the precipitation rate rises above a second pre-defined threshold, the surface modification is interrupted, or both.

US Pat. No. 10,170,272

SYSTEM AND METHOD FOR USE IN ELECTRON MICROSCOPY

1. An electron beam shaping unit for use in electron beam column, the electron beam shaping unit is configured for affecting multi electron wave function and comprising a mask unit configured for affecting propagation of electrons therethrough to thereby form at far field thereof a propagating electron beam having radial shape as determined by MENL function being an eigen function determined by a multi-electron Hartree-Fock Hamiltonian.

US Pat. No. 10,170,270

ION SOURCE

WISCONSIN ALUMNI RESEARCH...

1. An ion source device for producing an ion beam, comprising:a housing having an opening;
a first electrode within the housing and having a first side facing the opening, the first electrode is configured to provide a first electric field toward the opening; and
a second electrode having an end within the housing, the second electrode is configured to maintain one, or both of, a presence of electrons or a seed plasma between the first electrode and the opening when the first electric field is absent.

US Pat. No. 10,170,268

DISCRETE DYNODE ELECTRON MULTIPLIER FABRICATION METHOD

Harris Corporation, Melb...

1. A process of manufacturing a discrete-dynode electron multiplier (DDEM) comprising the steps of:mounting at least one insulator block to a monolithic conductor block;
forming a series of ion-optics geometrical structures in the monolithic conductor block, each ion-optics geometrical structure having a smallest dimension of less than 1 millimeter;
forming an opening in the monolithic conductor block; and
connecting a circuit board to the DDEM by positioning a fastener through the opening in the monolithic conductor block and through an opening in the circuit board.

US Pat. No. 10,170,266

WIRE-WOUND FUSE RESISTOR AND METHOD FOR MANUFACTURING SAME

1. A wire-wound fuse resistor, comprising:an insulating rod having a first end and a second end;
a metal wire having a wire head and a wire tail, being helically wound around the insulating rod from the first end to the second end, and being cut at a middle portion thereof to form a first winding wire connecting with the wire head and a second winding wire connecting with the wire tail, wherein the first winding wire and the second winding wire are separated from each other;
a connection part disposed at the cut portion for electrical connection between the first winding wire and the second winding wire, wherein the melting temperature of the connection part is lower than that of the first winding wire and the second winding wire; and
a first cap and a second cap respectively disposed to encapsulate the first end and the second end, in which the wire head and the wire tail are respectively soldered onto surfaces of the first cap and the second cap respectively at the first cap and the second cap, and the first cap and the second cap are respectively electroplated with a first cap electroplated layer and a second cap electroplated layer, wherein the first electroplated layer on the first cap, the second electroplated layer on the second cap and the connection part are formed in the same process, and wherein the connection part is cut off depending on a predetermined melting temperature or melting speed of the wire-wound fuse reistor.

US Pat. No. 10,170,264

INFORMATION DISPLAY SYSTEM FOR SWITCHING DEVICE, SWITCHING DEVICE, AND METHOD

ABB Schweiz AG, Baden (C...

1. An information display system for a switching device having an operating handle, the information display system comprising:a cover having a first side including an opening having the operating handle disposed therethrough, the cover first side defining a first section and a second section thereon, the first section defining a first longitudinal axis extending perpendicularly therethrough, the second section perpendicular to the first longitudinal axis; and
a faceplate including an opening to receive the operating handle therethrough, selectively secured to the first side in one of a plurality of rest positions and configured to carry information about the switching device, wherein in each one of the plurality of rest positions, at least a portion of the second section of the cover is overlapped by the faceplate, at least a portion of the first section is aligned with the opening, and the operating handle is disposed through the opening;
wherein the faceplate is rotatable with respect to the cover about the first longitudinal axis.

US Pat. No. 10,170,261

CONTACT DEVICE AND ELECTROMAGNETIC CONTACTOR USING SAME

1. A contact device comprising:a main contact mechanism that includes a pair of main fixed contacts separated from each other, a main movable contact disposed so as to be contacted with and separated from the pair of main fixed contacts, and a main contact support portion elastically supporting the main movable contact;
an auxiliary contact mechanism that is disposed at a different position from a position of the main contact mechanism, and that includes a pair of auxiliary fixed contacts separated from each other, an insulating auxiliary contact holding member supporting the main contact support portion and having an auxiliary movable contact disposed therein so as to be contacted with and separated from the pair of auxiliary fixed contacts, and an auxiliary contact support portion supporting the auxiliary contact holding member;
a contact housing portion that houses the main contact mechanism and the auxiliary contact mechanism; and
a movable iron core with which the auxiliary contact support portion is fixed,
wherein
the auxiliary contact support portion and the main contact support portion are formed as a movable shaft to move the main movable contact and the auxiliary movable contact, and
the auxiliary contact support portion and the main contact support portion are divided from each other and connected together via the auxiliary contact holding member so that the main contact support portion connects the main movable contact and the insulating auxiliary contact holding member, and the auxiliary contact support portion connects the insulating auxiliary contact holding member and the movable iron core.

US Pat. No. 10,170,260

ELECTROMAGNETIC RELAY

OMRON Corporation, Kyoto...

1. An electromagnetic relay comprising:a base;
an electromagnet block having a spool in which a through hole opening at a flange portion is formed, the electromagnet block being mounted on an upper surface of the base;
a movable iron piece configured to be rotatable based on excitation and non-excitation of the electromagnet block;
a movable contact piece configured to be rotatable integrally with the movable iron piece;
a movable contact fixed to a free end of the movable contact piece; and
a fixed contact fixed to a fixed contact terminal, and disposed so as to be connected with and separable from the movable contact along with rotation of the movable contact piece, wherein
an insulating rib is formed in a projecting manner on at least one of an inward facing surface of a spacer integrally formed with the movable iron piece and an outward facing surface of the flange portion such that the insulating rib intercepts a straight line which connects a magnetic pole portion which is one end portion of an iron core which projects from the through hole and the fixed contact or the fixed contact terminal with a shortest distance.

US Pat. No. 10,170,256

CIRCUIT BREAKER EQUIPPED WITH AN EXTENSIBLE EXHAUST COVER

GENERAL ELECTRIC TECHNOLO...

1. A medium-, high-, or very high-voltage circuit breaker, comprising at least one arc-control chamber and an outer casing defining a space in which the arc-control chamber is arranged, said arc-control chamber comprising:a first set of electrical contacts and a second set of electrical contacts, arranged at least in such a manner as to enable closing and opening operations of the circuit breaker;
an arc blast nozzle; and
a discharge cap forming a portion of an outer wall of the arc-control chamber, the discharge cap being situated in the space and internally defining a gas-flow chamber situated at least in part downstream from the blast nozzle with which the gas-flow chamber communicates, said discharge cap being suitable for including one or more openings for discharging a gas from the gas-flow chamber towards said space; and
a support that is electrically insulating and that mechanically connects the arc-control chamber to an end wall of the outer casing of the circuit breaker;
wherein the discharge cap comprises at least one portion that is movable under an effect of a gas pressure in the gas-flow chamber, so that a volume of the discharge cap is extensible.

US Pat. No. 10,170,255

VACUUM CAPACITOR SWITCH WITH PRE-INSERTION CONTACT

1. A vacuum capacitor switch with a pre-insertion contact, comprising:a vacuum enclosure;
a first contact system includes a moving contact and a stationary contact structure, said stationary contact structure includes a stationary contact support and a stationary contact, said stationary contact support includes a substantial bowl shaped cross section with angled side walls, said stationary contact extends from a bottom of said stationary contact support, said stationary contact structure is retained inside said vacuum enclosure at substantially at one end thereof, said angled side walls form an acute angle with a lengthwise axis of said vacuum enclosure; and
a second contact system includes a moving contact rod, a floating contact rod and a biasing device, said floating contact rod is retained at the other one end of said vacuum enclosure, said biasing device is retained on the other end of said vacuum enclosure, substantially one end of said floating contact rod is retained by said biasing device, the other end of said floating contact rod is biased toward the one end of said vacuum enclosure, said moving contact is retained on said moving contact rod, said biasing device includes a bracket and a threaded adjuster, said bracket is secured to said vacuum enclosure, said threaded adjuster is retained by said bracket, said floating contact rod is threadably engaged with said threaded adjuster, said floating contact rod is axially adjustable relative to said bracket, wherein a load is electrically connected between said stationary contact and said floating rod.

US Pat. No. 10,170,252

MICRO-SWITCH AND METHOD OF MANUFACTURE

JOHNSON ELECTRIC S.A., M...

1. An electric micro-switch comprising a switching mechanism having two stationary electric contacts and at least one counter contact engaged in a spring holder, wherein each stationary contact has a profiled section, and the profiled section has a longitudinal arched extension, a bent portion formed in the longitudinal arched extension and having an outer surface that is, at least in section, formed in a rounded manner, and a contact region defined on the outer surface of the bent portion, a longitudinal direction of the two stationary electric contacts is transverse to a longitudinal direction of the counter contact, the two stationary electric contacts and the spring holder are not coplanar, and a longitudinal extension of the counter contact is perpendicular to the longitudinal extension of the stationary electric contact.

US Pat. No. 10,170,250

DYE SENSITIZED PHOTOELECTRIC CONVERSION DEVICE

King Fahd University of P...

1. A dye sensitized photoelectric conversion device, comprising:a layer, comprising:
an anode,
a semiconductor, and
a light absorbing compound;
an iodine redox couple electrolytic solution, and
a passive substrate, comprising:
a cathode,
wherein the semiconductor and the light absorbing compound are between the anode and the cathode,
wherein the light absorbing compound is chemisorbed on the semiconductor;
wherein the semiconductor is a metal oxide, and
wherein the light absorbing compound has formula (I):
wherein A1 is a divalent thiophene group of formula (I?)A2 is a divalent 5-membered heterocyclic group of formula (II?), (III?), (IV?), or (V?):
A3 is an aromatic hydrocarbon chromophore of formula (VI?), (VII?), or (VIII?)

wherein R1 is H, OH, C1-C6 alkyl, Cl, Br, F, or I, m is 1 and n is 0 or 1.

US Pat. No. 10,170,248

STRUCTURE AND METHODS OF FORMING THE STRUCTURE

Micron Technology, Inc., ...

1. An apparatus, comprising:a three-dimensional (3D) memory cell region; and
a peripheral region adjacent to the memory cell region to supply at least one voltage to the 3D memory cell region, the peripheral region including:
a first conductive level, a second conductive level above the first conductive level and a third conductive level above the second conductive level, each of the conductive levels stepped back from an upper surface end portion of an underlying one of remaining ones of the conductive levels; and
first and second dielectric levels, each dielectric level disposed between respective adjacent conductive levels, each of the dielectric levels not covering at least some part of the upper surface end portion of an underlying conductive level.

US Pat. No. 10,170,247

MULTILAYER CAPACITOR AND INSTALLATION STRUCTURE OF MULTILAYER CAPACITOR

MURATA MANUFACTURING CO.,...

1. A multilayer capacitor comprising:a multilayer capacitor main body which includes first and second main surfaces, first and second side surfaces, and first and second end surfaces, the first and second main surfaces extending in a length direction and a width direction, the first and second side surfaces extending in the length direction and a thickness direction, and the first and second end surfaces extending in the width direction and the thickness direction;
a first inner electrode extending in the length direction and the thickness direction and including a first effective portion, a first extending portion, and a second extending portion, the first extending portion being connected to the first effective portion and extending to the second main surface, and the second extending portion being connected to the first effective portion and extending to the second main surface;
a second inner electrode extending in the length direction and the thickness direction and including a second effective portion and a third extending portion, the second effective portion facing the first effective portion in the width direction, and the third extending portion being connected to the second effective portion, not facing the first inner electrode, and extending to the second main surface;
a first terminal electrode which is connected to an exposed portion of the first extending portion at the second main surface and extends across a portion of the second main surface on a side of the first end surface in the length direction and the first end surface;
a second terminal electrode which is connected to the second extending portion at the second main surface and extends across a portion of the second main surface on a side of the second end surface in the length direction and the second end surface; and
a third terminal electrode which is connected to an exposed portion of the third extending portion at the second main surface and extends across a portion of the second main surface between the first terminal electrode and the second terminal electrode in the length direction; wherein
a minimum distance in a direction along the first extending portion and the second extending portion between the first effective portion and the second main surface is shorter than any of a dimension in the thickness direction of the first extending portion, a dimension in the thickness direction of the second extending portion, and a dimension in the thickness direction of the third extending portion;
a minimum distance in a direction along the third extending portion between the second effective portion and the second main surface is shorter than any of the dimension in the thickness direction of the first extending portion, the dimension in the thickness direction of the second extending portion and the dimension in the thickness direction of the third extending portion;
the first effective portion includes a first projecting portion, and a minimum distance between a center region of the first inner electrode and the second main surface is greater than a minimum distance between the first projecting portion and the second main surface;
the first inner electrode is spaced away from the first and second end surfaces;
the first projecting portion projects toward the second main surface in a region where the first extending portion, the second extending portion and the third extending portion are not provided in the length direction when viewed from the width direction;
the second effective portion includes a second projecting portion which projects toward the second main surface in a region where the first extending portion, the second extending portion and the third extending portion are not provided in the length direction when viewed from the width direction;
the first projecting portion is facing the second projecting portion in the width direction;
the first projecting portion and the second projecting portion are arranged at least between the first extending portion and the third extending portion when viewed from the width direction; and
the first projecting portion and the second projecting portion extend across from an edge of the first extending portion on a side of the second end surface in the length direction to an edge of the third extending portion on a side of the first end surface in the length direction when viewed from the width direction.

US Pat. No. 10,170,246

CAPACITOR COMPONENT WITH METALLIC PROTECTION PATTERN FOR IMPROVED MECHANICAL STRENGTH AND MOISTURE PROOF RELIABILITY

SAMSUNG ELECTRO-MECHANICS...

1. A capacitor component comprising:a body including a plurality of dielectric layers having a stacked structure, and first and second internal electrodes which are alternately disposed while having the dielectric layer interposed therebetween; and
first and second external electrodes formed on an outer surface of the body, and connected to the first and second internal electrodes, respectively,
wherein the body includes an active region having capacity by the first and second internal electrodes and a cover region located above and below the active region,
the cover region includes a protection pattern of a metal material having a plate shape connected to the first external electrode or the second external electrode,
the protection pattern does not overlap with an internal electrode having a different polarity among the first and second internal electrodes in a stacking direction of the first and second internal electrodes, and
the protection pattern has a shape having a width greater than that of either of the first and second internal electrodes.

US Pat. No. 10,170,245

METHOD OF MANUFACTURING MULTIPLAYER CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A method of manufacturing a multilayer capacitor, comprising:preparing a sheet;
forming a plurality of inner electrodes on the sheet;
cutting the sheet;
forming a laminate by laminating portions of the cut sheet;
forming a sealing portion on two lateral surfaces of the laminate; and
forming an external terminal on upper and lower surfaces of the laminate,
wherein each of the inner electrodes has at least two lead portions being respectively exposed to the upper and lower surfaces of the laminate,
wherein the inner electrodes include a fist inner electrode and a second inner electrode, the first inner electrode is exposed to the first lateral surface and unexposed from the second lateral surface, and the second inner electrode is exposed to the second lateral surface and unexposed from the fist lateral surface,
wherein the sealing portion which encapsulates the first inner electrode and a second portion which encapsulates the second inner electrode, the fist portion is disposed on the fist lateral surface and the second portion is disposed on the second lateral surface, and
wherein the sealing portion has insulating characteristics.

US Pat. No. 10,170,244

FABRICATION OF POROUS SILICON ELECTROCHEMICAL CAPACITORS

INTEL CORPORATION, Santa...

1. A method of making a charge storage structure, the method comprising:forming pores in a low-purity silicon substrate to form a low purity porous silicon structure wherein the low purity silicon substrate has a purity of 99.999 percent or less purity of silicon; and
forming an electrochemical capacitor comprising one of (1) a first low purity porous silicon structure and a second low purity porous silicon structure separated by an electrical insulator comprising a dielectric material, or (2) a first low purity porous silicon section and a second low purity porous silicon section separated by an electrical insulator comprising a dielectric material.

US Pat. No. 10,170,243

MULTILAYER CERAMIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A multilayer ceramic capacitor comprising:a multilayer body including a plurality of dielectric layers that are stacked on one another, a first main surface and a second main surface facing each other, a first side surface and a second side surface facing each other, and a first end surface and a second end surface facing each other;
inner electrodes stacked such that the inner electrodes and the plurality of dielectric layers are alternately arranged;
outer electrodes disposed on at least the first end surface and the second end surface; wherein
the inner electrodes include a first inner electrode, a second inner electrode, a third inner electrode, a fourth inner electrode, and a fifth inner electrode;
the first inner electrode, the second inner electrode, the third inner electrode, the fourth inner electrode, and the fifth inner electrode are disposed on different planes;
the first inner electrode includes a first end and a second end, the first end of the first inner electrode extending to the first end surface;
the second inner electrode includes a first end and a second end, the first end of the second inner electrode extending to the second end surface;
the third inner electrode is arranged alternately with each of the first inner electrode and the second inner electrode;
the third inner electrode includes a first end and a second end that do not extend to the first end surface or to the second end surface;
the fourth inner electrode is located between the first inner electrode or the second inner electrode that is closest to the first main surface and the fifth inner electrode;
the fourth inner electrode is located between the first inner electrode or the second inner electrode that is closest to the second main surface and the fifth inner electrode;
the fourth inner electrode includes a first portion located near the first end surface and a second portion located near the second end surface, the first portion and the second portion of the fourth inner electrode are spaced apart from each other in a center portion of the multilayer body in a length direction of the multilayer body, the first portion and the second portion of the fourth inner electrode do not extend to the first end surface or to the second end surface;
the fifth inner electrode is located closest to the first main surface of the multilayer body, and is located closest to the second main surface of the multilayer body;
the fifth inner electrode includes a first portion located near the first end surface and a second portion located near the second end surface, the first portion and the second portion of the fifth inner electrode are spaced apart from each other in the center portion of the multilayer body in the length direction of the multilayer body, an end of the first portion of the fifth inner electrode, which is closer to the first end surface, extends to the first end surface, an end of the second portion of the fifth inner electrode, which is closer to the second end surface, extends to the second end surface;
a first auxiliary electrode is disposed on a same plane as the first inner electrode and spaced apart from the first inner electrode;
a second auxiliary electrode is disposed on a same plane as the second inner electrode and spaced apart from the second inner electrode;
a third auxiliary electrode is disposed on a same plane as the third inner electrode and includes a first portion and a second portion spaced apart from each other with the third inner electrode therebetween;
a fourth auxiliary electrode is disposed on a same plane as the fourth inner electrode and includes a first portion and a second portion such that the first portion and the second portion of the fourth auxiliary electrode are spaced apart from the first portion and the second portion of the fourth inner electrode, respectively;
the first auxiliary electrode extends to the second end surface;
the second auxiliary electrode extends to the first end surface;
the first portion of the third auxiliary electrode extends to the first end surface;
the second portion of the third auxiliary electrode extends to the second end surface;
the first portion of the fourth auxiliary electrode extends to the first end surface;
the second portion of the fourth auxiliary electrode extends to the second end surface.

US Pat. No. 10,170,242

COMPOSITE ELECTRONIC COMPONENT, METHOD OF MANUFACTURING THE SAME, BOARD FOR MOUNTING THEREOF, AND PACKAGING UNIT THEREOF

SAMSUNG ELECTRO-MECHANICS...

1. A composite electronic component comprising:a composite body including a capacitor and an electrostatic discharge (ESD) protection device coupled to each other, the capacitor including a ceramic body in which a plurality of dielectric layers and internal electrodes are stacked with a respective dielectric layer interposed between the internal electrodes, and the ESD protection device including first and second electrodes disposed on the ceramic body, a discharging part disposed between the first and second electrodes, and a protective layer disposed on the first and second electrodes and the discharging part to substantially cover the entirety of upper surfaces of the first and second electrodes and the discharging part;
an input terminal disposed to cover an entirety of a first end surface of the composite body in a length direction of the composite body, partially disposed on a surface of the protective layer in a thickness direction, and connected to internal electrodes of the capacitor and the first electrode; and
a ground terminal disposed to cover an entirety of a second end surface of the composite body in the length direction, partially disposed on a surface of the protective layer in a thickness direction, and connected to internal electrodes of the capacitor and the second electrode,
wherein the protective layer ends, in the length direction, at a respective end surface of the composite body.

US Pat. No. 10,170,241

MULTILAYER ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

Samsung Electro-Mechanics...

1. A multilayer electronic component, comprising:a multilayer body comprising stacked insulating layers and internal coil parts disposed on the insulating layers;
external electrodes disposed on an outer portion of the multilayer body and connected to the internal coil parts; and
a material layer disposed on an outer surface of an outermost internal coil part among the internal coil parts and having a specific resistance that is lower than a specific resistance of the internal coil parts,
wherein the outermost coil part is disposed adjacent to a side surface of the multilayer body.