US Pat. No. 10,797,182

TRENCH SEMICONDUCTOR DEVICE HAVING SHAPED GATE DIELECTRIC AND GATE ELECTRODE STRUCTURES AND METHOD

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device comprising:a region of semiconductor material having a first major surface and a second major surface opposite to the first major surface;
a trench structure comprising:
a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view; and
a first conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region; and
a second conductive material having a first portion disposed adjacent the first major surface on opposing sides of the trench structure to provide a Schottky contact region, and a second portion disposed in the trench above and coupled to the first conductive material, wherein:
the Schottky contact region comprises an upper surface residing on a second horizontal plane in the cross-sectional view,
the dielectric region is disposed along opposing sidewall surfaces of the trench and disposed along a lower surface of the trench;
the dielectric region comprises a first uppermost surface;
a major portion of the first uppermost surface is disposed above the first horizontal plane in the cross-sectional view; and
at least a portion of the first uppermost surface of the dielectric region extends above an upper surface of the second portion of the second conductive material in the cross-sectional view.

US Pat. No. 10,797,181

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

HOSEI UNIVERSITY, Tokyo ...

1. A semiconductor device that functions as a pn-junction diode, comprising:a first semiconductor layer with n-type conductivity, containing a gallium nitride-based semiconductor;
a second semiconductor layer with p-type conductivity, which is laminated directly on the first semiconductor layer, and contains a gallium nitride-based semiconductor added with a p-type impurity at a concentration of more than 1?1020 cm?3;
a first electrode disposed in contact with the first semiconductor layer; and
a second electrode disposed in contact with the second semiconductor layer,
wherein a thickness of the second semiconductor layer is less than 100 nm, and
the second semiconductor layer is only a single semiconductor layer with p-type conductivity in the semiconductor device.

US Pat. No. 10,797,180

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising the steps of:forming a first insulating layer;
forming an island-shaped first oxide insulating layer, an island-shaped oxide semiconductor layer, and an island-shaped first conductive layer over the first insulating layer;
performing first etching on part of the island-shaped first conductive layer using a first mask to form a source electrode layer and a drain electrode layer over the island-shaped oxide semiconductor layer;
forming a second oxide insulating film over the first insulating layer, the island-shaped oxide semiconductor layer, the source electrode layer, and the drain electrode layer;
forming a first insulating film over the second oxide insulating film;
forming a second conductive film over the first insulating film;
performing second etching on part of the second conductive film and part of the first insulating film using a second mask to form a gate electrode layer and a gate insulating layer and to expose part of a side surface of the gate insulating layer;
forming a second insulating film over the first insulating layer, the source electrode layer, the drain electrode layer, and the gate electrode layer; and
performing third etching on part of the second insulating film and part of the second oxide insulating film using a third mask to form a second insulating layer and a second oxide insulating layer,
wherein the second insulating layer comprises a region in contact with the side surface of the gate insulating layer.

US Pat. No. 10,797,179

SEMICONDUCTOR DEVICE HAVING GATE ELECTRODE OVERLAPPING SEMICONDUCTOR FILM

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor comprising:
a first conductive layer over a substrate;
a first insulating film over the first conductive layer;
a semiconductor film comprising a channel formation region over and in direct contact with the first insulating film, the semiconductor film containing silicon;
a second insulating film over the semiconductor film;
a second conductive layer;
a third conductive layer over the second insulating film; and
a fourth conductive layer over the second insulating film,
wherein a first region of the second conductive layer is over the semiconductor film,
wherein in a cross section in a channel width direction of the transistor, the second conductive layer continuously covers a first side surface, a top surface, and a second side surface of the semiconductor film,
wherein in the cross section in the channel width direction of the transistor, the second insulating film is between the second conductive layer and the first side surface, the top surface, and the second side surface of the semiconductor film,
wherein in a cross section in a channel length direction of the transistor, a width of the second conductive layer is smaller than a distance between the third conductive layer and the fourth conductive layer, and
wherein a second region of the second conductive layer is in direct contact with the first conductive layer through an opening in the first insulating film.

US Pat. No. 10,797,178

MULTI-GATE FINFET INCLUDING NEGATIVE CAPACITOR, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE

Institute of Microelectro...

1. A Fin Field Effect Transistor (FinFET), comprising:a fin extending in a first direction on a substrate;
a first gate extending in a second direction crossing the first direction on the substrate on a first side of the fin to intersect the fin;
a second gate opposite to the first gate and extending in the second direction on the substrate on a second side of the fin opposite to the first side to intersect the fin;
a metallization stack provided on the substrate and above the fin and the first and second gates; and
a negative capacitor formed in the metallization stack and connected to the second gate,
wherein the negative capacitor has a capacitance whose absolute value is less than that of a second gate capacitor caused by the second gate.

US Pat. No. 10,797,177

METHOD TO IMPROVE FINFET DEVICE PERFORMANCE

SEMICONDUCTOR MANUFACTURI...

1. A method of forming a semiconductor structure, the method comprising:providing a substrate structure comprising a PMOS region and an NMOS region, the PMOS region including a first semiconductor region, a first gate structure on the first semiconductor region, and a first source region and a first drain region in the first semiconductor region on opposite sides of the first gate structure, the NMOS region including a second semiconductor region and a second gate structure on the second semiconductor region;
epitaxially growing a SiGe material in the first source and drain regions;
implanting a dose of p-type dopant into the SiGe material;
performing a first spike annealing process;
after implanting the dose of p-type dopant into the SiGe material, forming a recess in the second semiconductor region on opposite sides of the second gate structure;
epitaxially growing a SiP material in the recess;
implanting a dose of n-type dopant into the SiP material;
forming a silicon oxide layer on the SIP material; and
performing a second spike annealing process after forming a silicon oxide layer on the SIP material.

US Pat. No. 10,797,176

SELECTIVE GROWTH FOR HIGH-ASPECT RATIO METAL FILL

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a gate structure disposed over a substrate, the gate structure including a gate electrode;
an interlevel dielectric layer disposed over the gate structure,
an adhesion layer disposed within interlevel dielectric layer and having a first sidewall and an opposing second sidewall such that a bottom surface of the adhesion layer extends from the first sidewall to the second sidewall of the adhesion layer, the bottom surface of the adhesion layer interfacing with the gate electrode;
a growth control material disposed along the first and second sidewalls of the adhesion layer without being disposed on the bottom surface of the adhesion layer, wherein the growth control material has a first width along an upper portion of the first sidewall of the adhesion layer and a second width along a lower portion of the first sidewall, the first width being different than the second width; and
a conductive fill material disposed on the growth control material and on the bottom surface of the adhesion layer.

US Pat. No. 10,797,175

FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a fin protruding above a substrate, the fin having a first portion and a second portion, the first portion being in a PMOS region, and the second portion being in an NMOS region;
a first gate structure over the first portion of the fin in the PMOS region;
first gate spacers extending along opposing sidewalls of the first gate structure;
a second gate structure over the second portion of the fin in the NMOS region;
second gate spacers extending along opposing sidewalls of the second gate structure;
first epitaxial source/drain regions on opposing sides of the first gate structure and over the first portion of the fin, the first epitaxial source/drain regions being in the PMOS region and extending along a first upper surface of the first portion of the fin and along first sidewalls of the first portion of the fin; and
second epitaxial source/drain regions on opposing sides of the second gate structure and over the second portion of the fin, the second epitaxial source/drain regions being in the NMOS region and over a second upper surface of the second portion of the fin, wherein a first distance between the first gate spacers and respective first epitaxial source/drain regions is greater than a second distance between the second gate spacers and respective second epitaxial source/drain regions.

US Pat. No. 10,797,174

SEMICONDUCTOR DEVICE WITH FIN END SPACER DUMMY GATE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:forming a first isolation insulating layer between fins;
forming a sacrificial oxide layer over the fins and the first isolation insulating layer;
forming first sacrificial gate layers on the fins and second sacrificial gate layers on edge regions of the fins at an end in a lengthwise direction of the fins;
forming sidewall spacer layers on opposing side faces of the first and second sacrificial gate layers;
etching source/drain regions of the fins, which are not covered by the sidewall spacer layers and the first and second sacrificial gate layers, thereby forming source/drain spaces;
forming source/drain epitaxial layers in the source/drain spaces;
forming interlayer dielectric layers on the source/drain epitaxial layers;
at least partially removing the second sacrificial gate layers, thereby forming second gate spaces; and
forming spacer dummy gate layers in the second gate spaces,
wherein the second sacrificial gate layers are only partially removed leaving remaining second sacrificial layers and the spacer dummy gate layers are formed on the remaining second sacrificial layers.

US Pat. No. 10,797,173

MOS DEVICES WITH NON-UNIFORM P-TYPE IMPURITY PROFILE

Taiwan Semiconductor Manu...

1. A method comprising:forming a first gate stack and a second gate stack over a semiconductor substrate;
etching a portion of the semiconductor substrate between the first gate stack and the second gate stack to form an opening extending into the semiconductor substrate;
forming a silicon germanium region in the opening, wherein upper portions of the silicon germanium region have germanium concentrations higher than or equal to respective lower portions of the silicon germanium region, and the upper portions of the silicon germanium region comprise a p-type impurity having p-type impurity concentrations higher than or equal to the respective lower portions of the silicon germanium region, with a top layer of the silicon germanium region having a higher p-type impurity concentration than a bottom layer of the silicon germanium region; and
at a time after a top surface of the silicon germanium region is grown to be higher than an interface between the semiconductor substrate and the first gate stack, starting forming a silicon cap over and contacting the silicon germanium region.

US Pat. No. 10,797,172

METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETS USING AN ACCUMULATED CHARGE SINK-HARMONIC WRINKLE REDUCTION

pSemi Corporation, San D...

1. An RF switch circuit for switching RF signals, comprising:(A) a first RF port;
(B) a second RF port; and
(C) a pass transistor grouping having a first node coupled to the first RF port and a second node coupled to the second RF port, the pass transistor grouping comprising a first two or more accumulated charge control N-type MOSFETs (ACC N-MOSFETs) arranged in a stacked configuration; and
wherein:
(a) each ACC N-MOSFET of the first two or more ACC N-MOSFETs comprises:
(i) a first gate, a first drain, a first source, a first gate oxide layer, and a first body, wherein the first gate oxide layer is positioned between the first gate and the first body; and
(ii) two or more first accumulated charge sink (ACS) regions positioned proximate to portions of the first body, wherein each first ACS region of the two or more ACS regions is connected to the first body;
(b) the pass transistor grouping configured to couple the first RF port with the second RF port in a pass transistor grouping first state;
(c) the pass transistor grouping configured to isolate the first RF port from the second RF port in a pass transistor grouping second state, and wherein the pass transistor grouping is configured to have first bias voltages applied to the two or more ACS regions to remove or otherwise control, via the two or more first ACS regions, charge that, without the first bias voltages applied, would accumulate in the first body in the pass transistor grouping second state; and
(d) the first bias voltages being substantially negative with respect to ground, the first drain and the first source.

US Pat. No. 10,797,171

LATERALLY DIFFUSED MOSFET WITH LOCOS DOT

GLOBALFOUNDRIES SINGAPORE...

1. A structure comprising:a gate structure having a drain region and a source region; and
an oxidation extending from the gate structure to the drain region of the gate structure, the oxidation comprising a thinner oxide portion and a thicker oxide portion,
wherein the thinner oxide portion is aligned with a contact positioned between two adjacent gate structures.

US Pat. No. 10,797,170

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Hyundai Motor Company, S...

1. A semiconductor device, comprising:an n? type epitaxial layer disposed on a first surface of a substrate;
a p type region disposed on the n? type epitaxial layer;
an n+ type region disposed on the p type region;
a trench disposed in the n? type layer;
a gate insulating layer disposed within the trench;
a gate disposed on the n? type epitaxial layer, wherein the gate includes only a first gate and a second gate, the second gate disposed on the first gate, the first gate comprising only n type poly-crystalline silicon and the second gate comprising only p type poly-crystalline silicon, wherein the first gate is in contact with the second gate to form a single a PN junction portion at an interface between the first gate and the second gate, and wherein the first gate extends from a lateral surface to a lower surface of the trench and is contact with the gate insulating layer disposed at the lower surface of the trench;
an oxidation film disposed on the gate;
a source electrode disposed on the oxidation film and the n+ type region; and
a drain electrode disposed on a second surface of the substrate.

US Pat. No. 10,797,169

SILICON CARBIDE SEMICONDUCTOR DEVICE AND POWER CONVERSION APPARATUS

Mitsubishi Electric Corpo...

1. A silicon carbide semiconductor device comprising:a semiconductor substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface, the semiconductor substrate containing first conductivity type impurities;
a drain electrode provided on the first substrate surface of the semiconductor substrate;
a semiconductor layer having a first surface on the second substrate surface of the semiconductor substrate and a second surface opposite to the first surface, the semiconductor layer at least partially made of silicon carbide, the semiconductor layer including
a drift layer provided on the second substrate surface of the semiconductor substrate, the drift layer partially forming the second surface of the semiconductor layer, the drift layer containing the first conductivity type impurities,
a well region provided on the drift layer, the well region partially forming the second surface of the semiconductor layer, the well region containing second conductivity type impurities different from the first conductivity type impurities,
a source region provided on the well region, the source region separated from the drift layer by the well region, the source region partially forming the second surface of the semiconductor layer, the source region containing the first conductivity type impurities, and
a well contact region in contact with the well region, the well contact region partially forming the second surface of the semiconductor layer, the well contact region containing the second conductivity type impurities, the well contact region having an impurity concentration at the second surface higher than an impurity concentration at the second surface of the well region;
a gate insulating film covering the well region between the source region and the drift layer;
a gate electrode provided on the gate insulating film;
a Schottky electrode in contact with the drift layer;
a source ohmic electrode in contact with the source region on the second surface of the semiconductor layer;
a resistor in contact with the well contact region on the second surface of the semiconductor layer, the resistor having higher resistance per unit area than the source ohmic electrode; and
a source electrode electrically connected to each of the Schottky electrode, the source ohmic electrode, and the resistor.

US Pat. No. 10,797,168

ELECTRONIC DEVICE INCLUDING A HIGH ELECTRON MOBILITY TRANSISTOR THAT INCLUDES A BARRIER LAYER HAVING DIFFERENT PORTIONS

SEMICONDUCTOR COMPONENTS ...

1. An electronic device comprising a high electron mobility transistor comprising:a channel layer;
a first barrier layer including a first portion, a second portion, and a third portion; and
a gate electrode of the high electron mobility transistor,
wherein:
the first barrier layer is disposed between the channel layer and the gate electrode,
the second portion of the first barrier layer is spaced apart from the channel layer by the first portion of the first barrier layer,
the second portion of the first barrier layer is spaced apart from the gate electrode by the third portion of the first barrier layer,
the second portion of the first barrier layer has a semiconductor base material different from a semiconductor base material of each of the first portion of the barrier layer and the third portion of the first barrier layer, and
the second portion of the first barrier layer is configured to trap more charge, more readily recombine electrons and holes, or both as compared to each of the first and third portions of the first barrier layer.

US Pat. No. 10,797,167

SUPERJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR COMPONENTS ...

1. A method, comprising:forming a plurality of first active pillars and a plurality of edge pillars in a first semiconductor layer including an active region and a termination region;
forming a second semiconductor layer on the first semiconductor layer; and
forming a plurality of second active pillars and a plurality of preliminary charge balance layers in the second semiconductor layer,
the plurality of first active pillars and the plurality of second active pillars having impurities diffused such that the plurality of first active pillars and the plurality of second active pillars are connected.

US Pat. No. 10,797,166

MANUFACTURING METHOD FOR IGZO ACTIVE LAYER AND OXIDE THIN FILM TRANSISTOR

SHENZHEN CHINA STAR OPTOE...

1. A manufacturing method for an IGZO active layer, comprising steps of:after depositing a first metal layer and a gate insulation layer on a substrate, depositing an IGZO material on the gate insulation layer, and forming an IGZO film; and
performing a plasma cleaning treatment on a surface of the IGZO film by using an argon gas or a helium gas to adjust element contents on the surface of the IGZO film to form an IGZO active layer;
wherein the plasma cleaning treatment uses a power of 3000˜4000 watts; a gas pressure of 30˜50 mTorr; a gas flow rate of 500˜1000 standard milliliter/min, and a processing time of 5˜20 seconds.

US Pat. No. 10,797,165

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

12. A semiconductor device comprising:a well region in a substrate;
a semiconductor pattern on a well region, the semiconductor pattern being doped with an impurity;
isolation patterns in the well region at opposite sides of the semiconductor pattern;
a gate electrode covering the semiconductor pattern and the isolation patterns; and
source/drain regions on the well region at opposite sides of the gate electrode,
wherein the semiconductor pattern is interposed between the source/drain regions,
wherein a doping concentration of the impurity in the semiconductor pattern increases in a direction from an upper portion of the semiconductor pattern, adjacent to the gate electrode, to a lower portion of the semiconductor pattern, adjacent to the well region,
wherein the well region includes a dopant of a first conductivity type,
wherein the dopant of the first conductivity type includes a different element from the impurity in the semiconductor pattern; and
wherein a lower surface of the semiconductor pattern and lower surfaces of the source/drain regions are in contact with the well region.

US Pat. No. 10,797,164

FINFETS HAVING EPITAXIAL CAPPING LAYER ON FIN AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:patterning a semiconductor substrate to form a semiconductor fin on the semiconductor substrate, the patterning forming a top surface and sidewalls of the semiconductor fin, the top surface and the sidewalls of the semiconductor fin having a same material composition;
forming an isolation region on the semiconductor substrate, the isolation region surrounding the semiconductor fin;
implanting dopants into the semiconductor fin;
after implanting dopants into the semiconductor fin, recessing the isolation region to expose an upper portion of the semiconductor fin;
homoepitaxially growing a capping layer from the top surface and sidewalls of the semiconductor fin, the top surface and the sidewalls of the semiconductor fin being on the upper portion of the semiconductor fin; and
forming a gate dielectric layer over the capping layer, the gate dielectric layer contacting sidewalls of the capping layer and the semiconductor fin.

US Pat. No. 10,797,163

LEAKAGE CONTROL FOR GATE-ALL-AROUND FIELD-EFFECT TRANSISTOR DEVICES

International Business Ma...

1. A method for fabricating a semiconductor device, comprising:forming a first epitaxial semiconductor layer on a surface of a semiconductor substrate;
forming a screening layer over the first epitaxial semiconductor layer;
performing an ion implantation process to form an embedded insulation layer within the semiconductor substrate below the first epitaxial semiconductor layer;
forming a nanosheet field-effect transistor device over the embedded insulation layer, wherein the nanosheet field-effect transistor device comprises a plurality of active nanosheet channel layers, source/drain layers in contact with end portions of the active nanosheet channel layers, and a high-k dielectric/metal gate structure formed around the active nanosheet channel layers;
wherein forming the nanosheet field-effect transistor device comprises removing the first epitaxial semiconductor layer to release the active nanosheet channel layers;
wherein the embedded insulation layer isolates the high-k dielectric/metal gate structure and the source/drain layers from the semiconductor substrate;
wherein the screening layer is formed over the first epitaxial semiconductor layer, prior to performing the oxygen ion implantation process; and
wherein performing the ion implantation process to form the embedded insulation layer within the semiconductor substrate below the first epitaxial semiconductor layer comprises:
performing an oxygen ion implantation process to form an oxygen ion implant region within an upper surface region of the semiconductor substrate below the first epitaxial semiconductor layer; and
performing a thermal anneal process to convert the oxygen ion implant region to an embedded oxide layer.

US Pat. No. 10,797,162

FINFET DEVICE HAVING A CHANNEL DEFINED IN A DIAMOND-LIKE SHAPE SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:providing a substrate having a fin structure of a first semiconductor material disposed between an isolation feature, wherein the isolation feature has a top surface facing away from the substrate;
after providing the substrate having the fin structure of the first semiconductor material disposed between the isolation feature, recessing the fin structure to form a trench by removing a portion of the first semiconductor material from the fin structure;
epitaxially growing a second semiconductor material directly on a surface of the recessed fin structure within the trench to form a semiconductor structure on the fin structure, wherein the surface is formed of the first semiconductor material;
after epitaxially growing a second semiconductor material, forming a gate dielectric layer directly on the semiconductor structure; and
forming a gate electrode layer over the gate dielectric layer, wherein the second semiconductor material is disposed directly on the top surface of the isolation feature after forming the gate electrode layer over the gate dielectric layer.

US Pat. No. 10,797,161

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE USING SELECTIVE FORMING PROCESS

Taiwan Semiconductor Manu...

1. A method for manufacturing a semiconductor structure, comprising:forming a gate structure over a substrate;
forming a source/drain structure adjacent to the gate structure;
recessing the gate structure to form a recess;
forming a mask structure in the recess over the gate structure;
forming a contact over the source/drain structure;
selectively forming a metal-containing layer over a top surface of the contact;
forming a dielectric layer over the substrate and covering the gate structure and the contact;
forming a trench through the dielectric layer and the metal-containing layer to expose the top surface of the contact; and
forming a conductive structure in the trench.

US Pat. No. 10,797,160

METHODS OF FABRICATING SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

11. A method of fabricating a semiconductor device, the method comprising:forming a multi-layer dielectric film structure on a substrate on which a fin structure is formed, wherein the multi-layer dielectric film structure comprises a plurality of dielectric films that are stacked;
performing oxygen plasma processing on the substrate; and
forming a gate line on the multi-layer dielectric film structure that has undergone the oxygen plasma processing,
wherein the fin structure is not lost during the performing of the oxygen plasma processing,
wherein the multi-layer dielectric film structure comprises a lower dielectric film and an upper dielectric film, and
wherein a thickness of the lower dielectric film is less than a thickness of the upper dielectric film.

US Pat. No. 10,797,159

POLY FINGER FABRICATION FOR HCI DEGRADATION IMPROVEMENT OF ULTRA-LOW-RON EDNMOS

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:a gate oxide (GOX) layer over a substrate;
a first gate and plurality of fingers over the GOX layer;
a second gate and plurality of fingers over the GOX layer, the first and second gates and respective plurality of fingers laterally separated;
an oxide layer along sidewalls of the first and second gates and plurality of fingers and over portions of the GOX layer, wherein the oxide layer comprises:
an oxidation layer,
a first low temperature oxide (LTO) layer over the oxidation layer, and
a second LTO layer over the first LTO layer;
a nitride spacer over and adjacent to the oxide layer on opposite sides of each gate and plurality of fingers; and
S/D regions laterally separated in the substrate, each S/D region adjacent to a nitride spacer.

US Pat. No. 10,797,158

TRANSISTOR COMPRISING A LENGTHENED GATE

STMicroelectronics (Rouss...

1. An integrated MOS transistor, comprising:an active zone including a source region and a drain region of the integrated MOS transistor, the active zone being surrounded by an insulating region;
a conductive gate region of the integrated MOS transistor extending transversely to a source-drain direction and overlapping two opposite edges of the active zone at overlap zones;
wherein the conductive gate region includes a central zone having a first height; and
wherein the conductive gate region further includes, at a location of one of the source region or drain region:
a first conductive stair projecting perpendicularly from the central zone and extending along an entirety of the width of the active zone and further covering parts of the insulating region, the first conductive stair having a second height which is less than the first height; and
a second conductive stair above the first conductive stair and projecting perpendicularly from the central zone and extending along an entirety of the width of the active zone and further covering parts of the insulating region, the second conductive stair having a third height which is less than the first height.

US Pat. No. 10,797,157

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A method for fabricating semiconductor device, comprising:forming a gate structure on a substrate;
forming a polymer block on a corner between the gate structure and the substrate;
performing an oxidation process to form a first seal layer on sidewalls of the gate structure; and
forming a source/drain region adjacent to two sides of the gate structure.

US Pat. No. 10,797,156

METHOD OF FORMING THE GATE ELECTRODE OF FIELD EFFECT TRANSISTOR

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature;
performing a first chemical mechanical planarization (CMP) to expose the gate; and
performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.

US Pat. No. 10,797,155

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a substrate;
gate structures, disposed on the substrate, wherein each of the gate structures comprises:
a gate, disposed on the substrate;
a first spacer, disposed on a sidewall of the gate; and
a second spacer, disposed on the first spacer,
wherein the first spacers of two adjacent gate structures of the gate structures are separated from each other, the second spacers of the two adjacent gate structures of the gate structures are separated from each other, an upper portion of each of the second spacers has a recess, an entire surface of the recess is a concave curved surface, the concave curved surface has a first end and a second end higher than the first end, the first end of the concave curved surface is lower than a top of the second spacer, a distance between the concave curved surface and a bottom surface of the second spacer gradually decreases from the second end to the first end and a distance between the bottom surface of the second spacer and the first end is greater than half a distance between the bottom surface of the second spacer and a top of the second spacer; and a metal silicide layer, disposed on the substrate, wherein the two adjacent gate structures are connected by the metal silicide layer.

US Pat. No. 10,797,154

TRENCH SILICIDE CONTACTS WITH HIGH SELECTIVITY PROCESS

INTERNATIONAL BUSINESS MA...

1. A device having self-aligned contacts, comprising:a first region and a second region each including:
a plurality of fins formed on a substrate; and
a first dielectric layer adjacent to at least one fin of the plurality of fins and having a bottom surface disposed directly on the substrate;
a second dielectric layer separating the first and second regions, the second dielectric layer being disposed directly on the substrate and being directly adjacent to the first dielectric layer and having a bottom surface coplanar with the bottom surface of the first dielectric layer;
the first and second regions each further including:
source/drain regions disposed on respective ones of the plurality of fins and connected to each other;
gate structures disposed between the source/drain regions, the gate structures having gate cap layers; and
a silicide contact connected to the source/drain regions, wherein the silicide contacts have a width that is larger in contact with the source/drain regions and reduced with height to a level of the gate structures.

US Pat. No. 10,797,153

PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING AN ACCESS REGION

SEMICONDUCTOR COMPONENTS ...

1. A process of forming an electronic device comprising:forming a channel layer overlying a substrate;
forming a barrier layer overlying the channel layer;
forming a p-type semiconductor layer over the barrier layer;
patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure;
forming an access region layer over the barrier layer after patterning the p-type semiconductor layer, wherein the access region layer includes AlfIngGa(1-f-g)N, wherein 0 forming a drain electrode such that, within the transistor structure, a bottommost surface of the drain electrode is spaced apart from the barrier layer by at least the access region layer; and
forming a source electrode such that, within the transistor structure, a bottommost surface of the source electrode is spaced apart from the barrier layer by at least the access region layer.

US Pat. No. 10,797,152

PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING AN ACCESS REGION

SEMICONDUCTOR COMPONENTS ...

1. A process of forming an electronic device comprising:providing a substrate and a channel layer over the substrate, wherein the channel layer includes a III-V semiconductor material;
forming a masking feature over the channel layer;
forming an access region over the channel layer;
removing at least a portion the masking feature after forming the access region; and
forming a gate dielectric layer over the channel layer after removing the at least a portion of the masking feature,
wherein forming the masking feature, forming the gate dielectric layer, or both includes depositing a first dielectric film, wherein the first dielectric film contacts the channel layer.

US Pat. No. 10,797,151

METAL GATE STRUCTURES FOR FIELD EFFECT TRANSISTORS

Taiwan Semiconductor Manu...

15. A semiconductor structure, comprising:a fin on a substrate;
an isolation region on the substrate covering a bottom portion of the fin; and
a gate stack on a portion of the fin and on a portion of the isolation region, wherein the gate stack comprises:
a dielectric stack on the fin;
a capping layer on the dielectric stack;
a barrier layer on the capping layer;
a titanium-aluminum (TiAl) stack on the barrier layer and comprising two or more TiAl layers; and
a metal fill on the TiAl stack.

US Pat. No. 10,797,150

DIFFERENTIAL WORK FUNCTION BETWEEN GATE STACK METALS TO REDUCE PARASITIC CAPACITANCE

Intel Corporation, Santa...

1. An apparatus comprising:a non-planar body on a substrate, the non-planar body comprising an electrically conducting channel material on a blocking material, the channel material disposed between junction regions and comprising a band gap different from a band gap of the blocking material, wherein the channel material has a top and sidewalls, and the blocking material has a top and sidewalls; and
a gate stack on the body, the gate stack comprising a dielectric material and a first gate electrode material comprising a first work function and a second gate electrode material comprising a second work function different from the first work function, the second gate electrode material disposed (1) over the top and along the sidewalls of the channel material and between the channel material and the first gate electrode material and (2) along a portion of the sidewalls of the blocking material, wherein the first gate electrode material is over the top and along the sidewalls of the channel material but not along the sidewalls of the blocking material.

US Pat. No. 10,797,149

THIN FILM TRANSISTOR INCLUDING HIGH-DIELECTRIC INSULATING THIN FILM AND METHOD OF FABRICATING THE SAME

Industry-University Coope...

1. A thin film transistor comprising:a semiconductor layer;
a source electrode and a drain electrode electrically contacting with the semiconductor layer;
a gate electrode positioned over or under the semiconductor layer; and
a gate insulating film positioned between the semiconductor layer and the gate electrode, made of Al2-XYXO3, and having a higher dielectric constant than SiO2,
wherein x is 1.6 to 1.82.

US Pat. No. 10,797,148

III-V SEMICONDUCTOR LAYERS, III-V SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a Group III-V seed layer on a silicon (Si) substrate, the method comprising:supplying a first source gas containing a Group V element to a surface of the Si substrate while heating the Si substrate at a first temperature, thereby terminating the surface with the Group V element;
after the supplying the first source gas containing the Group V element to the surface of the Si substrate, supplying a second source gas containing a Group III element to the surface while heating the Si substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate; and
after the nucleation layer is formed, stop supplying the second source gas, and annealing the Si substrate at a third temperature while supplying the first source gas, thereby forming a seed layer.

US Pat. No. 10,797,147

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a semiconductor structure, comprising:providing a semiconductor substrate having a fin material layer on the semiconductor substrate;
forming an isolation material layer on the fin material layer and having a bandgap greater than a bandgap of the fin material layer;
forming a stacked channel material layer on the isolation material layer, wherein the stacked channel material layer includes a sacrificial material layer and a channel material layer on the sacrificial material layer;
etching the stacked channel material layer, the isolation material layer and the fin material layer to form fins protruding from the semiconductor substrate, an isolation layer on the fins and a stacked channel layer on the isolation layer, wherein the stacked channel layer includes a sacrificial layer on the isolation layer and a channel layer on the sacrificial layer; and
removing a portion of the sacrificial layer between the isolation layer and the channel layer to form a gap under the channel layer, wherein:
the gap passes through the sacrificial layer between the isolation layer and the channel layer;
forming the gap includes:
forming a dummy gate structure across at least the stacked channel layer and covering a portion of a top surface of the stacked channel layer and portions of sidewall surfaces of the stacked channel layer on the stacked channel layer;
removing the dummy gate structure to form a gate opening to at least expose a portion of the top surface of the stacked channel layer and portions of the sidewall surfaces of the stacked channel layer; and
forming the gap by removing the portion of the sacrificial layer exposed by the gate opening; and
after forming the gap, forming the all-around gate structure by filling the gate opening and the gap.

US Pat. No. 10,797,146

THIN FILM TRANSISTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A thin film transistor substrate comprising:a substrate;
an oxide semiconductor layer on the substrate;
a gate electrode on the substrate;
a gate insulating layer between the oxide semiconductor layer and the gate electrode; and
a source electrode and a drain electrode both connected to the oxide semiconductor layer, the source electrode and the drain electrode being spaced apart from each other,
wherein the gate insulating layer comprises:
a first gate insulating layer comprising a first material and having an oxygen content lower than that of a stoichiometric composition of the first material; and
a second gate insulating layer comprising a second material substantially the same as the first material, and having an oxygen content higher than that of the first gate insulating layer, and
the first gate insulating layer and the oxide semiconductor layer directly contact each other.

US Pat. No. 10,797,145

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. An SiC semiconductor device comprising:a first conductivity type semiconductor layer including a principal plane having an off angle relative to an internal crystalline plane;
a trench formed in the semiconductor layer including a pair of side surfaces which face each other, the trench having a tapered shape by narrowing a distance between the pair of side surfaces from the principal plane toward a depth direction of the trench, wherein
an inclination of one side of the pair of side surfaces relative to a perpendicular plane of the internal crystalline plane is smaller than an inclination of an other side of the pair of side surfaces relative to the perpendicular plane of the internal crystalline plane, and
the inclination of the one side of the pair of side surfaces is less than 3° and exceeding 1°.

US Pat. No. 10,797,144

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a base body including a first insulating film and a first semiconductor part provided above the first insulating film;
a stacked body provided above the base body, the stacked body including a plurality of conductive layers and a plurality of insulating layers, the conductive layers and the insulating layers being stacked alternately; and
a first columnar part provided inside the stacked body and inside the first semiconductor part, the first columnar part including a semiconductor body and a memory film, the semiconductor body extending in a stacking direction of the stacked body and being electrically connected to the first semiconductor part, the memory film including a charge trapping portion between the semiconductor body and one of conductive layers,
the first columnar part having a first diameter in a first direction crossing the stacking direction inside the first semiconductor part and a second diameter in the first direction inside the stacked body, the first diameter being larger than the second diameter,
the first semiconductor part including a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, the second semiconductor layer contacting the first semiconductor layer and the semiconductor body, the third semiconductor layer contacting the second semiconductor layer, and
the first columnar part including a first portion surrounded with the third semiconductor layer, the first diameter being a diameter of the first portion.

US Pat. No. 10,797,143

SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a plurality of gate electrodes stacked on a substrate and spaced apart from each other in a vertical direction; and
a channel region extending through the plurality of gate electrodes in the vertical direction,
wherein each of the plurality of gate electrodes includes a first conductive layer defining a recess recessed toward the channel region, and a second conductive layer in the recess defined by the first conductive layer, and the first conductive layer is between the channel region and the second conductive layer,
wherein a first concentration of impurities in the second conductive layer is higher than a second concentration of the impurities in the first conductive layer, and the impurities include nitrogen (N),
wherein the impurities further include at least one of fluorine (F), chlorine (Cl), and carbon (C), and a nitrogen concentration in the second conductive layer is lower than a concentration of fluorine, chlorine, and carbon in the second conductive layer.

US Pat. No. 10,797,142

FINFET-BASED SPLIT GATE NON-VOLATILE FLASH MEMORY WITH EXTENDED SOURCE LINE FINFET, AND METHOD OF FABRICATION

Silicon Storage Technolog...

1. A memory device, comprising:a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins including first and second side surfaces that oppose each other and that terminate in a top surface;
a first fin of the plurality of fins has a length that extends in a first direction;
a second fin of the plurality of fins has a length that extends in the first direction;
a third fin of the plurality of fins has a length that extends in a second direction that is perpendicular to the first direction;
a memory cell, comprising:
spaced apart first source and first drain regions in the first fin, with a first channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the first source and first drain regions, wherein the first source region is disposed at an intersection of the first and third fins,
spaced apart second source and second drain regions in the second fin, with a second channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the second source and second drain regions, wherein the second source region is disposed at an intersection of the second and third fins,
a floating gate disposed laterally between and insulated from the first and second fins, and is disposed laterally adjacent to and insulated from the third fin, wherein the floating gate extends along and is insulated from a first portion of the first channel region and a first portion of the second channel region,
a word line gate that extends along and is insulated from a second portion of the first channel region and a second portion of the second channel region,
a control gate that is disposed over and insulated from the floating gate, and
an erase gate that includes a first portion disposed over and insulated from the first and second source regions and a second portion that is disposed over and insulated from the floating gate.

US Pat. No. 10,797,141

SEMICONDUCTOR DEVICE

MITSUBISHI ELECTRIC CORPO...

1. A semiconductor device comprising:an underlying substrate having a first main surface and a second main surface which are opposed to each other;
a semiconductor layer formed on the first main surface;
electrode patterns in which a drain electrode and a source electrode are alternately arranged along at least one array direction determined in advance, on the semiconductor layer; and
a group of gate fingers, each gate finger having a shape extending in an extending direction different from the at least one array direction on the semiconductor layer, and the each gate finger being disposed in a region between the drain electrode and the source electrode, wherein:
the group of gate fingers includes a plurality of gate fingers which are arranged at a first position and a second position which are different positions in the extending direction; and
the plurality of gate fingers includes a plurality of first gate fingers arranged in a row along the at least one array direction at the first position, and at least one second gate finger disposed adjacent to at least one of the first gate fingers via the source electrode or the drain electrode, at the second position,
the at least one second gate finger being disposed in a region allowing an overlapping region between the at least one second gate finger and the plurality of first gate fingers to vanish as viewed from the at least one array direction.

US Pat. No. 10,797,140

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:epitaxially growing a source/drain region over a semiconductor region and adjacent to a first spacer;
covering the source/drain region with a dielectric material;
removing a first portion of the dielectric material to expose the source/drain region, wherein after the removing the first portion a second portion of the dielectric material remains adjacent to the first spacer; and
implanting dopants into each of the first spacer, the second portion of the dielectric material, and the source/drain region.

US Pat. No. 10,797,139

METHODS OF FORMING BACKSIDE SELF-ALIGNED VIAS AND STRUCTURES FORMED THEREBY

Intel Corporation, Santa...

1. A microelectronic device structure, comprising:a fin of monocrystalline semiconductor material over a dielectric material
a gate electrode adjacent to the fin;
a drain region adjacent to the fin;
a first contact to the drain region, the first contact adjacent to the gate electrode;
a source region adjacent to the fin, and opposite the drain region;
a second contact to the source region, the second contact adjacent to the gate electrode; and
a third contact adjacent to the dielectric material, and in contact with the source region or the drain region, wherein the third contact is opposite the first contact or the second contact.

US Pat. No. 10,797,138

VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH SELF-ALIGNED CONTACTS

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a vertical-transport field-effect transistor including a first source/drain region, a second source/drain region, and a semiconductor fin arranged to project vertically from the first source/drain region to the second source/drain region, the first source/drain region and the second source/drain region each comprised of a semiconductor material;
a plurality of trench isolation regions;
a first dielectric spacer layer positioned on the first source/drain region and the plurality of trench isolation regions;
a gate stack including a first section on the first dielectric spacer layer, a second section on the first dielectric spacer layer, and a third section on the first dielectric spacer layer, the third section of the gate stack vertically arranged between the first source/drain region and the second source/drain region, and the third section of the gate stack wrapped about the semiconductor fin to define a gate electrode of the vertical-transport field-effect transistor;
a second dielectric spacer layer positioned on the first section, the second section, and the third section of the gate stack, the semiconductor fin extending vertically through a thickness of the second dielectric spacer layer to the second source/drain region;
an interlayer dielectric layer over the second dielectric spacer layer, the interlayer dielectric layer including a first contact opening extending through the second dielectric spacer layer to the first section of the gate stack and a second contact opening extending through the second dielectric spacer layer to the second section of the gate stack;
a first gate contact in the first contact opening, the first gate contact in physical contact with the first section of the gate stack;
a second gate contact in the second contact opening, the second gate contact in physical contact with the second section of the gate stack; and
a dielectric pillar laterally arranged between the first contact opening and the second contact opening in the interlayer dielectric layer and between the first section and the second section of the gate stack.

US Pat. No. 10,797,137

METHOD FOR REDUCING SCHOTTKY BARRIER HEIGHT AND SEMICONDUCTOR DEVICE WITH REDUCED SCHOTTKY BARRIER HEIGHT

TAIWAN SEMICONDUCTOR MANU...

1. A method for controlling Schottky barrier height in a semiconductor device comprising:forming an alloy layer comprising at least a first element and a second element on a surface of a semiconductor substrate, wherein the semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements;
performing a first thermal anneal of the alloy layer and the first element-based semiconductor substrate at a temperature of 300° C. to 460° C., wherein the first thermal anneal causes the second element in the alloy layer to migrate towards a first surface of the alloy layer away from the semiconductor substrate; and
forming a Schottky contact layer on the first surface of the alloy layer after the first thermal anneal.

US Pat. No. 10,797,135

ASYMMETRIC SOURCE/DRAIN REGIONS OF TRANSISTORS

Micron Technology, Inc., ...

1. An apparatus, comprising:a first transistor and a second transistor, each having asymmetric source/drain regions, wherein:
a source/drain region of the first transistor is directly coupled to a source/drain region of the second transistor to form a junction;
a depth of the junction is greater than a depth of another source/drain region of the first transistor and a depth of another source/drain region of the second transistor;
the other source/drain regions of the first and second transistors have a same depth of a doping of a substrate material as a depth of a doping of the substrate material at the junction; and
the other source/drain regions of the first and second transistors are higher within the substrate material than the junction.

US Pat. No. 10,797,134

INTEGRATED CIRCUIT DEVICES

Samsung Electronics Co., ...

14. An integrated circuit device comprising:a substrate comprising a first active region and a second active region that are adjacent each other and spaced apart from each other in a first horizontal direction;
a device isolation region between the first active region and the second active region;
a first plurality of impurity diffusion regions in the first active region;
a second plurality of impurity diffusion regions in the second active region;
a first gate electrode over the first active region, the first gate electrode comprising a width equal to or less than a width of the first active region in the first horizontal direction;
a first insulating spacer on sidewalls of the first gate electrode and on the device isolation region;
a second gate electrode over the second active region, the second gate electrode comprising a width equal to or less than a width of the second active region in the first horizontal direction; and
a second insulating spacer on sidewalls of the second gate electrode and on the device isolation region,
wherein a separation distance between the first active region and the second active region in the first horizontal direction is constant along a second horizontal direction that is perpendicular to the first horizontal direction,
wherein a distance between the first gate electrode and the second gate electrode in the first horizontal direction is equal to or greater than the separation distance, and
wherein a first portion of the first insulating spacer and a second portion of the second insulating spacer overlap a top surface of the device isolation region.

US Pat. No. 10,797,133

METHOD FOR DEPOSITING A PHOSPHORUS DOPED SILICON ARSENIDE FILM AND RELATED SEMICONDUCTOR DEVICE STRUCTURES

ASM IP Holding B.V., Alm...

1. A method for depositing a phosphorus doped silicon arsenide film, the method comprising:providing a substrate within a reaction chamber;
heating the substrate to a deposition temperature;
exposing the substrate to a silicon precursor, an arsenic precursor, and a phosphorus dopant precursor; and
depositing the phosphorus doped silicon arsenide film over a surface of the substrate.

US Pat. No. 10,797,132

HETEROJUNCTION BIPOLAR TRANSISTOR FABRICATION USING RESIST MASK EDGE EFFECTS

Newport Fab, LLC, Newpor...

1. A method for manufacturing a heterojunction bipolar transistor, the method comprising:forming a semiconductor substrate having a first conductivity type with a buried layer region having a second conductivity type such that the buried layer region is separated from an upper surface of the semiconductor substrate by at least a portion of an intervening collector region of said semiconductor substrate;
forming a selectively implanted collector (SIC) region having the second conductivity type in said collector region such that the SIC region extends from the upper surface of the semiconductor substrate to the buried layer region;
forming a base structure having the first conductive type on the upper surface of the semiconductor substrate such that a portion of the base structure is disposed over the SIC region, thereby forming a base-collector junction of said heterojunction bipolar transistor between said base structure and said SIC region; and
forming an emitter structure having the second conductive type such that a portion of the emitter structure contacts the base structure,
wherein forming the SIC region includes:
forming an SIC implant mask including depositing a photoresist layer on the upper surface of the semiconductor substrate, and patterning said photoresist layer such that the SIC implant mask defines a plurality of mask openings that expose corresponding upper surface sections of said upper surface that are located over the collector region, and
directing dopant particles having the first conductive type toward the SIC implant mask such that first portions of said dopant particles pass directly through said plurality of mask openings and form one or more primary increased-doping regions in the collector region, and such that second portions of said dopant particles are subject to mask edge effects produced by side edges of the plurality of mask openings and form a plurality of secondary increased-doping regions in the collector region between the one or more primary increased-doping regions and the corresponding surface sections of the semiconductor substrate, whereby said secondary increased-doping regions enhance said base-collector junction.

US Pat. No. 10,797,131

ENHANCEMENTS TO CELL LAYOUT AND FABRICATION TECHNIQUES FOR MOS-GATED DEVICES

Pakal Technologies, Inc.,...

1. An electronic device comprising:a trench in a semiconductor material, the trench having sidewalls;
dopants of a first conductivity type implanted into a portion of at least one sidewall of the trench so that the dopants are not implanted into a lower portion of the sidewall, the implanted dopants for controlling a threshold voltage (Vth) of a MOSFET having a channel along the sidewall of the trench;
a first region of the first conductivity type abutting at least the lower portion of the sidewall and extending below the trench;
a second region of the first conductivity type abutting at least an upper portion of the sidewall such the channel extends between the first region and the second region;
a dielectric layer along the sidewalls of the trench;
a conductive material at least partially filling the trench to form a vertical gate for the MOSFET, wherein a voltage applied to the gate controls a conductivity of the MOSFET; and
a vertical, controllable conduction device, whose conductivity is controlled by the voltage applied to the gate, wherein the controllable conduction device includes at least a vertical bipolar transistor having an emitter and a base,
wherein the MOSFET, in response to a first gate voltage, reduces a base width of the bipolar transistor to turn on the controllable conduction device, and
wherein the MOSFET, in response to a second gate voltage, electrically connects the emitter to the base to turn off the bipolar transistor, which turns off the controllable conduction device.

US Pat. No. 10,797,130

SEMICONDUCTOR DEVICE

SANKEN ELECTRIC CO., LTD....

1. A semiconductor device including a cell region and a termination region arranged around the cell region, comprising:a substrate;
a first semiconductor region of a first conductivity type arranged in the cell region on a first surface side of the substrate;
a second semiconductor region of a second conductivity type arranged in the cell region on the first surface side of the substrate;
a channel stopper electrode arranged in the termination region on the first surface side of the substrate;
a first electrode arranged on the first surface of the substrate and electrically connected to the second semiconductor region;
a first interlayer insulation film arranged between the channel stopper electrode and the first electrode in the termination region of the substrate;
first conductors arranged inside the first interlayer insulation film;
second conductors arranged on the first interlayer insulation film; and
a second electrode arranged on a second surface side of the substrate, wherein
a width of an overlapping portion, in a height direction by which one of the first conductors is overlapped by one of the second conductors on the first electrode side is larger than a width of an overlapping portion, in the height direction by which one of the first conductors is overlapped by one of the second conductors on the channel stopper electrode side.

US Pat. No. 10,797,129

FIELD EFFECT TRANSISTOR STRUCTURE HAVING NOTCHED MESA

1. A Field Effect Transistor, comprising:a structure having a substrate with a Group III-V semiconductor mesa, the Group III-V semiconductor mesa having a notch projecting both horizontally into a side of the Group III-V semiconductor mesa and vertically into an upper surface of the Group III-V semiconductor mesa, the notch being disposed over portions of the substrate outside of the Group III-V semiconductor mesa; and
a source electrode in ohmic contact with the Group III-V semiconductor mesa;
a drain electrode in ohmic contact with the Group III-V semiconductor mesa;
a gate electrode having: a first portion disposed on the Group III-V semiconductor mesa for controlling a flow of carriers between the source electrode and the drain electrode through the Group III-V semiconductor mesa; and a second portion extending longitudinally from, and connected to, the first portion, the second portion comprising a gate pad being both: wider than the first portion; and disposed over the portions of the substrate outside of the Group III-V semiconductor mesa and under the notch; and
wherein the gate pad has a first portion disposed within the notch and a second portion, wider than the first portion, disposed outside the notch.

US Pat. No. 10,797,128

DISPLAY PANEL AND DEVICE

WUHAN CHINA STAR OPTOELEC...

1. A display panel for an organic light emitting diode (OLED) display device, comprising a plurality of parallel scan lines at intervals and a plurality of parallel data lines at intervals, wherein the data lines and the scan lines cross each other and are insulated from each other; a nth scan line, a (n+1)th scan line, a mth data line, and a (m+1)th data line jointly define a first pixel area; the nth scan line, the (n+1)th scan line, a (m+2)th data line, and a (m+3)th data line jointly define a second pixel area; the nth scan line, the (n+1)th scan line, a (m+4)th data line, and a (m+5)th data line jointly define a third pixel area; each of the first, second, and third pixel areas has at least a sub-pixel unit; the one or more sub-pixel units in the first pixel area and the one or more sub-pixel units in the third pixel area are disposed in a structurally symmetric manner relative to the second pixel area; n is a positive integer greater than or equal to 1; and m is a positive integer greater than or equal to 1; wherein each sub-pixel unit comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel; the first, second, and third sub-pixels are different; the first pixel area and the second pixel area jointly form a first area which has a first sub-pixel, a second sub-pixel, and a third sub-pixel; or the second pixel area and the third pixel area jointly form a second area which has a first sub-pixel, a second sub-pixel, and a third sub-pixel; wherein each first sub-pixel is a red sub-pixel; each second sub-pixel is a green sub-pixel; each third sub-pixel is a blue sub-pixel; and a first sub-pixel, two second sub-pixels, and a third sub-pixel jointly form a pixel group; wherein the second sub-pixel electrically connect to the (m+2)th data line is disposed in the second pixel area; and the second sub-pixel electrically connect to the (m+4)th data line is disposed in the second pixel area.

US Pat. No. 10,797,127

ELECTROLUMINESCENT DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An electroluminescent display device, comprising:a substrate on which a display area and a non-display area are defined;
a thin film transistor in the display area on the substrate;
a light-emitting diode connected to the thin film transistor and including a first electrode, a light-emitting layer, and a second electrode;
a first link line disposed in the non-display area and configured to apply a first voltage to the first electrode;
a second link line spaced apart from the first link line in the non-display area; and
a conductive pattern disposed in the non-display area and connected to the second electrode to apply a second voltage, the conductive pattern having an opening corresponding to the first and second link lines,
wherein the conductive pattern is formed of a same material and on a same layer as the first electrode.

US Pat. No. 10,797,126

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL

WUHAN CHINA STAR OPTOELEC...

1. A display panel comprising:a substrate defining a through hole;
a driving wiring carried on the substrate;
a solder pad being arranged on a back surface of the substrate;
an active area; and
a non-active area around the active area;
wherein a first end of the driving wiring is located on a front surface of the substrate, and a second end of the driving wiring is connected to the solder pad via the through hole;
wherein the through hole is located in the non-active area;
wherein the substrate is a bendable flexible substrate;
a strain sensor, wherein the strain sensor is arranged on the back surface of the substrate and in the active area, and is configured to detect a stress deformation parameter of the driving wiring.

US Pat. No. 10,797,125

ELECTRONIC DEVICE HAVING DISPLAY CIRCUITRY WITH ROUNDED CORNERS

Apple Inc., Cupertino, C...

1. A display, comprising;pixels configured to form an active area with rounded corners that displays images;
display driver circuitry; and
demultiplexer circuitry between the display driver circuitry and the pixels, wherein the display driver circuitry conveys signals to the demultiplexer circuitry to display the images and wherein the demultiplexer circuitry has a first portion with first demultiplexers that extend along a first dimension and a second portion with second demultiplexers that extend in a staircase pattern along a second dimension that is oriented at a non-zero angle with respect to the first dimension.

US Pat. No. 10,797,124

ORGANIC LIGHT EMITTING DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. An organic light emitting display substrate, comprising:a base substrate;
a driving transistor, disposed on the base substrate, wherein the driving transistor comprises:
an active layer;
a first insulating layer having at least one sub-layer covering the active layer and having a first via hole therein;
a source electrode and a drain electrode disposed on a side of the first insulating layer distal to the base substrate, and connected to the active layer through the first via hole in the first insulating layer, wherein the drain electrode comprises a first region and a second region, the source electrode and the first region of the drain electrode comprises a metal layer and a transparent conductive layer stacked together and having patterns substantially the same with each other, the transparent conductive layer being on a side of the metal layer proximal to the base substrate, the second region comprises the transparent conductive layer, and the transparent conductive layer in the second region serves as a first electrode;
wherein the second region of the drain electrode does not comprise the metal layer;
wherein the active layer comprises: a non-conductor region and conductor regions, the non-conductor region corresponding to a gate electrode of the driving transistor, and the conductor regions are respectively connected to the source electrode and the drain electrode, and
the organic light emitting display substrate further comprises: a light blocking layer disposed between the active layer and the base substrate, wherein the light blocking layer is provided opposite to the active layer to form a capacitor:
wherein the light blocking layer is electrically connected to the drain electrode;
wherein the organic light emitting display substrate further comprises a buffer layer disposed between the light blocking layer and the active layer, the light blocking layer is connected to the drain electrode through a second via hole penetrating through the first insulating layer and the buffer layer; and
wherein the transparent conductive layer and the metal layer stacked together are provided on a bottom and side surfaces of the second via hole.

US Pat. No. 10,797,123

DISPLAY PANEL AND METHOD OF FABRICATING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display panel, comprising:a base layer including a first region and a second region that is bent with respect to the first region;
at least one inorganic layer overlapping both the first region and the second region and disposed on the base layer;
a lower opening formed within the at least one inorganic layer and overlapping the second region;
a first thin-film transistor disposed on the at least one inorganic layer and including a silicon semiconductor pattern overlapping the first region;
a second thin-film transistor disposed on the at least one inorganic layer and including an oxide semiconductor pattern overlapping the first region, wherein the oxide semiconductor pattern is disposed on a layer different from the silicon semiconductor pattern;
a plurality of insulating layers overlapping both the first region and the second region;
an upper opening formed within the plurality of insulating layers and extended from the lower opening;
a signal line electrically connected to the second thin-film transistor;
an organic layer overlapping both the first region and the second region and disposed in both the lower opening and the upper opening; and
a luminescent device disposed on the organic layer and overlapping the first region.

US Pat. No. 10,797,122

OLED DISPLAY AND METHOD FOR MANUFACTURING SAME

Wuhan China Star Optoelec...

1. An organic light emitting diode (OLED) display, comprising:a substrate;
a thin film transistor (TFT) device disposed on the substrate, wherein a gate electrode, a source electrode, and a drain electrode of the TFT device are isolated from each other by an inorganic insulation layer;
a planarization layer disposed on the TFT device and the inorganic insulation layer;
a pixel defining layer disposed on the planarization layer, wherein the pixel defining layer defines a plurality of pixels in the OLED display, and each pixel includes a plurality of sub-pixels;
an OLED device disposed on the planarization layer and the pixel defining layer; and
an encapsulation layer disposed on the OLED device;
wherein one or more inorganic material included in the inorganic insulation layer, the planarization layer, and the encapsulation layer and a cathode electrode of the OLED device surround each sub-pixel, each pixel, or more than one pixel of the OLED display; and
wherein the pixel defining layer is made of an inorganic material, and the pixel defining layer includes a first plug that is connected to the inorganic insulation layer via a through-hole in the planarization layer.

US Pat. No. 10,797,121

DISPLAY APPARATUS WITH A REDUCED PERIPHERAL AREA

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising a display area in which a plurality of pixels are disposed to display an image and a peripheral area which is a non-display area, the display apparatus comprising:a first power line disposed in the peripheral area and configured to provide a first voltage to the plurality of pixels; and
a second power line disposed in the peripheral area and configured to provide a second voltage different from the first voltage to the plurality of pixels, and
wherein at least a portion of the first power line overlaps the second power line in the peripheral area,
the second power line comprises a second_first portion and a second_second portion,
the second_first portion and the second_second portion of the second power line are formed from different layers,
an insulation layer is disposed between the second_first portion and the second_second portion of the second power line, and
the second_first portion and the second_second portion contact each other through a contact hole formed through the insulation layer.

US Pat. No. 10,797,120

ARRAY SUBSTRATE, FABRICATION METHOD THEREOF, AND DISPLAY DEVICE

Wuhan China Star Optoelec...

1. An array substrate, comprising:a substrate having a display region and a package region surrounding the display region, wherein the display region comprises a side region adjacent to the package region;
a pixel definition layer disposed on the display region of the substrate, wherein the pixel definition layer is formed with a plurality of recesses and a plurality of protrusions surrounding each recess, and each recess and each protrusion correspond to the side region; and
a cathode trace disposed on a surface of each protrusion and a bottom surface of each recess, wherein a gap exists between the cathode trace on each protrusion and the cathode trace in each recess, and there is no light-emitting layer in any of the recesses.

US Pat. No. 10,797,119

ELECTROLUMINESCENT DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An electroluminescent display device comprising:a substrate;
a first electrode of a first subpixel provided on the substrate;
a bank including a first bank configured to cover an end of the first electrode and a second bank formed on the first bank and configured to define a first emission area of the first subpixel;
a first emission layer of the first subpixel, the first emission layer provided in the first emission area defined by the second bank;
a second electrode of the first subpixel, the second electrode including a first transparent conductive material and provided on the first emission layer, the second electrode of the first subpixel being isolated within the first emission area of the first subpixel; and
a connection layer provided on the second bank, the connection layer connecting the second electrode of the first subpixel with another second electrode of another subpixel neighboring the first subpixel, the connection layer being non-integral with the second electrode and including a second transparent conductive material that is different from the first transparent conductive material or an opaque conductive material,
wherein a profile of an upper surface of the second electrode has a first curvature in a center of the second electrode and a second curvature at an edge of the second electrode, and wherein the second curvature is greater than the first curvature.

US Pat. No. 10,797,118

TOUCH PANEL, METHOD FOR FABRICATING THE SAME AND DISPLAY DEVICE

BOE Technology Group Co.,...

11. A method for fabricating a touch panel, comprising:forming a plurality of spacers and a plurality of touch electrode lines on a base substrate, wherein each of the spacers comprises a first photo spacer and a second photo spacer stacked successively on the base substrate; and each of the touch electrode lines comprises a first lead part and a second lead part, the first lead part at least covers a surface of the first photo spacer, adjacent to a cathode to be connected therewith, facing the cathode, and the second lead part is configured to electrically connect the first lead part with a corresponding pin on a touch integrated circuit; and
forming a cathode layer on the base substrate formed with the spacers and the touch electrode lines, wherein the cathode layer is segmented by the spacers into a plurality of cathodes arranged in a matrix, and each of the cathodes corresponds to at least one of the touch electrode lines, and is electrically connected with the first lead part of the corresponding touch electrode line;
wherein the first lead part fully covers the surface of the first photo spacer, and the different first lead parts cover the different first photo spacers.

US Pat. No. 10,797,117

ORGANIC LIGHT EMITTING DIODE DISPLAY MODULE AND CONTROL METHOD THEREOF

Beijing Xiaomi Mobile Sof...

1. An organic light emitting diode display module, the display module comprising:an organic light emitting diode display panel, wherein the organic light emitting diode display panel is configured to emit light rays towards a finger placed adjacent to the organic light emitting diode display panel during a fingerprint recognition operation; and
a fingerprint recognition region defined within the organic light emitting diode display panel, wherein the fingerprint recognition region includes infrared pixels and/or infrared subpixels,
a fingerprint sensor positioned within the fingerprint recognition region and arranged on a side of the organic light emitting diode display panel away from a light emerging side,
wherein the fingerprint sensor is configured to receive light rays reflected by the finger,
wherein the fingerprint sensor generates a fingerprint pattern of the finger according to the light rays reflected by the finger, and
wherein the infrared pixels and/or infrared subpixels are controlled to emit infrared light rays towards the finger during the fingerprint recognition operation, and the fingerprint sensor is configured to receive the infrared light rays that are reflected by the finger and are penetrating though the organic light emitting diode display panel, and to determine the fingerprint pattern of the finger using the reflected infrared light rays, and
wherein the organic light emitting diode display panel is electrically connected to the fingerprint sensor through a wire arranged between the organic light emitting diode display panel and the fingerprint sensor and configured to, when emitting the light rays to the finger in response to that a pressure sensor in the organic light emitting diode display panel senses that the fingerprint recognition operation is required, transmit, through the wire, a signal for triggering reception of the light rays reflected by the finger to the fingerprint sensor.

US Pat. No. 10,797,116

COMPLEX FILM AND ORGANIC LIGHT EMITTING DISPLAY DEVICE COMPRISING THE SAME

LG Display Co., Ltd., Se...

1. A complex film comprising:an adhesive layer having a first area and a second area;
an optical film provided on the first area of the adhesive layer, wherein the optical film includes a wave plate provided on the first area of the adhesive layer, a linear polarizing layer provided on the wave plate and a low-reflection layer provided on the linear polarizing layer;
an optical conversion film provided on the second area of the adhesive layer; and
a protective film covering the optical film and the optical conversion film.

US Pat. No. 10,797,115

DISPLAY PANEL AND DISPLAY APPARATUS USING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A display panel comprising:a light emitting device;
three quantum dot converters which include quantum dot particles, and are configured to convert light of a first color emitted from the light emitting device to light of different colors, respectively, and to emit the light of different colors, respectively;
a transmission part configured to transmit the light of the first color emitted from the light emitting device; and
a transparent substrate configured to transmit the light emitted from the three quantum dot converters and the transmission part,
wherein one of the three quantum dot converters is further configured to emit a white light, among the light of different colors, to the transparent substrate,
wherein the light emitting device comprises:
a light emitting layer,
a plurality of anodes which are separated from each other by a gap, respectively, and disposed on one side of the light emitting layer,
a cathode disposed on other side of the light emitting layer and adapted to reflect light emitted from the light emitting layer toward the plurality of anodes,
the three quantum dot converters are disposed to correspond to a first anode, a second anode, and a fourth anode, respectively, among the plurality of anodes, and
the transmission part is disposed to correspond to a third anode among the plurality of anodes.

US Pat. No. 10,797,114

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. An organic light-emitting display apparatus comprising:a first light-emitting unit comprising a first color light-emitting layer on an area of a substrate, the first color light-emitting layer to emit light of a first color;
a second light-emitting unit comprising a second color light-emitting layer on the substrate and spaced apart from the first color light-emitting layer, the second color light-emitting layer to emit light of a second color; and
a third light-emitting unit comprising a third color light-emitting layer arranged on the substrate as a common layer corresponding to both areas of the first color light-emitting layer and the second color light-emitting layer, the third color light-emitting layer to emit light of a third color different from the first and second colors,
wherein the first color light-emitting layer comprises a lower light-emitting layer and an upper light-emitting layer that are stacked to have a multilayered structure and are stacked with the third light-emitting unit arranged as the common layer.

US Pat. No. 10,797,113

LIGHT-EMITTING DEVICE WITH LAYERED ELECTRODE STRUCTURES

Semiconductor Energy Labo...

1. A light-emitting device comprising:a first light-emitting element comprising a first electrode, a second electrode, and an electroluminescence layer including a light-emitting layer;
a second light-emitting element comprising the first electrode, a third electrode, and the electroluminescence layer including the light-emitting layer; and
a third light-emitting element comprising the first electrode, a fourth electrode, and the electroluminescence layer including the light-emitting layer,
wherein the third electrode comprises a first conductive film and a second conductive film over the first conductive film,
wherein the fourth electrode comprises the first conductive film and a third conductive film over the first conductive film,
wherein the second conductive film is thicker than the third conductive film,
wherein the first electrode is configured to reflect light,
wherein the first conductive film is configured to reflect light and transmit light,
wherein the second electrode, the second conductive film, and the third conductive film are configured to transmit light, and
wherein the second electrode, the third electrode and the fourth electrode have different overall thicknesses.

US Pat. No. 10,797,112

ENERGY EFFICIENT OLED TV

Universal Display Corpora...

1. A full-color pixel arrangement for a device, the full-color pixel arrangement comprising:a plurality of sub-pixels, each having an emissive region of a first color,
wherein the full-color pixel arrangement comprises emissive regions having exactly one emissive color that is a red-shifted color of a deep blue sub-pixel of the plurality of sub-pixels.

US Pat. No. 10,797,111

MATRIX DETECTION DEVICE INCORPORATING A METAL MESH IN A DETECTION LAYER, AND MANUFACTURING METHOD

1. A matrix-array detecting device including a stack comprising a matrix array of detecting-element pixels, and an active matrix array comprising a network of rows and columns for controlling the pixels and produced on the surface of a substrate, wherein:the detecting-element pixels comprise:
a common top electrode;
a detecting layer; and
discrete bottom electrodes;
said device comprising a metallic mesh:
that is connected to said top electrode;
that includes pads comprising at least one metal portion, said pads being incorporated into said detecting layer; and
that is positioned in correspondence with said network of controlling rows and columns,
wherein at least one of said pads comprises a metal top portion and a bottom portion comprising a dielectric,
wherein the metal top portion is in contact with the common top electrode.

US Pat. No. 10,797,110

ORGANIC PHOTODIODE PIXEL FOR IMAGE DETECTORS

GENERAL ELECTRIC COMPANY,...

1. An imaging system comprising:a radiation source;
a detector panel configured to receive an emission produced by the radiation source and transmitted through a subject disposed between the radiation source and the detector panel, wherein the detector panel comprises:
a thin film transistor (TFT) backplane on a substrate; and
a photodiode layer comprising:
an anode layer comprising a plurality of anodes, wherein each anode couples electrically to a corresponding pixel of the TFT backplane through a pixel coupling, and wherein the anode layer comprises a plurality of boundaries between the anodes that separates adjacent pixels;
an organic photoactive layer comprising an organic photodiode material and disposed above the anode layer;
a plurality of dielectric structures disposed above the anode layer and below the organic photoactive layer, wherein the plurality of dielectric structures comprise dielectric structures disposed along the boundaries that separate the pixels, wherein an entirety of the dielectric structures are disposed along the boundaries without covering any portion of the plurality of anodes; and
a cathode layer disposed above the organic photoactive layer and the plurality of dielectric structures, wherein the anode layer is disposed closer to the TFT backplane than the cathode layer; and
a scintillator layer disposed above the detector panel.

US Pat. No. 10,797,109

MICRO-STRUCTURED ORGANIC SENSOR DEVICE AND METHOD FOR MANUFACTURING SAME

1. A micro-structured organic sensor device comprising the following layers oriented in parallel to one another:a substrate layer for supporting the further layers;
an organic sensor layer for converting a technical quantity to be detected to an electrical quantity;
a first electrode layer for contacting the organic sensor layer on a side of the organic sensor layer facing the substrate layer;
a second electrode layer for contacting the organic sensor layer on a side of the organic sensor layer facing away from the substrate layer; and
one or several functional layers;
wherein the sensor layer is structured such that a plurality of horizontally spaced sensor segments are formed;
wherein at least one of the electrode layers is structured such that a plurality of horizontally spaced electrode segments are formed so that at least one of the electrode segments of the respective electrode layer is associated to each of the sensor segments; and
wherein the one or several functional layers at least partly fill gaps located horizontally between the sensor segments; and
wherein one or several light-emitting diodes is/are formed on the substrate layer.

US Pat. No. 10,797,108

PRINTED RECONFIGURABLE ELECTRONIC CIRCUIT

Her Majesty the Queen in ...

1. An electronic component comprising:a non-conducting substrate having printed thereon, in predetermined patterns, one or more layers of material wherein some of the material is ferroelectric or semi-conductive material and some of the material is at least one of conductive, dielectric, and resistive; and, printed resistive biasing circuitry having a resistance of at least 100 ohms per square millimetre, supported by the substrate, electrically coupled to one or more of the printed layers, wherein when a changing voltage is applied to the resistive biasing circuitry, an electronic property of the electronic component changes in response to the changing voltage.

US Pat. No. 10,797,107

SEMICONDUCTOR MEMORY DEVICE INCLUDING PHASE CHANGE MATERIAL LAYERS AND METHOD FOR MANUFACTURING THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor memory device disposed over a substrate, comprising:a common electrode;
a selector material layer surrounding the common electrode; and
a plurality of phase change material layers in contact with the selector material layer, respectively,
wherein the selector material layer is disposed between the common electrode and the plurality of phase change material layers, and
the selector material layer includes one or more selected from the group consisting of AsGeSe doped with one or more selected from the group consisting of N, P, S, Si and Te; and AsGeSeSi doped with one or more selected from the group consisting of N, P, S, Si and Te.

US Pat. No. 10,797,106

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

Hefei Reliance Memory Lim...

1. A re-writeable non-volatile memory device, comprising:a first terminal;
a second terminal;
a layer of a conductive metal oxide (CMO); and
a layer of reactive metal in direct contact with the layer of CMO;
wherein the layer of CMO and the layer of reactive metal are electrically in series with each other and with the first and second terminals.

US Pat. No. 10,797,105

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

NEC CORPORATION, Tokyo (...

1. A semiconductor device comprisinga first switching element and a second switching element that are disposed in a signal path of a logic circuit, wherein
the first switching element includes two rectifying elements and two first variable resistance elements,
the second switching element does not include any rectifying elements and includes two second variable resistance elements, and
the first switching element and the second switching element are formed in the same wiring layer.

US Pat. No. 10,797,104

DISPLAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY DEVICE HAVING ELECTROSTRICTION LAYER

BEIJING BOE DISPLAY TECHN...

1. A display substrate, comprising: a plurality of pixel units arranged in an array, wherein at least one of the pixel units comprises:a first electrode, comprising a first electrode body, a first electrostriction layer connected to the first electrode body and a first driving electrode electrically connected to the first electrostriction layer,
wherein the first electrostriction layer is configured to expand or shrink according to an electric signal of the first driving electrode and drive the first electrode body to expand or shrink,
wherein the first driving electrode comprises at least one first sub driving electrode pair, two first sub driving electrodes of each first sub driving electrode pair are respectively on two opposite ends of the first electrostriction layer in a first direction, and the first electrostriction layer is configured to expand or shrink in the first direction according to the electric signal of the first driving electrode.

US Pat. No. 10,797,103

METHOD FOR PRODUCING A BOLOMETRIC DETECTOR

1. A method for producing a bolometric detector comprising at least:producing a stack of layers on an electrical interconnect level of an electronic read-out circuit of the detector, the stack comprising at least one sacrificial layer positioned between a carrier layer and a first etch stop layer, the first etch stop layer being positioned between the sacrificial layer and said electrical interconnect level, and the sacrificial layer comprising at least one mineral material capable of being selectively etched relative to the carrier layer and the first etch stop layer;
forming an opening in the stack of layers including etching through the carrier layer to expose an electrically conducting portion of the electrical interconnect level of said electrical interconnect level connected to the electronic read-out circuit;
producing at least one electrically conducting via in the opening passing through at least the stack of layers such that at least one electrically conducting material of the via is in contact with at least one electrically conducting portion of said electrical interconnect level connected to the electronic read-out circuit;
depositing at least one electrically conducting layer onto the carrier layer and the via;
etching the electrically conducting layer and the carrier layer, forming a bolometer membrane electrically connected to the via by at least one remaining portion of the electrically conducting layer that covers at least one upper part of the via; and
eliminating the sacrificial layer by chemical etching to which the first etch stop layer and the carrier layer are resistant, and such that the membrane is suspended by means of the via.

US Pat. No. 10,797,102

CHIP-SCALE LINEAR LIGHT-EMITTING DEVICE

Maven Optronics Co., Ltd....

1. A linear light-emitting device comprising:a submount substrate comprising a substrate-top surface, wherein a first horizontal direction and a second horizontal direction perpendicular to each other are defined on the substrate-top surface;
a plurality of LED semiconductor chips disposed on the substrate-top surface of the submount substrate along the first horizontal direction, wherein each of the LED semiconductor chips includes a chip-upper surface, a chip-lower surface opposite to the chip-upper surface, a first chip-edge surface, a second chip-edge surface, and a set of electrodes, wherein the first chip-edge surface and the second chip-edge surface are disposed in parallel and spaced apart along the second horizontal direction and are connected to each of the chip-upper surface and the chip-lower surface, and the set of electrodes is disposed on the chip-lower surface;
a chip-scale packaging structure disposed on the substrate-top surface of the submount substrate and covering the second chip-edge surfaces of the LED semiconductor chips, wherein the chip-scale packaging structure includes a photoluminescent element covering the second chip-edge surfaces of the LED semiconductor chips, and comprises a package-top surface and a continuous main light-emitting side surface, wherein the continuous main light-emitting side surface and the second chip-edge surfaces of the LED semiconductor chips are disposed in parallel and are spaced apart from each other along the second horizontal direction and are perpendicular to the set of electrodes, and wherein the photoluminescent element is configured to cause light from the LED semiconductor chips to be emitted with a linearly and uniformly distributed light radiation pattern across the continuous main light-emitting side surface;
a reflective structure disposed on the substrate-top surface of the submount substrate, and covering the first chip-edge surfaces of the LED semiconductor chips, the chip-upper surfaces of the LED semiconductor chips, and the package-top surface of the chip-scale packaging structure, but exposing the continuous main light-emitting side surface of the chip-scale packaging structure and the second chip-edge surfaces of the LED semiconductor chips.

US Pat. No. 10,797,101

TIME DELAY INTEGRATION IMAGE SENSORS WITH NON-DESTRUCTIVE READOUT CAPABILITIES

SEMICONDUCTOR COMPONENTS ...

1. An image sensor comprising:a semiconductor substrate having first and second opposing surfaces;
a plurality of floating gates formed adjacent to the first surface of the semiconductor substrate;
a plurality of readout circuits, wherein each floating gate of the plurality of floating gates is coupled to a respective readout circuit of the plurality of readout circuits; and
a plurality of additional gates formed adjacent to the first surface of the semiconductor substrate, wherein a respective subset of the plurality of additional gates is interposed between each adjacent pair of floating gates.

US Pat. No. 10,797,100

IMAGING DEVICE

Kabushiki Kaisha Toshiba,...

1. An imaging device, comprising:a semiconductor substrate;
a plurality of pixels provided in the semiconductor substrate and arranged in a first direction along a front surface of the semiconductor substrate;
a charge detector provided in the semiconductor substrate, the charge detector being provided at a position separated from a column of the plurality of pixels in a second direction orthogonal to the first direction;
a plurality of charge storage portions provided on the charge detector side of the column of the plurality of pixels, the plurality of charge storage portions being linked respectively to the plurality of pixels via charge transfer portions;
an output gate portion positioned between the charge detector and the plurality of charge storage portions, the output gate portion including a plurality of charge transfer channels extending in a radial configuration in directions from the charge detector toward the column of the plurality of pixels; and
a shift gate portion positioned between one of the plurality of charge storage portions and a charge transfer channel of the plurality of charge transfer channels, the charge transfer channel extending in a third direction crossing the first direction and the second direction,
the shift gate portion including a gate electrode provided on the semiconductor substrate, a planar configuration of the gate electrode having a side orthogonal to the third direction, the side being most proximal to the charge transfer channel extending in the third direction.

US Pat. No. 10,797,099

IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A method of manufacturing an image sensor, the method comprising:forming a plurality of trenches in a first surface of a first substrate,
the forming the plurality of trenches including forming the plurality of trenches in a device region and a first residual scribe lane region, respectively, of the first substrate,
the first substrate including a plurality of unit pixels in the device region,
the first substrate including a second surface opposite the first surface,
the first residual scribe lane region surrounding the device region;
filling the plurality of trenches to simultaneously form insulating structures in the device region and the first residual scribe lane region;
forming a first structure on the first surface of the first substrate, the first structure including a first conductive film and a first insulating film;
grinding the second surface of the first substrate to expose the insulating structures;
forming a second structure on a front surface of a second substrate,
the second structure including a second conductive film and a second insulating film,
the second substrate including a second residual scribe lane region facing the first residual scribe lane region of the first substrate,
the second substrate having a rear surface opposite the front surface; and bonding the first structure and the second structure.

US Pat. No. 10,797,098

IMAGE SENSOR BASED ON AVALANCHE PHOTODIODES

SHENZHEN XPECTVISION TECH...

1. An apparatus comprising:an array of avalanche photodiodes (APDs), each of the APDs comprising an absorption region and an amplification region;
wherein the absorption region is configured to generate charge carriers from a photon absorbed by the absorption region;
wherein the amplification region comprises a junction with an electric field in the junction;
wherein the electric field is at a value sufficient to cause an avalanche of charge carriers entering the amplification region, but not sufficient to make the avalanche self-sustaining;
wherein the junctions of the APDs are discrete.

US Pat. No. 10,797,097

SOLID-STATE IMAGE-CAPTURING ELEMENT AND ELECTRONIC DEVICE

SONY SEMICONDUCTOR SOLUTI...

1. A light detecting device, comprising:a floating diffusion;
a floating diffusion wiring connected to the floating diffusion;
a first region of an insulating layer; and
a first hollow region,
wherein the floating diffusion wiring, the first region of the insulating layer, and the first hollow region are in this order in a specific direction.

US Pat. No. 10,797,096

SEMICONDUCTOR IMAGE SENSOR

TAIWAN SEMICONDUCTOR MANU...

1. A back side illumination (BSI) image sensor comprising:a substrate comprising a front side and a back side opposite to the front side;
a plurality of pixel sensors arranged in an array,
an isolation grid disposed in the substrate and separating the plurality of pixel sensors from each other;
a reflective grid disposed over the isolation grid on the back side of the substrate, and a depth of the reflective grid being less than a depth of the isolation grid; and
a low-n grid disposed over the back side of the substrate and overlapping the reflective grid from a plan view,
wherein a width of the low-n grid is greater than a width of the reflective grid.

US Pat. No. 10,797,095

IMAGE SENSORS AND METHODS OF FORMING THE SAME

Samsung Electronics Co., ...

1. An image sensor comprising:a substrate including a plurality of pixel regions that include a first pixel region and a second pixel region;
a plurality of photoelectric conversion parts including a first photoelectric conversion part disposed in the first pixel region and a second photoelectric conversion part disposed in the second pixel region; and
a device isolation pattern disposed between the first pixel region and the second pixel region in the substrate,
wherein a void is disposed in the device isolation pattern,
wherein a width of an upper portion of the device isolation pattern is less than a width of an intermediate portion of the device isolation pattern, and
wherein a width of a bottom portion of the device isolation pattern is less than the width of the intermediate portion of the device isolation pattern.

US Pat. No. 10,797,094

MECHANISMS FOR FORMING IMAGE SENSOR DEVICE

Taiwan Semiconductor Manu...

1. An image sensor device, comprising:a semiconductor substrate;
a light sensing region in the semiconductor substrate;
a dielectric layer over the semiconductor substrate;
a filter having a main portion and a protruding portion between the main portion and the semiconductor substrate, wherein the dielectric layer continuously surrounds the main portion of the filter, and the protruding portion of the filter extends past a bottommost surface of the dielectric layer; and
a shielding layer between the dielectric layer and the semiconductor substrate and surrounding the protruding portion of the filter.

US Pat. No. 10,797,093

IMAGING ELEMENT, MANUFACTURING METHOD OF IMAGING ELEMENT, METAL THIN FILM FILTER, AND ELECTRONIC DEVICE

Sony Semiconductor Soluti...

1. An imaging device, comprising:a filter layer configured to selectively filter incident light according to wavelengths of the light; and
a photoelectric conversion layer configured to receive light filtered by the filter layer and to produce an electric charge in response to the received light,
wherein the filter layer includes:
a first filter region corresponding to a first pixel of the imaging device, the first filter region having a first thickness and a plurality of through holes formed therein, wherein the first filter region transmits light incident on the first filter region with a first peak transmission wavelength; and
a second filter region corresponding to a second pixel of the imaging device, the second filter region having a second thickness greater than the first thickness and having a plurality of through holes formed therein, wherein the second filter region transmits light incident on the second filter region with a second peak transmission wavelength that is greater than the first peak transmission wavelength.

US Pat. No. 10,797,092

IMAGE SENSOR HAVING AN INTERCONNECTION LAYER CONNECTING TO STACKED TRANSPARENT ELECTRODES AND COVERING A BLACK PIXEL REGION

Samsung Electronics Co., ...

18. An image sensor comprising:a semiconductor substrate comprising an active pixel region in which a plurality of active pixels are disposed and a power delivery region in which a pad is disposed on the semiconductor substrate;
a first photolayer disposed over the semiconductor substrate and comprising a plurality of first lower transparent electrode layers respectively corresponding to the plurality of active pixels, a first upper transparent electrode layer integrally formed across the plurality of active pixels, and a first organic photoelectric layer disposed between the plurality of first lower transparent electrode layers and the first upper transparent electrode layer;
a second photolayer disposed over the first photolayer and comprising a plurality of second lower transparent electrode layers respectively corresponding to the plurality of active pixels, a second upper transparent electrode layer integrally formed across the plurality of active pixels, and a second organic photoelectric layer disposed between the plurality of second lower transparent electrode layers and the second upper transparent electrode layer;
a third photolayer disposed over the second photolayer and comprising a plurality of third lower transparent electrode layers respectively corresponding to the plurality of active pixels, a third upper transparent electrode layer integrally formed across the plurality of active pixels, and a third organic photoelectric layer disposed between the plurality of third lower transparent electrode layers and the third upper transparent electrode layer; and
an interconnection layer located at a level that is the same as or higher than an upper surface of the pad with respect to an upper main surface of the semiconductor substrate,
the interconnection layer extending from the pad, and comprising a connector electrically connecting the pad and the first upper transparent electrode layer, the second upper transparent electrode layer and the third upper transparent electrode layer,
wherein the pad is located at a level lower than the plurality of first transparent electrode layers,
wherein the semiconductor substrate further comprises a black pixel region that surrounds the active pixel region and in which a plurality of black pixels are disposed, the black pixel region is between the active pixel region and the power delivery region, and
wherein the interconnection layer further comprises a cover covering the black pixel region.

US Pat. No. 10,797,091

SEMICONDUCTOR IMAGING DEVICE HAVING IMPROVED DARK CURRENT PERFORMANCE

Taiwan Semiconductor Manu...

1. A pixel sensor, comprising:a first photodetector disposed in a semiconductor substrate;
a second photodetector disposed in the semiconductor substrate, wherein a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector;
a floating diffusion node disposed in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector;
a pick-up well contact region disposed in the semiconductor substrate, wherein a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region; and
a pixel device region disposed on a first side of the first substantially straight line axis, wherein the pixel device region comprises a source follower transistor, wherein the source follower transistor comprises a pair of source/drain regions, and wherein a third substantially straight line axis that is substantially parallel with the first substantially straight line axis intersect the pick-up well contact region and the source/drain regions.

US Pat. No. 10,797,090

IMAGE SENSOR WITH NEAR-INFRARED AND VISIBLE LIGHT PHASE DETECTION PIXELS

SEMICONDUCTOR COMPONENTS ...

1. An image sensor comprising a semiconductor substrate and a plurality of phase detection pixel groups, wherein each phase detection pixel group comprises:at least two photosensitive areas in the semiconductor substrate;
a microlens that covers the at least two photosensitive areas;
a color filter element that is interposed between the microlens and the at least two photosensitive areas;
light-scattering structures formed on a first side of the semiconductor substrate, wherein each of the at least two photosensitive areas is overlapped by a respective plurality of the light-scattering structures;
first isolation structures that are formed around a periphery of the phase detection pixel group; and
second isolation structures that are formed between each adjacent pair of photosensitive areas within the phase detection pixel group.

US Pat. No. 10,797,089

DISPLAY DEVICE HAVING COMPENSATING CAPACITOR AND METHOD OF MANUFACTURING THE SAME

KUNSHAN NEW FLAT PANEL DI...

1. A display device, comprising a plurality of pixel cells, wherein the display device comprises:a substrate; and
a patterned polysilicon layer, a patterned gate insulating layer and a patterned first conductive layer, stacked on the substrate in sequence, the patterned polysilicon layer comprising a plurality of polysilicon blocks which are arranged outside the pixel cells and doped with impurities, the patterned first conductive layer comprising a plurality of data lines, each of the plurality of data lines partially overlapping a corresponding polysilicon block of the plurality of polysilicon blocks to form a compensating capacitor to compensate for a parasitic capacitance of the data line which is related to a number of the pixel cells connected to the data line.

US Pat. No. 10,797,088

SEMICONDUCTOR DEVICE, DISPLAY APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING DISPLAY APPARATUS

TIANMA MICROELECTRONICS C...

1. A semiconductor device comprising:an insulating substrate;
a polysilicon layer formed on the insulating substrate;
a first-gate-insulating layer formed on the polysilicon layer;
a first metal layer formed on the first-gate-insulating layer;
an oxide-semiconductor layer formed on the first-gate-insulating layer;
a second-gate-insulating layer formed on the oxide-semiconductor layer;
a second metal layer formed on the second-gate-insulating layer;
a first insulating interlayer formed on the second metal layer;
a third metal layer formed on the first insulating interlayer;
a second insulating interlayer formed between the first-gate-insulating layer and the second-gate-insulating layer, the oxide-semiconductor layer being formed on the second insulating interlayer;
a first top gate planar-type thin film transistor in which the polysilicon layer serves as a channel and which has a source, a drain, and a gate; and
a second top gate planar self-aligned-type thin film transistor in which the oxide-semiconductor layer serves as a channel and which has a source, a drain, and a gate,
wherein the gate of the first top gate planar-type thin film transistor is made of the first metal layer,
the gate of the second top gate planar self-aligned-type thin film transistor is made of the second metal layer,
the source and the drain of the first top gate planar-type thin film transistor and the source and the drain of the second top gate planar self-aligned-type thin film transistor are made of the third metal layer,
the source or the drain of the first top gate planar-type thin film transistor and the gate of the second top gate planar self-aligned-type thin film transistor are electrically connected to each other,
a high-hydrogen-concentration region in which the hydrogen concentration becomes local maximum with respect to hydrogen diffused into the first-gate-insulating-layer is formed at an interface region of the first-gate-insulating layer and the second insulating interlayer,
the hydrogen concentration of the first-gate-insulating layer in a thickness direction of the first-gate-insulating layer gradually increases toward an interface of the first-gate-insulating layer and the second insulating interlayer, and
the hydrogen concentration of the second insulating interlayer in a thickness direction of the second insulating interlayer gradually increases toward the interface of the second insulating interlayer and the first-gate-insulating layer.

US Pat. No. 10,797,087

ARRAY SUBSTRATE MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

CHENGDU BOE OPTOELECTRONI...

1. An array substrate, comprising:a base substrate;
an insulating layer, a gate line, a source electrode, a drain electrode, and a data line on the base substrate,
wherein the insulating layer comprises a light transmission portion and a light shielding portion, and orthographic projections of the gate line, the source electrode, the drain electrode, and the data line on the base substrate are all within an orthographic projection of the light shielding portion on the base substrate,
the array substrate further comprising:
a common electrode, on the base substrate; and
a pixel electrode, on the base substrate same as the common electrode and between the common electrode and the gate insulation layer;
wherein part of the light-transmitting portion of the insulating layer is between the common electrode and the pixel electrode, and the part of the light-transmitting portion of the insulating layer is in direct contact with both the common electrode and the pixel electrode.

US Pat. No. 10,797,086

LIQUID CRYSTAL DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME

Mitsubishi Electric Corpo...

1. A liquid crystal display panel, comprisinga thin film transistor substrate in which a plurality of pixels are arranged in a matrix pattern, wherein
each of the plurality of pixels comprises:
a gate electrode selectively disposed on a substrate;
a gate insulating film covering the gate electrode;
a semiconductor film disposed on the gate insulating film so as to overlap the gate electrode;
a source electrode and a drain electrode provided on the semiconductor film so as to be separated apart from each other;
a planarizing insulating film covering the gate insulating film, the planarizing insulating film comprising an opening for partially exposing the source electrode and the drain electrode on a bottom of the opening;
a first transparent conductive film and a second transparent conductive film provided to extend from an uppermost surface of the planarizing insulating film toward a side surface of the opening and the bottom of the opening so as to respectively come in contact with a surface of the source electrode and a surface of the drain electrode that are exposed on the bottom of the opening;
an insulating film provided on the planarizing insulating film so as to cover the opening, the first transparent conductive film, and the second transparent conductive film;
a pixel electrode electrically connected to the drain electrode via the second transparent conductive film; and
a counter electrode provided to be opposed to the pixel electrode across the insulating film, and
the pixel electrode is provided on the insulating film and is electrically connected to the drain electrode through a contact hole, the contact hole being provided in the insulating film to penetrate the insulating film at a position corresponding to a position above the second transparent conductive film and above the uppermost surface of the planarizing insulating film outside the opening.

US Pat. No. 10,797,085

DISPLAY PANELS AND DISPLAY DEVICES

1. A display panel, comprising:a display area, and
a non-display area disposed around the display area;
wherein:
the display area comprises a first sub-display area and a second sub-display area, the first sub-display area comprising a plurality of pixel units arranged in an array and a first scanning wire connecting each row of the pixel units, the second sub-display area comprising a plurality of pixel units arranged in an array;
the non-display area is provided with a fixed potential signal wire, the fixed potential signal wire comprising a first signal wire and a second signal wire, the second signal wire being coupled to the first signal wire, the second signal wire comprising a connecting portion and strip portions coupled to the connecting portion and arranged at intervals, a width of the second signal wire being greater than a width of the first signal wire; and
the display panel further comprises a leading-out wire, the leading-out wire being correspondingly connected to the first scanning wire and extends to the non-display area to overlap with the second signal wire, the second signal wire and the leading-out wire being provided at different layers, wherein the second signal wire overlaps with the leading-out wire to generate a parasitic capacitance to compensate for a load of the first scanning wire.

US Pat. No. 10,797,084

DISPLAY APPARATUS

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate comprising a display area and a peripheral area located outside the display area, wherein a first part of an edge of the display area has a curved shape and the peripheral area includes a pad area;
a first wiring comprising a first one end located in the pad area and a first other end located in the peripheral area;
a first additional wiring comprising a first additional one end electrically connected to the first other end of the first wiring and a first additional other end located in the peripheral area; and
a first bridge wiring comprising a first end electrically connected to the first other end of the first wiring and a second end electrically connected to the first additional one end of the first additional wiring.

US Pat. No. 10,797,083

ARRAY SUBSTRATE WITH CONTACT HOLE HAVING HOLE WALLS FORMING AN OBTUSE ANGLE

SHENZHEN CHINA STAR OPTOE...

1. An array substrate, comprising:a base substrate;
a metal layer formed on the base substrate;
a passivation layer formed on the base substrate and the metal layer;
a planarization layer formed on the passivation layer;
a contact hole formed by two-step etching the planarization layer and the passivation layer on the metal layer, to make the metal layer at least partially exposed by the contact hole, wherein a hole wall of the contact hole at the passivation layer and a hole wall at the planarization layer form an obtuse angle greater than 90 degrees and less than 180 degrees, the hole wall of the contact hole at the passivation layer is inclined starting from a contact interface between the planarization layer and the passivation layer until another contact interface between the passivation layer and the metal layer; and
a continuous pixel electrode layer formed on the planarization layer and the contact hole, wherein the pixel electrode layer is connected to the metal layer, and portions of the continuous pixel electrode layer on the hole wall of the contact hole at the planarization layer and the hole wall of the contact hole at the passivation layer respectively as a whole is bended in shape.

US Pat. No. 10,797,082

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF PRODUCING THE SAME

SHARP KABUSHIKI KAISHA, ...

1. A thin film transistor array substrate including thin film transistors, the thin film transistor array substrate comprising:gate electrodes of the thin film transistors, the gate electrodes being made from a first metal film;
a first insulating film on the first metal film;
channels of the thin film transistors, the channels being made from a semiconductor film on the first insulating film and overlapping the gate electrodes;
source electrodes of the thin film transistors, the source electrodes being made from a second metal film on the semiconductor film and connected to first ends of the channels;
drain electrodes of the thin film transistors, the drain electrodes being made from the second metal film and connected to second ends of the channels;
pixel electrodes including portions of the semiconductor film having reduced resistances and being connected to the drain electrodes;
a second insulating film on the semiconductor film and the second metal film and including first sections overlapping the pixel electrodes without openings and second sections filling gaps between the source electrodes and the drain electrodes of adjacent thin film transistors, the second sections including bottom surfaces directly contacting top surfaces of the channels; and
a common electrode constructed from a transparent electrode film on the second insulating film and overlapping at least the pixel electrodes.

US Pat. No. 10,797,080

THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A pixel thin film transistor, comprising an active layer, a source electrode and a drain electrode, wherein,the active layer comprises a source electrode contact region, a drain electrode contact region, and a semiconductor channel region arranged between the source electrode contact region and the drain electrode contact region, and
a conductive layer is provided on the semiconductor channel region and is spaced apart from the source electrode and the drain electrode,
wherein the semiconductor channel region is U-shaped when viewed in a plane view of the pixel thin film transistor, and the source electrode comprises a U-shaped part corresponding to the U-shaped semiconductor channel region,
wherein the conductive layer comprises at least one conductive part, and the at least one conductive part is arranged between one end of the drain electrode and the U-shaped part of the source electrode, and
wherein the active layer further comprises an ohmic contact layer, and the source electrode, the drain electrode and the conductive layer are in contact with the source electrode contact region, the drain electrode region and the semiconductor channel region through the ohmic contact layer, respectively.

US Pat. No. 10,797,079

LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...

1. A method of manufacturing a display device comprising:providing a substrate having a plurality of driving elements;
transplanting a light emitting chip on the substrate; and
connecting electrodes of the light emitting chip and the driving element,
wherein the transplanting the light emitting chip on the substrate includes:
aligning a transfer substrate having the light emitting chip and a first structure with the substrate using the first structure as an alignment key for disposition of the light emitting chip on the substrate,
wherein the first structure is spaced apart from the light emitting chip; and
transplanting the light emitting chip and the first structure from the transfer substrate onto the substrate.

US Pat. No. 10,797,078

HYBRID FIN FIELD-EFFECT TRANSISTOR CELL STRUCTURES AND RELATED METHODS

Taiwan Semiconductor Manu...

1. A integrated circuit cell, comprising:a first circuit component that includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a first plurality of fin structures arranged in a first row and a second plurality of fin structures arranged in a second row; and
a second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a third plurality of fin structures arranged in a third row and a fourth plurality of fin structures arranged in a fourth row, wherein each of the third row and the fourth row, in the less fin portion, contain a lesser number of fin structures than each of the first row and the second row, in the high fin portion.

US Pat. No. 10,797,077

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE INCLUDING SLIT WITH LATERAL SURFACES HAVING PERIODICITY

Toshiba Memory Corporatio...

1. A semiconductor device comprising:a stack including a plurality of conductive layers and a plurality of insulating layers alternately stacked in a first direction, the plurality of conductive layers including a first conductive layer as a selection gate electrode and a plurality of second conductive layers as word lines;
a slit dividing the first conductive layer into a first region and a second region in a second direction crossing the first direction and extending in a third direction crossing the first and the second directions, the slit not dividing the plurality of second conductive layers, the slit including an insulating material;
a plurality of first columns respectively extending in the first direction through the first region of the first conductive layer and respectively including a first charge accumulating layer;
a plurality of second columns respectively extending in the first direction through the second region of the first conductive layer and respectively including a second charge accumulating layer;
a plurality of first plug electrodes provided on the plurality of first columns; and
a plurality of second plug electrodes provided on the plurality of second columns,
wherein
the slit has a first surface that faces the first region of the first conductive layer and a second surface that faces the second region of the first conductive layer,
the first columns and the second columns are arranged at a pitch in the third direction, and
the first surface and the second surface have waveform shapes that are shifted from each other by a half of the pitch in the third direction.

US Pat. No. 10,797,076

METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES

YANGTZE MEMORY TECHNOLOGI...

1. A method for forming a three-dimensional (3D) memory device, comprising:forming a first channel structure and a second channel structure each extending vertically through a memory stack comprising interleaved conductor layers and dielectric layers above a first substrate;
forming a semiconductor connection above the memory stack and in contact with one end of the first channel structure and one end of the second channel structure;
joining the first substrate and a second substrate;
removing the first substrate to expose another end of the first channel structure and another end of the second channel structure; and
forming a first semiconductor plug at the another end of the first channel structure and a second semiconductor plug at the another end of the second channel structure.

US Pat. No. 10,797,075

STAIRCASE AND CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY

Yangtze Memory Technologi...

1. A three-dimensional memory device, comprising:a semiconductor substrate;
a plurality of through-substrate-trenches penetrating the semiconductor substrate;
a film stack disposed on a first surface of the semiconductor substrate extending through the through-substrate-trenches to a second surface of the semiconductor substrate, wherein
the film stack comprises alternating conductive and dielectric layers; and
the first and second surfaces are on opposite sides of the semiconductor substrate; and
a staircase structure formed at an edge of the film stack.

US Pat. No. 10,797,074

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES

Samsung Electronics Co., ...

1. A three-dimensional semiconductor memory device, comprising:a first stack structure on a substrate, the substrate including a cell array region and a connection region; and
a second stack structure on the first stack structure, the second stack structure having a bottom surface, wherein
the first stack structure has a first vertical channel hole from the substrate to the bottom surface of the second stack structure, the first vertical channel hole having a top diameter, a first inner side surface, and a buffer pattern on the first inner side surface and adjacent to the bottom surface of the second stack structure, the first stack structure being located on the cell array region, and the first inner side surface having an upper portion, and
the second stack structure has a second vertical channel hole on the first vertical channel hole, the second vertical channel hole having a second inner side surface, and a bottom diameter that is smaller than the top diameter of the first vertical channel hole.

US Pat. No. 10,797,073

MEMORY SYSTEM AND SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A memory system comprising:a semiconductor memory device; and
a controller configured to control the semiconductor memory device,
wherein the semiconductor memory device includes:
a plurality of first interconnection layers stacked in a first direction;
a plurality of second interconnection layers stacked in the first direction, the second interconnection layers respectively disposed apart from one of the first interconnection layers in a second direction intersecting the first direction;
a semiconductor pillar provided between the first interconnection layers and the second interconnection layers, and extending in the first direction;
a first charge storage layer disposed between the first interconnection layers and the semiconductor pillar; and
a second charge storage layer disposed between the second interconnection layers and the semiconductor pillar,
wherein the semiconductor memory device is configured to execute an operation in a first mode or in a second mode, in the first mode, the device selects a third interconnection layer among the first interconnection layers independently with a fourth interconnection layer among the second interconnection layers disposed apart in the second direction from the third interconnection layer, in the second mode, the device selects a fifth interconnection layer among the first interconnection layers, and sixth interconnection layer among the second interconnection layers disposed apart in the second direction from the fifth interconnection layer in a batch, and
the controller is configured to send an instruction to the device to execute the operation in the first mode or the second mode.

US Pat. No. 10,797,072

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device comprising:an N-well region including two P-type impurity diffusion regions;
a first gate electrode above the N-well region between the two P-type impurity diffusion regions, the first gate electrode being opposed to the N-well region via a gate insulating film;
a columnar epitaxial layer on at least one of the two P-type impurity diffusion regions, the epitaxial layer including a first semiconductor layer including P-type impurities; and
a first contact on the first semiconductor layer of the epitaxial layer, wherein
the first semiconductor layer further includes carbon, and
a carbon concentration in the first semiconductor layer is 1019 (atoms/cm3) or more.

US Pat. No. 10,797,071

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor memory device, comprising:a peripheral circuit structure including a peripheral circuit insulating layer;
a middle connection structure on the peripheral circuit insulating layer, the middle connection structure including a middle connection insulating layer, and a bottom surface of the middle connection insulating layer is in contact with a top surface of the peripheral circuit insulating layer;
stack structures on sides of the middle connection structure; and
channel structures extending vertically through each of the stack structures,
wherein at least one side surface of the middle connection insulating layer is an inclined surface, a lateral sectional area of the middle connection insulating layer decreasing in an upward direction oriented away from the peripheral circuit insulating layer.

US Pat. No. 10,797,070

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A REPLACEMENT BURIED SOURCE LINE AND METHODS OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:a substrate including a stack of a first conductivity type semiconductor layer having a doping of a first conductivity type and a second conductivity type semiconductor layer having a doping of a second conductivity type that is an opposite of the first conductivity type and providing a p-n junction at an interface with a bottom surface of the first conductivity type semiconductor layer;
a source-level semiconductor material layer contacting a top surface of the first conductivity type semiconductor layer and having a doping of the first conductivity type;
an alternating stack of insulating layers and electrically conductive layers overlying semiconductor pillar structures and the source-level semiconductor material layer; and
memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective memory film.

US Pat. No. 10,797,069

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising: a semiconductor substrate;a pillar disposed above the semiconductor substrate and extending in a first direction crossing a principal surface of the semiconductor substrate;
a plurality of first memory cells arranged on a first side surface of the pillar along the first direction;
a plurality of second memory cells arranged on a second side surface of the pillar along the first direction, each of the first memory cells and the second memory cells including a charge storage layer:
a plurality of first control gate layers disposed along the first direction and respectively connected to the first memory cells;
a plurality of second control gate layers disposed along the first direction and respectively connected to the second memory cells; and
a stacked film disposed between one of the first control gate layers and one of the second control gate layers, the stacked film including a first insulating layer, a second insulating layer, and an electron capture layer disposed between the first insulating layer and the second insulating layer, the electron capture layer configured to capture electrons,
wherein the electron capture layer is separate from the charge storage layer of each of the first memory cells and the second memory cells.

US Pat. No. 10,797,068

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A three-dimensional semiconductor memory device comprising:a substrate;
a conductive line on the substrate, the conductive line extending in a first direction;
a semiconductor pattern between the substrate and the conductive line, wherein the semiconductor pattern comprises an opening;
a first peripheral contact pad between the substrate and the semiconductor pattern;
a stacked structure on the semiconductor pattern, wherein the stacked structure comprises interlayer insulating layers and cell gate conductive patterns that are alternately stacked;
a memory cell vertical structure extending through the stacked structure; and
a first peripheral contact structure on the first peripheral contact pad, wherein the first peripheral contact structure extends through the opening of the semiconductor pattern,
wherein the opening has a rectangular shape extending in a second direction different from the first direction when viewed from a plan perspective.

US Pat. No. 10,797,067

THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATING METHOD THEREOF

Yangtze Memory Technologi...

1. A three-dimensional (3D) NAND memory device, comprising:a substrate including a plurality of monolithic protruding islands in a recess region of the substrate;
a gate dielectric layer completely covering sidewalls of the plurality of protruding islands and a top surface of the recess region of the substrate, wherein the gate dielectric layer is a continuous piece;
an underlying conductor layer contacting the gate dielectric layer in both a lateral direction and a vertical direction, and surrounding the sidewalls of the plurality of protruding islands in a lateral plane;
an alternating conductor/dielectric stack including a plurality of alternatively stacked insulating layers and conductor layers on the underlying conductor layer and the plurality of protruding islands;
a plurality of channel holes vertically penetrating the alternating conductor/dielectric stack, each channel hole is above one protruding island; and
a memory layer in each channel hole, wherein a channel layer of the memory layer is electrically connected with a corresponding protruding island.

US Pat. No. 10,797,066

MEMORY DEVICES WITH THREE-DIMENSIONAL STRUCTURE

Samsung Electronics Co., ...

1. A memory device, comprising:a substrate;
a first memory structure directly on the substrate such that the first memory structure is in contact with the substrate, the first memory structure including a plurality of first word lines stacked on the substrate in a direction perpendicular to a top surface of the substrate;
an inter-metal layer directly on the first memory structure such that the inter-metal layer is in contact with the first memory structure, the inter-metal layer including a plurality of intermediate pads, the plurality of intermediate pads connected with separate, respective first word lines of the plurality of first word lines;
a second memory structure directly on the inter-metal layer such that the second memory structure is in contact with the inter-metal layer and the inter-metal layer is directly between the first and second memory structures, the second memory structure including a plurality of second word lines stacked on the inter-metal layer in the direction perpendicular to the top surface of the substrate; and
an upper metal layer directly on the second memory structure such that the upper metal layer is in contact with the second memory structure and the second memory structure is directly between the upper metal layer and the inter-metal layer, the upper metal layer including a plurality of upper pads, the plurality of upper pads connected with separate, respective second word lines of the plurality of second word lines,
wherein,
the first memory structure further includes a first pillar penetrating the plurality of first word lines,
the second memory structure further includes a second pillar penetrating the plurality of second word lines,
the inter-metal layer further includes an intermediate connection pad configured to electrically couple the first pillar and the second pillar to each other, and
the upper metal layer further includes a bit line electrically coupled to the second pillar.

US Pat. No. 10,797,065

NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURE THEREOF

TOSHIBA MEMORY CORPORATIO...

1. A nonvolatile semiconductor storage device, comprising:a memory cell transistor, the memory cell transistor comprising:
a semiconductor substrate, the semiconductor substrate including a device region defined by an isolation region;
a tunnel insulating film formed above the semiconductor substrate;
a charge storage layer formed above the tunnel insulating film, the charge storage layer being a single layer including silicon, and the charge storage layer having a pattern aligned with the device region in a cross section of the memory cell transistor orthogonal to a gate length direction of the memory cell transistor;
an insulating film formed above the charge storage layer, the insulating film having a gate pattern extending in a gate width direction of the memory cell transistor and having a dielectric constant larger than a dielectric constant of the tunnel insulating film, the gate width direction being orthogonal to the gate length direction and parallel to the cross section;
a metal-containing layer formed above and in direct contact with the insulating film, the metal-containing layer having the gate pattern and including tantalum, the metal-containing layer being a conductive single layer; and
a gate electrode layer formed above the metal-containing layer and constituted of a material different from a material of the metal-containing layer, the gate electrode layer having a dimension in the gate length direction smaller than a dimension in the gate length direction of the metal-containing layer and smaller than a dimension in the gate length direction of an under surface of a portion including the silicon of the charge storage layer.

US Pat. No. 10,797,064

SINGLE-POLY NON-VOLATILE MEMORY CELL AND OPERATING METHOD THEREOF

EMEMORY TECHNOLOGY INC., ...

1. A non-volatile memory cell, comprising:a floating-gate transistor, deposited in a P-well and comprising a gate terminal, a drain terminal, and a source terminal, wherein the gate terminal is coupled to a floating gate, the drain terminal is coupled to a bit line, and the source terminal is coupled to a first node, wherein the floating gate is formed by a first polysilicon layer;
a select transistor, deposited in the P-well and comprising a gate terminal, a drain terminal, and a source terminal, wherein the gate terminal is coupled to a select gate, the drain terminal is coupled to the first node, and the source terminal is coupled to a source line, wherein the select gate is coupled to a word line, wherein the floating-gate transistor and the select transistor are N-type transistors; and
a coupling structure, formed by extending the first polysilicon layer to overlap a control gate, wherein the control gate is a P-type doped region in an N-well, wherein the control gate is coupled to a control line.

US Pat. No. 10,797,063

SINGLE-POLY NONVOLATILE MEMORY UNIT

eMemory Technology Inc., ...

1. A single-poly non-volatile memory (NVM) unit, comprising:a semiconductor substrate having a first conductivity type;
a first oxide define region (OD) region, a second OD region, and a third OD region disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first well, and the first well has a second conductivity type;
a first memory cell disposed on the first OD region;
a second memory cell disposed on the second OD region, wherein the first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis; and
an erase gate disposed in the third OD region.

US Pat. No. 10,797,062

BONDED DIE ASSEMBLY USING A FACE-TO-BACK OXIDE BONDING AND METHODS FOR MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A bonded assembly comprising:a first semiconductor die comprising a first substrate, first semiconductor devices overlying the first substrate, first dielectric material layers overlying the first semiconductor devices and having a first silicon oxide surface as an uppermost surface, and first metal interconnect structures formed within the first dielectric material layers;
a second semiconductor die overlying the first semiconductor die, and comprising a second substrate, second semiconductor devices overlying a front-side surface of the second substrate, second dielectric material layers overlying the second semiconductor devices, and second metal interconnect structures formed within the second dielectric material layers, wherein a second silicon oxide surface of the second semiconductor die is located underneath the second substrate and is bonded to the first silicon oxide surface of the first semiconductor die at an oxide-to-oxide bonding interface; and
inter-die connection via structures vertically extending through the second substrate and the oxide-to-oxide bonding interface, contacting a top surface of a respective first metal pad structure selected from the first metal interconnect structures, and contacting a bottom surface of a respective second metal pad structure selected from the second metal interconnect structures;
wherein:
each of the inter-die connection via structures comprises a metallic via liner and a metallic via fill material portion; and
a top surface of the metallic via fill material portion contacts a metallic pad liner of one of the second metal pad structures and is vertically spaced from an underlying one of the first metal pad structures by a horizontal portion of the metallic via liner.

US Pat. No. 10,797,061

THREE-DIMENSIONAL MEMORY DEVICE HAVING STRESSED VERTICAL SEMICONDUCTOR CHANNELS AND METHOD OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;
a memory stack structure vertically extending through the alternating stack, wherein the memory stack structure comprises a memory film that contains a vertical stack of memory elements located at levels of the electrically conductive layers, and a vertical semiconductor channel that contacts the memory film;
a source contact layer underlying the alternating stack and laterally surrounding, and contacting a sidewall of, the vertical semiconductor channel; and
a dielectric fill material layer underlying the source contact layer and including a dielectric fill material having a Young's modulus that is less than 70% of a Young's modulus of a material of the source contact layer.

US Pat. No. 10,797,060

THREE-DIMENSIONAL MEMORY DEVICE HAVING STRESSED VERTICAL SEMICONDUCTOR CHANNELS AND METHOD OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;
a memory stack structure vertically extending through the alternating stack, wherein the memory stack structure comprises a memory film that contains a vertical stack of memory elements located at levels of the electrically conductive layers, and a vertical semiconductor channel that contacts the memory film; and
a stressor pillar structure located on a side of the vertical semiconductor channel, wherein:
the stressor pillar structure applies a vertical tensile stress to the vertical semiconductor channel;
a lateral extent of the stressor pillar structure is defined by at least one substantially vertical dielectric sidewall surface that provides a closed periphery around the stressor pillar structure;
the stressor pillar structure consists essentially of a stressor material and does not include any solid or liquid material therein other than the stressor material; and
the stressor material is selected from a dielectric metal oxide material, silicon nitride deposited under stress, thermal silicon oxide, or a semiconductor material having a greater lattice constant than that of the vertical semiconductor channel.

US Pat. No. 10,797,059

METHOD OF DESIGNING A LAYOUT OF A STATIC RANDOM ACCESS MEMORY PATTERN

UNITED MICROELECTRONICS C...

10. A method of designing a layout of a static random access memory (SRAM) pattern, comprising:according to a target pattern, forming a plurality of first patterns and a first dummy pattern in a substrate, wherein a first pattern that disposed at the outermost boundary of the first patterns is defined as a first edge pattern;
removing the first dummy pattern completely;
according to the target pattern, forming a plurality of second patterns and a second dummy pattern in the substrate, wherein the second dummy pattern is disposed between the first edge pattern and an original position of the first dummy pattern; and
removing the second dummy pattern completely.

US Pat. No. 10,797,058

CONDUCTIVE FEATURE FORMATION

Taiwan Semiconductor Manu...

1. A method of semiconductor processing, the method comprising:depositing a dielectric layer on a substrate;
depositing a mask over the dielectric layer;
patterning a photoresist over the mask, the photoresist having a trench;
etching a first mask opening and a second mask opening through the mask, etching the first mask opening and the second mask opening comprising etching the mask through the trench in the photoresist, wherein the trench has a uniform width across regions where the first mask opening and the second mask opening are etched;
etching a first contact opening and a second contact opening through the dielectric layer, etching the first contact opening and the second contact opening comprises etching the dielectric layer through the first mask opening to form the first contact opening and etching the dielectric layer through the second mask opening to form the second contact opening, the first contact opening and the second contact opening having respective lengths that are aligned and corresponding to a length of the trench in the photoresist, a width of the first contact opening being greater than a width of the second contact opening; and
filling the first contact opening and the second contact opening with a conductive material to form a first contact and a second contact, respectively.

US Pat. No. 10,797,057

DRAM SEMICONDUCTOR DEVICE HAVING REDUCED PARASITIC CAPACITANCE BETWEEN CAPACITOR CONTACTS AND BIT LINE STRUCTURES AND METHOD FOR MANUFACTURING THE SAME

Winbond Electronic Corp.,...

1. A method for manufacturing a semiconductor device, comprising:forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the plurality of bit line structures;
forming a first oxide layer conformally covering the plurality of bit line structures and the plurality of trenches;
forming a photoresist material layer in the plurality of trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer;
removing the photoresist material layer in a first region to expose the first oxide layer in the first region;
forming a second oxide layer on the first oxide layer in the first region;
removing the photoresist material layer and horizontal portions of the first oxide layer in a second region to form a plurality of capacitor contact holes between the plurality of bit line structures, wherein the first region and the second region are arranged in a staggered manner; and
forming a capacitor contact in each of the plurality of capacitor contact holes.

US Pat. No. 10,797,056

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a substrate including a first active region, a second active region, a first field region, a second field region and a third field region, the second field region being disposed between the first field region and the third field region, and the second active region being disposed between the second field region and the third field region;
a first buried semiconductor layer buried in the first active region of the substrate, and contacting the first field region and the first active region;
a second buried semiconductor layer buried in the second active region of the substrate, and contacting the second active region and the third field region;
a word line buried in the substrate and crossing at least one of the first active region and the second active region;
a bit line structure disposed on the second field region, and including a conductive bit line and a bit line capping pattern disposed on the conductive bit line;
a first conductive contact disposed on the first buried semiconductor layer;
a second conductive contact disposed on the second buried semiconductor layer;
a first insulation spacer disposed between the first conductive contact and the bit line structure;
a second insulation spacer disposed between the bit line structure and the second conductive contact; and
a charge storage disposed on at least one of the first conductive contact and the second conductive contact,
wherein the first buried semiconductor layer contacts the first conductive contact and the first insulation spacer,
the second buried semiconductor layer contacts the second conductive contact and the second insulation spacer, and
a top surface of the first insulation spacer is co-planar with a topmost surface of the bit line capping pattern.

US Pat. No. 10,797,055

MEMORY CELL COMPRISING FIRST AND SECOND TRANSISTORS AND METHODS OF OPERATING

Zeno Semiconductor, Inc.,...

1. A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said semiconductor memory cells comprises:a first transistor having a first body;
a second transistor having a second body;
a substrate underlying both of said first and second bodies;
a buried layer interposed between said substrate and at least one of said first and second bodies;
a first source region contacting said first body;
a first drain region separated from said first source region and contacting said first body;
a first gate insulated from said first body;
an insulating member insulating said first body from said second body;
a second source region contacting said second body;
a second drain region separated from said second source region and contacting said second body; and
a second gate insulated from said second body;
wherein said first drain region is electrically connected to said second source region.

US Pat. No. 10,797,054

MEMORY DEVICE AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising a first memory cell and a second memory cell, each of the first memory cell and the second memory cell comprising:a first transistor comprising a gate electrode, a gate insulating film over the gate electrode, and a channel formation region over the gate insulating film, the channel formation region comprising an oxide semiconductor material;
a second transistor comprising a first gate electrode, a first gate insulating film over the first gate electrode, a first channel formation region over the first gate insulating film, a second gate insulating film over the first channel formation region and a second gate electrode over the second gate insulating film;
a first wiring electrically connected to the gate electrode of the first transistor; and
a capacitor, wherein a first electrode of the capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor,
wherein the one of the source electrode and the drain electrode of the first transistor is directly connected to the second gate electrode of the second transistor, and
wherein the second transistor of the first memory cell and the second transistor of the second memory cell are connected to a second wiring in series.

US Pat. No. 10,797,053

GATED DIODE MEMORY CELLS

Micron Technology, Inc., ...

1. An apparatus, comprising:an access device coupled to a first access line and a second access line;
a gated diode coupled to the access device and comprising a gate stack structure; and
an ohmic contact coupled to the gated diode, wherein the ohmic contact extends in first dimension above the gated diode and in a second dimension orthogonal to the first dimension such that at least a portion of the ohmic contact is disposed at an elevation higher than the second access line.

US Pat. No. 10,797,052

METHOD AND STRUCTURE FOR FINFET DEVICES

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate;
an isolation structure over the substrate;
a semiconductor fin structure over the substrate and surrounded by the isolation structure, wherein the semiconductor fin structure includes a lower layer, a middle layer over the lower layer, and an upper layer over the middle layer wherein at least a portion of the upper layer is surrounded by the isolation structure; and
a doped material layer between the isolation structure and the semiconductor fin structure, wherein the doped material layer is only above the lower layer.

US Pat. No. 10,797,051

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate including a first active pattern and a second active pattern, the first active pattern including a first source/drain, a second source/drain and a first channel between the first source/drain and the second source/drain, the second active pattern including a third source/drain, a fourth source/drain and a second channel between the third source/drain and the fourth source/drain;
a device isolation pattern disposed between the first active pattern and the second active pattern;
a gate structure disposed on the device isolation pattern, the first channel and the second channel, and including a gate electrode, a gate dielectric surrounding a bottom surface and sidewalls of the gate electrode, a spacer disposed on a sidewall of the gate dielectric and a capping pattern disposed on the gate electrode;
a first contact disposed on the first source/drain and on a first sidewall of the gate structure, the first contact being electrically connected to the first source/drain, the first contact including a first conductive structure and a first barrier pattern surrounding a bottom surface and sidewalls of the first conductive structure;
a second contact disposed on the device isolation pattern, the second contact including a second conductive structure and a second barrier pattern surrounding a bottom surface and sidewalls of the second conductive structure; and
a conductive pattern disposed on the second contact and electrically connected to the second contact,
wherein the first conductive structure includes a first upper portion, a first lower portion and a first middle portion between the first upper portion and the first lower portion,
a width of the first upper portion of the first conductive structure is greater than a width of the first lower portion of the first conductive structure,
a slope of each of the sidewalls of the first conductive structure is changed at the first middle portion,
a sidewall of the first middle portion of the first conductive structure is concavely rounded,
the second conductive structure includes a second upper portion, a second lower portion and a second middle portion between the second upper portion and the second lower portion,
a width of the second upper portion of the second conductive structure is greater than a width of the second lower portion of the second conductive structure,
a slope of each of the sidewalls of the second conductive structure is changed at the second middle portion,
a sidewall of the second middle portion of the second conductive structure is concavely rounded, and
a bottom surface of the second contact is disposed higher than a highest portion of the device isolation pattern.

US Pat. No. 10,797,050

FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH CAPPING LAYER AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A fin field effect transistor (FinFET) device structure, comprising:a first gate structure formed over a fin structure;
a first capping layer formed over the first gate structure;
a first etching stop layer formed over the first capping layer and the first gate structure, wherein a top surface and a sidewall surface of the first capping layer are in direct contact with the first etching stop layer; and
a dielectric layer formed over the substrate, wherein the dielectric layer has a first portion and a second portion, the first portion and the second portion has a step height, and the first gate structure is formed in the first portion of the dielectric layer.

US Pat. No. 10,797,049

FINFET STRUCTURE WITH DIELECTRIC BAR CONTAINING GATE TO REDUCE EFFECTIVE CAPACITANCE, AND METHOD OF FORMING SAME

GLOBALFOUNDRIES INC., Gr...

1. A fin-type field effect transistor (FinFET) structure comprising:a substrate having at least two fins thereon laterally spaced from one another;
a metal gate over fin tops of the at least two fins and between sidewalls of upper portions of the at least two fins;
source/drain regions in each fin on opposing sides of the metal gate;
a dielectric bar within the metal gate located between the sidewalls of the upper portions of the at least two fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the at least two fins within the metal gate; and
a gate cut isolation extending from a portion of a top surface of the metal gate to at least a portion of a top surface of the dielectric bar.

US Pat. No. 10,797,048

SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a gate structure including a gate electrode layer, a first cap insulating layer disposed over the gate electrode layer, a second cap insulating layer disposed over the first cap insulating layer, and sidewall spacers disposed on opposing side walls of the gate electrode layer;
a gate contact contacting the gate electrode layer passing through the first and second cap insulating layers,
wherein the first cap insulating layer extends over and is disposed on the sidewall spacers, and surrounds the gate contact, and
the second cap insulating layer is disposed between a lateral portion of the first cap insulating layer and the gate contact;
an etch-stop-layer disposed on and in direct contact with the first cap insulating layer and the second cap insulating layer;
a first source/drain region disposed adjacent to one of the sidewall spacers;
a first source/drain conductive plug disposed on the first source/drain region, wherein a lateral surface of the first source/drain conductive plug contacts a lateral surface of the one of the sidewall spacer; and
a first source/drain etch-stop plug disposed on the first source/drain conductive plug, wherein a lateral surface of the first source/drain etch-stop plug is in direct contact with the lateral surface of the one of the sidewall spacers and is in direct contact with a lateral surface of the first cap insulating layer.

US Pat. No. 10,797,047

GATE ISOLATION IN NON-PLANAR TRANSISTORS

Intel Corporation, Santa...

1. An apparatus comprising:first and second semiconductor fins that are parallel to each other;
a first gate, on the first fin, including a first gate portion between the first and second fins;
a second gate, on the second fin, including a second gate portion between the first and second fins;
a first oxide layer extending along a first face of the first gate portion, a second oxide layer extending along a second face of the second gate portion, and a third oxide layer directly connecting the first and second oxide layers to each other; and
an insulation material between the first and second gate portions;
wherein (a) the first, second, and third oxide layers are contiguous and monolithic with each other, (b) the first, second, and third oxide layers each include an oxide material, and (c) the insulation material does not include the oxide material;
wherein (a) an axis intersects the first and second fins, the first and second gate portions, the first and second oxide layers, and the insulation material, (b) the first fin includes a long axis that is orthogonal to the axis, (c) the first oxide layer extends along a bottom portion of the first face but does not extend along a top portion of the first face, (d) the second oxide layer extends along a bottom portion of the second face but does not extend along a top portion of the second face, and (e) the bottom portion of the first face is between the first oxide layer and the first fin and the bottom portion of the second face is between the second oxide layer and the second fin.

US Pat. No. 10,797,046

RESISTOR STRUCTURE FOR INTEGRATED CIRCUIT, AND RELATED METHODS

GLOBALFOUNDRIES, INC., G...

1. A resistor structure for an integrated circuit (IC), the resistor structure comprising:a shallow trench isolation (STI) region on a substrate;
a resistive material above a portion of the shallow trench isolation (STI) region;
a gate structure on another portion of the STI region, above the substrate, and horizontally displaced from the resistive material;
an insulative barrier above the STI region and contacting an upper surface and sidewalls of the resistive material, wherein an upper surface of the insulative barrier is substantially coplanar with an upper surface of the gate structure;
a pair of contacts within the insulative barrier, and each positioned on an upper surface of the resistive material;
a transistor adjacent the STI region, the transistor including an additional gate structure horizontally displaced from the gate structure; and
an additional insulative barrier directly horizontally between a first portion of the additional gate structure and a second portion of the additional gate structure.

US Pat. No. 10,797,045

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate including a transistor region,
wherein in the transistor region, the semiconductor substrate includes:
a plurality of trench portions extending in a predetermined direction,
a mesa portion each provided between two adjacent trench portions in the plurality of trench portions, and
a drift layer of a first conductivity type provided below the mesa portion,
wherein the plurality of trench portions include:
a gate trench portion having a gate conductive portion, to which a gate potential is supplied, and
a plurality of dummy trench portions, each having a dummy trench conductive portion, to which an emitter potential is supplied,
wherein the mesa portion comprises:
an emitter region of the first conductivity type having a higher doping concentration than the drift layer, the emitter region being at least partially positioned on an upper surface of the semiconductor substrate,
a contact region of a second conductivity type being at least partially positioned on an upper surface of the semiconductor substrate, and
one or more accumulation layers being provided below the emitter region and the contact region, the one or more accumulation layers having a higher doping concentration of the first conductivity type than the drift layer,
wherein a number of the one or more accumulation layers provided in a depth direction from the upper surface to a lower surface of the semiconductor substrate in the mesa portion adjacent to the gate trench portion is larger than the number of the one or more accumulation layers provided in the depth direction in the mesa portion between two dummy trench portions among the plurality of dummy trench portions.

US Pat. No. 10,797,044

ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD

SEMICONDUCTOR MANUFACTURI...

1. An electrostatic discharge (ESD) protection device, comprising:a semiconductor substrate;
a semiconductor fin located on the semiconductor substrate, the semiconductor fin comprising:
a well region;
a first doped region having a first conductivity type; and
a second doped region having a second conductivity type opposite the first conductivity type, wherein the first doped region and the second doped region are respectively adjacent to and being separated by a first portion of the well region;
a first gate structure on said semiconductor fin between the first doped region and the second doped region, the first gate structure having first and second spacers on opposite sidewalls of the first gate structure, the first spacer on a surface portion of the first doped region, and the second spacer on a surface portion of the second doped region;
a first conductive structure electrically connecting the first gate structure and the first doped region to a same potential;
a second conductive structure for connecting the second doped region to a point between an external signal and a circuit to be protected;
a third doped region, separated from the second doped region by a second portion of the well region;
a second gate structure on the semiconductor fin and disposed between the second doped region and the third doped region; and
a third conductive structure electrically connecting the second gate structure and the third doped region to the same potential as the first gate structure and the first doped region;
wherein:
the well region has the first conductivity type;
the third doped region has the first conductivity type with a dopant concentration greater than a dopant concentration of the well region; and
the second doped region has a dopant concentration greater than the dopant concentration of the well region.

US Pat. No. 10,797,043

SEMICONDUCTOR DEVICE WITH BIDIRECTIONAL DIODE

ABLIC INC., Chiba (JP)

1. A semiconductor device, comprising:a semiconductor substrate;
a drain region of a first conductivity type and a source region of the first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed between the drain region and the source region;
a base contact region of the second conductivity type formed in the base region and being higher in concentration than the base region;
a gate electrode formed in the base region through a gate insulating film so that a channel is formed in the base region;
a bidirectional diode having a first end electrically connected to the source region;
a source metal layer electrically connected to the source region, the base contact region, and the first end of the bidirectional diode; and
a gate metal layer electrically connected to the gate electrode, and overlapping at least partially with the source metal layer in a first direction perpendicular to a surface of the semiconductor substrate, in at least a part of a region on the semiconductor substrate,
wherein the gate electrode is composed of a polysilicon layer of the first conductivity type,
wherein the bidirectional diode includes the gate electrode, a second polysilicon layer of the second conductivity type formed on the gate electrode, and a third polysilicon layer of the first conductivity type formed on the second polysilicon layer, and
wherein the gate electrode, the second polysilicon layer, and the third polysilicon layer are arranged in this order in the first direction.

US Pat. No. 10,797,042

SEMICONDUCTOR DEVICE

SOCIONEXT INC., Kanagawa...

1. A semiconductor device, comprising:a semiconductor substrate;
a first standard cell including a first active region and a second active region; and
a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and
wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction,
wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and
wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.

US Pat. No. 10,797,041

INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit comprising:a first region;
a first conductive structure in the first region, wherein the first conductive structure extends in a first direction;
a first via coupled to the first conductive structure;
a second region adjacent to the first region; and
a power structure configured to supply a voltage to the first region or the second region, wherein the power structure comprises a second conductive structure extending in the first direction and overlapping a boundary between the first region and the second region, the first conductive structure and the second conductive structure are aligned in a second direction different than the first direction, and the first conductive structure and the second conductive structure are separated from each other in the first direction by a distance greater than a minimum spacing requirement of the first conductive structure and the second conductive structure.

US Pat. No. 10,797,040

METHOD OF MANUFACTURING DISPLAY MODULE USING LED

SAMSUNG ELECTRONICS CO., ...

1. A display module comprising:a first substrate structure comprising:
a partition structure having a plurality of light-emitting windows, each of the plurality of light-emitting windows comprising a wavelength converter, wherein at least one of the plurality of light-emitting windows comprises an optical filter disposed on the wavelength converter;
a light-emitting diode (LED) array including:
a plurality of LED cells, each LED cell of the plurality of LED cells having a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer,
a first electrode pad and a second pad connected to the plurality of LED cells, the plurality of light-emitting windows being respectively disposed on the plurality of LED cells, and
a first bonding layer covering the LED array
wherein a bottom surface of the first electrode pad, a bottom surface of the second electrode pad and a bottom surface of the first bonding layer together form a first coplanar surface; and
a second substrate structure comprising:
a plurality of driving transistors disposed on the first substrate structure and configured to control the plurality of LED cells, each driving transistor of the plurality of driving transistors comprising:
a channel semiconductor layer providing a channel region of the plurality of driving transistors;
a source region;
a drain region; and
a gate electrode disposed between the source region and the drain region, wherein the second substrate structure is configured to form a circuit region, in which a first connection portion and a second connection portion, disposed to correspond to the first electrode pad and the second electrode pad respectively, are disposed one surface of the second substrate structure,
a second bonding layer covering the circuit region, wherein a top surface of the first connection portion, a top surface of the second connection portion and a top surface of the second bonding layer together form a second coplanar surface bonded to the first coplanar surface of the first substrate structure, and
a first electrode pattern and a second electrode pattern disposed on channel semiconductor layer, wherein the first electrode pattern is connected to the first connection portion, and the second electrode pattern is connected to the drain region.

US Pat. No. 10,797,039

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A 3D INTERPOSER SYSTEM-IN-PACKAGE MODULE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a first substrate;
providing a second substrate;
forming an opening through the second substrate;
disposing a first semiconductor component and second semiconductor component between the first substrate and second substrate, wherein the second substrate is electrically coupled to the first substrate through the first semiconductor component and the second semiconductor component extends into the opening, and wherein the first semiconductor component supports the first substrate over the second substrate; and
depositing an encapsulant over the first substrate and second substrate.

US Pat. No. 10,797,038

SEMICONDUCTOR PACKAGE AND REWORK PROCESS FOR THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming a second package, wherein forming the second package comprises:
forming a back-side redistribution structure;
forming first electrical connectors over the back-side redistribution structure, wherein forming the first electrical connectors comprises forming a seed layer over the back-side redistribution structure and plating a conductive material over the seed layer;
attaching a first die to the back-side redistribution structure using an adhesive;
forming an encapsulant surrounding the first die and the first electrical connectors;
planarizing the first die, the first electrical connectors, and the encapsulant such that the first electrical connectors have a first height measured between a bottommost surface of the first electrical connectors and a topmost surface of the first electrical connectors, the encapsulant has a second height measured between a bottommost surface of the encapsulant and a topmost surface of the encapsulant, the first die has a third height measured between a bottommost surface of the first die and a topmost surface of the first die, the first height being greater than the second height, the second height being greater than the third height, wherein the topmost surface of the first die is level with the topmost surface of the encapsulant and the topmost surface of the first electrical connectors; and
forming a front-side redistribution structure over the first die, the first electrical connectors, and the encapsulant, the front-side redistribution structure comprising a first set of conductive pads and a second conductive pad adjacent the first set of conductive pads, the second conductive pad having a height greater than heights of the conductive pads of the first set of conductive pads;
forming a metal pillar on the second conductive pad, the metal pillar having vertical sidewalls, the metal pillar comprising a material different from a material of the second conductive pad;
forming a metal cap layer over the metal pillar, the metal cap layer comprising a material different from the material of the metal pillar and the material of the second conductive pad;
bonding a front-side surface of a first package to the first set of conductive pads of the second package with a first set of solder joints, the first package having a height less than a height of the metal pillar;
testing the first package for defects;
heating the first set of solder joints by directing a laser beam at a back-side surface of the first package, the back-side surface of the first package being opposite the front-side surface of the first package, wherein heating the first package is based on testing the first package for defects;
when the first set of solder joints are heated, removing the first package;
after removing the first package, re-testing the first package to determine whether the first package is functional;
when the first package is removed, bonding a third package to the first set of conductive pads of the second package; and
after testing the first package for defects, sawing the second package to singulate the second package from a fourth package.

US Pat. No. 10,797,037

INTEGRATED CIRCUIT DEVICE HAVING A PLURALITY OF STACKED DIES

XILINX, INC., San Jose, ...

1. An integrated circuit device having a plurality of stacked dies, the integrated circuit device comprising:a first die of the plurality of stacked dies having an input/output element configured to receive an input signal, the first die comprising a signal driver circuit configured to provide the input signal to each die of the plurality of stacked dies and a chip select circuit for generating a plurality of chip select signals for the plurality of stacked dies; and
a second die of the plurality of stacked dies coupled to the first die, the second die having a function block configured to receive the input signal;
wherein the second die receives the input signal in response to a chip select signal of the plurality of chip select signals that corresponds to the second die.

US Pat. No. 10,797,036

SEMICONDUCTOR DEVICE

DENSO CORPORATION, Kariy...

1. A semiconductor device comprising:a first semiconductor chip that is formed with an IGBT, and has a collector electrode of the IGBT on a first surface and an emitter electrode of the IGBT on a second surface opposite to the first surface in a first direction which is a plate thickness direction;
a second semiconductor chip that is arranged next to the first semiconductor chip in a second direction perpendicular to the first direction, formed with a MOSFET, and has a drain electrode of the MOSFET on a first surface that is on a same side as the first surface of the first semiconductor chip in the first direction, and a source electrode of the MOSFET on a second surface that is on a same side as the second surface of the first semiconductor chip in the first direction;
a first metal member that is disposed adjacent to the first surfaces of the first and second semiconductor chips and electrically connected to both of the collector electrode and the drain electrode; and
a second metal member that is disposed adjacent to the second surfaces of the first and second semiconductor chips and electrically connected to both of the emitter electrode and the source electrode, wherein
the IGBT and the MOSFET are configured to be turned on in an order of the IGBT and then the MOSFET, and turned off in an order of the MOSFET and then the IGBT,
the second metal member includes a main body portion on which the first semiconductor chip and the second semiconductor chip are mounted, and a terminal portion that is connected to the main body portion and allows a current to flow into and out of the second metal member, and
in a plan view that is viewed in the first direction, a shortest distance between the terminal portion and the first semiconductor chip is shorter than a shortest distance between the terminal portion and the second semiconductor chip.

US Pat. No. 10,797,035

BONDED ASSEMBLY CONTAINING SIDE BONDING STRUCTURES AND METHODS OF MANUFACTURING THE SAME

SANDISK TECHNOLOGIES LLC,...

16. A method of forming a bonded assembly, comprising:forming a first external bonding pad on a front side of a first semiconductor die;
forming first bonding pads on the first semiconductor die such that bonding-side surfaces of the first bonding pads are more distal from a substrate of the first semiconductor die than a front-side surface of the first external bonding pad is from the substrate;
forming a first sacrificial pad cover structure over the first external bonding pad;
bonding a second semiconductor die to the first semiconductor die such that the first bonding pads of the first semiconductor die are bonded to second bonding pads of the second semiconductor die;
forming a first side cavity by removing the first sacrificial pad cover structure from a sidewall of the first semiconductor die; and
forming a bonding connection wire by injecting a bonding wire material into the first side cavity directly on the first external bonding pad and by continuously extracting the bonding wire material over the sidewall of the first semiconductor die.

US Pat. No. 10,797,034

ELECTRONIC DEVICE HAVING INDIVIDUAL WRAPPING OF ELECTRONIC PACKAGE UNITS AND MANUFACTURING METHOD THEREOF

GIO OPTOELECTRONICS CORP,...

1. A manufacturing method of electronic device, comprising:providing an insulation substrate, wherein the insulation substrate has a first surface and a second surface opposite to the first surface;
forming a plurality of sub-matrix circuits directly on the insulation substrate, wherein each of the sub-matrix circuits comprises at least one thin film transistor;
disposing at least one functional chip directly on the first surface, wherein the functional chip is electrically connected with the sub-matrix circuit;
forming a plurality of through-holes on the insulation substrate and disposing a conductive material in the through-holes, so that the functional chip is electrically connected to the second surface through the sub-matrix circuits and the conductive material;
forming a protection layer on the first surface to cover the functional chips;
cutting the insulation substrate and the protection layer to form a plurality of individual wrapping of the electronic package units; and
electrically connecting the conductive material of the electronic package units to a driving circuit board, wherein the driving circuit board faces toward the second surfaces of the insulation substrates, and the functional chips are electrically connected to the driving circuit board through the sub-matrix circuits and conductive material inside the through-holes.

US Pat. No. 10,797,033

APPARATUSES AND METHODS FOR HIGH SENSITIVITY TSV RESISTANCE MEASUREMENT CIRCUIT

Micron Technology, Inc., ...

1. An apparatus comprising:an interface (IF) die; and
at least one memory die, wherein the at least one memory die is stacked over the IF die through at least one through silicon/substrate via (TSV) so that current flows through the at least one TSV between the IF die and the at least one memory die;
wherein the IF die comprises:
a first conductive line through which current flows, and
an amplifier coupled to the at least one TSV and configured to output a signal related to a voltage across the at least one TSV;
wherein the at least one memory die comprises a second conductive line through which the current flows; and
wherein the first conductive line comprises a mesh wiring structure.

US Pat. No. 10,797,032

LIGHT-EMITTING ELEMENT MODULE

SHARP KABUSHIKI KAISHA, ...

1. A light-emitting element module comprising:at least two or more first electrodes of a first substrate that includes a circuit element; and
at least two or more light-emitting elements that are joined to the at least two or more first electrodes,
wherein the first substrate further includes a first wiring line to an n-th wiring line (n is an integer of 2 or more) that is formed into layers in order from the at least two or more light-emitting elements in a thickness direction of the first substrate,
wherein the first wiring line that is located in one of the layers of the first substrate nearest to the at least two or more light-emitting elements is formed at least in an interelectrode region between the adjacent first electrodes of the first substrate in a plan view, and
wherein a protective layer is formed as an outermost surface of the first substrate near the at least two or more light-emitting elements, the protective layer has an opening, the at least two or more first electrodes of the first substrate that are joined to second electrodes of the at least two or more light-emitting elements extend through the opening, and a second wiring line that is located in a layer adjacent to the first wiring line that is connected to the at least two or more first electrodes overlaps at least one of end portions of the first wiring line in a plan view.

US Pat. No. 10,797,031

SEMICONDUCTOR PACKAGE

Taiwan Semiconductor Manu...

1. A semiconductor package, comprising:a first optical transceiver comprising at least one optical input/output portion for transmitting and receiving an optical signal;
a second optical transceiver stacked on the first optical transceiver;
a third optical transceiver comprising at least one optical input/output portion for transmitting and receiving an optical signal, wherein the third optical transceiver is stacked on the second optical transceiver; and
a plasmonic waveguide penetrating through the second optical transceiver, wherein the plasmonic waveguide optically couples the at least one optical input/output portion of the first optical transceiver and the at least one optical input/output portion of the third optical transceiver.

US Pat. No. 10,797,030

SEMICONDUCTOR PACKAGES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package, comprising:a semiconductor chip, wherein the semiconductor chip comprises a first inner capacitor including a first terminal and a second terminal;
a plurality of first outer capacitors on the semiconductor chip, wherein the plurality of first outer capacitors are electrically connected in parallel to each other and wherein each first outer capacitor includes a first electrode and a second electrode;
a second outer capacitor on the semiconductor chip, wherein the second outer capacitor includes a first electrode pattern and a second electrode pattern;
a conductive pattern on the semiconductor chip and directly electrically connected to the first electrode of each of the plurality of first outer capacitors and the first electrode pattern of the second outer capacitor,
a first power pattern on the semiconductor chip and directly electrically connected to the second electrode of each of the plurality of first outer capacitors;
a ground via coupled to the conductive pattern; and
a first power via electrically connected to the first power pattern;
wherein the second electrode of each of the plurality of first outer capacitors is electrically insulated from the second electrode pattern of the second outer capacitor, and
wherein the first terminal and the second terminal are respectively electrically connected to the ground via and the first power via.

US Pat. No. 10,797,029

STRUCTURE WITH MICRO DEVICE

PlayNitride Inc., Hsinch...

1. A structure with micro device, comprising:a substrate;
a plurality of micro devices, disposed on the substrate and arranged in a plurality of rows, and each of the plurality of micro devices having a top surface facing away from the substrate; and
a plurality of holding structures, respectively disposed on the top surface of each of the plurality of micro devices and extending to the substrate, wherein distances between the plurality of holding structure on the top surface of the plurality of micro devices on any one of the rows and the plurality of holding structures on the top surface of the plurality of micro devices on two adjacent rows are different.

US Pat. No. 10,797,028

THREE-DIMENSIONAL MEMORY DEVICES WITH STACKED DEVICE CHIPS USING INTERPOSERS

YANGTZE MEMORY TECHNOLOGI...

1. A three-dimensional (3D) memory device, comprising:a first device chip, comprising:
a peripheral device; and
a first chip contact disposed on a surface of the first device chip and electrically connected to the peripheral device;
a second device chip, comprising:
an alternating conductor/dielectric stack and a memory string extending vertically through the alternating conductor/dielectric stack; and
a second chip contact disposed on a surface of the second device chip and electrically connected to the memory string; and
an interposer disposed vertically between the first device chip and the second device chip, the interposer comprising:
an interposer substrate;
a first interposer contact disposed on a first surface of the interposer; and
a second interposer contact disposed on a second surface opposite to the first surface of the interposer and electrically connected to the first interposer contact through the interposer substrate, wherein the first interposer contact is attached to the first chip contact, and the second interposer contact is attached to the second chip contact, and
wherein the second device chip further comprises a second chip substrate at a side of the second device chip opposite to the interposer.

US Pat. No. 10,797,027

DISPLAYING APPARATUS HAVING LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME AND METHOD OF TRANSFERRING LIGHT EMITTING DEVICE

Seoul Semiconductor Co., ...

1. A displaying apparatus, comprising:a panel substrate;
a plurality of light emitting devices arranged on the panel substrate; and
at least one connection tip disposed on one surface of each of the light emitting devices,
wherein each of the light emitting devices comprises:
a light emitting structure comprising a first conductivity type semiconductor layer, a second conductivity type semiconductor layer and an active layer interposed between the first and second conductivity type semiconductor layers; and
first and second electrode pads disposed on the light emitting structure, and
wherein the at least one connection tip is formed of material with a light transmittance of at least 90%.

US Pat. No. 10,797,026

VIDEO WALL MODULE AND METHOD OF PRODUCING A VIDEO WALL MODULE

OSRAM OLED GmbH, Regensb...

1. A video wall module comprising a plurality of light emitting diode chips,each comprising first contact electrodes and second contact electrodes arranged at a contact side,
wherein the light emitting diode chips are arranged at a top side of a multilayer circuit board,
the first and second contact electrodes electrically conductively connect to a first metallization layer arranged at the top side of the circuit board, and
the first contact electrode is an anode of the light emitting diode chip and the second contact electrode is a cathode of the light emitting diode chip or the first contact electrode is a cathode and the second contact electrode is an anode,
the circuit board comprises a second metallization layer, and
sections of the first metallization layer and sections of the second metallization layer electrically conductively connect to one another by through contacts arranged in the circuit board,
the circuit board comprises a third metallization layer, and
sections of the second metallization layer and sections of the third metallization layer electrically conductively connect to one another by through contacts arranged in the circuit board.

US Pat. No. 10,797,025

ADVANCED INFO POP AND METHOD OF FORMING THEREOF

Taiwan Semiconductor Manu...

1. A method of forming semiconductor packages comprising:providing a semiconductor structure comprising a plurality of top packages coupled to corresponding ones of a plurality of bottom packages;
attaching the semiconductor structure to an upper mold chase;
closing the upper mold chase and a lower mold chase, thereby forming an enclosed cavity;
removing air from the enclosed cavity;
immersing the semiconductor structure in a molded underfill (MUF) material contained in the enclosed cavity, wherein sidewalls of the plurality of top packages and sidewalls of the plurality of bottom packages are covered by the MUF material after the immersing, wherein a coefficient of thermal expansion (CTE) of the MUF material is chosen to be between a first overall CTE of the plurality of top packages and a second overall CTE of the plurality of bottom packages; and
curing the MUF material.

US Pat. No. 10,797,024

SYSTEM-IN-PACKAGE WITH DOUBLE-SIDED MOLDING

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a substrate including a first opening formed through the substrate;
disposing a first electronic component over the substrate;
disposing a second electronic component over the substrate;
providing a mold including a first chamber;
disposing the substrate in the mold with the first electronic component and second electronic component disposed in the first chamber, wherein a second opening of the mold is disposed over a first side of the substrate;
depositing an encapsulant into the second opening, wherein the encapsulant flows through the first opening to cover the first electronic component, second electronic component, and a second side of the substrate; and
singulating the substrate and encapsulant between the first electronic component and second electronic component.

US Pat. No. 10,797,023

INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING AN INTEGRATED FAN-OUT PACKAGE

Taiwan Semiconductor Manu...

1. A method of fabricating an integrated fan-out (INFO) package, comprising:forming a first buffer pattern and a second buffer pattern on a substrate;
attaching a first chip on the substrate through the first buffer pattern and attaching a second chip on the substrate through the second buffer pattern;
providing a squeezing force between an exterior surface of the substrate and a top surface of the first chip and between the exterior surface of the substrate and a top surface of the second chip, wherein the exterior surface of the substrate is parallel to the top surface and a bottom surface of the first chip and to the top surface and a bottom surface of the second chip;
curing the squeezed first buffer pattern and the squeezed second buffer pattern;
forming a molding compound surrounding the first chip, the second chip, the squeezed first buffer pattern and the squeezed second buffer pattern after curing the squeezed first buffer pattern and the squeezed second buffer pattern; and
forming a redistribution circuit structure layer electrically connected to the first chip and the second chip on the molding compound.

US Pat. No. 10,797,022

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a first redistribution layer (RDL);
a first die on the first RDL and electrically connected to the first RDL, the first die having a first electrical contact;
a second die on the first RDL and electrically connected to the first RDL, the second die having a second electrical contact;
a second RDL surrounded by the first RDL, the second RDL having a third electrical contact electrically connected to the first electrical contact of the first die and a fourth electrical contact electrically connected to the second electrical contact of the second die, a size of the third electrical contact of the second RDL being greater than a size of the fourth electrical contact of the second RDL; and
an encapsulant on the first RDL and covering the first die and the second die.

US Pat. No. 10,797,021

SEMICONDUCTOR PACKAGES HAVING IMPROVED THERMAL DISCHARGE AND ELECTROMAGNETIC SHIELDING CHARACTERISTICS

Samsung Electronics Co., ...

1. A semiconductor package, comprising:a first semiconductor chip on a wiring substrate, the first semiconductor chip electrically connected to the wiring substrate;
an intermediate layer on the first semiconductor chip, the intermediate layer covering an entire surface of the first semiconductor chip;
a second semiconductor chip on the intermediate layer, the second semiconductor chip electrically connected to the wiring substrate;
a mold layer on the wiring substrate, the mold layer covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces at least partially defining a mold via hole that exposes a portion of a surface of the intermediate layer;
an electromagnetic shielding layer on the one or more inner surfaces of the mold layer, the electromagnetic shielding layer further on one or more outer surfaces of the mold layer; and
a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

US Pat. No. 10,797,020

SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE STACKS OF DIFFERENT SEMICONDUCTOR DIES

Micron Technology, Inc., ...

1. A semiconductor device assembly, comprising:a package substrate having an upper surface with an upper surface area;
a first stack of semiconductor dies disposed over a first region on the substrate, each semiconductor die of the first stack of semiconductor dies having a same first length and a same first width;
a second stack of semiconductor dies disposed over a second region on the substrate, each semiconductor die of the second stack of semiconductor dies having a same second length and a same second width; and
an encapsulant at least partially encapsulating the substrate, the first stack and the second stack,
wherein the first length is different than the second length and the second width, and
wherein the first region has a first area, the second region has a second area, and a sum of the first and second areas is at least 90% of the upper surface area of the upper surface of the package substrate.

US Pat. No. 10,797,019

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a first semiconductor die having an active surface;
a second semiconductor die having an active surface;
a first conductive pillar disposed adjacent to the active surface of the first semiconductor die;
a second conductive pillar disposed adjacent to the active surface of the second semiconductor die, wherein a height of the first conductive pillar is different from a height of the second conductive pillar, and an end surface of the first conductive pillar of the first semiconductor die is substantially coplanar with an end surface of the second conductive pillar of the second semiconductor die;
an encapsulant covering the first semiconductor die, the second semiconductor die, the first conductive pillar and the second conductive pillar, wherein the encapsulant defines a first groove adjacent to and surrounding the first conductive pillar and a second groove adjacent to and surrounding the second conductive pillar, and a maximum depth of the first groove is substantially the same as a depth of the second groove; and
a circuit structure electrically connected to and in direct contact with the first conductive pillar and the second conductive pillar, wherein the circuit structure comprises a redistribution layer.

US Pat. No. 10,797,018

METHODS FOR FABRICATING 3D SEMICONDUCTOR DEVICE PACKAGES, RESULTING PACKAGES AND SYSTEMS INCORPORATING SUCH PACKAGES

Micron Technology, Inc., ...

1. A semiconductor device package, comprising:a stack of semiconductor dice, wherein a surface of a lowermost semiconductor die of the stack protrudes laterally beyond a periphery of other, higher semiconductor dice of the stack;
a non-polymeric dielectric bond line material between adjacent semiconductor dice of the stack;
connections between metal pillars and aligned terminal pads of adjacent semiconductor dice of the stack, the connections comprising diffusion bonds or mutual contact secured by a dielectric bond with the non-polymeric dielectric bond line material; and
a substantially conformal, non-polymeric coating extending over a back side of an uppermost semiconductor die of the stack, over and in contact with a material of the respective semiconductor dice on sides of the stack and over and in contact with the laterally protruding surface of the lowermost semiconductor die of the stack.

US Pat. No. 10,797,017

EMBEDDED CHIP PACKAGE, MANUFACTURING METHOD THEREOF, AND PACKAGE-ON-PACKAGE STRUCTURE

Unimicron Technology Corp...

1. An embedded chip package, comprising:a circuit board, comprising:
a glass substrate having a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate; and
at least one conductive via penetrating the glass substrate;
a chip disposed inside the through-hole;
a dielectric material layer filled inside the through-hole and covering the chip; and
a build-up circuit structure disposed on the circuit board, wherein the build-up circuit structure is electrically connected to the conductive via, a lower surface of the chip is exposed outside the dielectric material layer, and the lower surface of the chip is an active surface.

US Pat. No. 10,797,016

METHOD FOR BONDING SEMICONDUCTOR CHIPS TO A LANDING WAFER

IMEC vzw, Leuven (BE) Ka...

1. A method of bonding one or more individual semiconductor chips to a landing wafer, each chip comprising a chip bonding surface that is at least partially wettable by an alignment liquid, the landing wafer comprising one or more bonding sites respectively configured to receive the one or more chips, the one or more bonding sites comprising a landing wafer bonding surface that is at least partially wettable by the alignment liquid, the method comprising:supplying the alignment liquid through an orifice of a droplet dispensing apparatus, at least part of a volume of the alignment liquid attached to the orifice extending outward from the orifice;
moving a chip so that the chip bonding surface of the chip approaches the volume of the alignment liquid attached to the orifice until the volume of the alignment liquid spreads across the chip bonding surface or a wettable portion thereof, while being contained to the chip bonding surface;
after the volume of the alignment liquid spreads across the chip bonding surface or wettable portion thereof, positioning the chip above the landing wafer bonding surface of a bonding site of the landing wafer in such a manner that the alignment liquid spreads out across both the chip bonding surface and the landing wafer bonding surface or wettable portions thereof, while being contained to the chip bonding surface and the landing wafer bonding surface;
thereafter releasing the chip so that the alignment liquid establishes a self-alignment of the chip to the bonding site of the landing wafer,
optionally repeating the supplying, moving, positioning, and releasing steps for additional chips; and
bonding the one or more chips to the one or more bonding sites of the landing wafer, respectively.

US Pat. No. 10,797,015

METHOD OF MANUFACTURING 3DIC STRUCTURE

Taiwan Semiconductor Manu...

1. A method of manufacturing a 3DIC structure, comprising:bonding a die to a wafer;
forming a first dielectric layer on the wafer and laterally aside the die;
forming a second dielectric material layer on the die and the first dielectric layer;
selectively removing a portion of the second dielectric material layer over a non-edge region of the wafer to form a protruding portion over an edge region of the wafer; and
planarizing the second dielectric material layer to form a second dielectric layer on the first dielectric layer and the die;
wherein a first corner of the first dielectric layer comprises a first rounding portion, a second corner of the second dielectric layer comprises a second rounding portion; and
a width of the second rounding portion is less than a width of the first rounding portion, a height of the second rounding portion is less than a height of the first rounding portion.

US Pat. No. 10,797,014

ROUNDED METAL TRACE CORNER FOR STRESS REDUCTION

Intel Corporation, Santa...

1. An integrated circuit package, comprising:a first integrated circuit die;
a second integrated circuit die;a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate; andan interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners and a rounded bottom surface.

US Pat. No. 10,797,013

ACRYLIC RESIN COMPOSITION FOR SEALING, CURED PRODUCT OF SAME, METHOD FOR PRODUCING SAME, SEMICONDUCTOR DEVICE USING SAID RESIN COMPOSITION, AND METHOD FOR MANUFACTURING SAID SEMICONDUCTOR DEVICE

PANASONIC INTELLECTUAL PR...

1. A sealing acrylic resin composition comprising:a thermosetting acrylic resin in liquid phase;
an organic peroxide; and
an inorganic filler,wherein:the thermosetting acrylic resin includes
tricyclodecane dimethanol diacrylate and
bisphenol A epoxy acrylate,wherein a content proportion of tricyclodecane dimethanol diacrylate is greater than a content proportion of bisphenol A epoxy acrylate,a silane coupling agent is bonded to the inorganic filler, a total organic carbon content of the inorganic filler in proportion being ranging from 0.1% by mass to 1.0% by mass, inclusive, in a state before the inorganic filler is mixed with at least one of the thermosetting acrylic resin and the organic peroxide,
the silane coupling agent has an acrylic group,
the inorganic filler includes alumina, and
a content proportion of the inorganic filler in the sealing acrylic resin composition ranges from 70% by mass to 95% by mass, inclusive.

US Pat. No. 10,797,012

MULTI-PIN-WAFER-LEVEL-CHIP-SCALE-PACKAGING SOLUTION FOR HIGH POWER SEMICONDUCTOR DEVICES

Dialog Semiconductor (UK)...

1. A multi-pin wafer level chip scale package comprising:one or more solder pillars and one or more solder blocks on a silicon wafer wherein said one or more solder pillars and said one or more solder blocks all have a top surface in a same horizontal plane and wherein at least one side of said solder blocks in a two-dimensional plane is greater than 600 ?m and wherein said solder pillars are thinner and narrower than said solder blocks;
a pillar metal layer directly underlying each of said one or more solder pillars and electrically connecting said one or more solder pillars with said silicon wafer through an opening in a polymer layer over a passivation layer on said silicon wafer, wherein said pillar metal layer comprises:
a redistribution layer (RDL) trace contacting said silicon wafer at a silicon pad exposed by said opening in said polymer layer over said passivation layer; and
an under pillar metal (UPM) trace on said RDL trace; and
a block metal layer directly underlying each of said one or more solder blocks and electrically connecting said one or more solder blocks with said silicon wafer through a plurality of via openings through said polymer layer over said passivation layer on said silicon wafer, wherein said block metal layer comprises:
a redistribution layer via (RDL_VIA) contacting said silicon wafer through said plurality of via openings in said polymer layer and said passivation layer to said silicon wafer; and
an under block metal (UBM) layer covering said RDL_VIA layer in said plurality of via openings;
wherein said block metal layer is thicker and wider than said pillar metal layer, wherein said RDL trace has a thickness of at least 4 ?m, said UPM trace has a thickness of at least 8 ?m, said RDL_VIA layer has a thickness of at least 25 ?m, said UBM layer has a thickness of at least 25 ?m and a width of at least 600 ?m in at least one direction, said solder pillar has a height of at least 120 ?m and said solder block has a height of at least 100 ?m and a width of at least 600 ?m.

US Pat. No. 10,797,011

METHOD OF FORMING SOLDER BUMPS

International Business Ma...

1. A solder bump structure comprising:a free-standing metal pillar formed directly on an electrode pad;
a conductive layer disposed directly on the metal pillar over the electrode pad, the conductive layer including a sintered conductive paste formulated to form a cone-shaped top surface determined by volume shrinkage during sintering and dependent on dimensions of a solder bump, a planar bottom surface and a sidewall substantially perpendicular to the planar bottom surface; and
a solder formed on the cone-shaped top surface of the conductive layer, the solder having a convex top surface.

US Pat. No. 10,797,010

SEMICONDUCTOR PACKAGE HAVING A METAL BARRIER

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device comprising:a metallization layer electrically connected to an integrated circuit;
a passivation layer adjacent to the metallization layer;
a barrier layer of a same metal, electrically connected to the metallization layer and contacting a first adhesion layer, wherein the first adhesion layer contacts the passivation layer;
a polyimide layer in contact with the passivation layer and directly in contact with portions of a top surface of the barrier layer;
a metal structure electrically connected to the barrier layer, the metal structure in contact with a second adhesion layer, and the second adhesion layer in contact with portions of the polyimide layer; and
solder in contact with the metal structure.

US Pat. No. 10,797,009

METHOD FOR TRANSFERRING MICRO DEVICE

MIKRO MESA TECHNOLOGY CO....

1. A method for transferring a micro device, comprising:forming a liquid layer on the micro device attached on a transfer plate;
placing the micro device over a receiving substrate after forming the liquid layer, such that the liquid layer is between the micro device and a contact pad of the receiving substrate and contacts the contact pad; and
evaporating the liquid layer such that the micro device is bound to and in contact with the contact pad.

US Pat. No. 10,797,008

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

17. A manufacturing method of a semiconductor package, comprising:embedding a bottom of a semiconductor die in a die attach material that is on a dielectric layer of a redistribution structure, wherein in a plan view, a portion of the die attach material extends beyond sidewalls of the semiconductor die, and a width of the portion of the die attach material increases from an endpoint of a bottom edge of the portion of the die attach material to a midpoint of the bottom edge of the portion of the die attach material; and
forming an insulating encapsulant on the dielectric layer of the redistribution structure to encapsulate the semiconductor die and the die attach material.

US Pat. No. 10,797,007

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a first insulation;
a second insulation over the first insulation;
a third insulation over the second insulation;
a first conductor proximal to a boundary between the first insulation and the second insulation; and
an electronic device electrically connected to the first conductor and at least partially surrounded by the second insulation, wherein
a coefficient of thermal expansion (CTE) of the second insulation is larger than a CTE of the first insulation and larger than a CTE of the third insulation.

US Pat. No. 10,797,006

STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH LID

TAIWAN SEMICONDUCTOR MANU...

1. A chip package, comprising:a substrate;
a semiconductor die over the substrate; and
a lid covering a top surface of the semiconductor die, wherein the lid has a plurality of support structures, the plurality of support structures are positioned at respective corner portions of the substrate, one of the support structures has a first side and a second side opposite to the first side, the first side is separated from an edge of the substrate by a first distance that is smaller than a second distance between the first side and the second side, and a plurality of openings penetrate through the lid to expose a space containing the semiconductor die.