US Pat. No. 10,461,297

LAMINATED BODY

SUMITOMO CHEMICAL COMPANY...

1. A laminated body, comprising:a porous base material containing a polyolefin-based resin as a main component; and
a porous layer on at least one surface of the porous base material, the porous layer containing a polyvinylidene fluoride-based resin,
the porous base material having a parameter X of not more than 20, the parameter X being calculated in accordance with a formula below, where MD tan ? represents a tan ? measured in a machine direction through a viscoelasticity measurement performed at a frequency of 10 Hz and a temperature of 90° C., and TD tan ? represents a tan ? measured in a transverse direction through the viscoelasticity measurement,
X=100×|MD tan ??TD tan ?|/{(MD tan ?+TD tan ?)/2}
the polyvinylidene fluoride-based resin containing crystal form ? in an amount of not less than 36 mol % with respect to 100 mol % of a total amount of the crystal form ? and crystal form ? contained in the polyvinylidene fluoride-based resin,
where the amount of the crystal form ? is calculated from an absorption intensity at around 765 cm?1 in an IR spectrum of the porous layer, and an amount of the crystal form ? is calculated from an absorption intensity at around 840 cm?1 in the IR spectrum of the porous layer.

US Pat. No. 10,461,291

CURRENT-INTERRUPT DEVICE FOR BATTERY CELL

Ford Global Technologies,...

1. A current-interrupt device for a battery cell, the current-interrupt comprising:a plate defining a hole;
a diaphragm joined to the plate and covering a top of the hole;
a cover sealing a bottom of the hole; and
a dielectric fluid disposed in the hole, wherein, the diaphragm and the cover are movable, responsive to cell pressure exceeding a threshold, separating the diaphragm from the plate forming a gap therebetween and releasing the fluid into the gap, and preventing current from arching across the gap.

US Pat. No. 10,461,283

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND REPAIR METHOD THEREOF

LG DISPLAY CO., LTD., Se...

1. A repair method of an organic light emitting display device including a plurality of pixels, each pixel among the plurality of pixels including an organic light emitting diode (OLED) in every pixel area defined as a plurality of scan lines and a plurality of data lines intersecting with each other, and the organic light emitting display device further including a repair structure in a horizontal direction by one or more repair lines between two or more adjacent pixels among the plurality of pixels, the repair method comprising:cutting a connection between a driving thin-film transistor (TFT) defective in operation and an anode electrode of an OLED of a first pixel among the two or more adjacent pixels;
repairing a source electrode of an in-defective driving TFT of a second pixel and the anode electrode of the OLED of the first pixel by welding the repair line and the source electrode of the driving TFT of the second pixel adjacent to the first pixel; and
operating the OLED of the first pixel through the in-defective driving TFT of the second pixel,
wherein the repair line extends from the end of the anode electrode of the OLED of the first pixel to overlap the source electrode of the driving TFT of the second pixel, and
wherein the repairing includes welding the repair line and the source electrode of the driving TFT of the second pixel to connect the repair line and the source electrode of the driving TFT of the second pixel.

US Pat. No. 10,461,278

LIGHT-EMITTING DEVICE, DISPLAY APPARATUS, AND ILLUMINATION APPARATUS

SONY CORPORATION, Tokyo ...

1. A light-emitting device comprising: a first electrode;a second electrode; and an organic layer that is provided between the first electrode and the second electrode and is formed by stacking a first light-emitting layer and a second light-emitting layer in order from the first electrode side,
wherein light emitted from the organic layer is reflected by a first reflective interface formed between the first light-emitting layer and the first electrode, passes through the second electrode, and is emitted to the outside of the light-emitting device,
a first light-transmitting layer, a second light-transmitting layer, and a third light-transmitting layer are provided on a side of the second light-emitting layer opposite to the first light-emitting layer in order from the second light-emitting layer side,
a second reflective interface is formed at an interface of the first light-transmitting layer on the second light-emitting layer side,
a third reflective interface is formed between the first light-transmitting layer and the second light-transmitting layer,
a fourth reflective interface is formed between the second light-transmitting layer and the third light-transmitting layer,
an interference filter is formed by the first reflective interface, the second reflective interface, the third reflective interface, and the fourth reflective interface,
the first reflective interface is arranged so as to satisfy a first condition, and
the second reflective interface, the third reflective interface, and the fourth reflective interface are arranged so as to satisfy either or both of a second condition and a third condition,
wherein the first condition is that reflection of light rays, which are emitted from the first light-emitting layer, on the first reflective interface is reinforced, and reflection of light rays, which are emitted from the second light-emitting layer, on the first reflective interface is reinforced,
wherein the second condition is that reflection of light rays, which are emitted from the first light-emitting layer, on the second reflective interface is weakened, reflection of light rays, which are emitted from the first light-emitting layer, on the third reflective interface is reinforced, and reflection of light rays, which are emitted from the first light-emitting layer, on the fourth reflective interface is reinforced, and
wherein the third condition is that reflection of light rays, which are emitted from the second light-emitting layer, on the second reflective interface is weakened, reflection of light rays, which are emitted from the second light-emitting layer, on the third reflective interface is reinforced, and reflection of light rays, which are emitted from the second light-emitting layer, on the fourth reflective interface is reinforced.

US Pat. No. 10,461,273

DISPLAY DEVICE HAVING A STRUCTURE TO PREVENT DAMAGE TO A BENT PORTION OF A FLEXIBLE DISPLAY

Japan Display Inc., Mina...

1. A display device comprising:a flexible display including a display region and a peripheral region arranged in a length direction, the flexible display being bent in the peripheral region around an axis extending in a width direction orthogonal to the length direction, the flexible display being provided with a light-emitting element layer in the display region; and
a spacer disposed inside a bend of the flexible display and including both end portions on both sides in the width direction, the spacer including a guide surface regulating the bend,
a first reinforcement film on the display region of the flexible display;
a second reinforcement film on the peripheral region of the flexible display;
a semiconductor circuit chip on the peripheral region; and
a flexible board on the peripheral region, wherein
the both end portions of the spacer project from the flexible display in the width direction,
a side end portion of the first reinforcement film is in contact with a first side end portion of the second reinforcement film,
a second side end portion of the second reinforcement film is in contact with one side of the semiconductor circuit chip,
a third side end portion of the second reinforcement film is in contact with another side of the semiconductor circuit chip,
the second reinforcement film is continuously formed from the first side end portion to the second side end portion, and
the first reinforcement film, the first side end portion, the second side end portion, the semiconductor circuit chip, the third side end portion, and the flexible board are arranged in this order along a surface of the flexible display.

US Pat. No. 10,461,272

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A method of manufacturing a display device, the method comprising:preparing a first substrate;
disposing a pixel defining layer on the first substrate, the pixel defining layer configured to define an emissive area and a transmissive area;
disposing a first electrode in the emissive area;
disposing an organic light emitting layer on the first electrode;
disposing a second electrode in the emissive area and the transmissive area;
disposing a mask on the second electrode and injecting a modifying agent; and
disposing a second substrate facing the first substrate,
wherein the mask has a blocking portion corresponding to the emissive area, a transmissive portion corresponding to the transmissive area, and a stopper disposed on a rear surface of the mask at a boundary between the blocking portion and the transmissive portion.

US Pat. No. 10,461,271

LIGHT-EMITTING ELEMENT, DISPLAY DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting element comprising:a pair of electrodes,
a first light-emitting layer; and
a second light-emitting layer,
wherein the first light-emitting layer comprises a first fluorescent material and a first host material,
wherein a second fluorescent material, a first organic compound and a second organic compound are mixed in the second light-emitting layer,
wherein a triplet excited energy level of the first host material is lower than a triplet excited energy level of the first fluorescent material,
wherein the triplet excited energy level of the first host material is lower than triplet excited energy levels of the first organic compound and the second organic compound, and
wherein light emitted from the light-emitting element comprises delayed fluorescence.

US Pat. No. 10,461,267

FLEXIBLE DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A flexible display panel comprising:a flexible substrate including a display area and a peripheral area outside of the display area;
a wire or an organic layer disposed over the flexible substrate;
a polarizer disposed over the flexible substrate;
a lower film under the flexible substrate; and
an acryl-based resin layer disposed in the peripheral area, not disposed in the display area, and having a curvature radius which is greater than a curvature radius of the wire or the organic layer overlapping the acryl-based resin layer in a first direction perpendicular to an upper surface of the flexible substrate,
wherein:
the peripheral area of the flexible substrate in which the acryl-based resin layer is disposed is bent along a first bending line towards a rear side of the display area,
the acryl-based resin layer overlaps the first bending line in the first direction,
a side surface of the acryl-based resin layer is in contact with a side surface of the polarizer, and
a bottom side of the lower film includes at least one depression.

US Pat. No. 10,461,264

ORGANIC ELECTROLUMINESCENT ELEMENT

IDEMITSU KOSAN CO., LTD.,...

1. An organic electroluminescence device comprising a pair of electrodes and an organic compound layer therebetween, the organic compound layer comprising an emitting layer comprising: a first material; a second material; and a third material, whereinsinglet energy EgS(H1) of the first material, singlet energy EgS(H2) of the second material, and singlet energy EgS(D) of the third material satisfy a relationship of numerical formulae (1) and (2) below,
the singlet energy EgS(H1) of the first material and the singlet energy EgS(H2) of the second material satisfy a relationship of numerical formula (8) below,
a difference ?ST(H1) between the singlet energy EgS(H1) of the first material and an energy gap Eg77K(H1) at 77K of the first material satisfies a relationship of a numerical formula (3) below, and
the third material is a fluorescent material,
EgS(H1)>EgS(D)  (1)
EgS(H2)>EgS(D)  (2)
?ST(H1)=EgS(H1)?Eg77K(H1)<0.3 [eV]  (3)
EgS(H2)?EgS(H1)  (8).

US Pat. No. 10,461,262

CONDENSED CYCLIC COMPOUND AND AN ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A condensed cyclic compound represented by Formula 1:
wherein, in Formulae 1 and 2,
X1 is N or C(R11), X2 is N or C(R12), and X3 is N or C(R13), and at least one of X1 to X3 is N;
L1 to L3 are each independently selected from a substituted or unsubstituted C3-C10 cycloalkylene, a substituted or unsubstituted C1-C10 heterocycloalkylene, a substituted or unsubstituted C3-C 10 cycloalkenylene, a substituted or unsubstituted C1-C10 heterocycloalkenylene, a substituted or unsubstituted C6-C60 arylene, a substituted or unsubstituted C1-C60 beteroarylene, a substituted or unsubstituted divalent non-aromatic condensed polycyclic group, or a substituted or unsubstituted divalent non-aromatic condensed heteropolycyclic group;
a1 to a3 are each independently an integer selected front 0 to 3, wherein, when a1 is 2 or greater, at least 2 or L1(s) are the same as or different from each other, when a2 is 2 or greater, at least 2 L2(s) are the same as or different from each other, and when a3 is 2 or greater, at least 2 L3(s) are the same as or different from each other;
Ar1 and Ar2 are each independently selected from a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C1 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted-C6-C60 aryl group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, or a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group;
one of R1 and R2 is a group represented by Formula 2 and the other of R1 and R2 is hydrogen;
R3, R4, R5 and R6 are each hydrogen;
R7, R8 and R11 to R13 are each independently selected from a group represented by Formula 2, hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C 10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, —Si(Q1)(Q2)(Q3), —N(Q1)(Q2), —B(Q1)(Q2),—C(?O)(Q1), —S(?O)2(Q1), or —P(?O)(Q1)(Q2);
R7 and R8 are optionally linked to form a saturated or unsaturated ring;
at least one of R1 or R2 is a group represented by Formula 2;
* indicates a binding site to a neighboring atom; and
at least one substituent of the substituted C3-C10 cycloalkylene group, substituted C1-C10 heterocycloalkylene group, substituted C3-C10 cycloalkenylene group, substituted C1-C10 heterocycloalkenylene group, substituted C6 -C60 arylene group, substituted C1-C60 heteroarylene group, a substituted divalent non-aromatic condensed polycyclic group, a substituted divalent non-aromatic condensed heteropolycyclic group, substituted C1-C60 alkyl group, substituted C2-C60 alkenyl group, substituted C2-C60 alkynyl group, substituted C1-C60 alkoxy group, substituted C3-C10 cycloalkyl group, substituted C1-C10 heterocycloalkyl group, substituted C3-C10 cycloalkenyl group, substituted C1-C10 heterocycloalkenyl group, substituted C6-C60 aryl group, substituted C6-C60 aryloxy group, substituted C6-C60 arylthio group, substituted C1-C60 heteroaryl group, substituted monovalent non-aromatic condensed polycyclic group, or substituted monovalent non-aromatic condensed heteropolycyclic group is selected from:
deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, or a C1-C60 alkoxy group;
a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a C3-C 10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6 -C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —Si(Q11)(Q12)(Q13),—N(Q11)(Q12), —B(Q11)(Q12), —C(?O)(Q11), —S(?O)2(Q11), and —P(?O)(Q11)(Q12);
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6 -C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, a biphenyl group, or a terphenyl group;
a C3-C10 cycloalkyl group. a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6 C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, 13 Si(Q21)(Q22)(Q23), —N(Q21)(Q22), —B(Q21)(Q22), —C(?O)(Q21), —S(?O)2(Q21), and —P(?O)(Q21)(Q22); or
—Si(Q31)(Q32)(Q33), —N (Q31)(Q32), —B(Q31)(Q32), —C(?O)(Q31), —S(?O)2(Q31), or —P(?O)(Q31)(Q32),
wherein Q1 to Q3, Q11 to Q13, Q21 to Q23, and Q31 to Q33 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10cycloalkenyl group, a C1-C60 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryl group substituted with a C1-C60 alkyl group, a C6-C60 aryl group substituted with a C6-C60 aryl group, a terphenyl group, a C1-C60 heteroaryl group, a C1-C60 heteroaryl group substituted with a C1-C60 alkyl group, a C1-C60 heteroaryl group substituted with a C6-C60 aryl group, a monovalent non-aromatic condensed polycyclic group, or a monovalent non-aromatic condensed heteropolycyclic group.

US Pat. No. 10,461,260

ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES

Universal Display Corpora...

1. A first device comprising a first organic light emitting device, the first organic light emitting device comprising:an anode;
a cathode; and
an emissive layer, disposed between the anode and the cathode, wherein the emissive layer comprises a first light emitting compound having a structure according to Formula 1:

wherein Rf is hydrogen and Ra to Re, Rg, R1 and R2 are independently selected from the group consisting of hydrogen, deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carbonyl, carboxylic acids, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof; and
wherein Ar1 is

wherein Ar2 and Ar3 are independently substituted or unsubstituted aryl or heteroaryl, and Ar1, Ar2, and Ar3 are not connected to one another to form fused ring(s),
wherein L is a direct bond or a linker;
wherein the first light emitting compound emits a luminescent radiation at room temperature when a voltage is applied across the organic light emitting device; and
wherein the luminescent radiation comprises a delayed fluorescence process.

US Pat. No. 10,461,258

COMPOUND

IDEMITSU KOSAN CO., LTD.,...

1. A compound represented by the following formula (1):
wherein in the formula (1), Xs are independently a nitrogen atom or CH, and at least two Xs are nitrogen atoms;
Ar1 and Ar2 are independently a substituted or unsubstituted aromatic hydrocarbon group including 6 to 30 ring carbon atoms or a substituted or unsubstituted aromatic heterocyclic group including 5 to 30 ring atoms;
L1 and L2 are independently a single bond or a substituted or unsubstituted aromatic hydrocarbon group including 6 to 30 ring carbon atoms;
Ar3 is a substituted or unsubstituted aromatic hydrocarbon group including 6 to 15 ring carbon atoms;
Ar4 is a substituted or unsubstituted 6-membered nitrogen-containing aromatic monocyclic group or a substituted or unsubstituted nitrogen-containing aromatic fused ring group in which two or more 6-membered rings are fused; and
Ar5 is represented by any of the following formulas (11) to (13):

wherein in the formula (11), any one of A1 to A12 is a carbon atom that is used for bonding with Ar3, any two of A1 to A12 that are not used for bonding with Ar3 are CR1s, the two R1s are bonded with each other to form a substituted or unsubstituted 6-membered ring, and remaining A1 to A12 are independently a nitrogen atom or CR2; and
R2 is a hydrogen atom or a substituent;
wherein in the formula (12), any one of A21 to A32 is a carbon atom that is used for bonding with Ar3, any two of A21 to A32 that are not used for bonding with Ar3 are CR1s, the two R1s are bonded with each other to form a substituted or unsubstituted 6-membered ring, and remaining A21 to A32 are independently a nitrogen atom or CR2; and
wherein in the formula (13), any one of A41 to A52 is a carbon atom that is used for bonding with Ar3, any two of A41 to A52 that are not used for bonding with Ar3 are CR1s, the two R1s are bonded with each other to form a substituted or unsubstituted 6-membered ring, and remaining A41 to A52 are independently a nitrogen atom or CR2.

US Pat. No. 10,461,257

ANTHRACENE DERIVATIVES, LUMINESCENT MATERIALS AND ORGANIC ELECTROLUMINESCENT DEVICES

IDEMITSU KOSAN CO., LTD.,...

1. An anthracene derivative comprising a phenanthryl group, the anthracene derivative being represented by formula (1-1):
wherein:
L1 represents a single bond in formula (1-1),
Ar1 represents a group represented by formula (2):

or a substituted or unsubstituted fused aromatic ring group having 10 to 50 ring-forming carbon atoms,
wherein the phenanthryl group is bound to the anthracene group of formula (1-1) via a 3 position or 4 position of the phenanthryl group, and wherein when Ar1 represents a group other than a group represented by the above-mentioned general formula (2), and a 3-position of the phenanthryl group is bonded to the anthracene skeleton, Ar1 represents a group other than an unsubstituted 3-phenanthryl group;
wherein substituents Rx, Ra, and Rb each independently represent a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkenyl group having 2 to 50 carbon atoms, a substituted or unsubstituted alkynyl group having 2 to 50 carbon atoms, a substituted or unsubstituted aralkyl group having 7 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 20 carbon atoms, a substituted or unsubstituted alkoxyl group having 1 to 20 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 20 ring-forming carbon atoms, a substituted or unsubstituted aryl group having 6 to 50 ring-forming carbon atoms, a substituted or unsubstituted heteroaryl group having 5 to 50 ring-forming atoms, a substituted or unsubstituted alkylsilyl group having 1 to 30 carbon atoms, a substituted or unsubstituted arylsilyl group having 6 to 50 ring-forming carbon atoms, a substituted or unsubstituted alkylgermanium group having 1 to 50 carbon atoms, or a substituted or unsubstituted arylgermanium group having 6 to 50 ring-forming carbon atoms;
“p” represents an integer of 0 to 8, “q” represents an integer of 0 to 9, and “y” represents an integer of 0 to 4, and when “p” represents 2 to 8, “q” represents 2 to 9, or “y” represents 2 to 4, a plurality of Rx's a plurality of Ra's, or a plurality of Rb's may be identical to or different from each other, provided that a case where all Rx, Ra, and Rb each represent an anthracenyl group is excluded; and
Arz represents a substituent selected from the group consisting of a substituted or unsubstituted naphthyl group, a substituted or unsubstituted phenanthryl group, a substituted or unsubstituted anthracenyl group, a substituted or unsubstituted benzanthracenyl group, a substituted or unsubstituted naphthacenyl group, a substituted or unsubstituted fluoranthenyl group, a substituted or unsubstituted benzofluoranthenyl group, a substituted or unsubstituted triphenylenyl group, a substituted or unsubstituted chrysenyl group, a substituted or unsubstituted pyrenyl group, a substituted or unsubstituted benzophenanthryl group, a substituted or unsubstituted benzochrysenyl group, and a substituted or unsubstituted heterocycle-containing group having 3 to 50 nucleus forming atoms, when Arz has a plurality of substituents, a plurality of adjacent substituents may be bonded to each other to form in a saturated or unsaturated divalent group that completes a ring.

US Pat. No. 10,461,254

METHODS OF GRAPHENE GROWTH AND RELATED STRUCTURES

Taiwan Semiconductor Manu...

1. A device, comprising:a substrate having a first surface that includes a curved region;
a conformal graphene layer disposed over the substrate, wherein the conformal graphene layer includes a second surface that follows a first surface contour of the curved region to provide a curved graphene layer within the curved region; and
a source/drain electrode in contact with the conformal graphene layer outside the curved region.

US Pat. No. 10,461,251

METHOD OF MANUFACTURING INTEGRATED CIRCUIT USING ENCAPSULATION DURING AN ETCH PROCESS

EVERSPIN TECHNOLOGIES, IN...

1. A method of fabricating a magnetoresistive bit from a magnetoresistive stack including (i) a first magnetic region, (ii) an intermediate region disposed over the first magnetic region, and (iii) a second magnetic region disposed over the intermediate region, the method comprising:etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls, wherein at least a portion of the sidewalls includes redeposited material after the etching;
modifying at least a portion of the redeposited material on the sidewalls, wherein the modifying step includes rendering at least a portion of the redeposited material on the sidewalls electrically-nonconductive; and
etching through a second portion of the magnetoresistive stack after the modifying step.

US Pat. No. 10,461,243

TUNING MAGNETIC ANISOTROPY FOR SPIN-TORQUE MEMORY

Everspin Technologies, In...

13. A magnetoresistive device, comprising:a fixed portion, wherein a magnetic state for the fixed portion is in a predetermined state;
a free portion, wherein the free portion includes:
a first magnetic layer having a first perpendicular magnetic anisotropy field parameter, wherein the first perpendicular magnetic anisotropy field parameter corresponds to a first magnetic field that is required to move a magnetic state of the first magnetic layer from a position along an easy axis of the first magnetic layer to a position perpendicular to the easy axis of the first magnetic layer;
a second magnetic layer having second perpendicular magnetic anisotropy field parameter, wherein the second perpendicular magnetic anisotropy field parameter corresponds to a second magnetic field that is required to move a magnetic state of the second magnetic layer from a position along an easy axis of the second magnetic layer to a position perpendicular to the easy axis of the second magnetic layer, wherein the second magnetic layer is more susceptible to changes in magnetic state in response to a spin-torque switching current than the first magnetic layer; and
a coupling layer between the first magnetic layer and the second magnetic layer; and
a first dielectric layer adjacent the second magnetic layer, wherein the first dielectric layer is between the fixed portion and the free portion.

US Pat. No. 10,461,239

MICROSCALE SENSOR STRUCTURE WITH BACKSIDE CONTACTS AND PACKAGING OF THE SAME

INTERDISCIPLINARY CONSULT...

1. A microscale sensor comprising: a device layer having a front side and a back side, the front side of the device layer being positioned for exposure to a passing fluid; a support substrate at the back side of the device layer, the support substrate having contact openings for accessing a conductive backside surface at the back side of the device layer, wherein electrical connection to the device layer is not formed with a through-wafer via; and wherein the microscale sensor is configured to be flush mounted.

US Pat. No. 10,461,237

THERMOELECTRIC DEVICE

Mahle International GmbH,...

1. A thermoelectric device, comprising:a plurality of electrically conductive first threads and a plurality of electrically insulating second threads structured and arranged to define a fabric;
at least one first thread of the plurality of electrically conductive first threads including a plurality of p-doped thread sections and a plurality of n-doped thread sections arranged in alternating relationship with one another; and
the plurality of electrically conductive first threads extending in a wavy course defining a plurality of curvature-turning points;
wherein the plurality of p-doped thread sections and the plurality of n-doped thread sections are arranged in a respective curvature-turning point of the plurality of curvature-turning points; wherein one of: the plurality of electrically conductive first threads are arranged as warp threads of the fabric, and the plurality of electrically insulating second threads are arranged as weft threads of the fabric; and the plurality of electrically conductive first threads are arranged as the weft threads of the fabric, and the plurality of electrically insulating second threads are arranged as the warp threads of the fabric.

US Pat. No. 10,461,230

LIGHT EMITTING DIODE COMPONENT

Koninklijke Philips N.V.,...

1. A method, comprising:providing a light emitting semiconductor structure grown on a growth substrate;
removing at least a portion of the growth substrate; and
forming a multilayer structure arranged to guide light out from a surface of the light emitting semiconductor structure, the multilayer structure covering the surface of the light emitting structure, the multilayer structure comprising a plurality of layers, wherein an i+1:th layer is arranged on top an i:th layer in a sequence as seen from the light emitting semiconductor structure, wherein a refractive index, ni, of the i:th layer is greater than a refractive index, ni+1, of the i+1:th layer, wherein the value of i is selected from the set of positive integers, wherein a thickness of the i+1:th layer is greater than a thickness of the i:th layer.

US Pat. No. 10,461,220

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

IMEC, Leuven (BE)

1. A method of fabricating a light-emitting semiconductor device, the method comprising:providing a light-emitting layer stack;
forming a stop layer over the light-emitting layer stack;
forming a light-transmission layer on the stop layer, the light-transmission layer formed of a crystalline III-V semiconductor material that is optically transmissive to emission wavelengths of the light-emitting layer stack;
patterning a mask layer on the light-transmission layer such that portions of the light-transmission layer are exposed;
thermally texturing in an atmosphere comprising molecular hydrogen (H2) and ammonia, the thermally texturing comprises decomposing the light-transmission layer at the exposed portions into chemical constituents of the III-V semiconductor material and redepositing to form a plurality of crystals of the III-V semiconductor material having triangular crystal facets; and
stopping the thermal texturing by locally stopping the decomposing and redepositing at an interface formed by the stop layer and the light-transmission layer,
wherein the stop layer has a decomposition temperature that is higher than that of the light-transmission layer such that texturing is prevented from extending into the stop layer.

US Pat. No. 10,461,218

SEMICONDUCTOR DEVICE

LG INNOTEK CO., LTD., Se...

1. A semiconductor device comprising:a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, and a plurality of recesses through which a lower portion of the first conductive semiconductor layer is exposed;
at least one pad arranged outside the light emitting structure, and arranged to be adjacent to at least one edge; and
a plurality of insulation patterns arranged inside the recesses and extending to a lower surface of the light emitting structure,
wherein widths of the plurality of insulation patterns are reduced as the insulation patterns become further away from the pad,
wherein the pad includes a first pad arranged to be adjacent to a first edge and a second pad arranged to be adjacent to a second edge, and
wherein widths of the plurality of insulation patterns are reduced as the insulation patterns go from the first edge toward a third edge in a diagonal direction.

US Pat. No. 10,461,210

METHOD FOR MANUFACTURING A DETECTION DEVICE WITH TWO SUBSTRATES AND SUCH A DETECTION DEVICE

1. A method for manufacturing a device for detecting electromagnetic radiation, the method including the following steps:supplying a first substrate, the first substrate integrating a reading circuit and comprising a first surface and a second surface, the first substrate further including at least two first contact plugs connected to the reading circuit and at least one first annular bonding element surrounding the first contact plugs, the first contact plugs and the first annular bonding element each being at least in part exposed on the first surface of the first substrate,
supplying a second substrate, the second substrate including:
a first surface of the second substrate and a second surface of the second substrate,
at least one detection structure, for the detection of electromagnetic radiation, provided with at least two connecting arms each extending by a second contact plug complementary to one corresponding first contact plug,
a sacrificial material enclosing the detection structure, the first connecting arm and the second connecting arm,
a cap including the first surface of the second substrate,
at least one annular side wall extending from the cap, the annular side wall forming with the cap a cavity housing the detection structure and the sacrificial material, the annular side wall being provided, on one end opposite to the cap, with a second annular bonding element complementary to the first annular bonding element,
wherein the second contact plugs and the second annular bonding element are each at least in part exposed on the second surface of the second substrate,
bonding the second surface of the second substrate on the first surface of the first substrate by bonding the second annular bonding element on the first annular bonding element and bonding the first contact plugs on the second contact plugs,
arranging at least one opening in the second substrate,
selective elimination of the sacrificial material,
closing said opening under at least a primary vacuum whereby the device for detecting electromagnetic radiation is formed.

US Pat. No. 10,461,209

AVALANCHE PHOTODIODE FOR DETECTING ULTRAVIOLET RADIATION AND MANUFACTURING METHOD THEREOF

STMICROELECTRONICS S.R.L....

1. An avalanche photodiode for detecting ultraviolet radiation, comprising:a semiconductor body having a front surface and forms including:
a silicon carbide substrate having a first type of conductivity at a first dopant level;
a first silicon carbide epitaxial layer having the first type of conductivity at a second dopant level less than the first dopant level;
a second silicon carbide epitaxial layer having a third dopant level between the first and second dopant levels, the first silicon carbide epitaxial layer being positioned between the silicon carbide substrate and the second silicon carbide epitaxial layer, at least a portion of the second silicon carbide epitaxial layer being a cathode region; and
a third silicon carbide epitaxial layer on the second silicon carbide epitaxial layer and having a fourth dopant level less than the third dopant level;
an anode region extending completely through the third silicon carbide epitaxial layer and having a second type of conductivity, which extends into said semiconductor body starting from the front surface and contacts the cathode region; and
a guard ring having the second type of conductivity, which extends into said semiconductor body starting from the front surface and completely laterally surrounds the anode region.

US Pat. No. 10,461,207

PHOTOVOLTAIC DEVICES AND METHOD OF MANUFACTURING

First Solar, Inc., Tempe...

1. A photovoltaic device comprising:a substrate;
a transparent conductive oxide (TCO) layer formed on the substrate;
a back contact;
a CdSeTe absorber layer formed between the TCO layer and the back contact, wherein:
the CdSeTe absorber layer contacts the back contact,
the CdSeTe absorber layer is composed of cadmium, selenium, and tellurium in varying amounts,
a ratio of Te atoms to a sum of Se atoms and the Te atoms throughout the CdSeTe absorber layer compound is between about 99 to 100 and about 60 to 100; and
a buffer layer formed between the TCO layer and the CdSeTe absorber layer,
and wherein the buffer layer comprises magnesium,
and wherein a peak concentration of Se is located at an interface between the buffer layer and the CdSeTe absorber layer.

US Pat. No. 10,461,205

SOLAR PANEL HOUSING

1. A housing for a solar panel comprising:a glazed element; and
a tray; said tray including:
a plate;
a pair of side walls extending generally vertical from said plate and from opposing ends of said plate, said pair of side walls include at least one first aperture, said at least one first aperture configured to allow passage of a tube or conduit;
a top end cap extending generally vertical from said plate;
a bottom end cap extending generally vertical from said plate at an opposite end from said top end cap;
a top surface of said pair of side walls, said top end cap and said bottom end cap;
a lip, said lip positioned proximate a junction of said top surface of said pair of side walls, said top end cap and said bottom end cap and an interior wall of said pair of side walls, said top end cap and said bottom end cap, said lip including a seating surface that is positioned below said top surface of said pair of side walls, said top end cap and said bottom end cap, said lip extending the interior perimeter of each of said pair of side walls, said top end cap and said bottom end cap, and said lip configured to seat said glazed element such that a top surface of said glazed element is flush to said top surface of said pair of side walls, said top end cap and said bottom end cap;
wherein said plate, said pair of side walls, said top end cap, said bottom end cap, said top surface of said pair of side walls, said top end cap and said bottom end cap and said lip are formed of a single material and as a single integral component; and
wherein said plate, said pair of side walls, said top end cap and said bottom end cap collectively form a cavity; and
wherein said top end cap includes a top header, said top header extending the length of said top end cap, said top header extending outward from said top end cap and in a direction away from said cavity, said top header including:
at least one pipe extending outwardly from said top header at both ends of said top header and extending the length of said top header and throughout an interior space of said top header;
at least one void extending the length of said top header and throughout the interior space of said top header, said void positioned proximate the exterior of said pipe and distinct from said pipe; and
at least one hole extending from said void through said top end cap to said cavity.

US Pat. No. 10,461,201

HIGHLY-FLUORESCENT AND PHOTO-STABLE CHROMOPHORES FOR WAVELENGTH CONVERSION

Nitto Denko Corporation, ...

1. A chromophore represented by formula (I):
wherein:
each L is independently C1-8 alkyl or C6-10 aryl;
D1 is selected from the group consisting of:
(1) hydrogen;
(2) C6-10 aryl, substituted by C1-6 alkoxy;
(3) C6-10 aryl-NR?R?; and
(4) C6-10 aryl-C6-10 aryl-NR?R?;
D2 is selected from the group consisting of:
(1) hydrogen;
(2) C6-10 aryl, substituted by C1-6 alkoxy;
(3) C6-10 aryl-NR?R?; and
(4) C6-10 aryl-C6-10 aryl-NR?R?;
R? is C1-8 alkyl or C6-10 aryl, wherein the C6-10 aryl is optionally substituted by C1-8 alkyl, C1-6 alkoxy or —C(?O)R; or
R?, together with the C6-10 aryl to which the nitrogen atom is attached to, forms a fused C1-8 heterocyclic ring comprising nitrogen;
R? is C1-8 alkyl or C6-10 aryl, wherein the C6-10 aryl is optionally substituted by C1-8 alkyl, C1-6 alkoxy or —C(?O)R; or
R?, together with the C6-10 aryl to which the nitrogen atom is attached to, forms a fused C1-8 heterocyclic ring comprising nitrogen; or
R? and R?, together with the C6-10 aryl to which the nitrogen atom is attached to, forms a fused C1-8 heterocyclic ring comprising nitrogen;
Het is selected from the group consisting of:

X is —N(A0)-;
A0 is selected from the group consisting of:
(1) hydrogen;
(2) C1-8 alkyl, optionally substituted by halo or C1-6 alkoxy;
(3) C2-8 alkenyl, optionally substituted by halo, C1-8 alkyl or C1-6 alkoxy;
(4) C1-6 alkoxy, optionally substituted by halo; and
(5) C6-10 aryl, optionally substituted by halo, C1-8 alkyl or C1-6 alkoxy;
Ra is selected from the group consisting of:
(1) hydrogen;
(2) C1-8 alkyl, optionally substituted by:
(a) halo;
(b) CN;
(c) C1-6 alkoxy;
(d) C6-10 aryloxy, optionally substituted by CN or —C(?O)R;
(e) C3-10 cycloalkyl; or
(f) C6-10 aryl, optionally substituted by halo or CN;
(3) C6-10 aryl, optionally substituted by:
(a) halo;
(b) CN;
(c) C1-8 alkyl;
(d) C1-6 alkoxy; or
(e) C(?O)R; and
(4) C6-10 heteroaryl, optionally substituted by:
(a) halo;
(b) CN; or
(c) C1-8 alkyl;
wherein the C6-10 heteroaryl contains one or more nitrogen heteroatoms;
Rb is selected from the group consisting of:
(1) hydrogen;
(2) C1-8 alkyl, optionally substituted by:
(a) halo;
(b) CN;
(c) C1-6 alkoxy;
(d) C6-10 aryloxy, optionally substituted by CN or —C(?O)R;
(e) C3-10 cycloalkyl; or
(f) C6-10 aryl, optionally substituted by halo or CN;
(3) C6-10 aryl, optionally substituted by:
(a) halo;
(b) CN;
(c) C1-8 alkyl;
(d) C1-6 alkoxy; or
(e) C(?O)R; and
(4) C6-10 heteroaryl, optionally substituted by:
(a) halo;
(b) CN; or
(c) C1-8 alkyl;
wherein the C6-10 heteroaryl contains one or more nitrogen heteroatoms; or
Ra and Rb, together with the carbon atoms to which they are attached, form a monocyclic ring or a polycyclic ring system selected from the group consisting of:
C3-10 cycloalkyl, C6-10 aryl,

wherein the monocyclic ring or polycyclic ring system is optionally substituted by:
(a) halo;
(b) C1-8 alkyl;
(c) C1-6 alkoxy; or
(d) C6-10 aryl, optionally substituted by C1-6 alkoxy;
each R is independently C1-8 alkyl, C1-6 alkoxy or C6-10 aryl, wherein the C6-10 aryl is optionally substituted by C1-8 alkyl; and
i is 0;
with the proviso that D1 and D2 are not both hydrogen.

US Pat. No. 10,461,198

THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE

INDUSTRY-UNIVERSITY COOPE...

1. A method for manufacturing a thin film transistor substrate comprising:forming a first protection film on a base substrate, the first protection film comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer which are sequentially stacked;
after forming the first protection film, forming an oxide semiconductor layer on the first protection film;
forming source and drain electrodes provided at a predetermined interval from each other and connected with the oxide semiconductor layer;
forming a gate electrode insulated from the oxide semiconductor layer and partially overlapped with at least one portion of the oxide semiconductor layer; and
performing a thermal treatment at less than 350° C.,
wherein the oxide semiconductor layer has a hydrogen content of 2.4 at % (atomic % or atom %)˜2.6 at %.

US Pat. No. 10,461,196

CONTROL OF LENGTH IN GATE REGION DURING PROCESSING OF VFET STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a vertical FinFET, the method comprising:forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof;
laterally recessing the semiconductor fin causing the fin mask to overhang above the fin;
forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner;
forming a gate mask laterally adjacent to the second portion of the conformal gate liner;
removing the first portion of the conformal gate liner, wherein the second portion of the conformal gate liner remains intact after the removing of the first portion;
removing the gate mask to expose the remaining second portion of the conformal gate liner;
forming a nitride liner on the remaining second portion of the conformal gate liner, exposed portion of the semiconductor fin above the second portion of the conformal gate liner, and the fin mask, after removing the gate mask to expose the remaining second portion of the conformal gate liner;
forming an intermediate mask on a portion of the nitride liner that is above the fin mask to vertically cover a vertical section of the first portion of the conformal gate liner adjacent to the recessed semiconductor fin and the nitride liner on top thereof;
applying a directional etching to remove portions of the conformal gate liner and the nitride liner on top thereof, that are above the substrate and not vertically covered by the intermediate mask;
removing the intermediate mask; and
forming a gate contact to the remaining second portion of the conformal gate liner, wherein a length of the gate is determined by the remaining second portion of the conformal gate liner.

US Pat. No. 10,461,193

APPARATUS AND METHODS TO CREATE A BUFFER WHICH EXTENDS INTO A GATED REGION OF A TRANSISTOR

Intel Corporation, Santa...

1. A microelectronic structure, comprising:a substrate;
a low band-gap active channel;
a high band-gap sub-structure disposed between the substrate and the low band-gap active channel, wherein the high band-gap sub-structure abuts the low band-gap active channel;
at least one isolation structure abutting the high band-gap sub-structure, wherein a portion of the high band-gap sub-structure extends from the at least one isolation structure and wherein another portion of the high band-gap sub-structure extends into the substrate;
a gated region comprising the low band-gap active channel and the portion of the high band-gap sub-structure extending from the at least one isolation structure; and
a gate on the gated region, wherein the gate comprises a gate dielectric layer and a gate electrode, and wherein the gate dielectric layer contacts both the low band-gap active channel and the portion of the high band-gap sub-structure extending from the at least one isolation structure.

US Pat. No. 10,461,192

METAL OXIDE PROTECTION STRUCTURE OF A SEMICONDUCTOR DEVICE

Samsung Display Co., Ltd....

1. A semiconductor device comprising:a gate electrode disposed on a substrate;
a gate insulation layer disposed on the substrate to cover the gate electrode;
an active layer disposed on the gate insulation layer, the active layer comprising an oxide semiconductor;
an insulating interlayer disposed on the gate insulation layer and configured to cover the active layer;
a protection structure disposed on the insulating interlayer; and
a source electrode and a drain electrode disposed on the protection structure, the source electrode and the drain electrode contacting a source region and a drain region of the active layer, respectively,
wherein:
the protection structure comprises a first metal oxide layer disposed on the insulating interlayer, and a second metal oxide layer disposed on the first metal oxide layer;
the first metal oxide layer has a first oxygen content greater than a second oxygen content of the second metal oxide layer;
the second oxygen content abruptly varies from the first oxygen content at an interface between the first metal oxide layer and the second metal oxide layer;
the first metal oxide layer has a first composition of MOx1 (where M represents aluminum, titanium, tantalum or zirconium, O denotes oxygen, and x means a positive real number) having a first oxygen content, and the second metal oxide layer has a second composition of MOx2 having a second oxygen content; and
a thickness ratio between the first metal oxide layer and the second metal oxide layer is in a range of about 1.0:0.03 to 1.0:0.6.

US Pat. No. 10,461,187

INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. An integrated circuit device comprising:a substrate comprising a main surface;
a transistor (TR) comprising a first section, a vertical channel region, and a second section on the main surface; and
a gate electrode on the vertical channel region,
wherein the first section, the vertical channel region, and the second section extend from the main surface in a first direction perpendicular to the main surface, wherein the vertical channel region and the first and second sections have the same composition as each other and have different crystal phases from each other, and wherein the vertical channel region has a first width in a second direction parallel to the main surface and the first section has a second width in the second direction, the first width being narrower than the second width.

US Pat. No. 10,461,184

TRANSISTOR HAVING REDUCED GATE-INDUCED DRAIN-LEAKAGE CURRENT

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming a semiconductor fin that extends vertically from a first source or drain (S/D) region of the semiconductor device, the semiconductor fin comprising a first type of semiconductor material having a first band gap;
converting an upper portion of the semiconductor fin into a second semiconductor material having a second band gap that is greater than the first band gap; and
forming a second S/D region on the second semiconductor material so that the second semiconductor material is interposed between a non-converted portion of the semiconductor fin and the second S/D region.

US Pat. No. 10,461,180

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a first conductivity type drift region formed on a semiconductor substrate;
a gate trench portion provided reaching from an upper surface of the semiconductor substrate to an inner part of the semiconductor substrate and provided extending in a predetermined extending direction from the upper surface;
a first mesa portion being in direct contact with one of two side walls of the gate trench portion;
a second mesa portion being in direct contact with an opposite side of the one of two side walls of the gate trench portion;
a first conductivity type accumulation region having doping concentration higher than that in the drift region, which is provided being in direct contact with the gate trench portion above the drift region;
a second conductivity type base region provided being in direct contact with the gate trench portion above the accumulation region;
a first conductivity type emitter region having doping concentration higher than that in the drift region, which is provided on the upper surface of the semiconductor substrate such that it is in direct contact with the one of two side walls of the gate trench portion in at least the first mesa portion; and
an electrically floating second conductivity type floating region provided below the base region in the second mesa portion and at a position shallower than a bottom of the gate trench portion.

US Pat. No. 10,461,179

DEVICES HAVING A SEMICONDUCTOR MATERIAL THAT IS SEMIMETAL IN BULK AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming an isolation region in a substrate, wherein the isolation region is between a first and second region of the substrate, and wherein at least a portion of the isolation region is configured to extend from a top surface of the substrate;
forming a first highly doped source/drain contact region in the first region of the substrate and a second highly doped source/drain contact region in the second region of the substrate;
forming a first gate electrode over the first highly doped source/drain contact region;
forming a second gate electrode over the second highly doped source/drain contact region;
forming a first opening through the first gate electrode and to the first highly doped source/drain contact region;
forming a second opening through the second gate electrode and to the second highly doped source/drain contact region;
depositing a first bismuth-containing semiconductor material in the first opening to form a first bismuth-containing channel structure, the first bismuth-containing channel structure being connected to the first highly doped source/drain contact region;
depositing a second bismuth-containing semiconductor material in the second opening to form a second bismuth-containing channel structure, the second bismuth-containing channel structure being connected to the second highly doped source/drain contact region;
forming a third source/drain contact region over and connected to the first bismuth-containing channel structure;
forming a fourth source/drain contact region over and connected to the second bismuth-containing channel structure;
forming a dielectric layer over the third source/drain contact region and the fourth source/drain contact region; and
crystallizing the first and second bismuth-containing semiconductor materials, the crystallizing comprising performing an anneal.

US Pat. No. 10,461,177

CONFINED EPITAXIAL REGIONS FOR SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING CONFINED EPITAXIAL REGIONS

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a semiconductor fin above and continuous with a semiconductor substrate, the semiconductor fin comprising a channel region having an uppermost surface;
an isolation structure above the semiconductor substrate and adjacent to lower portions of the semiconductor fin, wherein an upper portion of the semiconductor fin protrudes above an uppermost surface of the isolation structure;
epitaxial source or drain regions adjacent to the channel region in the upper portion of the semiconductor fin, wherein the epitaxial source or drain regions have substantially vertical sidewalls, and wherein the epitaxial source and drain regions do not extend laterally over the isolation structure, wherein the epitaxial source and drain regions have an uppermost surface above the uppermost surface of the channel of the semiconductor fin, and wherein the epitaxial source or drain regions have a bottom surface below the uppermost surface of the isolation structure; and
a gate electrode over the channel region of the semiconductor fin.

US Pat. No. 10,461,176

FINFET DEVICE INCLUDING A STEM REGION OF A FIN ELEMENT

TAIWAN SEMICONDUCTOR MANU...

1. A fin-type field effect transistor (finFET) device, comprising:a substrate;
a fin disposed on the substrate, wherein the fin includes a passive region, a stem region overlying the passive region, and an active region overlying the stem region, wherein the stem region has a first width and the active region has a second width, the first width being less than the second width; and wherein the stem region has a first composition and the active region has a second composition, the second composition being different than the first composition, and wherein the first composition is an oxide;
a gate structure disposed on the active region, the gate structure including a gate electrode physically contacting the first composition of oxide of the stem region; and
a source region and a drain region adjacent the gate structure, wherein the first composition of oxide of the stem region extends under a bottommost edge of at least one of the source region or the drain region.

US Pat. No. 10,461,174

VERTICAL FIELD EFFECT TRANSISTORS WITH SELF ALIGNED GATE AND SOURCE/DRAIN CONTACTS

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming a bottom source or drain (S/D) layer on a substrate;
forming a bottom spacer layer on the bottom S/D layer;
forming a vertical transistor channel on the bottom S/D layer, the vertical transistor channel passing through the bottom spacer layer;
forming a high-k metal gate layer on sides of the vertical transistor channel and above the bottom S/D layer;
forming a gate spacer on sides of the vertical transistor channel and on top of the high-k metal gate layer;
removing portions of the high-k metal gate layer with a timed etch;
covering the high-k metal gate layer, the vertical transistor channel and bottom S/D layer with an interlayer dielectric (ILD);
forming with a non-self-aligned contact (SAC) etch a bottom S/D recess through the ILD to expose the bottom S/D layer, the etch removing at least portion of the gate spacer and the high-k metal gate layer;
forming a bottom S/D contact spacer on sides of the bottom S/D recess; and
forming a bottom S/D contact in the bottom S/D recess.

US Pat. No. 10,461,167

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a first transistor on a substrate; and
a second transistor on the substrate,
wherein each of the first and second transistors includes,
a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and
a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns, wherein
the work function pattern of the first transistor includes a first work function metal layer,
the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer,
the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and
the first transistor has a threshold voltage less than that of the second transistor.

US Pat. No. 10,461,164

COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE

QUALCOMM Incorporated, S...

1. A compound semiconductor field effect transistor (FET), comprising:gallium nitride (GaN) and alloy material layers;
a pair of L-shaped contacts on the GaN and alloy material layers;
a pair of gate spacers between the pair of L-shaped contacts and on the GaN and alloy material layers, each of the pair of gate spacers contacting one of the pair of L-shaped contacts; and
a base gate between the pair of gate spacers and on the GaN and alloy material layers, in which the pair of L-shaped contacts is self-aligned with the base gate, and in which the pair of L-shaped contacts comprises a planar portion on a GaN cap layer of the GaN and alloy material layers and an orthogonal portion on the GaN cap layer and in contact with sidewalls of the pair of gate spacers, the orthogonal portion of the pair of L-shaped contacts extending toward a coplanar surface of the base gate and the pair of gate spacers, distal from the GaN cap layer of the GaN and alloy material layers.

US Pat. No. 10,461,163

THREE-DIMENSIONAL MEMORY DEVICE WITH THICKENED WORD LINES IN TERRACE REGION AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein each of the electrically conductive layers has a respective first thickness in a memory array region and a respective second thickness that is greater than the respective first thickness in a stepped terrace region;
memory stack structures located in the memory array region and vertically extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and
contact via structures located in the terrace region and contacting a respective one of the electrically conductive layers.

US Pat. No. 10,461,162

TRANSISTOR DEVICE

Nanya Technology Corporat...

1. A transistor device comprising:an active region surrounded by an isolation structure;
a gate structure disposed over the active region and the isolation structure, the gate structure comprising:
a body portion extending in a first direction;
a first head portion and a second head portion extending in a second direction perpendicular to the first direction, wherein the first head portion and the second head portion are disposed at two opposite ends of the body portion;
a pair of first wing portions disposed at two opposite sides of the body portion, wherein each of the first wing portions is in contact with the first head portion and the body portion; and
a pair of second wing portions disposed at two opposite sides of the body portion, wherein each of the second wing portions is in contact with the second head portion and the body portion; and
a source/drain disposed in the active region;
wherein the first head portion comprises a first side extending in the first direction, the body portion comprises a second side extending in the first direction, and the second head portion comprises a third side extending in the first direction;
wherein each of the first wing portions comprises a fourth side in contact with the first side of the first head portion and the second side of the body portion, and each of the second wing portions comprises a fifth side in contact with the third side of the second head portion and the second side of the body portion;
wherein the second side of the body portion and the fourth side of the first wing portion form a first included angle, the second side of the body portion and the fifth side of the second wing portion form a second included angle, and the first included angle and the second included angle are obtuse angles;
wherein the first included angle and the second included angle are between 130° and 165°, respectively.

US Pat. No. 10,461,161

GAN DEVICE WITH FLOATING FIELD PLATES

NAVITAS SEMICONDUCTOR, IN...

1. A semiconductor device comprising:a substrate including a transition layer that can form a two-dimensional electron gas;
a source electrode ohmically coupled to the transition layer;
a drain electrode ohmically coupled to the transition layer;
a gate stack formed on the transition layer; and
a field termination structure spaced apart from the transition layer and positioned between the gate stack and the drain electrode, wherein the field termination structure includes a source plate electrically connected to the source electrode and at least one capacitively coupled floating plate.

US Pat. No. 10,461,160

SEMICONDUCTING COMPONENT

INSTITUTT FOR ENERGITEKNI...

1. An electronic semiconductive device comprising at least one transparent, complete n- or p-type semiconductive metal hydride layer containing a semiconductive metal hydride having a chosen dopant; wherein said semiconductive metal hydride has a band gap in the range of 3 eV to 7 eV, and wherein said electronic semiconductive device does not comprise a silicon layer.

US Pat. No. 10,461,154

BOTTOM ISOLATION FOR NANOSHEET TRANSISTORS ON BULK SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A method of forming nanosheets comprising:providing at least two stacks of semiconductor material layers on a supporting bulk semiconductor substrate, wherein the at least two stacks of semiconductor material layers includes a sacrificial semiconductor layer of a first composition, and a nanosheet semiconductor layer of a second composition, and removing the sacrificial semiconductor layer to provide nanosheets composed of the nanosheet semiconductor layer;
forming a first undercut region filled with a first dielectric material extending from an opening into the supporting bulk semiconductor substrate underlying the semiconductor material layers of the at least two stacks of semiconductor material layers; and
forming a second undercut region into the supporting bulk semiconductor substrate filled with a second dielectric material from a side of the at least two stacks of semiconductor material layers that is opposite a side of the at least two stacks of semiconductor material layers at which the first undercut region is positioned, wherein the first and second dielectric materials provide an isolation region.

US Pat. No. 10,461,153

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor memory device comprising;a substrate including active regions;
word lines in the substrate, each of the word lines extending in a first direction parallel to an upper surface of the substrate;
bit line structures connected to the active regions, respectively, each of the bit line structures extending in a second direction crossing the first direction; and
spacer structures on sidewalls of respective ones of the bit line structures,
each of the spacer structures including a first spacer, a second spacer, and a third spacer,
the second spacer being disposed between the first spacer and the third spacer,
the second spacer including a void, and
a height of the second spacer being greater than a height of the void with respect to the upper surface of the substrate,
the second spacer filling a bottom portion of a gap region defined by the first spacer and the third spacer;
contact plugs between each of the bit line structures, the contact plugs being connected to the active regions, respectively;
connection pads on the contact plugs, respectively; and
a separation layer between each of the connection pads, wherein
a lowermost surface of the separation layer is higher than an uppermost surface of the second spacer with respect to the upper surface of the substrate,
an upper surface of the third spacer is lower than an upper surface of the first spacer with respect to the upper surface of the substrate,
an upper surface of the second spacer is lower than the upper surface of the third spacer with respect to the upper surface of the substrate, and
each of the spacer structures further includes a fourth spacer on a sidewall of the first spacer and on the upper surface of the second spacer.

US Pat. No. 10,461,152

RADIO FREQUENCY SWITCHES WITH AIR GAP STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising a substrate with at least one trench structure extending from a surface of the substrate to at least one airgap structure formed in a well region of the substrate and under at least one gate structure having a channel extending continuously into the well region, the at least one airgap devoid of a lining and which extends within the substrate to a junction formed by a source/drain region in the substrate of the at least one gate structure, and the at least one trench is capped with insulator material which seals the at least one airgap structure to prevent moisture from entering into the at least one airgap structure.

US Pat. No. 10,461,151

LOCALIZED STRAIN RELIEF FOR AN INTEGRATED CIRCUIT

Analog Devices Global, H...

1. An integrated circuit comprising:a semiconductor die;
one or more circuit components formed in a surface of the semiconductor die;
a protective layer deposited over the one or more circuit components in the semiconductor die;
a cap disposed over the one or more circuit components to protect the one or more circuit components, the cap mechanically coupled with the protective layer;
one or more trenches at least partially surrounding the one or more circuit components, the one or more trenches spaced apart by at least one gap;
a connecting line passing through the at least one gap to connect the one or more circuit components to another circuit component outside an area at least partially surrounded by the one or more trenches, the connecting line comprising at least one turn such that the connecting line is disposed along at least two different directions; and
an encapsulating material disposed over the cap and the protective layer.

US Pat. No. 10,461,150

SEMICONDUCTOR DEVICE

SOCIONEXT INC., Kanagawa...

1. A semiconductor device comprising:a substrate;
a first transistor formed on the substrate, and including a first impurity region of a first conductivity type, and a second impurity region of the first conductivity type;
a second transistor formed on the substrate, and including a third impurity region of the first conductivity type electrically connected to the second impurity region, and a fourth impurity region of the first conductivity type;
a power supply terminal electrically connected to the first impurity region;
a ground terminal electrically connected to the fourth impurity region;
a first guard ring of a second conductivity type different from the first conductivity type, formed on the substrate, surrounding the first transistor in a plan view, and electrically connected to the ground terminal; and
a second guard ring of the second conductivity type, formed on the substrate, surrounding the second transistor in a plan view, and electrically connected to the ground terminal,
wherein the first guard ring includes a first part having a longitudinal axis which extends in a first direction in the plan view,
wherein the second guard ring includes a second part having a longitudinal axis which extends in the first direction in the plan view, and
wherein a width of the second part along a second direction, which is perpendicular to the first direction, is narrower than a width of the first part along the second direction in a plan view.

US Pat. No. 10,461,147

SEMICONDUCTOR DEVICE FABRICATING METHOD AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:a lower electrode disposed on a substrate;
a first insulating film disposed on one portion of an upper surface of the lower electrode;
an upper electrode disposed on one portion of an upper surface of the first insulating film;
a second insulating film that covers the upper electrode, another portion of the upper surface of the first insulating film other than the one portion of the upper surface of the first insulating film and
covers another portion of the upper surface of the lower electrode other than the one portion of the upper surface of the lower electrode;
a first conductive portion formed in a first open portion of the second insulating film, the first open portion runs through the second insulating film and exposes the upper electrode, and the first conductive portion is electrically connected to the upper electrode; and
a second conductive portion formed in a second open portion of the second insulating film, the second open portion runs through the second insulating film and exposes the lower electrode, and the second conductive portion is electrically connected to the lower electrode;
wherein a material of the first insulating film is different from a material of the second insulating film and the second insulating film extends beyond the second open portion on the another portion of the upper surface of the lower electrode.

US Pat. No. 10,461,144

CIRCUIT FOR PREVENTING STATIC ELECTRICITY AND DISPLAY DEVICE HAVING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a display unit comprising a plurality of pixels in a display region;
a driving circuit in a non-display region, the driving circuit being configured to drive the display unit;
a first clock signal wire configured to transmit a first clock signal to the driving circuit; and
a first circuit in the non-display region,
wherein the first circuit comprises:
a transistor electrically coupled to the first clock signal wire through a conductive wire and comprising a source electrode, a drain electrode, and a gate electrode; and
a capacitor comprising a first electrode coupled to the source electrode and to the drain electrode of the transistor, and a second electrode,
wherein the conductive wire is coupled to the first clock signal wire through a first contact hole and coupled to the gate electrode, and
wherein the second electrode of the capacitor is configured to receive a fixed voltage so that the second electrode is set to a voltage of the fixed voltage.

US Pat. No. 10,461,142

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a base layer including a plurality of islands in which a pixel is disposed, and a plurality of bridges disposed around each of the plurality of islands;
an inorganic insulating layer disposed on the base layer and having an opening exposing a portion of the bridge;
an organic material layer covering the opening; and
a plurality of first wires disposed on a bridge of the plurality of bridges and electrically connected to the pixel,
wherein adjacent islands of the plurality of islands are connected to each other through at least the bridge of the plurality of bridges,
and the plurality of first wires are disposed on the organic material layer.

US Pat. No. 10,461,141

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...

1. A display device comprising:a substrate;
a buffer layer disposed on the substrate;
a first semiconductor layer of a first thin film transistor disposed on the buffer layer;
a gate insulating layer disposed on a channel region of the first semiconductor layer, on a source region of the first semiconductor layer, and on a drain region of the first semiconductor layer;
a first gate electrode disposed on the gate insulating layer over the channel region of the first semiconductor layer;
a first source electrode in direct contact with the source region of the first semiconductor layer, wherein the first source electrode is disposed on the gate insulating layer over the source region of the first semiconductor layer and contacts the source region of the first semiconductor layer via a first channel hole through the gate insulating layer;
a first drain electrode in direct contact with the drain region of the first semiconductor layer, wherein the first drain electrode is disposed on the gate insulating layer over the drain region of the first semiconductor layer and contacts the drain region of the first semiconductor layer via a second channel hole through the gate insulating layer;
a passivation layer disposed on the first gate electrode, the first source electrode, and the first drain electrode, wherein the passivation layer is in direct contact with the first semiconductor layer in a region between the first source electrode and the first gate electrode, and wherein the passivation layer is in direct contact with the first semiconductor layer in a region between the first gate electrode and the first drain electrode,
wherein the first gate electrode, the first source electrode, and the first drain electrode are in a same layer and comprise a same material.

US Pat. No. 10,461,140

LIGHT EMITTING DEVICE

Semiconductor Energy Labo...

1. A light emitting device comprising:a current control transistor;
a light emitting element;
a power supply line; and
a capacitor,
wherein one of a source and a drain of the current control transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the current control transistor is electrically connected to the light emitting element,
wherein a part of the power supply line is configured to function as one terminal of the capacitor,
wherein a part of a gate electrode of the current control transistor is configured to function as the other terminal of the capacitor,
wherein the current control transistor is driven in a saturation region, and
wherein the current control transistor has a channel conductance gd from 0 to 1×10?8 S.

US Pat. No. 10,461,139

LIGHT EMITTING DEVICE MANUFACTURING METHOD AND APPARATUS THEREOF

INT TECH CO., LTD., Hsin...

1. A method of manufacturing a light emitting device, comprising:providing a substrate;
forming a plurality of photosensitive bumps over the substrate;
forming a photosensitive layer over the plurality of photosensitive bumps;
forming a buffer layer between the photosensitive layer and the plurality of photosensitive bumps;
patterning the photosensitive layer to form a recess through the photosensitive layer to expose a surface;
disposing an organic emissive layer on the surface,
forming a metal containing layer over the organic emissive layer, and
removing the patterned photosensitive layer.

US Pat. No. 10,461,136

ORGANIC ELECTROLUMINESCENT DISPLAY PANEL WITH SEMICONDUCTOR LAYER, MANUFACTURING METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. An organic electroluminescent display panel comprising:a base substrate, a first electrode and a second electrode on the base substrate, and an organic light emitting layer located between the first electrode and the second electrode, wherein the first electrode is closer to the base substrate than the second electrode,
wherein the organic electroluminescent display panel further comprises a semiconductor layer covering the entire base substrate of the display panel, wherein the semiconductor layer is located between the organic light emitting layer and one of the first electrode and the second electrode,
wherein the semiconductor layer comprises a first portion and a second portion, an orthographic projection of the first portion of the semiconductor layer on the first electrode overlaps the first electrode, the second portion of the semiconductor layer covers a side surface of the first electrode, the side surface of the first electrode is crossed with a plane where the base substrate is located, and the first portion of the semiconductor layer and the second portion of the semiconductor layer are integral.

US Pat. No. 10,461,134

LIGHT-EMITTING DEVICE AND DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a first light-emitting element comprising:
a first electrode that is reflective;
a first light-emitting layer;
a second light-emitting layer over the first light-emitting layer; and
a second electrode;
a second light-emitting element comprising:
a third electrode that is reflective;
the first light-emitting layer;
the second light-emitting layer over the first light-emitting layer; and
the second electrode;
a first color filter overlapping with the first light-emitting element and having a first central wavelength of a first wavelength range in which the first color filter has a transmittance of 50% or higher in a visible wavelength range; and
a second color filter overlapping with the second light-emitting element and having a second central wavelength of a second wavelength range in which the second color filter has a transmittance of 50% or higher in the visible light range,
wherein the first wavelength range is different from the second wavelength range,
wherein the first central wavelength is different from the second central wavelength, and
wherein a first optical path length between the first light-emitting layer and the first electrode is different from a second optical path length between the second light-emitting layer and the third electrode in accordance with the difference between the first central wavelength and the second central wavelength.

US Pat. No. 10,461,132

DISPLAY APPARATUS AND METHOD FOR MANUFACTURING SAME

SHARP KABUSHIKI KAISHA, ...

1. A display apparatus comprising:a display region;
a first electrode;
a second electrode; and
a layered body formed between the first electrode and the second electrode,
wherein the display region includes
a first subpixel,
a second subpixel, and
a third subpixel,
the first subpixel, the second subpixel, and the third subpixel emit their respective light having mutually different peak wavelengths,
the layered body includes
a first light-emitting layer containing a first fluorescent luminescent material,
a second light-emitting layer containing a second fluorescent luminescent material,
a third light-emitting layer containing a third fluorescent luminescent material or a phosphorescent luminescent material as a luminescent material, and
a separation layer containing no luminescent material,
the second fluorescent luminescent material has a lower energy level in a minimum excited singlet state than an energy level of the first fluorescent luminescent material in the minimum excited singlet state,
the third fluorescent luminescent material or the phosphorescent luminescent material has a lower energy level in a minimum excited singlet state than the energy level of the second fluorescent luminescent material in the minimum excited singlet state,
the second light-emitting layer is formed as a layer that is common to the first subpixel, the second subpixel, and the third subpixel,
the first light-emitting layer is formed only in the first subpixel,
the third light-emitting layer is formed only in the third subpixel,
the separation layer is formed between the first light-emitting layer and the second light-emitting layer in the first subpixel, and
a distance between the first light-emitting layer and the second light-emitting layer in the first subpixel is greater than a Förster radius.

US Pat. No. 10,461,128

ARRAYS OF MEMORY CELLS AND METHODS OF FORMING AN ARRAY OF ELEVATIONALLY-OUTER-TIER MEMORY CELLS AND ELEVATIONALLY-INNER-TIER MEMORY CELLS

Micron Technology, Inc., ...

1. A method of forming an array of elevationally-outer-tier memory cells and elevationally-inner-tier memory cells, comprising:forming an elevationally-inner tier of line constructions comprising spaced-lower-first-conductive lines, programmable material directly above the inner-tier-lower-first-conductive lines, and insulator material over sidewalls of the inner-tier-lower-first-conductive lines and over sidewalls of the inner-tier-programmable material;
forming an elevationally-outer tier of line constructions comprising spaced-lower-first-conductive lines, spaced-programmable-material lines directly above the outer-tier-lower-first-conductive lines, and insulative material over sidewalls of the outer-tier-lower-first-conductive lines and over sidewalls of the outer-tier-programmable-material lines; individual of the outer-tier-lower-first-conductive lines being laterally between and longitudinally-elongated parallel with immediately-adjacent of the inner-tier-line constructions, the forming of the outer-tier-line constructions comprising:
forming at least lowermost portions of the outer-tier-lower-first-conductive lines in a self-aligned manner by depositing conductive material laterally between and longitudinally-elongated parallel with immediately-adjacent of the inner-tier-line constructions;
forming the outer-tier-programmable material directly above the conductive material;
patterning at least the outer-tier-programmable material to form lines thereof that are directly above the lowermost portions of the outer-tier-lower-first-conductive lines; and
forming the insulative material over tops and the sidewalls of the outer-tier-programmable material lines and then anisotropically etching the insulative material to remove it from being over the tops; and
forming spaced-upper-second-conductive lines for each of an elevationally-outer tier of memory cells and an elevationally-inner tier of memory cells.

US Pat. No. 10,461,127

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A variable resistance memory device comprising:a first conductive line on a substrate, the first conductive line extending in a first direction;
a second conductive line on the first conductive line, the second conductive line extending in a second direction, the second direction being a direction crossing the first direction; and
a memory cell pillar connected to the first conductive line and the second conductive line at an intersection point therebetween, the memory cell pillar including a heating electrode layer and a variable resistance layer, the variable resistance layer in contact with the heating electrode layer, two opposite sidewalls of the heating electrode layer aligned with two opposite sidewalls of the first conductive line in the first direction, respectively.

US Pat. No. 10,461,126

MEMORY CIRCUIT AND FORMATION METHOD THEREOF

Taiwan Semiconductor Manu...

1. A memory circuit, comprising:a control device arranged within a substrate and having a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal;
a first memory device having a first lower electrode separated from a first upper electrode by a first data storage layer, wherein the first upper electrode is coupled to the third terminal and the first lower electrode is coupled to a first bit-line; and
a second memory device having a second lower electrode separated from a second upper electrode by a second data storage layer, wherein the second upper electrode is coupled to a second bit-line and the second lower electrode is coupled to the third terminal.

US Pat. No. 10,461,125

THREE DIMENSIONAL MEMORY ARRAYS

Micron Technology, Inc., ...

1. A memory array, comprising:a plurality of first dielectric materials and a plurality of stacks, wherein each respective first dielectric material and each respective stack alternate, and wherein each respective stack comprises a first conductive material and a storage material on only one side of the first conductive material;
a second conductive material passing through the plurality of first dielectric materials and the plurality of stacks such that a major axis of the second conductive material is perpendicular to a major axis of the storage material; and
a second dielectric material in direct physical contact with the second conductive material and passing through the plurality of first dielectric materials and the plurality of stacks between the second conductive material and the plurality of stacks;
wherein each respective stack further comprises a third dielectric material between the first conductive material and the second dielectric material such that the storage material of the respective stack is on only one side of the third dielectric material, the second dielectric material is between the second conductive material and the third dielectric material, and the third dielectric material is in direct physical contact with the first conductive material and the second dielectric material.

US Pat. No. 10,461,124

ULTRASONIC SENSING DEVICE

InvenSense, Inc., San Jo...

1. An electronic device comprising:a CMOS substrate having a first surface and a second surface opposite the first surface;
a plurality of Piezoelectric Micromachined Ultrasonic Transducer (PMUT) devices having a transmit/receive surface, wherein the transmit/receive surface is disposed on the second surface of the CMOS substrate, wherein at least one PMUT device comprises:
an edge support structure connected to the CMOS substrate; and
a membrane connected to the edge support structure such that a cavity is defined between the membrane and the CMOS substrate, the membrane configured to allow movement at ultrasonic frequencies, the membrane comprising:
a piezoelectric layer; and
first and second electrodes coupled to opposing sides of the piezoelectric layer; and
an interior support structure disposed within the cavity and connected to the CMOS substrate and the membrane; and
a contact surface piezoelectrically associated with the plurality of PMUT devices and disposed on the first surface;
wherein the CMOS substrate is between the plurality of PMUT devices and the contact surface.

US Pat. No. 10,461,121

MINIATURE LED DISPLAY PANEL AND MINIATURE LED DISPLAY

SHENZHEN CHINA STAR OPTOE...

1. A miniature LED display panel comprising:a first substrate;
a second substrate having a cathode driving circuit disposed on a surface of the second substrate facing the first substrate;
N row signal lines disposed on the first substrate;
an insulating layer disposed on the first substrate and the row signal lines;
M column signal lines disposed on the insulating layer;
M compensation signal lines disposed on the insulating layer; and
a plurality of LED light emitting components arranged in an array of M rows and N columns on the first substrate;
wherein the LED light emitting components in a same row are electrically connected with a same row signal line, the LED light emitting components in a same column are electrically connected with a same compensation signal line and a same column signal line, and one end of each of the LED light emitting components away from the first substrate is connected with the second substrate and electrically connected with the cathode driving circuit; and
wherein each of the LED light emitting components comprises:
a first thin film transistor disposed on the first substrate and having a source electrically connected with a corresponding column signal line and a gate electrically connected with a corresponding row signal line;
a second thin film transistor disposed on the first substrate and having a source connected with a corresponding compensation signal line and a gate electrically connected with a drain of the first thin film transistor;
a first connecting metal layer disposed on the first substrate and electrically connected with a corresponding row signal line;
a second connecting metal layer disposed on the insulating layer, wherein the first connecting metal layer and the second connecting metal layer partially face each other to form a storage capacitor; and
a light emitting unit having one end electrically connected with the cathode driving circuit and the other end electrically connected with the second connecting metal layer and a drain of the second thin film transistor;
wherein the insulating layer is a silicon nitride layer or a silicon dioxide layer;
wherein each of the first substrate and the second substrate is a glass substrate; and
wherein the light emitting unit is an inorganic LED.

US Pat. No. 10,461,117

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

XINTEC INC., Taoyuan (TW...

1. A method for manufacturing semiconductor structure, comprising:(a) adhering a first carrier to a first surface of a wafer by a first temporary bonding layer;
(b) etching a second surface of the wafer facing away from the first carrier to form at least one through hole and at least one trench, wherein a conductive pad of the wafer is exposed through the through hole;
(c) forming an isolation layer on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench;
(d) forming a redistribution layer on the isolation layer and the conductive pad;
(e) adhering a second carrier to the second surface of the wafer by a second temporary bonding layer, wherein the through hole and the trench are covered by the second carrier;
(f) removing the first carrier and the first temporary bonding layer;
(g) disposing an optical element that has a dam element on the first surface of the wafer;
(h) removing the second carrier and the second temporary bonding layer after the optical element is disposed on the first surface of the wafer; and
(i) forming an insulating layer that covers the redistribution layer, the through hole, and the trench after the second carrier and the second temporary bonding layer are removed.

US Pat. No. 10,461,113

IMAGE SENSORS, AND FABRICATION AND OPERATION METHODS THEREOF

Samiconductor Manufacturi...

1. An image sensor, comprising:a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate includes a photo-sensitive region and a connection region, the photo-sensitive region comprises a transparent region and a shading region, and the shading region is between the transparent region and the connection region;
a buffer layer formed on the first surface of the substrate in the photo-sensitive region;
a metal grid formed on the buffer layer and including a plurality of staggered metal wires in the transparent region and in the shading region, wherein the metal grid is connected to an operation voltage, and a plurality of trenches are formed in the metal grid with each trench surrounded by the plurality of staggered metal wires; and
a plurality of color filters formed in the plurality of trenches of the metal grid.

US Pat. No. 10,461,112

IMAGE SENSOR USING A LARGE-AREA HIGH-ASPECT-RATIO INTEGRAL IMAGE SENSOR WITH PLURAL LIGHT SENSITIVE SUBAREAS

Alentic Microscience Inc....

1. An apparatus comprisinga large-area high-aspect-ratio integral image sensor comprising two or more light-sensitive subareas in at least one row at a sensor surface,
a chamber configured to confine a sample at a supporting surface, the chamber having a chamber surface spaced from the supporting surface by a predetermined distance associated with characteristics of the sample, and
a processor and an application coupled to a memory, the application being configured to perform a count of elements in the sample.

US Pat. No. 10,461,111

SOLID STATE IMAGING APPARATUS AND METHOD OF PRODUCING THE SAME

Sony Corporation, Tokyo ...

1. A solid state imaging apparatus comprising:a solid state image sensor including
an optical pixel region;
a metal body; and
a peripheral circuit region positioned at a periphery of the optical pixel region, the peripheral circuit region including
a multifunctional chip being electrically connected to the optical pixel region via the metal body;
a sealing resin layer formed with a sealing resin and seals the multifunctional chip in the peripheral circuit region; and
a concave structure configured to inhibit a flow of the sealing resin in a liquid state when the sealing resin layer is formed;
wherein the concave structure configured to inhibit the flow of the sealing resin in the liquid state includes a scoop portion having a scooping surface that surrounds the multifunctional chip, and
wherein the concave structure that is configured to inhibit the flow of the sealing resin in the liquid state is formed only by an optical film layer of the solid state image sensor.

US Pat. No. 10,461,110

IMAGE PICKUP ELEMENT, METHOD OF MANUFACTURING IMAGE PICKUP ELEMENT, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An imaging device comprising:a substrate;
a first photoelectric conversion region disposed in the substrate;
a second photoelectric conversion region disposed in the substrate;
a trench disposed between the first photoelectric conversion region and the second photoelectric conversion region;
a first silicon oxide film disposed in the trench, the first silicon oxide film contacting the substrate;
a hafnium oxide film disposed in the trench, the hafnium oxide film disposed at an inner side of the first silicon oxide film;
a tantalum oxide film disposed in the trench, the tantalum oxide film disposed at an inner side of the hafnium oxide film;
a second silicon oxide film disposed in the trench, the second silicon oxide film disposed at an inner side of the tantalum oxide film; and
tungsten material disposed in the trench, the tungsten material disposed at an inner side of the second silicon oxide film,
wherein,
the first silicon oxide film is disposed over the first photoelectric conversion region and contacts the substrate,
the hafnium oxide film is disposed over the first photoelectric conversion region and contacts the first silicon oxide film,
the tantalum oxide film is disposed over the first photoelectric conversion region and contacts the hafnium oxide film,
the second silicon oxide film is disposed over the first photoelectric conversion region and contacts the tantalum oxide film, and
a thickness of the second silicon oxide film over the first photoelectric conversion region is larger than a thickness of the second silicon oxide film between the tantalum oxide film and the tungsten material in the trench.

US Pat. No. 10,461,109

MULTIPLE DEEP TRENCH ISOLATION (MDTI) STRUCTURE FOR CMOS IMAGE SENSOR

Taiwan Semiconductor Manu...

1. A CMOS image sensor, comprising:a substrate having a front-side and a back-side opposite to the front-side;
a plurality of pixel regions disposed on the substrate and respectively comprising a photodiode configured to convert radiation that enters the substrate from the back-side into an electrical signal;
a boundary deep trench isolation (BDTI) structure disposed between adjacent pixel regions, extending from the back-side of the substrate to a first depth within the substrate, and surrounding the photodiode;
a multiple deep trench isolation (MDTI) structure disposed within the plurality of pixel regions, extending from the back-side of the substrate to a second depth within the substrate, and overlying the photodiode; and
a dielectric layer filling in a BDTI trench of the BDTI structure and a MDTI trench of the MDTI structure;
wherein the MDTI structure comprises segments that are spaced apart from one other and are symmetrical along a middle line of the pixel region.

US Pat. No. 10,461,106

IMAGING ELEMENT AND CAMERA SYSTEM

Sony Corporation, Tokyo ...

1. An imaging element comprising:a plurality of photoelectric conversion sections that are arrayed on a substrate to receive light incident through a dual-pass filter having transmission bands for visible light and a predetermined range of near-infrared light,
wherein the photoelectric conversion sections include a visible light photoelectric conversion section and a near-infrared light photoelectric conversion section, and the visible light photoelectric conversion section includes a red light photoelectric conversion section, a green light photoelectric conversion section, and a blue light photoelectric conversion section,
wherein a near-infrared absorption filter is selectively disposed on a light incident surface of the photoelectric conversion sections in correspondence with the visible light photoelectric conversion section, and
wherein at least a part of the near-infrared absorption filter is embedded into an opening in a light-shielding layer separating neighboring photoelectric conversion sections.

US Pat. No. 10,461,105

PHOTODIODE ARRAY

ams AG, Unterpremstaette...

1. A photodiode array, comprising:A first photodiode comprising a first set of spatially separate and electrically interconnected photodiode segments,
A second photodiode comprising a second set of spatially separate and electrically interconnected photodiode segments,
A first group of photodiode segments comprising photodiode segments from the first and/or second set of photodiode segments, wherein the photodiode segments from the first group of photodiode segments are radially arranged around a common center of symmetry in a common first distance with respect to the common center of symmetry, and
A second group of photodiode segments comprising photodiode segments from the first and/or second set of photodiode segments, wherein photodiode segments from the second group of photodiode segments are radially arranged around the common center of symmetry in a second common distance with respect to the common center of symmetry, wherein the first distance is different from the second distance, and wherein
Each photodiode has an area matched counterpart photodiode forming a matched pair of photodiodes,
The matched counterpart photodiodes comprise a matched set of spatially separate and electrically interconnected photodiode segments, and
Each group of photodiode segments comprises the corresponding matched set of photodiode segments.

US Pat. No. 10,461,103

POWER STORAGE ELEMENT, MANUFACTURING METHOD THEREOF, AND POWER STORAGE DEVICE

Semiconductor Energy Labo...

1. A power storage element comprising:a pair of electrodes;
a solid electrolyte layer in contact with the pair of electrodes; and
a lithium layer spaced apart from the pair of electrodes with the solid electrolyte layer provided therebetween,
wherein the solid electrolyte layer is between the pair of electrodes.

US Pat. No. 10,461,102

DISPLAY DEVICE, TRANSFLECTIVE ARRAY SUBSTRATE, AND MANUFACTURING METHOD THEREOF

Shenzhen China Star Optoe...

1. A manufacturing method of a transflective array substrate, wherein the transflective array substrate comprises a plurality of pixel cells, each of the pixel cells comprises a reflective area, and the manufacturing method comprises:arranging a plurality of scanning lines, a plurality of data lines intersecting with the scanning lines, and a plurality of TFTs, wherein the TFT is surrounded by the scanning lines and the data lines, the TFT is configured within the pixel cell, and the TFT electrically connects to the scanning line and the data line respectively;
arranging a photoresist layer above the TFT corresponding to each of the pixel cells;
arranging at least one pixel electrode above the photoresist layer corresponding to each of the pixel cells, wherein the TFT electrically connects to the pixel electrode;
arranging a reflective layer within the reflective area, wherein the reflective layer is configured above the photoresist layer, so as to prevent ambient light beams from being filtered by the photoresist layer when the ambient light beams enter the reflective area;
wherein step of arranging a plurality of the scanning lines, a plurality of the data lines intersecting with the scanning lines, and a plurality of the TFTs further comprises:
depositing a gate metal layer on a glass substrate;
forming the scanning lines and a gate of the TFT by conducting an exposure process, a development process, a wet-etching process, and a peeling-off process on the gate metal layer, wherein the gate electrically connects to the scanning line;
depositing a source-drain metal layer above the scanning line and the gate;
forming the data lines, and a source and a drain of the TFT by conducting the exposure process, the development process, the wet-etching process, a dry-etching process, and the peeling-off process on the source-drain metal layer, wherein the source electrically connects to the data line, and the drain electrically connects to the pixel electrode;
wherein, before the step of depositing the source-drain metal layer above the scanning line and the gate, the manufacturing method further comprises:
depositing a gate insulation layer above the scanning line and the gate to form a first insulation layer;
depositing an N-doped amorphous silicon layer on the first insulation layer;
forming a semiconductor layer by conducting the exposure process, the development process, the dry-etching process, and the peeling-off process on the N-doped amorphous silicon layer;
before the step of arranging the photoresist layer above the TFT corresponding to each of the pixel cells, the manufacturing method further comprises:
depositing a photoresist insulation layer on the data line, and the source and the drain of the TFT to form a second insulation layer;
before the step of arranging at least one pixel electrode above the photoresist layer corresponding to each of the pixel cells, the manufacturing method further comprises:
depositing a flat layer on the photoresist layer to form a third insulation layer;
forming a through hole by conducting a through-hole etching process on the third insulation layer, wherein the through hole penetrates the third insulation layer, the photoresist layer, and a second insulation layer, the drain is exposed by the through hole;
the step of arranging the pixel electrode above the photoresist layer corresponding to each of the pixel cells further comprises:
depositing a first conductive material layer on the third insulation layer;
forming the pixel electrode by conducting the exposure process, the development process, the wet-etching process, and the peeling-off process on the first conductive material layer, wherein the pixel electrode electrically connects to the drain via the through hole;
before the step of arranging the reflective layer, the manufacturing method further comprises:
depositing an electrode insulation layer on the pixel electrode to form a fourth insulation layer.

US Pat. No. 10,461,100

DISPLAY DEVICE HAVING A DIFFERENT TYPE OF OXIDE SEMICONDUCTOR TRANSISTOR

Japan Display Inc., Toky...

1. A display device comprising:a display circuit provided with a plurality of pixel circuits in a matrix shape;
a drive circuit provided in a periphery of the display circuit, the drive circuit driving each of the plurality of pixel circuits;
a first transistor having a first oxide semiconductor layer as a channel and a first gate electrode, the first transistor being included in the drive circuit;
a second transistor having a second oxide semiconductor layer as a channel and a second gate electrode, the second transistor being included in the pixel circuit, and a composition of the first oxide semiconductor layer is different from a composition of the second oxide semiconductor layer,
wherein
the first oxide semiconductor layer and the second oxide semiconductor layer include Sn, and
a content ratio of the Sn included in the first oxide semiconductor layer is more than a content ratio of the Sn included in the second oxide semiconductor layer.

US Pat. No. 10,461,099

METAL OXIDE FILM AND METHOD FOR FORMING METAL OXIDE FILM

Semiconductor Energy Labo...

1. A method for manufacturing a metal oxide film comprising:forming the metal oxide film by a sputtering method using a sputtering target comprising a polycrystalline oxide in an atmosphere where oxygen partial pressure is greater than or equal to 33%,
wherein the sputtering target comprises indium, gallium and zinc,
wherein the metal oxide film comprises a plurality of crystal parts when the metal oxide film is formed,
wherein a size of one of the plurality of crystal parts is less than or equal to 10 nm, and
wherein a crystal peak is not observable in an XRD spectrum with respect to the metal oxide film.

US Pat. No. 10,461,098

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. An electronic device comprising:a band portion configured to be worn on a wrist;
a display portion configured to display a button on a screen; and
a microphone,
wherein the display portion comprises a pixel portion comprising a transistor,
wherein the transistor comprises an oxide semiconductor layer comprising In, Ga, Zn and O,
wherein the electronic device is configured such that data is input by touching the button, and
wherein the electronic device is configured such that data is input by inputting voice into the microphone.

US Pat. No. 10,461,097

ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

Shenzhen China Star Optoe...

1. An array substrate, comprising: a substrate; a first insulating layer disposed on the substrate, wherein the first insulating layer defines a channel; a source electrode pattern disposed in the channel of the first insulating layer; an annular gate electrode pattern disposed on the first insulating layer and surrounding the periphery of the source electrode pattern; a second insulating layer covering the annular gate electrode pattern, wherein the second insulating layer defines an opening corresponding to the channel of the first insulating layer, such that a face of the source electrode pattern away from the substrate is at least partially accessible through the channel of the first insulating layer and the opening of the second insulating layer; a semiconductor pattern disposed in the annular area of the annular gate electrode pattern, and is electrically connected to the accessible face of the source electrode pattern, the semiconductor pattern is further electrically insulated from the annular gate electrode pattern by the second insulating layer; a pixel electrode disposed on the second insulating layer and electrically connected to a face of the semiconductor pattern away from the substrate;a data line electrically connected to the source electrode pattern, wherein the first insulating layer comprising a buffer layer and a passivation layer, the data line is formed within the buffer layer and covered by the passivation layer; and wherein the source electrode pattern comprises a first source electrode pattern layer and a second source electrode pattern layer disposed stacked together, the first source electrode pattern layer and the data line are formed by the same material, the second source electrode pattern layer and the annular gate electrode pattern are formed by the same material.

US Pat. No. 10,461,091

NAND FLASH MEMORY DEVICE HAVING FACING BAR AND METHOD OF FABRICATING THE SAME

DOSILICON CO., LTD., Sha...

1. A NAND flash memory device comprising:a facing bar configured to protrude to have a predetermined width and height from a planar surface of a semiconductor substrate and configured to extend in a first direction which is a horizontal direction with respect to a horizontal surface of the semiconductor substrate, the facing bar being divided into a plurality of device forming sections by a plurality of active regions, wherein the plurality of active regions extend parallel with one another in a second direction of the horizontal direction and are electrically isolated from one another, and the second direction intersects the first direction; and
a first side structure and a second side structure provided on two side surfaces of the facing bar, each of the first side structure and the second side structure including a base electrode guard including a conductive material, the base electrode guard extending in the first direction to be provided on the plurality of active regions, wherein the first side structure and the second side structure are divided into a plurality of first active structures and a plurality of second active structures to correspond to the plurality of device forming sections,
wherein each of the plurality of first active structures and the plurality of second active structures comprises a base transistor in which at least a portion of a base transmission channel is provided on a side surface of the facing bar according to a voltage applied to a control gate, and the control gate is provided as a portion of the base electrode guard,
wherein the base transistor of the first active structures and the base transistor of the second active structures, which correspond to one of the device forming sections, are provided as a portion of one cell string.

US Pat. No. 10,461,089

CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY

Taiwan Semiconductor Manu...

1. An integrated circuit (IC) comprising:a semiconductor substrate including a peripheral region and a memory region separated by an isolation structure, wherein the isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material;
a memory cell on the memory region;
a dummy control gate structure on the isolation structure, wherein the dummy control gate structure defines a dummy sidewall that faces the peripheral region and that comprises multiple different materials;
a sidewall spacer on the isolation structure, along the dummy sidewall of the dummy control gate structure, wherein the sidewall spacer has a boundary sidewall that faces the peripheral region and that is smooth; and
a logic device on the peripheral region.

US Pat. No. 10,461,087

STRUCTURE AND METHOD FOR FINFET SRAM

TAIWAN SEMICONDUCTOR MANU...

1. A method for semiconductor fabrication, comprising:forming mandrel patterns over a substrate using a first mask that defines the mandrel patterns, wherein the first mask includes at least four first patterns that are spaced from each other in a first direction, wherein each of the first patterns extends lengthwise in a second direction orthogonal to the first direction;
forming spacers on sidewalls of the mandrel patterns;
removing the mandrel patterns;
etching the substrate using the spacers as an etch mask, thereby forming fin lines in the substrate; and
performing a fin cut process using a second mask to remove selective ones of the fin lines, wherein the second mask includes at least four second patterns, each being an elongated shape extending lengthwise in the second direction, wherein the second patterns are spaced from each other in the first direction, and each of the second patterns covers a side of one of the first patterns when the first and second masks are superimposed, the side extending in the second direction.

US Pat. No. 10,461,086

MEMORY CELL STRUCTURE

Taiwan Semiconductor Manu...

1. A memory device comprising:an SRAM memory cell disposed on a substrate and including:
a first transistor;
a first Vss node component including a first conductive island on a first metallization layer;
a first via physically interfacing a bottom surface of the first metallization layer and coupling the first Vss node component and the first transistor, wherein the first via has a length and a width, the length at least 1.5 times that of the width, wherein the length and width are measured on a plane parallel a top surface of the substrate;
an extended contact physically interfacing a bottom surface of the first via and extending to a source region of the first transistor;
a second Vss node component including a second conductive island on a second metallization layer, wherein a second via extends from the first conductive island to the second conductive island;
a word line on a second metallization layer above the first metallization layer; and
a Vss line coupled to the second Vss node component by a third via extending from the second conductive island to the Vss line.

US Pat. No. 10,461,085

SEMICONDUCTOR DEVICE INCLUDING INSULATING ELEMENT

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a substrate;
a first transistor on the substrate, wherein the first transistor comprises a first source/drain electrode in the substrate;
a second transistor on the substrate, wherein the second transistor comprises a second source/drain electrode; and
an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode, a top surface of the insulating layer is above a top surface of the substrate, wherein the insulating layer corresponds to a continuous poly on oxide definition (CPODE) pattern.

US Pat. No. 10,461,083

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. A semiconductor memory cell comprising:a memory transistor comprising:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first insulating region located above said floating body region;
second insulating regions adjacent to said floating body region;
a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions, wherein:
said floating body region is configured to be bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, and a depletion region formed as a result of an application of a back bias to said buried layer region; and
an access device comprising a body region, wherein said access device is connected in series to said memory transistor, and wherein said body region is configured to be isolated from said floating body region by said depletion region.

US Pat. No. 10,461,082

WELL-BASED INTEGRATION OF HETEROEPITAXIAL N-TYPE TRANSISTORS WITH P-TYPE TRANSISTORS

Intel Corporation, Santa...

1. Integrated circuit (IC) structures, comprising:a well recess in a first region of a substrate, the well recess containing an amorphous well-isolation material over a bottom of the well recess, and a crystalline well material over the well-isolation material, wherein the well material is coupled to a seeding surface of the substrate at the bottom of the well recess by a crystalline pillar material that extends through the well-isolation material;
an amorphous fin-isolation material over a first surface of the well material, and over a second surface in a second region of the substrate adjacent to the first region wherein the first surface is substantially planar with the second surface; and
a first fin comprising a first crystalline material, wherein the first fin extends from the first surface of the well material and protrudes through the fin-isolation material to a first height over the fin-isolation material; and
a second fin comprising a second crystalline material, wherein the second fin extends from the second surface of the second region of the substrate and protrudes through the fin-isolation material to a second height over the fin-isolation material, the second height being substantially equal to the first height.

US Pat. No. 10,461,081

SUPER-SELF-ALIGNED CONTACTS AND METHOD FOR MAKING THE SAME

Tel Innovations, Inc., L...

1. A semiconductor device, comprising:a first linear gate structure;
a second linear gate structure located next to the first linear gate structure, the second linear gate structure separated from the first linear gate structure by a gate pitch, the second linear gate structure forming a first PMOS transistor and a first NMOS transistor;
a third linear gate structure located next to the second linear gate structure, the third linear gate structure separated from the second linear gate structure by the gate pitch, the third linear gate structure forming a second PMOS transistor and a second NMOS transistor;
a fourth linear gate structure located next to the third linear gate structure, the fourth linear gate structure separated from the third linear gate structure by the gate pitch, the fourth linear gate structure forming a third PMOS transistor and a third NMOS transistor;
a fifth linear gate structures located next to the fourth linear gate structure, the fifth linear gate structure separated from the fourth linear gate structure by the gate pitch;
a first gate contact physically connected to the second linear gate structure at a location between the first PMOS transistor and the first NMOS transistor;
a second gate contact physically connected to the third linear gate structure at a location between the second PMOS transistor and the second NMOS transistor; and
a third gate contact physically connected to the fourth linear gate structure at a location between the third PMOS transistor and the third NMOS transistor.

US Pat. No. 10,461,079

METHOD AND DEVICE OF PREVENTING MERGING OF RESIST-PROTECTION-OXIDE (RPO) BETWEEN ADJACENT STRUCTURES

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating semiconductor device, comprising:epitaxially growing a first source/drain on a first fin structure and a second source/drain on a second fin structure;
forming a first layer over the first source/drain but not over the second source/drain;
forming a dielectric layer over the first layer and over the second source/drain; and
removing a first segment of the dielectric layer but not a second segment of the dielectric layer, wherein the first segment is disposed over the first layer, and wherein the second segment is disposed over the second source/drain.

US Pat. No. 10,461,078

CREATING DEVICES WITH MULTIPLE THRESHOLD VOLTAGE BY CUT-METAL-GATE PROCESS

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:providing a workpiece that includes a substrate, a semiconductor fin over the substrate, and first and second high-k metal gate structures engaging the semiconductor fin to define first and second transistors respectively, wherein the first and second high-k metal gate structures have a same number of material layers, are isolated from each other, and are oriented lengthwise along a first direction;
etching the first and second high-k metal gate structures, resulting in a first trench and a second trench in the workpiece, wherein the first trench has a first dimension along the first direction, and is away from the semiconductor fin by a first distance along the first direction, wherein the second trench has a second dimension along the first direction, and is away from the semiconductor fin by a second distance along the first direction; and
filling the first and second trenches with one or more dielectric materials, wherein the first dimension is configured to be different from the second dimension or the first distance is configured to be different from the second distance such that the first and second transistors are provided with different threshold voltages.

US Pat. No. 10,461,077

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, comprising:a first conductive-type SiC base layer having a first surface and a second surface, the second surface of the first conductive-type SiC base layer being on a first conductive-type SiC substrate, the first conductive-type SiC substrate having a first surface facing the second surface of the SiC base layer and a second surface opposite the first surface of the SiC substrate and defining a drain region of the SiC-MOSFET;
a trench etched in the second surface of the SiC substrate, the trench dividing the SiC substrate into a plurality of first conductive-type regions;
a second conductive-type region in a bottom surface of the trench so as to form a collector region in the bottom surface;
a second conductive-type region in the first surface of the SiC base layer so as to form a channel region in a surficial portion of the SiC base layer;
a first conductive-type region in the first surface of the SiC base layer so as to form an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET;
a second conductive-type region in the first surface of the SiC base layer so as to form a channel contact region in a surficial portion of the SiC base layer, the channel contact region penetrating the emitter region and contacting with the channel region, wherein
a first unit including the channel region, the emitter region and the channel contact region faces a second unit including a plurality of collector region and the plurality of the first conductive-type regions in the thickness direction of the SiC base layer, and
a deepest portion of the trench is at a position nearer the first surface of the SiC base layer with respect to an interface between the SiC substrate and the SiC base layer.

US Pat. No. 10,461,076

3D STACKED INTEGRATED CIRCUITS HAVING FUNCTIONAL BLOCKS CONFIGURED TO ACCELERATE ARTIFICIAL NEURAL NETWORK (ANN) COMPUTATION

MICRON TECHNOLOGY, INC., ...

1. A three-dimensional stacked integrated circuit (3D SIC) for implementing an artificial neural network (ANN), comprising:a non-volatile memory die comprising an array of non-volatile memory partitions, wherein each partition of the array of non-volatile memory partitions is configured to store first parameters of a set of neurons;
a volatile memory die comprising an array of volatile memory partitions, wherein each partition of the array of volatile memory partitions is configured to store second parameters of the set of neurons; and
a processing logic die comprising an array of processing logic partitions, wherein each partition of the array of processing logic partitions is configured to:
receive input data; and
process the input data according to the set of neurons to generate output data.

US Pat. No. 10,461,074

FIELD-EFFECT SEMICONDUCTOR DEVICE HAVING A HETEROJUNCTION CONTACT

Infineon Technologies Aus...

1. A semiconductor device, comprising:a semiconductor body having a main surface, the semiconductor body comprising a drift region of monocrystalline SiC, the drift region being of a first conductivity type; and
a metallization arranged at the main surface,
wherein in a cross-section which is substantially orthogonal to the main surface, the semiconductor body further comprises:
a contact region of the monocrystalline SiC directly adjoining the drift region and the metallization, the contact region being of a second conductivity type; and
an anode region of a semiconductor material having a lower band-gap than the monocrystalline SiC, the anode region being in ohmic contact with the metallization and forming a heterojunction with the drift region.

US Pat. No. 10,461,073

POWER MODULE WITH MOSFET BODY DIODE ON WHICH ENERGIZATION TEST CAN BE CONDUCTED EFFICIENTLY

Mitsubishi Electric Corpo...

1. A power module comprising:a casing;
a first terminal, a second terminal, and a third terminal, each being fixed to the casing and connectable to an outside;
a first MOS transistor contained in the casing, connected between the first terminal and the second terminal, and having a forward direction from the second terminal to the first terminal;
a second MOS transistor contained in the casing, connected between the second terminal and the third terminal, and having a forward direction from the third terminal to the second terminal;
a first Schottky barrier diode contained in the casing, being in parallel with the first MOS transistor, having an anode connected to the first terminal, and having a cathode connected to the second terminal; and
a second Schottky barrier diode contained in the casing, being in parallel with the second MOS transistor, having an anode connected to the second terminal, and having a cathode connected to the third terminal,
each of the first Schottky barrier diode and the second Schottky barrier diode including a resistive layer formed of polysilicon in direct contact with a surface of a cathode electrode layer on a side of the cathode electrode layer opposite to an n-type drift layer having a p-type guard ring region which is in direct contact with portions of a dielectric film and a Schottky anode electrode,
the resistive layer of the first Schottky barrier diode being configured such that:
a current value at a first crossing point is within a range of ±10% of a rated current of the power module, the first crossing point being a crossing point of:
a current-voltage characteristic graph of the first MOS transistor when forward current is caused to flow in a body diode of the first MOS transistor crossing a current-voltage characteristic graph of the first Schottky barrier diode when forward current is caused to flow in the first Schottky barrier diode,
the resistive layer of the second Schottky barrier diode being configured such that:
a current value at a second crossing point is within a range of ±10% of the rated current of the power module, the second crossing point being a crossing point of:
a current-voltage characteristic graph of the second MOS transistor when forward current is caused to flow in a body diode of the second MOS transistor crossing a current-voltage characteristic graph of the second Schottky barrier diode when forward current is caused to flow in the second Schottky barrier diode.

US Pat. No. 10,461,072

ISOLATION STRUCTURE FOR IC WITH EPI REGIONS SHARING THE SAME TANK

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device comprising:a substrate having a p-type epitaxial (p-epi) layer thereon;
an n+ buried layer disposed within the p-epi layer and defining a buried portion of the p-epi layer below the n+ buried layer;
an outer isolation ring including a first dielectric sidewall and a first deep n-type (DEEPN) diffusion region, wherein the first DEEPN diffusion region is arranged in a ring in the p-epi layer and contacts the p-epi layer and the first dielectric sidewall, and wherein the first DEEPN diffusion region extends downward from the p-epi layer to the n+ buried layer and encloses a portion of the p-epi layer to define an enclosed p-epi region; and
a plurality of inner isolation structures within the enclosed p-epi region, each inner isolation structure including one of a corresponding plurality of second dielectric sidewalls and one of a corresponding plurality of second DEEPN diffusion regions each second DEEPN diffusion region contacting the corresponding second dielectric sidewall, separating the corresponding second dielectric sidewall from an adjacent second dielectric sidewall, and extending downward from the p-epi layer to the n+ buried layer;
wherein the plurality of inner isolation structures are spaced apart such that adjacent ones of the second DEEPN diffusion regions overlap to form a continuous wall of n-type material extending from a first side to a second side of the outer isolation ring thereby dividing the enclosed p-epi region into a first p-epi region and a second p-epi region, wherein the n+ buried layer in the first p-epi region connects to the n+ buried layer in the second p-epi region.

US Pat. No. 10,461,070

DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A display apparatus, comprising:a substrate comprising a display area and a peripheral area surrounding the display area, the display area comprising:
a main area located at a center of the substrate;
a first protruding area extending from the main area and protruding toward the peripheral area in a first direction;
a second protruding area extending from the main area and protruding toward the peripheral area in the first direction, the second protruding area being spaced apart from the first protruding area in a second direction that intersects the first direction; and
a groove portion disposed between the first protruding area and the second protruding area;
a display unit comprising a first light emitter disposed on the first protruding area and a second light emitter disposed on the second protruding area;
a first load matching part disposed on a portion of the peripheral area adjacent to the first light emitter and electrically connected to the first light emitter; and
a second load matching part disposed on a portion of the peripheral area adjacent to the second light emitter and electrically connected to the second light emitter,
wherein the first load matching part and the second load matching part are electrically connected to each other by a conductive film disposed on the peripheral area.

US Pat. No. 10,461,069

HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device structure, comprising:a bonding structure formed between a first substrate and a second substrate, wherein the bonding structure comprises a first polymer bonded to a second polymer, and a first conductive material bonded to a second conductive material;
a first TSV formed in the first substrate;
an interconnect structure formed over the first TSV, wherein the first TSV is between the interconnect structure and the bonding structure; and
a first conductive layer between the first conductive material and the first TSV, wherein the first conductive layer has a first surface and a second surface, the first surface is in direct contact with the first TSV, and the second surface is in direct contact with the first polymer.

US Pat. No. 10,461,064

RED FLIP CHIP LIGHT EMITTING DIODE, PACKAGE, AND METHOD OF MAKING THE SAME

Bridgelux, Inc., Livermo...

1. A method for making a flip chip light emitting diode comprising the steps of:growing a layer of active material onto a substrate having a crystalline lattice matching the crystalline lattice of the layer of active material;
attaching a carrier to a surface of the active material layer that is opposite the substrate, wherein the carrier is formed from a material transparent to a wavelength of light emitted from the active material layer, wherein the carrier is continuous construction extending along the surface of the active material layer;
removing the substrate from the active material layer thereby exposing a surface of the active material layer opposite the carrier; and
forming a pair of electrodes on the light emitting diode along a common surface of the active material layer earlier covered by the substrate and opposite the carrier for connecting with electrical contacts of an adjacent connection member positioned opposite the common surface, wherein a surface of the carrier opposite the active material layer is free of electrodes.

US Pat. No. 10,461,063

LIGHT-EMITTING DEVICE

Toshiba Hokuto Electronic...

1. A light-emitting device having flexibility comprising:a light-emitting part;
an external wiring part; and
a joint part,
the light-emitting part comprising a first portion of a first insulating substrate, at least a first portion of a second insulating substrate, a plurality of light-emitting elements, a first portion of an internal wiring pattern, and a resin layer, the first portion of the first insulating substrate and the first portion of the second insulating substrate are each light transmitting and flexible, the plurality of light-emitting elements are between the first portion of the first insulating substrate and the first portion of the second insulating substrate, the first portion of the internal wiring pattern is formed on at least one inside surface of at least one of the first portion of the first insulating substrate and the first portion of the second insulating substrate, the resin layer is light transmissive and insulating, the resin layer is between the first portion of the first insulating substrate and the first portion of the second insulating substrate,
the external wiring part comprising a first portion of a third insulating substrate and a first portion of an external wiring, the first portion of the third substrate is flexible,
the joint part comprising:
a second portion of the internal wiring pattern that extends beyond the light-emitting part, said second portion of the internal wiring pattern comprising first and second internal wiring ends, each of the internal wiring ends having a respective internal wiring end width, the first internal wiring end is an anode, the second internal wiring end is a cathode;
a second portion of the external wiring that extends beyond the external wiring part;
a second portion of the third insulating substrate that extends beyond the external wiring part; and
an anisotropic conductive adhesive,
at least part of the second portion of the external wiring is divided into a plurality of divided wirings, each divided wiring of the plurality of divided wirings having a width that is less than each of the internal wiring end widths,
the first internal wiring end is adjacent to the second internal wiring end, and the anisotropic conductive adhesive comprises a single region that is in contact with each of the plurality of divided wirings and the first and second internal wiring ends, and the single region of the anisotropic conductive adhesive electrically connects the first internal wiring end to at least a first divided wiring of the plurality of divided wirings, and connects the second internal wiring end to at least a second divided wiring of the plurality of divided wirings.

US Pat. No. 10,461,061

APPARATUSES AND METHODS FOR SEMICONDUCTOR DIE HEAT DISSIPATION

Micron Technology, Inc., ...

1. An apparatus, comprising:a substrate;
a thermal interface layer disposed on a surface of the substrate; and
a heat spreader with a plurality of substrate-facing protrusions in contact with the thermal interface layer,
wherein the heat spreader covers an entire surface of a top die of a stack of semiconductor die, and
wherein a thickness of the thermal interface layer under a face of the substrate-facing protrusions facing the substrate is thinner relative to a thickness of the thermal interface layer under areas of the heat spreader that have no substrate-facing protrusions.

US Pat. No. 10,461,056

CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE WITH A METAL CONTACT STRUCTURE AND PROTECTIVE LAYER, AND METHOD OF FORMING AN ELECTRICAL CONTACT

Infineon Technologies AG,...

1. A chip package, comprising:a chip comprising a chip metal surface;
a metal contact structure, the metal contact structure electrically contacting the chip metal surface;
a packaging material; and
a protective layer comprising a portion formed at an interface between a portion of the metal contact structure and the packaging material;
wherein the protective layer comprises at least one material of a group of inorganic materials, the group consisting of
Ni, Co, Cr, Ti, V, Mn, Zn, Sn, Mo, and Zr,
wherein the protective layer further comprises a noble metal, wherein the protective layer comprises regions free from the noble metal, wherein the regions free from the noble metal provide at least a portion of the interface between the portion of the metal contact structure and the packaging material.

US Pat. No. 10,461,054

ANISOTROPIC CONDUCTIVE FILM AND PRODUCTION METHOD OF THE SAME

DEXERIALS CORPORATION, T...

1. An anisotropic conductive film in which conductive particles are dispersed in an insulating resin layer, the anisotropic conductive film comprising:a first conductive particle layer in which conductive particles are dispersed at a predetermined depth in a film thickness of the anisotropic conductive film; and
a second conductive particle layer in which conductive particles are dispersed at a depth that is different from that of the first conductive particle layer, wherein
in each of the conductive particle layers, a closest distance between the adjacent conductive particles is 2 times or more an average particle diameter of the conductive particles.

US Pat. No. 10,461,051

VIA STRUCTURE FOR PACKAGING AND A METHOD OF FORMING

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a substrate;
a plurality of conductive pads on the substrate;
a passivation layer on the conductive pads and the substrate;
a plurality of conductive pillars extending through the passivation layer and connected to the conductive pads; and
a molding compound extending between the conductive pillars and encapsulating sidewalls of the substrate, the molding compound comprising a single continuous material, wherein uppermost surfaces of the conductive pillars are level with uppermost surfaces of the molding compound.

US Pat. No. 10,461,045

POWER SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A power semiconductor device comprising:an insulating substrate having a metal layer which is formed on an upper surface of said insulating substrate;
a semiconductor element and a main electrode each bonded to an upper surface of said metal layer;
a metal ware connecting said metal layer and said semiconductor element;
a metal member bonded to a lower surface side of said insulating substrate;
a case member surrounding said insulating substrate and affixed to said metal member; and
a sealing resin filled in a region surrounded by said metal member and said case member, said sealing resin having a resin strength equal to or higher than 0.12 MPa at room temperature, a microcrystallization temperature equal to or lower than ?55° C. and a needle penetration of 30 to 50 after storage at 175° C. for 1000 hours, said sealing resin sealing said insulating substrate, said metal layer, said semiconductor element, said metal wire, and said main electrode.

US Pat. No. 10,461,044

WAFER LEVEL FAN-OUT PACKAGE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A method of manufacturing a wafer level fan-out package, comprising:placing a chip and a base substrate against each other with an active surface of the chip facing the base substrate;
encapsulating the chip by forming an encapsulant on the base substrate;
removing the base substrate to expose the active surface of the chip and a surface of the encapsulant laterally adjacent to the chip;
forming a wiring structure on the active surface of the chip and on the surface of the encapsulant adjacent to the chip; and
subsequently mounting a passive electronic component on and electrically connecting the passive electronic component to the wiring structure,
wherein a recess is formed in the surface of the encapsulant laterally adjacent to the chip such that the recess is defined to one side of the chip in a direction parallel to said surface of the encapsulant, and
the passive electronic component is set within the recess such that the passive electronic component is disposed to said one side of the chip in the direction parallel to said surface of the encapsulant.

US Pat. No. 10,461,041

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

Siliconware Precision Ind...

1. An electronic package, comprising:a first carrier having a first side and a second side opposite to the first side;
at least one semiconductor chip disposed on the first side of the first carrier;
an encapsulant formed on the second side of the first carrier;
a first conductor disposed on the encapsulant and configured for generating radiation energy by an alternating voltage, an alternating current or radiation variation; and
a second conductor disposed on the second side of the first carrier and corresponding in function to the first conductor.

US Pat. No. 10,461,034

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

18. A manufacturing method of a package structure, comprising:providing a carrier;
forming a conductive plate having a first surface and a second surface opposite to the first surface and disposing the first surface of the conductive plate on the carrier;
disposing at least one die provided with a connecting film directly on the second surface of the conductive plate and physically contacting the at least one die and the second surface of the conductive plate by sandwiching the connecting film therebetween;
forming through interlayer vias on the second surface of the conductive plate;
encapsulating the at least one die, the connecting film and the through interlayer vias, and covering the second surface of the conductive plate with a molding compound;
debonding the carrier and exposing a third surface of the molding compound levelled and coplanar with the first surface of the conductive plate;
forming an encapsulant over the third surface of the molding compound; and
forming antenna elements on the encapsulant, the encapsulant being located between the antenna elements and the conductive plate, and the conductive plate being located between the encapsulant and the connecting film.

US Pat. No. 10,461,033

SEMICONDUCTOR MEMORY PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor memory package comprising:a package base substrate comprising a substrate base, and a plurality of chip connection pads and a plurality of external connection pads respectively arranged on upper and lower surfaces of the substrate base; and
at least two semiconductor memory chips mounted on the package base substrate and each having a plurality of chip pads electrically connected to the plurality of chip connection pads,
wherein a first electrical path extends from one of the plurality of external connection pads to a first chip pad of one of the at least two semiconductor memory chips and a second electrical path extends from the one of the plurality of external connection pads to a second chip pad of another of the at least two semiconductor memory chips,
the first electrical path and the second electrical path comprises a common line extending from a branch point of the first electrical path and the second electrical path, to the one of the plurality of external connection pads,
a first branch line of the first electrical path extends from the branch point to the first chip pad and a second branch line of the second electrical path extends from the branch point to the second chip pad, and
the package base substrate comprises an open stub extending from the common line, the open stub having one end connected to the common line and another other end which is open without being connected to another electrical path and having a stub extension length greater than half of a branch extension length of a longer of the first branch line and the second branch line and less than twice the branch extension length.

US Pat. No. 10,461,032

SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE

Intel Corporation, Santa...

1. An apparatus, comprising:a first die and a die-bonding film disposed on and entirely covering a back surface of the first die, but not extending beyond the back surface of the first die, wherein a surface of the die-bonding film is an exposed surface;
a second die including one or more through-silicon vias disposed therein (TSV die), the first die electrically coupled to the TSV die through the one or more through-silicon vias, wherein the first die is electrically coupled to the TSV die through the one or more through-silicon vias by one or more corresponding conductive bumps disposed on the first die and by one or more bond pads disposed on the TSV die;
a layer of epoxy flux material disposed between the first die and the TSV die, the layer of epoxy flux material surrounding the one or more corresponding conductive bumps disposed on the first die;
a coreless substrate, wherein the die-bonding film and both the first die and the TSV die are embedded in the coreless substrate, wherein no surface of the first die and the die-bonding film protrudes from a surface of the coreless substrate, and wherein the coreless substrate comprises a continuous encapsulation layer laterally surrounding both the first die and the TSV die, wherein one or more conductive vias extend through the entirety of the coreless substrate, wherein the exposed surface of the die-bonding film is co-planar with corresponding pads of the one or more conductive vias;
a plurality of conductive contacts disposed on a surface of the coreless substrate, wherein the plurality of conductive contacts is above the second die and the second die is above the first die and the die-bonding film; and
a packaged die attached to the corresponding pads of the one or more conductive vias.

US Pat. No. 10,461,029

HYBRID MATERIAL ELECTRICALLY PROGRAMMABLE FUSE AND METHODS OF FORMING

GLOBALFOUNDRIES INC., Gr...

1. An electrically programmable fuse (e-fuse) comprising:a substrate;
an insulator layer over the substrate;
a pair of contact regions overlying the insulator layer; and
a silicide channel overlying the insulator layer and connecting the pair of contact regions, the silicide channel having a first portion including silicide silicon and a second portion coupled with the first portion and on a common level with the first portion, the second portion including silicide silicon germanium (SiGe) or silicide silicon phosphorous (SiP), wherein the first portion has an upper surface and a lower surface and the second portion has an upper surface and a lower surface, wherein the upper surface of the first portion is coplanar with the upper surface of the second portion and the lower surface of the first portion is coplanar with the lower surface of the second portion;
wherein a first one of the pair of contact regions includes a silicon layer on the common level with the first portion of the silicide channel and the second portion of the silicide channel, and a second one of the pair of contact regions includes a SiGe layer on the common level with the second portion of the silicide channel and the first portion of the silicide channel;
wherein the first portion is formed entirely of the silicide Si and the second portion is formed entirely of the silicide SiGe or the silicide SiP; and
wherein an upper surface of the silicon layer of the first one of the pair of contact regions is coplanar with an upper surface of the SiGe layer of the second one of the pair of contact regions.

US Pat. No. 10,461,028

SEMICONDUCTOR DEVICE INCLUDING A VERTICAL ONE-TIME PROGRAMMABLE FUSE THAT INCLUDES A CONDUCTIVE LAYER AND A RESISTIVE MATERIAL AND A METHOD OF MAKING THE SAME

SEMICONDUCTOR COMPONENTS ...

1. A method of making a semiconductor device, comprising:providing a substrate;
forming a first insulating layer over the substrate;
forming a first opening through the first insulating layer;
forming a first conductive layer along a sidewall of the first opening; and
depositing a resistive material within the first opening over the first conductive layer, wherein:
the resistive material has a resistivity 10 times or greater than the first conductive layer, and
the first conductive layer and resistive material form a vertical one-time-programmable (OTP) fuse with electrically conductive properties associated with the fuse along the sidewall of the first opening.

US Pat. No. 10,461,026

TECHNIQUES TO IMPROVE RELIABILITY IN CU INTERCONNECTS USING CU INTERMETALLICS

International Business Ma...

1. A method of forming a copper (Cu) interconnect in a dielectric over a Cu line, the method comprising the steps of:forming at least one via in the dielectric over the Cu line;
depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic;
annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via;
plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier; and
forming a Cu intermetallic liner on sidewalls of the via, wherein the Cu intermetallic liner is formed on the sidewalls of the via after the Cu intermetallic barrier is formed at the bottom of the via,
wherein the method further comprises the steps of:
depositing a Cu seed layer into and lining the via;
performing another anneal which comprises annealing the metal layer and the Cu seed layer to form the Cu intermetallic liner on the sidewalls of the via; and
plating the Cu into the via over the Cu intermetallic liner.

US Pat. No. 10,461,022

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a first die including a first surface and a second surface opposite to the first surface;
a molding surrounding the first die;
a via extended through the molding;
an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed below the first surface of the first die and the molding, and the conductive member is disposed within the dielectric layer;
a second die disposed over the molding and including a third surface facing the first die, a fourth surface opposite to the third surface and a sidewall between the third surface and the fourth surface;
a connector disposed between the second die and the via and being in contact with the third surface of the second die and the via; and
an underfill surrounding the connector and being in contact with a portion of the second surface of the first die,wherein the second die is electrically connected to the via, and the underfill covers a portion of the sidewall of the second die and exposes entirely the fourth surface of the second die.

US Pat. No. 10,461,020

POSITIONAL RELATIONSHIP AMONG COMPONENTS OF SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. An electronic device, comprising:a mother board;
a plurality of metal pins inserted into the mother board;
a first semiconductor device mounted on the mother board; and
a second semiconductor device mounted on the mother board,
wherein the plurality of metal pins has:
a first metal pin located closest to the first semiconductor device, and
a second metal pin located closest to the second semiconductor device,
wherein a first distance between the first metal pin and the first semiconductor device is smaller than a second distance between the second metal pin and the second semiconductor device,
wherein the first semiconductor device is comprised of:
a die pad including a first surface and a second surface opposite to the first surface,
a semiconductor chip including a main surface, a plurality of bonding electrodes formed on the main surface and a back surface opposite to the main surface, and mounted on the first surface of the die pad via a die bond material such that the back surface faces the first surface of the die pad, the semiconductor chip being essentially comprised a first material having a first linear expansion coefficient,
a plurality of leads electrically connected with the plurality of bonding electrodes via a plurality of wires, respectively, and
a sealing body including an upper surface located on the same side as the main surface of the semiconductor chip, a lower surface opposite to the upper surface, a first side surface located between the upper surface and the lower surface, and a second side surface located between the upper surface and the lower surface and also opposite to the first side surface, and sealing the semiconductor chip and the plurality of wires, the sealing body being essentially comprised of a second material having a second linear expansion coefficient, which is higher than the first linear expansion coefficient,
wherein each of the plurality of leads has:
an inner part sealed with the sealing body, and
an outer part exposed from the sealing body,
wherein the outer part has:
a first part connected to the inner part and extending in a horizontal direction, which is along the upper surface of the sealing body,
a second part connected to the first part via a first bending portion that bends the outer part in a thickness direction, which is from the upper surface toward the lower surface, of the sealing body, and
a third part connected to the second part via a second bending portion that bends the outer part in the horizontal direction,
wherein the plurality of leads has:
a first lead electrically connected with a first bonding electrode of the plurality of bonding electrodes via a first wire of the plurality of wires and protruding from the first side surface of the sealing body, and
a second lead electrically connected with a second bonding electrode of the plurality of bonding electrodes via a second wire of the plurality of wires and protruding from the second side surface of the sealing body,
wherein, in cross-section view, the semiconductor chip is located between the inner part of the first lead and the inner part of the second lead,
wherein, in cross-section view, a first thickness of the semiconductor chip is greater than a second thickness from the second surface of the die pad to the lower surface of the sealing body, which is greater than a third thickness of each of the die pad and the die bond material,
wherein, in cross-section view, a stand-off amount of each of the plurality of leads, which is a distance, in the thickness direction of the sealing body, from the lower surface of the sealing body to the third part of the outer part, is greater than 0.40 mm and less than a fourth thickness from the upper surface of the sealing body to the lower surface of the sealing body, and body, and
wherein, in cross-section view, the stand-off amount of each of the plurality of leads is greater than a fifth thickness from an upper surface of the inner part of each of the plurality of leads, which is located on the same side as the main surface of the semiconductor chip, to the upper surface of the sealing body, or a sixth thickness from a lower surface of the inner part of each of the plurality of leads, which is located on the same side as the second surface of the die pad, to the lower surface of the sealing body.

US Pat. No. 10,461,019

PACKAGE WITH BACKSIDE PROTECTIVE LAYER DURING MOLDING TO PREVENT MOLD FLASHING FAILURE

STMICROELECTRONICS, INC.,...

1. A semiconductor package, comprising:a leadframe, the leadframe including:
a die pad having a thick portion and a thin portion, the thin portion being in a peripheral region of the die pad and extending away from a central region; and
a plurality of leads spaced from and adjacent to the die pad, each lead of the plurality of leads having a thick portion and a thin portion, the thin portion of the lead being in a peripheral region of the lead and extending towards the thin portion of the die pad;
a die coupled to the die pad;
a plurality of wires, each wire having a first end coupled to a respective lead of the plurality of leads and a second end coupled to the die;
a molding compound that encases the die, the plurality of wires, the die pad, and each lead of the plurality of leads, the molding compound being positioned in the space between the die pad and each lead of the plurality of leads, the molding compound having a first width in a location between the thin portion of the die pad and the thin portion of the lead and a second, greater width in a location between the thick portion of the die pad and the thick portion of the lead;
an extension portion of molding compound that is integral with the molding compound, the extension portion including an end extending a first length beyond a first exposed surface of each lead of the plurality of leads and a second exposed surface of the die pad, the extension portion having the second width that is greater than the first width and extending a second, greater length from the thin portions of the plurality of leads and the thin portion of the die pad to the end of the extension portion;
a plurality of first recesses in the molding compound exposing the first exposed surface of each lead of the plurality of leads, each first recess having a first depth equal to the first length; and
a second recess exposing the second exposed surface of the die pad, the second recess having a second depth equal to the first length.

US Pat. No. 10,461,016

CERAMIC MODULE FOR POWER SEMICONDUCTOR INTEGRATED PACKAGING AND PREPARATION METHOD THEREOF

DONGGUAN CHINA ADVANCED C...

1. A ceramic module for power semiconductor integrated packaging, comprising a ceramic substrate and an integrated metal dam layer; a lower surface of the ceramic substrate being provided with a conductive circuit layer, an insulating layer and a heat dissipation layer, the insulating layer completely covering the conductive circuit layer, the heat dissipation layer being located on an area outside the conductive circuit layer and spaced apart from the conductive circuit layer, the heat dissipation layer having a thickness not less than a total thickness of the conductive circuit layer and the insulation layer; an upper surface of the ceramic substrate being provided with a positive electrode pad, a negative electrode pad and a plurality of die bonding regions, the die bonding regions each having a connecting layer and a die bonding layer, the connecting layer and the die bonding layer being spaced apart from each other; the ceramic substrate being provided with vertical via holes, the vertical via holes being electrically connected between the die bonding regions and the conductive circuit layer and between the conductive circuit layer and the positive electrode pad and the negative electrode pad respectively; the integrated metal dam layer being disposed on the upper surface of the ceramic substrate, the integrated metal dam layer surrounding a periphery of a single one or the plurality of die bonding regions and being spaced apart from the die bonding regions, the integrated metal dam layer having a thickness greater than that of the die bonding regions;wherein the integrated metal dam layer is formed with a plurality of cavities each of which extends from a top surface of the integrated metal dam to the upper surface of the ceramic substrate, each of the plurality of cavities defining one of the die bonding regions, the connecting layer and the die bonding layer of the one of the die bonding region being disposed on a part of the upper surface of the ceramic substrate that is located inside the cavity such that each of the connecting layer and the die bonding layer is connected to one of the vertical via holes; and
wherein each one of the die bonding regions is separated from adjacent ones of the die bonding regions by the integrated metal dam and the connecting layer and the die bonding layer of said each one of the die bonding regions are each connected to one of the connecting layer and the die bonding layer of an adjacent one of the die bonding regions by means of the vertical via holes connected thereto and a part of the conductive circuit layer connected between the via holes that are connected to said each one of the die bonding regions and said adjacent one of the die bonding regions so that said each one and said adjacent one of the die bonding regions that are provided on the upper surface of the ceramic substrate are electrically connected to each other by means of the part of the conductive circuit layer provided on the lower surface of the ceramic substrate and the plurality of die bonding regions are connected to each other and are also connected to the positive and negative electrode pads by means of the conductive circuit layer provided on an opposite side of the ceramic substrate.

US Pat. No. 10,461,015

CARBON NANOTUBE-BASED THERMAL INTERFACE MATERIALS AND METHODS OF MAKING AND USING THEREOF

CARBICE CORPORATION, Atl...

1. A method for making contact to a device under test with a thermally conductive and/or electrically conductive, mechanically compliant substrate having an adhesive surface, the method comprising the steps of:attaching the thermally conductive and/or electrically conductive, mechanically compliant substrate directly to a thermal or electrical unit head to cover an area of the thermal or electrical unit head completely or matching a size of the device under test;
engaging the thermal or electrical unit head to the attached thermally conductive and/or electrically conductive, mechanically compliant substrate to the device under test at a pressure of at least 10 psi and at a temperature of less than 150° C.;
holding the thermal or electrical unit head engaged to the attached thermally conductive and/or electrically conductive, mechanically compliant substrate to the device under test under the pressure of at least 10 psi for at least 1 to 300 seconds;
disengaging and re-engaging the thermal or electrical head to the attached thermally conductive and/or electrically conductive, mechanically compliant substrate with the device under test for at least 1,500 cycles of powering up of the device under test; and
measuring or calculating thermal resistance and/or relative thermal resistance of the device under test following cycling.

US Pat. No. 10,461,013

HEAT SINK AND ELECTRONIC COMPONENT DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A heat sink comprising:a flat plate portion;
a first protruding portion which is formed on an outer peripheral portion of the flat plate portion so as to surround a central portion of the flat plate portion and which protrudes in a thickness direction of the flat plate portion, and the first protruding portion is formed into a frame shape in a plan view;
an extending portion which extends outward from the flat plate portion; and
a second protruding portion which is formed on the extending portion such that the first protruding portion is positioned between the second protruding portion and the central portion of the flat plate portion and which protrudes in the thickness direction of the flat plate portion, the second protruding portion is formed on the extending portion such that the second protruding portion discontinuously surrounds the first protruding portion such that the second protruding portion is not opposed to the first protruding portion at four corners of the first protruding portion,
wherein the flat portion, the extending portion, the first protruding portion, and the second protruding portion are integrally formed as a unitary piece.

US Pat. No. 10,461,012

SEMICONDUCTOR MODULE WITH REINFORCING BOARD

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor module comprising:a semiconductor element;
an insulating circuit board having an insulating substrate, a circuit member electrically connected to the semiconductor element and disposed on one principal surface of the insulating substrate, and a first metal member disposed on another principal surface of the insulating substrate arranged at a side opposite to the one principal surface;
a second metal member, a portion of which is at least disposed outside the insulating substrate, continuously and entirely surrounding the insulating substrate with a space therebetween, the second metal member including a bottom portion and side portions extending from the bottom portion in a direction away from the cooler;
a molding resin portion sealing the semiconductor element, the insulating circuit board, and the second metal member such that a bottom portion of the first metal member and the bottom portion of the second metal member are not covered by the molding resin, and the molding resin is interposed between the first metal member and the second metal member and is surrounded by the side portions of the second metal member;
a cooler, wherein the bottom portion of the second metal member faces the cooler;
a first bonding member bonding the cooler and the first metal member; and
a second bonding member bonding the cooler and the second metal member and spaced from the first bonding member without the molding resin between the first bonding member and the second bonding member,
wherein the second metal member is a frame forming an L shaped erected portion that reinforces an outer shape of the molding resin portion.

US Pat. No. 10,461,010

POWER MODULE, POWER SEMICONDUCTOR DEVICE AND POWER MODULE MANUFACTURING METHOD

MITSUBISHI ELECTRIC CORPO...

1. A power module which comprises a power element, a metal base for dissipating heat from the power element, a lead frame electrically connected to electrodes of the power element, and a resin enclosure that encapsulates the power element so that one surface of the metal base and a part of the lead frame are exposed from the enclosure,said resin enclosure comprising:
a body portion in which the power element and a part of the lead frame are placed, and at a bottom surface of which said one surface of the metal base is exposed; and
a rib portion which is placed on the bottom surface of the body portion so as to surround an outer periphery of the metal base, and is formed to protrude from the bottom surface of the body portion in a direction perpendicular to the bottom surface, the rib portion extending lower than said one surface of the metal base;
wherein the rib portion has a depression at its end overhanging from the bottom surface.

US Pat. No. 10,461,003

ELECTRONIC PACKAGE THAT INCLUDES MULTIPLE SUPPORTS

Intel Corporation, Santa...

1. An electronic package comprising:a substrate;
a die attached to the substrate, the die including an upper surface;
an underfill positioned between the die and the substrate;
a first support adjacent to the die and attached to the substrate; and
a second support mounted on the first support, the second support including an upper surface, wherein the second support is closer to the die than the first support, wherein the second support is thicker than the first support, wherein the upper surface of the die is aligned with the upper surface of the second support.

US Pat. No. 10,461,002

FABRICATION METHOD OF ELECTRONIC MODULE

Siliconware Precision Ind...

1. A method for fabricating an electronic module, comprising the steps of:providing a substrate having a plurality of electronic elements and a plurality of separation portions each formed between adjacent two of the electronic elements, wherein each of the electronic elements has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface;
disposing the substrate on a carrier, wherein the active surface of each of the electronic elements is disposed on the carrier;
after disposing the substrate on the carrier, removing each of the separation portions to form at least an opening in each of the separation portions, causing each of the electronic elements to have a side surface connecting the active and inactive surfaces thereof;
forming a strengthening layer in the openings of the separation portions and on the side surfaces of the electronic elements; and
singulating the electronic elements along the opening.

US Pat. No. 10,461,001

METHOD FOR MANUFACTURING HERMETIC SEALING LID MEMBER, AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT HOUSING PACKAGE

HITACHI METALS, LTD., To...

1. A method for manufacturing a hermetic sealing lid member used for an electronic component housing package in which an electronic component is housed, comprising:forming a Ni plated metal plate by forming a Ni plated layer on a surface of a metal plate made of an alloy having a corrosion resistance comprising Fe and 1 mass % or more of Cr; and
forming the hermetic sealing lid member by punching the Ni plated metal plate.

US Pat. No. 10,461,000

SEMICONDUCTOR WAFER AND METHOD OF PROBE TESTING

SEMICONDUCTOR COMPONENTS ...

1. A method of making a semiconductor device, comprising:providing a semiconductor wafer;
providing a wafer holder including a tape portion with an opening through the tape portion;
mounting the semiconductor wafer over the opening in the tape portion of the wafer holder; and
providing an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test.

US Pat. No. 10,460,999

METROLOGY DEVICE AND METROLOGY METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A metrology device, comprising:a light source configured to provide an X-ray;
at least one lens configured to focus the X-ray to a wafer that has a periodic structure, the focused X-ray passing through the wafer and being diffracted by the wafer;
an image sensor configured to detect the diffracted X-ray;
a Fourier's transformer configured to conduct a Fourier's transform of the diffracted X-ray detected by the image sensor; and
a processor configured to identify at least one peak from the Fourier's transform and to analyze the at least one peak to obtain a distance between layers of a transistor structure of the wafer.

US Pat. No. 10,460,998

METHOD FOR INSPECTING SUBSTRATE, SUBSTRATE INSPECTION APPARATUS, EXPOSURE SYSTEM, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Nikon Corporation, Tokyo...

1. A method for inspecting a substrate comprising:irradiating infrared light of a plurality of different wavelengths onto a first surface or a second surface opposite to the first surface, of the substrate in which a pattern having a periodicity and extending from the first surface to an inside of the substrate is formed in the first surface, each of the plurality of different wavelengths of the infrared light having a permeability to permeate the substrate to a respective predetermined depth;
detecting, with respect to each of the wavelengths, a diffracted light diffracted by the pattern of the substrate, or a polarization component of light transmitted through the substrate; and
inspecting the substrate up as far as the predetermined depths based on detection results of the wavelengths regarding the diffracted light diffracted by the pattern of the substrate, or the polarization component of the light transmitted through the substrate,
wherein at least one of an incidence angle of the infrared light with respect to the substrate and an exit angle of the diffracted light or the transmitted light with respect to the substrate is changed in accordance with the plurality of different wavelengths.

US Pat. No. 10,460,992

HIGH FREQUENCY ATTENUATOR

THIN FILM TECHNOLOGY CORP...

1. A passive, high frequency attenuator comprising:a substrate comprising a substrate material having a first side and a second side, the second side being opposite the first;
a first portion coupled to the first side of the substrate, the first portion comprising:
an input contact section;
an output contact section; and
a ground section;
a second portion coupled to the second side of the substrate, the second portion comprising:
a first ground section positioned along a first edge of the second side of the substrate;
a second ground section positioned along a second edge of the second side of the substrate, the second edge being opposite the first edge; and
an attenuation section positioned between the first and second ground sections, the attenuation section comprising:
an input section;
an output section; and
a plurality of resistive sections positioned between the input section, the output section, and the first ground section; and
a plurality of through-holes extending through the substrate and providing electrical communication between the first side of the substrate and the second side of the substrate; and wherein
the input contact section of the first portion is in electrical communication with the input section of the attenuation section of the second portion;
the output contact section of the first portion is in electrical communication with the output section of the attenuation section of the second portion; and
the ground section of the first portion is in electrical communication with the first ground section of the second portion and the second ground section of the second portion.

US Pat. No. 10,460,990

SEMICONDUCTOR VIA STRUCTURE WITH LOWER ELECTRICAL RESISTANCE

INTERNATIONAL BUSINESS MA...

12. A semiconductor device comprising:a first conductive line including a first conductive material;
a second conductive line including a second conductive material;
a via including opposing tapered sidewalls each having a lower end contacting the first conductive material and an upper end contact the second conductive material, a distance between the lower end of the tapered sidewalls being less than a distance between the upper end of tapered sidewalls, the via connecting the first conductive line and the second conductive line, wherein the via includes a via material disposed between the tapered sidewalls such that the via material includes a via material top surface extending between the upper end of the tapered sidewalls and a via material bottom surface, wherein the via material bottom surface has a first contact area extending between the lower end of the tapered sidewalls that is in direct physical contact with the first conductive line, wherein the via material top surface is convex and has a second contact area that is greater than the first contact area;
a first liner material coating inner surfaces of the via side walls; and
a second liner material coating the via material top surface,
wherein the via material top surface directly contacts a bottom surface of the second liner material.

US Pat. No. 10,460,989

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor element;
a semiconductor substrate on which the semiconductor element is mounted, the substrate having a main surface;
a conductive layer formed on the substrate; and
a sealing resin covering the semiconductor element,
wherein the substrate is formed with a recess receding from the main surface, the recess including a bottom surface and first and second sloped surfaces spaced apart from each other in a first direction perpendicular to a thickness direction of the substrate,
the conductive layer includes first conduction paths on the first sloped surface, second conduction paths on the second sloped surface and bottom conduction paths on the bottom surface,
the second sloped surface includes a plurality of regions that are line-symmetrical to the first conduction paths with respect to an imaginary line parallel to a second direction perpendicular to both the thickness direction of the substrate and the first direction, and the plurality of regions are without the second conduction paths,
each of the bottom conduction paths includes a portion extending parallel to the second direction,
said portion extending parallel to the second direction is in physical contact with an intersection between the bottom surface and the first or second sloped surface, and
the semiconductor element is a Hall-effect element.

US Pat. No. 10,460,987

SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor package device, comprising:a semiconductor die; and
a first redistribution layer disposed over and electrically coupled to the semiconductor die, the first redistribution layer comprising:
a first conductive plate;
a second conductive plate disposed over the first conductive plate;
an insulating film between the first conductive plate and the second conductive plate and electrically isolating the first conductive plate from the second conductive plate; and
a first dielectric material being different from the insulating film and laterally surrounding the first conductive plate, the second conductive plate and the insulating film, the first conductive plate and the second conductive plate being configured as an antenna plane and a ground plane, respectively.

US Pat. No. 10,460,986

CAP STRUCTURE

GLOBALFOUNDRIES INC., Gr...

1. A structure, comprising:a gate structure composed of conductive gate material;
sidewall spacers on the gate structure, extending above the conductive gate material;
a first capping material directly on the conductive gate material and comprising a recessed portion between the sidewall spacers on the gate structure; and
a second capping material within the recessed portion of the first capping material and extending over and in direct contact with a top surface of the sidewall spacers on the gate structure.

US Pat. No. 10,460,985

ENHANCEMENT OF ISO-VIA RELIABILITY

INTERNATIONAL BUSINESS MA...

1. A semiconductor structure comprising:a semiconductor base comprising a plurality of semiconductor devices;
a back end of the line wiring layer comprising:
a wiring line;
a cap layer on the wiring line;
a reliability enhancement material within the cap layer and on the wiring line;
an interlayer dielectric (ILD) layer on the cap layer and the reliability enhancement material;
a via extending through the ILD and the reliability enhancement material to communicate with the wiring line; and
a metal filling the via and in contact with the wiring line;
wherein the reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the reliability enhancement material has different physical properties than the cap layer.

US Pat. No. 10,460,981

ARRAY OF GATED DEVICES AND METHODS OF FORMING AN ARRAY OF GATED DEVICES

Micron Technology, Inc., ...

1. An array of gated devices, comprising:rows and columns comprising a plurality of gated devices individually comprising an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region, individual of the inner regions comprising one of a plurality of pillars, the one pillar being spaced from others of the pillars of other inner regions in a horizontal cross section;
a plurality of access lines that individually are laterally proximate the mid regions along individual of the rows;
a plurality of data/sense lines that individually are elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns;
metal circumferentially surrounding, directly against, and electrically coupled to sidewalls of the inner regions of the pillars; the metal being electrically isolated from the data/sense lines; and
the inner regions being electrically coupled to one another elevationally inward of the metal, thereby being electrically coupled to one another by other than, and/or not solely by, the metal that is directly against the sidewalls of the inner regions of the pillars.

US Pat. No. 10,460,980

SEMICONDUCTOR DEVICE COMPRISING A DEEP TRENCH ISOLATION STRUCTURE AND A TRAP RICH ISOLATION STRUCTURE IN A SUBSTRATE AND A METHOD OF MAKING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a metal-oxide semiconductor (MOS) transistor on a substrate;
a deep trench isolation structure in the substrate and around the MOS transistor, wherein the deep trench isolation structure comprises a liner in the substrate and an insulating layer on the liner, wherein the liner comprises silicon oxide and the insulating layer comprises undoped polysilicon or silicon nitride; and
a trap rich isolation structure in the substrate and surrounding the deep trench isolation structure, wherein the deep trench isolation structure and the trap rich isolation structure comprise different materials and a number of layers in the trap rich isolation structure is less than a number of layers in the deep trench isolation structure, wherein the trap rich isolation structure comprises undoped polysilicon and the undoped polysilicon of the trap rich isolation structure is in direct contact with the substrate.

US Pat. No. 10,460,978

BOLTLESS SUBSTRATE SUPPORT ASSEMBLY

LAM RESEARCH CORPORATION,...

1. A substrate support, comprising:a conductive baseplate arranged to support a ceramic layer, the conductive baseplate including a first cavity extending along an axis perpendicular to a horizontal plane defined by the conductive baseplate; and
a coupling assembly arranged within the first cavity, the coupling assembly comprising
a gear arranged within the first cavity and configured to rotate about the axis, and
a pin arranged within the first cavity, the pin extending along the axis through the gear and into a second cavity below the conductive baseplate, wherein rotation of the gear causes the pin to move upward or downward relative to the conductive baseplate, and wherein the pin is retained within the second cavity when the gear is rotated to cause the pin to move downward into the second cavity, and wherein the pin does not extend to an upper surface of the conductive baseplate.

US Pat. No. 10,460,977

LIFT PIN HOLDER WITH SPRING RETENTION FOR SUBSTRATE PROCESSING SYSTEMS

LAM RESEARCH CORPORATION,...

1. A lift pin holder assembly, comprising:a lift pin holder including a central bore extending in a first direction, wherein the central bore defines a first groove arranged transverse to the first direction on a radially inner surface of the central bore,
wherein the lift pin holder is made of ceramic;
a lift pin received in the central bore, extending in the first direction and including a second groove arranged transverse to the first direction on a radially outer surface thereof; and
a spring at least partially arranged in the first groove of the lift pin holder and the second groove of the lift pin to retain the lift pin in the central bore of the lift pin holder.

US Pat. No. 10,460,970

ELECTROSTATIC CHUCK

NGK Insulators, Ltd., Na...

1. An electrostatic chuck comprising:a dielectric layer including an oriented alumina sintered body having a degree of c-plane orientation of 5% or more, the degree of c-plane orientation being determined by a Lotgering method using an X-ray diffraction profile obtained by the irradiation of an X-ray in the 2? range of 20° to 70°;
a ceramic layer integrated with a surface disposed opposite a wafer placement surface of the dielectric layer; and
an electrostatic electrode between the dielectric layer and the ceramic layer,
wherein a proportion by volume of pores having a diameter of 0.2 ?m or more with respect to the volume of the oriented alumina sintered body is 130 ppm or less by volume.

US Pat. No. 10,460,969

BIPOLAR ELECTROSTATIC CHUCK AND METHOD FOR USING THE SAME

Applied Materials, Inc., ...

1. An electrostatic chuck comprising:a chuck body; and
a plurality of independently replaceable electrostatic chuck assemblies mounted in an array across the chuck body to define a substrate support surface suitable for supporting a large area substrate, at least a first electrostatic chuck assembly of the plurality of electrostatic chuck assemblies operable independent of an operation of a second electrostatic chuck assembly of the plurality of electrostatic chuck assemblies, wherein the first electrostatic chuck assembly is laterally spaced apart from the second electrostatic chuck assembly to form a gap therebetween, and wherein the chuck body comprises:
a port aligned with and configured to flow gas into the gap defined between the first and second electrostatic chuck assemblies.

US Pat. No. 10,460,968

ELECTROSTATIC CHUCK WITH VARIABLE PIXELATED MAGNETIC FIELD

Applied Materials, Inc., ...

1. An electrostatic chuck (ESC), comprising:a ceramic plate having a front surface and a back surface, the front surface for supporting a wafer or substrate;
a base coupled to the back surface of the ceramic plate, wherein the base is bonded to the ceramic plate with a perforated bonding layer; and
a plurality of discrete electromagnets disposed in the base, the plurality of discrete electromagnets configured to provide pixelated magnetic field tuning capability for the ESC, wherein individual ones of the plurality of discrete electromagnets are directly exposed to the ceramic plate through holes in the perforated bonding layer and through holes in the base, wherein the holes in the perforated bonding layer are aligned with the holes in the base, wherein the plurality of discrete electromagnets comprises discrete electromagnets arranged in a plurality of concentric circles, and wherein each of the plurality of concentric circles comprises a plurality of the plurality of discrete electromagnets.

US Pat. No. 10,460,967

OVERHEAD TRANSPORT VEHICLE SYSTEM AND TEACHING METHOD FOR OVERHEAD TRANSPORT VEHICLE

MURATA MACHINERY, LTD., ...

1. An overhead transport vehicle system comprising:a plurality of overhead transport vehicles each including:
a winding drum to wind a hoisting material, attached to a lift stage to transfer goods, by lap winding; and
a controller that controls an amount of rotation of the winding drum to control a height of the lift stage;
a storage that stores the amount of rotation of the winding drum corresponding to an overall length of the hoisting material, unique to each of the plurality of overhead transport vehicles; and
a calculator that calculates the amount of rotation of the winding drum, corresponding to a corresponding one of a plurality of transfer heights, for each of the plurality of overhead transport vehicles, from the amount of rotation unique to each of the plurality of overhead transports vehicle stored in the storage.

US Pat. No. 10,460,966

ENCAPSULATED INSTRUMENTED SUBSTRATE APPARATUS FOR ACQUIRING MEASUREMENT PARAMETERS IN HIGH TEMPERATURE PROCESS APPLICATIONS

KLA-Tencor Corporation, ...

1. An apparatus comprising:a substrate assembly including a bottom substrate and a top substrate, wherein the top substrate is mechanically coupled to the bottom substrate;
an electronic assembly;
a nested enclosure assembly including an outer enclosure and an inner enclosure, wherein the outer enclosure encloses the inner enclosure, wherein the inner enclosure encloses at least the electronic assembly;
an insulating medium disposed within a cavity between an outer surface of the inner enclosure and an inner surface of the outer enclosure; and
a sensor assembly communicatively coupled to the electronic assembly, wherein the sensor assembly includes one or more sensors, the one or more sensors disposed within the substrate assembly at one or more locations across the substrate assembly, wherein the one or more sensors are configured to acquire one or more measurement parameters at the one or more locations across the substrate assembly, wherein the electronic assembly is configured to receive the one or more measurement parameters from the one or more sensors, wherein the apparatus is disposed on a rotatable platform.

US Pat. No. 10,460,960

GAS PANEL APPARATUS AND METHOD FOR REDUCING EXHAUST REQUIREMENTS

APPLIED MATERIALS, INC., ...

1. An apparatus for delivering gases, comprising:a gas stick to deliver to at least a portion of the apparatus at least one gas to be delivered by the apparatus;
a purge module including a purge stick and a plurality of diffusers to distribute an inert gas in at least one portion of the apparatus in which a gas to be delivered by the apparatus is present;
at least one pressure sensor to detect leaks in the apparatus; and
a controller, the controller including a processor and a memory coupled to the processor, the memory having stored therein instructions executable by the processor to configure the controller to:
communicate a signal to cause the purge module to distribute the inert gas in the at least one interior portion of the apparatus;
monitor for leaks in the at least one interior portion of the apparatus using signals received from the at least one pressure sensor; and
in response to a detected leak, communicate a signal to cause the purge module to increase the distribution of the inert gas in at least the portion of the apparatus in which the leak was detected.

US Pat. No. 10,460,953

SEMICONDUCTOR MANUFACTURING APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A HIGH-K INSULATING FILM, AND A METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

HITACHI HIGH-TECHNOLOGIES...

1. A method for manufacturing a semiconductor device, the method comprising:placing, in a processing chamber, a semiconductor substrate on which a mask layer having a predetermined pattern shape is formed on a high-k insulating film;
desorbing gas or a foreign matter adsorbed on a surface of the semiconductor substrate;
supplying reactive gas to the processing chamber in a state where a temperature of the semiconductor substrate falls below a predetermined temperature;
stopping the supply of the reactive gas and heating the semiconductor substrate; and
vaporizing an organometallic complex generated by reacting with a metal element included in the high-k insulating film and exhausting the vaporized organometallic complex from the processing chamber,
wherein the reactive gas is mixed gas including complex-forming gas forming the organometallic complex by reacting with the metal element included in the high-k insulating film and complex stabilizing material gas that increases stability of the organometallic complex.

US Pat. No. 10,460,952

STRESS RELIEVING SEMICONDUCTOR LAYER

Sensor Electronic Technol...

1. A structure comprising:a substrate;
a nucleation layer located on the substrate, wherein the nucleation layer is formed of a plurality of nucleation islands; and
a cavity containing layer located over the nucleation layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

US Pat. No. 10,460,949

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND STORAGE MEDIUM

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus for performing a predetermined substrate process on a plurality of target substrates under a vacuum atmosphere, comprising:a plurality of processing parts installed within a single chamber and configured to perform the substrate process on the plurality of target substrates, respectively, each of the plurality of processing parts including a substrate mounting table on which one of the plurality of target substrates is mounted, a showerhead facing the substrate mounting table, and a cylindrical inner wall surrounding the substrate mounting table and the showerhead so as to define a process space located between the substrate mounting table and the showerhead;
a gas supply mechanism positioned outside the single chamber and configured to separately supply a processing gas and a pressure control gas to the plurality of processing parts, the gas supply mechanism including a processing gas supply pipe and a pressure control gas supply pipe which are connected to the showerhead of each of the plurality of processing parts, and each of the processing gas supply pipe and the pressure control gas supply pipe including flow rate controllers and on-off valves;
a single exhaust mechanism configured to collectively exhaust the processing gas and the pressure control gas within the plurality of processing parts, the single exhaust mechanism including an exhaust pipe connecting an exhaust port formed in a bottom portion of the single chamber with a vacuum pump via an automatic pressure control valve; and
a control part as a process controller configured to control the gas supply mechanism and the single exhaust mechanism,
wherein the control part performs a control to:
while the inside of the plurality of processing parts are collectively exhausted by the single exhaust mechanism,
supply the pressure control gas into the plurality of processing parts such that the internal pressure of the plurality of processing parts is stabilized to have the same level of pressure;
when the internal pressure of the plurality of processing parts is stabilized to have the same level of pressure, start supply of the processing gas into the plurality of processing parts, and supply the pressure control gas into the plurality of processing parts at a first flow rate, such that the predetermined substrate process is performed in the plurality of processing parts, the processing gas and the pressure control gas being different from each other; and
when the predetermined substrate process is terminated in at least one of the plurality of processing parts, stop the supply of the processing gas into the at least one of the plurality of processing parts, and supply the pressure control gas into the at least one of the plurality of processing parts at a second flow rate that is different from the first flow rate, while the processing gas continues to be supplied into the remaining of the plurality of processing parts and the pressure control gas continues to be supplied into the remaining of the plurality of processing parts at the first flow rate,
wherein the first flow rate and the second flow rate are non-zero and set such that a difference in internal pressure among the plurality of processing parts is prevented from occurring due to the stop of the supply of the processing gas.

US Pat. No. 10,460,945

MACHINE SUITABLE FOR PLATING A CAVITY OF A SEMI-CONDUCTIVE OR CONDUCTIVE SUBSTRATE SUCH AS A THROUGH VIA STRUCTURE

ALCHIMER, Massy (FR)

1. A machine adapted to metallise a cavity of a semiconductive or conductive substrate, said substrate having a first active face on which said cavity is formed and a rear face opposite to said first face,wherein said machine comprises:
at least one pre-wetting module for pre-wetting the substrate,
at least one insulating dielectric layer depositing module for depositing an insulating dielectric layer,
at least one barrier layer depositing module for depositing a barrier layer to diffusion,
at least one filling module for filling said cavity by electrodeposition of a metal, and
at least one annealing module for annealing the substrate,
wherein each of said at least one pre-wetting modules, each of said at least one insulating dielectric layer depositing modules, each of said at least one barrier layer depositing modules, and each of said at least one filling modules comprises a container having a bottom and a support, each said container containing a liquid bath for immersing the substrate, said support being arranged horizontally at the bottom of each said container to receive said rear face of the substrate such that the active face of said substrate is oriented upwards in the direction opposite the bottom of each of the modules,
such that the machine completes the entire metallisation process of the cavity.

US Pat. No. 10,460,942

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

16. A method for manufacturing a semiconductor structure comprising:forming an active semiconductor fin;
forming a dielectric material around the active semiconductor fin;
forming a protection layer over the active semiconductor fin and the dielectric material;
forming a photoresist layer over the protection layer;
doping the dielectric material with dopants after forming the protection layer;
removing the protection layer after doping the dielectric material;
recessing the doped dielectric material after removing the protection layer, wherein recessing the doped dielectric material comprises:
forming a sacrificial layer on the doped dielectric material after removing the protection layer; and
removing the sacrificial layer; and
tuning a thickness of the doped dielectric material by repeating forming the sacrificial layer and removing the sacrificial layer.

US Pat. No. 10,460,941

PLASMA DOPING USING A SOLID DOPANT SOURCE

Varian Semiconductor Equi...

13. A method of processing a workpiece, comprising:placing a workpiece in a plasma chamber; and
creating a plasma by energizing a working gas in the plasma chamber while the workpiece is disposed in the plasma chamber; and
performing a deposition process, wherein the plasma causes dopant species that coated interior surfaces of the plasma chamber to sputter and deposit on the workpiece, wherein the working gas does not comprise the dopant species and the workpiece is not negatively biased during the deposition process.

US Pat. No. 10,460,939

PATTERNING METHOD

UNITED MICROELECTRONICS C...

1. A patterning method, comprising:forming a second mask layer on a first mask layer;
performing a patterning process to the first mask layer and the second mask layer, wherein the first mask layer is patterned to be a first mask pattern, and the second mask layer is patterned to be a second mask pattern formed on the first mask pattern;
performing a first trim process to the second mask pattern, wherein a width of the second mask pattern is smaller than a width of the first mask pattern after the first trim process;
forming a cover layer covering the first mask pattern and the second mask pattern after the first trim process;
performing an etching process to the first mask pattern after the step of forming the cover layer;
removing a part of the cover layer for exposing the second mask pattern before the etching process;
removing the second mask pattern before the etching process; and
performing a second trim process to the cover layer after the step of removing the second mask pattern and before the etching process.

US Pat. No. 10,460,937

POST GROWTH HETEROEPITAXIAL LAYER SEPARATION FOR DEFECT REDUCTION IN HETEROEPITAXIAL FILMS

International Business Ma...

1. A method for reducing defects in a semiconductor structure, the method comprising:epitaxially growing a first crystalline material over a crystalline substrate, the first crystalline material being substantially planar;
epitaxially growing a second crystalline material over the first crystalline material;
patterning and removing portions of the second crystalline material to form openings extending to a top surface of the first crystalline material without penetrating the first crystalline material;
converting the first crystalline material into a non-crystalline material;
depositing a thermally stable material in the openings, the thermally stable material directly contacting the top surface of the converted substantially planar first crystalline material;
depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure; and
annealing the substantially enclosed semiconductor structure.

US Pat. No. 10,460,930

SELECTIVE GROWTH OF SIO2 ON DIELECTRIC SURFACES IN THE PRESENCE OF COPPER

Lam Research Corporation,...

1. A method of selectively depositing silicon oxide on a dielectric material relative to copper on a substrate, the method comprising:(a) providing the substrate comprising the dielectric material and exposed copper metal surface;
(b) prior to depositing the silicon oxide, exposing the substrate to a copper-blocking reagent to selectively adsorb onto the exposed copper metal surface;
(c) exposing the substrate to a silicon-containing precursor to adsorb the silicon-containing precursor onto the dielectric material;
(d) exposing the substrate to an oxidizing plasma generated in an environment comprising a weak oxidant to convert the adsorbed silicon-containing precursors to silicon oxide; and
(e) exposing the substrate to a reducing agent to reduce the exposed copper metal surface.

US Pat. No. 10,460,926

METHOD AND APPARATUS FOR CHEMICAL MECHANICAL POLISHING PROCESS

Taiwan Semiconductor Manu...

1. A method for processing a semiconductor wafer, comprising:transferring the semiconductor wafer from an interface tool to a chemical mechanical polishing (CMP) tool;
polishing the semiconductor wafer with the CMP tool;
transferring the semiconductor wafer back to the interface tool from the CMP tool; and
converting a mixture into a mist spray and discharging the mist spray over the semiconductor wafer in the interface tool after the semiconductor wafer is polished by the CMP tool.

US Pat. No. 10,460,920

FLEXIBLE ION CONDUIT

Battelle Memorial Institu...

1. An apparatus, comprising:a flexible ion conduit extending between an input end situated to receive ions and an output end to deliver ions and defining an ion passageway, the flexible ion conduit including an inner conduit portion having an inner surface facing the interior ion passageway and having a plurality of RF electrodes situated to receive RF voltages wherein each RF voltage is out of phase with respect to the RF voltage applied to a nearest RF electrode of the RF electrodes to direct the received ions away from the inner surface of the ion passageway.

US Pat. No. 10,460,918

FORMING ION PUMP HAVING SILICON MANIFOLD

COLDQUANTA, INC, Boulder...

1. An ion-pump formation process comprising:forming a silicon manifold by forming a Penning-trap aperture and a flow aperture in a block of monocrystalline silicon, the Penning trap aperture being formed between a first pair of faces of the silicon block, the flow aperture being formed between a second pair of faces of the silicon block;
coating walls of the Penning-trap aperture and the flow aperture with conductive material, the resulting coated wall of the Penning-trap aperture defining a wall anode;
positioning cathodes so that the wall anode is located between the cathodes; and
hermetically sealing a volume including the cathode aperture and the cathodes.

US Pat. No. 10,460,917

MINIATURE ION PUMP

AOSense, Inc., Sunnyvale...

1. A system for ion pumping, comprising:an anode, wherein the anode comprises one or more cylindrical anode chambers, wherein at least one cylindrical anode chamber of the one or more cylindrical anode chambers has a central axis;
a cathode, wherein the cathode surrounds the anode, and wherein the central axis of the at least one cylindrical anode chamber of the one or more anode chambers is orthogonal to a longitudinal axis of a length of the cathode; and
a magnet, wherein the magnet comprises a Halbach magnet that surrounds the cathode, and wherein the longitudinal axis of the length of the cathode is coaxial with a longitudinal axis of a length of the magnet.

US Pat. No. 10,460,916

REAL TIME MONITORING WITH CLOSED LOOP CHUCKING FORCE CONTROL

APPLIED MATERIALS, INC., ...

1. A method for minimizing chucking forces on a workpiece disposed on a electrostatic chuck within a plasma processing chamber, the method comprising:placing a workpiece on an electrostatic chuck in a processing chamber;
striking a plasma within the processing chamber;
monitoring a deflection force on the workpiece;
applying a chucking voltage at a minimum value;
applying a backside gas pressure at a minimum pressure;
adjusting the chucking voltage and or backside gas pressure such that the deflection force is less than a threshold value; and
simultaneously ramping up the chucking voltage and the backside gas pressure.

US Pat. No. 10,460,914

FERRITE CAGE RF ISOLATOR FOR POWER CIRCUITRY

LAM RESEARCH CORPORATION,...

1. Apparatus for providing isolated power to a component of a plasma processing chamber that also is subject to a plurality of RF signals, the plurality of RF signals including at least a first RF signal having a first RF frequency, the apparatus comprising:first and second coils; and
a ferrite cage that surrounds said first and second coils, said ferrite cage comprising:
a first dielectric disc supporting said first coil;
a second dielectric disc supporting said second coil;
first and second pluralities of ferrite pieces disposed on a side of said first dielectric disc facing away from said second dielectric disc;
third and fourth pluralities of ferrite pieces disposed on a side of said second dielectric disc facing away from said first dielectric disc;
the first through fourth pluralities of ferrite pieces being arranged such that the first and second dielectric discs and the first and second coils are inside the first through fourth pluralities of ferrite pieces;
a fifth plurality of ferrite pieces to connect respective ones of the first and second pluralities of ferrite pieces to the third and fourth pluralities of ferrite pieces;
said fifth plurality of ferrite pieces to separate said first and second dielectric discs so that the first and second coils are spaced apart by a predetermined distance; and
said first coil to receive an input voltage signal and said second coil to provide an isolated power signal.

US Pat. No. 10,460,908

MULTI CHARGED PARTICLE BEAM WRITING APPARATUS AND MULTI CHARGED PARTICLE BEAM WRITING METHOD

NuFlare Technology, Inc.,...

1. A multiple charged particle beam writing apparatus comprising:an emission source configured to emit a charged particle beam;
a shaping aperture array substrate configured to form multiple charged particle beams by being irradiated with the charged particle beam;
a combination setting circuitry configured to set, for each of a plurality of design grids being irradiation positions in design of the multiple charged particle beams, a plurality of combinations each composed of three beams whose actual irradiation positions surround a design grid concerned in the plurality of design grids, by using four or more beams whose actual irradiation positions are close to the design grid concerned;
a first distribution coefficient calculation circuitry configured to calculate, for each of the plurality of combinations, a first distribution coefficient for each of the three beams configuring a combination concerned in the plurality of combinations, for distributing a dose to irradiate the design grid concerned to the three beams configuring the combination concerned such that a position of a gravity center of each distributed dose coincides with a position of the design grid concerned and a sum of the each distributed dose coincides with the dose to irradiate the design grid concerned, where at least one the first distribution coefficient is calculated for the each of the four or more beams;
a second distribution coefficient calculation circuitry configured to calculate, for each of the four or more beams, a second distribution coefficient of the each of the four or more beams relating to the design grid concerned by dividing a total value of the at least one the first distribution coefficient corresponding to a beam concerned in the four or more beams by a number of the plurality of combinations; and
a writing mechanism configured to write a pattern on a target object with the multiple charged particle beams in which the dose to irradiate each of the plurality of design grids has been distributed to each corresponding one of the four or more beams.

US Pat. No. 10,460,907

ELECTRON BEAM SURFACE MODIFICATION APPARATUS

Sodick Co., Ltd., Kanaga...

1. An electron beam surface modification apparatus configured to perform a surface modification of a side surface of an irradiation hole being formed on an irradiated object, and the electron beam surface modification apparatus comprising:a vacuum chamber, accommodating the irradiated object;
a cathode electrode, being surrounded by the irradiation hole, and the cathode electrode having:
a base body, facing at least the side surface of the irradiation hole; and
a plurality of metal projections over a region of an outer circumferential surface of the base body; and
a conductive mesh, being arranged at least between the cathode electrode and the side surface of the irradiation hole, the conductive mesh partially contacting the irradiated object and being set to have a same potential as the irradiated object,
wherein the conductive mesh is disposed to face an entire region of the side surface of the irradiation hole.

US Pat. No. 10,460,906

METHOD FOR MONITORING ENVIRONMENTAL STATES OF A MICROSCOPE SAMPLE WITH AN ELECTRON MICROSCOPE SAMPLE HOLDER

PROTOCHIPS, INC., Morris...

1. An electron microscope sample holder comprising:a specimen tip defining a cell; and
a fiber optic sensor assembly comprising a fiber optic cable and a sensor end carried by the fiber optic cable, the sensor end positioned in the specimen tip.

US Pat. No. 10,460,904

IMAGING DEVICE FOR IMAGING AN OBJECT AND FOR IMAGING A STRUCTURAL UNIT IN A PARTICLE BEAM APPARATUS

Carl Zeiss Microscopy Gmb...

1. A particle beam apparatus for analyzing and/or processing an object, having:at least one beam generator for generating a particle beam comprising charged primary particles;
at least one objective lens for focusing the particle beam onto the object, wherein interaction particles and/or interaction radiation arise/arises during an interaction of the particle beam with the object;
at least one detector for detecting the interaction particles and/or interaction radiation, wherein the at least one detector is sensitive to light of a first spectral range and is non-sensitive to light in a second spectral range; and
at least one imaging device for imaging the object and/or for imaging a structural unit of the particle beam apparatus, the at least one imaging device having:
at least one illumination unit with a first switching state and a second switching state for illuminating the object and/or for illuminating the structural unit with illumination light, wherein, in the first switching state, the illumination light includes only light of the first spectral range and wherein, in the second switching state, the illumination light includes only light of the second spectral range,
at least one control unit for switching the illumination unit into the first switching state or into the second switching state, wherein the control unit operates the illumination unit of the imaging device in the first switching state and switches the illumination unit into the second switching state only if the at least one detector is: (i) in operation, and (ii) in a position in which the at least one detector detects light of the first spectral range in the first switching state, and
at least one camera unit for imaging the object and/or for imaging the structural unit with light of the first spectral range in the first switching state of the illumination unit or with light of the second spectral range in the second switching state of the illumination unit.

US Pat. No. 10,460,903

METHOD AND SYSTEM FOR CHARGE CONTROL FOR IMAGING FLOATING METAL STRUCTURES ON NON-CONDUCTING SUBSTRATES

KLA-Tencor Corporation, ...

1. A scanning electron microscopy apparatus comprising:a sample stage configured to secure a sample;
an electron-optical column comprising:
an electron source configured to generate a primary electron beam; and
a set of electron-optical elements configured to direct at least a portion of the primary electron beam onto one or more electrically floating metal structures disposed above insulating material of the sample;
a detector assembly configured to detect electrons emanating from a surface of the sample; and
a controller communicatively coupled to the detector assembly, the controller including one or more processors configured to execute program instructions maintained in memory, the program instructions configured to cause the one or more processors to:
direct the electron-optical column to perform, with the primary electron beam, an alternating series of image scans and flood scans of the one or more electrically floating metal structures disposed above the insulating material of the sample, wherein the image scans are performed over a first range of landing energies and the flood scans are performed at an additional landing energy lower than the first range of landing energies of the image scans, wherein the flood scans negatively charge a surface of the one or more electrically floating metal structures via absorption of electrons of the flood scans via the surface of the one or more electrically floating metal structures, wherein the image scans positively charge the surface of the one or more electrically floating metal structures via emission of electrons of the image scans, wherein the flood scans are configured to establish a dynamic equilibrium in surface charge on the one or more electrically floating metal structures such that a charging effect in a flooding state counter-balances a charging effect in a imaging state.

US Pat. No. 10,460,902

CHARGED PARTICLE BEAM WRITING APPARATUS AND METHOD FOR DIAGNOSING FAILURE OF BLANKING CIRCUIT

NuFlare Technology, Inc.,...

1. A charged particle beam writing apparatus comprising:an emitter emitting a charged particle beam;
a blanking deflector performing blanking control of the charged particle beam by deflecting the beam in accordance with an applied blanking voltage;
a blanking circuit applying the blanking voltage to the blanking deflector;
a stage on which a substrate irradiated with the charged particle beam is placed;
a mark on the stage;
a detector detecting an irradiation position of the charged particle beam based on irradiation of the mark with the charged particle beam; and
a diagnostic electric circuitry that causes the charged particle beam to enter a predetermined defocused state relative to the mark, obtains a difference between a first irradiation position detected by the detector when the mark is scanned with the charged particle beam under first irradiation conditions and a second irradiation position detected by the detector when the mark is scanned with the charged particle beam under second irradiation conditions in which at least either of irradiation time and settling time in the first irradiation conditions is varied, and determines occurrence of a failure of the blanking circuit when the difference is a predetermined value or more.

US Pat. No. 10,460,899

MODIFICATION ARRANGEMENT FOR AN X-RAY GENERATING DEVICE

KONINKLIJKE PHILIPS N.V.,...

1. A modification arrangement for an X-ray device, comprisinga cathode configured to provide an electron beam;
an anode configured to rotate under impact of the electron beam, the anode being segmented by slits arranged around a circumference of the anode;
a modification device configured to modify the electron beam when the electron beam is hitting one of the slits of the anode,
wherein the modification device is configured to deflect the electron beam tangentially forward in or backward against a direction of a rotational movement of the anode, and then backward against or forward in the direction of the rotational movement of the anode to reduce time during which the electron beam hits one of the slits.

US Pat. No. 10,460,898

CIRCUIT BREAKERS

LSIS CO., LTD., Anyang-s...

1. A circuit breaker comprising a single pole breaking unit with a pressure trip device that rotates a trip bar through an arc gas and an opening/closing mechanism unit adjusted to be in a trip state as the trip bar rotates through the pressure trip device,wherein the pressure trip device comprises:
a first case connected to the single pole breaking unit and having an arc gas discharge hole;
a barrier positioned in the front of the arc gas discharge hole and bent through an arc gas discharged through the arc gas discharge hole;
a shooter seated on the first case and configured to drive the trip bar while moving through the arc gas discharged through the arc gas discharge hole; and
a second case connected to cover the first case,
wherein the shooter comprises:
an arc gas action portion disposed above the arc gas discharge hole; and
a shooter portion configured to rotate the trip bar while moving up and down in connection to a side surface of the arc gas action portion, and
wherein the shooter portion defines a vertical line, and the arc gas discharge hole is not positioned on the vertical line defined by the shooter portion.

US Pat. No. 10,460,896

RELAY CONTROL DEVICE

AutoNetworks Technologies...

1. A relay control device that controls switching between a conductive state and a cut-off state of an electromagnetic relay by energizing a coil, comprising:a voltage-drop DC/DC converter unit for dropping a voltage supplied from a power supply and outputting the dropped voltage to the coil;
a control unit for outputting a control signal for modulating a pulse frequency to control an operation of the voltage-drop DC/DC converter unit;
a filter unit for allowing passage of the control signal output by the control unit that has a predetermined frequency; and
a circuit unit for controlling the operation of the voltage-drop DC/DC converter unit in accordance with a signal output by the filter unit, the circuit unit being provided between the filter unit and the voltage-drop DC/DC converter unit,
wherein, if the filter unit does not allow passage of the control signal, the circuit unit performs control so that the voltage-drop DC/DC converter unit outputs the voltage supplied from the power supply without dropping the voltage, and cuts off a current path from the power supply to a ground potential within the circuit.

US Pat. No. 10,460,893

EMBEDDED POLE PART FOR MEDIUM OR HIGH VOLTAGE USE, WITH A VACUUM INTERRUPTER WHICH IS EMBEDDED INTO AN INSULATING RESIN

ABB SCHWEIZ AG, Baden (C...

1. An embedded pole part for medium or high voltage use, the part comprising:a vacuum interrupter which is embedded into an insulating resin;
a current and/or voltage sensor including a sensor housing, integrated inside the insulating resin, arranged rotationally symmetrically around a conductor of the pole part, the sensor housing having an outer circumference;
a metal grid, implemented into the insulating resin and around the outer circumference of the sensor housing.

US Pat. No. 10,460,890

MULTI-POLE DOME SWITCH

1. A multi-pole dome switch configured to be positioned on a printed circuit board having a first circuit and a second circuit, the multi-pole dome switch comprising:a conductive dome configured to make conductive contact with a first trace and a second trace of the first circuit when depressed, the conductive dome comprises a centrally located opening that extends therethrough;
a conductive insert, the conductive insert comprises a downwardly extending feature having a contact portion, the downwardly extending feature of the conductive insert is configured to extend through the centrally located opening of the conductive dome and position the contact portion thereof to conductively connect a first trace and a second trace of the second circuit when the conductive dome is depressed; and
an insulator positioned between the conductive dome and the conductive insert, the insulator is configured to prevent contact between the conductive dome and the conductive insert.

US Pat. No. 10,460,884

SWITCHING ARRANGEMENT FOR A CONTROL TRANSFORMER, IN PARTICULAR POLARITY SWITCHING MEANS

MASCHINENFABRIK REINHAUSE...

1. A polarity switch for a control transformer comprising a first winding for a phase to be regulated, of an alternating current mains, the polarity switch comprising:a first connection terminal connectable with the winding;
a second connection terminal connectable with a diverter;
a vacuum interrupter having a fixed contact and a movable contact;
an isolator having a stationary switching-on contact and an electrically conductive movable bearing housing selectably engageable with and disengageable from the switching-on contact;
a resistor connected in a series circuit with the vacuum interrupter and the isolator, the first connection terminal being connected with the second connection terminal by the series circuit;
a rotatable polarity rotor carrying the bearing housing and rotatable to actuate the isolator and the vacuum interrupter, the polarity rotor having a lower support plate carrying the fixed contact and an upper support plate mechanically connected to the movable contact, the vacuum interrupter being mounted vertically between the plates; and
a vertical drive shaft between the support plates for rotating the polarity rotor.

US Pat. No. 10,460,881

FLEXIBLE AND CONDUCTIVE WASTE TIRE-DERIVED CARBON/POLYMER COMPOSITE PAPER AS PSEUDOCAPACITIVE ELECTRODE

UT-Battelle, LLC, Oak Ri...

1. An electrode comprising a tire-derived carbon composite comprising carbon black embedded in sulfonated rubber-derived carbon matrix comprising graphitized interface portions and being activated, and coated with a redox-active polymer to provide a redox-active polymer coated, activated tire-derived carbon composite.

US Pat. No. 10,460,877

THIN-FILM CAPACITOR INCLUDING GROOVE PORTIONS

TDK CORPORATION, Tokyo (...

1. A thin-film capacitor comprising:a laminate having a laminated structure including a first electrode layer and a second electrode layer laminated between one end surface side of the laminate and another end surface side of the laminate along a lamination direction, and a dielectric layer interposed between the first electrode layer and the second electrode layer in the lamination direction;
a first groove portion and a second groove portion provided on the one end surface side of the laminate and each extending in the laminating direction, the first groove portion and the second groove portion each having a width in a separation direction that is perpendicular to the lamination direction and that is along a direction in which the first groove portion and the second groove portion are separated from each other, each of the width of the first groove portion and the width of the second groove portion being narrowed from the one end surface side to the other end surface side of the laminate; and
a pair of extraction electrodes configured to cross the first groove portion and the second groove portion, respectively, and provided along two side surfaces of each of the first groove portion and second groove portion, the two side surfaces of the first groove portion facing each other in the separation direction, the two side surfaces of the second groove portion facing each other in the separation direction, each of the first electrode layer and the second electrode layer extending over both sides of the first groove portion and both sides of the second groove portion and having portions exposed on both side surfaces of the first groove portion and on both side surfaces of the second groove portion,
wherein a first extraction electrode provided in the first groove portion among the pair of extraction electrodes is in contact with the first electrode layer exposed on the side surface of the first groove portion and is not in contact with the second electrode layer, and
wherein a second extraction electrode provided in the second groove portion among the pair of extraction electrodes is in contact with the second electrode layer exposed on the side surface of the second groove portion and is not in contact with the first electrode layer.

US Pat. No. 10,460,876

MULTI-LAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multi-layer ceramic capacitor, comprising:a body including
a multi-layer unit including
ceramic layers laminated in a first direction,
a first internal electrode and a second internal electrode that are alternately disposed between the ceramic layers,
an end surface that is oriented in a second direction orthogonal to the first direction, the first internal electrode being drawn from the end surface,
an end margin that is disposed between the end surface and the second internal electrode, and
a side surface that is oriented in a third direction orthogonal to the first direction and the second direction, the first internal electrode and the second internal electrode being exposed to the side surface, and
a side margin that covers the side surface of the multi-layer unit; and
an external electrode that includes an entry portion and covers the body from a side of the end surface,
the entry portion being disposed on the end margin,
the entry portion entering a gap, between the side surface and the side margin, from the end surface,
the entry portion projecting outward from the side surface towards the side margin,
the entry portion being in direct physical contact with the side surface, and
the side surface being absent in the side margin.

US Pat. No. 10,460,875

MULTILAYER ELECTRONIC COMPONENT AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer electronic component comprising: a capacitor body including a plurality of dielectric layers and a plurality of first and second internal electrodes alternately disposed with dielectric layers interposed therebetween having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first, second, third, and fourth surfaces, and opposing each other, wherein one end of each of the first and second internal electrodes is exposed through the third and fourth surfaces, respectively; first and second external electrodes including, respectively, first and second connected portions respectively disposed on the third and fourth surfaces of the capacitor body and first and second band portions respectively extended from the first and second connected portions to portions of the first surface of the capacitor body; a first connection terminal disposed on the first band portion to be spaced apart from the first connected portion so that a first space portion, open in directions corresponding to the third surface, the fifth surface, and the sixth surface of the capacitor body is provided on a lower surface of the first band portion; and a second connection terminal disposed on the second band portion to be spaced apart from the second connected portion so that a second space portion, open in directions corresponding to the fourth surface, the fifth surface, and the sixth surface of the capacitor body is provided on a lower surface of the second band portion, wherein BW/4?G?3BW/4 in which BW is a width of the first or second band portion of the first or second external electrode, and G is a length of the first or second space portion.

US Pat. No. 10,460,874

ELECTRONIC COMPONENT WITH METAL TERMINALS

TAIYO YUDEN CO., LTD., T...

1. An electronic component with metal terminals, constituted by an electronic component on which metal terminals are provided, wherein:the electronic component has a component body of roughly rectangular solid shape that contains internal conductors, and external electrodes provided on opposing ends of the component body, respectively;
each of the metal terminals has a first planar part and a second planar part oriented differently from the first planar part;
the first planar part of the metal terminal is connected to one of the external electrodes via a conductive bonding material provided in between in a manner facing one face of the component body; and
the second planar part of the metal terminal is positioned in a manner facing at least partially, across a clearance in closest proximity, another face adjoining the one face of the component body, while being fixed to the component body by an adhesive provided in the clearance,
wherein the metal terminal is provided only on the one face and the another face of the component body, among all of the faces of the component body, and
the adhesive and the conductive bonding material are constituted by different materials, and a thickness of the adhesive is greater than a thickness of the conductive bonding material.

US Pat. No. 10,460,873

ENHANCING DIELECTRIC CONSTANTS OF ELASTOMER SHEETS

Facebook Technologies, LL...

1. A method comprising:receiving an uncured elastomer;
depositing dielectric ceramic particulates having a value of a dielectric constant satisfying one or more conditions onto the uncured elastomer;
receiving an additional uncured elastomer;
layering the additional uncured elastomer onto the dielectric ceramic particulates deposited onto the uncured elastomer;
depositing additional dielectric ceramic particulates having an additional value of an additional dielectric constant satisfying the one or more conditions;
curing the uncured elastomer and the additional uncured elastomer for an interval of time and at a specified temperature within a mold having an anode and a cathode; and
for at least a portion of the interval of time during the curing while a temperature within the mold is within a threshold amount of a Curie temperature of the dielectric ceramic particulates or of the additional dielectric ceramic particulates, applying an electric field by applying a voltage to the anode and to the cathode of the mold including the uncured elastomer and the additional uncured elastomer such that a cured elastomer and the uncured elastomer have different dielectric constants.

US Pat. No. 10,460,871

METHOD FOR FABRICATING NON-PLANAR MAGNET

GM GLOBAL TECHNOLOGY OPER...

1. A method for fabricating a non-planar magnet, comprising:extruding a precursor material including neodymium iron boron crystalline grains into an original anisotropic neodymium iron boron permanent magnet having an original shape, wherein the original anisotropic neodymium iron boron permanent magnet has at least 90 percent neodymium iron boron magnetic material by volume;
heating the original anisotropic neodymium iron boron permanent magnet to a deformation temperature; and
deforming the original anisotropic neodymium iron boron permanent magnet into a reshaped anisotropic neodymium iron boron permanent magnet having a second shape substantially different from the original shape using heated tooling to apply a deformation load to the original anisotropic neodymium iron boron permanent magnet, wherein the original anisotropic neodymium iron boron permanent magnet and the reshaped anisotropic neodymium iron boron permanent magnet each have respective magnetic moments substantially aligned with a respective local surface normal corresponding to the respective magnetic moment.

US Pat. No. 10,460,870

INDUCTION COIL ASSEMBLY AND WIRELESS POWER TRANSFER SYSTEM

NINGBO WEIE ELECTRONICS T...

1. An induction coil assembly, comprising:at least one substrate, each including at least one through hole;
a first part of a wire of the induction coil assembly wound on a first surface of the substrate; and
a second part of the wire extended onto a second surface of the substrate via one of the through holes of the substrate and wound on the second surface of the substrate
wherein the wire forms an N-turn coil, locations of the windings on the first surface of the substrate and locations of the windings on the second surface of the substrate are mutually staggered with each other up and down.

US Pat. No. 10,460,868

IGNITION COIL FOR INTERNAL COMBUSTION ENGINE

DENSO CORPORATION, Kariy...

1. An ignition coil for an internal combustion engine comprising:a primary coil;
a secondary coil disposed concentrically around the outer periphery of the primary coil;
a center core disposed on the inner periphery of the primary coil;
an outer peripheral core surrounding the secondary coil, the outer peripheral core including a central opening;
a core cover including an inside cover part facing an inner surface of the outer peripheral core, a first end-side cover part facing a surface on one end of the outer peripheral core in a penetration direction, and a second end-side cover part facing a surface of the other end of the outer peripheral core in the penetration direction, the first end-side cover part and the second end-side cover part being connected by the inside cover part, the first end-side cover part of the core cover only including a wall portion that is on a high voltage side of the secondary coil such that the core cover does not include another wall portion elsewhere and that protrudes in the penetration direction, the core cover having a plurality of steps formed on at least one of an inner surface of the wall portion, an outer surface of the wall portion, and a surface on one end of the wall portion in the penetration direction of the core cover;
a case provided with an accommodation opening on a side on which the surface on the one end of the outer peripheral core in the penetration direction is located, the accommodation opening accommodating the primary coil, the secondary coil, the center core, the outer peripheral core, and the core cover; and
a filling resin filling gaps in the case, the filling resin being in contact with the steps.